4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 const uint8_t parity_table
[256] = {
25 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
26 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
27 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
28 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
29 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
30 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
31 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
32 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
33 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
34 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
35 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
36 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
37 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
38 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
39 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
40 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
41 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
42 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
43 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
44 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
45 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
46 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
47 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
48 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
49 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
50 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
51 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
52 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
53 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
54 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
55 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
56 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
60 const uint8_t rclw_table
[32] = {
61 0, 1, 2, 3, 4, 5, 6, 7,
62 8, 9,10,11,12,13,14,15,
63 16, 0, 1, 2, 3, 4, 5, 6,
64 7, 8, 9,10,11,12,13,14,
68 const uint8_t rclb_table
[32] = {
69 0, 1, 2, 3, 4, 5, 6, 7,
70 8, 0, 1, 2, 3, 4, 5, 6,
71 7, 8, 0, 1, 2, 3, 4, 5,
72 6, 7, 8, 0, 1, 2, 3, 4,
75 const CPU86_LDouble f15rk
[7] =
77 0.00000000000000000000L,
78 1.00000000000000000000L,
79 3.14159265358979323851L, /*pi*/
80 0.30102999566398119523L, /*lg2*/
81 0.69314718055994530943L, /*ln2*/
82 1.44269504088896340739L, /*l2e*/
83 3.32192809488736234781L, /*l2t*/
88 spinlock_t global_cpu_lock
= SPIN_LOCK_UNLOCKED
;
92 spin_lock(&global_cpu_lock
);
97 spin_unlock(&global_cpu_lock
);
100 void cpu_loop_exit(void)
102 /* NOTE: the register at this point must be saved by hand because
103 longjmp restore them */
105 env
->regs
[R_EAX
] = EAX
;
108 env
->regs
[R_ECX
] = ECX
;
111 env
->regs
[R_EDX
] = EDX
;
114 env
->regs
[R_EBX
] = EBX
;
117 env
->regs
[R_ESP
] = ESP
;
120 env
->regs
[R_EBP
] = EBP
;
123 env
->regs
[R_ESI
] = ESI
;
126 env
->regs
[R_EDI
] = EDI
;
128 longjmp(env
->jmp_env
, 1);
131 /* return non zero if error */
132 static inline int load_segment(uint32_t *e1_ptr
, uint32_t *e2_ptr
,
143 index
= selector
& ~7;
144 if ((index
+ 7) > dt
->limit
)
146 ptr
= dt
->base
+ index
;
147 *e1_ptr
= ldl_kernel(ptr
);
148 *e2_ptr
= ldl_kernel(ptr
+ 4);
152 static inline unsigned int get_seg_limit(uint32_t e1
, uint32_t e2
)
155 limit
= (e1
& 0xffff) | (e2
& 0x000f0000);
156 if (e2
& DESC_G_MASK
)
157 limit
= (limit
<< 12) | 0xfff;
161 static inline uint8_t *get_seg_base(uint32_t e1
, uint32_t e2
)
163 return (uint8_t *)((e1
>> 16) | ((e2
& 0xff) << 16) | (e2
& 0xff000000));
166 static inline void load_seg_cache_raw_dt(SegmentCache
*sc
, uint32_t e1
, uint32_t e2
)
168 sc
->base
= get_seg_base(e1
, e2
);
169 sc
->limit
= get_seg_limit(e1
, e2
);
173 /* init the segment cache in vm86 mode. */
174 static inline void load_seg_vm(int seg
, int selector
)
177 cpu_x86_load_seg_cache(env
, seg
, selector
,
178 (uint8_t *)(selector
<< 4), 0xffff, 0);
181 static inline void get_ss_esp_from_tss(uint32_t *ss_ptr
,
182 uint32_t *esp_ptr
, int dpl
)
184 int type
, index
, shift
;
189 printf("TR: base=%p limit=%x\n", env
->tr
.base
, env
->tr
.limit
);
190 for(i
=0;i
<env
->tr
.limit
;i
++) {
191 printf("%02x ", env
->tr
.base
[i
]);
192 if ((i
& 7) == 7) printf("\n");
198 if (!(env
->tr
.flags
& DESC_P_MASK
))
199 cpu_abort(env
, "invalid tss");
200 type
= (env
->tr
.flags
>> DESC_TYPE_SHIFT
) & 0xf;
202 cpu_abort(env
, "invalid tss type");
204 index
= (dpl
* 4 + 2) << shift
;
205 if (index
+ (4 << shift
) - 1 > env
->tr
.limit
)
206 raise_exception_err(EXCP0A_TSS
, env
->tr
.selector
& 0xfffc);
208 *esp_ptr
= lduw_kernel(env
->tr
.base
+ index
);
209 *ss_ptr
= lduw_kernel(env
->tr
.base
+ index
+ 2);
211 *esp_ptr
= ldl_kernel(env
->tr
.base
+ index
);
212 *ss_ptr
= lduw_kernel(env
->tr
.base
+ index
+ 4);
216 /* XXX: merge with load_seg() */
217 static void tss_load_seg(int seg_reg
, int selector
)
222 if ((selector
& 0xfffc) != 0) {
223 if (load_segment(&e1
, &e2
, selector
) != 0)
224 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
225 if (!(e2
& DESC_S_MASK
))
226 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
228 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
229 cpl
= env
->hflags
& HF_CPL_MASK
;
230 if (seg_reg
== R_CS
) {
231 if (!(e2
& DESC_CS_MASK
))
232 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
234 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
235 if ((e2
& DESC_C_MASK
) && dpl
> rpl
)
236 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
238 } else if (seg_reg
== R_SS
) {
239 /* SS must be writable data */
240 if ((e2
& DESC_CS_MASK
) || !(e2
& DESC_W_MASK
))
241 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
242 if (dpl
!= cpl
|| dpl
!= rpl
)
243 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
245 /* not readable code */
246 if ((e2
& DESC_CS_MASK
) && !(e2
& DESC_R_MASK
))
247 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
248 /* if data or non conforming code, checks the rights */
249 if (((e2
>> DESC_TYPE_SHIFT
) & 0xf) < 12) {
250 if (dpl
< cpl
|| dpl
< rpl
)
251 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
254 if (!(e2
& DESC_P_MASK
))
255 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
256 cpu_x86_load_seg_cache(env
, seg_reg
, selector
,
257 get_seg_base(e1
, e2
),
258 get_seg_limit(e1
, e2
),
261 if (seg_reg
== R_SS
|| seg_reg
== R_CS
)
262 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
266 #define SWITCH_TSS_JMP 0
267 #define SWITCH_TSS_IRET 1
268 #define SWITCH_TSS_CALL 2
270 /* XXX: restore CPU state in registers (PowerPC case) */
271 static void switch_tss(int tss_selector
,
272 uint32_t e1
, uint32_t e2
, int source
)
274 int tss_limit
, tss_limit_max
, type
, old_tss_limit_max
, old_type
, v1
, v2
, i
;
276 uint32_t new_regs
[8], new_segs
[6];
277 uint32_t new_eflags
, new_eip
, new_cr3
, new_ldt
, new_trap
;
278 uint32_t old_eflags
, eflags_mask
;
283 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
286 fprintf(logfile
, "switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector
, type
, source
);
289 /* if task gate, we read the TSS segment and we load it */
291 if (!(e2
& DESC_P_MASK
))
292 raise_exception_err(EXCP0B_NOSEG
, tss_selector
& 0xfffc);
293 tss_selector
= e1
>> 16;
294 if (tss_selector
& 4)
295 raise_exception_err(EXCP0A_TSS
, tss_selector
& 0xfffc);
296 if (load_segment(&e1
, &e2
, tss_selector
) != 0)
297 raise_exception_err(EXCP0D_GPF
, tss_selector
& 0xfffc);
298 if (e2
& DESC_S_MASK
)
299 raise_exception_err(EXCP0D_GPF
, tss_selector
& 0xfffc);
300 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
302 raise_exception_err(EXCP0D_GPF
, tss_selector
& 0xfffc);
305 if (!(e2
& DESC_P_MASK
))
306 raise_exception_err(EXCP0B_NOSEG
, tss_selector
& 0xfffc);
312 tss_limit
= get_seg_limit(e1
, e2
);
313 tss_base
= get_seg_base(e1
, e2
);
314 if ((tss_selector
& 4) != 0 ||
315 tss_limit
< tss_limit_max
)
316 raise_exception_err(EXCP0A_TSS
, tss_selector
& 0xfffc);
317 old_type
= (env
->tr
.flags
>> DESC_TYPE_SHIFT
) & 0xf;
319 old_tss_limit_max
= 103;
321 old_tss_limit_max
= 43;
323 /* read all the registers from the new TSS */
326 new_cr3
= ldl_kernel(tss_base
+ 0x1c);
327 new_eip
= ldl_kernel(tss_base
+ 0x20);
328 new_eflags
= ldl_kernel(tss_base
+ 0x24);
329 for(i
= 0; i
< 8; i
++)
330 new_regs
[i
] = ldl_kernel(tss_base
+ (0x28 + i
* 4));
331 for(i
= 0; i
< 6; i
++)
332 new_segs
[i
] = lduw_kernel(tss_base
+ (0x48 + i
* 4));
333 new_ldt
= lduw_kernel(tss_base
+ 0x60);
334 new_trap
= ldl_kernel(tss_base
+ 0x64);
338 new_eip
= lduw_kernel(tss_base
+ 0x0e);
339 new_eflags
= lduw_kernel(tss_base
+ 0x10);
340 for(i
= 0; i
< 8; i
++)
341 new_regs
[i
] = lduw_kernel(tss_base
+ (0x12 + i
* 2)) | 0xffff0000;
342 for(i
= 0; i
< 4; i
++)
343 new_segs
[i
] = lduw_kernel(tss_base
+ (0x22 + i
* 4));
344 new_ldt
= lduw_kernel(tss_base
+ 0x2a);
350 /* NOTE: we must avoid memory exceptions during the task switch,
351 so we make dummy accesses before */
352 /* XXX: it can still fail in some cases, so a bigger hack is
353 necessary to valid the TLB after having done the accesses */
355 v1
= ldub_kernel(env
->tr
.base
);
356 v2
= ldub(env
->tr
.base
+ old_tss_limit_max
);
357 stb_kernel(env
->tr
.base
, v1
);
358 stb_kernel(env
->tr
.base
+ old_tss_limit_max
, v2
);
360 /* clear busy bit (it is restartable) */
361 if (source
== SWITCH_TSS_JMP
|| source
== SWITCH_TSS_IRET
) {
364 ptr
= env
->gdt
.base
+ (env
->tr
.selector
<< 3);
365 e2
= ldl_kernel(ptr
+ 4);
366 e2
&= ~DESC_TSS_BUSY_MASK
;
367 stl_kernel(ptr
+ 4, e2
);
369 old_eflags
= compute_eflags();
370 if (source
== SWITCH_TSS_IRET
)
371 old_eflags
&= ~NT_MASK
;
373 /* save the current state in the old TSS */
376 stl_kernel(env
->tr
.base
+ 0x20, env
->eip
);
377 stl_kernel(env
->tr
.base
+ 0x24, old_eflags
);
378 for(i
= 0; i
< 8; i
++)
379 stl_kernel(env
->tr
.base
+ (0x28 + i
* 4), env
->regs
[i
]);
380 for(i
= 0; i
< 6; i
++)
381 stw_kernel(env
->tr
.base
+ (0x48 + i
* 4), env
->segs
[i
].selector
);
384 stw_kernel(env
->tr
.base
+ 0x0e, new_eip
);
385 stw_kernel(env
->tr
.base
+ 0x10, old_eflags
);
386 for(i
= 0; i
< 8; i
++)
387 stw_kernel(env
->tr
.base
+ (0x12 + i
* 2), env
->regs
[i
]);
388 for(i
= 0; i
< 4; i
++)
389 stw_kernel(env
->tr
.base
+ (0x22 + i
* 4), env
->segs
[i
].selector
);
392 /* now if an exception occurs, it will occurs in the next task
395 if (source
== SWITCH_TSS_CALL
) {
396 stw_kernel(tss_base
, env
->tr
.selector
);
397 new_eflags
|= NT_MASK
;
401 if (source
== SWITCH_TSS_JMP
|| source
== SWITCH_TSS_CALL
) {
404 ptr
= env
->gdt
.base
+ (tss_selector
<< 3);
405 e2
= ldl_kernel(ptr
+ 4);
406 e2
|= DESC_TSS_BUSY_MASK
;
407 stl_kernel(ptr
+ 4, e2
);
410 /* set the new CPU state */
411 /* from this point, any exception which occurs can give problems */
412 env
->cr
[0] |= CR0_TS_MASK
;
413 env
->tr
.selector
= tss_selector
;
414 env
->tr
.base
= tss_base
;
415 env
->tr
.limit
= tss_limit
;
416 env
->tr
.flags
= e2
& ~DESC_TSS_BUSY_MASK
;
418 if ((type
& 8) && (env
->cr
[0] & CR0_PG_MASK
)) {
419 env
->cr
[3] = new_cr3
;
420 cpu_x86_update_cr3(env
);
423 /* load all registers without an exception, then reload them with
424 possible exception */
426 eflags_mask
= TF_MASK
| AC_MASK
| ID_MASK
|
427 IF_MASK
| IOPL_MASK
| VM_MASK
| RF_MASK
;
429 eflags_mask
&= 0xffff;
430 load_eflags(new_eflags
, eflags_mask
);
431 for(i
= 0; i
< 8; i
++)
432 env
->regs
[i
] = new_regs
[i
];
433 if (new_eflags
& VM_MASK
) {
434 for(i
= 0; i
< 6; i
++)
435 load_seg_vm(i
, new_segs
[i
]);
436 /* in vm86, CPL is always 3 */
437 cpu_x86_set_cpl(env
, 3);
439 /* CPL is set the RPL of CS */
440 cpu_x86_set_cpl(env
, new_segs
[R_CS
] & 3);
441 /* first just selectors as the rest may trigger exceptions */
442 for(i
= 0; i
< 6; i
++)
443 cpu_x86_load_seg_cache(env
, i
, new_segs
[i
], NULL
, 0, 0);
446 env
->ldt
.selector
= new_ldt
& ~4;
447 env
->ldt
.base
= NULL
;
453 raise_exception_err(EXCP0A_TSS
, new_ldt
& 0xfffc);
456 index
= new_ldt
& ~7;
457 if ((index
+ 7) > dt
->limit
)
458 raise_exception_err(EXCP0A_TSS
, new_ldt
& 0xfffc);
459 ptr
= dt
->base
+ index
;
460 e1
= ldl_kernel(ptr
);
461 e2
= ldl_kernel(ptr
+ 4);
462 if ((e2
& DESC_S_MASK
) || ((e2
>> DESC_TYPE_SHIFT
) & 0xf) != 2)
463 raise_exception_err(EXCP0A_TSS
, new_ldt
& 0xfffc);
464 if (!(e2
& DESC_P_MASK
))
465 raise_exception_err(EXCP0A_TSS
, new_ldt
& 0xfffc);
466 load_seg_cache_raw_dt(&env
->ldt
, e1
, e2
);
468 /* load the segments */
469 if (!(new_eflags
& VM_MASK
)) {
470 tss_load_seg(R_CS
, new_segs
[R_CS
]);
471 tss_load_seg(R_SS
, new_segs
[R_SS
]);
472 tss_load_seg(R_ES
, new_segs
[R_ES
]);
473 tss_load_seg(R_DS
, new_segs
[R_DS
]);
474 tss_load_seg(R_FS
, new_segs
[R_FS
]);
475 tss_load_seg(R_GS
, new_segs
[R_GS
]);
478 /* check that EIP is in the CS segment limits */
479 if (new_eip
> env
->segs
[R_CS
].limit
) {
480 raise_exception_err(EXCP0D_GPF
, 0);
484 /* check if Port I/O is allowed in TSS */
485 static inline void check_io(int addr
, int size
)
487 int io_offset
, val
, mask
;
489 /* TSS must be a valid 32 bit one */
490 if (!(env
->tr
.flags
& DESC_P_MASK
) ||
491 ((env
->tr
.flags
>> DESC_TYPE_SHIFT
) & 0xf) != 9 ||
494 io_offset
= lduw_kernel(env
->tr
.base
+ 0x66);
495 io_offset
+= (addr
>> 3);
496 /* Note: the check needs two bytes */
497 if ((io_offset
+ 1) > env
->tr
.limit
)
499 val
= lduw_kernel(env
->tr
.base
+ io_offset
);
501 mask
= (1 << size
) - 1;
502 /* all bits must be zero to allow the I/O */
503 if ((val
& mask
) != 0) {
505 raise_exception_err(EXCP0D_GPF
, 0);
509 void check_iob_T0(void)
514 void check_iow_T0(void)
519 void check_iol_T0(void)
524 void check_iob_DX(void)
526 check_io(EDX
& 0xffff, 1);
529 void check_iow_DX(void)
531 check_io(EDX
& 0xffff, 2);
534 void check_iol_DX(void)
536 check_io(EDX
& 0xffff, 4);
539 static inline unsigned int get_sp_mask(unsigned int e2
)
541 if (e2
& DESC_B_MASK
)
547 /* XXX: add a is_user flag to have proper security support */
548 #define PUSHW(ssp, sp, sp_mask, val)\
551 stw_kernel((ssp) + (sp & (sp_mask)), (val));\
554 #define PUSHL(ssp, sp, sp_mask, val)\
557 stl_kernel((ssp) + (sp & (sp_mask)), (val));\
560 #define POPW(ssp, sp, sp_mask, val)\
562 val = lduw_kernel((ssp) + (sp & (sp_mask)));\
566 #define POPL(ssp, sp, sp_mask, val)\
568 val = ldl_kernel((ssp) + (sp & (sp_mask)));\
572 /* protected mode interrupt */
573 static void do_interrupt_protected(int intno
, int is_int
, int error_code
,
574 unsigned int next_eip
, int is_hw
)
578 int type
, dpl
, selector
, ss_dpl
, cpl
, sp_mask
;
579 int has_error_code
, new_stack
, shift
;
580 uint32_t e1
, e2
, offset
, ss
, esp
, ss_e1
, ss_e2
;
584 if (!is_int
&& !is_hw
) {
599 if (intno
* 8 + 7 > dt
->limit
)
600 raise_exception_err(EXCP0D_GPF
, intno
* 8 + 2);
601 ptr
= dt
->base
+ intno
* 8;
602 e1
= ldl_kernel(ptr
);
603 e2
= ldl_kernel(ptr
+ 4);
604 /* check gate type */
605 type
= (e2
>> DESC_TYPE_SHIFT
) & 0x1f;
607 case 5: /* task gate */
608 /* must do that check here to return the correct error code */
609 if (!(e2
& DESC_P_MASK
))
610 raise_exception_err(EXCP0B_NOSEG
, intno
* 8 + 2);
611 switch_tss(intno
* 8, e1
, e2
, SWITCH_TSS_CALL
);
612 if (has_error_code
) {
614 /* push the error code */
615 shift
= (env
->segs
[R_CS
].flags
>> DESC_B_SHIFT
) & 1;
616 if (env
->segs
[R_SS
].flags
& DESC_B_MASK
)
620 esp
= (env
->regs
[R_ESP
] - (2 << shift
)) & mask
;
621 ssp
= env
->segs
[R_SS
].base
+ esp
;
623 stl_kernel(ssp
, error_code
);
625 stw_kernel(ssp
, error_code
);
626 env
->regs
[R_ESP
] = (esp
& mask
) | (env
->regs
[R_ESP
] & ~mask
);
629 case 6: /* 286 interrupt gate */
630 case 7: /* 286 trap gate */
631 case 14: /* 386 interrupt gate */
632 case 15: /* 386 trap gate */
635 raise_exception_err(EXCP0D_GPF
, intno
* 8 + 2);
638 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
639 cpl
= env
->hflags
& HF_CPL_MASK
;
640 /* check privledge if software int */
641 if (is_int
&& dpl
< cpl
)
642 raise_exception_err(EXCP0D_GPF
, intno
* 8 + 2);
643 /* check valid bit */
644 if (!(e2
& DESC_P_MASK
))
645 raise_exception_err(EXCP0B_NOSEG
, intno
* 8 + 2);
647 offset
= (e2
& 0xffff0000) | (e1
& 0x0000ffff);
648 if ((selector
& 0xfffc) == 0)
649 raise_exception_err(EXCP0D_GPF
, 0);
651 if (load_segment(&e1
, &e2
, selector
) != 0)
652 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
653 if (!(e2
& DESC_S_MASK
) || !(e2
& (DESC_CS_MASK
)))
654 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
655 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
657 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
658 if (!(e2
& DESC_P_MASK
))
659 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
660 if (!(e2
& DESC_C_MASK
) && dpl
< cpl
) {
661 /* to inner priviledge */
662 get_ss_esp_from_tss(&ss
, &esp
, dpl
);
663 if ((ss
& 0xfffc) == 0)
664 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
666 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
667 if (load_segment(&ss_e1
, &ss_e2
, ss
) != 0)
668 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
669 ss_dpl
= (ss_e2
>> DESC_DPL_SHIFT
) & 3;
671 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
672 if (!(ss_e2
& DESC_S_MASK
) ||
673 (ss_e2
& DESC_CS_MASK
) ||
674 !(ss_e2
& DESC_W_MASK
))
675 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
676 if (!(ss_e2
& DESC_P_MASK
))
677 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
679 sp_mask
= get_sp_mask(ss_e2
);
680 ssp
= get_seg_base(ss_e1
, ss_e2
);
681 } else if ((e2
& DESC_C_MASK
) || dpl
== cpl
) {
682 /* to same priviledge */
683 if (env
->eflags
& VM_MASK
)
684 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
686 sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
687 ssp
= env
->segs
[R_SS
].base
;
690 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
691 new_stack
= 0; /* avoid warning */
692 sp_mask
= 0; /* avoid warning */
693 ssp
= NULL
; /* avoid warning */
694 esp
= 0; /* avoid warning */
700 /* XXX: check that enough room is available */
701 push_size
= 6 + (new_stack
<< 2) + (has_error_code
<< 1);
702 if (env
->eflags
& VM_MASK
)
712 if (env
->eflags
& VM_MASK
) {
713 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_GS
].selector
);
714 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_FS
].selector
);
715 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_DS
].selector
);
716 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_ES
].selector
);
718 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_SS
].selector
);
719 PUSHL(ssp
, esp
, sp_mask
, ESP
);
721 PUSHL(ssp
, esp
, sp_mask
, compute_eflags());
722 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_CS
].selector
);
723 PUSHL(ssp
, esp
, sp_mask
, old_eip
);
724 if (has_error_code
) {
725 PUSHL(ssp
, esp
, sp_mask
, error_code
);
729 if (env
->eflags
& VM_MASK
) {
730 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_GS
].selector
);
731 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_FS
].selector
);
732 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_DS
].selector
);
733 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_ES
].selector
);
735 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_SS
].selector
);
736 PUSHW(ssp
, esp
, sp_mask
, ESP
);
738 PUSHW(ssp
, esp
, sp_mask
, compute_eflags());
739 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_CS
].selector
);
740 PUSHW(ssp
, esp
, sp_mask
, old_eip
);
741 if (has_error_code
) {
742 PUSHW(ssp
, esp
, sp_mask
, error_code
);
747 if (env
->eflags
& VM_MASK
) {
748 /* XXX: explain me why W2K hangs if the whole segment cache is
750 env
->segs
[R_ES
].selector
= 0;
751 env
->segs
[R_ES
].flags
= 0;
752 env
->segs
[R_DS
].selector
= 0;
753 env
->segs
[R_DS
].flags
= 0;
754 env
->segs
[R_FS
].selector
= 0;
755 env
->segs
[R_FS
].flags
= 0;
756 env
->segs
[R_GS
].selector
= 0;
757 env
->segs
[R_GS
].flags
= 0;
759 ss
= (ss
& ~3) | dpl
;
760 cpu_x86_load_seg_cache(env
, R_SS
, ss
,
761 ssp
, get_seg_limit(ss_e1
, ss_e2
), ss_e2
);
763 ESP
= (ESP
& ~sp_mask
) | (esp
& sp_mask
);
765 selector
= (selector
& ~3) | dpl
;
766 cpu_x86_load_seg_cache(env
, R_CS
, selector
,
767 get_seg_base(e1
, e2
),
768 get_seg_limit(e1
, e2
),
770 cpu_x86_set_cpl(env
, dpl
);
773 /* interrupt gate clear IF mask */
774 if ((type
& 1) == 0) {
775 env
->eflags
&= ~IF_MASK
;
777 env
->eflags
&= ~(TF_MASK
| VM_MASK
| RF_MASK
| NT_MASK
);
780 /* real mode interrupt */
781 static void do_interrupt_real(int intno
, int is_int
, int error_code
,
782 unsigned int next_eip
)
787 uint32_t offset
, esp
;
788 uint32_t old_cs
, old_eip
;
790 /* real mode (simpler !) */
792 if (intno
* 4 + 3 > dt
->limit
)
793 raise_exception_err(EXCP0D_GPF
, intno
* 8 + 2);
794 ptr
= dt
->base
+ intno
* 4;
795 offset
= lduw_kernel(ptr
);
796 selector
= lduw_kernel(ptr
+ 2);
798 ssp
= env
->segs
[R_SS
].base
;
803 old_cs
= env
->segs
[R_CS
].selector
;
804 /* XXX: use SS segment size ? */
805 PUSHW(ssp
, esp
, 0xffff, compute_eflags());
806 PUSHW(ssp
, esp
, 0xffff, old_cs
);
807 PUSHW(ssp
, esp
, 0xffff, old_eip
);
809 /* update processor state */
810 ESP
= (ESP
& ~0xffff) | (esp
& 0xffff);
812 env
->segs
[R_CS
].selector
= selector
;
813 env
->segs
[R_CS
].base
= (uint8_t *)(selector
<< 4);
814 env
->eflags
&= ~(IF_MASK
| TF_MASK
| AC_MASK
| RF_MASK
);
817 /* fake user mode interrupt */
818 void do_interrupt_user(int intno
, int is_int
, int error_code
,
819 unsigned int next_eip
)
827 ptr
= dt
->base
+ (intno
* 8);
828 e2
= ldl_kernel(ptr
+ 4);
830 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
831 cpl
= env
->hflags
& HF_CPL_MASK
;
832 /* check privledge if software int */
833 if (is_int
&& dpl
< cpl
)
834 raise_exception_err(EXCP0D_GPF
, intno
* 8 + 2);
836 /* Since we emulate only user space, we cannot do more than
837 exiting the emulation with the suitable exception and error
844 * Begin excution of an interruption. is_int is TRUE if coming from
845 * the int instruction. next_eip is the EIP value AFTER the interrupt
846 * instruction. It is only relevant if is_int is TRUE.
848 void do_interrupt(int intno
, int is_int
, int error_code
,
849 unsigned int next_eip
, int is_hw
)
855 if ((env
->cr
[0] && CR0_PE_MASK
)) {
856 fprintf(stdout
, "%d: interrupt: vector=%02x error_code=%04x int=%d CPL=%d CS:EIP=%04x:%08x SS:ESP=%04x:%08x EAX=%08x\n",
857 count
, intno
, error_code
, is_int
,
858 env
->hflags
& HF_CPL_MASK
,
859 env
->segs
[R_CS
].selector
, EIP
,
860 env
->segs
[R_SS
].selector
, ESP
,
863 cpu_x86_dump_state(env
, stdout
, X86_DUMP_CCOP
);
868 fprintf(stdout
, " code=");
869 ptr
= env
->segs
[R_CS
].base
+ env
->eip
;
870 for(i
= 0; i
< 16; i
++) {
871 fprintf(stdout
, " %02x", ldub(ptr
+ i
));
873 fprintf(stdout
, "\n");
885 fprintf(logfile
, "%d: interrupt: vector=%02x error_code=%04x int=%d\n",
886 count
, intno
, error_code
, is_int
);
887 cpu_x86_dump_state(env
, logfile
, X86_DUMP_CCOP
);
892 fprintf(logfile
, " code=");
893 ptr
= env
->segs
[R_CS
].base
+ env
->eip
;
894 for(i
= 0; i
< 16; i
++) {
895 fprintf(logfile
, " %02x", ldub(ptr
+ i
));
897 fprintf(logfile
, "\n");
903 if (env
->cr
[0] & CR0_PE_MASK
) {
904 do_interrupt_protected(intno
, is_int
, error_code
, next_eip
, is_hw
);
906 do_interrupt_real(intno
, is_int
, error_code
, next_eip
);
911 * Signal an interruption. It is executed in the main CPU loop.
912 * is_int is TRUE if coming from the int instruction. next_eip is the
913 * EIP value AFTER the interrupt instruction. It is only relevant if
916 void raise_interrupt(int intno
, int is_int
, int error_code
,
917 unsigned int next_eip
)
919 env
->exception_index
= intno
;
920 env
->error_code
= error_code
;
921 env
->exception_is_int
= is_int
;
922 env
->exception_next_eip
= next_eip
;
926 /* shortcuts to generate exceptions */
927 void raise_exception_err(int exception_index
, int error_code
)
929 raise_interrupt(exception_index
, 0, error_code
, 0);
932 void raise_exception(int exception_index
)
934 raise_interrupt(exception_index
, 0, 0, 0);
937 #ifdef BUGGY_GCC_DIV64
938 /* gcc 2.95.4 on PowerPC does not seem to like using __udivdi3, so we
939 call it from another function */
940 uint32_t div64(uint32_t *q_ptr
, uint64_t num
, uint32_t den
)
946 int32_t idiv64(int32_t *q_ptr
, int64_t num
, int32_t den
)
953 void helper_divl_EAX_T0(uint32_t eip
)
955 unsigned int den
, q
, r
;
958 num
= EAX
| ((uint64_t)EDX
<< 32);
962 raise_exception(EXCP00_DIVZ
);
964 #ifdef BUGGY_GCC_DIV64
965 r
= div64(&q
, num
, den
);
974 void helper_idivl_EAX_T0(uint32_t eip
)
979 num
= EAX
| ((uint64_t)EDX
<< 32);
983 raise_exception(EXCP00_DIVZ
);
985 #ifdef BUGGY_GCC_DIV64
986 r
= idiv64(&q
, num
, den
);
995 void helper_cmpxchg8b(void)
1000 eflags
= cc_table
[CC_OP
].compute_all();
1001 d
= ldq((uint8_t *)A0
);
1002 if (d
== (((uint64_t)EDX
<< 32) | EAX
)) {
1003 stq((uint8_t *)A0
, ((uint64_t)ECX
<< 32) | EBX
);
1013 #define CPUID_FP87 (1 << 0)
1014 #define CPUID_VME (1 << 1)
1015 #define CPUID_DE (1 << 2)
1016 #define CPUID_PSE (1 << 3)
1017 #define CPUID_TSC (1 << 4)
1018 #define CPUID_MSR (1 << 5)
1019 #define CPUID_PAE (1 << 6)
1020 #define CPUID_MCE (1 << 7)
1021 #define CPUID_CX8 (1 << 8)
1022 #define CPUID_APIC (1 << 9)
1023 #define CPUID_SEP (1 << 11) /* sysenter/sysexit */
1024 #define CPUID_MTRR (1 << 12)
1025 #define CPUID_PGE (1 << 13)
1026 #define CPUID_MCA (1 << 14)
1027 #define CPUID_CMOV (1 << 15)
1029 #define CPUID_MMX (1 << 23)
1030 #define CPUID_FXSR (1 << 24)
1031 #define CPUID_SSE (1 << 25)
1032 #define CPUID_SSE2 (1 << 26)
1034 void helper_cpuid(void)
1038 EAX
= 2; /* max EAX index supported */
1045 int family
, model
, stepping
;
1048 /* pentium 75-200 */
1058 EAX
= (family
<< 8) | (model
<< 4) | stepping
;
1061 EDX
= CPUID_FP87
| CPUID_DE
| CPUID_PSE
|
1062 CPUID_TSC
| CPUID_MSR
| CPUID_MCE
|
1063 CPUID_CX8
| CPUID_PGE
| CPUID_CMOV
;
1067 /* cache info: needed for Pentium Pro compatibility */
1076 void helper_lldt_T0(void)
1084 selector
= T0
& 0xffff;
1085 if ((selector
& 0xfffc) == 0) {
1086 /* XXX: NULL selector case: invalid LDT */
1087 env
->ldt
.base
= NULL
;
1091 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1093 index
= selector
& ~7;
1094 if ((index
+ 7) > dt
->limit
)
1095 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1096 ptr
= dt
->base
+ index
;
1097 e1
= ldl_kernel(ptr
);
1098 e2
= ldl_kernel(ptr
+ 4);
1099 if ((e2
& DESC_S_MASK
) || ((e2
>> DESC_TYPE_SHIFT
) & 0xf) != 2)
1100 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1101 if (!(e2
& DESC_P_MASK
))
1102 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
1103 load_seg_cache_raw_dt(&env
->ldt
, e1
, e2
);
1105 env
->ldt
.selector
= selector
;
1108 void helper_ltr_T0(void)
1116 selector
= T0
& 0xffff;
1117 if ((selector
& 0xfffc) == 0) {
1118 /* NULL selector case: invalid LDT */
1119 env
->tr
.base
= NULL
;
1124 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1126 index
= selector
& ~7;
1127 if ((index
+ 7) > dt
->limit
)
1128 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1129 ptr
= dt
->base
+ index
;
1130 e1
= ldl_kernel(ptr
);
1131 e2
= ldl_kernel(ptr
+ 4);
1132 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
1133 if ((e2
& DESC_S_MASK
) ||
1134 (type
!= 1 && type
!= 9))
1135 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1136 if (!(e2
& DESC_P_MASK
))
1137 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
1138 load_seg_cache_raw_dt(&env
->tr
, e1
, e2
);
1139 e2
|= DESC_TSS_BUSY_MASK
;
1140 stl_kernel(ptr
+ 4, e2
);
1142 env
->tr
.selector
= selector
;
1145 /* only works if protected mode and not VM86. seg_reg must be != R_CS */
1146 void load_seg(int seg_reg
, int selector
)
1155 if ((selector
& 0xfffc) == 0) {
1156 /* null selector case */
1157 if (seg_reg
== R_SS
)
1158 raise_exception_err(EXCP0D_GPF
, 0);
1159 cpu_x86_load_seg_cache(env
, seg_reg
, selector
, NULL
, 0, 0);
1166 index
= selector
& ~7;
1167 if ((index
+ 7) > dt
->limit
)
1168 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1169 ptr
= dt
->base
+ index
;
1170 e1
= ldl_kernel(ptr
);
1171 e2
= ldl_kernel(ptr
+ 4);
1173 if (!(e2
& DESC_S_MASK
))
1174 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1176 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1177 cpl
= env
->hflags
& HF_CPL_MASK
;
1178 if (seg_reg
== R_SS
) {
1179 /* must be writable segment */
1180 if ((e2
& DESC_CS_MASK
) || !(e2
& DESC_W_MASK
))
1181 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1182 if (rpl
!= cpl
|| dpl
!= cpl
)
1183 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1185 /* must be readable segment */
1186 if ((e2
& (DESC_CS_MASK
| DESC_R_MASK
)) == DESC_CS_MASK
)
1187 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1189 if (!(e2
& DESC_CS_MASK
) || !(e2
& DESC_C_MASK
)) {
1190 /* if not conforming code, test rights */
1191 if (dpl
< cpl
|| dpl
< rpl
)
1192 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1196 if (!(e2
& DESC_P_MASK
)) {
1197 if (seg_reg
== R_SS
)
1198 raise_exception_err(EXCP0C_STACK
, selector
& 0xfffc);
1200 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
1203 /* set the access bit if not already set */
1204 if (!(e2
& DESC_A_MASK
)) {
1206 stl_kernel(ptr
+ 4, e2
);
1209 cpu_x86_load_seg_cache(env
, seg_reg
, selector
,
1210 get_seg_base(e1
, e2
),
1211 get_seg_limit(e1
, e2
),
1214 fprintf(logfile
, "load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
1215 selector
, (unsigned long)sc
->base
, sc
->limit
, sc
->flags
);
1220 /* protected mode jump */
1221 void helper_ljmp_protected_T0_T1(void)
1223 int new_cs
, new_eip
, gate_cs
, type
;
1224 uint32_t e1
, e2
, cpl
, dpl
, rpl
, limit
;
1228 if ((new_cs
& 0xfffc) == 0)
1229 raise_exception_err(EXCP0D_GPF
, 0);
1230 if (load_segment(&e1
, &e2
, new_cs
) != 0)
1231 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1232 cpl
= env
->hflags
& HF_CPL_MASK
;
1233 if (e2
& DESC_S_MASK
) {
1234 if (!(e2
& DESC_CS_MASK
))
1235 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1236 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1237 if (e2
& DESC_C_MASK
) {
1238 /* conforming code segment */
1240 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1242 /* non conforming code segment */
1245 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1247 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1249 if (!(e2
& DESC_P_MASK
))
1250 raise_exception_err(EXCP0B_NOSEG
, new_cs
& 0xfffc);
1251 limit
= get_seg_limit(e1
, e2
);
1252 if (new_eip
> limit
)
1253 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1254 cpu_x86_load_seg_cache(env
, R_CS
, (new_cs
& 0xfffc) | cpl
,
1255 get_seg_base(e1
, e2
), limit
, e2
);
1258 /* jump to call or task gate */
1259 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1261 cpl
= env
->hflags
& HF_CPL_MASK
;
1262 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
1264 case 1: /* 286 TSS */
1265 case 9: /* 386 TSS */
1266 case 5: /* task gate */
1267 if (dpl
< cpl
|| dpl
< rpl
)
1268 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1269 switch_tss(new_cs
, e1
, e2
, SWITCH_TSS_JMP
);
1271 case 4: /* 286 call gate */
1272 case 12: /* 386 call gate */
1273 if ((dpl
< cpl
) || (dpl
< rpl
))
1274 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1275 if (!(e2
& DESC_P_MASK
))
1276 raise_exception_err(EXCP0B_NOSEG
, new_cs
& 0xfffc);
1278 if (load_segment(&e1
, &e2
, gate_cs
) != 0)
1279 raise_exception_err(EXCP0D_GPF
, gate_cs
& 0xfffc);
1280 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1281 /* must be code segment */
1282 if (((e2
& (DESC_S_MASK
| DESC_CS_MASK
)) !=
1283 (DESC_S_MASK
| DESC_CS_MASK
)))
1284 raise_exception_err(EXCP0D_GPF
, gate_cs
& 0xfffc);
1285 if (((e2
& DESC_C_MASK
) && (dpl
> cpl
)) ||
1286 (!(e2
& DESC_C_MASK
) && (dpl
!= cpl
)))
1287 raise_exception_err(EXCP0D_GPF
, gate_cs
& 0xfffc);
1288 if (!(e2
& DESC_P_MASK
))
1289 raise_exception_err(EXCP0D_GPF
, gate_cs
& 0xfffc);
1290 new_eip
= (e1
& 0xffff);
1292 new_eip
|= (e2
& 0xffff0000);
1293 limit
= get_seg_limit(e1
, e2
);
1294 if (new_eip
> limit
)
1295 raise_exception_err(EXCP0D_GPF
, 0);
1296 cpu_x86_load_seg_cache(env
, R_CS
, (gate_cs
& 0xfffc) | cpl
,
1297 get_seg_base(e1
, e2
), limit
, e2
);
1301 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1307 /* real mode call */
1308 void helper_lcall_real_T0_T1(int shift
, int next_eip
)
1310 int new_cs
, new_eip
;
1311 uint32_t esp
, esp_mask
;
1317 esp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
1318 ssp
= env
->segs
[R_SS
].base
;
1320 PUSHL(ssp
, esp
, esp_mask
, env
->segs
[R_CS
].selector
);
1321 PUSHL(ssp
, esp
, esp_mask
, next_eip
);
1323 PUSHW(ssp
, esp
, esp_mask
, env
->segs
[R_CS
].selector
);
1324 PUSHW(ssp
, esp
, esp_mask
, next_eip
);
1327 ESP
= (ESP
& ~esp_mask
) | (esp
& esp_mask
);
1329 env
->segs
[R_CS
].selector
= new_cs
;
1330 env
->segs
[R_CS
].base
= (uint8_t *)(new_cs
<< 4);
1333 /* protected mode call */
1334 void helper_lcall_protected_T0_T1(int shift
, int next_eip
)
1336 int new_cs
, new_eip
, new_stack
, i
;
1337 uint32_t e1
, e2
, cpl
, dpl
, rpl
, selector
, offset
, param_count
;
1338 uint32_t ss
, ss_e1
, ss_e2
, sp
, type
, ss_dpl
, sp_mask
;
1339 uint32_t val
, limit
, old_sp_mask
;
1340 uint8_t *ssp
, *old_ssp
;
1346 fprintf(logfile
, "lcall %04x:%08x\n",
1348 cpu_x86_dump_state(env
, logfile
, X86_DUMP_CCOP
);
1351 if ((new_cs
& 0xfffc) == 0)
1352 raise_exception_err(EXCP0D_GPF
, 0);
1353 if (load_segment(&e1
, &e2
, new_cs
) != 0)
1354 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1355 cpl
= env
->hflags
& HF_CPL_MASK
;
1358 fprintf(logfile
, "desc=%08x:%08x\n", e1
, e2
);
1361 if (e2
& DESC_S_MASK
) {
1362 if (!(e2
& DESC_CS_MASK
))
1363 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1364 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1365 if (e2
& DESC_C_MASK
) {
1366 /* conforming code segment */
1368 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1370 /* non conforming code segment */
1373 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1375 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1377 if (!(e2
& DESC_P_MASK
))
1378 raise_exception_err(EXCP0B_NOSEG
, new_cs
& 0xfffc);
1381 sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
1382 ssp
= env
->segs
[R_SS
].base
;
1384 PUSHL(ssp
, sp
, sp_mask
, env
->segs
[R_CS
].selector
);
1385 PUSHL(ssp
, sp
, sp_mask
, next_eip
);
1387 PUSHW(ssp
, sp
, sp_mask
, env
->segs
[R_CS
].selector
);
1388 PUSHW(ssp
, sp
, sp_mask
, next_eip
);
1391 limit
= get_seg_limit(e1
, e2
);
1392 if (new_eip
> limit
)
1393 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1394 /* from this point, not restartable */
1395 ESP
= (ESP
& ~sp_mask
) | (sp
& sp_mask
);
1396 cpu_x86_load_seg_cache(env
, R_CS
, (new_cs
& 0xfffc) | cpl
,
1397 get_seg_base(e1
, e2
), limit
, e2
);
1400 /* check gate type */
1401 type
= (e2
>> DESC_TYPE_SHIFT
) & 0x1f;
1402 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1405 case 1: /* available 286 TSS */
1406 case 9: /* available 386 TSS */
1407 case 5: /* task gate */
1408 if (dpl
< cpl
|| dpl
< rpl
)
1409 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1410 switch_tss(new_cs
, e1
, e2
, SWITCH_TSS_CALL
);
1412 case 4: /* 286 call gate */
1413 case 12: /* 386 call gate */
1416 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1421 if (dpl
< cpl
|| dpl
< rpl
)
1422 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1423 /* check valid bit */
1424 if (!(e2
& DESC_P_MASK
))
1425 raise_exception_err(EXCP0B_NOSEG
, new_cs
& 0xfffc);
1426 selector
= e1
>> 16;
1427 offset
= (e2
& 0xffff0000) | (e1
& 0x0000ffff);
1428 param_count
= e2
& 0x1f;
1429 if ((selector
& 0xfffc) == 0)
1430 raise_exception_err(EXCP0D_GPF
, 0);
1432 if (load_segment(&e1
, &e2
, selector
) != 0)
1433 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1434 if (!(e2
& DESC_S_MASK
) || !(e2
& (DESC_CS_MASK
)))
1435 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1436 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1438 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1439 if (!(e2
& DESC_P_MASK
))
1440 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
1442 if (!(e2
& DESC_C_MASK
) && dpl
< cpl
) {
1443 /* to inner priviledge */
1444 get_ss_esp_from_tss(&ss
, &sp
, dpl
);
1447 fprintf(logfile
, "ss=%04x sp=%04x param_count=%d ESP=%x\n",
1448 ss
, sp
, param_count
, ESP
);
1450 if ((ss
& 0xfffc) == 0)
1451 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
1452 if ((ss
& 3) != dpl
)
1453 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
1454 if (load_segment(&ss_e1
, &ss_e2
, ss
) != 0)
1455 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
1456 ss_dpl
= (ss_e2
>> DESC_DPL_SHIFT
) & 3;
1458 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
1459 if (!(ss_e2
& DESC_S_MASK
) ||
1460 (ss_e2
& DESC_CS_MASK
) ||
1461 !(ss_e2
& DESC_W_MASK
))
1462 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
1463 if (!(ss_e2
& DESC_P_MASK
))
1464 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
1466 // push_size = ((param_count * 2) + 8) << shift;
1468 old_sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
1469 old_ssp
= env
->segs
[R_SS
].base
;
1471 sp_mask
= get_sp_mask(ss_e2
);
1472 ssp
= get_seg_base(ss_e1
, ss_e2
);
1474 PUSHL(ssp
, sp
, sp_mask
, env
->segs
[R_SS
].selector
);
1475 PUSHL(ssp
, sp
, sp_mask
, ESP
);
1476 for(i
= param_count
- 1; i
>= 0; i
--) {
1477 val
= ldl_kernel(old_ssp
+ ((ESP
+ i
* 4) & old_sp_mask
));
1478 PUSHL(ssp
, sp
, sp_mask
, val
);
1481 PUSHW(ssp
, sp
, sp_mask
, env
->segs
[R_SS
].selector
);
1482 PUSHW(ssp
, sp
, sp_mask
, ESP
);
1483 for(i
= param_count
- 1; i
>= 0; i
--) {
1484 val
= lduw_kernel(old_ssp
+ ((ESP
+ i
* 2) & old_sp_mask
));
1485 PUSHW(ssp
, sp
, sp_mask
, val
);
1490 /* to same priviledge */
1492 sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
1493 ssp
= env
->segs
[R_SS
].base
;
1494 // push_size = (4 << shift);
1499 PUSHL(ssp
, sp
, sp_mask
, env
->segs
[R_CS
].selector
);
1500 PUSHL(ssp
, sp
, sp_mask
, next_eip
);
1502 PUSHW(ssp
, sp
, sp_mask
, env
->segs
[R_CS
].selector
);
1503 PUSHW(ssp
, sp
, sp_mask
, next_eip
);
1506 /* from this point, not restartable */
1509 ss
= (ss
& ~3) | dpl
;
1510 cpu_x86_load_seg_cache(env
, R_SS
, ss
,
1512 get_seg_limit(ss_e1
, ss_e2
),
1516 selector
= (selector
& ~3) | dpl
;
1517 cpu_x86_load_seg_cache(env
, R_CS
, selector
,
1518 get_seg_base(e1
, e2
),
1519 get_seg_limit(e1
, e2
),
1521 cpu_x86_set_cpl(env
, dpl
);
1522 ESP
= (ESP
& ~sp_mask
) | (sp
& sp_mask
);
1527 /* real and vm86 mode iret */
1528 void helper_iret_real(int shift
)
1530 uint32_t sp
, new_cs
, new_eip
, new_eflags
, sp_mask
;
1534 sp_mask
= 0xffff; /* XXXX: use SS segment size ? */
1536 ssp
= env
->segs
[R_SS
].base
;
1539 POPL(ssp
, sp
, sp_mask
, new_eip
);
1540 POPL(ssp
, sp
, sp_mask
, new_cs
);
1542 POPL(ssp
, sp
, sp_mask
, new_eflags
);
1545 POPW(ssp
, sp
, sp_mask
, new_eip
);
1546 POPW(ssp
, sp
, sp_mask
, new_cs
);
1547 POPW(ssp
, sp
, sp_mask
, new_eflags
);
1549 ESP
= (ESP
& ~sp_mask
) | (sp
& sp_mask
);
1550 load_seg_vm(R_CS
, new_cs
);
1552 if (env
->eflags
& VM_MASK
)
1553 eflags_mask
= TF_MASK
| AC_MASK
| ID_MASK
| IF_MASK
| RF_MASK
;
1555 eflags_mask
= TF_MASK
| AC_MASK
| ID_MASK
| IF_MASK
| IOPL_MASK
| RF_MASK
;
1557 eflags_mask
&= 0xffff;
1558 load_eflags(new_eflags
, eflags_mask
);
1561 static inline void validate_seg(int seg_reg
, int cpl
)
1566 e2
= env
->segs
[seg_reg
].flags
;
1567 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1568 if (!(e2
& DESC_CS_MASK
) || !(e2
& DESC_C_MASK
)) {
1569 /* data or non conforming code segment */
1571 cpu_x86_load_seg_cache(env
, seg_reg
, 0, NULL
, 0, 0);
1576 /* protected mode iret */
1577 static inline void helper_ret_protected(int shift
, int is_iret
, int addend
)
1579 uint32_t sp
, new_cs
, new_eip
, new_eflags
, new_esp
, new_ss
, sp_mask
;
1580 uint32_t new_es
, new_ds
, new_fs
, new_gs
;
1581 uint32_t e1
, e2
, ss_e1
, ss_e2
;
1582 int cpl
, dpl
, rpl
, eflags_mask
, iopl
;
1585 sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
1587 ssp
= env
->segs
[R_SS
].base
;
1590 POPL(ssp
, sp
, sp_mask
, new_eip
);
1591 POPL(ssp
, sp
, sp_mask
, new_cs
);
1594 POPL(ssp
, sp
, sp_mask
, new_eflags
);
1595 if (new_eflags
& VM_MASK
)
1596 goto return_to_vm86
;
1600 POPW(ssp
, sp
, sp_mask
, new_eip
);
1601 POPW(ssp
, sp
, sp_mask
, new_cs
);
1603 POPW(ssp
, sp
, sp_mask
, new_eflags
);
1607 fprintf(logfile
, "lret new %04x:%08x addend=0x%x\n",
1608 new_cs
, new_eip
, addend
);
1609 cpu_x86_dump_state(env
, logfile
, X86_DUMP_CCOP
);
1612 if ((new_cs
& 0xfffc) == 0)
1613 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1614 if (load_segment(&e1
, &e2
, new_cs
) != 0)
1615 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1616 if (!(e2
& DESC_S_MASK
) ||
1617 !(e2
& DESC_CS_MASK
))
1618 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1619 cpl
= env
->hflags
& HF_CPL_MASK
;
1622 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1623 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1624 if (e2
& DESC_C_MASK
) {
1626 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1629 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1631 if (!(e2
& DESC_P_MASK
))
1632 raise_exception_err(EXCP0B_NOSEG
, new_cs
& 0xfffc);
1636 /* return to same priledge level */
1637 cpu_x86_load_seg_cache(env
, R_CS
, new_cs
,
1638 get_seg_base(e1
, e2
),
1639 get_seg_limit(e1
, e2
),
1642 /* return to different priviledge level */
1645 POPL(ssp
, sp
, sp_mask
, new_esp
);
1646 POPL(ssp
, sp
, sp_mask
, new_ss
);
1650 POPW(ssp
, sp
, sp_mask
, new_esp
);
1651 POPW(ssp
, sp
, sp_mask
, new_ss
);
1654 if ((new_ss
& 3) != rpl
)
1655 raise_exception_err(EXCP0D_GPF
, new_ss
& 0xfffc);
1656 if (load_segment(&ss_e1
, &ss_e2
, new_ss
) != 0)
1657 raise_exception_err(EXCP0D_GPF
, new_ss
& 0xfffc);
1658 if (!(ss_e2
& DESC_S_MASK
) ||
1659 (ss_e2
& DESC_CS_MASK
) ||
1660 !(ss_e2
& DESC_W_MASK
))
1661 raise_exception_err(EXCP0D_GPF
, new_ss
& 0xfffc);
1662 dpl
= (ss_e2
>> DESC_DPL_SHIFT
) & 3;
1664 raise_exception_err(EXCP0D_GPF
, new_ss
& 0xfffc);
1665 if (!(ss_e2
& DESC_P_MASK
))
1666 raise_exception_err(EXCP0B_NOSEG
, new_ss
& 0xfffc);
1668 cpu_x86_load_seg_cache(env
, R_CS
, new_cs
,
1669 get_seg_base(e1
, e2
),
1670 get_seg_limit(e1
, e2
),
1672 cpu_x86_load_seg_cache(env
, R_SS
, new_ss
,
1673 get_seg_base(ss_e1
, ss_e2
),
1674 get_seg_limit(ss_e1
, ss_e2
),
1676 cpu_x86_set_cpl(env
, rpl
);
1678 /* XXX: change sp_mask according to old segment ? */
1680 /* validate data segments */
1681 validate_seg(R_ES
, cpl
);
1682 validate_seg(R_DS
, cpl
);
1683 validate_seg(R_FS
, cpl
);
1684 validate_seg(R_GS
, cpl
);
1686 ESP
= (ESP
& ~sp_mask
) | (sp
& sp_mask
);
1689 /* NOTE: 'cpl' is the _old_ CPL */
1690 eflags_mask
= TF_MASK
| AC_MASK
| ID_MASK
| RF_MASK
;
1692 eflags_mask
|= IOPL_MASK
;
1693 iopl
= (env
->eflags
>> IOPL_SHIFT
) & 3;
1695 eflags_mask
|= IF_MASK
;
1697 eflags_mask
&= 0xffff;
1698 load_eflags(new_eflags
, eflags_mask
);
1703 POPL(ssp
, sp
, sp_mask
, new_esp
);
1704 POPL(ssp
, sp
, sp_mask
, new_ss
);
1705 POPL(ssp
, sp
, sp_mask
, new_es
);
1706 POPL(ssp
, sp
, sp_mask
, new_ds
);
1707 POPL(ssp
, sp
, sp_mask
, new_fs
);
1708 POPL(ssp
, sp
, sp_mask
, new_gs
);
1710 /* modify processor state */
1711 load_eflags(new_eflags
, TF_MASK
| AC_MASK
| ID_MASK
|
1712 IF_MASK
| IOPL_MASK
| VM_MASK
| VIF_MASK
| VIP_MASK
);
1713 load_seg_vm(R_CS
, new_cs
& 0xffff);
1714 cpu_x86_set_cpl(env
, 3);
1715 load_seg_vm(R_SS
, new_ss
& 0xffff);
1716 load_seg_vm(R_ES
, new_es
& 0xffff);
1717 load_seg_vm(R_DS
, new_ds
& 0xffff);
1718 load_seg_vm(R_FS
, new_fs
& 0xffff);
1719 load_seg_vm(R_GS
, new_gs
& 0xffff);
1725 void helper_iret_protected(int shift
)
1727 int tss_selector
, type
;
1730 /* specific case for TSS */
1731 if (env
->eflags
& NT_MASK
) {
1732 tss_selector
= lduw_kernel(env
->tr
.base
+ 0);
1733 if (tss_selector
& 4)
1734 raise_exception_err(EXCP0A_TSS
, tss_selector
& 0xfffc);
1735 if (load_segment(&e1
, &e2
, tss_selector
) != 0)
1736 raise_exception_err(EXCP0A_TSS
, tss_selector
& 0xfffc);
1737 type
= (e2
>> DESC_TYPE_SHIFT
) & 0x17;
1738 /* NOTE: we check both segment and busy TSS */
1740 raise_exception_err(EXCP0A_TSS
, tss_selector
& 0xfffc);
1741 switch_tss(tss_selector
, e1
, e2
, SWITCH_TSS_IRET
);
1743 helper_ret_protected(shift
, 1, 0);
1747 void helper_lret_protected(int shift
, int addend
)
1749 helper_ret_protected(shift
, 0, addend
);
1752 void helper_movl_crN_T0(int reg
)
1757 cpu_x86_update_cr0(env
);
1760 cpu_x86_update_cr3(env
);
1766 void helper_movl_drN_T0(int reg
)
1771 void helper_invlpg(unsigned int addr
)
1773 cpu_x86_flush_tlb(env
, addr
);
1781 void helper_rdtsc(void)
1785 asm("rdtsc" : "=A" (val
));
1787 /* better than nothing: the time increases */
1794 void helper_wrmsr(void)
1797 case MSR_IA32_SYSENTER_CS
:
1798 env
->sysenter_cs
= EAX
& 0xffff;
1800 case MSR_IA32_SYSENTER_ESP
:
1801 env
->sysenter_esp
= EAX
;
1803 case MSR_IA32_SYSENTER_EIP
:
1804 env
->sysenter_eip
= EAX
;
1807 /* XXX: exception ? */
1812 void helper_rdmsr(void)
1815 case MSR_IA32_SYSENTER_CS
:
1816 EAX
= env
->sysenter_cs
;
1819 case MSR_IA32_SYSENTER_ESP
:
1820 EAX
= env
->sysenter_esp
;
1823 case MSR_IA32_SYSENTER_EIP
:
1824 EAX
= env
->sysenter_eip
;
1828 /* XXX: exception ? */
1833 void helper_lsl(void)
1835 unsigned int selector
, limit
;
1837 int rpl
, dpl
, cpl
, type
;
1839 CC_SRC
= cc_table
[CC_OP
].compute_all() & ~CC_Z
;
1840 selector
= T0
& 0xffff;
1841 if (load_segment(&e1
, &e2
, selector
) != 0)
1844 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1845 cpl
= env
->hflags
& HF_CPL_MASK
;
1846 if (e2
& DESC_S_MASK
) {
1847 if ((e2
& DESC_CS_MASK
) && (e2
& DESC_C_MASK
)) {
1850 if (dpl
< cpl
|| dpl
< rpl
)
1854 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
1865 if (dpl
< cpl
|| dpl
< rpl
)
1868 limit
= get_seg_limit(e1
, e2
);
1873 void helper_lar(void)
1875 unsigned int selector
;
1877 int rpl
, dpl
, cpl
, type
;
1879 CC_SRC
= cc_table
[CC_OP
].compute_all() & ~CC_Z
;
1880 selector
= T0
& 0xffff;
1881 if ((selector
& 0xfffc) == 0)
1883 if (load_segment(&e1
, &e2
, selector
) != 0)
1886 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1887 cpl
= env
->hflags
& HF_CPL_MASK
;
1888 if (e2
& DESC_S_MASK
) {
1889 if ((e2
& DESC_CS_MASK
) && (e2
& DESC_C_MASK
)) {
1892 if (dpl
< cpl
|| dpl
< rpl
)
1896 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
1910 if (dpl
< cpl
|| dpl
< rpl
)
1913 T1
= e2
& 0x00f0ff00;
1917 void helper_verr(void)
1919 unsigned int selector
;
1923 CC_SRC
= cc_table
[CC_OP
].compute_all() & ~CC_Z
;
1924 selector
= T0
& 0xffff;
1925 if ((selector
& 0xfffc) == 0)
1927 if (load_segment(&e1
, &e2
, selector
) != 0)
1929 if (!(e2
& DESC_S_MASK
))
1932 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1933 cpl
= env
->hflags
& HF_CPL_MASK
;
1934 if (e2
& DESC_CS_MASK
) {
1935 if (!(e2
& DESC_R_MASK
))
1937 if (!(e2
& DESC_C_MASK
)) {
1938 if (dpl
< cpl
|| dpl
< rpl
)
1942 if (dpl
< cpl
|| dpl
< rpl
)
1948 void helper_verw(void)
1950 unsigned int selector
;
1954 CC_SRC
= cc_table
[CC_OP
].compute_all() & ~CC_Z
;
1955 selector
= T0
& 0xffff;
1956 if ((selector
& 0xfffc) == 0)
1958 if (load_segment(&e1
, &e2
, selector
) != 0)
1960 if (!(e2
& DESC_S_MASK
))
1963 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1964 cpl
= env
->hflags
& HF_CPL_MASK
;
1965 if (e2
& DESC_CS_MASK
) {
1968 if (dpl
< cpl
|| dpl
< rpl
)
1970 if (!(e2
& DESC_W_MASK
))
1978 void helper_fldt_ST0_A0(void)
1981 new_fpstt
= (env
->fpstt
- 1) & 7;
1982 env
->fpregs
[new_fpstt
] = helper_fldt((uint8_t *)A0
);
1983 env
->fpstt
= new_fpstt
;
1984 env
->fptags
[new_fpstt
] = 0; /* validate stack entry */
1987 void helper_fstt_ST0_A0(void)
1989 helper_fstt(ST0
, (uint8_t *)A0
);
1994 #define MUL10(iv) ( iv + iv + (iv << 3) )
1996 void helper_fbld_ST0_A0(void)
2004 for(i
= 8; i
>= 0; i
--) {
2005 v
= ldub((uint8_t *)A0
+ i
);
2006 val
= (val
* 100) + ((v
>> 4) * 10) + (v
& 0xf);
2009 if (ldub((uint8_t *)A0
+ 9) & 0x80)
2015 void helper_fbst_ST0_A0(void)
2019 uint8_t *mem_ref
, *mem_end
;
2024 mem_ref
= (uint8_t *)A0
;
2025 mem_end
= mem_ref
+ 9;
2032 while (mem_ref
< mem_end
) {
2037 v
= ((v
/ 10) << 4) | (v
% 10);
2040 while (mem_ref
< mem_end
) {
2045 void helper_f2xm1(void)
2047 ST0
= pow(2.0,ST0
) - 1.0;
2050 void helper_fyl2x(void)
2052 CPU86_LDouble fptemp
;
2056 fptemp
= log(fptemp
)/log(2.0); /* log2(ST) */
2060 env
->fpus
&= (~0x4700);
2065 void helper_fptan(void)
2067 CPU86_LDouble fptemp
;
2070 if((fptemp
> MAXTAN
)||(fptemp
< -MAXTAN
)) {
2076 env
->fpus
&= (~0x400); /* C2 <-- 0 */
2077 /* the above code is for |arg| < 2**52 only */
2081 void helper_fpatan(void)
2083 CPU86_LDouble fptemp
, fpsrcop
;
2087 ST1
= atan2(fpsrcop
,fptemp
);
2091 void helper_fxtract(void)
2093 CPU86_LDoubleU temp
;
2094 unsigned int expdif
;
2097 expdif
= EXPD(temp
) - EXPBIAS
;
2098 /*DP exponent bias*/
2105 void helper_fprem1(void)
2107 CPU86_LDouble dblq
, fpsrcop
, fptemp
;
2108 CPU86_LDoubleU fpsrcop1
, fptemp1
;
2114 fpsrcop1
.d
= fpsrcop
;
2116 expdif
= EXPD(fpsrcop1
) - EXPD(fptemp1
);
2118 dblq
= fpsrcop
/ fptemp
;
2119 dblq
= (dblq
< 0.0)? ceil(dblq
): floor(dblq
);
2120 ST0
= fpsrcop
- fptemp
*dblq
;
2121 q
= (int)dblq
; /* cutting off top bits is assumed here */
2122 env
->fpus
&= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2123 /* (C0,C1,C3) <-- (q2,q1,q0) */
2124 env
->fpus
|= (q
&0x4) << 6; /* (C0) <-- q2 */
2125 env
->fpus
|= (q
&0x2) << 8; /* (C1) <-- q1 */
2126 env
->fpus
|= (q
&0x1) << 14; /* (C3) <-- q0 */
2128 env
->fpus
|= 0x400; /* C2 <-- 1 */
2129 fptemp
= pow(2.0, expdif
-50);
2130 fpsrcop
= (ST0
/ ST1
) / fptemp
;
2131 /* fpsrcop = integer obtained by rounding to the nearest */
2132 fpsrcop
= (fpsrcop
-floor(fpsrcop
) < ceil(fpsrcop
)-fpsrcop
)?
2133 floor(fpsrcop
): ceil(fpsrcop
);
2134 ST0
-= (ST1
* fpsrcop
* fptemp
);
2138 void helper_fprem(void)
2140 CPU86_LDouble dblq
, fpsrcop
, fptemp
;
2141 CPU86_LDoubleU fpsrcop1
, fptemp1
;
2147 fpsrcop1
.d
= fpsrcop
;
2149 expdif
= EXPD(fpsrcop1
) - EXPD(fptemp1
);
2150 if ( expdif
< 53 ) {
2151 dblq
= fpsrcop
/ fptemp
;
2152 dblq
= (dblq
< 0.0)? ceil(dblq
): floor(dblq
);
2153 ST0
= fpsrcop
- fptemp
*dblq
;
2154 q
= (int)dblq
; /* cutting off top bits is assumed here */
2155 env
->fpus
&= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2156 /* (C0,C1,C3) <-- (q2,q1,q0) */
2157 env
->fpus
|= (q
&0x4) << 6; /* (C0) <-- q2 */
2158 env
->fpus
|= (q
&0x2) << 8; /* (C1) <-- q1 */
2159 env
->fpus
|= (q
&0x1) << 14; /* (C3) <-- q0 */
2161 env
->fpus
|= 0x400; /* C2 <-- 1 */
2162 fptemp
= pow(2.0, expdif
-50);
2163 fpsrcop
= (ST0
/ ST1
) / fptemp
;
2164 /* fpsrcop = integer obtained by chopping */
2165 fpsrcop
= (fpsrcop
< 0.0)?
2166 -(floor(fabs(fpsrcop
))): floor(fpsrcop
);
2167 ST0
-= (ST1
* fpsrcop
* fptemp
);
2171 void helper_fyl2xp1(void)
2173 CPU86_LDouble fptemp
;
2176 if ((fptemp
+1.0)>0.0) {
2177 fptemp
= log(fptemp
+1.0) / log(2.0); /* log2(ST+1.0) */
2181 env
->fpus
&= (~0x4700);
2186 void helper_fsqrt(void)
2188 CPU86_LDouble fptemp
;
2192 env
->fpus
&= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2198 void helper_fsincos(void)
2200 CPU86_LDouble fptemp
;
2203 if ((fptemp
> MAXTAN
)||(fptemp
< -MAXTAN
)) {
2209 env
->fpus
&= (~0x400); /* C2 <-- 0 */
2210 /* the above code is for |arg| < 2**63 only */
2214 void helper_frndint(void)
2220 switch(env
->fpuc
& RC_MASK
) {
2223 asm("rndd %0, %1" : "=f" (a
) : "f"(a
));
2226 asm("rnddm %0, %1" : "=f" (a
) : "f"(a
));
2229 asm("rnddp %0, %1" : "=f" (a
) : "f"(a
));
2232 asm("rnddz %0, %1" : "=f" (a
) : "f"(a
));
2241 void helper_fscale(void)
2243 CPU86_LDouble fpsrcop
, fptemp
;
2246 fptemp
= pow(fpsrcop
,ST1
);
2250 void helper_fsin(void)
2252 CPU86_LDouble fptemp
;
2255 if ((fptemp
> MAXTAN
)||(fptemp
< -MAXTAN
)) {
2259 env
->fpus
&= (~0x400); /* C2 <-- 0 */
2260 /* the above code is for |arg| < 2**53 only */
2264 void helper_fcos(void)
2266 CPU86_LDouble fptemp
;
2269 if((fptemp
> MAXTAN
)||(fptemp
< -MAXTAN
)) {
2273 env
->fpus
&= (~0x400); /* C2 <-- 0 */
2274 /* the above code is for |arg5 < 2**63 only */
2278 void helper_fxam_ST0(void)
2280 CPU86_LDoubleU temp
;
2285 env
->fpus
&= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2287 env
->fpus
|= 0x200; /* C1 <-- 1 */
2289 expdif
= EXPD(temp
);
2290 if (expdif
== MAXEXPD
) {
2291 if (MANTD(temp
) == 0)
2292 env
->fpus
|= 0x500 /*Infinity*/;
2294 env
->fpus
|= 0x100 /*NaN*/;
2295 } else if (expdif
== 0) {
2296 if (MANTD(temp
) == 0)
2297 env
->fpus
|= 0x4000 /*Zero*/;
2299 env
->fpus
|= 0x4400 /*Denormal*/;
2305 void helper_fstenv(uint8_t *ptr
, int data32
)
2307 int fpus
, fptag
, exp
, i
;
2311 fpus
= (env
->fpus
& ~0x3800) | (env
->fpstt
& 0x7) << 11;
2313 for (i
=7; i
>=0; i
--) {
2315 if (env
->fptags
[i
]) {
2318 tmp
.d
= env
->fpregs
[i
];
2321 if (exp
== 0 && mant
== 0) {
2324 } else if (exp
== 0 || exp
== MAXEXPD
2325 #ifdef USE_X86LDOUBLE
2326 || (mant
& (1LL << 63)) == 0
2329 /* NaNs, infinity, denormal */
2336 stl(ptr
, env
->fpuc
);
2338 stl(ptr
+ 8, fptag
);
2345 stw(ptr
, env
->fpuc
);
2347 stw(ptr
+ 4, fptag
);
2355 void helper_fldenv(uint8_t *ptr
, int data32
)
2360 env
->fpuc
= lduw(ptr
);
2361 fpus
= lduw(ptr
+ 4);
2362 fptag
= lduw(ptr
+ 8);
2365 env
->fpuc
= lduw(ptr
);
2366 fpus
= lduw(ptr
+ 2);
2367 fptag
= lduw(ptr
+ 4);
2369 env
->fpstt
= (fpus
>> 11) & 7;
2370 env
->fpus
= fpus
& ~0x3800;
2371 for(i
= 0;i
< 7; i
++) {
2372 env
->fptags
[i
] = ((fptag
& 3) == 3);
2377 void helper_fsave(uint8_t *ptr
, int data32
)
2382 helper_fstenv(ptr
, data32
);
2384 ptr
+= (14 << data32
);
2385 for(i
= 0;i
< 8; i
++) {
2387 helper_fstt(tmp
, ptr
);
2405 void helper_frstor(uint8_t *ptr
, int data32
)
2410 helper_fldenv(ptr
, data32
);
2411 ptr
+= (14 << data32
);
2413 for(i
= 0;i
< 8; i
++) {
2414 tmp
= helper_fldt(ptr
);
2420 #if !defined(CONFIG_USER_ONLY)
2422 #define MMUSUFFIX _mmu
2423 #define GETPC() (__builtin_return_address(0))
2426 #include "softmmu_template.h"
2429 #include "softmmu_template.h"
2432 #include "softmmu_template.h"
2435 #include "softmmu_template.h"
2439 /* try to fill the TLB and return an exception if error. If retaddr is
2440 NULL, it means that the function was called in C code (i.e. not
2441 from generated code or from helper.c) */
2442 /* XXX: fix it to restore all registers */
2443 void tlb_fill(unsigned long addr
, int is_write
, int is_user
, void *retaddr
)
2445 TranslationBlock
*tb
;
2448 CPUX86State
*saved_env
;
2450 /* XXX: hack to restore env in all cases, even if not called from
2453 env
= cpu_single_env
;
2455 ret
= cpu_x86_handle_mmu_fault(env
, addr
, is_write
, is_user
, 1);
2458 /* now we have a real cpu fault */
2459 pc
= (unsigned long)retaddr
;
2460 tb
= tb_find_pc(pc
);
2462 /* the PC is inside the translated code. It means that we have
2463 a virtual CPU fault */
2464 cpu_restore_state(tb
, env
, pc
);
2467 raise_exception_err(EXCP0E_PAGE
, env
->error_code
);