4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
8 * Anthony Liguori <aliguori@us.ibm.com>
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
19 #include <linux/kvm.h>
21 #include "qemu-common.h"
26 #include "host-utils.h"
30 #ifdef CONFIG_KVM_PARA
31 #include <linux/kvm_para.h>
37 #define DPRINTF(fmt, ...) \
38 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
40 #define DPRINTF(fmt, ...) \
44 #define MSR_KVM_WALL_CLOCK 0x11
45 #define MSR_KVM_SYSTEM_TIME 0x12
47 #ifdef KVM_CAP_EXT_CPUID
49 static struct kvm_cpuid2
*try_get_cpuid(KVMState
*s
, int max
)
51 struct kvm_cpuid2
*cpuid
;
54 size
= sizeof(*cpuid
) + max
* sizeof(*cpuid
->entries
);
55 cpuid
= (struct kvm_cpuid2
*)qemu_mallocz(size
);
57 r
= kvm_ioctl(s
, KVM_GET_SUPPORTED_CPUID
, cpuid
);
58 if (r
== 0 && cpuid
->nent
>= max
) {
66 fprintf(stderr
, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
74 uint32_t kvm_arch_get_supported_cpuid(CPUState
*env
, uint32_t function
,
75 uint32_t index
, int reg
)
77 struct kvm_cpuid2
*cpuid
;
82 if (!kvm_check_extension(env
->kvm_state
, KVM_CAP_EXT_CPUID
)) {
87 while ((cpuid
= try_get_cpuid(env
->kvm_state
, max
)) == NULL
) {
91 for (i
= 0; i
< cpuid
->nent
; ++i
) {
92 if (cpuid
->entries
[i
].function
== function
&&
93 cpuid
->entries
[i
].index
== index
) {
96 ret
= cpuid
->entries
[i
].eax
;
99 ret
= cpuid
->entries
[i
].ebx
;
102 ret
= cpuid
->entries
[i
].ecx
;
105 ret
= cpuid
->entries
[i
].edx
;
108 /* KVM before 2.6.30 misreports the following features */
109 ret
|= CPUID_MTRR
| CPUID_PAT
| CPUID_MCE
| CPUID_MCA
;
112 /* On Intel, kvm returns cpuid according to the Intel spec,
113 * so add missing bits according to the AMD spec:
115 cpuid_1_edx
= kvm_arch_get_supported_cpuid(env
, 1, 0, R_EDX
);
116 ret
|= cpuid_1_edx
& 0x183f7ff;
131 uint32_t kvm_arch_get_supported_cpuid(CPUState
*env
, uint32_t function
,
132 uint32_t index
, int reg
)
139 #ifdef CONFIG_KVM_PARA
140 struct kvm_para_features
{
143 } para_features
[] = {
144 #ifdef KVM_CAP_CLOCKSOURCE
145 { KVM_CAP_CLOCKSOURCE
, KVM_FEATURE_CLOCKSOURCE
},
147 #ifdef KVM_CAP_NOP_IO_DELAY
148 { KVM_CAP_NOP_IO_DELAY
, KVM_FEATURE_NOP_IO_DELAY
},
150 #ifdef KVM_CAP_PV_MMU
151 { KVM_CAP_PV_MMU
, KVM_FEATURE_MMU_OP
},
156 static int get_para_features(CPUState
*env
)
160 for (i
= 0; i
< ARRAY_SIZE(para_features
) - 1; i
++) {
161 if (kvm_check_extension(env
->kvm_state
, para_features
[i
].cap
))
162 features
|= (1 << para_features
[i
].feature
);
169 int kvm_arch_init_vcpu(CPUState
*env
)
172 struct kvm_cpuid2 cpuid
;
173 struct kvm_cpuid_entry2 entries
[100];
174 } __attribute__((packed
)) cpuid_data
;
175 uint32_t limit
, i
, j
, cpuid_i
;
177 struct kvm_cpuid_entry2
*c
;
178 #ifdef KVM_CPUID_SIGNATURE
179 uint32_t signature
[3];
182 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
184 env
->cpuid_features
&= kvm_arch_get_supported_cpuid(env
, 1, 0, R_EDX
);
186 i
= env
->cpuid_ext_features
& CPUID_EXT_HYPERVISOR
;
187 env
->cpuid_ext_features
&= kvm_arch_get_supported_cpuid(env
, 1, 0, R_ECX
);
188 env
->cpuid_ext_features
|= i
;
190 env
->cpuid_ext2_features
&= kvm_arch_get_supported_cpuid(env
, 0x80000001,
192 env
->cpuid_ext3_features
&= kvm_arch_get_supported_cpuid(env
, 0x80000001,
197 #ifdef CONFIG_KVM_PARA
198 /* Paravirtualization CPUIDs */
199 memcpy(signature
, "KVMKVMKVM\0\0\0", 12);
200 c
= &cpuid_data
.entries
[cpuid_i
++];
201 memset(c
, 0, sizeof(*c
));
202 c
->function
= KVM_CPUID_SIGNATURE
;
204 c
->ebx
= signature
[0];
205 c
->ecx
= signature
[1];
206 c
->edx
= signature
[2];
208 c
= &cpuid_data
.entries
[cpuid_i
++];
209 memset(c
, 0, sizeof(*c
));
210 c
->function
= KVM_CPUID_FEATURES
;
211 c
->eax
= env
->cpuid_kvm_features
& get_para_features(env
);
214 cpu_x86_cpuid(env
, 0, 0, &limit
, &unused
, &unused
, &unused
);
216 for (i
= 0; i
<= limit
; i
++) {
217 c
= &cpuid_data
.entries
[cpuid_i
++];
221 /* Keep reading function 2 till all the input is received */
225 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
|
226 KVM_CPUID_FLAG_STATE_READ_NEXT
;
227 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
228 times
= c
->eax
& 0xff;
230 for (j
= 1; j
< times
; ++j
) {
231 c
= &cpuid_data
.entries
[cpuid_i
++];
233 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
;
234 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
243 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
245 cpu_x86_cpuid(env
, i
, j
, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
247 if (i
== 4 && c
->eax
== 0)
249 if (i
== 0xb && !(c
->ecx
& 0xff00))
251 if (i
== 0xd && c
->eax
== 0)
254 c
= &cpuid_data
.entries
[cpuid_i
++];
260 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
264 cpu_x86_cpuid(env
, 0x80000000, 0, &limit
, &unused
, &unused
, &unused
);
266 for (i
= 0x80000000; i
<= limit
; i
++) {
267 c
= &cpuid_data
.entries
[cpuid_i
++];
271 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
274 cpuid_data
.cpuid
.nent
= cpuid_i
;
276 return kvm_vcpu_ioctl(env
, KVM_SET_CPUID2
, &cpuid_data
);
279 void kvm_arch_reset_vcpu(CPUState
*env
)
281 env
->exception_injected
= -1;
282 env
->interrupt_injected
= -1;
283 env
->nmi_injected
= 0;
284 env
->nmi_pending
= 0;
287 static int kvm_has_msr_star(CPUState
*env
)
289 static int has_msr_star
;
293 if (has_msr_star
== 0) {
294 struct kvm_msr_list msr_list
, *kvm_msr_list
;
298 /* Obtain MSR list from KVM. These are the MSRs that we must
301 ret
= kvm_ioctl(env
->kvm_state
, KVM_GET_MSR_INDEX_LIST
, &msr_list
);
302 if (ret
< 0 && ret
!= -E2BIG
) {
305 /* Old kernel modules had a bug and could write beyond the provided
306 memory. Allocate at least a safe amount of 1K. */
307 kvm_msr_list
= qemu_mallocz(MAX(1024, sizeof(msr_list
) +
309 sizeof(msr_list
.indices
[0])));
311 kvm_msr_list
->nmsrs
= msr_list
.nmsrs
;
312 ret
= kvm_ioctl(env
->kvm_state
, KVM_GET_MSR_INDEX_LIST
, kvm_msr_list
);
316 for (i
= 0; i
< kvm_msr_list
->nmsrs
; i
++) {
317 if (kvm_msr_list
->indices
[i
] == MSR_STAR
) {
327 if (has_msr_star
== 1)
332 static int kvm_init_identity_map_page(KVMState
*s
)
334 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
336 uint64_t addr
= 0xfffbc000;
338 if (!kvm_check_extension(s
, KVM_CAP_SET_IDENTITY_MAP_ADDR
)) {
342 ret
= kvm_vm_ioctl(s
, KVM_SET_IDENTITY_MAP_ADDR
, &addr
);
344 fprintf(stderr
, "kvm_set_identity_map_addr: %s\n", strerror(ret
));
351 int kvm_arch_init(KVMState
*s
, int smp_cpus
)
355 /* create vm86 tss. KVM uses vm86 mode to emulate 16-bit code
356 * directly. In order to use vm86 mode, a TSS is needed. Since this
357 * must be part of guest physical memory, we need to allocate it. Older
358 * versions of KVM just assumed that it would be at the end of physical
359 * memory but that doesn't work with more than 4GB of memory. We simply
360 * refuse to work with those older versions of KVM. */
361 ret
= kvm_ioctl(s
, KVM_CHECK_EXTENSION
, KVM_CAP_SET_TSS_ADDR
);
363 fprintf(stderr
, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
367 /* this address is 3 pages before the bios, and the bios should present
368 * as unavaible memory. FIXME, need to ensure the e820 map deals with
372 * Tell fw_cfg to notify the BIOS to reserve the range.
374 if (e820_add_entry(0xfffbc000, 0x4000, E820_RESERVED
) < 0) {
375 perror("e820_add_entry() table is full");
378 ret
= kvm_vm_ioctl(s
, KVM_SET_TSS_ADDR
, 0xfffbd000);
383 return kvm_init_identity_map_page(s
);
386 static void set_v8086_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
388 lhs
->selector
= rhs
->selector
;
389 lhs
->base
= rhs
->base
;
390 lhs
->limit
= rhs
->limit
;
402 static void set_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
404 unsigned flags
= rhs
->flags
;
405 lhs
->selector
= rhs
->selector
;
406 lhs
->base
= rhs
->base
;
407 lhs
->limit
= rhs
->limit
;
408 lhs
->type
= (flags
>> DESC_TYPE_SHIFT
) & 15;
409 lhs
->present
= (flags
& DESC_P_MASK
) != 0;
410 lhs
->dpl
= rhs
->selector
& 3;
411 lhs
->db
= (flags
>> DESC_B_SHIFT
) & 1;
412 lhs
->s
= (flags
& DESC_S_MASK
) != 0;
413 lhs
->l
= (flags
>> DESC_L_SHIFT
) & 1;
414 lhs
->g
= (flags
& DESC_G_MASK
) != 0;
415 lhs
->avl
= (flags
& DESC_AVL_MASK
) != 0;
419 static void get_seg(SegmentCache
*lhs
, const struct kvm_segment
*rhs
)
421 lhs
->selector
= rhs
->selector
;
422 lhs
->base
= rhs
->base
;
423 lhs
->limit
= rhs
->limit
;
425 (rhs
->type
<< DESC_TYPE_SHIFT
)
426 | (rhs
->present
* DESC_P_MASK
)
427 | (rhs
->dpl
<< DESC_DPL_SHIFT
)
428 | (rhs
->db
<< DESC_B_SHIFT
)
429 | (rhs
->s
* DESC_S_MASK
)
430 | (rhs
->l
<< DESC_L_SHIFT
)
431 | (rhs
->g
* DESC_G_MASK
)
432 | (rhs
->avl
* DESC_AVL_MASK
);
435 static void kvm_getput_reg(__u64
*kvm_reg
, target_ulong
*qemu_reg
, int set
)
438 *kvm_reg
= *qemu_reg
;
440 *qemu_reg
= *kvm_reg
;
443 static int kvm_getput_regs(CPUState
*env
, int set
)
445 struct kvm_regs regs
;
449 ret
= kvm_vcpu_ioctl(env
, KVM_GET_REGS
, ®s
);
454 kvm_getput_reg(®s
.rax
, &env
->regs
[R_EAX
], set
);
455 kvm_getput_reg(®s
.rbx
, &env
->regs
[R_EBX
], set
);
456 kvm_getput_reg(®s
.rcx
, &env
->regs
[R_ECX
], set
);
457 kvm_getput_reg(®s
.rdx
, &env
->regs
[R_EDX
], set
);
458 kvm_getput_reg(®s
.rsi
, &env
->regs
[R_ESI
], set
);
459 kvm_getput_reg(®s
.rdi
, &env
->regs
[R_EDI
], set
);
460 kvm_getput_reg(®s
.rsp
, &env
->regs
[R_ESP
], set
);
461 kvm_getput_reg(®s
.rbp
, &env
->regs
[R_EBP
], set
);
463 kvm_getput_reg(®s
.r8
, &env
->regs
[8], set
);
464 kvm_getput_reg(®s
.r9
, &env
->regs
[9], set
);
465 kvm_getput_reg(®s
.r10
, &env
->regs
[10], set
);
466 kvm_getput_reg(®s
.r11
, &env
->regs
[11], set
);
467 kvm_getput_reg(®s
.r12
, &env
->regs
[12], set
);
468 kvm_getput_reg(®s
.r13
, &env
->regs
[13], set
);
469 kvm_getput_reg(®s
.r14
, &env
->regs
[14], set
);
470 kvm_getput_reg(®s
.r15
, &env
->regs
[15], set
);
473 kvm_getput_reg(®s
.rflags
, &env
->eflags
, set
);
474 kvm_getput_reg(®s
.rip
, &env
->eip
, set
);
477 ret
= kvm_vcpu_ioctl(env
, KVM_SET_REGS
, ®s
);
482 static int kvm_put_fpu(CPUState
*env
)
487 memset(&fpu
, 0, sizeof fpu
);
488 fpu
.fsw
= env
->fpus
& ~(7 << 11);
489 fpu
.fsw
|= (env
->fpstt
& 7) << 11;
491 for (i
= 0; i
< 8; ++i
)
492 fpu
.ftwx
|= (!env
->fptags
[i
]) << i
;
493 memcpy(fpu
.fpr
, env
->fpregs
, sizeof env
->fpregs
);
494 memcpy(fpu
.xmm
, env
->xmm_regs
, sizeof env
->xmm_regs
);
495 fpu
.mxcsr
= env
->mxcsr
;
497 return kvm_vcpu_ioctl(env
, KVM_SET_FPU
, &fpu
);
500 static int kvm_put_sregs(CPUState
*env
)
502 struct kvm_sregs sregs
;
504 memset(sregs
.interrupt_bitmap
, 0, sizeof(sregs
.interrupt_bitmap
));
505 if (env
->interrupt_injected
>= 0) {
506 sregs
.interrupt_bitmap
[env
->interrupt_injected
/ 64] |=
507 (uint64_t)1 << (env
->interrupt_injected
% 64);
510 if ((env
->eflags
& VM_MASK
)) {
511 set_v8086_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
512 set_v8086_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
513 set_v8086_seg(&sregs
.es
, &env
->segs
[R_ES
]);
514 set_v8086_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
515 set_v8086_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
516 set_v8086_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
518 set_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
519 set_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
520 set_seg(&sregs
.es
, &env
->segs
[R_ES
]);
521 set_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
522 set_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
523 set_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
525 if (env
->cr
[0] & CR0_PE_MASK
) {
526 /* force ss cpl to cs cpl */
527 sregs
.ss
.selector
= (sregs
.ss
.selector
& ~3) |
528 (sregs
.cs
.selector
& 3);
529 sregs
.ss
.dpl
= sregs
.ss
.selector
& 3;
533 set_seg(&sregs
.tr
, &env
->tr
);
534 set_seg(&sregs
.ldt
, &env
->ldt
);
536 sregs
.idt
.limit
= env
->idt
.limit
;
537 sregs
.idt
.base
= env
->idt
.base
;
538 sregs
.gdt
.limit
= env
->gdt
.limit
;
539 sregs
.gdt
.base
= env
->gdt
.base
;
541 sregs
.cr0
= env
->cr
[0];
542 sregs
.cr2
= env
->cr
[2];
543 sregs
.cr3
= env
->cr
[3];
544 sregs
.cr4
= env
->cr
[4];
546 sregs
.cr8
= cpu_get_apic_tpr(env
->apic_state
);
547 sregs
.apic_base
= cpu_get_apic_base(env
->apic_state
);
549 sregs
.efer
= env
->efer
;
551 return kvm_vcpu_ioctl(env
, KVM_SET_SREGS
, &sregs
);
554 static void kvm_msr_entry_set(struct kvm_msr_entry
*entry
,
555 uint32_t index
, uint64_t value
)
557 entry
->index
= index
;
561 static int kvm_put_msrs(CPUState
*env
, int level
)
564 struct kvm_msrs info
;
565 struct kvm_msr_entry entries
[100];
567 struct kvm_msr_entry
*msrs
= msr_data
.entries
;
570 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_CS
, env
->sysenter_cs
);
571 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_ESP
, env
->sysenter_esp
);
572 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_EIP
, env
->sysenter_eip
);
573 if (kvm_has_msr_star(env
))
574 kvm_msr_entry_set(&msrs
[n
++], MSR_STAR
, env
->star
);
576 /* FIXME if lm capable */
577 kvm_msr_entry_set(&msrs
[n
++], MSR_CSTAR
, env
->cstar
);
578 kvm_msr_entry_set(&msrs
[n
++], MSR_KERNELGSBASE
, env
->kernelgsbase
);
579 kvm_msr_entry_set(&msrs
[n
++], MSR_FMASK
, env
->fmask
);
580 kvm_msr_entry_set(&msrs
[n
++], MSR_LSTAR
, env
->lstar
);
582 if (level
== KVM_PUT_FULL_STATE
) {
583 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_TSC
, env
->tsc
);
584 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_SYSTEM_TIME
,
585 env
->system_time_msr
);
586 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_WALL_CLOCK
, env
->wall_clock_msr
);
589 msr_data
.info
.nmsrs
= n
;
591 return kvm_vcpu_ioctl(env
, KVM_SET_MSRS
, &msr_data
);
596 static int kvm_get_fpu(CPUState
*env
)
601 ret
= kvm_vcpu_ioctl(env
, KVM_GET_FPU
, &fpu
);
605 env
->fpstt
= (fpu
.fsw
>> 11) & 7;
608 for (i
= 0; i
< 8; ++i
)
609 env
->fptags
[i
] = !((fpu
.ftwx
>> i
) & 1);
610 memcpy(env
->fpregs
, fpu
.fpr
, sizeof env
->fpregs
);
611 memcpy(env
->xmm_regs
, fpu
.xmm
, sizeof env
->xmm_regs
);
612 env
->mxcsr
= fpu
.mxcsr
;
617 static int kvm_get_sregs(CPUState
*env
)
619 struct kvm_sregs sregs
;
623 ret
= kvm_vcpu_ioctl(env
, KVM_GET_SREGS
, &sregs
);
627 /* There can only be one pending IRQ set in the bitmap at a time, so try
628 to find it and save its number instead (-1 for none). */
629 env
->interrupt_injected
= -1;
630 for (i
= 0; i
< ARRAY_SIZE(sregs
.interrupt_bitmap
); i
++) {
631 if (sregs
.interrupt_bitmap
[i
]) {
632 bit
= ctz64(sregs
.interrupt_bitmap
[i
]);
633 env
->interrupt_injected
= i
* 64 + bit
;
638 get_seg(&env
->segs
[R_CS
], &sregs
.cs
);
639 get_seg(&env
->segs
[R_DS
], &sregs
.ds
);
640 get_seg(&env
->segs
[R_ES
], &sregs
.es
);
641 get_seg(&env
->segs
[R_FS
], &sregs
.fs
);
642 get_seg(&env
->segs
[R_GS
], &sregs
.gs
);
643 get_seg(&env
->segs
[R_SS
], &sregs
.ss
);
645 get_seg(&env
->tr
, &sregs
.tr
);
646 get_seg(&env
->ldt
, &sregs
.ldt
);
648 env
->idt
.limit
= sregs
.idt
.limit
;
649 env
->idt
.base
= sregs
.idt
.base
;
650 env
->gdt
.limit
= sregs
.gdt
.limit
;
651 env
->gdt
.base
= sregs
.gdt
.base
;
653 env
->cr
[0] = sregs
.cr0
;
654 env
->cr
[2] = sregs
.cr2
;
655 env
->cr
[3] = sregs
.cr3
;
656 env
->cr
[4] = sregs
.cr4
;
658 cpu_set_apic_base(env
->apic_state
, sregs
.apic_base
);
660 env
->efer
= sregs
.efer
;
661 //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
663 #define HFLAG_COPY_MASK ~( \
664 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
665 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
666 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
667 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
671 hflags
= (env
->segs
[R_CS
].flags
>> DESC_DPL_SHIFT
) & HF_CPL_MASK
;
672 hflags
|= (env
->cr
[0] & CR0_PE_MASK
) << (HF_PE_SHIFT
- CR0_PE_SHIFT
);
673 hflags
|= (env
->cr
[0] << (HF_MP_SHIFT
- CR0_MP_SHIFT
)) &
674 (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
);
675 hflags
|= (env
->eflags
& (HF_TF_MASK
| HF_VM_MASK
| HF_IOPL_MASK
));
676 hflags
|= (env
->cr
[4] & CR4_OSFXSR_MASK
) <<
677 (HF_OSFXSR_SHIFT
- CR4_OSFXSR_SHIFT
);
679 if (env
->efer
& MSR_EFER_LMA
) {
680 hflags
|= HF_LMA_MASK
;
683 if ((hflags
& HF_LMA_MASK
) && (env
->segs
[R_CS
].flags
& DESC_L_MASK
)) {
684 hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
686 hflags
|= (env
->segs
[R_CS
].flags
& DESC_B_MASK
) >>
687 (DESC_B_SHIFT
- HF_CS32_SHIFT
);
688 hflags
|= (env
->segs
[R_SS
].flags
& DESC_B_MASK
) >>
689 (DESC_B_SHIFT
- HF_SS32_SHIFT
);
690 if (!(env
->cr
[0] & CR0_PE_MASK
) ||
691 (env
->eflags
& VM_MASK
) ||
692 !(hflags
& HF_CS32_MASK
)) {
693 hflags
|= HF_ADDSEG_MASK
;
695 hflags
|= ((env
->segs
[R_DS
].base
|
696 env
->segs
[R_ES
].base
|
697 env
->segs
[R_SS
].base
) != 0) <<
701 env
->hflags
= (env
->hflags
& HFLAG_COPY_MASK
) | hflags
;
706 static int kvm_get_msrs(CPUState
*env
)
709 struct kvm_msrs info
;
710 struct kvm_msr_entry entries
[100];
712 struct kvm_msr_entry
*msrs
= msr_data
.entries
;
716 msrs
[n
++].index
= MSR_IA32_SYSENTER_CS
;
717 msrs
[n
++].index
= MSR_IA32_SYSENTER_ESP
;
718 msrs
[n
++].index
= MSR_IA32_SYSENTER_EIP
;
719 if (kvm_has_msr_star(env
))
720 msrs
[n
++].index
= MSR_STAR
;
721 msrs
[n
++].index
= MSR_IA32_TSC
;
723 /* FIXME lm_capable_kernel */
724 msrs
[n
++].index
= MSR_CSTAR
;
725 msrs
[n
++].index
= MSR_KERNELGSBASE
;
726 msrs
[n
++].index
= MSR_FMASK
;
727 msrs
[n
++].index
= MSR_LSTAR
;
729 msrs
[n
++].index
= MSR_KVM_SYSTEM_TIME
;
730 msrs
[n
++].index
= MSR_KVM_WALL_CLOCK
;
732 msr_data
.info
.nmsrs
= n
;
733 ret
= kvm_vcpu_ioctl(env
, KVM_GET_MSRS
, &msr_data
);
737 for (i
= 0; i
< ret
; i
++) {
738 switch (msrs
[i
].index
) {
739 case MSR_IA32_SYSENTER_CS
:
740 env
->sysenter_cs
= msrs
[i
].data
;
742 case MSR_IA32_SYSENTER_ESP
:
743 env
->sysenter_esp
= msrs
[i
].data
;
745 case MSR_IA32_SYSENTER_EIP
:
746 env
->sysenter_eip
= msrs
[i
].data
;
749 env
->star
= msrs
[i
].data
;
753 env
->cstar
= msrs
[i
].data
;
755 case MSR_KERNELGSBASE
:
756 env
->kernelgsbase
= msrs
[i
].data
;
759 env
->fmask
= msrs
[i
].data
;
762 env
->lstar
= msrs
[i
].data
;
766 env
->tsc
= msrs
[i
].data
;
768 case MSR_KVM_SYSTEM_TIME
:
769 env
->system_time_msr
= msrs
[i
].data
;
771 case MSR_KVM_WALL_CLOCK
:
772 env
->wall_clock_msr
= msrs
[i
].data
;
780 static int kvm_put_mp_state(CPUState
*env
)
782 struct kvm_mp_state mp_state
= { .mp_state
= env
->mp_state
};
784 return kvm_vcpu_ioctl(env
, KVM_SET_MP_STATE
, &mp_state
);
787 static int kvm_get_mp_state(CPUState
*env
)
789 struct kvm_mp_state mp_state
;
792 ret
= kvm_vcpu_ioctl(env
, KVM_GET_MP_STATE
, &mp_state
);
796 env
->mp_state
= mp_state
.mp_state
;
800 static int kvm_put_vcpu_events(CPUState
*env
, int level
)
802 #ifdef KVM_CAP_VCPU_EVENTS
803 struct kvm_vcpu_events events
;
805 if (!kvm_has_vcpu_events()) {
809 events
.exception
.injected
= (env
->exception_injected
>= 0);
810 events
.exception
.nr
= env
->exception_injected
;
811 events
.exception
.has_error_code
= env
->has_error_code
;
812 events
.exception
.error_code
= env
->error_code
;
814 events
.interrupt
.injected
= (env
->interrupt_injected
>= 0);
815 events
.interrupt
.nr
= env
->interrupt_injected
;
816 events
.interrupt
.soft
= env
->soft_interrupt
;
818 events
.nmi
.injected
= env
->nmi_injected
;
819 events
.nmi
.pending
= env
->nmi_pending
;
820 events
.nmi
.masked
= !!(env
->hflags2
& HF2_NMI_MASK
);
822 events
.sipi_vector
= env
->sipi_vector
;
825 if (level
>= KVM_PUT_RESET_STATE
) {
827 KVM_VCPUEVENT_VALID_NMI_PENDING
| KVM_VCPUEVENT_VALID_SIPI_VECTOR
;
830 return kvm_vcpu_ioctl(env
, KVM_SET_VCPU_EVENTS
, &events
);
836 static int kvm_get_vcpu_events(CPUState
*env
)
838 #ifdef KVM_CAP_VCPU_EVENTS
839 struct kvm_vcpu_events events
;
842 if (!kvm_has_vcpu_events()) {
846 ret
= kvm_vcpu_ioctl(env
, KVM_GET_VCPU_EVENTS
, &events
);
850 env
->exception_injected
=
851 events
.exception
.injected
? events
.exception
.nr
: -1;
852 env
->has_error_code
= events
.exception
.has_error_code
;
853 env
->error_code
= events
.exception
.error_code
;
855 env
->interrupt_injected
=
856 events
.interrupt
.injected
? events
.interrupt
.nr
: -1;
857 env
->soft_interrupt
= events
.interrupt
.soft
;
859 env
->nmi_injected
= events
.nmi
.injected
;
860 env
->nmi_pending
= events
.nmi
.pending
;
861 if (events
.nmi
.masked
) {
862 env
->hflags2
|= HF2_NMI_MASK
;
864 env
->hflags2
&= ~HF2_NMI_MASK
;
867 env
->sipi_vector
= events
.sipi_vector
;
873 static int kvm_guest_debug_workarounds(CPUState
*env
)
876 #ifdef KVM_CAP_SET_GUEST_DEBUG
877 unsigned long reinject_trap
= 0;
879 if (!kvm_has_vcpu_events()) {
880 if (env
->exception_injected
== 1) {
881 reinject_trap
= KVM_GUESTDBG_INJECT_DB
;
882 } else if (env
->exception_injected
== 3) {
883 reinject_trap
= KVM_GUESTDBG_INJECT_BP
;
885 env
->exception_injected
= -1;
889 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
890 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
891 * by updating the debug state once again if single-stepping is on.
892 * Another reason to call kvm_update_guest_debug here is a pending debug
893 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
894 * reinject them via SET_GUEST_DEBUG.
897 (!kvm_has_robust_singlestep() && env
->singlestep_enabled
)) {
898 ret
= kvm_update_guest_debug(env
, reinject_trap
);
900 #endif /* KVM_CAP_SET_GUEST_DEBUG */
904 static int kvm_put_debugregs(CPUState
*env
)
906 #ifdef KVM_CAP_DEBUGREGS
907 struct kvm_debugregs dbgregs
;
910 if (!kvm_has_debugregs()) {
914 for (i
= 0; i
< 4; i
++) {
915 dbgregs
.db
[i
] = env
->dr
[i
];
917 dbgregs
.dr6
= env
->dr
[6];
918 dbgregs
.dr7
= env
->dr
[7];
921 return kvm_vcpu_ioctl(env
, KVM_SET_DEBUGREGS
, &dbgregs
);
927 static int kvm_get_debugregs(CPUState
*env
)
929 #ifdef KVM_CAP_DEBUGREGS
930 struct kvm_debugregs dbgregs
;
933 if (!kvm_has_debugregs()) {
937 ret
= kvm_vcpu_ioctl(env
, KVM_GET_DEBUGREGS
, &dbgregs
);
941 for (i
= 0; i
< 4; i
++) {
942 env
->dr
[i
] = dbgregs
.db
[i
];
944 env
->dr
[4] = env
->dr
[6] = dbgregs
.dr6
;
945 env
->dr
[5] = env
->dr
[7] = dbgregs
.dr7
;
951 int kvm_arch_put_registers(CPUState
*env
, int level
)
955 assert(cpu_is_stopped(env
) || qemu_cpu_self(env
));
957 ret
= kvm_getput_regs(env
, 1);
961 ret
= kvm_put_fpu(env
);
965 ret
= kvm_put_sregs(env
);
969 ret
= kvm_put_msrs(env
, level
);
973 if (level
>= KVM_PUT_RESET_STATE
) {
974 ret
= kvm_put_mp_state(env
);
979 ret
= kvm_put_vcpu_events(env
, level
);
984 ret
= kvm_guest_debug_workarounds(env
);
988 ret
= kvm_put_debugregs(env
);
995 int kvm_arch_get_registers(CPUState
*env
)
999 assert(cpu_is_stopped(env
) || qemu_cpu_self(env
));
1001 ret
= kvm_getput_regs(env
, 0);
1005 ret
= kvm_get_fpu(env
);
1009 ret
= kvm_get_sregs(env
);
1013 ret
= kvm_get_msrs(env
);
1017 ret
= kvm_get_mp_state(env
);
1021 ret
= kvm_get_vcpu_events(env
);
1025 ret
= kvm_get_debugregs(env
);
1032 int kvm_arch_pre_run(CPUState
*env
, struct kvm_run
*run
)
1034 /* Try to inject an interrupt if the guest can accept it */
1035 if (run
->ready_for_interrupt_injection
&&
1036 (env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1037 (env
->eflags
& IF_MASK
)) {
1040 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
1041 irq
= cpu_get_pic_interrupt(env
);
1043 struct kvm_interrupt intr
;
1046 DPRINTF("injected interrupt %d\n", irq
);
1047 kvm_vcpu_ioctl(env
, KVM_INTERRUPT
, &intr
);
1051 /* If we have an interrupt but the guest is not ready to receive an
1052 * interrupt, request an interrupt window exit. This will
1053 * cause a return to userspace as soon as the guest is ready to
1054 * receive interrupts. */
1055 if ((env
->interrupt_request
& CPU_INTERRUPT_HARD
))
1056 run
->request_interrupt_window
= 1;
1058 run
->request_interrupt_window
= 0;
1060 DPRINTF("setting tpr\n");
1061 run
->cr8
= cpu_get_apic_tpr(env
->apic_state
);
1066 int kvm_arch_post_run(CPUState
*env
, struct kvm_run
*run
)
1069 env
->eflags
|= IF_MASK
;
1071 env
->eflags
&= ~IF_MASK
;
1073 cpu_set_apic_tpr(env
->apic_state
, run
->cr8
);
1074 cpu_set_apic_base(env
->apic_state
, run
->apic_base
);
1079 int kvm_arch_process_irqchip_events(CPUState
*env
)
1081 if (env
->interrupt_request
& CPU_INTERRUPT_INIT
) {
1082 kvm_cpu_synchronize_state(env
);
1084 env
->exception_index
= EXCP_HALTED
;
1087 if (env
->interrupt_request
& CPU_INTERRUPT_SIPI
) {
1088 kvm_cpu_synchronize_state(env
);
1095 static int kvm_handle_halt(CPUState
*env
)
1097 if (!((env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1098 (env
->eflags
& IF_MASK
)) &&
1099 !(env
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
1101 env
->exception_index
= EXCP_HLT
;
1108 int kvm_arch_handle_exit(CPUState
*env
, struct kvm_run
*run
)
1112 switch (run
->exit_reason
) {
1114 DPRINTF("handle_hlt\n");
1115 ret
= kvm_handle_halt(env
);
1122 #ifdef KVM_CAP_SET_GUEST_DEBUG
1123 int kvm_arch_insert_sw_breakpoint(CPUState
*env
, struct kvm_sw_breakpoint
*bp
)
1125 static const uint8_t int3
= 0xcc;
1127 if (cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 0) ||
1128 cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&int3
, 1, 1))
1133 int kvm_arch_remove_sw_breakpoint(CPUState
*env
, struct kvm_sw_breakpoint
*bp
)
1137 if (cpu_memory_rw_debug(env
, bp
->pc
, &int3
, 1, 0) || int3
!= 0xcc ||
1138 cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 1))
1149 static int nb_hw_breakpoint
;
1151 static int find_hw_breakpoint(target_ulong addr
, int len
, int type
)
1155 for (n
= 0; n
< nb_hw_breakpoint
; n
++)
1156 if (hw_breakpoint
[n
].addr
== addr
&& hw_breakpoint
[n
].type
== type
&&
1157 (hw_breakpoint
[n
].len
== len
|| len
== -1))
1162 int kvm_arch_insert_hw_breakpoint(target_ulong addr
,
1163 target_ulong len
, int type
)
1166 case GDB_BREAKPOINT_HW
:
1169 case GDB_WATCHPOINT_WRITE
:
1170 case GDB_WATCHPOINT_ACCESS
:
1177 if (addr
& (len
- 1))
1188 if (nb_hw_breakpoint
== 4)
1191 if (find_hw_breakpoint(addr
, len
, type
) >= 0)
1194 hw_breakpoint
[nb_hw_breakpoint
].addr
= addr
;
1195 hw_breakpoint
[nb_hw_breakpoint
].len
= len
;
1196 hw_breakpoint
[nb_hw_breakpoint
].type
= type
;
1202 int kvm_arch_remove_hw_breakpoint(target_ulong addr
,
1203 target_ulong len
, int type
)
1207 n
= find_hw_breakpoint(addr
, (type
== GDB_BREAKPOINT_HW
) ? 1 : len
, type
);
1212 hw_breakpoint
[n
] = hw_breakpoint
[nb_hw_breakpoint
];
1217 void kvm_arch_remove_all_hw_breakpoints(void)
1219 nb_hw_breakpoint
= 0;
1222 static CPUWatchpoint hw_watchpoint
;
1224 int kvm_arch_debug(struct kvm_debug_exit_arch
*arch_info
)
1229 if (arch_info
->exception
== 1) {
1230 if (arch_info
->dr6
& (1 << 14)) {
1231 if (cpu_single_env
->singlestep_enabled
)
1234 for (n
= 0; n
< 4; n
++)
1235 if (arch_info
->dr6
& (1 << n
))
1236 switch ((arch_info
->dr7
>> (16 + n
*4)) & 0x3) {
1242 cpu_single_env
->watchpoint_hit
= &hw_watchpoint
;
1243 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
1244 hw_watchpoint
.flags
= BP_MEM_WRITE
;
1248 cpu_single_env
->watchpoint_hit
= &hw_watchpoint
;
1249 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
1250 hw_watchpoint
.flags
= BP_MEM_ACCESS
;
1254 } else if (kvm_find_sw_breakpoint(cpu_single_env
, arch_info
->pc
))
1258 cpu_synchronize_state(cpu_single_env
);
1259 assert(cpu_single_env
->exception_injected
== -1);
1261 cpu_single_env
->exception_injected
= arch_info
->exception
;
1262 cpu_single_env
->has_error_code
= 0;
1268 void kvm_arch_update_guest_debug(CPUState
*env
, struct kvm_guest_debug
*dbg
)
1270 const uint8_t type_code
[] = {
1271 [GDB_BREAKPOINT_HW
] = 0x0,
1272 [GDB_WATCHPOINT_WRITE
] = 0x1,
1273 [GDB_WATCHPOINT_ACCESS
] = 0x3
1275 const uint8_t len_code
[] = {
1276 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1280 if (kvm_sw_breakpoints_active(env
))
1281 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
;
1283 if (nb_hw_breakpoint
> 0) {
1284 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_HW_BP
;
1285 dbg
->arch
.debugreg
[7] = 0x0600;
1286 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
1287 dbg
->arch
.debugreg
[n
] = hw_breakpoint
[n
].addr
;
1288 dbg
->arch
.debugreg
[7] |= (2 << (n
* 2)) |
1289 (type_code
[hw_breakpoint
[n
].type
] << (16 + n
*4)) |
1290 (len_code
[hw_breakpoint
[n
].len
] << (18 + n
*4));
1294 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1296 bool kvm_arch_stop_on_emulation_error(CPUState
*env
)
1298 return !(env
->cr
[0] & CR0_PE_MASK
) ||
1299 ((env
->segs
[R_CS
].selector
& 3) != 3);