target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18
  19 #include <linux/kvm.h>
  20
  21 #include "qemu-common.h"
  22 #include "sysemu.h"
  23 #include "kvm.h"
  24 #include "cpu.h"
  25 #include "gdbstub.h"
  26 #include "host-utils.h"
  27 #include "hw/pc.h"
  28 #include "ioport.h"
  29
  30 #ifdef CONFIG_KVM_PARA
  31 #include <linux/kvm_para.h>
  32 #endif
  33 //
  34 //#define DEBUG_KVM
  35
  36 #ifdef DEBUG_KVM
  37 #define DPRINTF(fmt, ...) \
  38     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  39 #else
  40 #define DPRINTF(fmt, ...) \
  41     do { } while (0)
  42 #endif
  43
  44 #define MSR_KVM_WALL_CLOCK  0x11
  45 #define MSR_KVM_SYSTEM_TIME 0x12
  46
  47 #ifdef KVM_CAP_EXT_CPUID
  48
  49 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  50 {
  51     struct kvm_cpuid2 *cpuid;
  52     int r, size;
  53
  54     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  55     cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
  56     cpuid->nent = max;
  57     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  58     if (r == 0 && cpuid->nent >= max) {
  59         r = -E2BIG;
  60     }
  61     if (r < 0) {
  62         if (r == -E2BIG) {
  63             qemu_free(cpuid);
  64             return NULL;
  65         } else {
  66             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  67                     strerror(-r));
  68             exit(1);
  69         }
  70     }
  71     return cpuid;
  72 }
  73
  74 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
  75                                       uint32_t index, int reg)
  76 {
  77     struct kvm_cpuid2 *cpuid;
  78     int i, max;
  79     uint32_t ret = 0;
  80     uint32_t cpuid_1_edx;
  81
  82     if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
  83         return -1U;
  84     }
  85
  86     max = 1;
  87     while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
  88         max *= 2;
  89     }
  90
  91     for (i = 0; i < cpuid->nent; ++i) {
  92         if (cpuid->entries[i].function == function &&
  93             cpuid->entries[i].index == index) {
  94             switch (reg) {
  95             case R_EAX:
  96                 ret = cpuid->entries[i].eax;
  97                 break;
  98             case R_EBX:
  99                 ret = cpuid->entries[i].ebx;
 100                 break;
 101             case R_ECX:
 102                 ret = cpuid->entries[i].ecx;
 103                 break;
 104             case R_EDX:
 105                 ret = cpuid->entries[i].edx;
 106                 switch (function) {
 107                 case 1:
 108                     /* KVM before 2.6.30 misreports the following features */
 109                     ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 110                     break;
 111                 case 0x80000001:
 112                     /* On Intel, kvm returns cpuid according to the Intel spec,
 113                      * so add missing bits according to the AMD spec:
 114                      */
 115                     cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 116                     ret |= cpuid_1_edx & 0x183f7ff;
 117                     break;
 118                 }
 119                 break;
 120             }
 121         }
 122     }
 123
 124     qemu_free(cpuid);
 125
 126     return ret;
 127 }
 128
 129 #else
 130
 131 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
 132                                       uint32_t index, int reg)
 133 {
 134     return -1U;
 135 }
 136
 137 #endif
 138
 139 #ifdef CONFIG_KVM_PARA
 140 struct kvm_para_features {
 141         int cap;
 142         int feature;
 143 } para_features[] = {
 144 #ifdef KVM_CAP_CLOCKSOURCE
 145         { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 146 #endif
 147 #ifdef KVM_CAP_NOP_IO_DELAY
 148         { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 149 #endif
 150 #ifdef KVM_CAP_PV_MMU
 151         { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 152 #endif
 153         { -1, -1 }
 154 };
 155
 156 static int get_para_features(CPUState *env)
 157 {
 158         int i, features = 0;
 159
 160         for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 161                 if (kvm_check_extension(env->kvm_state, para_features[i].cap))
 162                         features |= (1 << para_features[i].feature);
 163         }
 164
 165         return features;
 166 }
 167 #endif
 168
 169 int kvm_arch_init_vcpu(CPUState *env)
 170 {
 171     struct {
 172         struct kvm_cpuid2 cpuid;
 173         struct kvm_cpuid_entry2 entries[100];
 174     } __attribute__((packed)) cpuid_data;
 175     uint32_t limit, i, j, cpuid_i;
 176     uint32_t unused;
 177     struct kvm_cpuid_entry2 *c;
 178 #ifdef KVM_CPUID_SIGNATURE
 179     uint32_t signature[3];
 180 #endif
 181
 182     env->mp_state = KVM_MP_STATE_RUNNABLE;
 183
 184     env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 185
 186     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 187     env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX);
 188     env->cpuid_ext_features |= i;
 189
 190     env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 191                                                              0, R_EDX);
 192     env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 193                                                              0, R_ECX);
 194
 195     cpuid_i = 0;
 196
 197 #ifdef CONFIG_KVM_PARA
 198     /* Paravirtualization CPUIDs */
 199     memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 200     c = &cpuid_data.entries[cpuid_i++];
 201     memset(c, 0, sizeof(*c));
 202     c->function = KVM_CPUID_SIGNATURE;
 203     c->eax = 0;
 204     c->ebx = signature[0];
 205     c->ecx = signature[1];
 206     c->edx = signature[2];
 207
 208     c = &cpuid_data.entries[cpuid_i++];
 209     memset(c, 0, sizeof(*c));
 210     c->function = KVM_CPUID_FEATURES;
 211     c->eax = env->cpuid_kvm_features & get_para_features(env);
 212 #endif
 213
 214     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 215
 216     for (i = 0; i <= limit; i++) {
 217         c = &cpuid_data.entries[cpuid_i++];
 218
 219         switch (i) {
 220         case 2: {
 221             /* Keep reading function 2 till all the input is received */
 222             int times;
 223
 224             c->function = i;
 225             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 226                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 227             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 228             times = c->eax & 0xff;
 229
 230             for (j = 1; j < times; ++j) {
 231                 c = &cpuid_data.entries[cpuid_i++];
 232                 c->function = i;
 233                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 234                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 235             }
 236             break;
 237         }
 238         case 4:
 239         case 0xb:
 240         case 0xd:
 241             for (j = 0; ; j++) {
 242                 c->function = i;
 243                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 244                 c->index = j;
 245                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 246
 247                 if (i == 4 && c->eax == 0)
 248                     break;
 249                 if (i == 0xb && !(c->ecx & 0xff00))
 250                     break;
 251                 if (i == 0xd && c->eax == 0)
 252                     break;
 253
 254                 c = &cpuid_data.entries[cpuid_i++];
 255             }
 256             break;
 257         default:
 258             c->function = i;
 259             c->flags = 0;
 260             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 261             break;
 262         }
 263     }
 264     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 265
 266     for (i = 0x80000000; i <= limit; i++) {
 267         c = &cpuid_data.entries[cpuid_i++];
 268
 269         c->function = i;
 270         c->flags = 0;
 271         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 272     }
 273
 274     cpuid_data.cpuid.nent = cpuid_i;
 275
 276     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 277 }
 278
 279 void kvm_arch_reset_vcpu(CPUState *env)
 280 {
 281     env->exception_injected = -1;
 282     env->interrupt_injected = -1;
 283     env->nmi_injected = 0;
 284     env->nmi_pending = 0;
 285     if (kvm_irqchip_in_kernel()) {
 286         env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE :
 287                                           KVM_MP_STATE_UNINITIALIZED;
 288     } else {
 289         env->mp_state = KVM_MP_STATE_RUNNABLE;
 290     }
 291 }
 292
 293 static int kvm_has_msr_star(CPUState *env)
 294 {
 295     static int has_msr_star;
 296     int ret;
 297
 298     /* first time */
 299     if (has_msr_star == 0) {
 300         struct kvm_msr_list msr_list, *kvm_msr_list;
 301
 302         has_msr_star = -1;
 303
 304         /* Obtain MSR list from KVM.  These are the MSRs that we must
 305          * save/restore */
 306         msr_list.nmsrs = 0;
 307         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
 308         if (ret < 0 && ret != -E2BIG) {
 309             return 0;
 310         }
 311         /* Old kernel modules had a bug and could write beyond the provided
 312            memory. Allocate at least a safe amount of 1K. */
 313         kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
 314                                               msr_list.nmsrs *
 315                                               sizeof(msr_list.indices[0])));
 316
 317         kvm_msr_list->nmsrs = msr_list.nmsrs;
 318         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 319         if (ret >= 0) {
 320             int i;
 321
 322             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 323                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 324                     has_msr_star = 1;
 325                     break;
 326                 }
 327             }
 328         }
 329
 330         free(kvm_msr_list);
 331     }
 332
 333     if (has_msr_star == 1)
 334         return 1;
 335     return 0;
 336 }
 337
 338 static int kvm_init_identity_map_page(KVMState *s)
 339 {
 340 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
 341     int ret;
 342     uint64_t addr = 0xfffbc000;
 343
 344     if (!kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 345         return 0;
 346     }
 347
 348     ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &addr);
 349     if (ret < 0) {
 350         fprintf(stderr, "kvm_set_identity_map_addr: %s\n", strerror(ret));
 351         return ret;
 352     }
 353 #endif
 354     return 0;
 355 }
 356
 357 int kvm_arch_init(KVMState *s, int smp_cpus)
 358 {
 359     int ret;
 360
 361     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 362      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 363      * must be part of guest physical memory, we need to allocate it.  Older
 364      * versions of KVM just assumed that it would be at the end of physical
 365      * memory but that doesn't work with more than 4GB of memory.  We simply
 366      * refuse to work with those older versions of KVM. */
 367     ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
 368     if (ret <= 0) {
 369         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 370         return ret;
 371     }
 372
 373     /* this address is 3 pages before the bios, and the bios should present
 374      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 375      * this?
 376      */
 377     /*
 378      * Tell fw_cfg to notify the BIOS to reserve the range.
 379      */
 380     if (e820_add_entry(0xfffbc000, 0x4000, E820_RESERVED) < 0) {
 381         perror("e820_add_entry() table is full");
 382         exit(1);
 383     }
 384     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 385     if (ret < 0) {
 386         return ret;
 387     }
 388
 389     return kvm_init_identity_map_page(s);
 390 }
 391
 392 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 393 {
 394     lhs->selector = rhs->selector;
 395     lhs->base = rhs->base;
 396     lhs->limit = rhs->limit;
 397     lhs->type = 3;
 398     lhs->present = 1;
 399     lhs->dpl = 3;
 400     lhs->db = 0;
 401     lhs->s = 1;
 402     lhs->l = 0;
 403     lhs->g = 0;
 404     lhs->avl = 0;
 405     lhs->unusable = 0;
 406 }
 407
 408 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 409 {
 410     unsigned flags = rhs->flags;
 411     lhs->selector = rhs->selector;
 412     lhs->base = rhs->base;
 413     lhs->limit = rhs->limit;
 414     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 415     lhs->present = (flags & DESC_P_MASK) != 0;
 416     lhs->dpl = rhs->selector & 3;
 417     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 418     lhs->s = (flags & DESC_S_MASK) != 0;
 419     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 420     lhs->g = (flags & DESC_G_MASK) != 0;
 421     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 422     lhs->unusable = 0;
 423 }
 424
 425 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 426 {
 427     lhs->selector = rhs->selector;
 428     lhs->base = rhs->base;
 429     lhs->limit = rhs->limit;
 430     lhs->flags =
 431         (rhs->type << DESC_TYPE_SHIFT)
 432         | (rhs->present * DESC_P_MASK)
 433         | (rhs->dpl << DESC_DPL_SHIFT)
 434         | (rhs->db << DESC_B_SHIFT)
 435         | (rhs->s * DESC_S_MASK)
 436         | (rhs->l << DESC_L_SHIFT)
 437         | (rhs->g * DESC_G_MASK)
 438         | (rhs->avl * DESC_AVL_MASK);
 439 }
 440
 441 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 442 {
 443     if (set)
 444         *kvm_reg = *qemu_reg;
 445     else
 446         *qemu_reg = *kvm_reg;
 447 }
 448
 449 static int kvm_getput_regs(CPUState *env, int set)
 450 {
 451     struct kvm_regs regs;
 452     int ret = 0;
 453
 454     if (!set) {
 455         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 456         if (ret < 0)
 457             return ret;
 458     }
 459
 460     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 461     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 462     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 463     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 464     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 465     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 466     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 467     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 468 #ifdef TARGET_X86_64
 469     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 470     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 471     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 472     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 473     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 474     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 475     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 476     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 477 #endif
 478
 479     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 480     kvm_getput_reg(&regs.rip, &env->eip, set);
 481
 482     if (set)
 483         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 484
 485     return ret;
 486 }
 487
 488 static int kvm_put_fpu(CPUState *env)
 489 {
 490     struct kvm_fpu fpu;
 491     int i;
 492
 493     memset(&fpu, 0, sizeof fpu);
 494     fpu.fsw = env->fpus & ~(7 << 11);
 495     fpu.fsw |= (env->fpstt & 7) << 11;
 496     fpu.fcw = env->fpuc;
 497     for (i = 0; i < 8; ++i)
 498         fpu.ftwx |= (!env->fptags[i]) << i;
 499     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 500     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 501     fpu.mxcsr = env->mxcsr;
 502
 503     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 504 }
 505
 506 #ifdef KVM_CAP_XSAVE
 507 #define XSAVE_CWD_RIP     2
 508 #define XSAVE_CWD_RDP     4
 509 #define XSAVE_MXCSR       6
 510 #define XSAVE_ST_SPACE    8
 511 #define XSAVE_XMM_SPACE   40
 512 #define XSAVE_XSTATE_BV   128
 513 #define XSAVE_YMMH_SPACE  144
 514 #endif
 515
 516 static int kvm_put_xsave(CPUState *env)
 517 {
 518 #ifdef KVM_CAP_XSAVE
 519     int i;
 520     struct kvm_xsave* xsave;
 521     uint16_t cwd, swd, twd, fop;
 522
 523     if (!kvm_has_xsave())
 524         return kvm_put_fpu(env);
 525
 526     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 527     memset(xsave, 0, sizeof(struct kvm_xsave));
 528     cwd = swd = twd = fop = 0;
 529     swd = env->fpus & ~(7 << 11);
 530     swd |= (env->fpstt & 7) << 11;
 531     cwd = env->fpuc;
 532     for (i = 0; i < 8; ++i)
 533         twd |= (!env->fptags[i]) << i;
 534     xsave->region[0] = (uint32_t)(swd << 16) + cwd;
 535     xsave->region[1] = (uint32_t)(fop << 16) + twd;
 536     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 537             sizeof env->fpregs);
 538     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 539             sizeof env->xmm_regs);
 540     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 541     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 542     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 543             sizeof env->ymmh_regs);
 544     return kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
 545 #else
 546     return kvm_put_fpu(env);
 547 #endif
 548 }
 549
 550 static int kvm_put_xcrs(CPUState *env)
 551 {
 552 #ifdef KVM_CAP_XCRS
 553     struct kvm_xcrs xcrs;
 554
 555     if (!kvm_has_xcrs())
 556         return 0;
 557
 558     xcrs.nr_xcrs = 1;
 559     xcrs.flags = 0;
 560     xcrs.xcrs[0].xcr = 0;
 561     xcrs.xcrs[0].value = env->xcr0;
 562     return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
 563 #else
 564     return 0;
 565 #endif
 566 }
 567
 568 static int kvm_put_sregs(CPUState *env)
 569 {
 570     struct kvm_sregs sregs;
 571
 572     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 573     if (env->interrupt_injected >= 0) {
 574         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 575                 (uint64_t)1 << (env->interrupt_injected % 64);
 576     }
 577
 578     if ((env->eflags & VM_MASK)) {
 579             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 580             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 581             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 582             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 583             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 584             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 585     } else {
 586             set_seg(&sregs.cs, &env->segs[R_CS]);
 587             set_seg(&sregs.ds, &env->segs[R_DS]);
 588             set_seg(&sregs.es, &env->segs[R_ES]);
 589             set_seg(&sregs.fs, &env->segs[R_FS]);
 590             set_seg(&sregs.gs, &env->segs[R_GS]);
 591             set_seg(&sregs.ss, &env->segs[R_SS]);
 592
 593             if (env->cr[0] & CR0_PE_MASK) {
 594                 /* force ss cpl to cs cpl */
 595                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 596                         (sregs.cs.selector & 3);
 597                 sregs.ss.dpl = sregs.ss.selector & 3;
 598             }
 599     }
 600
 601     set_seg(&sregs.tr, &env->tr);
 602     set_seg(&sregs.ldt, &env->ldt);
 603
 604     sregs.idt.limit = env->idt.limit;
 605     sregs.idt.base = env->idt.base;
 606     sregs.gdt.limit = env->gdt.limit;
 607     sregs.gdt.base = env->gdt.base;
 608
 609     sregs.cr0 = env->cr[0];
 610     sregs.cr2 = env->cr[2];
 611     sregs.cr3 = env->cr[3];
 612     sregs.cr4 = env->cr[4];
 613
 614     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
 615     sregs.apic_base = cpu_get_apic_base(env->apic_state);
 616
 617     sregs.efer = env->efer;
 618
 619     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 620 }
 621
 622 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 623                               uint32_t index, uint64_t value)
 624 {
 625     entry->index = index;
 626     entry->data = value;
 627 }
 628
 629 static int kvm_put_msrs(CPUState *env, int level)
 630 {
 631     struct {
 632         struct kvm_msrs info;
 633         struct kvm_msr_entry entries[100];
 634     } msr_data;
 635     struct kvm_msr_entry *msrs = msr_data.entries;
 636     int n = 0;
 637
 638     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 639     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 640     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 641     if (kvm_has_msr_star(env))
 642         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 643 #ifdef TARGET_X86_64
 644     /* FIXME if lm capable */
 645     kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 646     kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 647     kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 648     kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 649 #endif
 650     if (level == KVM_PUT_FULL_STATE) {
 651         kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 652         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
 653                           env->system_time_msr);
 654         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
 655     }
 656
 657     msr_data.info.nmsrs = n;
 658
 659     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 660
 661 }
 662
 663
 664 static int kvm_get_fpu(CPUState *env)
 665 {
 666     struct kvm_fpu fpu;
 667     int i, ret;
 668
 669     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 670     if (ret < 0)
 671         return ret;
 672
 673     env->fpstt = (fpu.fsw >> 11) & 7;
 674     env->fpus = fpu.fsw;
 675     env->fpuc = fpu.fcw;
 676     for (i = 0; i < 8; ++i)
 677         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 678     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 679     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 680     env->mxcsr = fpu.mxcsr;
 681
 682     return 0;
 683 }
 684
 685 static int kvm_get_xsave(CPUState *env)
 686 {
 687 #ifdef KVM_CAP_XSAVE
 688     struct kvm_xsave* xsave;
 689     int ret, i;
 690     uint16_t cwd, swd, twd, fop;
 691
 692     if (!kvm_has_xsave())
 693         return kvm_get_fpu(env);
 694
 695     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 696     ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
 697     if (ret < 0)
 698         return ret;
 699
 700     cwd = (uint16_t)xsave->region[0];
 701     swd = (uint16_t)(xsave->region[0] >> 16);
 702     twd = (uint16_t)xsave->region[1];
 703     fop = (uint16_t)(xsave->region[1] >> 16);
 704     env->fpstt = (swd >> 11) & 7;
 705     env->fpus = swd;
 706     env->fpuc = cwd;
 707     for (i = 0; i < 8; ++i)
 708         env->fptags[i] = !((twd >> i) & 1);
 709     env->mxcsr = xsave->region[XSAVE_MXCSR];
 710     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
 711             sizeof env->fpregs);
 712     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
 713             sizeof env->xmm_regs);
 714     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
 715     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
 716             sizeof env->ymmh_regs);
 717     return 0;
 718 #else
 719     return kvm_get_fpu(env);
 720 #endif
 721 }
 722
 723 static int kvm_get_xcrs(CPUState *env)
 724 {
 725 #ifdef KVM_CAP_XCRS
 726     int i, ret;
 727     struct kvm_xcrs xcrs;
 728
 729     if (!kvm_has_xcrs())
 730         return 0;
 731
 732     ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
 733     if (ret < 0)
 734         return ret;
 735
 736     for (i = 0; i < xcrs.nr_xcrs; i++)
 737         /* Only support xcr0 now */
 738         if (xcrs.xcrs[0].xcr == 0) {
 739             env->xcr0 = xcrs.xcrs[0].value;
 740             break;
 741         }
 742     return 0;
 743 #else
 744     return 0;
 745 #endif
 746 }
 747
 748 static int kvm_get_sregs(CPUState *env)
 749 {
 750     struct kvm_sregs sregs;
 751     uint32_t hflags;
 752     int bit, i, ret;
 753
 754     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 755     if (ret < 0)
 756         return ret;
 757
 758     /* There can only be one pending IRQ set in the bitmap at a time, so try
 759        to find it and save its number instead (-1 for none). */
 760     env->interrupt_injected = -1;
 761     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
 762         if (sregs.interrupt_bitmap[i]) {
 763             bit = ctz64(sregs.interrupt_bitmap[i]);
 764             env->interrupt_injected = i * 64 + bit;
 765             break;
 766         }
 767     }
 768
 769     get_seg(&env->segs[R_CS], &sregs.cs);
 770     get_seg(&env->segs[R_DS], &sregs.ds);
 771     get_seg(&env->segs[R_ES], &sregs.es);
 772     get_seg(&env->segs[R_FS], &sregs.fs);
 773     get_seg(&env->segs[R_GS], &sregs.gs);
 774     get_seg(&env->segs[R_SS], &sregs.ss);
 775
 776     get_seg(&env->tr, &sregs.tr);
 777     get_seg(&env->ldt, &sregs.ldt);
 778
 779     env->idt.limit = sregs.idt.limit;
 780     env->idt.base = sregs.idt.base;
 781     env->gdt.limit = sregs.gdt.limit;
 782     env->gdt.base = sregs.gdt.base;
 783
 784     env->cr[0] = sregs.cr0;
 785     env->cr[2] = sregs.cr2;
 786     env->cr[3] = sregs.cr3;
 787     env->cr[4] = sregs.cr4;
 788
 789     cpu_set_apic_base(env->apic_state, sregs.apic_base);
 790
 791     env->efer = sregs.efer;
 792     //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
 793
 794 #define HFLAG_COPY_MASK ~( \
 795                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 796                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 797                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 798                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 799
 800
 801
 802     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 803     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 804     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 805             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 806     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 807     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 808             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 809
 810     if (env->efer & MSR_EFER_LMA) {
 811         hflags |= HF_LMA_MASK;
 812     }
 813
 814     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 815         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 816     } else {
 817         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 818                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 819         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 820                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 821         if (!(env->cr[0] & CR0_PE_MASK) ||
 822                    (env->eflags & VM_MASK) ||
 823                    !(hflags & HF_CS32_MASK)) {
 824                 hflags |= HF_ADDSEG_MASK;
 825             } else {
 826                 hflags |= ((env->segs[R_DS].base |
 827                                 env->segs[R_ES].base |
 828                                 env->segs[R_SS].base) != 0) <<
 829                     HF_ADDSEG_SHIFT;
 830             }
 831     }
 832     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 833
 834     return 0;
 835 }
 836
 837 static int kvm_get_msrs(CPUState *env)
 838 {
 839     struct {
 840         struct kvm_msrs info;
 841         struct kvm_msr_entry entries[100];
 842     } msr_data;
 843     struct kvm_msr_entry *msrs = msr_data.entries;
 844     int ret, i, n;
 845
 846     n = 0;
 847     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 848     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 849     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 850     if (kvm_has_msr_star(env))
 851         msrs[n++].index = MSR_STAR;
 852     msrs[n++].index = MSR_IA32_TSC;
 853 #ifdef TARGET_X86_64
 854     /* FIXME lm_capable_kernel */
 855     msrs[n++].index = MSR_CSTAR;
 856     msrs[n++].index = MSR_KERNELGSBASE;
 857     msrs[n++].index = MSR_FMASK;
 858     msrs[n++].index = MSR_LSTAR;
 859 #endif
 860     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
 861     msrs[n++].index = MSR_KVM_WALL_CLOCK;
 862
 863     msr_data.info.nmsrs = n;
 864     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
 865     if (ret < 0)
 866         return ret;
 867
 868     for (i = 0; i < ret; i++) {
 869         switch (msrs[i].index) {
 870         case MSR_IA32_SYSENTER_CS:
 871             env->sysenter_cs = msrs[i].data;
 872             break;
 873         case MSR_IA32_SYSENTER_ESP:
 874             env->sysenter_esp = msrs[i].data;
 875             break;
 876         case MSR_IA32_SYSENTER_EIP:
 877             env->sysenter_eip = msrs[i].data;
 878             break;
 879         case MSR_STAR:
 880             env->star = msrs[i].data;
 881             break;
 882 #ifdef TARGET_X86_64
 883         case MSR_CSTAR:
 884             env->cstar = msrs[i].data;
 885             break;
 886         case MSR_KERNELGSBASE:
 887             env->kernelgsbase = msrs[i].data;
 888             break;
 889         case MSR_FMASK:
 890             env->fmask = msrs[i].data;
 891             break;
 892         case MSR_LSTAR:
 893             env->lstar = msrs[i].data;
 894             break;
 895 #endif
 896         case MSR_IA32_TSC:
 897             env->tsc = msrs[i].data;
 898             break;
 899         case MSR_KVM_SYSTEM_TIME:
 900             env->system_time_msr = msrs[i].data;
 901             break;
 902         case MSR_KVM_WALL_CLOCK:
 903             env->wall_clock_msr = msrs[i].data;
 904             break;
 905         }
 906     }
 907
 908     return 0;
 909 }
 910
 911 static int kvm_put_mp_state(CPUState *env)
 912 {
 913     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
 914
 915     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
 916 }
 917
 918 static int kvm_get_mp_state(CPUState *env)
 919 {
 920     struct kvm_mp_state mp_state;
 921     int ret;
 922
 923     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
 924     if (ret < 0) {
 925         return ret;
 926     }
 927     env->mp_state = mp_state.mp_state;
 928     return 0;
 929 }
 930
 931 static int kvm_put_vcpu_events(CPUState *env, int level)
 932 {
 933 #ifdef KVM_CAP_VCPU_EVENTS
 934     struct kvm_vcpu_events events;
 935
 936     if (!kvm_has_vcpu_events()) {
 937         return 0;
 938     }
 939
 940     events.exception.injected = (env->exception_injected >= 0);
 941     events.exception.nr = env->exception_injected;
 942     events.exception.has_error_code = env->has_error_code;
 943     events.exception.error_code = env->error_code;
 944
 945     events.interrupt.injected = (env->interrupt_injected >= 0);
 946     events.interrupt.nr = env->interrupt_injected;
 947     events.interrupt.soft = env->soft_interrupt;
 948
 949     events.nmi.injected = env->nmi_injected;
 950     events.nmi.pending = env->nmi_pending;
 951     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
 952
 953     events.sipi_vector = env->sipi_vector;
 954
 955     events.flags = 0;
 956     if (level >= KVM_PUT_RESET_STATE) {
 957         events.flags |=
 958             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
 959     }
 960
 961     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
 962 #else
 963     return 0;
 964 #endif
 965 }
 966
 967 static int kvm_get_vcpu_events(CPUState *env)
 968 {
 969 #ifdef KVM_CAP_VCPU_EVENTS
 970     struct kvm_vcpu_events events;
 971     int ret;
 972
 973     if (!kvm_has_vcpu_events()) {
 974         return 0;
 975     }
 976
 977     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
 978     if (ret < 0) {
 979        return ret;
 980     }
 981     env->exception_injected =
 982        events.exception.injected ? events.exception.nr : -1;
 983     env->has_error_code = events.exception.has_error_code;
 984     env->error_code = events.exception.error_code;
 985
 986     env->interrupt_injected =
 987         events.interrupt.injected ? events.interrupt.nr : -1;
 988     env->soft_interrupt = events.interrupt.soft;
 989
 990     env->nmi_injected = events.nmi.injected;
 991     env->nmi_pending = events.nmi.pending;
 992     if (events.nmi.masked) {
 993         env->hflags2 |= HF2_NMI_MASK;
 994     } else {
 995         env->hflags2 &= ~HF2_NMI_MASK;
 996     }
 997
 998     env->sipi_vector = events.sipi_vector;
 999 #endif
1000
1001     return 0;
1002 }
1003
1004 static int kvm_guest_debug_workarounds(CPUState *env)
1005 {
1006     int ret = 0;
1007 #ifdef KVM_CAP_SET_GUEST_DEBUG
1008     unsigned long reinject_trap = 0;
1009
1010     if (!kvm_has_vcpu_events()) {
1011         if (env->exception_injected == 1) {
1012             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1013         } else if (env->exception_injected == 3) {
1014             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1015         }
1016         env->exception_injected = -1;
1017     }
1018
1019     /*
1020      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1021      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1022      * by updating the debug state once again if single-stepping is on.
1023      * Another reason to call kvm_update_guest_debug here is a pending debug
1024      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1025      * reinject them via SET_GUEST_DEBUG.
1026      */
1027     if (reinject_trap ||
1028         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1029         ret = kvm_update_guest_debug(env, reinject_trap);
1030     }
1031 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1032     return ret;
1033 }
1034
1035 static int kvm_put_debugregs(CPUState *env)
1036 {
1037 #ifdef KVM_CAP_DEBUGREGS
1038     struct kvm_debugregs dbgregs;
1039     int i;
1040
1041     if (!kvm_has_debugregs()) {
1042         return 0;
1043     }
1044
1045     for (i = 0; i < 4; i++) {
1046         dbgregs.db[i] = env->dr[i];
1047     }
1048     dbgregs.dr6 = env->dr[6];
1049     dbgregs.dr7 = env->dr[7];
1050     dbgregs.flags = 0;
1051
1052     return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1053 #else
1054     return 0;
1055 #endif
1056 }
1057
1058 static int kvm_get_debugregs(CPUState *env)
1059 {
1060 #ifdef KVM_CAP_DEBUGREGS
1061     struct kvm_debugregs dbgregs;
1062     int i, ret;
1063
1064     if (!kvm_has_debugregs()) {
1065         return 0;
1066     }
1067
1068     ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1069     if (ret < 0) {
1070        return ret;
1071     }
1072     for (i = 0; i < 4; i++) {
1073         env->dr[i] = dbgregs.db[i];
1074     }
1075     env->dr[4] = env->dr[6] = dbgregs.dr6;
1076     env->dr[5] = env->dr[7] = dbgregs.dr7;
1077 #endif
1078
1079     return 0;
1080 }
1081
1082 int kvm_arch_put_registers(CPUState *env, int level)
1083 {
1084     int ret;
1085
1086     assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1087
1088     ret = kvm_getput_regs(env, 1);
1089     if (ret < 0)
1090         return ret;
1091
1092     ret = kvm_put_xsave(env);
1093     if (ret < 0)
1094         return ret;
1095
1096     ret = kvm_put_xcrs(env);
1097     if (ret < 0)
1098         return ret;
1099
1100     ret = kvm_put_sregs(env);
1101     if (ret < 0)
1102         return ret;
1103
1104     ret = kvm_put_msrs(env, level);
1105     if (ret < 0)
1106         return ret;
1107
1108     if (level >= KVM_PUT_RESET_STATE) {
1109         ret = kvm_put_mp_state(env);
1110         if (ret < 0)
1111             return ret;
1112     }
1113
1114     ret = kvm_put_vcpu_events(env, level);
1115     if (ret < 0)
1116         return ret;
1117
1118     /* must be last */
1119     ret = kvm_guest_debug_workarounds(env);
1120     if (ret < 0)
1121         return ret;
1122
1123     ret = kvm_put_debugregs(env);
1124     if (ret < 0)
1125         return ret;
1126
1127     return 0;
1128 }
1129
1130 int kvm_arch_get_registers(CPUState *env)
1131 {
1132     int ret;
1133
1134     assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1135
1136     ret = kvm_getput_regs(env, 0);
1137     if (ret < 0)
1138         return ret;
1139
1140     ret = kvm_get_xsave(env);
1141     if (ret < 0)
1142         return ret;
1143
1144     ret = kvm_get_xcrs(env);
1145     if (ret < 0)
1146         return ret;
1147
1148     ret = kvm_get_sregs(env);
1149     if (ret < 0)
1150         return ret;
1151
1152     ret = kvm_get_msrs(env);
1153     if (ret < 0)
1154         return ret;
1155
1156     ret = kvm_get_mp_state(env);
1157     if (ret < 0)
1158         return ret;
1159
1160     ret = kvm_get_vcpu_events(env);
1161     if (ret < 0)
1162         return ret;
1163
1164     ret = kvm_get_debugregs(env);
1165     if (ret < 0)
1166         return ret;
1167
1168     return 0;
1169 }
1170
1171 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1172 {
1173     /* Try to inject an interrupt if the guest can accept it */
1174     if (run->ready_for_interrupt_injection &&
1175         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1176         (env->eflags & IF_MASK)) {
1177         int irq;
1178
1179         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1180         irq = cpu_get_pic_interrupt(env);
1181         if (irq >= 0) {
1182             struct kvm_interrupt intr;
1183             intr.irq = irq;
1184             /* FIXME: errors */
1185             DPRINTF("injected interrupt %d\n", irq);
1186             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1187         }
1188     }
1189
1190     /* If we have an interrupt but the guest is not ready to receive an
1191      * interrupt, request an interrupt window exit.  This will
1192      * cause a return to userspace as soon as the guest is ready to
1193      * receive interrupts. */
1194     if ((env->interrupt_request & CPU_INTERRUPT_HARD))
1195         run->request_interrupt_window = 1;
1196     else
1197         run->request_interrupt_window = 0;
1198
1199     DPRINTF("setting tpr\n");
1200     run->cr8 = cpu_get_apic_tpr(env->apic_state);
1201
1202     return 0;
1203 }
1204
1205 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
1206 {
1207     if (run->if_flag)
1208         env->eflags |= IF_MASK;
1209     else
1210         env->eflags &= ~IF_MASK;
1211
1212     cpu_set_apic_tpr(env->apic_state, run->cr8);
1213     cpu_set_apic_base(env->apic_state, run->apic_base);
1214
1215     return 0;
1216 }
1217
1218 int kvm_arch_process_irqchip_events(CPUState *env)
1219 {
1220     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1221         kvm_cpu_synchronize_state(env);
1222         do_cpu_init(env);
1223         env->exception_index = EXCP_HALTED;
1224     }
1225
1226     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1227         kvm_cpu_synchronize_state(env);
1228         do_cpu_sipi(env);
1229     }
1230
1231     return env->halted;
1232 }
1233
1234 static int kvm_handle_halt(CPUState *env)
1235 {
1236     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1237           (env->eflags & IF_MASK)) &&
1238         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1239         env->halted = 1;
1240         env->exception_index = EXCP_HLT;
1241         return 0;
1242     }
1243
1244     return 1;
1245 }
1246
1247 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
1248 {
1249     int ret = 0;
1250
1251     switch (run->exit_reason) {
1252     case KVM_EXIT_HLT:
1253         DPRINTF("handle_hlt\n");
1254         ret = kvm_handle_halt(env);
1255         break;
1256     }
1257
1258     return ret;
1259 }
1260
1261 #ifdef KVM_CAP_SET_GUEST_DEBUG
1262 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1263 {
1264     static const uint8_t int3 = 0xcc;
1265
1266     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1267         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
1268         return -EINVAL;
1269     return 0;
1270 }
1271
1272 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1273 {
1274     uint8_t int3;
1275
1276     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1277         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
1278         return -EINVAL;
1279     return 0;
1280 }
1281
1282 static struct {
1283     target_ulong addr;
1284     int len;
1285     int type;
1286 } hw_breakpoint[4];
1287
1288 static int nb_hw_breakpoint;
1289
1290 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1291 {
1292     int n;
1293
1294     for (n = 0; n < nb_hw_breakpoint; n++)
1295         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1296             (hw_breakpoint[n].len == len || len == -1))
1297             return n;
1298     return -1;
1299 }
1300
1301 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1302                                   target_ulong len, int type)
1303 {
1304     switch (type) {
1305     case GDB_BREAKPOINT_HW:
1306         len = 1;
1307         break;
1308     case GDB_WATCHPOINT_WRITE:
1309     case GDB_WATCHPOINT_ACCESS:
1310         switch (len) {
1311         case 1:
1312             break;
1313         case 2:
1314         case 4:
1315         case 8:
1316             if (addr & (len - 1))
1317                 return -EINVAL;
1318             break;
1319         default:
1320             return -EINVAL;
1321         }
1322         break;
1323     default:
1324         return -ENOSYS;
1325     }
1326
1327     if (nb_hw_breakpoint == 4)
1328         return -ENOBUFS;
1329
1330     if (find_hw_breakpoint(addr, len, type) >= 0)
1331         return -EEXIST;
1332
1333     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1334     hw_breakpoint[nb_hw_breakpoint].len = len;
1335     hw_breakpoint[nb_hw_breakpoint].type = type;
1336     nb_hw_breakpoint++;
1337
1338     return 0;
1339 }
1340
1341 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1342                                   target_ulong len, int type)
1343 {
1344     int n;
1345
1346     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1347     if (n < 0)
1348         return -ENOENT;
1349
1350     nb_hw_breakpoint--;
1351     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1352
1353     return 0;
1354 }
1355
1356 void kvm_arch_remove_all_hw_breakpoints(void)
1357 {
1358     nb_hw_breakpoint = 0;
1359 }
1360
1361 static CPUWatchpoint hw_watchpoint;
1362
1363 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1364 {
1365     int handle = 0;
1366     int n;
1367
1368     if (arch_info->exception == 1) {
1369         if (arch_info->dr6 & (1 << 14)) {
1370             if (cpu_single_env->singlestep_enabled)
1371                 handle = 1;
1372         } else {
1373             for (n = 0; n < 4; n++)
1374                 if (arch_info->dr6 & (1 << n))
1375                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1376                     case 0x0:
1377                         handle = 1;
1378                         break;
1379                     case 0x1:
1380                         handle = 1;
1381                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1382                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1383                         hw_watchpoint.flags = BP_MEM_WRITE;
1384                         break;
1385                     case 0x3:
1386                         handle = 1;
1387                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1388                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1389                         hw_watchpoint.flags = BP_MEM_ACCESS;
1390                         break;
1391                     }
1392         }
1393     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
1394         handle = 1;
1395
1396     if (!handle) {
1397         cpu_synchronize_state(cpu_single_env);
1398         assert(cpu_single_env->exception_injected == -1);
1399
1400         cpu_single_env->exception_injected = arch_info->exception;
1401         cpu_single_env->has_error_code = 0;
1402     }
1403
1404     return handle;
1405 }
1406
1407 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1408 {
1409     const uint8_t type_code[] = {
1410         [GDB_BREAKPOINT_HW] = 0x0,
1411         [GDB_WATCHPOINT_WRITE] = 0x1,
1412         [GDB_WATCHPOINT_ACCESS] = 0x3
1413     };
1414     const uint8_t len_code[] = {
1415         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1416     };
1417     int n;
1418
1419     if (kvm_sw_breakpoints_active(env))
1420         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1421
1422     if (nb_hw_breakpoint > 0) {
1423         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1424         dbg->arch.debugreg[7] = 0x0600;
1425         for (n = 0; n < nb_hw_breakpoint; n++) {
1426             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1427             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1428                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1429                 (len_code[hw_breakpoint[n].len] << (18 + n*4));
1430         }
1431     }
1432     /* Legal xcr0 for loading */
1433     env->xcr0 = 1;
1434 }
1435 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1436
1437 bool kvm_arch_stop_on_emulation_error(CPUState *env)
1438 {
1439       return !(env->cr[0] & CR0_PE_MASK) ||
1440               ((env->segs[R_CS].selector  & 3) != 3);
1441 }
1442