target-i386/machine.c

   1 #include "hw/hw.h"
   2 #include "hw/boards.h"
   3 #include "hw/pc.h"
   4 #include "hw/isa.h"
   5 #include "host-utils.h"
   6
   7 #include "exec-all.h"
   8 #include "kvm.h"
   9
  10 static void cpu_put_seg(QEMUFile *f, SegmentCache *dt)
  11 {
  12     qemu_put_be32(f, dt->selector);
  13     qemu_put_betl(f, dt->base);
  14     qemu_put_be32(f, dt->limit);
  15     qemu_put_be32(f, dt->flags);
  16 }
  17
  18 static void cpu_get_seg(QEMUFile *f, SegmentCache *dt)
  19 {
  20     dt->selector = qemu_get_be32(f);
  21     dt->base = qemu_get_betl(f);
  22     dt->limit = qemu_get_be32(f);
  23     dt->flags = qemu_get_be32(f);
  24 }
  25
  26 void cpu_save(QEMUFile *f, void *opaque)
  27 {
  28     CPUState *env = opaque;
  29     uint16_t fptag, fpus, fpuc, fpregs_format;
  30     uint32_t hflags;
  31     int32_t a20_mask;
  32     int32_t pending_irq;
  33     int i, bit;
  34
  35     cpu_synchronize_state(env);
  36
  37     for(i = 0; i < CPU_NB_REGS; i++)
  38         qemu_put_betls(f, &env->regs[i]);
  39     qemu_put_betls(f, &env->eip);
  40     qemu_put_betls(f, &env->eflags);
  41     hflags = env->hflags; /* XXX: suppress most of the redundant hflags */
  42     qemu_put_be32s(f, &hflags);
  43
  44     /* FPU */
  45     fpuc = env->fpuc;
  46     fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
  47     fptag = 0;
  48     for(i = 0; i < 8; i++) {
  49         fptag |= ((!env->fptags[i]) << i);
  50     }
  51
  52     qemu_put_be16s(f, &fpuc);
  53     qemu_put_be16s(f, &fpus);
  54     qemu_put_be16s(f, &fptag);
  55
  56 #ifdef USE_X86LDOUBLE
  57     fpregs_format = 0;
  58 #else
  59     fpregs_format = 1;
  60 #endif
  61     qemu_put_be16s(f, &fpregs_format);
  62
  63     for(i = 0; i < 8; i++) {
  64 #ifdef USE_X86LDOUBLE
  65         {
  66             uint64_t mant;
  67             uint16_t exp;
  68             /* we save the real CPU data (in case of MMX usage only 'mant'
  69                contains the MMX register */
  70             cpu_get_fp80(&mant, &exp, env->fpregs[i].d);
  71             qemu_put_be64(f, mant);
  72             qemu_put_be16(f, exp);
  73         }
  74 #else
  75         /* if we use doubles for float emulation, we save the doubles to
  76            avoid losing information in case of MMX usage. It can give
  77            problems if the image is restored on a CPU where long
  78            doubles are used instead. */
  79         qemu_put_be64(f, env->fpregs[i].mmx.MMX_Q(0));
  80 #endif
  81     }
  82
  83     for(i = 0; i < 6; i++)
  84         cpu_put_seg(f, &env->segs[i]);
  85     cpu_put_seg(f, &env->ldt);
  86     cpu_put_seg(f, &env->tr);
  87     cpu_put_seg(f, &env->gdt);
  88     cpu_put_seg(f, &env->idt);
  89
  90     qemu_put_be32s(f, &env->sysenter_cs);
  91     qemu_put_betls(f, &env->sysenter_esp);
  92     qemu_put_betls(f, &env->sysenter_eip);
  93
  94     qemu_put_betls(f, &env->cr[0]);
  95     qemu_put_betls(f, &env->cr[2]);
  96     qemu_put_betls(f, &env->cr[3]);
  97     qemu_put_betls(f, &env->cr[4]);
  98
  99     for(i = 0; i < 8; i++)
 100         qemu_put_betls(f, &env->dr[i]);
 101
 102     /* MMU */
 103     a20_mask = (int32_t) env->a20_mask;
 104     qemu_put_sbe32s(f, &a20_mask);
 105
 106     /* XMM */
 107     qemu_put_be32s(f, &env->mxcsr);
 108     for(i = 0; i < CPU_NB_REGS; i++) {
 109         qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(0));
 110         qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(1));
 111     }
 112
 113 #ifdef TARGET_X86_64
 114     qemu_put_be64s(f, &env->efer);
 115     qemu_put_be64s(f, &env->star);
 116     qemu_put_be64s(f, &env->lstar);
 117     qemu_put_be64s(f, &env->cstar);
 118     qemu_put_be64s(f, &env->fmask);
 119     qemu_put_be64s(f, &env->kernelgsbase);
 120 #endif
 121     qemu_put_be32s(f, &env->smbase);
 122
 123     qemu_put_be64s(f, &env->pat);
 124     qemu_put_be32s(f, &env->hflags2);
 125
 126     qemu_put_be64s(f, &env->vm_hsave);
 127     qemu_put_be64s(f, &env->vm_vmcb);
 128     qemu_put_be64s(f, &env->tsc_offset);
 129     qemu_put_be64s(f, &env->intercept);
 130     qemu_put_be16s(f, &env->intercept_cr_read);
 131     qemu_put_be16s(f, &env->intercept_cr_write);
 132     qemu_put_be16s(f, &env->intercept_dr_read);
 133     qemu_put_be16s(f, &env->intercept_dr_write);
 134     qemu_put_be32s(f, &env->intercept_exceptions);
 135     qemu_put_8s(f, &env->v_tpr);
 136
 137     /* MTRRs */
 138     for(i = 0; i < 11; i++)
 139         qemu_put_be64s(f, &env->mtrr_fixed[i]);
 140     qemu_put_be64s(f, &env->mtrr_deftype);
 141     for(i = 0; i < 8; i++) {
 142         qemu_put_be64s(f, &env->mtrr_var[i].base);
 143         qemu_put_be64s(f, &env->mtrr_var[i].mask);
 144     }
 145
 146     /* KVM-related states */
 147
 148     /* There can only be one pending IRQ set in the bitmap at a time, so try
 149        to find it and save its number instead (-1 for none). */
 150     pending_irq = -1;
 151     for (i = 0; i < ARRAY_SIZE(env->interrupt_bitmap); i++) {
 152         if (env->interrupt_bitmap[i]) {
 153             bit = ctz64(env->interrupt_bitmap[i]);
 154             pending_irq = i * 64 + bit;
 155             break;
 156         }
 157     }
 158     qemu_put_sbe32s(f, &pending_irq);
 159     qemu_put_be32s(f, &env->mp_state);
 160     qemu_put_be64s(f, &env->tsc);
 161
 162     /* MCE */
 163     qemu_put_be64s(f, &env->mcg_cap);
 164     if (env->mcg_cap) {
 165         qemu_put_be64s(f, &env->mcg_status);
 166         qemu_put_be64s(f, &env->mcg_ctl);
 167         for (i = 0; i < (env->mcg_cap & 0xff); i++) {
 168             qemu_put_be64s(f, &env->mce_banks[4*i]);
 169             qemu_put_be64s(f, &env->mce_banks[4*i + 1]);
 170             qemu_put_be64s(f, &env->mce_banks[4*i + 2]);
 171             qemu_put_be64s(f, &env->mce_banks[4*i + 3]);
 172         }
 173     }
 174     qemu_put_be64s(f, &env->tsc_aux);
 175  }
 176
 177 #ifdef USE_X86LDOUBLE
 178 /* XXX: add that in a FPU generic layer */
 179 union x86_longdouble {
 180     uint64_t mant;
 181     uint16_t exp;
 182 };
 183
 184 #define MANTD1(fp)      (fp & ((1LL << 52) - 1))
 185 #define EXPBIAS1 1023
 186 #define EXPD1(fp)       ((fp >> 52) & 0x7FF)
 187 #define SIGND1(fp)      ((fp >> 32) & 0x80000000)
 188
 189 static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp)
 190 {
 191     int e;
 192     /* mantissa */
 193     p->mant = (MANTD1(temp) << 11) | (1LL << 63);
 194     /* exponent + sign */
 195     e = EXPD1(temp) - EXPBIAS1 + 16383;
 196     e |= SIGND1(temp) >> 16;
 197     p->exp = e;
 198 }
 199 #endif
 200
 201 int cpu_load(QEMUFile *f, void *opaque, int version_id)
 202 {
 203     CPUState *env = opaque;
 204     int i, guess_mmx;
 205     uint32_t hflags;
 206     uint16_t fpus, fpuc, fptag, fpregs_format;
 207     int32_t a20_mask;
 208     int32_t pending_irq;
 209
 210     cpu_synchronize_state(env);
 211     if (version_id < 3 || version_id > CPU_SAVE_VERSION)
 212         return -EINVAL;
 213     for(i = 0; i < CPU_NB_REGS; i++)
 214         qemu_get_betls(f, &env->regs[i]);
 215     qemu_get_betls(f, &env->eip);
 216     qemu_get_betls(f, &env->eflags);
 217     qemu_get_be32s(f, &hflags);
 218
 219     qemu_get_be16s(f, &fpuc);
 220     qemu_get_be16s(f, &fpus);
 221     qemu_get_be16s(f, &fptag);
 222     qemu_get_be16s(f, &fpregs_format);
 223
 224     /* NOTE: we cannot always restore the FPU state if the image come
 225        from a host with a different 'USE_X86LDOUBLE' define. We guess
 226        if we are in an MMX state to restore correctly in that case. */
 227     guess_mmx = ((fptag == 0xff) && (fpus & 0x3800) == 0);
 228     for(i = 0; i < 8; i++) {
 229         uint64_t mant;
 230         uint16_t exp;
 231
 232         switch(fpregs_format) {
 233         case 0:
 234             mant = qemu_get_be64(f);
 235             exp = qemu_get_be16(f);
 236 #ifdef USE_X86LDOUBLE
 237             env->fpregs[i].d = cpu_set_fp80(mant, exp);
 238 #else
 239             /* difficult case */
 240             if (guess_mmx)
 241                 env->fpregs[i].mmx.MMX_Q(0) = mant;
 242             else
 243                 env->fpregs[i].d = cpu_set_fp80(mant, exp);
 244 #endif
 245             break;
 246         case 1:
 247             mant = qemu_get_be64(f);
 248 #ifdef USE_X86LDOUBLE
 249             {
 250                 union x86_longdouble *p;
 251                 /* difficult case */
 252                 p = (void *)&env->fpregs[i];
 253                 if (guess_mmx) {
 254                     p->mant = mant;
 255                     p->exp = 0xffff;
 256                 } else {
 257                     fp64_to_fp80(p, mant);
 258                 }
 259             }
 260 #else
 261             env->fpregs[i].mmx.MMX_Q(0) = mant;
 262 #endif
 263             break;
 264         default:
 265             return -EINVAL;
 266         }
 267     }
 268
 269     env->fpuc = fpuc;
 270     /* XXX: restore FPU round state */
 271     env->fpstt = (fpus >> 11) & 7;
 272     env->fpus = fpus & ~0x3800;
 273     fptag ^= 0xff;
 274     for(i = 0; i < 8; i++) {
 275         env->fptags[i] = (fptag >> i) & 1;
 276     }
 277
 278     for(i = 0; i < 6; i++)
 279         cpu_get_seg(f, &env->segs[i]);
 280     cpu_get_seg(f, &env->ldt);
 281     cpu_get_seg(f, &env->tr);
 282     cpu_get_seg(f, &env->gdt);
 283     cpu_get_seg(f, &env->idt);
 284
 285     qemu_get_be32s(f, &env->sysenter_cs);
 286     if (version_id >= 7) {
 287         qemu_get_betls(f, &env->sysenter_esp);
 288         qemu_get_betls(f, &env->sysenter_eip);
 289     } else {
 290         env->sysenter_esp = qemu_get_be32(f);
 291         env->sysenter_eip = qemu_get_be32(f);
 292     }
 293
 294     qemu_get_betls(f, &env->cr[0]);
 295     qemu_get_betls(f, &env->cr[2]);
 296     qemu_get_betls(f, &env->cr[3]);
 297     qemu_get_betls(f, &env->cr[4]);
 298
 299     for(i = 0; i < 8; i++)
 300         qemu_get_betls(f, &env->dr[i]);
 301     cpu_breakpoint_remove_all(env, BP_CPU);
 302     cpu_watchpoint_remove_all(env, BP_CPU);
 303     for (i = 0; i < 4; i++)
 304         hw_breakpoint_insert(env, i);
 305
 306     /* MMU */
 307     qemu_get_sbe32s(f, &a20_mask);
 308     env->a20_mask = a20_mask;
 309
 310     qemu_get_be32s(f, &env->mxcsr);
 311     for(i = 0; i < CPU_NB_REGS; i++) {
 312         qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(0));
 313         qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(1));
 314     }
 315
 316 #ifdef TARGET_X86_64
 317     qemu_get_be64s(f, &env->efer);
 318     qemu_get_be64s(f, &env->star);
 319     qemu_get_be64s(f, &env->lstar);
 320     qemu_get_be64s(f, &env->cstar);
 321     qemu_get_be64s(f, &env->fmask);
 322     qemu_get_be64s(f, &env->kernelgsbase);
 323 #endif
 324     if (version_id >= 4) {
 325         qemu_get_be32s(f, &env->smbase);
 326     }
 327     if (version_id >= 5) {
 328         qemu_get_be64s(f, &env->pat);
 329         qemu_get_be32s(f, &env->hflags2);
 330         if (version_id < 6)
 331             qemu_get_be32s(f, &env->halted);
 332
 333         qemu_get_be64s(f, &env->vm_hsave);
 334         qemu_get_be64s(f, &env->vm_vmcb);
 335         qemu_get_be64s(f, &env->tsc_offset);
 336         qemu_get_be64s(f, &env->intercept);
 337         qemu_get_be16s(f, &env->intercept_cr_read);
 338         qemu_get_be16s(f, &env->intercept_cr_write);
 339         qemu_get_be16s(f, &env->intercept_dr_read);
 340         qemu_get_be16s(f, &env->intercept_dr_write);
 341         qemu_get_be32s(f, &env->intercept_exceptions);
 342         qemu_get_8s(f, &env->v_tpr);
 343     }
 344
 345     if (version_id >= 8) {
 346         /* MTRRs */
 347         for(i = 0; i < 11; i++)
 348             qemu_get_be64s(f, &env->mtrr_fixed[i]);
 349         qemu_get_be64s(f, &env->mtrr_deftype);
 350         for(i = 0; i < 8; i++) {
 351             qemu_get_be64s(f, &env->mtrr_var[i].base);
 352             qemu_get_be64s(f, &env->mtrr_var[i].mask);
 353         }
 354     }
 355
 356     if (version_id >= 9) {
 357         qemu_get_sbe32s(f, &pending_irq);
 358         memset(&env->interrupt_bitmap, 0, sizeof(env->interrupt_bitmap));
 359         if (pending_irq >= 0) {
 360             env->interrupt_bitmap[pending_irq / 64] |=
 361                 (uint64_t)1 << (pending_irq % 64);
 362         }
 363         qemu_get_be32s(f, &env->mp_state);
 364         qemu_get_be64s(f, &env->tsc);
 365     }
 366
 367     if (version_id >= 10) {
 368         qemu_get_be64s(f, &env->mcg_cap);
 369         if (env->mcg_cap) {
 370             qemu_get_be64s(f, &env->mcg_status);
 371             qemu_get_be64s(f, &env->mcg_ctl);
 372             for (i = 0; i < (env->mcg_cap & 0xff); i++) {
 373                 qemu_get_be64s(f, &env->mce_banks[4*i]);
 374                 qemu_get_be64s(f, &env->mce_banks[4*i + 1]);
 375                 qemu_get_be64s(f, &env->mce_banks[4*i + 2]);
 376                 qemu_get_be64s(f, &env->mce_banks[4*i + 3]);
 377             }
 378         }
 379     }
 380
 381     if (version_id >= 11) {
 382         qemu_get_be64s(f, &env->tsc_aux);
 383     }
 384     /* XXX: ensure compatiblity for halted bit ? */
 385     /* XXX: compute redundant hflags bits */
 386     env->hflags = hflags;
 387     tlb_flush(env, 1);
 388     return 0;
 389 }