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1 /*
2 * i386 translation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25 #include <signal.h>
26 #include <assert.h>
27 #include <sys/mman.h>
28
29 #include "cpu.h"
30 #include "exec-all.h"
31 #include "disas.h"
32
33 /* XXX: move that elsewhere */
34 static uint16_t *gen_opc_ptr;
35 static uint32_t *gen_opparam_ptr;
36
37 #define PREFIX_REPZ 0x01
38 #define PREFIX_REPNZ 0x02
39 #define PREFIX_LOCK 0x04
40 #define PREFIX_DATA 0x08
41 #define PREFIX_ADR 0x10
42
43 typedef struct DisasContext {
44 /* current insn context */
45 int override; /* -1 if no override */
46 int prefix;
47 int aflag, dflag;
48 uint8_t *pc; /* pc = eip + cs_base */
49 int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
50 static state change (stop translation) */
51 /* current block context */
52 uint8_t *cs_base; /* base of CS segment */
53 int pe; /* protected mode */
54 int code32; /* 32 bit code segment */
55 int ss32; /* 32 bit stack segment */
56 int cc_op; /* current CC operation */
57 int addseg; /* non zero if either DS/ES/SS have a non zero base */
58 int f_st; /* currently unused */
59 int vm86; /* vm86 mode */
60 int cpl;
61 int iopl;
62 int tf; /* TF cpu flag */
63 int singlestep_enabled; /* "hardware" single step enabled */
64 int jmp_opt; /* use direct block chaining for direct jumps */
65 int mem_index; /* select memory access functions */
66 struct TranslationBlock *tb;
67 int popl_esp_hack; /* for correct popl with esp base handling */
68 } DisasContext;
69
70 static void gen_eob(DisasContext *s);
71 static void gen_jmp(DisasContext *s, unsigned int eip);
72
73 /* i386 arith/logic operations */
74 enum {
75 OP_ADDL,
76 OP_ORL,
77 OP_ADCL,
78 OP_SBBL,
79 OP_ANDL,
80 OP_SUBL,
81 OP_XORL,
82 OP_CMPL,
83 };
84
85 /* i386 shift ops */
86 enum {
87 OP_ROL,
88 OP_ROR,
89 OP_RCL,
90 OP_RCR,
91 OP_SHL,
92 OP_SHR,
93 OP_SHL1, /* undocumented */
94 OP_SAR = 7,
95 };
96
97 enum {
98 #define DEF(s, n, copy_size) INDEX_op_ ## s,
99 #include "opc.h"
100 #undef DEF
101 NB_OPS,
102 };
103
104 #include "gen-op.h"
105
106 /* operand size */
107 enum {
108 OT_BYTE = 0,
109 OT_WORD,
110 OT_LONG,
111 OT_QUAD,
112 };
113
114 enum {
115 /* I386 int registers */
116 OR_EAX, /* MUST be even numbered */
117 OR_ECX,
118 OR_EDX,
119 OR_EBX,
120 OR_ESP,
121 OR_EBP,
122 OR_ESI,
123 OR_EDI,
124 OR_TMP0, /* temporary operand register */
125 OR_TMP1,
126 OR_A0, /* temporary register used when doing address evaluation */
127 OR_ZERO, /* fixed zero register */
128 NB_OREGS,
129 };
130
131 typedef void (GenOpFunc)(void);
132 typedef void (GenOpFunc1)(long);
133 typedef void (GenOpFunc2)(long, long);
134 typedef void (GenOpFunc3)(long, long, long);
135
136 static GenOpFunc *gen_op_mov_reg_T0[3][8] = {
137 [OT_BYTE] = {
138 gen_op_movb_EAX_T0,
139 gen_op_movb_ECX_T0,
140 gen_op_movb_EDX_T0,
141 gen_op_movb_EBX_T0,
142 gen_op_movh_EAX_T0,
143 gen_op_movh_ECX_T0,
144 gen_op_movh_EDX_T0,
145 gen_op_movh_EBX_T0,
146 },
147 [OT_WORD] = {
148 gen_op_movw_EAX_T0,
149 gen_op_movw_ECX_T0,
150 gen_op_movw_EDX_T0,
151 gen_op_movw_EBX_T0,
152 gen_op_movw_ESP_T0,
153 gen_op_movw_EBP_T0,
154 gen_op_movw_ESI_T0,
155 gen_op_movw_EDI_T0,
156 },
157 [OT_LONG] = {
158 gen_op_movl_EAX_T0,
159 gen_op_movl_ECX_T0,
160 gen_op_movl_EDX_T0,
161 gen_op_movl_EBX_T0,
162 gen_op_movl_ESP_T0,
163 gen_op_movl_EBP_T0,
164 gen_op_movl_ESI_T0,
165 gen_op_movl_EDI_T0,
166 },
167 };
168
169 static GenOpFunc *gen_op_mov_reg_T1[3][8] = {
170 [OT_BYTE] = {
171 gen_op_movb_EAX_T1,
172 gen_op_movb_ECX_T1,
173 gen_op_movb_EDX_T1,
174 gen_op_movb_EBX_T1,
175 gen_op_movh_EAX_T1,
176 gen_op_movh_ECX_T1,
177 gen_op_movh_EDX_T1,
178 gen_op_movh_EBX_T1,
179 },
180 [OT_WORD] = {
181 gen_op_movw_EAX_T1,
182 gen_op_movw_ECX_T1,
183 gen_op_movw_EDX_T1,
184 gen_op_movw_EBX_T1,
185 gen_op_movw_ESP_T1,
186 gen_op_movw_EBP_T1,
187 gen_op_movw_ESI_T1,
188 gen_op_movw_EDI_T1,
189 },
190 [OT_LONG] = {
191 gen_op_movl_EAX_T1,
192 gen_op_movl_ECX_T1,
193 gen_op_movl_EDX_T1,
194 gen_op_movl_EBX_T1,
195 gen_op_movl_ESP_T1,
196 gen_op_movl_EBP_T1,
197 gen_op_movl_ESI_T1,
198 gen_op_movl_EDI_T1,
199 },
200 };
201
202 static GenOpFunc *gen_op_mov_reg_A0[2][8] = {
203 [0] = {
204 gen_op_movw_EAX_A0,
205 gen_op_movw_ECX_A0,
206 gen_op_movw_EDX_A0,
207 gen_op_movw_EBX_A0,
208 gen_op_movw_ESP_A0,
209 gen_op_movw_EBP_A0,
210 gen_op_movw_ESI_A0,
211 gen_op_movw_EDI_A0,
212 },
213 [1] = {
214 gen_op_movl_EAX_A0,
215 gen_op_movl_ECX_A0,
216 gen_op_movl_EDX_A0,
217 gen_op_movl_EBX_A0,
218 gen_op_movl_ESP_A0,
219 gen_op_movl_EBP_A0,
220 gen_op_movl_ESI_A0,
221 gen_op_movl_EDI_A0,
222 },
223 };
224
225 static GenOpFunc *gen_op_mov_TN_reg[3][2][8] =
226 {
227 [OT_BYTE] = {
228 {
229 gen_op_movl_T0_EAX,
230 gen_op_movl_T0_ECX,
231 gen_op_movl_T0_EDX,
232 gen_op_movl_T0_EBX,
233 gen_op_movh_T0_EAX,
234 gen_op_movh_T0_ECX,
235 gen_op_movh_T0_EDX,
236 gen_op_movh_T0_EBX,
237 },
238 {
239 gen_op_movl_T1_EAX,
240 gen_op_movl_T1_ECX,
241 gen_op_movl_T1_EDX,
242 gen_op_movl_T1_EBX,
243 gen_op_movh_T1_EAX,
244 gen_op_movh_T1_ECX,
245 gen_op_movh_T1_EDX,
246 gen_op_movh_T1_EBX,
247 },
248 },
249 [OT_WORD] = {
250 {
251 gen_op_movl_T0_EAX,
252 gen_op_movl_T0_ECX,
253 gen_op_movl_T0_EDX,
254 gen_op_movl_T0_EBX,
255 gen_op_movl_T0_ESP,
256 gen_op_movl_T0_EBP,
257 gen_op_movl_T0_ESI,
258 gen_op_movl_T0_EDI,
259 },
260 {
261 gen_op_movl_T1_EAX,
262 gen_op_movl_T1_ECX,
263 gen_op_movl_T1_EDX,
264 gen_op_movl_T1_EBX,
265 gen_op_movl_T1_ESP,
266 gen_op_movl_T1_EBP,
267 gen_op_movl_T1_ESI,
268 gen_op_movl_T1_EDI,
269 },
270 },
271 [OT_LONG] = {
272 {
273 gen_op_movl_T0_EAX,
274 gen_op_movl_T0_ECX,
275 gen_op_movl_T0_EDX,
276 gen_op_movl_T0_EBX,
277 gen_op_movl_T0_ESP,
278 gen_op_movl_T0_EBP,
279 gen_op_movl_T0_ESI,
280 gen_op_movl_T0_EDI,
281 },
282 {
283 gen_op_movl_T1_EAX,
284 gen_op_movl_T1_ECX,
285 gen_op_movl_T1_EDX,
286 gen_op_movl_T1_EBX,
287 gen_op_movl_T1_ESP,
288 gen_op_movl_T1_EBP,
289 gen_op_movl_T1_ESI,
290 gen_op_movl_T1_EDI,
291 },
292 },
293 };
294
295 static GenOpFunc *gen_op_movl_A0_reg[8] = {
296 gen_op_movl_A0_EAX,
297 gen_op_movl_A0_ECX,
298 gen_op_movl_A0_EDX,
299 gen_op_movl_A0_EBX,
300 gen_op_movl_A0_ESP,
301 gen_op_movl_A0_EBP,
302 gen_op_movl_A0_ESI,
303 gen_op_movl_A0_EDI,
304 };
305
306 static GenOpFunc *gen_op_addl_A0_reg_sN[4][8] = {
307 [0] = {
308 gen_op_addl_A0_EAX,
309 gen_op_addl_A0_ECX,
310 gen_op_addl_A0_EDX,
311 gen_op_addl_A0_EBX,
312 gen_op_addl_A0_ESP,
313 gen_op_addl_A0_EBP,
314 gen_op_addl_A0_ESI,
315 gen_op_addl_A0_EDI,
316 },
317 [1] = {
318 gen_op_addl_A0_EAX_s1,
319 gen_op_addl_A0_ECX_s1,
320 gen_op_addl_A0_EDX_s1,
321 gen_op_addl_A0_EBX_s1,
322 gen_op_addl_A0_ESP_s1,
323 gen_op_addl_A0_EBP_s1,
324 gen_op_addl_A0_ESI_s1,
325 gen_op_addl_A0_EDI_s1,
326 },
327 [2] = {
328 gen_op_addl_A0_EAX_s2,
329 gen_op_addl_A0_ECX_s2,
330 gen_op_addl_A0_EDX_s2,
331 gen_op_addl_A0_EBX_s2,
332 gen_op_addl_A0_ESP_s2,
333 gen_op_addl_A0_EBP_s2,
334 gen_op_addl_A0_ESI_s2,
335 gen_op_addl_A0_EDI_s2,
336 },
337 [3] = {
338 gen_op_addl_A0_EAX_s3,
339 gen_op_addl_A0_ECX_s3,
340 gen_op_addl_A0_EDX_s3,
341 gen_op_addl_A0_EBX_s3,
342 gen_op_addl_A0_ESP_s3,
343 gen_op_addl_A0_EBP_s3,
344 gen_op_addl_A0_ESI_s3,
345 gen_op_addl_A0_EDI_s3,
346 },
347 };
348
349 static GenOpFunc *gen_op_cmov_reg_T1_T0[2][8] = {
350 [0] = {
351 gen_op_cmovw_EAX_T1_T0,
352 gen_op_cmovw_ECX_T1_T0,
353 gen_op_cmovw_EDX_T1_T0,
354 gen_op_cmovw_EBX_T1_T0,
355 gen_op_cmovw_ESP_T1_T0,
356 gen_op_cmovw_EBP_T1_T0,
357 gen_op_cmovw_ESI_T1_T0,
358 gen_op_cmovw_EDI_T1_T0,
359 },
360 [1] = {
361 gen_op_cmovl_EAX_T1_T0,
362 gen_op_cmovl_ECX_T1_T0,
363 gen_op_cmovl_EDX_T1_T0,
364 gen_op_cmovl_EBX_T1_T0,
365 gen_op_cmovl_ESP_T1_T0,
366 gen_op_cmovl_EBP_T1_T0,
367 gen_op_cmovl_ESI_T1_T0,
368 gen_op_cmovl_EDI_T1_T0,
369 },
370 };
371
372 static GenOpFunc *gen_op_arith_T0_T1_cc[8] = {
373 NULL,
374 gen_op_orl_T0_T1,
375 NULL,
376 NULL,
377 gen_op_andl_T0_T1,
378 NULL,
379 gen_op_xorl_T0_T1,
380 NULL,
381 };
382
383 static GenOpFunc *gen_op_arithc_T0_T1_cc[3][2] = {
384 [OT_BYTE] = {
385 gen_op_adcb_T0_T1_cc,
386 gen_op_sbbb_T0_T1_cc,
387 },
388 [OT_WORD] = {
389 gen_op_adcw_T0_T1_cc,
390 gen_op_sbbw_T0_T1_cc,
391 },
392 [OT_LONG] = {
393 gen_op_adcl_T0_T1_cc,
394 gen_op_sbbl_T0_T1_cc,
395 },
396 };
397
398 static GenOpFunc *gen_op_arithc_mem_T0_T1_cc[3][2] = {
399 [OT_BYTE] = {
400 gen_op_adcb_mem_T0_T1_cc,
401 gen_op_sbbb_mem_T0_T1_cc,
402 },
403 [OT_WORD] = {
404 gen_op_adcw_mem_T0_T1_cc,
405 gen_op_sbbw_mem_T0_T1_cc,
406 },
407 [OT_LONG] = {
408 gen_op_adcl_mem_T0_T1_cc,
409 gen_op_sbbl_mem_T0_T1_cc,
410 },
411 };
412
413 static const int cc_op_arithb[8] = {
414 CC_OP_ADDB,
415 CC_OP_LOGICB,
416 CC_OP_ADDB,
417 CC_OP_SUBB,
418 CC_OP_LOGICB,
419 CC_OP_SUBB,
420 CC_OP_LOGICB,
421 CC_OP_SUBB,
422 };
423
424 static GenOpFunc *gen_op_cmpxchg_T0_T1_EAX_cc[3] = {
425 gen_op_cmpxchgb_T0_T1_EAX_cc,
426 gen_op_cmpxchgw_T0_T1_EAX_cc,
427 gen_op_cmpxchgl_T0_T1_EAX_cc,
428 };
429
430 static GenOpFunc *gen_op_cmpxchg_mem_T0_T1_EAX_cc[3] = {
431 gen_op_cmpxchgb_mem_T0_T1_EAX_cc,
432 gen_op_cmpxchgw_mem_T0_T1_EAX_cc,
433 gen_op_cmpxchgl_mem_T0_T1_EAX_cc,
434 };
435
436 static GenOpFunc *gen_op_shift_T0_T1_cc[3][8] = {
437 [OT_BYTE] = {
438 gen_op_rolb_T0_T1_cc,
439 gen_op_rorb_T0_T1_cc,
440 gen_op_rclb_T0_T1_cc,
441 gen_op_rcrb_T0_T1_cc,
442 gen_op_shlb_T0_T1_cc,
443 gen_op_shrb_T0_T1_cc,
444 gen_op_shlb_T0_T1_cc,
445 gen_op_sarb_T0_T1_cc,
446 },
447 [OT_WORD] = {
448 gen_op_rolw_T0_T1_cc,
449 gen_op_rorw_T0_T1_cc,
450 gen_op_rclw_T0_T1_cc,
451 gen_op_rcrw_T0_T1_cc,
452 gen_op_shlw_T0_T1_cc,
453 gen_op_shrw_T0_T1_cc,
454 gen_op_shlw_T0_T1_cc,
455 gen_op_sarw_T0_T1_cc,
456 },
457 [OT_LONG] = {
458 gen_op_roll_T0_T1_cc,
459 gen_op_rorl_T0_T1_cc,
460 gen_op_rcll_T0_T1_cc,
461 gen_op_rcrl_T0_T1_cc,
462 gen_op_shll_T0_T1_cc,
463 gen_op_shrl_T0_T1_cc,
464 gen_op_shll_T0_T1_cc,
465 gen_op_sarl_T0_T1_cc,
466 },
467 };
468
469 static GenOpFunc *gen_op_shift_mem_T0_T1_cc[3][8] = {
470 [OT_BYTE] = {
471 gen_op_rolb_mem_T0_T1_cc,
472 gen_op_rorb_mem_T0_T1_cc,
473 gen_op_rclb_mem_T0_T1_cc,
474 gen_op_rcrb_mem_T0_T1_cc,
475 gen_op_shlb_mem_T0_T1_cc,
476 gen_op_shrb_mem_T0_T1_cc,
477 gen_op_shlb_mem_T0_T1_cc,
478 gen_op_sarb_mem_T0_T1_cc,
479 },
480 [OT_WORD] = {
481 gen_op_rolw_mem_T0_T1_cc,
482 gen_op_rorw_mem_T0_T1_cc,
483 gen_op_rclw_mem_T0_T1_cc,
484 gen_op_rcrw_mem_T0_T1_cc,
485 gen_op_shlw_mem_T0_T1_cc,
486 gen_op_shrw_mem_T0_T1_cc,
487 gen_op_shlw_mem_T0_T1_cc,
488 gen_op_sarw_mem_T0_T1_cc,
489 },
490 [OT_LONG] = {
491 gen_op_roll_mem_T0_T1_cc,
492 gen_op_rorl_mem_T0_T1_cc,
493 gen_op_rcll_mem_T0_T1_cc,
494 gen_op_rcrl_mem_T0_T1_cc,
495 gen_op_shll_mem_T0_T1_cc,
496 gen_op_shrl_mem_T0_T1_cc,
497 gen_op_shll_mem_T0_T1_cc,
498 gen_op_sarl_mem_T0_T1_cc,
499 },
500 };
501
502 static GenOpFunc1 *gen_op_shiftd_T0_T1_im_cc[2][2] = {
503 [0] = {
504 gen_op_shldw_T0_T1_im_cc,
505 gen_op_shrdw_T0_T1_im_cc,
506 },
507 [1] = {
508 gen_op_shldl_T0_T1_im_cc,
509 gen_op_shrdl_T0_T1_im_cc,
510 },
511 };
512
513 static GenOpFunc *gen_op_shiftd_T0_T1_ECX_cc[2][2] = {
514 [0] = {
515 gen_op_shldw_T0_T1_ECX_cc,
516 gen_op_shrdw_T0_T1_ECX_cc,
517 },
518 [1] = {
519 gen_op_shldl_T0_T1_ECX_cc,
520 gen_op_shrdl_T0_T1_ECX_cc,
521 },
522 };
523
524 static GenOpFunc1 *gen_op_shiftd_mem_T0_T1_im_cc[2][2] = {
525 [0] = {
526 gen_op_shldw_mem_T0_T1_im_cc,
527 gen_op_shrdw_mem_T0_T1_im_cc,
528 },
529 [1] = {
530 gen_op_shldl_mem_T0_T1_im_cc,
531 gen_op_shrdl_mem_T0_T1_im_cc,
532 },
533 };
534
535 static GenOpFunc *gen_op_shiftd_mem_T0_T1_ECX_cc[2][2] = {
536 [0] = {
537 gen_op_shldw_mem_T0_T1_ECX_cc,
538 gen_op_shrdw_mem_T0_T1_ECX_cc,
539 },
540 [1] = {
541 gen_op_shldl_mem_T0_T1_ECX_cc,
542 gen_op_shrdl_mem_T0_T1_ECX_cc,
543 },
544 };
545
546 static GenOpFunc *gen_op_btx_T0_T1_cc[2][4] = {
547 [0] = {
548 gen_op_btw_T0_T1_cc,
549 gen_op_btsw_T0_T1_cc,
550 gen_op_btrw_T0_T1_cc,
551 gen_op_btcw_T0_T1_cc,
552 },
553 [1] = {
554 gen_op_btl_T0_T1_cc,
555 gen_op_btsl_T0_T1_cc,
556 gen_op_btrl_T0_T1_cc,
557 gen_op_btcl_T0_T1_cc,
558 },
559 };
560
561 static GenOpFunc *gen_op_bsx_T0_cc[2][2] = {
562 [0] = {
563 gen_op_bsfw_T0_cc,
564 gen_op_bsrw_T0_cc,
565 },
566 [1] = {
567 gen_op_bsfl_T0_cc,
568 gen_op_bsrl_T0_cc,
569 },
570 };
571
572 static GenOpFunc *gen_op_lds_T0_A0[3 * 3] = {
573 gen_op_ldsb_raw_T0_A0,
574 gen_op_ldsw_raw_T0_A0,
575 NULL,
576 #ifndef CONFIG_USER_ONLY
577 gen_op_ldsb_kernel_T0_A0,
578 gen_op_ldsw_kernel_T0_A0,
579 NULL,
580
581 gen_op_ldsb_user_T0_A0,
582 gen_op_ldsw_user_T0_A0,
583 NULL,
584 #endif
585 };
586
587 static GenOpFunc *gen_op_ldu_T0_A0[3 * 3] = {
588 gen_op_ldub_raw_T0_A0,
589 gen_op_lduw_raw_T0_A0,
590 NULL,
591
592 #ifndef CONFIG_USER_ONLY
593 gen_op_ldub_kernel_T0_A0,
594 gen_op_lduw_kernel_T0_A0,
595 NULL,
596
597 gen_op_ldub_user_T0_A0,
598 gen_op_lduw_user_T0_A0,
599 NULL,
600 #endif
601 };
602
603 /* sign does not matter, except for lidt/lgdt call (TODO: fix it) */
604 static GenOpFunc *gen_op_ld_T0_A0[3 * 3] = {
605 gen_op_ldub_raw_T0_A0,
606 gen_op_lduw_raw_T0_A0,
607 gen_op_ldl_raw_T0_A0,
608
609 #ifndef CONFIG_USER_ONLY
610 gen_op_ldub_kernel_T0_A0,
611 gen_op_lduw_kernel_T0_A0,
612 gen_op_ldl_kernel_T0_A0,
613
614 gen_op_ldub_user_T0_A0,
615 gen_op_lduw_user_T0_A0,
616 gen_op_ldl_user_T0_A0,
617 #endif
618 };
619
620 static GenOpFunc *gen_op_ld_T1_A0[3 * 3] = {
621 gen_op_ldub_raw_T1_A0,
622 gen_op_lduw_raw_T1_A0,
623 gen_op_ldl_raw_T1_A0,
624
625 #ifndef CONFIG_USER_ONLY
626 gen_op_ldub_kernel_T1_A0,
627 gen_op_lduw_kernel_T1_A0,
628 gen_op_ldl_kernel_T1_A0,
629
630 gen_op_ldub_user_T1_A0,
631 gen_op_lduw_user_T1_A0,
632 gen_op_ldl_user_T1_A0,
633 #endif
634 };
635
636 static GenOpFunc *gen_op_st_T0_A0[3 * 3] = {
637 gen_op_stb_raw_T0_A0,
638 gen_op_stw_raw_T0_A0,
639 gen_op_stl_raw_T0_A0,
640
641 #ifndef CONFIG_USER_ONLY
642 gen_op_stb_kernel_T0_A0,
643 gen_op_stw_kernel_T0_A0,
644 gen_op_stl_kernel_T0_A0,
645
646 gen_op_stb_user_T0_A0,
647 gen_op_stw_user_T0_A0,
648 gen_op_stl_user_T0_A0,
649 #endif
650 };
651
652 static inline void gen_string_movl_A0_ESI(DisasContext *s)
653 {
654 int override;
655
656 override = s->override;
657 if (s->aflag) {
658 /* 32 bit address */
659 if (s->addseg && override < 0)
660 override = R_DS;
661 if (override >= 0) {
662 gen_op_movl_A0_seg(offsetof(CPUX86State,segs[override].base));
663 gen_op_addl_A0_reg_sN[0][R_ESI]();
664 } else {
665 gen_op_movl_A0_reg[R_ESI]();
666 }
667 } else {
668 /* 16 address, always override */
669 if (override < 0)
670 override = R_DS;
671 gen_op_movl_A0_reg[R_ESI]();
672 gen_op_andl_A0_ffff();
673 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
674 }
675 }
676
677 static inline void gen_string_movl_A0_EDI(DisasContext *s)
678 {
679 if (s->aflag) {
680 if (s->addseg) {
681 gen_op_movl_A0_seg(offsetof(CPUX86State,segs[R_ES].base));
682 gen_op_addl_A0_reg_sN[0][R_EDI]();
683 } else {
684 gen_op_movl_A0_reg[R_EDI]();
685 }
686 } else {
687 gen_op_movl_A0_reg[R_EDI]();
688 gen_op_andl_A0_ffff();
689 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_ES].base));
690 }
691 }
692
693 static GenOpFunc *gen_op_movl_T0_Dshift[3] = {
694 gen_op_movl_T0_Dshiftb,
695 gen_op_movl_T0_Dshiftw,
696 gen_op_movl_T0_Dshiftl,
697 };
698
699 static GenOpFunc2 *gen_op_jz_ecx[2] = {
700 gen_op_jz_ecxw,
701 gen_op_jz_ecxl,
702 };
703
704 static GenOpFunc1 *gen_op_jz_ecx_im[2] = {
705 gen_op_jz_ecxw_im,
706 gen_op_jz_ecxl_im,
707 };
708
709 static GenOpFunc *gen_op_dec_ECX[2] = {
710 gen_op_decw_ECX,
711 gen_op_decl_ECX,
712 };
713
714 static GenOpFunc1 *gen_op_string_jnz_sub[2][3] = {
715 {
716 gen_op_string_jnz_subb,
717 gen_op_string_jnz_subw,
718 gen_op_string_jnz_subl,
719 },
720 {
721 gen_op_string_jz_subb,
722 gen_op_string_jz_subw,
723 gen_op_string_jz_subl,
724 },
725 };
726
727 static GenOpFunc1 *gen_op_string_jnz_sub_im[2][3] = {
728 {
729 gen_op_string_jnz_subb_im,
730 gen_op_string_jnz_subw_im,
731 gen_op_string_jnz_subl_im,
732 },
733 {
734 gen_op_string_jz_subb_im,
735 gen_op_string_jz_subw_im,
736 gen_op_string_jz_subl_im,
737 },
738 };
739
740 static GenOpFunc *gen_op_in_DX_T0[3] = {
741 gen_op_inb_DX_T0,
742 gen_op_inw_DX_T0,
743 gen_op_inl_DX_T0,
744 };
745
746 static GenOpFunc *gen_op_out_DX_T0[3] = {
747 gen_op_outb_DX_T0,
748 gen_op_outw_DX_T0,
749 gen_op_outl_DX_T0,
750 };
751
752 static inline void gen_movs(DisasContext *s, int ot)
753 {
754 gen_string_movl_A0_ESI(s);
755 gen_op_ld_T0_A0[ot + s->mem_index]();
756 gen_string_movl_A0_EDI(s);
757 gen_op_st_T0_A0[ot + s->mem_index]();
758 gen_op_movl_T0_Dshift[ot]();
759 if (s->aflag) {
760 gen_op_addl_ESI_T0();
761 gen_op_addl_EDI_T0();
762 } else {
763 gen_op_addw_ESI_T0();
764 gen_op_addw_EDI_T0();
765 }
766 }
767
768 static inline void gen_update_cc_op(DisasContext *s)
769 {
770 if (s->cc_op != CC_OP_DYNAMIC) {
771 gen_op_set_cc_op(s->cc_op);
772 s->cc_op = CC_OP_DYNAMIC;
773 }
774 }
775
776 static inline void gen_jz_ecx_string(DisasContext *s, unsigned int next_eip)
777 {
778 if (s->jmp_opt) {
779 gen_op_jz_ecx[s->aflag]((long)s->tb, next_eip);
780 } else {
781 /* XXX: does not work with gdbstub "ice" single step - not a
782 serious problem */
783 gen_op_jz_ecx_im[s->aflag](next_eip);
784 }
785 }
786
787 static inline void gen_stos(DisasContext *s, int ot)
788 {
789 gen_op_mov_TN_reg[OT_LONG][0][R_EAX]();
790 gen_string_movl_A0_EDI(s);
791 gen_op_st_T0_A0[ot + s->mem_index]();
792 gen_op_movl_T0_Dshift[ot]();
793 if (s->aflag) {
794 gen_op_addl_EDI_T0();
795 } else {
796 gen_op_addw_EDI_T0();
797 }
798 }
799
800 static inline void gen_lods(DisasContext *s, int ot)
801 {
802 gen_string_movl_A0_ESI(s);
803 gen_op_ld_T0_A0[ot + s->mem_index]();
804 gen_op_mov_reg_T0[ot][R_EAX]();
805 gen_op_movl_T0_Dshift[ot]();
806 if (s->aflag) {
807 gen_op_addl_ESI_T0();
808 } else {
809 gen_op_addw_ESI_T0();
810 }
811 }
812
813 static inline void gen_scas(DisasContext *s, int ot)
814 {
815 gen_op_mov_TN_reg[OT_LONG][0][R_EAX]();
816 gen_string_movl_A0_EDI(s);
817 gen_op_ld_T1_A0[ot + s->mem_index]();
818 gen_op_cmpl_T0_T1_cc();
819 gen_op_movl_T0_Dshift[ot]();
820 if (s->aflag) {
821 gen_op_addl_EDI_T0();
822 } else {
823 gen_op_addw_EDI_T0();
824 }
825 }
826
827 static inline void gen_cmps(DisasContext *s, int ot)
828 {
829 gen_string_movl_A0_ESI(s);
830 gen_op_ld_T0_A0[ot + s->mem_index]();
831 gen_string_movl_A0_EDI(s);
832 gen_op_ld_T1_A0[ot + s->mem_index]();
833 gen_op_cmpl_T0_T1_cc();
834 gen_op_movl_T0_Dshift[ot]();
835 if (s->aflag) {
836 gen_op_addl_ESI_T0();
837 gen_op_addl_EDI_T0();
838 } else {
839 gen_op_addw_ESI_T0();
840 gen_op_addw_EDI_T0();
841 }
842 }
843
844 static inline void gen_ins(DisasContext *s, int ot)
845 {
846 gen_op_in_DX_T0[ot]();
847 gen_string_movl_A0_EDI(s);
848 gen_op_st_T0_A0[ot + s->mem_index]();
849 gen_op_movl_T0_Dshift[ot]();
850 if (s->aflag) {
851 gen_op_addl_EDI_T0();
852 } else {
853 gen_op_addw_EDI_T0();
854 }
855 }
856
857 static inline void gen_outs(DisasContext *s, int ot)
858 {
859 gen_string_movl_A0_ESI(s);
860 gen_op_ld_T0_A0[ot + s->mem_index]();
861 gen_op_out_DX_T0[ot]();
862 gen_op_movl_T0_Dshift[ot]();
863 if (s->aflag) {
864 gen_op_addl_ESI_T0();
865 } else {
866 gen_op_addw_ESI_T0();
867 }
868 }
869
870 /* same method as Valgrind : we generate jumps to current or next
871 instruction */
872 #define GEN_REPZ(op) \
873 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
874 unsigned int cur_eip, unsigned int next_eip) \
875 { \
876 gen_update_cc_op(s); \
877 gen_jz_ecx_string(s, next_eip); \
878 gen_ ## op(s, ot); \
879 gen_op_dec_ECX[s->aflag](); \
880 /* a loop would cause two single step exceptions if ECX = 1 \
881 before rep string_insn */ \
882 if (!s->jmp_opt) \
883 gen_op_jz_ecx_im[s->aflag](next_eip); \
884 gen_jmp(s, cur_eip); \
885 }
886
887 #define GEN_REPZ2(op) \
888 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
889 unsigned int cur_eip, \
890 unsigned int next_eip, \
891 int nz) \
892 { \
893 gen_update_cc_op(s); \
894 gen_jz_ecx_string(s, next_eip); \
895 gen_ ## op(s, ot); \
896 gen_op_dec_ECX[s->aflag](); \
897 gen_op_set_cc_op(CC_OP_SUBB + ot); \
898 if (!s->jmp_opt) \
899 gen_op_string_jnz_sub_im[nz][ot](next_eip); \
900 else \
901 gen_op_string_jnz_sub[nz][ot]((long)s->tb); \
902 if (!s->jmp_opt) \
903 gen_op_jz_ecx_im[s->aflag](next_eip); \
904 gen_jmp(s, cur_eip); \
905 }
906
907 GEN_REPZ(movs)
908 GEN_REPZ(stos)
909 GEN_REPZ(lods)
910 GEN_REPZ(ins)
911 GEN_REPZ(outs)
912 GEN_REPZ2(scas)
913 GEN_REPZ2(cmps)
914
915 static GenOpFunc *gen_op_in[3] = {
916 gen_op_inb_T0_T1,
917 gen_op_inw_T0_T1,
918 gen_op_inl_T0_T1,
919 };
920
921 static GenOpFunc *gen_op_out[3] = {
922 gen_op_outb_T0_T1,
923 gen_op_outw_T0_T1,
924 gen_op_outl_T0_T1,
925 };
926
927 enum {
928 JCC_O,
929 JCC_B,
930 JCC_Z,
931 JCC_BE,
932 JCC_S,
933 JCC_P,
934 JCC_L,
935 JCC_LE,
936 };
937
938 static GenOpFunc3 *gen_jcc_sub[3][8] = {
939 [OT_BYTE] = {
940 NULL,
941 gen_op_jb_subb,
942 gen_op_jz_subb,
943 gen_op_jbe_subb,
944 gen_op_js_subb,
945 NULL,
946 gen_op_jl_subb,
947 gen_op_jle_subb,
948 },
949 [OT_WORD] = {
950 NULL,
951 gen_op_jb_subw,
952 gen_op_jz_subw,
953 gen_op_jbe_subw,
954 gen_op_js_subw,
955 NULL,
956 gen_op_jl_subw,
957 gen_op_jle_subw,
958 },
959 [OT_LONG] = {
960 NULL,
961 gen_op_jb_subl,
962 gen_op_jz_subl,
963 gen_op_jbe_subl,
964 gen_op_js_subl,
965 NULL,
966 gen_op_jl_subl,
967 gen_op_jle_subl,
968 },
969 };
970 static GenOpFunc2 *gen_op_loop[2][4] = {
971 [0] = {
972 gen_op_loopnzw,
973 gen_op_loopzw,
974 gen_op_loopw,
975 gen_op_jecxzw,
976 },
977 [1] = {
978 gen_op_loopnzl,
979 gen_op_loopzl,
980 gen_op_loopl,
981 gen_op_jecxzl,
982 },
983 };
984
985 static GenOpFunc *gen_setcc_slow[8] = {
986 gen_op_seto_T0_cc,
987 gen_op_setb_T0_cc,
988 gen_op_setz_T0_cc,
989 gen_op_setbe_T0_cc,
990 gen_op_sets_T0_cc,
991 gen_op_setp_T0_cc,
992 gen_op_setl_T0_cc,
993 gen_op_setle_T0_cc,
994 };
995
996 static GenOpFunc *gen_setcc_sub[3][8] = {
997 [OT_BYTE] = {
998 NULL,
999 gen_op_setb_T0_subb,
1000 gen_op_setz_T0_subb,
1001 gen_op_setbe_T0_subb,
1002 gen_op_sets_T0_subb,
1003 NULL,
1004 gen_op_setl_T0_subb,
1005 gen_op_setle_T0_subb,
1006 },
1007 [OT_WORD] = {
1008 NULL,
1009 gen_op_setb_T0_subw,
1010 gen_op_setz_T0_subw,
1011 gen_op_setbe_T0_subw,
1012 gen_op_sets_T0_subw,
1013 NULL,
1014 gen_op_setl_T0_subw,
1015 gen_op_setle_T0_subw,
1016 },
1017 [OT_LONG] = {
1018 NULL,
1019 gen_op_setb_T0_subl,
1020 gen_op_setz_T0_subl,
1021 gen_op_setbe_T0_subl,
1022 gen_op_sets_T0_subl,
1023 NULL,
1024 gen_op_setl_T0_subl,
1025 gen_op_setle_T0_subl,
1026 },
1027 };
1028
1029 static GenOpFunc *gen_op_fp_arith_ST0_FT0[8] = {
1030 gen_op_fadd_ST0_FT0,
1031 gen_op_fmul_ST0_FT0,
1032 gen_op_fcom_ST0_FT0,
1033 gen_op_fcom_ST0_FT0,
1034 gen_op_fsub_ST0_FT0,
1035 gen_op_fsubr_ST0_FT0,
1036 gen_op_fdiv_ST0_FT0,
1037 gen_op_fdivr_ST0_FT0,
1038 };
1039
1040 /* NOTE the exception in "r" op ordering */
1041 static GenOpFunc1 *gen_op_fp_arith_STN_ST0[8] = {
1042 gen_op_fadd_STN_ST0,
1043 gen_op_fmul_STN_ST0,
1044 NULL,
1045 NULL,
1046 gen_op_fsubr_STN_ST0,
1047 gen_op_fsub_STN_ST0,
1048 gen_op_fdivr_STN_ST0,
1049 gen_op_fdiv_STN_ST0,
1050 };
1051
1052 /* if d == OR_TMP0, it means memory operand (address in A0) */
1053 static void gen_op(DisasContext *s1, int op, int ot, int d)
1054 {
1055 GenOpFunc *gen_update_cc;
1056
1057 if (d != OR_TMP0) {
1058 gen_op_mov_TN_reg[ot][0][d]();
1059 } else {
1060 gen_op_ld_T0_A0[ot + s1->mem_index]();
1061 }
1062 switch(op) {
1063 case OP_ADCL:
1064 case OP_SBBL:
1065 if (s1->cc_op != CC_OP_DYNAMIC)
1066 gen_op_set_cc_op(s1->cc_op);
1067 if (d != OR_TMP0) {
1068 gen_op_arithc_T0_T1_cc[ot][op - OP_ADCL]();
1069 gen_op_mov_reg_T0[ot][d]();
1070 } else {
1071 gen_op_arithc_mem_T0_T1_cc[ot][op - OP_ADCL]();
1072 }
1073 s1->cc_op = CC_OP_DYNAMIC;
1074 goto the_end;
1075 case OP_ADDL:
1076 gen_op_addl_T0_T1();
1077 s1->cc_op = CC_OP_ADDB + ot;
1078 gen_update_cc = gen_op_update2_cc;
1079 break;
1080 case OP_SUBL:
1081 gen_op_subl_T0_T1();
1082 s1->cc_op = CC_OP_SUBB + ot;
1083 gen_update_cc = gen_op_update2_cc;
1084 break;
1085 default:
1086 case OP_ANDL:
1087 case OP_ORL:
1088 case OP_XORL:
1089 gen_op_arith_T0_T1_cc[op]();
1090 s1->cc_op = CC_OP_LOGICB + ot;
1091 gen_update_cc = gen_op_update1_cc;
1092 break;
1093 case OP_CMPL:
1094 gen_op_cmpl_T0_T1_cc();
1095 s1->cc_op = CC_OP_SUBB + ot;
1096 gen_update_cc = NULL;
1097 break;
1098 }
1099 if (op != OP_CMPL) {
1100 if (d != OR_TMP0)
1101 gen_op_mov_reg_T0[ot][d]();
1102 else
1103 gen_op_st_T0_A0[ot + s1->mem_index]();
1104 }
1105 /* the flags update must happen after the memory write (precise
1106 exception support) */
1107 if (gen_update_cc)
1108 gen_update_cc();
1109 the_end: ;
1110 }
1111
1112 /* if d == OR_TMP0, it means memory operand (address in A0) */
1113 static void gen_inc(DisasContext *s1, int ot, int d, int c)
1114 {
1115 if (d != OR_TMP0)
1116 gen_op_mov_TN_reg[ot][0][d]();
1117 else
1118 gen_op_ld_T0_A0[ot + s1->mem_index]();
1119 if (s1->cc_op != CC_OP_DYNAMIC)
1120 gen_op_set_cc_op(s1->cc_op);
1121 if (c > 0) {
1122 gen_op_incl_T0();
1123 s1->cc_op = CC_OP_INCB + ot;
1124 } else {
1125 gen_op_decl_T0();
1126 s1->cc_op = CC_OP_DECB + ot;
1127 }
1128 if (d != OR_TMP0)
1129 gen_op_mov_reg_T0[ot][d]();
1130 else
1131 gen_op_st_T0_A0[ot + s1->mem_index]();
1132 gen_op_update_inc_cc();
1133 }
1134
1135 static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1136 {
1137 if (d != OR_TMP0)
1138 gen_op_mov_TN_reg[ot][0][d]();
1139 else
1140 gen_op_ld_T0_A0[ot + s1->mem_index]();
1141 if (s != OR_TMP1)
1142 gen_op_mov_TN_reg[ot][1][s]();
1143 /* for zero counts, flags are not updated, so must do it dynamically */
1144 if (s1->cc_op != CC_OP_DYNAMIC)
1145 gen_op_set_cc_op(s1->cc_op);
1146
1147 if (d != OR_TMP0)
1148 gen_op_shift_T0_T1_cc[ot][op]();
1149 else
1150 gen_op_shift_mem_T0_T1_cc[ot][op]();
1151 if (d != OR_TMP0)
1152 gen_op_mov_reg_T0[ot][d]();
1153 s1->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1154 }
1155
1156 static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1157 {
1158 /* currently not optimized */
1159 gen_op_movl_T1_im(c);
1160 gen_shift(s1, op, ot, d, OR_TMP1);
1161 }
1162
1163 static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
1164 {
1165 int havesib;
1166 int base, disp;
1167 int index;
1168 int scale;
1169 int opreg;
1170 int mod, rm, code, override, must_add_seg;
1171
1172 override = s->override;
1173 must_add_seg = s->addseg;
1174 if (override >= 0)
1175 must_add_seg = 1;
1176 mod = (modrm >> 6) & 3;
1177 rm = modrm & 7;
1178
1179 if (s->aflag) {
1180
1181 havesib = 0;
1182 base = rm;
1183 index = 0;
1184 scale = 0;
1185
1186 if (base == 4) {
1187 havesib = 1;
1188 code = ldub_code(s->pc++);
1189 scale = (code >> 6) & 3;
1190 index = (code >> 3) & 7;
1191 base = code & 7;
1192 }
1193
1194 switch (mod) {
1195 case 0:
1196 if (base == 5) {
1197 base = -1;
1198 disp = ldl_code(s->pc);
1199 s->pc += 4;
1200 } else {
1201 disp = 0;
1202 }
1203 break;
1204 case 1:
1205 disp = (int8_t)ldub_code(s->pc++);
1206 break;
1207 default:
1208 case 2:
1209 disp = ldl_code(s->pc);
1210 s->pc += 4;
1211 break;
1212 }
1213
1214 if (base >= 0) {
1215 /* for correct popl handling with esp */
1216 if (base == 4 && s->popl_esp_hack)
1217 disp += s->popl_esp_hack;
1218 gen_op_movl_A0_reg[base]();
1219 if (disp != 0)
1220 gen_op_addl_A0_im(disp);
1221 } else {
1222 gen_op_movl_A0_im(disp);
1223 }
1224 /* XXX: index == 4 is always invalid */
1225 if (havesib && (index != 4 || scale != 0)) {
1226 gen_op_addl_A0_reg_sN[scale][index]();
1227 }
1228 if (must_add_seg) {
1229 if (override < 0) {
1230 if (base == R_EBP || base == R_ESP)
1231 override = R_SS;
1232 else
1233 override = R_DS;
1234 }
1235 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
1236 }
1237 } else {
1238 switch (mod) {
1239 case 0:
1240 if (rm == 6) {
1241 disp = lduw_code(s->pc);
1242 s->pc += 2;
1243 gen_op_movl_A0_im(disp);
1244 rm = 0; /* avoid SS override */
1245 goto no_rm;
1246 } else {
1247 disp = 0;
1248 }
1249 break;
1250 case 1:
1251 disp = (int8_t)ldub_code(s->pc++);
1252 break;
1253 default:
1254 case 2:
1255 disp = lduw_code(s->pc);
1256 s->pc += 2;
1257 break;
1258 }
1259 switch(rm) {
1260 case 0:
1261 gen_op_movl_A0_reg[R_EBX]();
1262 gen_op_addl_A0_reg_sN[0][R_ESI]();
1263 break;
1264 case 1:
1265 gen_op_movl_A0_reg[R_EBX]();
1266 gen_op_addl_A0_reg_sN[0][R_EDI]();
1267 break;
1268 case 2:
1269 gen_op_movl_A0_reg[R_EBP]();
1270 gen_op_addl_A0_reg_sN[0][R_ESI]();
1271 break;
1272 case 3:
1273 gen_op_movl_A0_reg[R_EBP]();
1274 gen_op_addl_A0_reg_sN[0][R_EDI]();
1275 break;
1276 case 4:
1277 gen_op_movl_A0_reg[R_ESI]();
1278 break;
1279 case 5:
1280 gen_op_movl_A0_reg[R_EDI]();
1281 break;
1282 case 6:
1283 gen_op_movl_A0_reg[R_EBP]();
1284 break;
1285 default:
1286 case 7:
1287 gen_op_movl_A0_reg[R_EBX]();
1288 break;
1289 }
1290 if (disp != 0)
1291 gen_op_addl_A0_im(disp);
1292 gen_op_andl_A0_ffff();
1293 no_rm:
1294 if (must_add_seg) {
1295 if (override < 0) {
1296 if (rm == 2 || rm == 3 || rm == 6)
1297 override = R_SS;
1298 else
1299 override = R_DS;
1300 }
1301 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
1302 }
1303 }
1304
1305 opreg = OR_A0;
1306 disp = 0;
1307 *reg_ptr = opreg;
1308 *offset_ptr = disp;
1309 }
1310
1311 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg !=
1312 OR_TMP0 */
1313 static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
1314 {
1315 int mod, rm, opreg, disp;
1316
1317 mod = (modrm >> 6) & 3;
1318 rm = modrm & 7;
1319 if (mod == 3) {
1320 if (is_store) {
1321 if (reg != OR_TMP0)
1322 gen_op_mov_TN_reg[ot][0][reg]();
1323 gen_op_mov_reg_T0[ot][rm]();
1324 } else {
1325 gen_op_mov_TN_reg[ot][0][rm]();
1326 if (reg != OR_TMP0)
1327 gen_op_mov_reg_T0[ot][reg]();
1328 }
1329 } else {
1330 gen_lea_modrm(s, modrm, &opreg, &disp);
1331 if (is_store) {
1332 if (reg != OR_TMP0)
1333 gen_op_mov_TN_reg[ot][0][reg]();
1334 gen_op_st_T0_A0[ot + s->mem_index]();
1335 } else {
1336 gen_op_ld_T0_A0[ot + s->mem_index]();
1337 if (reg != OR_TMP0)
1338 gen_op_mov_reg_T0[ot][reg]();
1339 }
1340 }
1341 }
1342
1343 static inline uint32_t insn_get(DisasContext *s, int ot)
1344 {
1345 uint32_t ret;
1346
1347 switch(ot) {
1348 case OT_BYTE:
1349 ret = ldub_code(s->pc);
1350 s->pc++;
1351 break;
1352 case OT_WORD:
1353 ret = lduw_code(s->pc);
1354 s->pc += 2;
1355 break;
1356 default:
1357 case OT_LONG:
1358 ret = ldl_code(s->pc);
1359 s->pc += 4;
1360 break;
1361 }
1362 return ret;
1363 }
1364
1365 static inline void gen_jcc(DisasContext *s, int b, int val, int next_eip)
1366 {
1367 TranslationBlock *tb;
1368 int inv, jcc_op;
1369 GenOpFunc3 *func;
1370
1371 inv = b & 1;
1372 jcc_op = (b >> 1) & 7;
1373
1374 if (s->jmp_opt) {
1375 switch(s->cc_op) {
1376 /* we optimize the cmp/jcc case */
1377 case CC_OP_SUBB:
1378 case CC_OP_SUBW:
1379 case CC_OP_SUBL:
1380 func = gen_jcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1381 break;
1382
1383 /* some jumps are easy to compute */
1384 case CC_OP_ADDB:
1385 case CC_OP_ADDW:
1386 case CC_OP_ADDL:
1387 case CC_OP_ADCB:
1388 case CC_OP_ADCW:
1389 case CC_OP_ADCL:
1390 case CC_OP_SBBB:
1391 case CC_OP_SBBW:
1392 case CC_OP_SBBL:
1393 case CC_OP_LOGICB:
1394 case CC_OP_LOGICW:
1395 case CC_OP_LOGICL:
1396 case CC_OP_INCB:
1397 case CC_OP_INCW:
1398 case CC_OP_INCL:
1399 case CC_OP_DECB:
1400 case CC_OP_DECW:
1401 case CC_OP_DECL:
1402 case CC_OP_SHLB:
1403 case CC_OP_SHLW:
1404 case CC_OP_SHLL:
1405 case CC_OP_SARB:
1406 case CC_OP_SARW:
1407 case CC_OP_SARL:
1408 switch(jcc_op) {
1409 case JCC_Z:
1410 func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1411 break;
1412 case JCC_S:
1413 func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1414 break;
1415 default:
1416 func = NULL;
1417 break;
1418 }
1419 break;
1420 default:
1421 func = NULL;
1422 break;
1423 }
1424
1425 if (s->cc_op != CC_OP_DYNAMIC)
1426 gen_op_set_cc_op(s->cc_op);
1427
1428 if (!func) {
1429 gen_setcc_slow[jcc_op]();
1430 func = gen_op_jcc;
1431 }
1432
1433 tb = s->tb;
1434 if (!inv) {
1435 func((long)tb, val, next_eip);
1436 } else {
1437 func((long)tb, next_eip, val);
1438 }
1439 s->is_jmp = 3;
1440 } else {
1441 if (s->cc_op != CC_OP_DYNAMIC) {
1442 gen_op_set_cc_op(s->cc_op);
1443 s->cc_op = CC_OP_DYNAMIC;
1444 }
1445 gen_setcc_slow[jcc_op]();
1446 if (!inv) {
1447 gen_op_jcc_im(val, next_eip);
1448 } else {
1449 gen_op_jcc_im(next_eip, val);
1450 }
1451 gen_eob(s);
1452 }
1453 }
1454
1455 static void gen_setcc(DisasContext *s, int b)
1456 {
1457 int inv, jcc_op;
1458 GenOpFunc *func;
1459
1460 inv = b & 1;
1461 jcc_op = (b >> 1) & 7;
1462 switch(s->cc_op) {
1463 /* we optimize the cmp/jcc case */
1464 case CC_OP_SUBB:
1465 case CC_OP_SUBW:
1466 case CC_OP_SUBL:
1467 func = gen_setcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1468 if (!func)
1469 goto slow_jcc;
1470 break;
1471
1472 /* some jumps are easy to compute */
1473 case CC_OP_ADDB:
1474 case CC_OP_ADDW:
1475 case CC_OP_ADDL:
1476 case CC_OP_LOGICB:
1477 case CC_OP_LOGICW:
1478 case CC_OP_LOGICL:
1479 case CC_OP_INCB:
1480 case CC_OP_INCW:
1481 case CC_OP_INCL:
1482 case CC_OP_DECB:
1483 case CC_OP_DECW:
1484 case CC_OP_DECL:
1485 case CC_OP_SHLB:
1486 case CC_OP_SHLW:
1487 case CC_OP_SHLL:
1488 switch(jcc_op) {
1489 case JCC_Z:
1490 func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1491 break;
1492 case JCC_S:
1493 func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1494 break;
1495 default:
1496 goto slow_jcc;
1497 }
1498 break;
1499 default:
1500 slow_jcc:
1501 if (s->cc_op != CC_OP_DYNAMIC)
1502 gen_op_set_cc_op(s->cc_op);
1503 func = gen_setcc_slow[jcc_op];
1504 break;
1505 }
1506 func();
1507 if (inv) {
1508 gen_op_xor_T0_1();
1509 }
1510 }
1511
1512 /* move T0 to seg_reg and compute if the CPU state may change. Never
1513 call this function with seg_reg == R_CS */
1514 static void gen_movl_seg_T0(DisasContext *s, int seg_reg, unsigned int cur_eip)
1515 {
1516 if (s->pe && !s->vm86)
1517 gen_op_movl_seg_T0(seg_reg, cur_eip);
1518 else
1519 gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[seg_reg]));
1520 /* abort translation because the register may have a non zero base
1521 or because ss32 may change. For R_SS, translation must always
1522 stop as a special handling must be done to disable hardware
1523 interrupts for the next instruction */
1524 if (seg_reg == R_SS || (!s->addseg && seg_reg < R_FS))
1525 s->is_jmp = 3;
1526 }
1527
1528 /* generate a push. It depends on ss32, addseg and dflag */
1529 static void gen_push_T0(DisasContext *s)
1530 {
1531 if (s->ss32) {
1532 if (!s->addseg) {
1533 if (s->dflag)
1534 gen_op_pushl_T0();
1535 else
1536 gen_op_pushw_T0();
1537 } else {
1538 if (s->dflag)
1539 gen_op_pushl_ss32_T0();
1540 else
1541 gen_op_pushw_ss32_T0();
1542 }
1543 } else {
1544 if (s->dflag)
1545 gen_op_pushl_ss16_T0();
1546 else
1547 gen_op_pushw_ss16_T0();
1548 }
1549 }
1550
1551 /* two step pop is necessary for precise exceptions */
1552 static void gen_pop_T0(DisasContext *s)
1553 {
1554 if (s->ss32) {
1555 if (!s->addseg) {
1556 if (s->dflag)
1557 gen_op_popl_T0();
1558 else
1559 gen_op_popw_T0();
1560 } else {
1561 if (s->dflag)
1562 gen_op_popl_ss32_T0();
1563 else
1564 gen_op_popw_ss32_T0();
1565 }
1566 } else {
1567 if (s->dflag)
1568 gen_op_popl_ss16_T0();
1569 else
1570 gen_op_popw_ss16_T0();
1571 }
1572 }
1573
1574 static inline void gen_stack_update(DisasContext *s, int addend)
1575 {
1576 if (s->ss32) {
1577 if (addend == 2)
1578 gen_op_addl_ESP_2();
1579 else if (addend == 4)
1580 gen_op_addl_ESP_4();
1581 else
1582 gen_op_addl_ESP_im(addend);
1583 } else {
1584 if (addend == 2)
1585 gen_op_addw_ESP_2();
1586 else if (addend == 4)
1587 gen_op_addw_ESP_4();
1588 else
1589 gen_op_addw_ESP_im(addend);
1590 }
1591 }
1592
1593 static void gen_pop_update(DisasContext *s)
1594 {
1595 gen_stack_update(s, 2 << s->dflag);
1596 }
1597
1598 static void gen_stack_A0(DisasContext *s)
1599 {
1600 gen_op_movl_A0_ESP();
1601 if (!s->ss32)
1602 gen_op_andl_A0_ffff();
1603 gen_op_movl_T1_A0();
1604 if (s->addseg)
1605 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
1606 }
1607
1608 /* NOTE: wrap around in 16 bit not fully handled */
1609 static void gen_pusha(DisasContext *s)
1610 {
1611 int i;
1612 gen_op_movl_A0_ESP();
1613 gen_op_addl_A0_im(-16 << s->dflag);
1614 if (!s->ss32)
1615 gen_op_andl_A0_ffff();
1616 gen_op_movl_T1_A0();
1617 if (s->addseg)
1618 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
1619 for(i = 0;i < 8; i++) {
1620 gen_op_mov_TN_reg[OT_LONG][0][7 - i]();
1621 gen_op_st_T0_A0[OT_WORD + s->dflag + s->mem_index]();
1622 gen_op_addl_A0_im(2 << s->dflag);
1623 }
1624 gen_op_mov_reg_T1[OT_WORD + s->dflag][R_ESP]();
1625 }
1626
1627 /* NOTE: wrap around in 16 bit not fully handled */
1628 static void gen_popa(DisasContext *s)
1629 {
1630 int i;
1631 gen_op_movl_A0_ESP();
1632 if (!s->ss32)
1633 gen_op_andl_A0_ffff();
1634 gen_op_movl_T1_A0();
1635 gen_op_addl_T1_im(16 << s->dflag);
1636 if (s->addseg)
1637 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
1638 for(i = 0;i < 8; i++) {
1639 /* ESP is not reloaded */
1640 if (i != 3) {
1641 gen_op_ld_T0_A0[OT_WORD + s->dflag + s->mem_index]();
1642 gen_op_mov_reg_T0[OT_WORD + s->dflag][7 - i]();
1643 }
1644 gen_op_addl_A0_im(2 << s->dflag);
1645 }
1646 gen_op_mov_reg_T1[OT_WORD + s->dflag][R_ESP]();
1647 }
1648
1649 /* NOTE: wrap around in 16 bit not fully handled */
1650 /* XXX: check this */
1651 static void gen_enter(DisasContext *s, int esp_addend, int level)
1652 {
1653 int ot, level1, addend, opsize;
1654
1655 ot = s->dflag + OT_WORD;
1656 level &= 0x1f;
1657 level1 = level;
1658 opsize = 2 << s->dflag;
1659
1660 gen_op_movl_A0_ESP();
1661 gen_op_addl_A0_im(-opsize);
1662 if (!s->ss32)
1663 gen_op_andl_A0_ffff();
1664 gen_op_movl_T1_A0();
1665 if (s->addseg)
1666 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
1667 /* push bp */
1668 gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
1669 gen_op_st_T0_A0[ot + s->mem_index]();
1670 if (level) {
1671 while (level--) {
1672 gen_op_addl_A0_im(-opsize);
1673 gen_op_addl_T0_im(-opsize);
1674 gen_op_st_T0_A0[ot + s->mem_index]();
1675 }
1676 gen_op_addl_A0_im(-opsize);
1677 /* XXX: add st_T1_A0 ? */
1678 gen_op_movl_T0_T1();
1679 gen_op_st_T0_A0[ot + s->mem_index]();
1680 }
1681 gen_op_mov_reg_T1[ot][R_EBP]();
1682 addend = -esp_addend;
1683 if (level1)
1684 addend -= opsize * (level1 + 1);
1685 gen_op_addl_T1_im(addend);
1686 gen_op_mov_reg_T1[ot][R_ESP]();
1687 }
1688
1689 static void gen_exception(DisasContext *s, int trapno, unsigned int cur_eip)
1690 {
1691 if (s->cc_op != CC_OP_DYNAMIC)
1692 gen_op_set_cc_op(s->cc_op);
1693 gen_op_jmp_im(cur_eip);
1694 gen_op_raise_exception(trapno);
1695 s->is_jmp = 3;
1696 }
1697
1698 /* an interrupt is different from an exception because of the
1699 priviledge checks */
1700 static void gen_interrupt(DisasContext *s, int intno,
1701 unsigned int cur_eip, unsigned int next_eip)
1702 {
1703 if (s->cc_op != CC_OP_DYNAMIC)
1704 gen_op_set_cc_op(s->cc_op);
1705 gen_op_jmp_im(cur_eip);
1706 gen_op_raise_interrupt(intno, next_eip);
1707 s->is_jmp = 3;
1708 }
1709
1710 static void gen_debug(DisasContext *s, unsigned int cur_eip)
1711 {
1712 if (s->cc_op != CC_OP_DYNAMIC)
1713 gen_op_set_cc_op(s->cc_op);
1714 gen_op_jmp_im(cur_eip);
1715 gen_op_debug();
1716 s->is_jmp = 3;
1717 }
1718
1719 /* generate a generic end of block. Trace exception is also generated
1720 if needed */
1721 static void gen_eob(DisasContext *s)
1722 {
1723 if (s->cc_op != CC_OP_DYNAMIC)
1724 gen_op_set_cc_op(s->cc_op);
1725 if (s->singlestep_enabled) {
1726 gen_op_debug();
1727 } else if (s->tf) {
1728 gen_op_raise_exception(EXCP01_SSTP);
1729 } else {
1730 gen_op_movl_T0_0();
1731 gen_op_exit_tb();
1732 }
1733 s->is_jmp = 3;
1734 }
1735
1736 /* generate a jump to eip. No segment change must happen before as a
1737 direct call to the next block may occur */
1738 static void gen_jmp(DisasContext *s, unsigned int eip)
1739 {
1740 TranslationBlock *tb = s->tb;
1741
1742 if (s->jmp_opt) {
1743 if (s->cc_op != CC_OP_DYNAMIC)
1744 gen_op_set_cc_op(s->cc_op);
1745 gen_op_jmp((long)tb, eip);
1746 s->is_jmp = 3;
1747 } else {
1748 gen_op_jmp_im(eip);
1749 gen_eob(s);
1750 }
1751 }
1752
1753 /* convert one instruction. s->is_jmp is set if the translation must
1754 be stopped. Return the next pc value */
1755 static uint8_t *disas_insn(DisasContext *s, uint8_t *pc_start)
1756 {
1757 int b, prefixes, aflag, dflag;
1758 int shift, ot;
1759 int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
1760 unsigned int next_eip;
1761
1762 s->pc = pc_start;
1763 prefixes = 0;
1764 aflag = s->code32;
1765 dflag = s->code32;
1766 s->override = -1;
1767 next_byte:
1768 b = ldub_code(s->pc);
1769 s->pc++;
1770 /* check prefixes */
1771 switch (b) {
1772 case 0xf3:
1773 prefixes |= PREFIX_REPZ;
1774 goto next_byte;
1775 case 0xf2:
1776 prefixes |= PREFIX_REPNZ;
1777 goto next_byte;
1778 case 0xf0:
1779 prefixes |= PREFIX_LOCK;
1780 goto next_byte;
1781 case 0x2e:
1782 s->override = R_CS;
1783 goto next_byte;
1784 case 0x36:
1785 s->override = R_SS;
1786 goto next_byte;
1787 case 0x3e:
1788 s->override = R_DS;
1789 goto next_byte;
1790 case 0x26:
1791 s->override = R_ES;
1792 goto next_byte;
1793 case 0x64:
1794 s->override = R_FS;
1795 goto next_byte;
1796 case 0x65:
1797 s->override = R_GS;
1798 goto next_byte;
1799 case 0x66:
1800 prefixes |= PREFIX_DATA;
1801 goto next_byte;
1802 case 0x67:
1803 prefixes |= PREFIX_ADR;
1804 goto next_byte;
1805 }
1806
1807 if (prefixes & PREFIX_DATA)
1808 dflag ^= 1;
1809 if (prefixes & PREFIX_ADR)
1810 aflag ^= 1;
1811
1812 s->prefix = prefixes;
1813 s->aflag = aflag;
1814 s->dflag = dflag;
1815
1816 /* lock generation */
1817 if (prefixes & PREFIX_LOCK)
1818 gen_op_lock();
1819
1820 /* now check op code */
1821 reswitch:
1822 switch(b) {
1823 case 0x0f:
1824 /**************************/
1825 /* extended op code */
1826 b = ldub_code(s->pc++) | 0x100;
1827 goto reswitch;
1828
1829 /**************************/
1830 /* arith & logic */
1831 case 0x00 ... 0x05:
1832 case 0x08 ... 0x0d:
1833 case 0x10 ... 0x15:
1834 case 0x18 ... 0x1d:
1835 case 0x20 ... 0x25:
1836 case 0x28 ... 0x2d:
1837 case 0x30 ... 0x35:
1838 case 0x38 ... 0x3d:
1839 {
1840 int op, f, val;
1841 op = (b >> 3) & 7;
1842 f = (b >> 1) & 3;
1843
1844 if ((b & 1) == 0)
1845 ot = OT_BYTE;
1846 else
1847 ot = dflag ? OT_LONG : OT_WORD;
1848
1849 switch(f) {
1850 case 0: /* OP Ev, Gv */
1851 modrm = ldub_code(s->pc++);
1852 reg = ((modrm >> 3) & 7);
1853 mod = (modrm >> 6) & 3;
1854 rm = modrm & 7;
1855 if (mod != 3) {
1856 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1857 opreg = OR_TMP0;
1858 } else if (op == OP_XORL && rm == reg) {
1859 xor_zero:
1860 /* xor reg, reg optimisation */
1861 gen_op_movl_T0_0();
1862 s->cc_op = CC_OP_LOGICB + ot;
1863 gen_op_mov_reg_T0[ot][reg]();
1864 gen_op_update1_cc();
1865 break;
1866 } else {
1867 opreg = rm;
1868 }
1869 gen_op_mov_TN_reg[ot][1][reg]();
1870 gen_op(s, op, ot, opreg);
1871 break;
1872 case 1: /* OP Gv, Ev */
1873 modrm = ldub_code(s->pc++);
1874 mod = (modrm >> 6) & 3;
1875 reg = ((modrm >> 3) & 7);
1876 rm = modrm & 7;
1877 if (mod != 3) {
1878 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1879 gen_op_ld_T1_A0[ot + s->mem_index]();
1880 } else if (op == OP_XORL && rm == reg) {
1881 goto xor_zero;
1882 } else {
1883 gen_op_mov_TN_reg[ot][1][rm]();
1884 }
1885 gen_op(s, op, ot, reg);
1886 break;
1887 case 2: /* OP A, Iv */
1888 val = insn_get(s, ot);
1889 gen_op_movl_T1_im(val);
1890 gen_op(s, op, ot, OR_EAX);
1891 break;
1892 }
1893 }
1894 break;
1895
1896 case 0x80: /* GRP1 */
1897 case 0x81:
1898 case 0x83:
1899 {
1900 int val;
1901
1902 if ((b & 1) == 0)
1903 ot = OT_BYTE;
1904 else
1905 ot = dflag ? OT_LONG : OT_WORD;
1906
1907 modrm = ldub_code(s->pc++);
1908 mod = (modrm >> 6) & 3;
1909 rm = modrm & 7;
1910 op = (modrm >> 3) & 7;
1911
1912 if (mod != 3) {
1913 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1914 opreg = OR_TMP0;
1915 } else {
1916 opreg = rm + OR_EAX;
1917 }
1918
1919 switch(b) {
1920 default:
1921 case 0x80:
1922 case 0x81:
1923 val = insn_get(s, ot);
1924 break;
1925 case 0x83:
1926 val = (int8_t)insn_get(s, OT_BYTE);
1927 break;
1928 }
1929 gen_op_movl_T1_im(val);
1930 gen_op(s, op, ot, opreg);
1931 }
1932 break;
1933
1934 /**************************/
1935 /* inc, dec, and other misc arith */
1936 case 0x40 ... 0x47: /* inc Gv */
1937 ot = dflag ? OT_LONG : OT_WORD;
1938 gen_inc(s, ot, OR_EAX + (b & 7), 1);
1939 break;
1940 case 0x48 ... 0x4f: /* dec Gv */
1941 ot = dflag ? OT_LONG : OT_WORD;
1942 gen_inc(s, ot, OR_EAX + (b & 7), -1);
1943 break;
1944 case 0xf6: /* GRP3 */
1945 case 0xf7:
1946 if ((b & 1) == 0)
1947 ot = OT_BYTE;
1948 else
1949 ot = dflag ? OT_LONG : OT_WORD;
1950
1951 modrm = ldub_code(s->pc++);
1952 mod = (modrm >> 6) & 3;
1953 rm = modrm & 7;
1954 op = (modrm >> 3) & 7;
1955 if (mod != 3) {
1956 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1957 gen_op_ld_T0_A0[ot + s->mem_index]();
1958 } else {
1959 gen_op_mov_TN_reg[ot][0][rm]();
1960 }
1961
1962 switch(op) {
1963 case 0: /* test */
1964 val = insn_get(s, ot);
1965 gen_op_movl_T1_im(val);
1966 gen_op_testl_T0_T1_cc();
1967 s->cc_op = CC_OP_LOGICB + ot;
1968 break;
1969 case 2: /* not */
1970 gen_op_notl_T0();
1971 if (mod != 3) {
1972 gen_op_st_T0_A0[ot + s->mem_index]();
1973 } else {
1974 gen_op_mov_reg_T0[ot][rm]();
1975 }
1976 break;
1977 case 3: /* neg */
1978 gen_op_negl_T0();
1979 if (mod != 3) {
1980 gen_op_st_T0_A0[ot + s->mem_index]();
1981 } else {
1982 gen_op_mov_reg_T0[ot][rm]();
1983 }
1984 gen_op_update_neg_cc();
1985 s->cc_op = CC_OP_SUBB + ot;
1986 break;
1987 case 4: /* mul */
1988 switch(ot) {
1989 case OT_BYTE:
1990 gen_op_mulb_AL_T0();
1991 break;
1992 case OT_WORD:
1993 gen_op_mulw_AX_T0();
1994 break;
1995 default:
1996 case OT_LONG:
1997 gen_op_mull_EAX_T0();
1998 break;
1999 }
2000 s->cc_op = CC_OP_MUL;
2001 break;
2002 case 5: /* imul */
2003 switch(ot) {
2004 case OT_BYTE:
2005 gen_op_imulb_AL_T0();
2006 break;
2007 case OT_WORD:
2008 gen_op_imulw_AX_T0();
2009 break;
2010 default:
2011 case OT_LONG:
2012 gen_op_imull_EAX_T0();
2013 break;
2014 }
2015 s->cc_op = CC_OP_MUL;
2016 break;
2017 case 6: /* div */
2018 switch(ot) {
2019 case OT_BYTE:
2020 gen_op_divb_AL_T0(pc_start - s->cs_base);
2021 break;
2022 case OT_WORD:
2023 gen_op_divw_AX_T0(pc_start - s->cs_base);
2024 break;
2025 default:
2026 case OT_LONG:
2027 gen_op_divl_EAX_T0(pc_start - s->cs_base);
2028 break;
2029 }
2030 break;
2031 case 7: /* idiv */
2032 switch(ot) {
2033 case OT_BYTE:
2034 gen_op_idivb_AL_T0(pc_start - s->cs_base);
2035 break;
2036 case OT_WORD:
2037 gen_op_idivw_AX_T0(pc_start - s->cs_base);
2038 break;
2039 default:
2040 case OT_LONG:
2041 gen_op_idivl_EAX_T0(pc_start - s->cs_base);
2042 break;
2043 }
2044 break;
2045 default:
2046 goto illegal_op;
2047 }
2048 break;
2049
2050 case 0xfe: /* GRP4 */
2051 case 0xff: /* GRP5 */
2052 if ((b & 1) == 0)
2053 ot = OT_BYTE;
2054 else
2055 ot = dflag ? OT_LONG : OT_WORD;
2056
2057 modrm = ldub_code(s->pc++);
2058 mod = (modrm >> 6) & 3;
2059 rm = modrm & 7;
2060 op = (modrm >> 3) & 7;
2061 if (op >= 2 && b == 0xfe) {
2062 goto illegal_op;
2063 }
2064 if (mod != 3) {
2065 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2066 if (op >= 2 && op != 3 && op != 5)
2067 gen_op_ld_T0_A0[ot + s->mem_index]();
2068 } else {
2069 gen_op_mov_TN_reg[ot][0][rm]();
2070 }
2071
2072 switch(op) {
2073 case 0: /* inc Ev */
2074 if (mod != 3)
2075 opreg = OR_TMP0;
2076 else
2077 opreg = rm;
2078 gen_inc(s, ot, opreg, 1);
2079 break;
2080 case 1: /* dec Ev */
2081 if (mod != 3)
2082 opreg = OR_TMP0;
2083 else
2084 opreg = rm;
2085 gen_inc(s, ot, opreg, -1);
2086 break;
2087 case 2: /* call Ev */
2088 /* XXX: optimize if memory (no and is necessary) */
2089 if (s->dflag == 0)
2090 gen_op_andl_T0_ffff();
2091 gen_op_jmp_T0();
2092 next_eip = s->pc - s->cs_base;
2093 gen_op_movl_T0_im(next_eip);
2094 gen_push_T0(s);
2095 gen_eob(s);
2096 break;
2097 case 3: /* lcall Ev */
2098 gen_op_ld_T1_A0[ot + s->mem_index]();
2099 gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
2100 gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
2101 do_lcall:
2102 if (s->pe && !s->vm86) {
2103 if (s->cc_op != CC_OP_DYNAMIC)
2104 gen_op_set_cc_op(s->cc_op);
2105 gen_op_jmp_im(pc_start - s->cs_base);
2106 gen_op_lcall_protected_T0_T1(dflag, s->pc - s->cs_base);
2107 } else {
2108 gen_op_lcall_real_T0_T1(dflag, s->pc - s->cs_base);
2109 }
2110 gen_eob(s);
2111 break;
2112 case 4: /* jmp Ev */
2113 if (s->dflag == 0)
2114 gen_op_andl_T0_ffff();
2115 gen_op_jmp_T0();
2116 gen_eob(s);
2117 break;
2118 case 5: /* ljmp Ev */
2119 gen_op_ld_T1_A0[ot + s->mem_index]();
2120 gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
2121 gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
2122 do_ljmp:
2123 if (s->pe && !s->vm86) {
2124 if (s->cc_op != CC_OP_DYNAMIC)
2125 gen_op_set_cc_op(s->cc_op);
2126 gen_op_jmp_im(pc_start - s->cs_base);
2127 gen_op_ljmp_protected_T0_T1();
2128 } else {
2129 gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
2130 gen_op_movl_T0_T1();
2131 gen_op_jmp_T0();
2132 }
2133 gen_eob(s);
2134 break;
2135 case 6: /* push Ev */
2136 gen_push_T0(s);
2137 break;
2138 default:
2139 goto illegal_op;
2140 }
2141 break;
2142
2143 case 0x84: /* test Ev, Gv */
2144 case 0x85:
2145 if ((b & 1) == 0)
2146 ot = OT_BYTE;
2147 else
2148 ot = dflag ? OT_LONG : OT_WORD;
2149
2150 modrm = ldub_code(s->pc++);
2151 mod = (modrm >> 6) & 3;
2152 rm = modrm & 7;
2153 reg = (modrm >> 3) & 7;
2154
2155 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2156 gen_op_mov_TN_reg[ot][1][reg + OR_EAX]();
2157 gen_op_testl_T0_T1_cc();
2158 s->cc_op = CC_OP_LOGICB + ot;
2159 break;
2160
2161 case 0xa8: /* test eAX, Iv */
2162 case 0xa9:
2163 if ((b & 1) == 0)
2164 ot = OT_BYTE;
2165 else
2166 ot = dflag ? OT_LONG : OT_WORD;
2167 val = insn_get(s, ot);
2168
2169 gen_op_mov_TN_reg[ot][0][OR_EAX]();
2170 gen_op_movl_T1_im(val);
2171 gen_op_testl_T0_T1_cc();
2172 s->cc_op = CC_OP_LOGICB + ot;
2173 break;
2174
2175 case 0x98: /* CWDE/CBW */
2176 if (dflag)
2177 gen_op_movswl_EAX_AX();
2178 else
2179 gen_op_movsbw_AX_AL();
2180 break;
2181 case 0x99: /* CDQ/CWD */
2182 if (dflag)
2183 gen_op_movslq_EDX_EAX();
2184 else
2185 gen_op_movswl_DX_AX();
2186 break;
2187 case 0x1af: /* imul Gv, Ev */
2188 case 0x69: /* imul Gv, Ev, I */
2189 case 0x6b:
2190 ot = dflag ? OT_LONG : OT_WORD;
2191 modrm = ldub_code(s->pc++);
2192 reg = ((modrm >> 3) & 7) + OR_EAX;
2193 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2194 if (b == 0x69) {
2195 val = insn_get(s, ot);
2196 gen_op_movl_T1_im(val);
2197 } else if (b == 0x6b) {
2198 val = insn_get(s, OT_BYTE);
2199 gen_op_movl_T1_im(val);
2200 } else {
2201 gen_op_mov_TN_reg[ot][1][reg]();
2202 }
2203
2204 if (ot == OT_LONG) {
2205 gen_op_imull_T0_T1();
2206 } else {
2207 gen_op_imulw_T0_T1();
2208 }
2209 gen_op_mov_reg_T0[ot][reg]();
2210 s->cc_op = CC_OP_MUL;
2211 break;
2212 case 0x1c0:
2213 case 0x1c1: /* xadd Ev, Gv */
2214 if ((b & 1) == 0)
2215 ot = OT_BYTE;
2216 else
2217 ot = dflag ? OT_LONG : OT_WORD;
2218 modrm = ldub_code(s->pc++);
2219 reg = (modrm >> 3) & 7;
2220 mod = (modrm >> 6) & 3;
2221 if (mod == 3) {
2222 rm = modrm & 7;
2223 gen_op_mov_TN_reg[ot][0][reg]();
2224 gen_op_mov_TN_reg[ot][1][rm]();
2225 gen_op_addl_T0_T1();
2226 gen_op_mov_reg_T0[ot][rm]();
2227 gen_op_mov_reg_T1[ot][reg]();
2228 } else {
2229 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2230 gen_op_mov_TN_reg[ot][0][reg]();
2231 gen_op_ld_T1_A0[ot + s->mem_index]();
2232 gen_op_addl_T0_T1();
2233 gen_op_st_T0_A0[ot + s->mem_index]();
2234 gen_op_mov_reg_T1[ot][reg]();
2235 }
2236 gen_op_update2_cc();
2237 s->cc_op = CC_OP_ADDB + ot;
2238 break;
2239 case 0x1b0:
2240 case 0x1b1: /* cmpxchg Ev, Gv */
2241 if ((b & 1) == 0)
2242 ot = OT_BYTE;
2243 else
2244 ot = dflag ? OT_LONG : OT_WORD;
2245 modrm = ldub_code(s->pc++);
2246 reg = (modrm >> 3) & 7;
2247 mod = (modrm >> 6) & 3;
2248 gen_op_mov_TN_reg[ot][1][reg]();
2249 if (mod == 3) {
2250 rm = modrm & 7;
2251 gen_op_mov_TN_reg[ot][0][rm]();
2252 gen_op_cmpxchg_T0_T1_EAX_cc[ot]();
2253 gen_op_mov_reg_T0[ot][rm]();
2254 } else {
2255 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2256 gen_op_ld_T0_A0[ot + s->mem_index]();
2257 gen_op_cmpxchg_mem_T0_T1_EAX_cc[ot]();
2258 }
2259 s->cc_op = CC_OP_SUBB + ot;
2260 break;
2261 case 0x1c7: /* cmpxchg8b */
2262 modrm = ldub_code(s->pc++);
2263 mod = (modrm >> 6) & 3;
2264 if (mod == 3)
2265 goto illegal_op;
2266 if (s->cc_op != CC_OP_DYNAMIC)
2267 gen_op_set_cc_op(s->cc_op);
2268 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2269 gen_op_cmpxchg8b();
2270 s->cc_op = CC_OP_EFLAGS;
2271 break;
2272
2273 /**************************/
2274 /* push/pop */
2275 case 0x50 ... 0x57: /* push */
2276 gen_op_mov_TN_reg[OT_LONG][0][b & 7]();
2277 gen_push_T0(s);
2278 break;
2279 case 0x58 ... 0x5f: /* pop */
2280 ot = dflag ? OT_LONG : OT_WORD;
2281 gen_pop_T0(s);
2282 gen_op_mov_reg_T0[ot][b & 7]();
2283 gen_pop_update(s);
2284 break;
2285 case 0x60: /* pusha */
2286 gen_pusha(s);
2287 break;
2288 case 0x61: /* popa */
2289 gen_popa(s);
2290 break;
2291 case 0x68: /* push Iv */
2292 case 0x6a:
2293 ot = dflag ? OT_LONG : OT_WORD;
2294 if (b == 0x68)
2295 val = insn_get(s, ot);
2296 else
2297 val = (int8_t)insn_get(s, OT_BYTE);
2298 gen_op_movl_T0_im(val);
2299 gen_push_T0(s);
2300 break;
2301 case 0x8f: /* pop Ev */
2302 ot = dflag ? OT_LONG : OT_WORD;
2303 modrm = ldub_code(s->pc++);
2304 gen_pop_T0(s);
2305 s->popl_esp_hack = 2 << dflag;
2306 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
2307 s->popl_esp_hack = 0;
2308 gen_pop_update(s);
2309 break;
2310 case 0xc8: /* enter */
2311 {
2312 int level;
2313 val = lduw_code(s->pc);
2314 s->pc += 2;
2315 level = ldub_code(s->pc++);
2316 gen_enter(s, val, level);
2317 }
2318 break;
2319 case 0xc9: /* leave */
2320 /* XXX: exception not precise (ESP is updated before potential exception) */
2321 if (s->ss32) {
2322 gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
2323 gen_op_mov_reg_T0[OT_LONG][R_ESP]();
2324 } else {
2325 gen_op_mov_TN_reg[OT_WORD][0][R_EBP]();
2326 gen_op_mov_reg_T0[OT_WORD][R_ESP]();
2327 }
2328 gen_pop_T0(s);
2329 ot = dflag ? OT_LONG : OT_WORD;
2330 gen_op_mov_reg_T0[ot][R_EBP]();
2331 gen_pop_update(s);
2332 break;
2333 case 0x06: /* push es */
2334 case 0x0e: /* push cs */
2335 case 0x16: /* push ss */
2336 case 0x1e: /* push ds */
2337 gen_op_movl_T0_seg(b >> 3);
2338 gen_push_T0(s);
2339 break;
2340 case 0x1a0: /* push fs */
2341 case 0x1a8: /* push gs */
2342 gen_op_movl_T0_seg((b >> 3) & 7);
2343 gen_push_T0(s);
2344 break;
2345 case 0x07: /* pop es */
2346 case 0x17: /* pop ss */
2347 case 0x1f: /* pop ds */
2348 reg = b >> 3;
2349 gen_pop_T0(s);
2350 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
2351 gen_pop_update(s);
2352 if (reg == R_SS) {
2353 /* if reg == SS, inhibit interrupts/trace */
2354 gen_op_set_inhibit_irq();
2355 s->tf = 0;
2356 }
2357 if (s->is_jmp) {
2358 gen_op_jmp_im(s->pc - s->cs_base);
2359 gen_eob(s);
2360 }
2361 break;
2362 case 0x1a1: /* pop fs */
2363 case 0x1a9: /* pop gs */
2364 gen_pop_T0(s);
2365 gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
2366 gen_pop_update(s);
2367 if (s->is_jmp) {
2368 gen_op_jmp_im(s->pc - s->cs_base);
2369 gen_eob(s);
2370 }
2371 break;
2372
2373 /**************************/
2374 /* mov */
2375 case 0x88:
2376 case 0x89: /* mov Gv, Ev */
2377 if ((b & 1) == 0)
2378 ot = OT_BYTE;
2379 else
2380 ot = dflag ? OT_LONG : OT_WORD;
2381 modrm = ldub_code(s->pc++);
2382 reg = (modrm >> 3) & 7;
2383
2384 /* generate a generic store */
2385 gen_ldst_modrm(s, modrm, ot, OR_EAX + reg, 1);
2386 break;
2387 case 0xc6:
2388 case 0xc7: /* mov Ev, Iv */
2389 if ((b & 1) == 0)
2390 ot = OT_BYTE;
2391 else
2392 ot = dflag ? OT_LONG : OT_WORD;
2393 modrm = ldub_code(s->pc++);
2394 mod = (modrm >> 6) & 3;
2395 if (mod != 3)
2396 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2397 val = insn_get(s, ot);
2398 gen_op_movl_T0_im(val);
2399 if (mod != 3)
2400 gen_op_st_T0_A0[ot + s->mem_index]();
2401 else
2402 gen_op_mov_reg_T0[ot][modrm & 7]();
2403 break;
2404 case 0x8a:
2405 case 0x8b: /* mov Ev, Gv */
2406 if ((b & 1) == 0)
2407 ot = OT_BYTE;
2408 else
2409 ot = dflag ? OT_LONG : OT_WORD;
2410 modrm = ldub_code(s->pc++);
2411 reg = (modrm >> 3) & 7;
2412
2413 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2414 gen_op_mov_reg_T0[ot][reg]();
2415 break;
2416 case 0x8e: /* mov seg, Gv */
2417 modrm = ldub_code(s->pc++);
2418 reg = (modrm >> 3) & 7;
2419 if (reg >= 6 || reg == R_CS)
2420 goto illegal_op;
2421 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
2422 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
2423 if (reg == R_SS) {
2424 /* if reg == SS, inhibit interrupts/trace */
2425 gen_op_set_inhibit_irq();
2426 s->tf = 0;
2427 }
2428 if (s->is_jmp) {
2429 gen_op_jmp_im(s->pc - s->cs_base);
2430 gen_eob(s);
2431 }
2432 break;
2433 case 0x8c: /* mov Gv, seg */
2434 modrm = ldub_code(s->pc++);
2435 reg = (modrm >> 3) & 7;
2436 mod = (modrm >> 6) & 3;
2437 if (reg >= 6)
2438 goto illegal_op;
2439 gen_op_movl_T0_seg(reg);
2440 ot = OT_WORD;
2441 if (mod == 3 && dflag)
2442 ot = OT_LONG;
2443 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
2444 break;
2445
2446 case 0x1b6: /* movzbS Gv, Eb */
2447 case 0x1b7: /* movzwS Gv, Eb */
2448 case 0x1be: /* movsbS Gv, Eb */
2449 case 0x1bf: /* movswS Gv, Eb */
2450 {
2451 int d_ot;
2452 /* d_ot is the size of destination */
2453 d_ot = dflag + OT_WORD;
2454 /* ot is the size of source */
2455 ot = (b & 1) + OT_BYTE;
2456 modrm = ldub_code(s->pc++);
2457 reg = ((modrm >> 3) & 7) + OR_EAX;
2458 mod = (modrm >> 6) & 3;
2459 rm = modrm & 7;
2460
2461 if (mod == 3) {
2462 gen_op_mov_TN_reg[ot][0][rm]();
2463 switch(ot | (b & 8)) {
2464 case OT_BYTE:
2465 gen_op_movzbl_T0_T0();
2466 break;
2467 case OT_BYTE | 8:
2468 gen_op_movsbl_T0_T0();
2469 break;
2470 case OT_WORD:
2471 gen_op_movzwl_T0_T0();
2472 break;
2473 default:
2474 case OT_WORD | 8:
2475 gen_op_movswl_T0_T0();
2476 break;
2477 }
2478 gen_op_mov_reg_T0[d_ot][reg]();
2479 } else {
2480 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2481 if (b & 8) {
2482 gen_op_lds_T0_A0[ot + s->mem_index]();
2483 } else {
2484 gen_op_ldu_T0_A0[ot + s->mem_index]();
2485 }
2486 gen_op_mov_reg_T0[d_ot][reg]();
2487 }
2488 }
2489 break;
2490
2491 case 0x8d: /* lea */
2492 ot = dflag ? OT_LONG : OT_WORD;
2493 modrm = ldub_code(s->pc++);
2494 reg = (modrm >> 3) & 7;
2495 /* we must ensure that no segment is added */
2496 s->override = -1;
2497 val = s->addseg;
2498 s->addseg = 0;
2499 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2500 s->addseg = val;
2501 gen_op_mov_reg_A0[ot - OT_WORD][reg]();
2502 break;
2503
2504 case 0xa0: /* mov EAX, Ov */
2505 case 0xa1:
2506 case 0xa2: /* mov Ov, EAX */
2507 case 0xa3:
2508 if ((b & 1) == 0)
2509 ot = OT_BYTE;
2510 else
2511 ot = dflag ? OT_LONG : OT_WORD;
2512 if (s->aflag)
2513 offset_addr = insn_get(s, OT_LONG);
2514 else
2515 offset_addr = insn_get(s, OT_WORD);
2516 gen_op_movl_A0_im(offset_addr);
2517 /* handle override */
2518 {
2519 int override, must_add_seg;
2520 must_add_seg = s->addseg;
2521 if (s->override >= 0) {
2522 override = s->override;
2523 must_add_seg = 1;
2524 } else {
2525 override = R_DS;
2526 }
2527 if (must_add_seg) {
2528 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
2529 }
2530 }
2531 if ((b & 2) == 0) {
2532 gen_op_ld_T0_A0[ot + s->mem_index]();
2533 gen_op_mov_reg_T0[ot][R_EAX]();
2534 } else {
2535 gen_op_mov_TN_reg[ot][0][R_EAX]();
2536 gen_op_st_T0_A0[ot + s->mem_index]();
2537 }
2538 break;
2539 case 0xd7: /* xlat */
2540 gen_op_movl_A0_reg[R_EBX]();
2541 gen_op_addl_A0_AL();
2542 if (s->aflag == 0)
2543 gen_op_andl_A0_ffff();
2544 /* handle override */
2545 {
2546 int override, must_add_seg;
2547 must_add_seg = s->addseg;
2548 override = R_DS;
2549 if (s->override >= 0) {
2550 override = s->override;
2551 must_add_seg = 1;
2552 } else {
2553 override = R_DS;
2554 }
2555 if (must_add_seg) {
2556 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
2557 }
2558 }
2559 gen_op_ldu_T0_A0[OT_BYTE + s->mem_index]();
2560 gen_op_mov_reg_T0[OT_BYTE][R_EAX]();
2561 break;
2562 case 0xb0 ... 0xb7: /* mov R, Ib */
2563 val = insn_get(s, OT_BYTE);
2564 gen_op_movl_T0_im(val);
2565 gen_op_mov_reg_T0[OT_BYTE][b & 7]();
2566 break;
2567 case 0xb8 ... 0xbf: /* mov R, Iv */
2568 ot = dflag ? OT_LONG : OT_WORD;
2569 val = insn_get(s, ot);
2570 reg = OR_EAX + (b & 7);
2571 gen_op_movl_T0_im(val);
2572 gen_op_mov_reg_T0[ot][reg]();
2573 break;
2574
2575 case 0x91 ... 0x97: /* xchg R, EAX */
2576 ot = dflag ? OT_LONG : OT_WORD;
2577 reg = b & 7;
2578 rm = R_EAX;
2579 goto do_xchg_reg;
2580 case 0x86:
2581 case 0x87: /* xchg Ev, Gv */
2582 if ((b & 1) == 0)
2583 ot = OT_BYTE;
2584 else
2585 ot = dflag ? OT_LONG : OT_WORD;
2586 modrm = ldub_code(s->pc++);
2587 reg = (modrm >> 3) & 7;
2588 mod = (modrm >> 6) & 3;
2589 if (mod == 3) {
2590 rm = modrm & 7;
2591 do_xchg_reg:
2592 gen_op_mov_TN_reg[ot][0][reg]();
2593 gen_op_mov_TN_reg[ot][1][rm]();
2594 gen_op_mov_reg_T0[ot][rm]();
2595 gen_op_mov_reg_T1[ot][reg]();
2596 } else {
2597 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2598 gen_op_mov_TN_reg[ot][0][reg]();
2599 /* for xchg, lock is implicit */
2600 if (!(prefixes & PREFIX_LOCK))
2601 gen_op_lock();
2602 gen_op_ld_T1_A0[ot + s->mem_index]();
2603 gen_op_st_T0_A0[ot + s->mem_index]();
2604 if (!(prefixes & PREFIX_LOCK))
2605 gen_op_unlock();
2606 gen_op_mov_reg_T1[ot][reg]();
2607 }
2608 break;
2609 case 0xc4: /* les Gv */
2610 op = R_ES;
2611 goto do_lxx;
2612 case 0xc5: /* lds Gv */
2613 op = R_DS;
2614 goto do_lxx;
2615 case 0x1b2: /* lss Gv */
2616 op = R_SS;
2617 goto do_lxx;
2618 case 0x1b4: /* lfs Gv */
2619 op = R_FS;
2620 goto do_lxx;
2621 case 0x1b5: /* lgs Gv */
2622 op = R_GS;
2623 do_lxx:
2624 ot = dflag ? OT_LONG : OT_WORD;
2625 modrm = ldub_code(s->pc++);
2626 reg = (modrm >> 3) & 7;
2627 mod = (modrm >> 6) & 3;
2628 if (mod == 3)
2629 goto illegal_op;
2630 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2631 gen_op_ld_T1_A0[ot + s->mem_index]();
2632 gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
2633 /* load the segment first to handle exceptions properly */
2634 gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
2635 gen_movl_seg_T0(s, op, pc_start - s->cs_base);
2636 /* then put the data */
2637 gen_op_mov_reg_T1[ot][reg]();
2638 if (s->is_jmp) {
2639 gen_op_jmp_im(s->pc - s->cs_base);
2640 gen_eob(s);
2641 }
2642 break;
2643
2644 /************************/
2645 /* shifts */
2646 case 0xc0:
2647 case 0xc1:
2648 /* shift Ev,Ib */
2649 shift = 2;
2650 grp2:
2651 {
2652 if ((b & 1) == 0)
2653 ot = OT_BYTE;
2654 else
2655 ot = dflag ? OT_LONG : OT_WORD;
2656
2657 modrm = ldub_code(s->pc++);
2658 mod = (modrm >> 6) & 3;
2659 rm = modrm & 7;
2660 op = (modrm >> 3) & 7;
2661
2662 if (mod != 3) {
2663 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2664 opreg = OR_TMP0;
2665 } else {
2666 opreg = rm + OR_EAX;
2667 }
2668
2669 /* simpler op */
2670 if (shift == 0) {
2671 gen_shift(s, op, ot, opreg, OR_ECX);
2672 } else {
2673 if (shift == 2) {
2674 shift = ldub_code(s->pc++);
2675 }
2676 gen_shifti(s, op, ot, opreg, shift);
2677 }
2678 }
2679 break;
2680 case 0xd0:
2681 case 0xd1:
2682 /* shift Ev,1 */
2683 shift = 1;
2684 goto grp2;
2685 case 0xd2:
2686 case 0xd3:
2687 /* shift Ev,cl */
2688 shift = 0;
2689 goto grp2;
2690
2691 case 0x1a4: /* shld imm */
2692 op = 0;
2693 shift = 1;
2694 goto do_shiftd;
2695 case 0x1a5: /* shld cl */
2696 op = 0;
2697 shift = 0;
2698 goto do_shiftd;
2699 case 0x1ac: /* shrd imm */
2700 op = 1;
2701 shift = 1;
2702 goto do_shiftd;
2703 case 0x1ad: /* shrd cl */
2704 op = 1;
2705 shift = 0;
2706 do_shiftd:
2707 ot = dflag ? OT_LONG : OT_WORD;
2708 modrm = ldub_code(s->pc++);
2709 mod = (modrm >> 6) & 3;
2710 rm = modrm & 7;
2711 reg = (modrm >> 3) & 7;
2712
2713 if (mod != 3) {
2714 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2715 gen_op_ld_T0_A0[ot + s->mem_index]();
2716 } else {
2717 gen_op_mov_TN_reg[ot][0][rm]();
2718 }
2719 gen_op_mov_TN_reg[ot][1][reg]();
2720
2721 if (shift) {
2722 val = ldub_code(s->pc++);
2723 val &= 0x1f;
2724 if (val) {
2725 if (mod == 3)
2726 gen_op_shiftd_T0_T1_im_cc[ot - OT_WORD][op](val);
2727 else
2728 gen_op_shiftd_mem_T0_T1_im_cc[ot - OT_WORD][op](val);
2729 if (op == 0 && ot != OT_WORD)
2730 s->cc_op = CC_OP_SHLB + ot;
2731 else
2732 s->cc_op = CC_OP_SARB + ot;
2733 }
2734 } else {
2735 if (s->cc_op != CC_OP_DYNAMIC)
2736 gen_op_set_cc_op(s->cc_op);
2737 if (mod == 3)
2738 gen_op_shiftd_T0_T1_ECX_cc[ot - OT_WORD][op]();
2739 else
2740 gen_op_shiftd_mem_T0_T1_ECX_cc[ot - OT_WORD][op]();
2741 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
2742 }
2743 if (mod == 3) {
2744 gen_op_mov_reg_T0[ot][rm]();
2745 }
2746 break;
2747
2748 /************************/
2749 /* floats */
2750 case 0xd8 ... 0xdf:
2751 modrm = ldub_code(s->pc++);
2752 mod = (modrm >> 6) & 3;
2753 rm = modrm & 7;
2754 op = ((b & 7) << 3) | ((modrm >> 3) & 7);
2755
2756 if (mod != 3) {
2757 /* memory op */
2758 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2759 switch(op) {
2760 case 0x00 ... 0x07: /* fxxxs */
2761 case 0x10 ... 0x17: /* fixxxl */
2762 case 0x20 ... 0x27: /* fxxxl */
2763 case 0x30 ... 0x37: /* fixxx */
2764 {
2765 int op1;
2766 op1 = op & 7;
2767
2768 switch(op >> 4) {
2769 case 0:
2770 gen_op_flds_FT0_A0();
2771 break;
2772 case 1:
2773 gen_op_fildl_FT0_A0();
2774 break;
2775 case 2:
2776 gen_op_fldl_FT0_A0();
2777 break;
2778 case 3:
2779 default:
2780 gen_op_fild_FT0_A0();
2781 break;
2782 }
2783
2784 gen_op_fp_arith_ST0_FT0[op1]();
2785 if (op1 == 3) {
2786 /* fcomp needs pop */
2787 gen_op_fpop();
2788 }
2789 }
2790 break;
2791 case 0x08: /* flds */
2792 case 0x0a: /* fsts */
2793 case 0x0b: /* fstps */
2794 case 0x18: /* fildl */
2795 case 0x1a: /* fistl */
2796 case 0x1b: /* fistpl */
2797 case 0x28: /* fldl */
2798 case 0x2a: /* fstl */
2799 case 0x2b: /* fstpl */
2800 case 0x38: /* filds */
2801 case 0x3a: /* fists */
2802 case 0x3b: /* fistps */
2803
2804 switch(op & 7) {
2805 case 0:
2806 switch(op >> 4) {
2807 case 0:
2808 gen_op_flds_ST0_A0();
2809 break;
2810 case 1:
2811 gen_op_fildl_ST0_A0();
2812 break;
2813 case 2:
2814 gen_op_fldl_ST0_A0();
2815 break;
2816 case 3:
2817 default:
2818 gen_op_fild_ST0_A0();
2819 break;
2820 }
2821 break;
2822 default:
2823 switch(op >> 4) {
2824 case 0:
2825 gen_op_fsts_ST0_A0();
2826 break;
2827 case 1:
2828 gen_op_fistl_ST0_A0();
2829 break;
2830 case 2:
2831 gen_op_fstl_ST0_A0();
2832 break;
2833 case 3:
2834 default:
2835 gen_op_fist_ST0_A0();
2836 break;
2837 }
2838 if ((op & 7) == 3)
2839 gen_op_fpop();
2840 break;
2841 }
2842 break;
2843 case 0x0c: /* fldenv mem */
2844 gen_op_fldenv_A0(s->dflag);
2845 break;
2846 case 0x0d: /* fldcw mem */
2847 gen_op_fldcw_A0();
2848 break;
2849 case 0x0e: /* fnstenv mem */
2850 gen_op_fnstenv_A0(s->dflag);
2851 break;
2852 case 0x0f: /* fnstcw mem */
2853 gen_op_fnstcw_A0();
2854 break;
2855 case 0x1d: /* fldt mem */
2856 gen_op_fldt_ST0_A0();
2857 break;
2858 case 0x1f: /* fstpt mem */
2859 gen_op_fstt_ST0_A0();
2860 gen_op_fpop();
2861 break;
2862 case 0x2c: /* frstor mem */
2863 gen_op_frstor_A0(s->dflag);
2864 break;
2865 case 0x2e: /* fnsave mem */
2866 gen_op_fnsave_A0(s->dflag);
2867 break;
2868 case 0x2f: /* fnstsw mem */
2869 gen_op_fnstsw_A0();
2870 break;
2871 case 0x3c: /* fbld */
2872 gen_op_fbld_ST0_A0();
2873 break;
2874 case 0x3e: /* fbstp */
2875 gen_op_fbst_ST0_A0();
2876 gen_op_fpop();
2877 break;
2878 case 0x3d: /* fildll */
2879 gen_op_fildll_ST0_A0();
2880 break;
2881 case 0x3f: /* fistpll */
2882 gen_op_fistll_ST0_A0();
2883 gen_op_fpop();
2884 break;
2885 default:
2886 goto illegal_op;
2887 }
2888 } else {
2889 /* register float ops */
2890 opreg = rm;
2891
2892 switch(op) {
2893 case 0x08: /* fld sti */
2894 gen_op_fpush();
2895 gen_op_fmov_ST0_STN((opreg + 1) & 7);
2896 break;
2897 case 0x09: /* fxchg sti */
2898 gen_op_fxchg_ST0_STN(opreg);
2899 break;
2900 case 0x0a: /* grp d9/2 */
2901 switch(rm) {
2902 case 0: /* fnop */
2903 break;
2904 default:
2905 goto illegal_op;
2906 }
2907 break;
2908 case 0x0c: /* grp d9/4 */
2909 switch(rm) {
2910 case 0: /* fchs */
2911 gen_op_fchs_ST0();
2912 break;
2913 case 1: /* fabs */
2914 gen_op_fabs_ST0();
2915 break;
2916 case 4: /* ftst */
2917 gen_op_fldz_FT0();
2918 gen_op_fcom_ST0_FT0();
2919 break;
2920 case 5: /* fxam */
2921 gen_op_fxam_ST0();
2922 break;
2923 default:
2924 goto illegal_op;
2925 }
2926 break;
2927 case 0x0d: /* grp d9/5 */
2928 {
2929 switch(rm) {
2930 case 0:
2931 gen_op_fpush();
2932 gen_op_fld1_ST0();
2933 break;
2934 case 1:
2935 gen_op_fpush();
2936 gen_op_fldl2t_ST0();
2937 break;
2938 case 2:
2939 gen_op_fpush();
2940 gen_op_fldl2e_ST0();
2941 break;
2942 case 3:
2943 gen_op_fpush();
2944 gen_op_fldpi_ST0();
2945 break;
2946 case 4:
2947 gen_op_fpush();
2948 gen_op_fldlg2_ST0();
2949 break;
2950 case 5:
2951 gen_op_fpush();
2952 gen_op_fldln2_ST0();
2953 break;
2954 case 6:
2955 gen_op_fpush();
2956 gen_op_fldz_ST0();
2957 break;
2958 default:
2959 goto illegal_op;
2960 }
2961 }
2962 break;
2963 case 0x0e: /* grp d9/6 */
2964 switch(rm) {
2965 case 0: /* f2xm1 */
2966 gen_op_f2xm1();
2967 break;
2968 case 1: /* fyl2x */
2969 gen_op_fyl2x();
2970 break;
2971 case 2: /* fptan */
2972 gen_op_fptan();
2973 break;
2974 case 3: /* fpatan */
2975 gen_op_fpatan();
2976 break;
2977 case 4: /* fxtract */
2978 gen_op_fxtract();
2979 break;
2980 case 5: /* fprem1 */
2981 gen_op_fprem1();
2982 break;
2983 case 6: /* fdecstp */
2984 gen_op_fdecstp();
2985 break;
2986 default:
2987 case 7: /* fincstp */
2988 gen_op_fincstp();
2989 break;
2990 }
2991 break;
2992 case 0x0f: /* grp d9/7 */
2993 switch(rm) {
2994 case 0: /* fprem */
2995 gen_op_fprem();
2996 break;
2997 case 1: /* fyl2xp1 */
2998 gen_op_fyl2xp1();
2999 break;
3000 case 2: /* fsqrt */
3001 gen_op_fsqrt();
3002 break;
3003 case 3: /* fsincos */
3004 gen_op_fsincos();
3005 break;
3006 case 5: /* fscale */
3007 gen_op_fscale();
3008 break;
3009 case 4: /* frndint */
3010 gen_op_frndint();
3011 break;
3012 case 6: /* fsin */
3013 gen_op_fsin();
3014 break;
3015 default:
3016 case 7: /* fcos */
3017 gen_op_fcos();
3018 break;
3019 }
3020 break;
3021 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
3022 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
3023 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
3024 {
3025 int op1;
3026
3027 op1 = op & 7;
3028 if (op >= 0x20) {
3029 gen_op_fp_arith_STN_ST0[op1](opreg);
3030 if (op >= 0x30)
3031 gen_op_fpop();
3032 } else {
3033 gen_op_fmov_FT0_STN(opreg);
3034 gen_op_fp_arith_ST0_FT0[op1]();
3035 }
3036 }
3037 break;
3038 case 0x02: /* fcom */
3039 gen_op_fmov_FT0_STN(opreg);
3040 gen_op_fcom_ST0_FT0();
3041 break;
3042 case 0x03: /* fcomp */
3043 gen_op_fmov_FT0_STN(opreg);
3044 gen_op_fcom_ST0_FT0();
3045 gen_op_fpop();
3046 break;
3047 case 0x15: /* da/5 */
3048 switch(rm) {
3049 case 1: /* fucompp */
3050 gen_op_fmov_FT0_STN(1);
3051 gen_op_fucom_ST0_FT0();
3052 gen_op_fpop();
3053 gen_op_fpop();
3054 break;
3055 default:
3056 goto illegal_op;
3057 }
3058 break;
3059 case 0x1c:
3060 switch(rm) {
3061 case 0: /* feni (287 only, just do nop here) */
3062 break;
3063 case 1: /* fdisi (287 only, just do nop here) */
3064 break;
3065 case 2: /* fclex */
3066 gen_op_fclex();
3067 break;
3068 case 3: /* fninit */
3069 gen_op_fninit();
3070 break;
3071 case 4: /* fsetpm (287 only, just do nop here) */
3072 break;
3073 default:
3074 goto illegal_op;
3075 }
3076 break;
3077 case 0x1d: /* fucomi */
3078 if (s->cc_op != CC_OP_DYNAMIC)
3079 gen_op_set_cc_op(s->cc_op);
3080 gen_op_fmov_FT0_STN(opreg);
3081 gen_op_fucomi_ST0_FT0();
3082 s->cc_op = CC_OP_EFLAGS;
3083 break;
3084 case 0x1e: /* fcomi */
3085 if (s->cc_op != CC_OP_DYNAMIC)
3086 gen_op_set_cc_op(s->cc_op);
3087 gen_op_fmov_FT0_STN(opreg);
3088 gen_op_fcomi_ST0_FT0();
3089 s->cc_op = CC_OP_EFLAGS;
3090 break;
3091 case 0x2a: /* fst sti */
3092 gen_op_fmov_STN_ST0(opreg);
3093 break;
3094 case 0x2b: /* fstp sti */
3095 gen_op_fmov_STN_ST0(opreg);
3096 gen_op_fpop();
3097 break;
3098 case 0x2c: /* fucom st(i) */
3099 gen_op_fmov_FT0_STN(opreg);
3100 gen_op_fucom_ST0_FT0();
3101 break;
3102 case 0x2d: /* fucomp st(i) */
3103 gen_op_fmov_FT0_STN(opreg);
3104 gen_op_fucom_ST0_FT0();
3105 gen_op_fpop();
3106 break;
3107 case 0x33: /* de/3 */
3108 switch(rm) {
3109 case 1: /* fcompp */
3110 gen_op_fmov_FT0_STN(1);
3111 gen_op_fcom_ST0_FT0();
3112 gen_op_fpop();
3113 gen_op_fpop();
3114 break;
3115 default:
3116 goto illegal_op;
3117 }
3118 break;
3119 case 0x3c: /* df/4 */
3120 switch(rm) {
3121 case 0:
3122 gen_op_fnstsw_EAX();
3123 break;
3124 default:
3125 goto illegal_op;
3126 }
3127 break;
3128 case 0x3d: /* fucomip */
3129 if (s->cc_op != CC_OP_DYNAMIC)
3130 gen_op_set_cc_op(s->cc_op);
3131 gen_op_fmov_FT0_STN(opreg);
3132 gen_op_fucomi_ST0_FT0();
3133 gen_op_fpop();
3134 s->cc_op = CC_OP_EFLAGS;
3135 break;
3136 case 0x3e: /* fcomip */
3137 if (s->cc_op != CC_OP_DYNAMIC)
3138 gen_op_set_cc_op(s->cc_op);
3139 gen_op_fmov_FT0_STN(opreg);
3140 gen_op_fcomi_ST0_FT0();
3141 gen_op_fpop();
3142 s->cc_op = CC_OP_EFLAGS;
3143 break;
3144 default:
3145 goto illegal_op;
3146 }
3147 }
3148 break;
3149 /************************/
3150 /* string ops */
3151
3152 case 0xa4: /* movsS */
3153 case 0xa5:
3154 if ((b & 1) == 0)
3155 ot = OT_BYTE;
3156 else
3157 ot = dflag ? OT_LONG : OT_WORD;
3158
3159 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3160 gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3161 } else {
3162 gen_movs(s, ot);
3163 }
3164 break;
3165
3166 case 0xaa: /* stosS */
3167 case 0xab:
3168 if ((b & 1) == 0)
3169 ot = OT_BYTE;
3170 else
3171 ot = dflag ? OT_LONG : OT_WORD;
3172
3173 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3174 gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3175 } else {
3176 gen_stos(s, ot);
3177 }
3178 break;
3179 case 0xac: /* lodsS */
3180 case 0xad:
3181 if ((b & 1) == 0)
3182 ot = OT_BYTE;
3183 else
3184 ot = dflag ? OT_LONG : OT_WORD;
3185 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3186 gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3187 } else {
3188 gen_lods(s, ot);
3189 }
3190 break;
3191 case 0xae: /* scasS */
3192 case 0xaf:
3193 if ((b & 1) == 0)
3194 ot = OT_BYTE;
3195 else
3196 ot = dflag ? OT_LONG : OT_WORD;
3197 if (prefixes & PREFIX_REPNZ) {
3198 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
3199 } else if (prefixes & PREFIX_REPZ) {
3200 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
3201 } else {
3202 gen_scas(s, ot);
3203 s->cc_op = CC_OP_SUBB + ot;
3204 }
3205 break;
3206
3207 case 0xa6: /* cmpsS */
3208 case 0xa7:
3209 if ((b & 1) == 0)
3210 ot = OT_BYTE;
3211 else
3212 ot = dflag ? OT_LONG : OT_WORD;
3213 if (prefixes & PREFIX_REPNZ) {
3214 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
3215 } else if (prefixes & PREFIX_REPZ) {
3216 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
3217 } else {
3218 gen_cmps(s, ot);
3219 s->cc_op = CC_OP_SUBB + ot;
3220 }
3221 break;
3222 case 0x6c: /* insS */
3223 case 0x6d:
3224 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
3225 /* NOTE: even for (E)CX = 0 the exception is raised */
3226 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3227 } else {
3228 if ((b & 1) == 0)
3229 ot = OT_BYTE;
3230 else
3231 ot = dflag ? OT_LONG : OT_WORD;
3232 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3233 gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3234 } else {
3235 gen_ins(s, ot);
3236 }
3237 }
3238 break;
3239 case 0x6e: /* outsS */
3240 case 0x6f:
3241 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
3242 /* NOTE: even for (E)CX = 0 the exception is raised */
3243 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3244 } else {
3245 if ((b & 1) == 0)
3246 ot = OT_BYTE;
3247 else
3248 ot = dflag ? OT_LONG : OT_WORD;
3249 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3250 gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3251 } else {
3252 gen_outs(s, ot);
3253 }
3254 }
3255 break;
3256
3257 /************************/
3258 /* port I/O */
3259 case 0xe4:
3260 case 0xe5:
3261 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
3262 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3263 } else {
3264 if ((b & 1) == 0)
3265 ot = OT_BYTE;
3266 else
3267 ot = dflag ? OT_LONG : OT_WORD;
3268 val = ldub_code(s->pc++);
3269 gen_op_movl_T0_im(val);
3270 gen_op_in[ot]();
3271 gen_op_mov_reg_T1[ot][R_EAX]();
3272 }
3273 break;
3274 case 0xe6:
3275 case 0xe7:
3276 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
3277 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3278 } else {
3279 if ((b & 1) == 0)
3280 ot = OT_BYTE;
3281 else
3282 ot = dflag ? OT_LONG : OT_WORD;
3283 val = ldub_code(s->pc++);
3284 gen_op_movl_T0_im(val);
3285 gen_op_mov_TN_reg[ot][1][R_EAX]();
3286 gen_op_out[ot]();
3287 }
3288 break;
3289 case 0xec:
3290 case 0xed:
3291 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
3292 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3293 } else {
3294 if ((b & 1) == 0)
3295 ot = OT_BYTE;
3296 else
3297 ot = dflag ? OT_LONG : OT_WORD;
3298 gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
3299 gen_op_in[ot]();
3300 gen_op_mov_reg_T1[ot][R_EAX]();
3301 }
3302 break;
3303 case 0xee:
3304 case 0xef:
3305 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
3306 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3307 } else {
3308 if ((b & 1) == 0)
3309 ot = OT_BYTE;
3310 else
3311 ot = dflag ? OT_LONG : OT_WORD;
3312 gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
3313 gen_op_mov_TN_reg[ot][1][R_EAX]();
3314 gen_op_out[ot]();
3315 }
3316 break;
3317
3318 /************************/
3319 /* control */
3320 case 0xc2: /* ret im */
3321 val = ldsw_code(s->pc);
3322 s->pc += 2;
3323 gen_pop_T0(s);
3324 gen_stack_update(s, val + (2 << s->dflag));
3325 if (s->dflag == 0)
3326 gen_op_andl_T0_ffff();
3327 gen_op_jmp_T0();
3328 gen_eob(s);
3329 break;
3330 case 0xc3: /* ret */
3331 gen_pop_T0(s);
3332 gen_pop_update(s);
3333 if (s->dflag == 0)
3334 gen_op_andl_T0_ffff();
3335 gen_op_jmp_T0();
3336 gen_eob(s);
3337 break;
3338 case 0xca: /* lret im */
3339 val = ldsw_code(s->pc);
3340 s->pc += 2;
3341 do_lret:
3342 if (s->pe && !s->vm86) {
3343 if (s->cc_op != CC_OP_DYNAMIC)
3344 gen_op_set_cc_op(s->cc_op);
3345 gen_op_jmp_im(pc_start - s->cs_base);
3346 gen_op_lret_protected(s->dflag, val);
3347 } else {
3348 gen_stack_A0(s);
3349 /* pop offset */
3350 gen_op_ld_T0_A0[1 + s->dflag + s->mem_index]();
3351 if (s->dflag == 0)
3352 gen_op_andl_T0_ffff();
3353 /* NOTE: keeping EIP updated is not a problem in case of
3354 exception */
3355 gen_op_jmp_T0();
3356 /* pop selector */
3357 gen_op_addl_A0_im(2 << s->dflag);
3358 gen_op_ld_T0_A0[1 + s->dflag + s->mem_index]();
3359 gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
3360 /* add stack offset */
3361 gen_stack_update(s, val + (4 << s->dflag));
3362 }
3363 gen_eob(s);
3364 break;
3365 case 0xcb: /* lret */
3366 val = 0;
3367 goto do_lret;
3368 case 0xcf: /* iret */
3369 if (!s->pe) {
3370 /* real mode */
3371 gen_op_iret_real(s->dflag);
3372 s->cc_op = CC_OP_EFLAGS;
3373 } else if (s->vm86 && s->iopl != 3) {
3374 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3375 } else {
3376 if (s->cc_op != CC_OP_DYNAMIC)
3377 gen_op_set_cc_op(s->cc_op);
3378 gen_op_jmp_im(pc_start - s->cs_base);
3379 gen_op_iret_protected(s->dflag);
3380 s->cc_op = CC_OP_EFLAGS;
3381 }
3382 gen_eob(s);
3383 break;
3384 case 0xe8: /* call im */
3385 {
3386 unsigned int next_eip;
3387 ot = dflag ? OT_LONG : OT_WORD;
3388 val = insn_get(s, ot);
3389 next_eip = s->pc - s->cs_base;
3390 val += next_eip;
3391 if (s->dflag == 0)
3392 val &= 0xffff;
3393 gen_op_movl_T0_im(next_eip);
3394 gen_push_T0(s);
3395 gen_jmp(s, val);
3396 }
3397 break;
3398 case 0x9a: /* lcall im */
3399 {
3400 unsigned int selector, offset;
3401
3402 ot = dflag ? OT_LONG : OT_WORD;
3403 offset = insn_get(s, ot);
3404 selector = insn_get(s, OT_WORD);
3405
3406 gen_op_movl_T0_im(selector);
3407 gen_op_movl_T1_im(offset);
3408 }
3409 goto do_lcall;
3410 case 0xe9: /* jmp */
3411 ot = dflag ? OT_LONG : OT_WORD;
3412 val = insn_get(s, ot);
3413 val += s->pc - s->cs_base;
3414 if (s->dflag == 0)
3415 val = val & 0xffff;
3416 gen_jmp(s, val);
3417 break;
3418 case 0xea: /* ljmp im */
3419 {
3420 unsigned int selector, offset;
3421
3422 ot = dflag ? OT_LONG : OT_WORD;
3423 offset = insn_get(s, ot);
3424 selector = insn_get(s, OT_WORD);
3425
3426 gen_op_movl_T0_im(selector);
3427 gen_op_movl_T1_im(offset);
3428 }
3429 goto do_ljmp;
3430 case 0xeb: /* jmp Jb */
3431 val = (int8_t)insn_get(s, OT_BYTE);
3432 val += s->pc - s->cs_base;
3433 if (s->dflag == 0)
3434 val = val & 0xffff;
3435 gen_jmp(s, val);
3436 break;
3437 case 0x70 ... 0x7f: /* jcc Jb */
3438 val = (int8_t)insn_get(s, OT_BYTE);
3439 goto do_jcc;
3440 case 0x180 ... 0x18f: /* jcc Jv */
3441 if (dflag) {
3442 val = insn_get(s, OT_LONG);
3443 } else {
3444 val = (int16_t)insn_get(s, OT_WORD);
3445 }
3446 do_jcc:
3447 next_eip = s->pc - s->cs_base;
3448 val += next_eip;
3449 if (s->dflag == 0)
3450 val &= 0xffff;
3451 gen_jcc(s, b, val, next_eip);
3452 break;
3453
3454 case 0x190 ... 0x19f: /* setcc Gv */
3455 modrm = ldub_code(s->pc++);
3456 gen_setcc(s, b);
3457 gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
3458 break;
3459 case 0x140 ... 0x14f: /* cmov Gv, Ev */
3460 ot = dflag ? OT_LONG : OT_WORD;
3461 modrm = ldub_code(s->pc++);
3462 reg = (modrm >> 3) & 7;
3463 mod = (modrm >> 6) & 3;
3464 gen_setcc(s, b);
3465 if (mod != 3) {
3466 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3467 gen_op_ld_T1_A0[ot + s->mem_index]();
3468 } else {
3469 rm = modrm & 7;
3470 gen_op_mov_TN_reg[ot][1][rm]();
3471 }
3472 gen_op_cmov_reg_T1_T0[ot - OT_WORD][reg]();
3473 break;
3474
3475 /************************/
3476 /* flags */
3477 case 0x9c: /* pushf */
3478 if (s->vm86 && s->iopl != 3) {
3479 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3480 } else {
3481 if (s->cc_op != CC_OP_DYNAMIC)
3482 gen_op_set_cc_op(s->cc_op);
3483 gen_op_movl_T0_eflags();
3484 gen_push_T0(s);
3485 }
3486 break;
3487 case 0x9d: /* popf */
3488 if (s->vm86 && s->iopl != 3) {
3489 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3490 } else {
3491 gen_pop_T0(s);
3492 if (s->cpl == 0) {
3493 if (s->dflag) {
3494 gen_op_movl_eflags_T0_cpl0();
3495 } else {
3496 gen_op_movw_eflags_T0_cpl0();
3497 }
3498 } else {
3499 if (s->dflag) {
3500 gen_op_movl_eflags_T0();
3501 } else {
3502 gen_op_movw_eflags_T0();
3503 }
3504 }
3505 gen_pop_update(s);
3506 s->cc_op = CC_OP_EFLAGS;
3507 /* abort translation because TF flag may change */
3508 gen_op_jmp_im(s->pc - s->cs_base);
3509 gen_eob(s);
3510 }
3511 break;
3512 case 0x9e: /* sahf */
3513 gen_op_mov_TN_reg[OT_BYTE][0][R_AH]();
3514 if (s->cc_op != CC_OP_DYNAMIC)
3515 gen_op_set_cc_op(s->cc_op);
3516 gen_op_movb_eflags_T0();
3517 s->cc_op = CC_OP_EFLAGS;
3518 break;
3519 case 0x9f: /* lahf */
3520 if (s->cc_op != CC_OP_DYNAMIC)
3521 gen_op_set_cc_op(s->cc_op);
3522 gen_op_movl_T0_eflags();
3523 gen_op_mov_reg_T0[OT_BYTE][R_AH]();
3524 break;
3525 case 0xf5: /* cmc */
3526 if (s->cc_op != CC_OP_DYNAMIC)
3527 gen_op_set_cc_op(s->cc_op);
3528 gen_op_cmc();
3529 s->cc_op = CC_OP_EFLAGS;
3530 break;
3531 case 0xf8: /* clc */
3532 if (s->cc_op != CC_OP_DYNAMIC)
3533 gen_op_set_cc_op(s->cc_op);
3534 gen_op_clc();
3535 s->cc_op = CC_OP_EFLAGS;
3536 break;
3537 case 0xf9: /* stc */
3538 if (s->cc_op != CC_OP_DYNAMIC)
3539 gen_op_set_cc_op(s->cc_op);
3540 gen_op_stc();
3541 s->cc_op = CC_OP_EFLAGS;
3542 break;
3543 case 0xfc: /* cld */
3544 gen_op_cld();
3545 break;
3546 case 0xfd: /* std */
3547 gen_op_std();
3548 break;
3549
3550 /************************/
3551 /* bit operations */
3552 case 0x1ba: /* bt/bts/btr/btc Gv, im */
3553 ot = dflag ? OT_LONG : OT_WORD;
3554 modrm = ldub_code(s->pc++);
3555 op = (modrm >> 3) & 7;
3556 mod = (modrm >> 6) & 3;
3557 rm = modrm & 7;
3558 if (mod != 3) {
3559 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3560 gen_op_ld_T0_A0[ot + s->mem_index]();
3561 } else {
3562 gen_op_mov_TN_reg[ot][0][rm]();
3563 }
3564 /* load shift */
3565 val = ldub_code(s->pc++);
3566 gen_op_movl_T1_im(val);
3567 if (op < 4)
3568 goto illegal_op;
3569 op -= 4;
3570 gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
3571 s->cc_op = CC_OP_SARB + ot;
3572 if (op != 0) {
3573 if (mod != 3)
3574 gen_op_st_T0_A0[ot + s->mem_index]();
3575 else
3576 gen_op_mov_reg_T0[ot][rm]();
3577 gen_op_update_bt_cc();
3578 }
3579 break;
3580 case 0x1a3: /* bt Gv, Ev */
3581 op = 0;
3582 goto do_btx;
3583 case 0x1ab: /* bts */
3584 op = 1;
3585 goto do_btx;
3586 case 0x1b3: /* btr */
3587 op = 2;
3588 goto do_btx;
3589 case 0x1bb: /* btc */
3590 op = 3;
3591 do_btx:
3592 ot = dflag ? OT_LONG : OT_WORD;
3593 modrm = ldub_code(s->pc++);
3594 reg = (modrm >> 3) & 7;
3595 mod = (modrm >> 6) & 3;
3596 rm = modrm & 7;
3597 gen_op_mov_TN_reg[OT_LONG][1][reg]();
3598 if (mod != 3) {
3599 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3600 /* specific case: we need to add a displacement */
3601 if (ot == OT_WORD)
3602 gen_op_add_bitw_A0_T1();
3603 else
3604 gen_op_add_bitl_A0_T1();
3605 gen_op_ld_T0_A0[ot + s->mem_index]();
3606 } else {
3607 gen_op_mov_TN_reg[ot][0][rm]();
3608 }
3609 gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
3610 s->cc_op = CC_OP_SARB + ot;
3611 if (op != 0) {
3612 if (mod != 3)
3613 gen_op_st_T0_A0[ot + s->mem_index]();
3614 else
3615 gen_op_mov_reg_T0[ot][rm]();
3616 gen_op_update_bt_cc();
3617 }
3618 break;
3619 case 0x1bc: /* bsf */
3620 case 0x1bd: /* bsr */
3621 ot = dflag ? OT_LONG : OT_WORD;
3622 modrm = ldub_code(s->pc++);
3623 reg = (modrm >> 3) & 7;
3624 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3625 gen_op_bsx_T0_cc[ot - OT_WORD][b & 1]();
3626 /* NOTE: we always write back the result. Intel doc says it is
3627 undefined if T0 == 0 */
3628 gen_op_mov_reg_T0[ot][reg]();
3629 s->cc_op = CC_OP_LOGICB + ot;
3630 break;
3631 /************************/
3632 /* bcd */
3633 case 0x27: /* daa */
3634 if (s->cc_op != CC_OP_DYNAMIC)
3635 gen_op_set_cc_op(s->cc_op);
3636 gen_op_daa();
3637 s->cc_op = CC_OP_EFLAGS;
3638 break;
3639 case 0x2f: /* das */
3640 if (s->cc_op != CC_OP_DYNAMIC)
3641 gen_op_set_cc_op(s->cc_op);
3642 gen_op_das();
3643 s->cc_op = CC_OP_EFLAGS;
3644 break;
3645 case 0x37: /* aaa */
3646 if (s->cc_op != CC_OP_DYNAMIC)
3647 gen_op_set_cc_op(s->cc_op);
3648 gen_op_aaa();
3649 s->cc_op = CC_OP_EFLAGS;
3650 break;
3651 case 0x3f: /* aas */
3652 if (s->cc_op != CC_OP_DYNAMIC)
3653 gen_op_set_cc_op(s->cc_op);
3654 gen_op_aas();
3655 s->cc_op = CC_OP_EFLAGS;
3656 break;
3657 case 0xd4: /* aam */
3658 val = ldub_code(s->pc++);
3659 gen_op_aam(val);
3660 s->cc_op = CC_OP_LOGICB;
3661 break;
3662 case 0xd5: /* aad */
3663 val = ldub_code(s->pc++);
3664 gen_op_aad(val);
3665 s->cc_op = CC_OP_LOGICB;
3666 break;
3667 /************************/
3668 /* misc */
3669 case 0x90: /* nop */
3670 break;
3671 case 0x9b: /* fwait */
3672 break;
3673 case 0xcc: /* int3 */
3674 gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
3675 break;
3676 case 0xcd: /* int N */
3677 val = ldub_code(s->pc++);
3678 /* XXX: add error code for vm86 GPF */
3679 if (!s->vm86)
3680 gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
3681 else
3682 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3683 break;
3684 case 0xce: /* into */
3685 if (s->cc_op != CC_OP_DYNAMIC)
3686 gen_op_set_cc_op(s->cc_op);
3687 gen_op_into(s->pc - s->cs_base);
3688 break;
3689 case 0xf1: /* icebp (undocumented, exits to external debugger) */
3690 gen_debug(s, pc_start - s->cs_base);
3691 break;
3692 case 0xfa: /* cli */
3693 if (!s->vm86) {
3694 if (s->cpl <= s->iopl) {
3695 gen_op_cli();
3696 } else {
3697 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3698 }
3699 } else {
3700 if (s->iopl == 3) {
3701 gen_op_cli();
3702 } else {
3703 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3704 }
3705 }
3706 break;
3707 case 0xfb: /* sti */
3708 if (!s->vm86) {
3709 if (s->cpl <= s->iopl) {
3710 gen_sti:
3711 gen_op_sti();
3712 /* interruptions are enabled only the first insn after sti */
3713 gen_op_set_inhibit_irq();
3714 /* give a chance to handle pending irqs */
3715 gen_op_jmp_im(s->pc - s->cs_base);
3716 gen_eob(s);
3717 } else {
3718 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3719 }
3720 } else {
3721 if (s->iopl == 3) {
3722 goto gen_sti;
3723 } else {
3724 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3725 }
3726 }
3727 break;
3728 case 0x62: /* bound */
3729 ot = dflag ? OT_LONG : OT_WORD;
3730 modrm = ldub_code(s->pc++);
3731 reg = (modrm >> 3) & 7;
3732 mod = (modrm >> 6) & 3;
3733 if (mod == 3)
3734 goto illegal_op;
3735 gen_op_mov_reg_T0[ot][reg]();
3736 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3737 if (ot == OT_WORD)
3738 gen_op_boundw(pc_start - s->cs_base);
3739 else
3740 gen_op_boundl(pc_start - s->cs_base);
3741 break;
3742 case 0x1c8 ... 0x1cf: /* bswap reg */
3743 reg = b & 7;
3744 gen_op_mov_TN_reg[OT_LONG][0][reg]();
3745 gen_op_bswapl_T0();
3746 gen_op_mov_reg_T0[OT_LONG][reg]();
3747 break;
3748 case 0xd6: /* salc */
3749 if (s->cc_op != CC_OP_DYNAMIC)
3750 gen_op_set_cc_op(s->cc_op);
3751 gen_op_salc();
3752 break;
3753 case 0xe0: /* loopnz */
3754 case 0xe1: /* loopz */
3755 if (s->cc_op != CC_OP_DYNAMIC)
3756 gen_op_set_cc_op(s->cc_op);
3757 /* FALL THRU */
3758 case 0xe2: /* loop */
3759 case 0xe3: /* jecxz */
3760 val = (int8_t)insn_get(s, OT_BYTE);
3761 next_eip = s->pc - s->cs_base;
3762 val += next_eip;
3763 if (s->dflag == 0)
3764 val &= 0xffff;
3765 gen_op_loop[s->aflag][b & 3](val, next_eip);
3766 gen_eob(s);
3767 break;
3768 case 0x130: /* wrmsr */
3769 case 0x132: /* rdmsr */
3770 if (s->cpl != 0) {
3771 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3772 } else {
3773 if (b & 2)
3774 gen_op_rdmsr();
3775 else
3776 gen_op_wrmsr();
3777 }
3778 break;
3779 case 0x131: /* rdtsc */
3780 gen_op_rdtsc();
3781 break;
3782 case 0x1a2: /* cpuid */
3783 gen_op_cpuid();
3784 break;
3785 case 0xf4: /* hlt */
3786 if (s->cpl != 0) {
3787 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3788 } else {
3789 if (s->cc_op != CC_OP_DYNAMIC)
3790 gen_op_set_cc_op(s->cc_op);
3791 gen_op_jmp_im(s->pc - s->cs_base);
3792 gen_op_hlt();
3793 s->is_jmp = 3;
3794 }
3795 break;
3796 case 0x100:
3797 modrm = ldub_code(s->pc++);
3798 mod = (modrm >> 6) & 3;
3799 op = (modrm >> 3) & 7;
3800 switch(op) {
3801 case 0: /* sldt */
3802 gen_op_movl_T0_env(offsetof(CPUX86State,ldt.selector));
3803 ot = OT_WORD;
3804 if (mod == 3)
3805 ot += s->dflag;
3806 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
3807 break;
3808 case 2: /* lldt */
3809 if (s->cpl != 0) {
3810 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3811 } else {
3812 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3813 gen_op_jmp_im(pc_start - s->cs_base);
3814 gen_op_lldt_T0();
3815 }
3816 break;
3817 case 1: /* str */
3818 gen_op_movl_T0_env(offsetof(CPUX86State,tr.selector));
3819 ot = OT_WORD;
3820 if (mod == 3)
3821 ot += s->dflag;
3822 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
3823 break;
3824 case 3: /* ltr */
3825 if (s->cpl != 0) {
3826 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3827 } else {
3828 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3829 gen_op_jmp_im(pc_start - s->cs_base);
3830 gen_op_ltr_T0();
3831 }
3832 break;
3833 case 4: /* verr */
3834 case 5: /* verw */
3835 default:
3836 goto illegal_op;
3837 }
3838 break;
3839 case 0x101:
3840 modrm = ldub_code(s->pc++);
3841 mod = (modrm >> 6) & 3;
3842 op = (modrm >> 3) & 7;
3843 switch(op) {
3844 case 0: /* sgdt */
3845 case 1: /* sidt */
3846 if (mod == 3)
3847 goto illegal_op;
3848 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3849 if (op == 0)
3850 gen_op_movl_T0_env(offsetof(CPUX86State,gdt.limit));
3851 else
3852 gen_op_movl_T0_env(offsetof(CPUX86State,idt.limit));
3853 gen_op_st_T0_A0[OT_WORD + s->mem_index]();
3854 gen_op_addl_A0_im(2);
3855 if (op == 0)
3856 gen_op_movl_T0_env(offsetof(CPUX86State,gdt.base));
3857 else
3858 gen_op_movl_T0_env(offsetof(CPUX86State,idt.base));
3859 if (!s->dflag)
3860 gen_op_andl_T0_im(0xffffff);
3861 gen_op_st_T0_A0[OT_LONG + s->mem_index]();
3862 break;
3863 case 2: /* lgdt */
3864 case 3: /* lidt */
3865 if (mod == 3)
3866 goto illegal_op;
3867 if (s->cpl != 0) {
3868 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3869 } else {
3870 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3871 gen_op_ld_T1_A0[OT_WORD + s->mem_index]();
3872 gen_op_addl_A0_im(2);
3873 gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
3874 if (!s->dflag)
3875 gen_op_andl_T0_im(0xffffff);
3876 if (op == 2) {
3877 gen_op_movl_env_T0(offsetof(CPUX86State,gdt.base));
3878 gen_op_movl_env_T1(offsetof(CPUX86State,gdt.limit));
3879 } else {
3880 gen_op_movl_env_T0(offsetof(CPUX86State,idt.base));
3881 gen_op_movl_env_T1(offsetof(CPUX86State,idt.limit));
3882 }
3883 }
3884 break;
3885 case 4: /* smsw */
3886 gen_op_movl_T0_env(offsetof(CPUX86State,cr[0]));
3887 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
3888 break;
3889 case 6: /* lmsw */
3890 if (s->cpl != 0) {
3891 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3892 } else {
3893 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3894 gen_op_lmsw_T0();
3895 }
3896 break;
3897 case 7: /* invlpg */
3898 if (s->cpl != 0) {
3899 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3900 } else {
3901 if (mod == 3)
3902 goto illegal_op;
3903 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3904 gen_op_invlpg_A0();
3905 }
3906 break;
3907 default:
3908 goto illegal_op;
3909 }
3910 break;
3911 case 0x102: /* lar */
3912 case 0x103: /* lsl */
3913 if (!s->pe || s->vm86)
3914 goto illegal_op;
3915 ot = dflag ? OT_LONG : OT_WORD;
3916 modrm = ldub_code(s->pc++);
3917 reg = (modrm >> 3) & 7;
3918 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3919 gen_op_mov_TN_reg[ot][1][reg]();
3920 if (s->cc_op != CC_OP_DYNAMIC)
3921 gen_op_set_cc_op(s->cc_op);
3922 if (b == 0x102)
3923 gen_op_lar();
3924 else
3925 gen_op_lsl();
3926 s->cc_op = CC_OP_EFLAGS;
3927 gen_op_mov_reg_T1[ot][reg]();
3928 break;
3929 case 0x118:
3930 modrm = ldub_code(s->pc++);
3931 mod = (modrm >> 6) & 3;
3932 op = (modrm >> 3) & 7;
3933 switch(op) {
3934 case 0: /* prefetchnta */
3935 case 1: /* prefetchnt0 */
3936 case 2: /* prefetchnt0 */
3937 case 3: /* prefetchnt0 */
3938 if (mod == 3)
3939 goto illegal_op;
3940 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3941 /* nothing more to do */
3942 break;
3943 default:
3944 goto illegal_op;
3945 }
3946 break;
3947 case 0x120: /* mov reg, crN */
3948 case 0x122: /* mov crN, reg */
3949 if (s->cpl != 0) {
3950 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3951 } else {
3952 modrm = ldub_code(s->pc++);
3953 if ((modrm & 0xc0) != 0xc0)
3954 goto illegal_op;
3955 rm = modrm & 7;
3956 reg = (modrm >> 3) & 7;
3957 switch(reg) {
3958 case 0:
3959 case 2:
3960 case 3:
3961 case 4:
3962 if (b & 2) {
3963 gen_op_mov_TN_reg[OT_LONG][0][rm]();
3964 gen_op_movl_crN_T0(reg);
3965 gen_op_jmp_im(s->pc - s->cs_base);
3966 gen_eob(s);
3967 } else {
3968 gen_op_movl_T0_env(offsetof(CPUX86State,cr[reg]));
3969 gen_op_mov_reg_T0[OT_LONG][rm]();
3970 }
3971 break;
3972 default:
3973 goto illegal_op;
3974 }
3975 }
3976 break;
3977 case 0x121: /* mov reg, drN */
3978 case 0x123: /* mov drN, reg */
3979 if (s->cpl != 0) {
3980 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3981 } else {
3982 modrm = ldub_code(s->pc++);
3983 if ((modrm & 0xc0) != 0xc0)
3984 goto illegal_op;
3985 rm = modrm & 7;
3986 reg = (modrm >> 3) & 7;
3987 /* XXX: do it dynamically with CR4.DE bit */
3988 if (reg == 4 || reg == 5)
3989 goto illegal_op;
3990 if (b & 2) {
3991 gen_op_mov_TN_reg[OT_LONG][0][rm]();
3992 gen_op_movl_drN_T0(reg);
3993 gen_op_jmp_im(s->pc - s->cs_base);
3994 gen_eob(s);
3995 } else {
3996 gen_op_movl_T0_env(offsetof(CPUX86State,dr[reg]));
3997 gen_op_mov_reg_T0[OT_LONG][rm]();
3998 }
3999 }
4000 break;
4001 case 0x106: /* clts */
4002 if (s->cpl != 0) {
4003 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4004 } else {
4005 gen_op_clts();
4006 }
4007 break;
4008 default:
4009 goto illegal_op;
4010 }
4011 /* lock generation */
4012 if (s->prefix & PREFIX_LOCK)
4013 gen_op_unlock();
4014 return s->pc;
4015 illegal_op:
4016 /* XXX: ensure that no lock was generated */
4017 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
4018 return s->pc;
4019 }
4020
4021 #define CC_OSZAPC (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C)
4022 #define CC_OSZAP (CC_O | CC_S | CC_Z | CC_A | CC_P)
4023
4024 /* flags read by an operation */
4025 static uint16_t opc_read_flags[NB_OPS] = {
4026 [INDEX_op_aas] = CC_A,
4027 [INDEX_op_aaa] = CC_A,
4028 [INDEX_op_das] = CC_A | CC_C,
4029 [INDEX_op_daa] = CC_A | CC_C,
4030
4031 [INDEX_op_adcb_T0_T1_cc] = CC_C,
4032 [INDEX_op_adcw_T0_T1_cc] = CC_C,
4033 [INDEX_op_adcl_T0_T1_cc] = CC_C,
4034 [INDEX_op_sbbb_T0_T1_cc] = CC_C,
4035 [INDEX_op_sbbw_T0_T1_cc] = CC_C,
4036 [INDEX_op_sbbl_T0_T1_cc] = CC_C,
4037
4038 [INDEX_op_adcb_mem_T0_T1_cc] = CC_C,
4039 [INDEX_op_adcw_mem_T0_T1_cc] = CC_C,
4040 [INDEX_op_adcl_mem_T0_T1_cc] = CC_C,
4041 [INDEX_op_sbbb_mem_T0_T1_cc] = CC_C,
4042 [INDEX_op_sbbw_mem_T0_T1_cc] = CC_C,
4043 [INDEX_op_sbbl_mem_T0_T1_cc] = CC_C,
4044
4045 /* subtle: due to the incl/decl implementation, C is used */
4046 [INDEX_op_update_inc_cc] = CC_C,
4047
4048 [INDEX_op_into] = CC_O,
4049
4050 [INDEX_op_jb_subb] = CC_C,
4051 [INDEX_op_jb_subw] = CC_C,
4052 [INDEX_op_jb_subl] = CC_C,
4053
4054 [INDEX_op_jz_subb] = CC_Z,
4055 [INDEX_op_jz_subw] = CC_Z,
4056 [INDEX_op_jz_subl] = CC_Z,
4057
4058 [INDEX_op_jbe_subb] = CC_Z | CC_C,
4059 [INDEX_op_jbe_subw] = CC_Z | CC_C,
4060 [INDEX_op_jbe_subl] = CC_Z | CC_C,
4061
4062 [INDEX_op_js_subb] = CC_S,
4063 [INDEX_op_js_subw] = CC_S,
4064 [INDEX_op_js_subl] = CC_S,
4065
4066 [INDEX_op_jl_subb] = CC_O | CC_S,
4067 [INDEX_op_jl_subw] = CC_O | CC_S,
4068 [INDEX_op_jl_subl] = CC_O | CC_S,
4069
4070 [INDEX_op_jle_subb] = CC_O | CC_S | CC_Z,
4071 [INDEX_op_jle_subw] = CC_O | CC_S | CC_Z,
4072 [INDEX_op_jle_subl] = CC_O | CC_S | CC_Z,
4073
4074 [INDEX_op_loopnzw] = CC_Z,
4075 [INDEX_op_loopnzl] = CC_Z,
4076 [INDEX_op_loopzw] = CC_Z,
4077 [INDEX_op_loopzl] = CC_Z,
4078
4079 [INDEX_op_seto_T0_cc] = CC_O,
4080 [INDEX_op_setb_T0_cc] = CC_C,
4081 [INDEX_op_setz_T0_cc] = CC_Z,
4082 [INDEX_op_setbe_T0_cc] = CC_Z | CC_C,
4083 [INDEX_op_sets_T0_cc] = CC_S,
4084 [INDEX_op_setp_T0_cc] = CC_P,
4085 [INDEX_op_setl_T0_cc] = CC_O | CC_S,
4086 [INDEX_op_setle_T0_cc] = CC_O | CC_S | CC_Z,
4087
4088 [INDEX_op_setb_T0_subb] = CC_C,
4089 [INDEX_op_setb_T0_subw] = CC_C,
4090 [INDEX_op_setb_T0_subl] = CC_C,
4091
4092 [INDEX_op_setz_T0_subb] = CC_Z,
4093 [INDEX_op_setz_T0_subw] = CC_Z,
4094 [INDEX_op_setz_T0_subl] = CC_Z,
4095
4096 [INDEX_op_setbe_T0_subb] = CC_Z | CC_C,
4097 [INDEX_op_setbe_T0_subw] = CC_Z | CC_C,
4098 [INDEX_op_setbe_T0_subl] = CC_Z | CC_C,
4099
4100 [INDEX_op_sets_T0_subb] = CC_S,
4101 [INDEX_op_sets_T0_subw] = CC_S,
4102 [INDEX_op_sets_T0_subl] = CC_S,
4103
4104 [INDEX_op_setl_T0_subb] = CC_O | CC_S,
4105 [INDEX_op_setl_T0_subw] = CC_O | CC_S,
4106 [INDEX_op_setl_T0_subl] = CC_O | CC_S,
4107
4108 [INDEX_op_setle_T0_subb] = CC_O | CC_S | CC_Z,
4109 [INDEX_op_setle_T0_subw] = CC_O | CC_S | CC_Z,
4110 [INDEX_op_setle_T0_subl] = CC_O | CC_S | CC_Z,
4111
4112 [INDEX_op_movl_T0_eflags] = CC_OSZAPC,
4113 [INDEX_op_cmc] = CC_C,
4114 [INDEX_op_salc] = CC_C,
4115
4116 [INDEX_op_rclb_T0_T1_cc] = CC_C,
4117 [INDEX_op_rclw_T0_T1_cc] = CC_C,
4118 [INDEX_op_rcll_T0_T1_cc] = CC_C,
4119 [INDEX_op_rcrb_T0_T1_cc] = CC_C,
4120 [INDEX_op_rcrw_T0_T1_cc] = CC_C,
4121 [INDEX_op_rcrl_T0_T1_cc] = CC_C,
4122
4123 [INDEX_op_rclb_mem_T0_T1_cc] = CC_C,
4124 [INDEX_op_rclw_mem_T0_T1_cc] = CC_C,
4125 [INDEX_op_rcll_mem_T0_T1_cc] = CC_C,
4126 [INDEX_op_rcrb_mem_T0_T1_cc] = CC_C,
4127 [INDEX_op_rcrw_mem_T0_T1_cc] = CC_C,
4128 [INDEX_op_rcrl_mem_T0_T1_cc] = CC_C,
4129 };
4130
4131 /* flags written by an operation */
4132 static uint16_t opc_write_flags[NB_OPS] = {
4133 [INDEX_op_update2_cc] = CC_OSZAPC,
4134 [INDEX_op_update1_cc] = CC_OSZAPC,
4135 [INDEX_op_cmpl_T0_T1_cc] = CC_OSZAPC,
4136 [INDEX_op_update_neg_cc] = CC_OSZAPC,
4137 /* subtle: due to the incl/decl implementation, C is used */
4138 [INDEX_op_update_inc_cc] = CC_OSZAPC,
4139 [INDEX_op_testl_T0_T1_cc] = CC_OSZAPC,
4140
4141 [INDEX_op_adcb_T0_T1_cc] = CC_OSZAPC,
4142 [INDEX_op_adcw_T0_T1_cc] = CC_OSZAPC,
4143 [INDEX_op_adcl_T0_T1_cc] = CC_OSZAPC,
4144 [INDEX_op_sbbb_T0_T1_cc] = CC_OSZAPC,
4145 [INDEX_op_sbbw_T0_T1_cc] = CC_OSZAPC,
4146 [INDEX_op_sbbl_T0_T1_cc] = CC_OSZAPC,
4147
4148 [INDEX_op_adcb_mem_T0_T1_cc] = CC_OSZAPC,
4149 [INDEX_op_adcw_mem_T0_T1_cc] = CC_OSZAPC,
4150 [INDEX_op_adcl_mem_T0_T1_cc] = CC_OSZAPC,
4151 [INDEX_op_sbbb_mem_T0_T1_cc] = CC_OSZAPC,
4152 [INDEX_op_sbbw_mem_T0_T1_cc] = CC_OSZAPC,
4153 [INDEX_op_sbbl_mem_T0_T1_cc] = CC_OSZAPC,
4154
4155 [INDEX_op_mulb_AL_T0] = CC_OSZAPC,
4156 [INDEX_op_imulb_AL_T0] = CC_OSZAPC,
4157 [INDEX_op_mulw_AX_T0] = CC_OSZAPC,
4158 [INDEX_op_imulw_AX_T0] = CC_OSZAPC,
4159 [INDEX_op_mull_EAX_T0] = CC_OSZAPC,
4160 [INDEX_op_imull_EAX_T0] = CC_OSZAPC,
4161 [INDEX_op_imulw_T0_T1] = CC_OSZAPC,
4162 [INDEX_op_imull_T0_T1] = CC_OSZAPC,
4163
4164 /* bcd */
4165 [INDEX_op_aam] = CC_OSZAPC,
4166 [INDEX_op_aad] = CC_OSZAPC,
4167 [INDEX_op_aas] = CC_OSZAPC,
4168 [INDEX_op_aaa] = CC_OSZAPC,
4169 [INDEX_op_das] = CC_OSZAPC,
4170 [INDEX_op_daa] = CC_OSZAPC,
4171
4172 [INDEX_op_movb_eflags_T0] = CC_S | CC_Z | CC_A | CC_P | CC_C,
4173 [INDEX_op_movw_eflags_T0] = CC_OSZAPC,
4174 [INDEX_op_movl_eflags_T0] = CC_OSZAPC,
4175 [INDEX_op_clc] = CC_C,
4176 [INDEX_op_stc] = CC_C,
4177 [INDEX_op_cmc] = CC_C,
4178
4179 [INDEX_op_rolb_T0_T1_cc] = CC_O | CC_C,
4180 [INDEX_op_rolw_T0_T1_cc] = CC_O | CC_C,
4181 [INDEX_op_roll_T0_T1_cc] = CC_O | CC_C,
4182 [INDEX_op_rorb_T0_T1_cc] = CC_O | CC_C,
4183 [INDEX_op_rorw_T0_T1_cc] = CC_O | CC_C,
4184 [INDEX_op_rorl_T0_T1_cc] = CC_O | CC_C,
4185
4186 [INDEX_op_rclb_T0_T1_cc] = CC_O | CC_C,
4187 [INDEX_op_rclw_T0_T1_cc] = CC_O | CC_C,
4188 [INDEX_op_rcll_T0_T1_cc] = CC_O | CC_C,
4189 [INDEX_op_rcrb_T0_T1_cc] = CC_O | CC_C,
4190 [INDEX_op_rcrw_T0_T1_cc] = CC_O | CC_C,
4191 [INDEX_op_rcrl_T0_T1_cc] = CC_O | CC_C,
4192
4193 [INDEX_op_shlb_T0_T1_cc] = CC_OSZAPC,
4194 [INDEX_op_shlw_T0_T1_cc] = CC_OSZAPC,
4195 [INDEX_op_shll_T0_T1_cc] = CC_OSZAPC,
4196
4197 [INDEX_op_shrb_T0_T1_cc] = CC_OSZAPC,
4198 [INDEX_op_shrw_T0_T1_cc] = CC_OSZAPC,
4199 [INDEX_op_shrl_T0_T1_cc] = CC_OSZAPC,
4200
4201 [INDEX_op_sarb_T0_T1_cc] = CC_OSZAPC,
4202 [INDEX_op_sarw_T0_T1_cc] = CC_OSZAPC,
4203 [INDEX_op_sarl_T0_T1_cc] = CC_OSZAPC,
4204
4205 [INDEX_op_shldw_T0_T1_ECX_cc] = CC_OSZAPC,
4206 [INDEX_op_shldl_T0_T1_ECX_cc] = CC_OSZAPC,
4207 [INDEX_op_shldw_T0_T1_im_cc] = CC_OSZAPC,
4208 [INDEX_op_shldl_T0_T1_im_cc] = CC_OSZAPC,
4209
4210 [INDEX_op_shrdw_T0_T1_ECX_cc] = CC_OSZAPC,
4211 [INDEX_op_shrdl_T0_T1_ECX_cc] = CC_OSZAPC,
4212 [INDEX_op_shrdw_T0_T1_im_cc] = CC_OSZAPC,
4213 [INDEX_op_shrdl_T0_T1_im_cc] = CC_OSZAPC,
4214
4215 [INDEX_op_rolb_mem_T0_T1_cc] = CC_O | CC_C,
4216 [INDEX_op_rolw_mem_T0_T1_cc] = CC_O | CC_C,
4217 [INDEX_op_roll_mem_T0_T1_cc] = CC_O | CC_C,
4218 [INDEX_op_rorb_mem_T0_T1_cc] = CC_O | CC_C,
4219 [INDEX_op_rorw_mem_T0_T1_cc] = CC_O | CC_C,
4220 [INDEX_op_rorl_mem_T0_T1_cc] = CC_O | CC_C,
4221
4222 [INDEX_op_rclb_mem_T0_T1_cc] = CC_O | CC_C,
4223 [INDEX_op_rclw_mem_T0_T1_cc] = CC_O | CC_C,
4224 [INDEX_op_rcll_mem_T0_T1_cc] = CC_O | CC_C,
4225 [INDEX_op_rcrb_mem_T0_T1_cc] = CC_O | CC_C,
4226 [INDEX_op_rcrw_mem_T0_T1_cc] = CC_O | CC_C,
4227 [INDEX_op_rcrl_mem_T0_T1_cc] = CC_O | CC_C,
4228
4229 [INDEX_op_shlb_mem_T0_T1_cc] = CC_OSZAPC,
4230 [INDEX_op_shlw_mem_T0_T1_cc] = CC_OSZAPC,
4231 [INDEX_op_shll_mem_T0_T1_cc] = CC_OSZAPC,
4232
4233 [INDEX_op_shrb_mem_T0_T1_cc] = CC_OSZAPC,
4234 [INDEX_op_shrw_mem_T0_T1_cc] = CC_OSZAPC,
4235 [INDEX_op_shrl_mem_T0_T1_cc] = CC_OSZAPC,
4236
4237 [INDEX_op_sarb_mem_T0_T1_cc] = CC_OSZAPC,
4238 [INDEX_op_sarw_mem_T0_T1_cc] = CC_OSZAPC,
4239 [INDEX_op_sarl_mem_T0_T1_cc] = CC_OSZAPC,
4240
4241 [INDEX_op_shldw_mem_T0_T1_ECX_cc] = CC_OSZAPC,
4242 [INDEX_op_shldl_mem_T0_T1_ECX_cc] = CC_OSZAPC,
4243 [INDEX_op_shldw_mem_T0_T1_im_cc] = CC_OSZAPC,
4244 [INDEX_op_shldl_mem_T0_T1_im_cc] = CC_OSZAPC,
4245
4246 [INDEX_op_shrdw_mem_T0_T1_ECX_cc] = CC_OSZAPC,
4247 [INDEX_op_shrdl_mem_T0_T1_ECX_cc] = CC_OSZAPC,
4248 [INDEX_op_shrdw_mem_T0_T1_im_cc] = CC_OSZAPC,
4249 [INDEX_op_shrdl_mem_T0_T1_im_cc] = CC_OSZAPC,
4250
4251 [INDEX_op_btw_T0_T1_cc] = CC_OSZAPC,
4252 [INDEX_op_btl_T0_T1_cc] = CC_OSZAPC,
4253 [INDEX_op_btsw_T0_T1_cc] = CC_OSZAPC,
4254 [INDEX_op_btsl_T0_T1_cc] = CC_OSZAPC,
4255 [INDEX_op_btrw_T0_T1_cc] = CC_OSZAPC,
4256 [INDEX_op_btrl_T0_T1_cc] = CC_OSZAPC,
4257 [INDEX_op_btcw_T0_T1_cc] = CC_OSZAPC,
4258 [INDEX_op_btcl_T0_T1_cc] = CC_OSZAPC,
4259
4260 [INDEX_op_bsfw_T0_cc] = CC_OSZAPC,
4261 [INDEX_op_bsfl_T0_cc] = CC_OSZAPC,
4262 [INDEX_op_bsrw_T0_cc] = CC_OSZAPC,
4263 [INDEX_op_bsrl_T0_cc] = CC_OSZAPC,
4264
4265 [INDEX_op_cmpxchgb_T0_T1_EAX_cc] = CC_OSZAPC,
4266 [INDEX_op_cmpxchgw_T0_T1_EAX_cc] = CC_OSZAPC,
4267 [INDEX_op_cmpxchgl_T0_T1_EAX_cc] = CC_OSZAPC,
4268
4269 [INDEX_op_cmpxchgb_mem_T0_T1_EAX_cc] = CC_OSZAPC,
4270 [INDEX_op_cmpxchgw_mem_T0_T1_EAX_cc] = CC_OSZAPC,
4271 [INDEX_op_cmpxchgl_mem_T0_T1_EAX_cc] = CC_OSZAPC,
4272
4273 [INDEX_op_cmpxchg8b] = CC_Z,
4274 [INDEX_op_lar] = CC_Z,
4275 [INDEX_op_lsl] = CC_Z,
4276 [INDEX_op_fcomi_ST0_FT0] = CC_Z | CC_P | CC_C,
4277 [INDEX_op_fucomi_ST0_FT0] = CC_Z | CC_P | CC_C,
4278 };
4279
4280 /* simpler form of an operation if no flags need to be generated */
4281 static uint16_t opc_simpler[NB_OPS] = {
4282 [INDEX_op_update2_cc] = INDEX_op_nop,
4283 [INDEX_op_update1_cc] = INDEX_op_nop,
4284 [INDEX_op_update_neg_cc] = INDEX_op_nop,
4285 #if 0
4286 /* broken: CC_OP logic must be rewritten */
4287 [INDEX_op_update_inc_cc] = INDEX_op_nop,
4288 #endif
4289 [INDEX_op_rolb_T0_T1_cc] = INDEX_op_rolb_T0_T1,
4290 [INDEX_op_rolw_T0_T1_cc] = INDEX_op_rolw_T0_T1,
4291 [INDEX_op_roll_T0_T1_cc] = INDEX_op_roll_T0_T1,
4292
4293 [INDEX_op_rorb_T0_T1_cc] = INDEX_op_rorb_T0_T1,
4294 [INDEX_op_rorw_T0_T1_cc] = INDEX_op_rorw_T0_T1,
4295 [INDEX_op_rorl_T0_T1_cc] = INDEX_op_rorl_T0_T1,
4296
4297 [INDEX_op_rolb_mem_T0_T1_cc] = INDEX_op_rolb_mem_T0_T1,
4298 [INDEX_op_rolw_mem_T0_T1_cc] = INDEX_op_rolw_mem_T0_T1,
4299 [INDEX_op_roll_mem_T0_T1_cc] = INDEX_op_roll_mem_T0_T1,
4300
4301 [INDEX_op_rorb_mem_T0_T1_cc] = INDEX_op_rorb_mem_T0_T1,
4302 [INDEX_op_rorw_mem_T0_T1_cc] = INDEX_op_rorw_mem_T0_T1,
4303 [INDEX_op_rorl_mem_T0_T1_cc] = INDEX_op_rorl_mem_T0_T1,
4304
4305 [INDEX_op_shlb_T0_T1_cc] = INDEX_op_shlb_T0_T1,
4306 [INDEX_op_shlw_T0_T1_cc] = INDEX_op_shlw_T0_T1,
4307 [INDEX_op_shll_T0_T1_cc] = INDEX_op_shll_T0_T1,
4308
4309 [INDEX_op_shrb_T0_T1_cc] = INDEX_op_shrb_T0_T1,
4310 [INDEX_op_shrw_T0_T1_cc] = INDEX_op_shrw_T0_T1,
4311 [INDEX_op_shrl_T0_T1_cc] = INDEX_op_shrl_T0_T1,
4312
4313 [INDEX_op_sarb_T0_T1_cc] = INDEX_op_sarb_T0_T1,
4314 [INDEX_op_sarw_T0_T1_cc] = INDEX_op_sarw_T0_T1,
4315 [INDEX_op_sarl_T0_T1_cc] = INDEX_op_sarl_T0_T1,
4316 };
4317
4318 void optimize_flags_init(void)
4319 {
4320 int i;
4321 /* put default values in arrays */
4322 for(i = 0; i < NB_OPS; i++) {
4323 if (opc_simpler[i] == 0)
4324 opc_simpler[i] = i;
4325 }
4326 }
4327
4328 /* CPU flags computation optimization: we move backward thru the
4329 generated code to see which flags are needed. The operation is
4330 modified if suitable */
4331 static void optimize_flags(uint16_t *opc_buf, int opc_buf_len)
4332 {
4333 uint16_t *opc_ptr;
4334 int live_flags, write_flags, op;
4335
4336 opc_ptr = opc_buf + opc_buf_len;
4337 /* live_flags contains the flags needed by the next instructions
4338 in the code. At the end of the bloc, we consider that all the
4339 flags are live. */
4340 live_flags = CC_OSZAPC;
4341 while (opc_ptr > opc_buf) {
4342 op = *--opc_ptr;
4343 /* if none of the flags written by the instruction is used,
4344 then we can try to find a simpler instruction */
4345 write_flags = opc_write_flags[op];
4346 if ((live_flags & write_flags) == 0) {
4347 *opc_ptr = opc_simpler[op];
4348 }
4349 /* compute the live flags before the instruction */
4350 live_flags &= ~write_flags;
4351 live_flags |= opc_read_flags[op];
4352 }
4353 }
4354
4355 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
4356 basic block 'tb'. If search_pc is TRUE, also generate PC
4357 information for each intermediate instruction. */
4358 static inline int gen_intermediate_code_internal(CPUState *env,
4359 TranslationBlock *tb,
4360 int search_pc)
4361 {
4362 DisasContext dc1, *dc = &dc1;
4363 uint8_t *pc_ptr;
4364 uint16_t *gen_opc_end;
4365 int flags, j, lj;
4366 uint8_t *pc_start;
4367 uint8_t *cs_base;
4368
4369 /* generate intermediate code */
4370 pc_start = (uint8_t *)tb->pc;
4371 cs_base = (uint8_t *)tb->cs_base;
4372 flags = tb->flags;
4373
4374 dc->pe = env->cr[0] & CR0_PE_MASK;
4375 dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
4376 dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
4377 dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
4378 dc->f_st = 0;
4379 dc->vm86 = (flags >> VM_SHIFT) & 1;
4380 dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
4381 dc->iopl = (flags >> IOPL_SHIFT) & 3;
4382 dc->tf = (flags >> TF_SHIFT) & 1;
4383 dc->singlestep_enabled = env->singlestep_enabled;
4384 dc->cc_op = CC_OP_DYNAMIC;
4385 dc->cs_base = cs_base;
4386 dc->tb = tb;
4387 dc->popl_esp_hack = 0;
4388 /* select memory access functions */
4389 dc->mem_index = 0;
4390 if (flags & HF_SOFTMMU_MASK) {
4391 if (dc->cpl == 3)
4392 dc->mem_index = 6;
4393 else
4394 dc->mem_index = 3;
4395 }
4396 dc->jmp_opt = !(dc->tf || env->singlestep_enabled
4397 #ifndef CONFIG_SOFT_MMU
4398 || (flags & HF_SOFTMMU_MASK)
4399 #endif
4400 );
4401 gen_opc_ptr = gen_opc_buf;
4402 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4403 gen_opparam_ptr = gen_opparam_buf;
4404
4405 dc->is_jmp = DISAS_NEXT;
4406 pc_ptr = pc_start;
4407 lj = -1;
4408
4409 /* if irq were inhibited for the next instruction, we can disable
4410 them here as it is simpler (otherwise jumps would have to
4411 handled as special case) */
4412 if (flags & HF_INHIBIT_IRQ_MASK) {
4413 gen_op_reset_inhibit_irq();
4414 }
4415 for(;;) {
4416 if (env->nb_breakpoints > 0) {
4417 for(j = 0; j < env->nb_breakpoints; j++) {
4418 if (env->breakpoints[j] == (unsigned long)pc_ptr) {
4419 gen_debug(dc, pc_ptr - dc->cs_base);
4420 break;
4421 }
4422 }
4423 }
4424 if (search_pc) {
4425 j = gen_opc_ptr - gen_opc_buf;
4426 if (lj < j) {
4427 lj++;
4428 while (lj < j)
4429 gen_opc_instr_start[lj++] = 0;
4430 }
4431 gen_opc_pc[lj] = (uint32_t)pc_ptr;
4432 gen_opc_cc_op[lj] = dc->cc_op;
4433 gen_opc_instr_start[lj] = 1;
4434 }
4435 pc_ptr = disas_insn(dc, pc_ptr);
4436 /* stop translation if indicated */
4437 if (dc->is_jmp)
4438 break;
4439 /* if single step mode, we generate only one instruction and
4440 generate an exception */
4441 if (dc->tf || dc->singlestep_enabled) {
4442 gen_op_jmp_im(pc_ptr - dc->cs_base);
4443 gen_eob(dc);
4444 break;
4445 }
4446 /* if too long translation, stop generation too */
4447 if (gen_opc_ptr >= gen_opc_end ||
4448 (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32)) {
4449 gen_op_jmp_im(pc_ptr - dc->cs_base);
4450 gen_eob(dc);
4451 break;
4452 }
4453 }
4454 *gen_opc_ptr = INDEX_op_end;
4455 /* we don't forget to fill the last values */
4456 if (search_pc) {
4457 j = gen_opc_ptr - gen_opc_buf;
4458 lj++;
4459 while (lj <= j)
4460 gen_opc_instr_start[lj++] = 0;
4461 }
4462
4463 #ifdef DEBUG_DISAS
4464 if (loglevel) {
4465 fprintf(logfile, "----------------\n");
4466 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4467 disas(logfile, pc_start, pc_ptr - pc_start, 0, !dc->code32);
4468 fprintf(logfile, "\n");
4469
4470 fprintf(logfile, "OP:\n");
4471 dump_ops(gen_opc_buf, gen_opparam_buf);
4472 fprintf(logfile, "\n");
4473 }
4474 #endif
4475
4476 /* optimize flag computations */
4477 optimize_flags(gen_opc_buf, gen_opc_ptr - gen_opc_buf);
4478
4479 #ifdef DEBUG_DISAS
4480 if (loglevel) {
4481 fprintf(logfile, "AFTER FLAGS OPT:\n");
4482 dump_ops(gen_opc_buf, gen_opparam_buf);
4483 fprintf(logfile, "\n");
4484 }
4485 #endif
4486 if (!search_pc)
4487 tb->size = pc_ptr - pc_start;
4488 return 0;
4489 }
4490
4491 int gen_intermediate_code(CPUState *env, TranslationBlock *tb)
4492 {
4493 return gen_intermediate_code_internal(env, tb, 0);
4494 }
4495
4496 int gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
4497 {
4498 return gen_intermediate_code_internal(env, tb, 1);
4499 }
4500
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