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git.proxmox.com Git - qemu.git/blob - target-microblaze/translate.c
2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
4 * Copyright (c) 2009 Edgar E. Iglesias.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
32 #include "microblaze-decode.h"
33 #include "qemu-common.h"
41 #if DISAS_MB && !SIM_COMPAT
42 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
44 # define LOG_DIS(...) do { } while (0)
49 #define EXTRACT_FIELD(src, start, end) \
50 (((src) >> start) & ((1 << (end - start + 1)) - 1))
52 static TCGv env_debug
;
53 static TCGv_ptr cpu_env
;
54 static TCGv cpu_R
[32];
55 static TCGv cpu_SR
[18];
57 static TCGv env_btaken
;
58 static TCGv env_btarget
;
59 static TCGv env_iflags
;
61 #include "gen-icount.h"
63 /* This is the state at translation time. */
64 typedef struct DisasContext
{
67 target_ulong cache_pc
;
76 unsigned int cpustate_changed
;
77 unsigned int delayed_branch
;
78 unsigned int tb_flags
, synced_flags
; /* tb dependent flags. */
79 unsigned int clear_imm
;
84 #define JMP_INDIRECT 2
88 int abort_at_next_insn
;
90 struct TranslationBlock
*tb
;
91 int singlestep_enabled
;
94 static const char *regnames
[] =
96 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
97 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
98 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
99 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
102 static const char *special_regnames
[] =
104 "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
105 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
106 "sr16", "sr17", "sr18"
109 /* Sign extend at translation time. */
110 static inline int sign_extend(unsigned int val
, unsigned int width
)
122 static inline void t_sync_flags(DisasContext
*dc
)
124 /* Synch the tb dependant flags between translator and runtime. */
125 if (dc
->tb_flags
!= dc
->synced_flags
) {
126 tcg_gen_movi_tl(env_iflags
, dc
->tb_flags
);
127 dc
->synced_flags
= dc
->tb_flags
;
131 static inline void t_gen_raise_exception(DisasContext
*dc
, uint32_t index
)
133 TCGv_i32 tmp
= tcg_const_i32(index
);
136 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dc
->pc
);
137 gen_helper_raise_exception(tmp
);
138 tcg_temp_free_i32(tmp
);
139 dc
->is_jmp
= DISAS_UPDATE
;
142 static void gen_goto_tb(DisasContext
*dc
, int n
, target_ulong dest
)
144 TranslationBlock
*tb
;
146 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
148 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dest
);
149 tcg_gen_exit_tb((long)tb
+ n
);
151 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dest
);
156 /* True if ALU operand b is a small immediate that may deserve
158 static inline int dec_alu_op_b_is_small_imm(DisasContext
*dc
)
160 /* Immediate insn without the imm prefix ? */
161 return dc
->type_b
&& !(dc
->tb_flags
& IMM_FLAG
);
164 static inline TCGv
*dec_alu_op_b(DisasContext
*dc
)
167 if (dc
->tb_flags
& IMM_FLAG
)
168 tcg_gen_ori_tl(env_imm
, env_imm
, dc
->imm
);
170 tcg_gen_movi_tl(env_imm
, (int32_t)((int16_t)dc
->imm
));
173 return &cpu_R
[dc
->rb
];
176 static void dec_add(DisasContext
*dc
)
183 LOG_DIS("add%s%s%s r%d r%d r%d\n",
184 dc
->type_b
? "i" : "", k
? "k" : "", c
? "c" : "",
185 dc
->rd
, dc
->ra
, dc
->rb
);
187 if (k
&& !c
&& dc
->rd
)
188 tcg_gen_add_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
190 gen_helper_addkc(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)),
191 tcg_const_tl(k
), tcg_const_tl(c
));
193 TCGv d
= tcg_temp_new();
194 gen_helper_addkc(d
, cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)),
195 tcg_const_tl(k
), tcg_const_tl(c
));
200 static void dec_sub(DisasContext
*dc
)
202 unsigned int u
, cmp
, k
, c
;
207 cmp
= (dc
->imm
& 1) && (!dc
->type_b
) && k
;
210 LOG_DIS("cmp%s r%d, r%d ir=%x\n", u
? "u" : "", dc
->rd
, dc
->ra
, dc
->ir
);
213 gen_helper_cmpu(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
215 gen_helper_cmp(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
218 LOG_DIS("sub%s%s r%d, r%d r%d\n",
219 k
? "k" : "", c
? "c" : "", dc
->rd
, dc
->ra
, dc
->rb
);
225 gen_helper_subkc(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)),
226 tcg_const_tl(k
), tcg_const_tl(c
));
228 gen_helper_subkc(t
, cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)),
229 tcg_const_tl(k
), tcg_const_tl(c
));
233 tcg_gen_sub_tl(cpu_R
[dc
->rd
], *(dec_alu_op_b(dc
)), cpu_R
[dc
->ra
]);
237 static void dec_pattern(DisasContext
*dc
)
242 if ((dc
->tb_flags
& MSR_EE_FLAG
)
243 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
244 && !((dc
->env
->pvr
.regs
[2] & PVR2_USE_PCMP_INSTR
))) {
245 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
246 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
249 mode
= dc
->opcode
& 3;
253 LOG_DIS("pcmpbf r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
255 gen_helper_pcmpbf(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
258 LOG_DIS("pcmpeq r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
260 TCGv t0
= tcg_temp_local_new();
261 l1
= gen_new_label();
262 tcg_gen_movi_tl(t0
, 1);
263 tcg_gen_brcond_tl(TCG_COND_EQ
,
264 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
], l1
);
265 tcg_gen_movi_tl(t0
, 0);
267 tcg_gen_mov_tl(cpu_R
[dc
->rd
], t0
);
272 LOG_DIS("pcmpne r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
273 l1
= gen_new_label();
275 TCGv t0
= tcg_temp_local_new();
276 tcg_gen_movi_tl(t0
, 1);
277 tcg_gen_brcond_tl(TCG_COND_NE
,
278 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
], l1
);
279 tcg_gen_movi_tl(t0
, 0);
281 tcg_gen_mov_tl(cpu_R
[dc
->rd
], t0
);
287 "unsupported pattern insn opcode=%x\n", dc
->opcode
);
292 static void dec_and(DisasContext
*dc
)
296 if (!dc
->type_b
&& (dc
->imm
& (1 << 10))) {
301 not = dc
->opcode
& (1 << 1);
302 LOG_DIS("and%s\n", not ? "n" : "");
308 TCGv t
= tcg_temp_new();
309 tcg_gen_not_tl(t
, *(dec_alu_op_b(dc
)));
310 tcg_gen_and_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], t
);
313 tcg_gen_and_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
316 static void dec_or(DisasContext
*dc
)
318 if (!dc
->type_b
&& (dc
->imm
& (1 << 10))) {
323 LOG_DIS("or r%d r%d r%d imm=%x\n", dc
->rd
, dc
->ra
, dc
->rb
, dc
->imm
);
325 tcg_gen_or_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
328 static void dec_xor(DisasContext
*dc
)
330 if (!dc
->type_b
&& (dc
->imm
& (1 << 10))) {
335 LOG_DIS("xor r%d\n", dc
->rd
);
337 tcg_gen_xor_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
340 static void read_carry(DisasContext
*dc
, TCGv d
)
342 tcg_gen_shri_tl(d
, cpu_SR
[SR_MSR
], 31);
345 static void write_carry(DisasContext
*dc
, TCGv v
)
347 TCGv t0
= tcg_temp_new();
348 tcg_gen_shli_tl(t0
, v
, 31);
349 tcg_gen_sari_tl(t0
, t0
, 31);
350 tcg_gen_mov_tl(env_debug
, t0
);
351 tcg_gen_andi_tl(t0
, t0
, (MSR_C
| MSR_CC
));
352 tcg_gen_andi_tl(cpu_SR
[SR_MSR
], cpu_SR
[SR_MSR
],
354 tcg_gen_or_tl(cpu_SR
[SR_MSR
], cpu_SR
[SR_MSR
], t0
);
359 static inline void msr_read(DisasContext
*dc
, TCGv d
)
361 tcg_gen_mov_tl(d
, cpu_SR
[SR_MSR
]);
364 static inline void msr_write(DisasContext
*dc
, TCGv v
)
366 dc
->cpustate_changed
= 1;
367 tcg_gen_mov_tl(cpu_SR
[SR_MSR
], v
);
368 /* PVR, we have a processor version register. */
369 tcg_gen_ori_tl(cpu_SR
[SR_MSR
], cpu_SR
[SR_MSR
], (1 << 10));
372 static void dec_msr(DisasContext
*dc
)
375 unsigned int sr
, to
, rn
;
376 int mem_index
= cpu_mmu_index(dc
->env
);
378 sr
= dc
->imm
& ((1 << 14) - 1);
379 to
= dc
->imm
& (1 << 14);
382 dc
->cpustate_changed
= 1;
384 /* msrclr and msrset. */
385 if (!(dc
->imm
& (1 << 15))) {
386 unsigned int clr
= dc
->ir
& (1 << 16);
388 LOG_DIS("msr%s r%d imm=%x\n", clr
? "clr" : "set",
391 if (!(dc
->env
->pvr
.regs
[2] & PVR2_USE_MSR_INSTR
)) {
396 if ((dc
->tb_flags
& MSR_EE_FLAG
)
397 && mem_index
== MMU_USER_IDX
&& (dc
->imm
!= 4 && dc
->imm
!= 0)) {
398 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
399 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
404 msr_read(dc
, cpu_R
[dc
->rd
]);
409 tcg_gen_mov_tl(t1
, *(dec_alu_op_b(dc
)));
412 tcg_gen_not_tl(t1
, t1
);
413 tcg_gen_and_tl(t0
, t0
, t1
);
415 tcg_gen_or_tl(t0
, t0
, t1
);
419 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dc
->pc
+ 4);
420 dc
->is_jmp
= DISAS_UPDATE
;
425 if ((dc
->tb_flags
& MSR_EE_FLAG
)
426 && mem_index
== MMU_USER_IDX
) {
427 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
428 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
433 #if !defined(CONFIG_USER_ONLY)
434 /* Catch read/writes to the mmu block. */
435 if ((sr
& ~0xff) == 0x1000) {
437 LOG_DIS("m%ss sr%d r%d imm=%x\n", to
? "t" : "f", sr
, dc
->ra
, dc
->imm
);
439 gen_helper_mmu_write(tcg_const_tl(sr
), cpu_R
[dc
->ra
]);
441 gen_helper_mmu_read(cpu_R
[dc
->rd
], tcg_const_tl(sr
));
447 LOG_DIS("m%ss sr%x r%d imm=%x\n", to
? "t" : "f", sr
, dc
->ra
, dc
->imm
);
452 msr_write(dc
, cpu_R
[dc
->ra
]);
455 tcg_gen_mov_tl(cpu_SR
[SR_EAR
], cpu_R
[dc
->ra
]);
458 tcg_gen_mov_tl(cpu_SR
[SR_ESR
], cpu_R
[dc
->ra
]);
461 /* Ignored at the moment. */
464 cpu_abort(dc
->env
, "unknown mts reg %x\n", sr
);
468 LOG_DIS("m%ss r%d sr%x imm=%x\n", to
? "t" : "f", dc
->rd
, sr
, dc
->imm
);
472 tcg_gen_movi_tl(cpu_R
[dc
->rd
], dc
->pc
);
475 msr_read(dc
, cpu_R
[dc
->rd
]);
478 tcg_gen_mov_tl(cpu_R
[dc
->rd
], cpu_SR
[SR_EAR
]);
481 tcg_gen_mov_tl(cpu_R
[dc
->rd
], cpu_SR
[SR_ESR
]);
484 tcg_gen_movi_tl(cpu_R
[dc
->rd
], 0);
487 tcg_gen_mov_tl(cpu_R
[dc
->rd
], cpu_SR
[SR_BTR
]);
503 tcg_gen_ld_tl(cpu_R
[dc
->rd
],
504 cpu_env
, offsetof(CPUState
, pvr
.regs
[rn
]));
507 cpu_abort(dc
->env
, "unknown mfs reg %x\n", sr
);
513 tcg_gen_movi_tl(cpu_R
[0], 0);
517 /* 64-bit signed mul, lower result in d and upper in d2. */
518 static void t_gen_muls(TCGv d
, TCGv d2
, TCGv a
, TCGv b
)
522 t0
= tcg_temp_new_i64();
523 t1
= tcg_temp_new_i64();
525 tcg_gen_ext_i32_i64(t0
, a
);
526 tcg_gen_ext_i32_i64(t1
, b
);
527 tcg_gen_mul_i64(t0
, t0
, t1
);
529 tcg_gen_trunc_i64_i32(d
, t0
);
530 tcg_gen_shri_i64(t0
, t0
, 32);
531 tcg_gen_trunc_i64_i32(d2
, t0
);
533 tcg_temp_free_i64(t0
);
534 tcg_temp_free_i64(t1
);
537 /* 64-bit unsigned muls, lower result in d and upper in d2. */
538 static void t_gen_mulu(TCGv d
, TCGv d2
, TCGv a
, TCGv b
)
542 t0
= tcg_temp_new_i64();
543 t1
= tcg_temp_new_i64();
545 tcg_gen_extu_i32_i64(t0
, a
);
546 tcg_gen_extu_i32_i64(t1
, b
);
547 tcg_gen_mul_i64(t0
, t0
, t1
);
549 tcg_gen_trunc_i64_i32(d
, t0
);
550 tcg_gen_shri_i64(t0
, t0
, 32);
551 tcg_gen_trunc_i64_i32(d2
, t0
);
553 tcg_temp_free_i64(t0
);
554 tcg_temp_free_i64(t1
);
557 /* Multiplier unit. */
558 static void dec_mul(DisasContext
*dc
)
561 unsigned int subcode
;
563 if ((dc
->tb_flags
& MSR_EE_FLAG
)
564 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
565 && !(dc
->env
->pvr
.regs
[0] & PVR0_USE_HW_MUL_MASK
)) {
566 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
567 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
571 subcode
= dc
->imm
& 3;
572 d
[0] = tcg_temp_new();
573 d
[1] = tcg_temp_new();
576 LOG_DIS("muli r%d r%d %x\n", dc
->rd
, dc
->ra
, dc
->imm
);
577 t_gen_mulu(cpu_R
[dc
->rd
], d
[1], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
581 /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */
582 if (subcode
>= 1 && subcode
<= 3
583 && !((dc
->env
->pvr
.regs
[2] & PVR2_USE_MUL64_MASK
))) {
589 LOG_DIS("mul r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
590 t_gen_mulu(cpu_R
[dc
->rd
], d
[1], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
593 LOG_DIS("mulh r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
594 t_gen_muls(d
[0], cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
597 LOG_DIS("mulhsu r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
598 t_gen_muls(d
[0], cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
601 LOG_DIS("mulhu r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
602 t_gen_mulu(d
[0], cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
605 cpu_abort(dc
->env
, "unknown MUL insn %x\n", subcode
);
614 static void dec_div(DisasContext
*dc
)
621 if ((dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
622 && !((dc
->env
->pvr
.regs
[0] & PVR0_USE_DIV_MASK
))) {
623 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
624 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
628 gen_helper_divu(cpu_R
[dc
->rd
], *(dec_alu_op_b(dc
)), cpu_R
[dc
->ra
]);
630 gen_helper_divs(cpu_R
[dc
->rd
], *(dec_alu_op_b(dc
)), cpu_R
[dc
->ra
]);
632 tcg_gen_movi_tl(cpu_R
[dc
->rd
], 0);
635 static void dec_barrel(DisasContext
*dc
)
640 if ((dc
->tb_flags
& MSR_EE_FLAG
)
641 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
642 && !(dc
->env
->pvr
.regs
[0] & PVR0_USE_BARREL_MASK
)) {
643 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
644 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
648 s
= dc
->imm
& (1 << 10);
649 t
= dc
->imm
& (1 << 9);
651 LOG_DIS("bs%s%s r%d r%d r%d\n",
652 s
? "l" : "r", t
? "a" : "l", dc
->rd
, dc
->ra
, dc
->rb
);
656 tcg_gen_mov_tl(t0
, *(dec_alu_op_b(dc
)));
657 tcg_gen_andi_tl(t0
, t0
, 31);
660 tcg_gen_shl_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], t0
);
663 tcg_gen_sar_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], t0
);
665 tcg_gen_shr_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], t0
);
669 static void dec_bit(DisasContext
*dc
)
673 int mem_index
= cpu_mmu_index(dc
->env
);
675 op
= dc
->ir
& ((1 << 8) - 1);
681 LOG_DIS("src r%d r%d\n", dc
->rd
, dc
->ra
);
682 tcg_gen_andi_tl(t0
, cpu_R
[dc
->ra
], 1);
686 tcg_gen_shli_tl(t1
, t1
, 31);
688 tcg_gen_shri_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], 1);
689 tcg_gen_or_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->rd
], t1
);
702 LOG_DIS("srl r%d r%d\n", dc
->rd
, dc
->ra
);
705 tcg_gen_andi_tl(t0
, cpu_R
[dc
->ra
], 1);
710 tcg_gen_shri_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], 1);
712 tcg_gen_sari_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], 1);
716 LOG_DIS("ext8s r%d r%d\n", dc
->rd
, dc
->ra
);
717 tcg_gen_ext8s_i32(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
]);
720 LOG_DIS("ext16s r%d r%d\n", dc
->rd
, dc
->ra
);
721 tcg_gen_ext16s_i32(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
]);
728 LOG_DIS("wdc r%d\n", dc
->ra
);
729 if ((dc
->tb_flags
& MSR_EE_FLAG
)
730 && mem_index
== MMU_USER_IDX
) {
731 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
732 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
738 LOG_DIS("wic r%d\n", dc
->ra
);
739 if ((dc
->tb_flags
& MSR_EE_FLAG
)
740 && mem_index
== MMU_USER_IDX
) {
741 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
742 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
747 cpu_abort(dc
->env
, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
748 dc
->pc
, op
, dc
->rd
, dc
->ra
, dc
->rb
);
753 static inline void sync_jmpstate(DisasContext
*dc
)
755 if (dc
->jmp
== JMP_DIRECT
) {
756 dc
->jmp
= JMP_INDIRECT
;
757 tcg_gen_movi_tl(env_btaken
, 1);
758 tcg_gen_movi_tl(env_btarget
, dc
->jmp_pc
);
762 static void dec_imm(DisasContext
*dc
)
764 LOG_DIS("imm %x\n", dc
->imm
<< 16);
765 tcg_gen_movi_tl(env_imm
, (dc
->imm
<< 16));
766 dc
->tb_flags
|= IMM_FLAG
;
770 static inline void gen_load(DisasContext
*dc
, TCGv dst
, TCGv addr
,
773 int mem_index
= cpu_mmu_index(dc
->env
);
776 tcg_gen_qemu_ld8u(dst
, addr
, mem_index
);
777 } else if (size
== 2) {
778 tcg_gen_qemu_ld16u(dst
, addr
, mem_index
);
779 } else if (size
== 4) {
780 tcg_gen_qemu_ld32u(dst
, addr
, mem_index
);
782 cpu_abort(dc
->env
, "Incorrect load size %d\n", size
);
785 static inline TCGv
*compute_ldst_addr(DisasContext
*dc
, TCGv
*t
)
787 unsigned int extimm
= dc
->tb_flags
& IMM_FLAG
;
789 /* Treat the fast cases first. */
791 /* If any of the regs is r0, return a ptr to the other. */
793 return &cpu_R
[dc
->rb
];
794 } else if (dc
->rb
== 0) {
795 return &cpu_R
[dc
->ra
];
799 tcg_gen_add_tl(*t
, cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
805 return &cpu_R
[dc
->ra
];
808 tcg_gen_movi_tl(*t
, (int32_t)((int16_t)dc
->imm
));
809 tcg_gen_add_tl(*t
, cpu_R
[dc
->ra
], *t
);
812 tcg_gen_add_tl(*t
, cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
818 static void dec_load(DisasContext
*dc
)
823 size
= 1 << (dc
->opcode
& 3);
824 if (size
> 4 && (dc
->tb_flags
& MSR_EE_FLAG
)
825 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)) {
826 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
827 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
831 LOG_DIS("l %x %d\n", dc
->opcode
, size
);
833 addr
= compute_ldst_addr(dc
, &t
);
835 /* If we get a fault on a dslot, the jmpstate better be in sync. */
838 /* Verify alignment if needed. */
839 if ((dc
->env
->pvr
.regs
[2] & PVR2_UNALIGNED_EXC_MASK
) && size
> 1) {
840 TCGv v
= tcg_temp_new();
843 * Microblaze gives MMU faults priority over faults due to
844 * unaligned addresses. That's why we speculatively do the load
845 * into v. If the load succeeds, we verify alignment of the
846 * address and if that succeeds we write into the destination reg.
848 gen_load(dc
, v
, *addr
, size
);
850 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dc
->pc
);
851 gen_helper_memalign(*addr
, tcg_const_tl(dc
->rd
),
852 tcg_const_tl(0), tcg_const_tl(size
- 1));
854 tcg_gen_mov_tl(cpu_R
[dc
->rd
], v
);
858 gen_load(dc
, cpu_R
[dc
->rd
], *addr
, size
);
860 gen_load(dc
, env_imm
, *addr
, size
);
868 static void gen_store(DisasContext
*dc
, TCGv addr
, TCGv val
,
871 int mem_index
= cpu_mmu_index(dc
->env
);
874 tcg_gen_qemu_st8(val
, addr
, mem_index
);
875 else if (size
== 2) {
876 tcg_gen_qemu_st16(val
, addr
, mem_index
);
877 } else if (size
== 4) {
878 tcg_gen_qemu_st32(val
, addr
, mem_index
);
880 cpu_abort(dc
->env
, "Incorrect store size %d\n", size
);
883 static void dec_store(DisasContext
*dc
)
888 size
= 1 << (dc
->opcode
& 3);
890 if (size
> 4 && (dc
->tb_flags
& MSR_EE_FLAG
)
891 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)) {
892 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
893 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
897 LOG_DIS("s%d%s\n", size
, dc
->type_b
? "i" : "");
899 /* If we get a fault on a dslot, the jmpstate better be in sync. */
901 addr
= compute_ldst_addr(dc
, &t
);
903 gen_store(dc
, *addr
, cpu_R
[dc
->rd
], size
);
905 /* Verify alignment if needed. */
906 if ((dc
->env
->pvr
.regs
[2] & PVR2_UNALIGNED_EXC_MASK
) && size
> 1) {
907 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dc
->pc
);
908 /* FIXME: if the alignment is wrong, we should restore the value
911 gen_helper_memalign(*addr
, tcg_const_tl(dc
->rd
),
912 tcg_const_tl(1), tcg_const_tl(size
- 1));
919 static inline void eval_cc(DisasContext
*dc
, unsigned int cc
,
920 TCGv d
, TCGv a
, TCGv b
)
924 tcg_gen_setcond_tl(TCG_COND_EQ
, d
, a
, b
);
927 tcg_gen_setcond_tl(TCG_COND_NE
, d
, a
, b
);
930 tcg_gen_setcond_tl(TCG_COND_LT
, d
, a
, b
);
933 tcg_gen_setcond_tl(TCG_COND_LE
, d
, a
, b
);
936 tcg_gen_setcond_tl(TCG_COND_GE
, d
, a
, b
);
939 tcg_gen_setcond_tl(TCG_COND_GT
, d
, a
, b
);
942 cpu_abort(dc
->env
, "Unknown condition code %x.\n", cc
);
947 static void eval_cond_jmp(DisasContext
*dc
, TCGv pc_true
, TCGv pc_false
)
951 l1
= gen_new_label();
952 /* Conditional jmp. */
953 tcg_gen_mov_tl(cpu_SR
[SR_PC
], pc_false
);
954 tcg_gen_brcondi_tl(TCG_COND_EQ
, env_btaken
, 0, l1
);
955 tcg_gen_mov_tl(cpu_SR
[SR_PC
], pc_true
);
959 static void dec_bcc(DisasContext
*dc
)
964 cc
= EXTRACT_FIELD(dc
->ir
, 21, 23);
965 dslot
= dc
->ir
& (1 << 25);
966 LOG_DIS("bcc%s r%d %x\n", dslot
? "d" : "", dc
->ra
, dc
->imm
);
968 dc
->delayed_branch
= 1;
970 dc
->delayed_branch
= 2;
971 dc
->tb_flags
|= D_FLAG
;
972 tcg_gen_st_tl(tcg_const_tl(dc
->type_b
&& (dc
->tb_flags
& IMM_FLAG
)),
973 cpu_env
, offsetof(CPUState
, bimm
));
976 if (dec_alu_op_b_is_small_imm(dc
)) {
977 int32_t offset
= (int32_t)((int16_t)dc
->imm
); /* sign-extend. */
979 tcg_gen_movi_tl(env_btarget
, dc
->pc
+ offset
);
981 tcg_gen_movi_tl(env_btarget
, dc
->pc
);
982 tcg_gen_add_tl(env_btarget
, env_btarget
, *(dec_alu_op_b(dc
)));
984 dc
->jmp
= JMP_INDIRECT
;
985 eval_cc(dc
, cc
, env_btaken
, cpu_R
[dc
->ra
], tcg_const_tl(0));
988 static void dec_br(DisasContext
*dc
)
990 unsigned int dslot
, link
, abs
;
991 int mem_index
= cpu_mmu_index(dc
->env
);
993 dslot
= dc
->ir
& (1 << 20);
994 abs
= dc
->ir
& (1 << 19);
995 link
= dc
->ir
& (1 << 18);
996 LOG_DIS("br%s%s%s%s imm=%x\n",
997 abs
? "a" : "", link
? "l" : "",
998 dc
->type_b
? "i" : "", dslot
? "d" : "",
1001 dc
->delayed_branch
= 1;
1003 dc
->delayed_branch
= 2;
1004 dc
->tb_flags
|= D_FLAG
;
1005 tcg_gen_st_tl(tcg_const_tl(dc
->type_b
&& (dc
->tb_flags
& IMM_FLAG
)),
1006 cpu_env
, offsetof(CPUState
, bimm
));
1009 tcg_gen_movi_tl(cpu_R
[dc
->rd
], dc
->pc
);
1011 dc
->jmp
= JMP_INDIRECT
;
1013 tcg_gen_movi_tl(env_btaken
, 1);
1014 tcg_gen_mov_tl(env_btarget
, *(dec_alu_op_b(dc
)));
1015 if (link
&& !dslot
) {
1016 if (!(dc
->tb_flags
& IMM_FLAG
) && (dc
->imm
== 8 || dc
->imm
== 0x18))
1017 t_gen_raise_exception(dc
, EXCP_BREAK
);
1019 if ((dc
->tb_flags
& MSR_EE_FLAG
) && mem_index
== MMU_USER_IDX
) {
1020 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
1021 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1025 t_gen_raise_exception(dc
, EXCP_DEBUG
);
1029 if (dec_alu_op_b_is_small_imm(dc
)) {
1030 dc
->jmp
= JMP_DIRECT
;
1031 dc
->jmp_pc
= dc
->pc
+ (int32_t)((int16_t)dc
->imm
);
1033 tcg_gen_movi_tl(env_btaken
, 1);
1034 tcg_gen_movi_tl(env_btarget
, dc
->pc
);
1035 tcg_gen_add_tl(env_btarget
, env_btarget
, *(dec_alu_op_b(dc
)));
1040 static inline void do_rti(DisasContext
*dc
)
1043 t0
= tcg_temp_new();
1044 t1
= tcg_temp_new();
1045 tcg_gen_shri_tl(t0
, cpu_SR
[SR_MSR
], 1);
1046 tcg_gen_ori_tl(t1
, cpu_SR
[SR_MSR
], MSR_IE
);
1047 tcg_gen_andi_tl(t0
, t0
, (MSR_VM
| MSR_UM
));
1049 tcg_gen_andi_tl(t1
, t1
, ~(MSR_VM
| MSR_UM
));
1050 tcg_gen_or_tl(t1
, t1
, t0
);
1054 dc
->tb_flags
&= ~DRTI_FLAG
;
1057 static inline void do_rtb(DisasContext
*dc
)
1060 t0
= tcg_temp_new();
1061 t1
= tcg_temp_new();
1062 tcg_gen_andi_tl(t1
, cpu_SR
[SR_MSR
], ~MSR_BIP
);
1063 tcg_gen_shri_tl(t0
, t1
, 1);
1064 tcg_gen_andi_tl(t0
, t0
, (MSR_VM
| MSR_UM
));
1066 tcg_gen_andi_tl(t1
, t1
, ~(MSR_VM
| MSR_UM
));
1067 tcg_gen_or_tl(t1
, t1
, t0
);
1071 dc
->tb_flags
&= ~DRTB_FLAG
;
1074 static inline void do_rte(DisasContext
*dc
)
1077 t0
= tcg_temp_new();
1078 t1
= tcg_temp_new();
1080 tcg_gen_ori_tl(t1
, cpu_SR
[SR_MSR
], MSR_EE
);
1081 tcg_gen_andi_tl(t1
, t1
, ~MSR_EIP
);
1082 tcg_gen_shri_tl(t0
, t1
, 1);
1083 tcg_gen_andi_tl(t0
, t0
, (MSR_VM
| MSR_UM
));
1085 tcg_gen_andi_tl(t1
, t1
, ~(MSR_VM
| MSR_UM
));
1086 tcg_gen_or_tl(t1
, t1
, t0
);
1090 dc
->tb_flags
&= ~DRTE_FLAG
;
1093 static void dec_rts(DisasContext
*dc
)
1095 unsigned int b_bit
, i_bit
, e_bit
;
1096 int mem_index
= cpu_mmu_index(dc
->env
);
1098 i_bit
= dc
->ir
& (1 << 21);
1099 b_bit
= dc
->ir
& (1 << 22);
1100 e_bit
= dc
->ir
& (1 << 23);
1102 dc
->delayed_branch
= 2;
1103 dc
->tb_flags
|= D_FLAG
;
1104 tcg_gen_st_tl(tcg_const_tl(dc
->type_b
&& (dc
->tb_flags
& IMM_FLAG
)),
1105 cpu_env
, offsetof(CPUState
, bimm
));
1108 LOG_DIS("rtid ir=%x\n", dc
->ir
);
1109 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1110 && mem_index
== MMU_USER_IDX
) {
1111 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
1112 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1114 dc
->tb_flags
|= DRTI_FLAG
;
1116 LOG_DIS("rtbd ir=%x\n", dc
->ir
);
1117 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1118 && mem_index
== MMU_USER_IDX
) {
1119 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
1120 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1122 dc
->tb_flags
|= DRTB_FLAG
;
1124 LOG_DIS("rted ir=%x\n", dc
->ir
);
1125 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1126 && mem_index
== MMU_USER_IDX
) {
1127 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
1128 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1130 dc
->tb_flags
|= DRTE_FLAG
;
1132 LOG_DIS("rts ir=%x\n", dc
->ir
);
1134 tcg_gen_movi_tl(env_btaken
, 1);
1135 tcg_gen_add_tl(env_btarget
, cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
1138 static void dec_fpu(DisasContext
*dc
)
1140 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1141 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
1142 && !((dc
->env
->pvr
.regs
[2] & PVR2_USE_FPU_MASK
))) {
1143 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_FPU
);
1144 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1148 qemu_log ("unimplemented FPU insn pc=%x opc=%x\n", dc
->pc
, dc
->opcode
);
1149 dc
->abort_at_next_insn
= 1;
1152 static void dec_null(DisasContext
*dc
)
1154 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1155 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)) {
1156 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
1157 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1160 qemu_log ("unknown insn pc=%x opc=%x\n", dc
->pc
, dc
->opcode
);
1161 dc
->abort_at_next_insn
= 1;
1164 static struct decoder_info
{
1169 void (*dec
)(DisasContext
*dc
);
1177 {DEC_BARREL
, dec_barrel
},
1179 {DEC_ST
, dec_store
},
1191 static inline void decode(DisasContext
*dc
)
1196 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
)))
1197 tcg_gen_debug_insn_start(dc
->pc
);
1199 dc
->ir
= ir
= ldl_code(dc
->pc
);
1200 LOG_DIS("%8.8x\t", dc
->ir
);
1205 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1206 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
1207 && (dc
->env
->pvr
.regs
[2] & PVR2_OPCODE_0x0_ILL_MASK
)) {
1208 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
1209 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1213 LOG_DIS("nr_nops=%d\t", dc
->nr_nops
);
1215 if (dc
->nr_nops
> 4)
1216 cpu_abort(dc
->env
, "fetching nop sequence\n");
1218 /* bit 2 seems to indicate insn type. */
1219 dc
->type_b
= ir
& (1 << 29);
1221 dc
->opcode
= EXTRACT_FIELD(ir
, 26, 31);
1222 dc
->rd
= EXTRACT_FIELD(ir
, 21, 25);
1223 dc
->ra
= EXTRACT_FIELD(ir
, 16, 20);
1224 dc
->rb
= EXTRACT_FIELD(ir
, 11, 15);
1225 dc
->imm
= EXTRACT_FIELD(ir
, 0, 15);
1227 /* Large switch for all insns. */
1228 for (i
= 0; i
< ARRAY_SIZE(decinfo
); i
++) {
1229 if ((dc
->opcode
& decinfo
[i
].mask
) == decinfo
[i
].bits
) {
1236 static void check_breakpoint(CPUState
*env
, DisasContext
*dc
)
1240 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
1241 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
1242 if (bp
->pc
== dc
->pc
) {
1243 t_gen_raise_exception(dc
, EXCP_DEBUG
);
1244 dc
->is_jmp
= DISAS_UPDATE
;
1250 /* generate intermediate code for basic block 'tb'. */
1252 gen_intermediate_code_internal(CPUState
*env
, TranslationBlock
*tb
,
1255 uint16_t *gen_opc_end
;
1258 struct DisasContext ctx
;
1259 struct DisasContext
*dc
= &ctx
;
1260 uint32_t next_page_start
, org_flags
;
1265 qemu_log_try_set_file(stderr
);
1270 org_flags
= dc
->synced_flags
= dc
->tb_flags
= tb
->flags
;
1272 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
1274 dc
->is_jmp
= DISAS_NEXT
;
1276 dc
->delayed_branch
= !!(dc
->tb_flags
& D_FLAG
);
1280 dc
->singlestep_enabled
= env
->singlestep_enabled
;
1281 dc
->cpustate_changed
= 0;
1282 dc
->abort_at_next_insn
= 0;
1286 cpu_abort(env
, "Microblaze: unaligned PC=%x\n", pc_start
);
1288 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
1290 qemu_log("--------------\n");
1291 log_cpu_state(env
, 0);
1295 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
1298 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
1300 max_insns
= CF_COUNT_MASK
;
1306 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
1307 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dc
->pc
);
1311 check_breakpoint(env
, dc
);
1314 j
= gen_opc_ptr
- gen_opc_buf
;
1318 gen_opc_instr_start
[lj
++] = 0;
1320 gen_opc_pc
[lj
] = dc
->pc
;
1321 gen_opc_instr_start
[lj
] = 1;
1322 gen_opc_icount
[lj
] = num_insns
;
1326 LOG_DIS("%8.8x:\t", dc
->pc
);
1328 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
1334 dc
->tb_flags
&= ~IMM_FLAG
;
1339 if (dc
->delayed_branch
) {
1340 dc
->delayed_branch
--;
1341 if (!dc
->delayed_branch
) {
1342 if (dc
->tb_flags
& DRTI_FLAG
)
1344 if (dc
->tb_flags
& DRTB_FLAG
)
1346 if (dc
->tb_flags
& DRTE_FLAG
)
1348 /* Clear the delay slot flag. */
1349 dc
->tb_flags
&= ~D_FLAG
;
1350 /* If it is a direct jump, try direct chaining. */
1351 if (dc
->jmp
!= JMP_DIRECT
) {
1352 eval_cond_jmp(dc
, env_btarget
, tcg_const_tl(dc
->pc
));
1353 dc
->is_jmp
= DISAS_JUMP
;
1358 if (env
->singlestep_enabled
)
1360 } while (!dc
->is_jmp
&& !dc
->cpustate_changed
1361 && gen_opc_ptr
< gen_opc_end
1363 && (dc
->pc
< next_page_start
)
1364 && num_insns
< max_insns
);
1367 if (dc
->jmp
== JMP_DIRECT
) {
1368 if (dc
->tb_flags
& D_FLAG
) {
1369 dc
->is_jmp
= DISAS_UPDATE
;
1370 tcg_gen_movi_tl(cpu_SR
[SR_PC
], npc
);
1376 if (tb
->cflags
& CF_LAST_IO
)
1378 /* Force an update if the per-tb cpu state has changed. */
1379 if (dc
->is_jmp
== DISAS_NEXT
1380 && (dc
->cpustate_changed
|| org_flags
!= dc
->tb_flags
)) {
1381 dc
->is_jmp
= DISAS_UPDATE
;
1382 tcg_gen_movi_tl(cpu_SR
[SR_PC
], npc
);
1386 if (unlikely(env
->singlestep_enabled
)) {
1387 t_gen_raise_exception(dc
, EXCP_DEBUG
);
1388 if (dc
->is_jmp
== DISAS_NEXT
)
1389 tcg_gen_movi_tl(cpu_SR
[SR_PC
], npc
);
1391 switch(dc
->is_jmp
) {
1393 gen_goto_tb(dc
, 1, npc
);
1398 /* indicate that the hash table must be used
1399 to find the next TB */
1403 /* nothing more to generate */
1407 gen_icount_end(tb
, num_insns
);
1408 *gen_opc_ptr
= INDEX_op_end
;
1410 j
= gen_opc_ptr
- gen_opc_buf
;
1413 gen_opc_instr_start
[lj
++] = 0;
1415 tb
->size
= dc
->pc
- pc_start
;
1416 tb
->icount
= num_insns
;
1421 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
1424 log_target_disas(pc_start
, dc
->pc
- pc_start
, 0);
1426 qemu_log("\nisize=%d osize=%zd\n",
1427 dc
->pc
- pc_start
, gen_opc_ptr
- gen_opc_buf
);
1431 assert(!dc
->abort_at_next_insn
);
1434 void gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
1436 gen_intermediate_code_internal(env
, tb
, 0);
1439 void gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
1441 gen_intermediate_code_internal(env
, tb
, 1);
1444 void cpu_dump_state (CPUState
*env
, FILE *f
,
1445 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
1453 cpu_fprintf(f
, "IN: PC=%x %s\n",
1454 env
->sregs
[SR_PC
], lookup_symbol(env
->sregs
[SR_PC
]));
1455 cpu_fprintf(f
, "rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
1456 env
->sregs
[SR_MSR
], env
->sregs
[SR_ESR
], env
->sregs
[SR_EAR
],
1457 env
->debug
, env
->imm
, env
->iflags
);
1458 cpu_fprintf(f
, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
1459 env
->btaken
, env
->btarget
,
1460 (env
->sregs
[SR_MSR
] & MSR_UM
) ? "user" : "kernel",
1461 (env
->sregs
[SR_MSR
] & MSR_UMS
) ? "user" : "kernel",
1462 (env
->sregs
[SR_MSR
] & MSR_EIP
),
1463 (env
->sregs
[SR_MSR
] & MSR_IE
));
1465 for (i
= 0; i
< 32; i
++) {
1466 cpu_fprintf(f
, "r%2.2d=%8.8x ", i
, env
->regs
[i
]);
1467 if ((i
+ 1) % 4 == 0)
1468 cpu_fprintf(f
, "\n");
1470 cpu_fprintf(f
, "\n\n");
1473 CPUState
*cpu_mb_init (const char *cpu_model
)
1476 static int tcg_initialized
= 0;
1479 env
= qemu_mallocz(sizeof(CPUState
));
1485 if (tcg_initialized
)
1488 tcg_initialized
= 1;
1490 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
1492 env_debug
= tcg_global_mem_new(TCG_AREG0
,
1493 offsetof(CPUState
, debug
),
1495 env_iflags
= tcg_global_mem_new(TCG_AREG0
,
1496 offsetof(CPUState
, iflags
),
1498 env_imm
= tcg_global_mem_new(TCG_AREG0
,
1499 offsetof(CPUState
, imm
),
1501 env_btarget
= tcg_global_mem_new(TCG_AREG0
,
1502 offsetof(CPUState
, btarget
),
1504 env_btaken
= tcg_global_mem_new(TCG_AREG0
,
1505 offsetof(CPUState
, btaken
),
1507 for (i
= 0; i
< ARRAY_SIZE(cpu_R
); i
++) {
1508 cpu_R
[i
] = tcg_global_mem_new(TCG_AREG0
,
1509 offsetof(CPUState
, regs
[i
]),
1512 for (i
= 0; i
< ARRAY_SIZE(cpu_SR
); i
++) {
1513 cpu_SR
[i
] = tcg_global_mem_new(TCG_AREG0
,
1514 offsetof(CPUState
, sregs
[i
]),
1515 special_regnames
[i
]);
1517 #define GEN_HELPER 2
1523 void cpu_reset (CPUState
*env
)
1525 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
1526 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
1527 log_cpu_state(env
, 0);
1530 memset(env
, 0, offsetof(CPUMBState
, breakpoints
));
1533 env
->pvr
.regs
[0] = PVR0_PVR_FULL_MASK \
1534 | PVR0_USE_BARREL_MASK \
1535 | PVR0_USE_DIV_MASK \
1536 | PVR0_USE_HW_MUL_MASK \
1537 | PVR0_USE_EXC_MASK \
1538 | PVR0_USE_ICACHE_MASK \
1539 | PVR0_USE_DCACHE_MASK \
1542 env
->pvr
.regs
[2] = PVR2_D_OPB_MASK \
1546 | PVR2_USE_MSR_INSTR \
1547 | PVR2_USE_PCMP_INSTR \
1548 | PVR2_USE_BARREL_MASK \
1549 | PVR2_USE_DIV_MASK \
1550 | PVR2_USE_HW_MUL_MASK \
1551 | PVR2_USE_MUL64_MASK \
1553 env
->pvr
.regs
[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
1554 env
->pvr
.regs
[11] = PVR11_USE_MMU
| (16 << 17);
1556 env
->sregs
[SR_MSR
] = 0;
1557 #if defined(CONFIG_USER_ONLY)
1558 /* start in user mode with interrupts enabled. */
1559 env
->pvr
.regs
[10] = 0x0c000000; /* Spartan 3a dsp. */
1561 mmu_init(&env
->mmu
);
1563 env
->mmu
.c_mmu_tlb_access
= 3;
1564 env
->mmu
.c_mmu_zones
= 16;
1568 void gen_pc_load(CPUState
*env
, struct TranslationBlock
*tb
,
1569 unsigned long searched_pc
, int pc_pos
, void *puc
)
1571 env
->sregs
[SR_PC
] = gen_opc_pc
[pc_pos
];