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git.proxmox.com Git - qemu.git/blob - target-mips/exec.h
1 #if !defined(__QEMU_MIPS_EXEC_H__)
2 #define __QEMU_MIPS_EXEC_H__
8 #include "dyngen-exec.h"
11 register struct CPUMIPSState
*env
asm(AREG0
);
13 #if TARGET_LONG_BITS > HOST_LONG_BITS
18 register target_ulong T0
asm(AREG1
);
19 register target_ulong T1
asm(AREG2
);
20 register target_ulong T2
asm(AREG3
);
23 #if defined (USE_HOST_FLOAT_REGS)
24 #error "implement me."
26 #define FDT0 (env->fpu->ft0.fd)
27 #define FDT1 (env->fpu->ft1.fd)
28 #define FDT2 (env->fpu->ft2.fd)
29 #define FST0 (env->fpu->ft0.fs[FP_ENDIAN_IDX])
30 #define FST1 (env->fpu->ft1.fs[FP_ENDIAN_IDX])
31 #define FST2 (env->fpu->ft2.fs[FP_ENDIAN_IDX])
32 #define FSTH0 (env->fpu->ft0.fs[!FP_ENDIAN_IDX])
33 #define FSTH1 (env->fpu->ft1.fs[!FP_ENDIAN_IDX])
34 #define FSTH2 (env->fpu->ft2.fs[!FP_ENDIAN_IDX])
35 #define DT0 (env->fpu->ft0.d)
36 #define DT1 (env->fpu->ft1.d)
37 #define DT2 (env->fpu->ft2.d)
38 #define WT0 (env->fpu->ft0.w[FP_ENDIAN_IDX])
39 #define WT1 (env->fpu->ft1.w[FP_ENDIAN_IDX])
40 #define WT2 (env->fpu->ft2.w[FP_ENDIAN_IDX])
41 #define WTH0 (env->fpu->ft0.w[!FP_ENDIAN_IDX])
42 #define WTH1 (env->fpu->ft1.w[!FP_ENDIAN_IDX])
43 #define WTH2 (env->fpu->ft2.w[!FP_ENDIAN_IDX])
46 #if defined (DEBUG_OP)
47 # define RETURN() __asm__ __volatile__("nop" : : : "memory");
49 # define RETURN() __asm__ __volatile__("" : : : "memory");
55 #if !defined(CONFIG_USER_ONLY)
56 #include "softmmu_exec.h"
57 #endif /* !defined(CONFIG_USER_ONLY) */
59 #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
60 #if TARGET_LONG_BITS > HOST_LONG_BITS
62 void do_dsll32 (void);
64 void do_dsra32 (void);
66 void do_dsrl32 (void);
68 void do_drotr32 (void);
72 void do_drotrv (void);
76 #if HOST_LONG_BITS < 64
79 #if TARGET_LONG_BITS > HOST_LONG_BITS
87 #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
89 #if TARGET_LONG_BITS > HOST_LONG_BITS
93 void do_mfc0_random(void);
94 void do_mfc0_count(void);
95 void do_mtc0_entryhi(uint32_t in
);
96 void do_mtc0_status_debug(uint32_t old
, uint32_t val
);
97 void do_mtc0_status_irqraise_debug(void);
98 void dump_fpu(CPUState
*env
);
99 void fpu_dump_state(CPUState
*env
, FILE *f
,
100 int (*fpu_fprintf
)(FILE *f
, const char *fmt
, ...),
103 void do_lwl_raw (uint32_t);
104 void do_lwr_raw (uint32_t);
105 uint32_t do_swl_raw (uint32_t);
106 uint32_t do_swr_raw (uint32_t);
107 #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
108 void do_ldl_raw (uint64_t);
109 void do_ldr_raw (uint64_t);
110 uint64_t do_sdl_raw (uint64_t);
111 uint64_t do_sdr_raw (uint64_t);
113 #if !defined(CONFIG_USER_ONLY)
114 void do_lwl_user (uint32_t);
115 void do_lwl_kernel (uint32_t);
116 void do_lwr_user (uint32_t);
117 void do_lwr_kernel (uint32_t);
118 uint32_t do_swl_user (uint32_t);
119 uint32_t do_swl_kernel (uint32_t);
120 uint32_t do_swr_user (uint32_t);
121 uint32_t do_swr_kernel (uint32_t);
122 #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
123 void do_ldl_user (uint64_t);
124 void do_ldl_kernel (uint64_t);
125 void do_ldr_user (uint64_t);
126 void do_ldr_kernel (uint64_t);
127 uint64_t do_sdl_user (uint64_t);
128 uint64_t do_sdl_kernel (uint64_t);
129 uint64_t do_sdr_user (uint64_t);
130 uint64_t do_sdr_kernel (uint64_t);
133 void do_pmon (int function
);
137 int cpu_mips_handle_mmu_fault (CPUState
*env
, target_ulong address
, int rw
,
138 int is_user
, int is_softmmu
);
139 void do_interrupt (CPUState
*env
);
140 void r4k_invalidate_tlb (CPUState
*env
, int idx
, int use_extra
);
142 void cpu_loop_exit(void);
143 void do_raise_exception_err (uint32_t exception
, int error_code
);
144 void do_raise_exception (uint32_t exception
);
145 void do_raise_exception_direct_err (uint32_t exception
, int error_code
);
146 void do_raise_exception_direct (uint32_t exception
);
148 void cpu_dump_state(CPUState
*env
, FILE *f
,
149 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
151 void cpu_mips_irqctrl_init (void);
152 uint32_t cpu_mips_get_random (CPUState
*env
);
153 uint32_t cpu_mips_get_count (CPUState
*env
);
154 void cpu_mips_store_count (CPUState
*env
, uint32_t value
);
155 void cpu_mips_store_compare (CPUState
*env
, uint32_t value
);
156 void cpu_mips_start_count(CPUState
*env
);
157 void cpu_mips_stop_count(CPUState
*env
);
158 void cpu_mips_update_irq (CPUState
*env
);
159 void cpu_mips_clock_init (CPUState
*env
);
160 void cpu_mips_tlb_flush (CPUState
*env
, int flush_global
);
162 void do_cfc1 (int reg
);
163 void do_ctc1 (int reg
);
165 #define FOP_PROTO(op) \
166 void do_float_ ## op ## _s(void); \
167 void do_float_ ## op ## _d(void);
180 #define FOP_PROTO(op) \
181 void do_float_ ## op ## _s(void); \
182 void do_float_ ## op ## _d(void); \
183 void do_float_ ## op ## _ps(void);
194 void do_float_cvtd_s(void);
195 void do_float_cvtd_w(void);
196 void do_float_cvtd_l(void);
197 void do_float_cvtl_d(void);
198 void do_float_cvtl_s(void);
199 void do_float_cvtps_pw(void);
200 void do_float_cvtpw_ps(void);
201 void do_float_cvts_d(void);
202 void do_float_cvts_w(void);
203 void do_float_cvts_l(void);
204 void do_float_cvts_pl(void);
205 void do_float_cvts_pu(void);
206 void do_float_cvtw_s(void);
207 void do_float_cvtw_d(void);
209 void do_float_addr_ps(void);
210 void do_float_mulr_ps(void);
212 #define FOP_PROTO(op) \
213 void do_cmp_d_ ## op(long cc); \
214 void do_cmpabs_d_ ## op(long cc); \
215 void do_cmp_s_ ## op(long cc); \
216 void do_cmpabs_s_ ## op(long cc); \
217 void do_cmp_ps_ ## op(long cc); \
218 void do_cmpabs_ps_ ## op(long cc);
238 static inline void env_to_regs(void)
242 static inline void regs_to_env(void)
246 static inline int cpu_halted(CPUState
*env
)
250 if (env
->interrupt_request
&
251 (CPU_INTERRUPT_HARD
| CPU_INTERRUPT_TIMER
)) {
258 static inline void compute_hflags(CPUState
*env
)
260 env
->hflags
&= ~(MIPS_HFLAG_64
| MIPS_HFLAG_CP0
| MIPS_HFLAG_F64
|
261 MIPS_HFLAG_FPU
| MIPS_HFLAG_UM
);
262 if (!(env
->CP0_Status
& (1 << CP0St_EXL
)) &&
263 !(env
->CP0_Status
& (1 << CP0St_ERL
)) &&
264 !(env
->hflags
& MIPS_HFLAG_DM
)) {
265 if (env
->CP0_Status
& (1 << CP0St_UM
))
266 env
->hflags
|= MIPS_HFLAG_UM
;
267 if (env
->CP0_Status
& (1 << CP0St_R0
))
268 env
->hflags
|= MIPS_HFLAG_SM
;
270 #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
271 if (!(env
->hflags
& MIPS_HFLAG_UM
) ||
272 (env
->CP0_Status
& (1 << CP0St_PX
)) ||
273 (env
->CP0_Status
& (1 << CP0St_UX
)))
274 env
->hflags
|= MIPS_HFLAG_64
;
276 if ((env
->CP0_Status
& (1 << CP0St_CU0
)) ||
277 (!(env
->hflags
& MIPS_HFLAG_UM
) &&
278 !(env
->hflags
& MIPS_HFLAG_SM
)))
279 env
->hflags
|= MIPS_HFLAG_CP0
;
280 if (env
->CP0_Status
& (1 << CP0St_CU1
))
281 env
->hflags
|= MIPS_HFLAG_FPU
;
282 if (env
->CP0_Status
& (1 << CP0St_FR
))
283 env
->hflags
|= MIPS_HFLAG_F64
;
286 #endif /* !defined(__QEMU_MIPS_EXEC_H__) */