target-mips/exec.h

   1 #if !defined(__QEMU_MIPS_EXEC_H__)
   2 #define __QEMU_MIPS_EXEC_H__
   3
   4 //#define DEBUG_OP
   5
   6 #include "config.h"
   7 #include "mips-defs.h"
   8 #include "dyngen-exec.h"
   9 #include "cpu-defs.h"
  10
  11 register struct CPUMIPSState *env asm(AREG0);
  12
  13 #if TARGET_LONG_BITS > HOST_LONG_BITS
  14 #define T0 (env->t0)
  15 #else
  16 register target_ulong T0 asm(AREG1);
  17 #endif
  18
  19 #if defined (USE_HOST_FLOAT_REGS)
  20 #error "implement me."
  21 #else
  22 #define FDT0 (env->ft0.fd)
  23 #define FDT1 (env->ft1.fd)
  24 #define FDT2 (env->ft2.fd)
  25 #define FST0 (env->ft0.fs[FP_ENDIAN_IDX])
  26 #define FST1 (env->ft1.fs[FP_ENDIAN_IDX])
  27 #define FST2 (env->ft2.fs[FP_ENDIAN_IDX])
  28 #define FSTH0 (env->ft0.fs[!FP_ENDIAN_IDX])
  29 #define FSTH1 (env->ft1.fs[!FP_ENDIAN_IDX])
  30 #define FSTH2 (env->ft2.fs[!FP_ENDIAN_IDX])
  31 #define DT0 (env->ft0.d)
  32 #define DT1 (env->ft1.d)
  33 #define DT2 (env->ft2.d)
  34 #define WT0 (env->ft0.w[FP_ENDIAN_IDX])
  35 #define WT1 (env->ft1.w[FP_ENDIAN_IDX])
  36 #define WT2 (env->ft2.w[FP_ENDIAN_IDX])
  37 #define WTH0 (env->ft0.w[!FP_ENDIAN_IDX])
  38 #define WTH1 (env->ft1.w[!FP_ENDIAN_IDX])
  39 #define WTH2 (env->ft2.w[!FP_ENDIAN_IDX])
  40 #endif
  41
  42 #include "cpu.h"
  43 #include "exec-all.h"
  44
  45 #if !defined(CONFIG_USER_ONLY)
  46 #include "softmmu_exec.h"
  47 #endif /* !defined(CONFIG_USER_ONLY) */
  48
  49 void do_mtc0_status_debug(uint32_t old, uint32_t val);
  50 void do_mtc0_status_irqraise_debug(void);
  51 void dump_fpu(CPUState *env);
  52 void fpu_dump_state(CPUState *env, FILE *f,
  53                     int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
  54                     int flags);
  55
  56 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
  57                                int mmu_idx, int is_softmmu);
  58 void do_interrupt (CPUState *env);
  59 void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra);
  60
  61 void cpu_loop_exit(void);
  62 void do_raise_exception_err (uint32_t exception, int error_code);
  63 void do_raise_exception (uint32_t exception);
  64
  65 void cpu_dump_state(CPUState *env, FILE *f,
  66                     int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
  67                     int flags);
  68 void cpu_mips_irqctrl_init (void);
  69 uint32_t cpu_mips_get_random (CPUState *env);
  70 uint32_t cpu_mips_get_count (CPUState *env);
  71 void cpu_mips_store_count (CPUState *env, uint32_t value);
  72 void cpu_mips_store_compare (CPUState *env, uint32_t value);
  73 void cpu_mips_start_count(CPUState *env);
  74 void cpu_mips_stop_count(CPUState *env);
  75 void cpu_mips_update_irq (CPUState *env);
  76 void cpu_mips_clock_init (CPUState *env);
  77 void cpu_mips_tlb_flush (CPUState *env, int flush_global);
  78
  79 static always_inline void env_to_regs(void)
  80 {
  81 }
  82
  83 static always_inline void regs_to_env(void)
  84 {
  85 }
  86
  87 static always_inline int cpu_halted(CPUState *env)
  88 {
  89     if (!env->halted)
  90         return 0;
  91     if (env->interrupt_request &
  92         (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
  93         env->halted = 0;
  94         return 0;
  95     }
  96     return EXCP_HALTED;
  97 }
  98
  99 static always_inline void compute_hflags(CPUState *env)
 100 {
 101     env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
 102                      MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU);
 103     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
 104         !(env->CP0_Status & (1 << CP0St_ERL)) &&
 105         !(env->hflags & MIPS_HFLAG_DM)) {
 106         env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
 107     }
 108 #if defined(TARGET_MIPS64)
 109     if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
 110         (env->CP0_Status & (1 << CP0St_PX)) ||
 111         (env->CP0_Status & (1 << CP0St_UX)))
 112         env->hflags |= MIPS_HFLAG_64;
 113 #endif
 114     if ((env->CP0_Status & (1 << CP0St_CU0)) ||
 115         !(env->hflags & MIPS_HFLAG_KSU))
 116         env->hflags |= MIPS_HFLAG_CP0;
 117     if (env->CP0_Status & (1 << CP0St_CU1))
 118         env->hflags |= MIPS_HFLAG_FPU;
 119     if (env->CP0_Status & (1 << CP0St_FR))
 120         env->hflags |= MIPS_HFLAG_F64;
 121     if (env->insn_flags & ISA_MIPS32R2) {
 122         if (env->fpu->fcr0 & (1 << FCR0_F64))
 123             env->hflags |= MIPS_HFLAG_COP1X;
 124     } else if (env->insn_flags & ISA_MIPS32) {
 125         if (env->hflags & MIPS_HFLAG_64)
 126             env->hflags |= MIPS_HFLAG_COP1X;
 127     } else if (env->insn_flags & ISA_MIPS4) {
 128         /* All supported MIPS IV CPUs use the XX (CU3) to enable
 129            and disable the MIPS IV extensions to the MIPS III ISA.
 130            Some other MIPS IV CPUs ignore the bit, so the check here
 131            would be too restrictive for them.  */
 132         if (env->CP0_Status & (1 << CP0St_CU3))
 133             env->hflags |= MIPS_HFLAG_COP1X;
 134     }
 135 }
 136
 137 #endif /* !defined(__QEMU_MIPS_EXEC_H__) */