]>
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2 * MIPS32 emulation for qemu: main translation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 #include "qemu-common.h"
36 //#define MIPS_DEBUG_DISAS
37 //#define MIPS_DEBUG_SIGN_EXTENSIONS
38 //#define MIPS_SINGLE_STEP
40 /* MIPS major opcodes */
41 #define MASK_OP_MAJOR(op) (op & (0x3F << 26))
44 /* indirect opcode tables */
45 OPC_SPECIAL
= (0x00 << 26),
46 OPC_REGIMM
= (0x01 << 26),
47 OPC_CP0
= (0x10 << 26),
48 OPC_CP1
= (0x11 << 26),
49 OPC_CP2
= (0x12 << 26),
50 OPC_CP3
= (0x13 << 26),
51 OPC_SPECIAL2
= (0x1C << 26),
52 OPC_SPECIAL3
= (0x1F << 26),
53 /* arithmetic with immediate */
54 OPC_ADDI
= (0x08 << 26),
55 OPC_ADDIU
= (0x09 << 26),
56 OPC_SLTI
= (0x0A << 26),
57 OPC_SLTIU
= (0x0B << 26),
58 OPC_ANDI
= (0x0C << 26),
59 OPC_ORI
= (0x0D << 26),
60 OPC_XORI
= (0x0E << 26),
61 OPC_LUI
= (0x0F << 26),
62 OPC_DADDI
= (0x18 << 26),
63 OPC_DADDIU
= (0x19 << 26),
64 /* Jump and branches */
66 OPC_JAL
= (0x03 << 26),
67 OPC_BEQ
= (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
68 OPC_BEQL
= (0x14 << 26),
69 OPC_BNE
= (0x05 << 26),
70 OPC_BNEL
= (0x15 << 26),
71 OPC_BLEZ
= (0x06 << 26),
72 OPC_BLEZL
= (0x16 << 26),
73 OPC_BGTZ
= (0x07 << 26),
74 OPC_BGTZL
= (0x17 << 26),
75 OPC_JALX
= (0x1D << 26), /* MIPS 16 only */
77 OPC_LDL
= (0x1A << 26),
78 OPC_LDR
= (0x1B << 26),
79 OPC_LB
= (0x20 << 26),
80 OPC_LH
= (0x21 << 26),
81 OPC_LWL
= (0x22 << 26),
82 OPC_LW
= (0x23 << 26),
83 OPC_LBU
= (0x24 << 26),
84 OPC_LHU
= (0x25 << 26),
85 OPC_LWR
= (0x26 << 26),
86 OPC_LWU
= (0x27 << 26),
87 OPC_SB
= (0x28 << 26),
88 OPC_SH
= (0x29 << 26),
89 OPC_SWL
= (0x2A << 26),
90 OPC_SW
= (0x2B << 26),
91 OPC_SDL
= (0x2C << 26),
92 OPC_SDR
= (0x2D << 26),
93 OPC_SWR
= (0x2E << 26),
94 OPC_LL
= (0x30 << 26),
95 OPC_LLD
= (0x34 << 26),
96 OPC_LD
= (0x37 << 26),
97 OPC_SC
= (0x38 << 26),
98 OPC_SCD
= (0x3C << 26),
99 OPC_SD
= (0x3F << 26),
100 /* Floating point load/store */
101 OPC_LWC1
= (0x31 << 26),
102 OPC_LWC2
= (0x32 << 26),
103 OPC_LDC1
= (0x35 << 26),
104 OPC_LDC2
= (0x36 << 26),
105 OPC_SWC1
= (0x39 << 26),
106 OPC_SWC2
= (0x3A << 26),
107 OPC_SDC1
= (0x3D << 26),
108 OPC_SDC2
= (0x3E << 26),
109 /* MDMX ASE specific */
110 OPC_MDMX
= (0x1E << 26),
111 /* Cache and prefetch */
112 OPC_CACHE
= (0x2F << 26),
113 OPC_PREF
= (0x33 << 26),
114 /* Reserved major opcode */
115 OPC_MAJOR3B_RESERVED
= (0x3B << 26),
118 /* MIPS special opcodes */
119 #define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F)
123 OPC_SLL
= 0x00 | OPC_SPECIAL
,
124 /* NOP is SLL r0, r0, 0 */
125 /* SSNOP is SLL r0, r0, 1 */
126 /* EHB is SLL r0, r0, 3 */
127 OPC_SRL
= 0x02 | OPC_SPECIAL
, /* also ROTR */
128 OPC_SRA
= 0x03 | OPC_SPECIAL
,
129 OPC_SLLV
= 0x04 | OPC_SPECIAL
,
130 OPC_SRLV
= 0x06 | OPC_SPECIAL
, /* also ROTRV */
131 OPC_SRAV
= 0x07 | OPC_SPECIAL
,
132 OPC_DSLLV
= 0x14 | OPC_SPECIAL
,
133 OPC_DSRLV
= 0x16 | OPC_SPECIAL
, /* also DROTRV */
134 OPC_DSRAV
= 0x17 | OPC_SPECIAL
,
135 OPC_DSLL
= 0x38 | OPC_SPECIAL
,
136 OPC_DSRL
= 0x3A | OPC_SPECIAL
, /* also DROTR */
137 OPC_DSRA
= 0x3B | OPC_SPECIAL
,
138 OPC_DSLL32
= 0x3C | OPC_SPECIAL
,
139 OPC_DSRL32
= 0x3E | OPC_SPECIAL
, /* also DROTR32 */
140 OPC_DSRA32
= 0x3F | OPC_SPECIAL
,
141 /* Multiplication / division */
142 OPC_MULT
= 0x18 | OPC_SPECIAL
,
143 OPC_MULTU
= 0x19 | OPC_SPECIAL
,
144 OPC_DIV
= 0x1A | OPC_SPECIAL
,
145 OPC_DIVU
= 0x1B | OPC_SPECIAL
,
146 OPC_DMULT
= 0x1C | OPC_SPECIAL
,
147 OPC_DMULTU
= 0x1D | OPC_SPECIAL
,
148 OPC_DDIV
= 0x1E | OPC_SPECIAL
,
149 OPC_DDIVU
= 0x1F | OPC_SPECIAL
,
150 /* 2 registers arithmetic / logic */
151 OPC_ADD
= 0x20 | OPC_SPECIAL
,
152 OPC_ADDU
= 0x21 | OPC_SPECIAL
,
153 OPC_SUB
= 0x22 | OPC_SPECIAL
,
154 OPC_SUBU
= 0x23 | OPC_SPECIAL
,
155 OPC_AND
= 0x24 | OPC_SPECIAL
,
156 OPC_OR
= 0x25 | OPC_SPECIAL
,
157 OPC_XOR
= 0x26 | OPC_SPECIAL
,
158 OPC_NOR
= 0x27 | OPC_SPECIAL
,
159 OPC_SLT
= 0x2A | OPC_SPECIAL
,
160 OPC_SLTU
= 0x2B | OPC_SPECIAL
,
161 OPC_DADD
= 0x2C | OPC_SPECIAL
,
162 OPC_DADDU
= 0x2D | OPC_SPECIAL
,
163 OPC_DSUB
= 0x2E | OPC_SPECIAL
,
164 OPC_DSUBU
= 0x2F | OPC_SPECIAL
,
166 OPC_JR
= 0x08 | OPC_SPECIAL
, /* Also JR.HB */
167 OPC_JALR
= 0x09 | OPC_SPECIAL
, /* Also JALR.HB */
169 OPC_TGE
= 0x30 | OPC_SPECIAL
,
170 OPC_TGEU
= 0x31 | OPC_SPECIAL
,
171 OPC_TLT
= 0x32 | OPC_SPECIAL
,
172 OPC_TLTU
= 0x33 | OPC_SPECIAL
,
173 OPC_TEQ
= 0x34 | OPC_SPECIAL
,
174 OPC_TNE
= 0x36 | OPC_SPECIAL
,
175 /* HI / LO registers load & stores */
176 OPC_MFHI
= 0x10 | OPC_SPECIAL
,
177 OPC_MTHI
= 0x11 | OPC_SPECIAL
,
178 OPC_MFLO
= 0x12 | OPC_SPECIAL
,
179 OPC_MTLO
= 0x13 | OPC_SPECIAL
,
180 /* Conditional moves */
181 OPC_MOVZ
= 0x0A | OPC_SPECIAL
,
182 OPC_MOVN
= 0x0B | OPC_SPECIAL
,
184 OPC_MOVCI
= 0x01 | OPC_SPECIAL
,
187 OPC_PMON
= 0x05 | OPC_SPECIAL
, /* inofficial */
188 OPC_SYSCALL
= 0x0C | OPC_SPECIAL
,
189 OPC_BREAK
= 0x0D | OPC_SPECIAL
,
190 OPC_SPIM
= 0x0E | OPC_SPECIAL
, /* inofficial */
191 OPC_SYNC
= 0x0F | OPC_SPECIAL
,
193 OPC_SPECIAL15_RESERVED
= 0x15 | OPC_SPECIAL
,
194 OPC_SPECIAL28_RESERVED
= 0x28 | OPC_SPECIAL
,
195 OPC_SPECIAL29_RESERVED
= 0x29 | OPC_SPECIAL
,
196 OPC_SPECIAL35_RESERVED
= 0x35 | OPC_SPECIAL
,
197 OPC_SPECIAL37_RESERVED
= 0x37 | OPC_SPECIAL
,
198 OPC_SPECIAL39_RESERVED
= 0x39 | OPC_SPECIAL
,
199 OPC_SPECIAL3D_RESERVED
= 0x3D | OPC_SPECIAL
,
202 /* Multiplication variants of the vr54xx. */
203 #define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6))
206 OPC_VR54XX_MULS
= (0x03 << 6) | OPC_MULT
,
207 OPC_VR54XX_MULSU
= (0x03 << 6) | OPC_MULTU
,
208 OPC_VR54XX_MACC
= (0x05 << 6) | OPC_MULT
,
209 OPC_VR54XX_MACCU
= (0x05 << 6) | OPC_MULTU
,
210 OPC_VR54XX_MSAC
= (0x07 << 6) | OPC_MULT
,
211 OPC_VR54XX_MSACU
= (0x07 << 6) | OPC_MULTU
,
212 OPC_VR54XX_MULHI
= (0x09 << 6) | OPC_MULT
,
213 OPC_VR54XX_MULHIU
= (0x09 << 6) | OPC_MULTU
,
214 OPC_VR54XX_MULSHI
= (0x0B << 6) | OPC_MULT
,
215 OPC_VR54XX_MULSHIU
= (0x0B << 6) | OPC_MULTU
,
216 OPC_VR54XX_MACCHI
= (0x0D << 6) | OPC_MULT
,
217 OPC_VR54XX_MACCHIU
= (0x0D << 6) | OPC_MULTU
,
218 OPC_VR54XX_MSACHI
= (0x0F << 6) | OPC_MULT
,
219 OPC_VR54XX_MSACHIU
= (0x0F << 6) | OPC_MULTU
,
222 /* REGIMM (rt field) opcodes */
223 #define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
226 OPC_BLTZ
= (0x00 << 16) | OPC_REGIMM
,
227 OPC_BLTZL
= (0x02 << 16) | OPC_REGIMM
,
228 OPC_BGEZ
= (0x01 << 16) | OPC_REGIMM
,
229 OPC_BGEZL
= (0x03 << 16) | OPC_REGIMM
,
230 OPC_BLTZAL
= (0x10 << 16) | OPC_REGIMM
,
231 OPC_BLTZALL
= (0x12 << 16) | OPC_REGIMM
,
232 OPC_BGEZAL
= (0x11 << 16) | OPC_REGIMM
,
233 OPC_BGEZALL
= (0x13 << 16) | OPC_REGIMM
,
234 OPC_TGEI
= (0x08 << 16) | OPC_REGIMM
,
235 OPC_TGEIU
= (0x09 << 16) | OPC_REGIMM
,
236 OPC_TLTI
= (0x0A << 16) | OPC_REGIMM
,
237 OPC_TLTIU
= (0x0B << 16) | OPC_REGIMM
,
238 OPC_TEQI
= (0x0C << 16) | OPC_REGIMM
,
239 OPC_TNEI
= (0x0E << 16) | OPC_REGIMM
,
240 OPC_SYNCI
= (0x1F << 16) | OPC_REGIMM
,
243 /* Special2 opcodes */
244 #define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F)
247 /* Multiply & xxx operations */
248 OPC_MADD
= 0x00 | OPC_SPECIAL2
,
249 OPC_MADDU
= 0x01 | OPC_SPECIAL2
,
250 OPC_MUL
= 0x02 | OPC_SPECIAL2
,
251 OPC_MSUB
= 0x04 | OPC_SPECIAL2
,
252 OPC_MSUBU
= 0x05 | OPC_SPECIAL2
,
254 OPC_CLZ
= 0x20 | OPC_SPECIAL2
,
255 OPC_CLO
= 0x21 | OPC_SPECIAL2
,
256 OPC_DCLZ
= 0x24 | OPC_SPECIAL2
,
257 OPC_DCLO
= 0x25 | OPC_SPECIAL2
,
259 OPC_SDBBP
= 0x3F | OPC_SPECIAL2
,
262 /* Special3 opcodes */
263 #define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
266 OPC_EXT
= 0x00 | OPC_SPECIAL3
,
267 OPC_DEXTM
= 0x01 | OPC_SPECIAL3
,
268 OPC_DEXTU
= 0x02 | OPC_SPECIAL3
,
269 OPC_DEXT
= 0x03 | OPC_SPECIAL3
,
270 OPC_INS
= 0x04 | OPC_SPECIAL3
,
271 OPC_DINSM
= 0x05 | OPC_SPECIAL3
,
272 OPC_DINSU
= 0x06 | OPC_SPECIAL3
,
273 OPC_DINS
= 0x07 | OPC_SPECIAL3
,
274 OPC_FORK
= 0x08 | OPC_SPECIAL3
,
275 OPC_YIELD
= 0x09 | OPC_SPECIAL3
,
276 OPC_BSHFL
= 0x20 | OPC_SPECIAL3
,
277 OPC_DBSHFL
= 0x24 | OPC_SPECIAL3
,
278 OPC_RDHWR
= 0x3B | OPC_SPECIAL3
,
282 #define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
285 OPC_WSBH
= (0x02 << 6) | OPC_BSHFL
,
286 OPC_SEB
= (0x10 << 6) | OPC_BSHFL
,
287 OPC_SEH
= (0x18 << 6) | OPC_BSHFL
,
291 #define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
294 OPC_DSBH
= (0x02 << 6) | OPC_DBSHFL
,
295 OPC_DSHD
= (0x05 << 6) | OPC_DBSHFL
,
298 /* Coprocessor 0 (rs field) */
299 #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
302 OPC_MFC0
= (0x00 << 21) | OPC_CP0
,
303 OPC_DMFC0
= (0x01 << 21) | OPC_CP0
,
304 OPC_MTC0
= (0x04 << 21) | OPC_CP0
,
305 OPC_DMTC0
= (0x05 << 21) | OPC_CP0
,
306 OPC_MFTR
= (0x08 << 21) | OPC_CP0
,
307 OPC_RDPGPR
= (0x0A << 21) | OPC_CP0
,
308 OPC_MFMC0
= (0x0B << 21) | OPC_CP0
,
309 OPC_MTTR
= (0x0C << 21) | OPC_CP0
,
310 OPC_WRPGPR
= (0x0E << 21) | OPC_CP0
,
311 OPC_C0
= (0x10 << 21) | OPC_CP0
,
312 OPC_C0_FIRST
= (0x10 << 21) | OPC_CP0
,
313 OPC_C0_LAST
= (0x1F << 21) | OPC_CP0
,
317 #define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
320 OPC_DMT
= 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
321 OPC_EMT
= 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
322 OPC_DVPE
= 0x01 | (0 << 5) | OPC_MFMC0
,
323 OPC_EVPE
= 0x01 | (1 << 5) | OPC_MFMC0
,
324 OPC_DI
= (0 << 5) | (0x0C << 11) | OPC_MFMC0
,
325 OPC_EI
= (1 << 5) | (0x0C << 11) | OPC_MFMC0
,
328 /* Coprocessor 0 (with rs == C0) */
329 #define MASK_C0(op) MASK_CP0(op) | (op & 0x3F)
332 OPC_TLBR
= 0x01 | OPC_C0
,
333 OPC_TLBWI
= 0x02 | OPC_C0
,
334 OPC_TLBWR
= 0x06 | OPC_C0
,
335 OPC_TLBP
= 0x08 | OPC_C0
,
336 OPC_RFE
= 0x10 | OPC_C0
,
337 OPC_ERET
= 0x18 | OPC_C0
,
338 OPC_DERET
= 0x1F | OPC_C0
,
339 OPC_WAIT
= 0x20 | OPC_C0
,
342 /* Coprocessor 1 (rs field) */
343 #define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
346 OPC_MFC1
= (0x00 << 21) | OPC_CP1
,
347 OPC_DMFC1
= (0x01 << 21) | OPC_CP1
,
348 OPC_CFC1
= (0x02 << 21) | OPC_CP1
,
349 OPC_MFHC1
= (0x03 << 21) | OPC_CP1
,
350 OPC_MTC1
= (0x04 << 21) | OPC_CP1
,
351 OPC_DMTC1
= (0x05 << 21) | OPC_CP1
,
352 OPC_CTC1
= (0x06 << 21) | OPC_CP1
,
353 OPC_MTHC1
= (0x07 << 21) | OPC_CP1
,
354 OPC_BC1
= (0x08 << 21) | OPC_CP1
, /* bc */
355 OPC_BC1ANY2
= (0x09 << 21) | OPC_CP1
,
356 OPC_BC1ANY4
= (0x0A << 21) | OPC_CP1
,
357 OPC_S_FMT
= (0x10 << 21) | OPC_CP1
, /* 16: fmt=single fp */
358 OPC_D_FMT
= (0x11 << 21) | OPC_CP1
, /* 17: fmt=double fp */
359 OPC_E_FMT
= (0x12 << 21) | OPC_CP1
, /* 18: fmt=extended fp */
360 OPC_Q_FMT
= (0x13 << 21) | OPC_CP1
, /* 19: fmt=quad fp */
361 OPC_W_FMT
= (0x14 << 21) | OPC_CP1
, /* 20: fmt=32bit fixed */
362 OPC_L_FMT
= (0x15 << 21) | OPC_CP1
, /* 21: fmt=64bit fixed */
363 OPC_PS_FMT
= (0x16 << 21) | OPC_CP1
, /* 22: fmt=paired single fp */
366 #define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
367 #define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16))
370 OPC_BC1F
= (0x00 << 16) | OPC_BC1
,
371 OPC_BC1T
= (0x01 << 16) | OPC_BC1
,
372 OPC_BC1FL
= (0x02 << 16) | OPC_BC1
,
373 OPC_BC1TL
= (0x03 << 16) | OPC_BC1
,
377 OPC_BC1FANY2
= (0x00 << 16) | OPC_BC1ANY2
,
378 OPC_BC1TANY2
= (0x01 << 16) | OPC_BC1ANY2
,
382 OPC_BC1FANY4
= (0x00 << 16) | OPC_BC1ANY4
,
383 OPC_BC1TANY4
= (0x01 << 16) | OPC_BC1ANY4
,
386 #define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
389 OPC_MFC2
= (0x00 << 21) | OPC_CP2
,
390 OPC_DMFC2
= (0x01 << 21) | OPC_CP2
,
391 OPC_CFC2
= (0x02 << 21) | OPC_CP2
,
392 OPC_MFHC2
= (0x03 << 21) | OPC_CP2
,
393 OPC_MTC2
= (0x04 << 21) | OPC_CP2
,
394 OPC_DMTC2
= (0x05 << 21) | OPC_CP2
,
395 OPC_CTC2
= (0x06 << 21) | OPC_CP2
,
396 OPC_MTHC2
= (0x07 << 21) | OPC_CP2
,
397 OPC_BC2
= (0x08 << 21) | OPC_CP2
,
400 #define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
403 OPC_LWXC1
= 0x00 | OPC_CP3
,
404 OPC_LDXC1
= 0x01 | OPC_CP3
,
405 OPC_LUXC1
= 0x05 | OPC_CP3
,
406 OPC_SWXC1
= 0x08 | OPC_CP3
,
407 OPC_SDXC1
= 0x09 | OPC_CP3
,
408 OPC_SUXC1
= 0x0D | OPC_CP3
,
409 OPC_PREFX
= 0x0F | OPC_CP3
,
410 OPC_ALNV_PS
= 0x1E | OPC_CP3
,
411 OPC_MADD_S
= 0x20 | OPC_CP3
,
412 OPC_MADD_D
= 0x21 | OPC_CP3
,
413 OPC_MADD_PS
= 0x26 | OPC_CP3
,
414 OPC_MSUB_S
= 0x28 | OPC_CP3
,
415 OPC_MSUB_D
= 0x29 | OPC_CP3
,
416 OPC_MSUB_PS
= 0x2E | OPC_CP3
,
417 OPC_NMADD_S
= 0x30 | OPC_CP3
,
418 OPC_NMADD_D
= 0x31 | OPC_CP3
,
419 OPC_NMADD_PS
= 0x36 | OPC_CP3
,
420 OPC_NMSUB_S
= 0x38 | OPC_CP3
,
421 OPC_NMSUB_D
= 0x39 | OPC_CP3
,
422 OPC_NMSUB_PS
= 0x3E | OPC_CP3
,
425 /* global register indices */
426 static TCGv cpu_env
, cpu_gpr
[32], cpu_PC
;
427 static TCGv cpu_HI
[MIPS_DSP_ACC
], cpu_LO
[MIPS_DSP_ACC
], cpu_ACX
[MIPS_DSP_ACC
];
428 static TCGv cpu_dspctrl
, bcond
, btarget
;
429 static TCGv fpu_fpr32
[32], fpu_fpr32h
[32], fpu_fpr64
[32], fpu_fcr0
, fpu_fcr31
;
431 #include "gen-icount.h"
433 static inline void tcg_gen_helper_0_i(void *func
, uint32_t arg
)
436 TCGv tmp
= tcg_const_i32(arg
);
438 tcg_gen_helper_0_1(func
, tmp
);
442 static inline void tcg_gen_helper_0_ii(void *func
, uint32_t arg1
, uint32_t arg2
)
444 TCGv tmp1
= tcg_const_i32(arg1
);
445 TCGv tmp2
= tcg_const_i32(arg2
);
447 tcg_gen_helper_0_2(func
, tmp1
, tmp2
);
452 static inline void tcg_gen_helper_0_1i(void *func
, TCGv arg1
, uint32_t arg2
)
454 TCGv tmp
= tcg_const_i32(arg2
);
456 tcg_gen_helper_0_2(func
, arg1
, tmp
);
460 static inline void tcg_gen_helper_0_2i(void *func
, TCGv arg1
, TCGv arg2
, uint32_t arg3
)
462 TCGv tmp
= tcg_const_i32(arg3
);
464 tcg_gen_helper_0_3(func
, arg1
, arg2
, tmp
);
468 static inline void tcg_gen_helper_0_1ii(void *func
, TCGv arg1
, uint32_t arg2
, uint32_t arg3
)
470 TCGv tmp1
= tcg_const_i32(arg2
);
471 TCGv tmp2
= tcg_const_i32(arg3
);
473 tcg_gen_helper_0_3(func
, arg1
, tmp1
, tmp2
);
478 static inline void tcg_gen_helper_1_i(void *func
, TCGv ret
, uint32_t arg
)
480 TCGv tmp
= tcg_const_i32(arg
);
482 tcg_gen_helper_1_1(func
, ret
, tmp
);
486 static inline void tcg_gen_helper_1_1i(void *func
, TCGv ret
, TCGv arg1
, uint32_t arg2
)
488 TCGv tmp
= tcg_const_i32(arg2
);
490 tcg_gen_helper_1_2(func
, ret
, arg1
, tmp
);
494 static inline void tcg_gen_helper_1_1ii(void *func
, TCGv ret
, TCGv arg1
, uint32_t arg2
, uint32_t arg3
)
496 TCGv tmp1
= tcg_const_i32(arg2
);
497 TCGv tmp2
= tcg_const_i32(arg3
);
499 tcg_gen_helper_1_3(func
, ret
, arg1
, tmp1
, tmp2
);
504 static inline void tcg_gen_helper_1_2i(void *func
, TCGv ret
, TCGv arg1
, TCGv arg2
, uint32_t arg3
)
506 TCGv tmp
= tcg_const_i32(arg3
);
508 tcg_gen_helper_1_3(func
, ret
, arg1
, arg2
, tmp
);
512 static inline void tcg_gen_helper_1_2ii(void *func
, TCGv ret
, TCGv arg1
, TCGv arg2
, uint32_t arg3
, uint32_t arg4
)
514 TCGv tmp1
= tcg_const_i32(arg3
);
515 TCGv tmp2
= tcg_const_i32(arg4
);
517 tcg_gen_helper_1_4(func
, ret
, arg1
, arg2
, tmp1
, tmp2
);
522 typedef struct DisasContext
{
523 struct TranslationBlock
*tb
;
524 target_ulong pc
, saved_pc
;
526 /* Routine used to access memory */
528 uint32_t hflags
, saved_hflags
;
530 target_ulong btarget
;
534 BS_NONE
= 0, /* We go out of the TB without reaching a branch or an
535 * exception condition */
536 BS_STOP
= 1, /* We want to stop translation for any reason */
537 BS_BRANCH
= 2, /* We reached a branch condition */
538 BS_EXCP
= 3, /* We reached an exception condition */
541 static const char *regnames
[] =
542 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
543 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
544 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
545 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
547 static const char *regnames_HI
[] =
548 { "HI0", "HI1", "HI2", "HI3", };
550 static const char *regnames_LO
[] =
551 { "LO0", "LO1", "LO2", "LO3", };
553 static const char *regnames_ACX
[] =
554 { "ACX0", "ACX1", "ACX2", "ACX3", };
556 static const char *fregnames
[] =
557 { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
558 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
559 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
560 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
562 static const char *fregnames_64
[] =
563 { "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7",
564 "F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15",
565 "F16", "F17", "F18", "F19", "F20", "F21", "F22", "F23",
566 "F24", "F25", "F26", "F27", "F28", "F29", "F30", "F31", };
568 static const char *fregnames_h
[] =
569 { "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7",
570 "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15",
571 "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23",
572 "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31", };
574 #ifdef MIPS_DEBUG_DISAS
575 #define MIPS_DEBUG(fmt, args...) \
577 if (loglevel & CPU_LOG_TB_IN_ASM) { \
578 fprintf(logfile, TARGET_FMT_lx ": %08x " fmt "\n", \
579 ctx->pc, ctx->opcode , ##args); \
583 #define MIPS_DEBUG(fmt, args...) do { } while(0)
586 #define MIPS_INVAL(op) \
588 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
589 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
592 /* General purpose registers moves. */
593 static inline void gen_load_gpr (TCGv t
, int reg
)
596 tcg_gen_movi_tl(t
, 0);
598 tcg_gen_mov_tl(t
, cpu_gpr
[reg
]);
601 static inline void gen_store_gpr (TCGv t
, int reg
)
604 tcg_gen_mov_tl(cpu_gpr
[reg
], t
);
607 /* Moves to/from ACX register. */
608 static inline void gen_load_ACX (TCGv t
, int reg
)
610 tcg_gen_mov_tl(t
, cpu_ACX
[reg
]);
613 static inline void gen_store_ACX (TCGv t
, int reg
)
615 tcg_gen_mov_tl(cpu_ACX
[reg
], t
);
618 /* Moves to/from shadow registers. */
619 static inline void gen_load_srsgpr (int from
, int to
)
621 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_TL
);
624 tcg_gen_movi_tl(r_tmp1
, 0);
626 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I32
);
628 tcg_gen_ld_i32(r_tmp2
, cpu_env
, offsetof(CPUState
, CP0_SRSCtl
));
629 tcg_gen_shri_i32(r_tmp2
, r_tmp2
, CP0SRSCtl_PSS
);
630 tcg_gen_andi_i32(r_tmp2
, r_tmp2
, 0xf);
631 tcg_gen_muli_i32(r_tmp2
, r_tmp2
, sizeof(target_ulong
) * 32);
632 tcg_gen_add_i32(r_tmp2
, cpu_env
, r_tmp2
);
634 tcg_gen_ld_tl(r_tmp1
, r_tmp2
, sizeof(target_ulong
) * from
);
635 tcg_temp_free(r_tmp2
);
637 gen_store_gpr(r_tmp1
, to
);
638 tcg_temp_free(r_tmp1
);
641 static inline void gen_store_srsgpr (int from
, int to
)
644 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_TL
);
645 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I32
);
647 gen_load_gpr(r_tmp1
, from
);
648 tcg_gen_ld_i32(r_tmp2
, cpu_env
, offsetof(CPUState
, CP0_SRSCtl
));
649 tcg_gen_shri_i32(r_tmp2
, r_tmp2
, CP0SRSCtl_PSS
);
650 tcg_gen_andi_i32(r_tmp2
, r_tmp2
, 0xf);
651 tcg_gen_muli_i32(r_tmp2
, r_tmp2
, sizeof(target_ulong
) * 32);
652 tcg_gen_add_i32(r_tmp2
, cpu_env
, r_tmp2
);
654 tcg_gen_st_tl(r_tmp1
, r_tmp2
, sizeof(target_ulong
) * to
);
655 tcg_temp_free(r_tmp1
);
656 tcg_temp_free(r_tmp2
);
660 /* Floating point register moves. */
661 static inline void gen_load_fpr32 (TCGv t
, int reg
)
663 tcg_gen_mov_i32(t
, fpu_fpr32
[reg
]);
666 static inline void gen_store_fpr32 (TCGv t
, int reg
)
668 tcg_gen_mov_i32(fpu_fpr32
[reg
], t
);
671 static inline void gen_load_fpr64 (DisasContext
*ctx
, TCGv t
, int reg
)
673 if (ctx
->hflags
& MIPS_HFLAG_F64
)
674 tcg_gen_mov_i64(t
, fpu_fpr64
[reg
]);
676 tcg_gen_concat_i32_i64(t
, fpu_fpr32
[reg
& ~1], fpu_fpr32
[reg
| 1]);
680 static inline void gen_store_fpr64 (DisasContext
*ctx
, TCGv t
, int reg
)
682 if (ctx
->hflags
& MIPS_HFLAG_F64
)
683 tcg_gen_mov_i64(fpu_fpr64
[reg
], t
);
685 tcg_gen_trunc_i64_i32(fpu_fpr32
[reg
& ~1], t
);
686 tcg_gen_shri_i64(t
, t
, 32);
687 tcg_gen_trunc_i64_i32(fpu_fpr32
[reg
| 1], t
);
691 static inline void gen_load_fpr32h (TCGv t
, int reg
)
693 tcg_gen_mov_i32(t
, fpu_fpr32h
[reg
]);
696 static inline void gen_store_fpr32h (TCGv t
, int reg
)
698 tcg_gen_mov_i32(fpu_fpr32h
[reg
], t
);
701 static inline void get_fp_cond (TCGv t
)
703 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
704 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I32
);
706 tcg_gen_shri_i32(r_tmp2
, fpu_fcr31
, 24);
707 tcg_gen_andi_i32(r_tmp2
, r_tmp2
, 0xfe);
708 tcg_gen_shri_i32(r_tmp1
, fpu_fcr31
, 23);
709 tcg_gen_andi_i32(r_tmp1
, r_tmp1
, 0x1);
710 tcg_gen_or_i32(t
, r_tmp1
, r_tmp2
);
711 tcg_temp_free(r_tmp1
);
712 tcg_temp_free(r_tmp2
);
715 typedef void (fcmp_fun32
)(uint32_t, uint32_t, int);
716 typedef void (fcmp_fun64
)(uint64_t, uint64_t, int);
718 #define FOP_CONDS(fcmp_fun, type, fmt) \
719 static fcmp_fun * fcmp ## type ## _ ## fmt ## _table[16] = { \
720 do_cmp ## type ## _ ## fmt ## _f, \
721 do_cmp ## type ## _ ## fmt ## _un, \
722 do_cmp ## type ## _ ## fmt ## _eq, \
723 do_cmp ## type ## _ ## fmt ## _ueq, \
724 do_cmp ## type ## _ ## fmt ## _olt, \
725 do_cmp ## type ## _ ## fmt ## _ult, \
726 do_cmp ## type ## _ ## fmt ## _ole, \
727 do_cmp ## type ## _ ## fmt ## _ule, \
728 do_cmp ## type ## _ ## fmt ## _sf, \
729 do_cmp ## type ## _ ## fmt ## _ngle, \
730 do_cmp ## type ## _ ## fmt ## _seq, \
731 do_cmp ## type ## _ ## fmt ## _ngl, \
732 do_cmp ## type ## _ ## fmt ## _lt, \
733 do_cmp ## type ## _ ## fmt ## _nge, \
734 do_cmp ## type ## _ ## fmt ## _le, \
735 do_cmp ## type ## _ ## fmt ## _ngt, \
737 static inline void gen_cmp ## type ## _ ## fmt(int n, TCGv a, TCGv b, int cc) \
739 tcg_gen_helper_0_2i(fcmp ## type ## _ ## fmt ## _table[n], a, b, cc); \
742 FOP_CONDS(fcmp_fun64
, , d
)
743 FOP_CONDS(fcmp_fun64
, abs
, d
)
744 FOP_CONDS(fcmp_fun32
, , s
)
745 FOP_CONDS(fcmp_fun32
, abs
, s
)
746 FOP_CONDS(fcmp_fun64
, , ps
)
747 FOP_CONDS(fcmp_fun64
, abs
, ps
)
751 #define OP_COND(name, cond) \
752 static inline void glue(gen_op_, name) (TCGv t0, TCGv t1) \
754 int l1 = gen_new_label(); \
755 int l2 = gen_new_label(); \
757 tcg_gen_brcond_tl(cond, t0, t1, l1); \
758 tcg_gen_movi_tl(t0, 0); \
761 tcg_gen_movi_tl(t0, 1); \
764 OP_COND(eq
, TCG_COND_EQ
);
765 OP_COND(ne
, TCG_COND_NE
);
766 OP_COND(ge
, TCG_COND_GE
);
767 OP_COND(geu
, TCG_COND_GEU
);
768 OP_COND(lt
, TCG_COND_LT
);
769 OP_COND(ltu
, TCG_COND_LTU
);
772 #define OP_CONDI(name, cond) \
773 static inline void glue(gen_op_, name) (TCGv t, target_ulong val) \
775 int l1 = gen_new_label(); \
776 int l2 = gen_new_label(); \
778 tcg_gen_brcondi_tl(cond, t, val, l1); \
779 tcg_gen_movi_tl(t, 0); \
782 tcg_gen_movi_tl(t, 1); \
785 OP_CONDI(lti
, TCG_COND_LT
);
786 OP_CONDI(ltiu
, TCG_COND_LTU
);
789 #define OP_CONDZ(name, cond) \
790 static inline void glue(gen_op_, name) (TCGv t) \
792 int l1 = gen_new_label(); \
793 int l2 = gen_new_label(); \
795 tcg_gen_brcondi_tl(cond, t, 0, l1); \
796 tcg_gen_movi_tl(t, 0); \
799 tcg_gen_movi_tl(t, 1); \
802 OP_CONDZ(gez
, TCG_COND_GE
);
803 OP_CONDZ(gtz
, TCG_COND_GT
);
804 OP_CONDZ(lez
, TCG_COND_LE
);
805 OP_CONDZ(ltz
, TCG_COND_LT
);
808 static inline void gen_save_pc(target_ulong pc
)
810 tcg_gen_movi_tl(cpu_PC
, pc
);
813 static inline void save_cpu_state (DisasContext
*ctx
, int do_save_pc
)
815 #if defined MIPS_DEBUG_DISAS
816 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
817 fprintf(logfile
, "hflags %08x saved %08x\n",
818 ctx
->hflags
, ctx
->saved_hflags
);
821 if (do_save_pc
&& ctx
->pc
!= ctx
->saved_pc
) {
822 gen_save_pc(ctx
->pc
);
823 ctx
->saved_pc
= ctx
->pc
;
825 if (ctx
->hflags
!= ctx
->saved_hflags
) {
826 TCGv r_tmp
= tcg_temp_new(TCG_TYPE_I32
);
828 tcg_gen_movi_i32(r_tmp
, ctx
->hflags
);
829 tcg_gen_st_i32(r_tmp
, cpu_env
, offsetof(CPUState
, hflags
));
830 tcg_temp_free(r_tmp
);
831 ctx
->saved_hflags
= ctx
->hflags
;
832 switch (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
838 tcg_gen_movi_tl(btarget
, ctx
->btarget
);
844 static inline void restore_cpu_state (CPUState
*env
, DisasContext
*ctx
)
846 ctx
->saved_hflags
= ctx
->hflags
;
847 switch (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
853 ctx
->btarget
= env
->btarget
;
859 generate_exception_err (DisasContext
*ctx
, int excp
, int err
)
861 save_cpu_state(ctx
, 1);
862 tcg_gen_helper_0_ii(do_raise_exception_err
, excp
, err
);
863 tcg_gen_helper_0_0(do_interrupt_restart
);
868 generate_exception (DisasContext
*ctx
, int excp
)
870 save_cpu_state(ctx
, 1);
871 tcg_gen_helper_0_i(do_raise_exception
, excp
);
872 tcg_gen_helper_0_0(do_interrupt_restart
);
876 /* Addresses computation */
877 static inline void gen_op_addr_add (DisasContext
*ctx
, TCGv t0
, TCGv t1
)
879 tcg_gen_add_tl(t0
, t0
, t1
);
881 #if defined(TARGET_MIPS64)
882 /* For compatibility with 32-bit code, data reference in user mode
883 with Status_UX = 0 should be casted to 32-bit and sign extended.
884 See the MIPS64 PRA manual, section 4.10. */
885 if (((ctx
->hflags
& MIPS_HFLAG_KSU
) == MIPS_HFLAG_UM
) &&
886 !(ctx
->hflags
& MIPS_HFLAG_UX
)) {
887 tcg_gen_ext32s_i64(t0
, t0
);
892 static inline void check_cp0_enabled(DisasContext
*ctx
)
894 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_CP0
)))
895 generate_exception_err(ctx
, EXCP_CpU
, 1);
898 static inline void check_cp1_enabled(DisasContext
*ctx
)
900 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_FPU
)))
901 generate_exception_err(ctx
, EXCP_CpU
, 1);
904 /* Verify that the processor is running with COP1X instructions enabled.
905 This is associated with the nabla symbol in the MIPS32 and MIPS64
908 static inline void check_cop1x(DisasContext
*ctx
)
910 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_COP1X
)))
911 generate_exception(ctx
, EXCP_RI
);
914 /* Verify that the processor is running with 64-bit floating-point
915 operations enabled. */
917 static inline void check_cp1_64bitmode(DisasContext
*ctx
)
919 if (unlikely(~ctx
->hflags
& (MIPS_HFLAG_F64
| MIPS_HFLAG_COP1X
)))
920 generate_exception(ctx
, EXCP_RI
);
924 * Verify if floating point register is valid; an operation is not defined
925 * if bit 0 of any register specification is set and the FR bit in the
926 * Status register equals zero, since the register numbers specify an
927 * even-odd pair of adjacent coprocessor general registers. When the FR bit
928 * in the Status register equals one, both even and odd register numbers
929 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
931 * Multiple 64 bit wide registers can be checked by calling
932 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
934 static inline void check_cp1_registers(DisasContext
*ctx
, int regs
)
936 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_F64
) && (regs
& 1)))
937 generate_exception(ctx
, EXCP_RI
);
940 /* This code generates a "reserved instruction" exception if the
941 CPU does not support the instruction set corresponding to flags. */
942 static inline void check_insn(CPUState
*env
, DisasContext
*ctx
, int flags
)
944 if (unlikely(!(env
->insn_flags
& flags
)))
945 generate_exception(ctx
, EXCP_RI
);
948 /* This code generates a "reserved instruction" exception if 64-bit
949 instructions are not enabled. */
950 static inline void check_mips_64(DisasContext
*ctx
)
952 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_64
)))
953 generate_exception(ctx
, EXCP_RI
);
956 /* load/store instructions. */
957 #define OP_LD(insn,fname) \
958 static inline void op_ldst_##insn(TCGv t0, DisasContext *ctx) \
960 tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx); \
967 #if defined(TARGET_MIPS64)
973 #define OP_ST(insn,fname) \
974 static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
976 tcg_gen_qemu_##fname(t1, t0, ctx->mem_idx); \
981 #if defined(TARGET_MIPS64)
986 #define OP_LD_ATOMIC(insn,fname) \
987 static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
989 tcg_gen_mov_tl(t1, t0); \
990 tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx); \
991 tcg_gen_st_tl(t1, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
993 OP_LD_ATOMIC(ll
,ld32s
);
994 #if defined(TARGET_MIPS64)
995 OP_LD_ATOMIC(lld
,ld64
);
999 #define OP_ST_ATOMIC(insn,fname,almask) \
1000 static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
1002 TCGv r_tmp = tcg_temp_local_new(TCG_TYPE_TL); \
1003 int l1 = gen_new_label(); \
1004 int l2 = gen_new_label(); \
1005 int l3 = gen_new_label(); \
1007 tcg_gen_andi_tl(r_tmp, t0, almask); \
1008 tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp, 0, l1); \
1009 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
1010 generate_exception(ctx, EXCP_AdES); \
1011 gen_set_label(l1); \
1012 tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
1013 tcg_gen_brcond_tl(TCG_COND_NE, t0, r_tmp, l2); \
1014 tcg_gen_qemu_##fname(t1, t0, ctx->mem_idx); \
1015 tcg_gen_movi_tl(t0, 1); \
1017 gen_set_label(l2); \
1018 tcg_gen_movi_tl(t0, 0); \
1019 gen_set_label(l3); \
1020 tcg_temp_free(r_tmp); \
1022 OP_ST_ATOMIC(sc
,st32
,0x3);
1023 #if defined(TARGET_MIPS64)
1024 OP_ST_ATOMIC(scd
,st64
,0x7);
1028 /* Load and store */
1029 static void gen_ldst (DisasContext
*ctx
, uint32_t opc
, int rt
,
1030 int base
, int16_t offset
)
1032 const char *opn
= "ldst";
1033 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
1034 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
1037 tcg_gen_movi_tl(t0
, offset
);
1038 } else if (offset
== 0) {
1039 gen_load_gpr(t0
, base
);
1041 gen_load_gpr(t0
, base
);
1042 tcg_gen_movi_tl(t1
, offset
);
1043 gen_op_addr_add(ctx
, t0
, t1
);
1045 /* Don't do NOP if destination is zero: we must perform the actual
1048 #if defined(TARGET_MIPS64)
1050 op_ldst_lwu(t0
, ctx
);
1051 gen_store_gpr(t0
, rt
);
1055 op_ldst_ld(t0
, ctx
);
1056 gen_store_gpr(t0
, rt
);
1060 op_ldst_lld(t0
, t1
, ctx
);
1061 gen_store_gpr(t0
, rt
);
1065 gen_load_gpr(t1
, rt
);
1066 op_ldst_sd(t0
, t1
, ctx
);
1070 save_cpu_state(ctx
, 1);
1071 gen_load_gpr(t1
, rt
);
1072 op_ldst_scd(t0
, t1
, ctx
);
1073 gen_store_gpr(t0
, rt
);
1077 save_cpu_state(ctx
, 1);
1078 gen_load_gpr(t1
, rt
);
1079 tcg_gen_helper_1_2i(do_ldl
, t1
, t0
, t1
, ctx
->mem_idx
);
1080 gen_store_gpr(t1
, rt
);
1084 save_cpu_state(ctx
, 1);
1085 gen_load_gpr(t1
, rt
);
1086 tcg_gen_helper_0_2i(do_sdl
, t0
, t1
, ctx
->mem_idx
);
1090 save_cpu_state(ctx
, 1);
1091 gen_load_gpr(t1
, rt
);
1092 tcg_gen_helper_1_2i(do_ldr
, t1
, t0
, t1
, ctx
->mem_idx
);
1093 gen_store_gpr(t1
, rt
);
1097 save_cpu_state(ctx
, 1);
1098 gen_load_gpr(t1
, rt
);
1099 tcg_gen_helper_0_2i(do_sdr
, t0
, t1
, ctx
->mem_idx
);
1104 op_ldst_lw(t0
, ctx
);
1105 gen_store_gpr(t0
, rt
);
1109 gen_load_gpr(t1
, rt
);
1110 op_ldst_sw(t0
, t1
, ctx
);
1114 op_ldst_lh(t0
, ctx
);
1115 gen_store_gpr(t0
, rt
);
1119 gen_load_gpr(t1
, rt
);
1120 op_ldst_sh(t0
, t1
, ctx
);
1124 op_ldst_lhu(t0
, ctx
);
1125 gen_store_gpr(t0
, rt
);
1129 op_ldst_lb(t0
, ctx
);
1130 gen_store_gpr(t0
, rt
);
1134 gen_load_gpr(t1
, rt
);
1135 op_ldst_sb(t0
, t1
, ctx
);
1139 op_ldst_lbu(t0
, ctx
);
1140 gen_store_gpr(t0
, rt
);
1144 save_cpu_state(ctx
, 1);
1145 gen_load_gpr(t1
, rt
);
1146 tcg_gen_helper_1_2i(do_lwl
, t1
, t0
, t1
, ctx
->mem_idx
);
1147 gen_store_gpr(t1
, rt
);
1151 save_cpu_state(ctx
, 1);
1152 gen_load_gpr(t1
, rt
);
1153 tcg_gen_helper_0_2i(do_swl
, t0
, t1
, ctx
->mem_idx
);
1157 save_cpu_state(ctx
, 1);
1158 gen_load_gpr(t1
, rt
);
1159 tcg_gen_helper_1_2i(do_lwr
, t1
, t0
, t1
, ctx
->mem_idx
);
1160 gen_store_gpr(t1
, rt
);
1164 save_cpu_state(ctx
, 1);
1165 gen_load_gpr(t1
, rt
);
1166 tcg_gen_helper_0_2i(do_swr
, t0
, t1
, ctx
->mem_idx
);
1170 op_ldst_ll(t0
, t1
, ctx
);
1171 gen_store_gpr(t0
, rt
);
1175 save_cpu_state(ctx
, 1);
1176 gen_load_gpr(t1
, rt
);
1177 op_ldst_sc(t0
, t1
, ctx
);
1178 gen_store_gpr(t0
, rt
);
1183 generate_exception(ctx
, EXCP_RI
);
1186 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
1192 /* Load and store */
1193 static void gen_flt_ldst (DisasContext
*ctx
, uint32_t opc
, int ft
,
1194 int base
, int16_t offset
)
1196 const char *opn
= "flt_ldst";
1197 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
1200 tcg_gen_movi_tl(t0
, offset
);
1201 } else if (offset
== 0) {
1202 gen_load_gpr(t0
, base
);
1204 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
1206 gen_load_gpr(t0
, base
);
1207 tcg_gen_movi_tl(t1
, offset
);
1208 gen_op_addr_add(ctx
, t0
, t1
);
1211 /* Don't do NOP if destination is zero: we must perform the actual
1216 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
1218 tcg_gen_qemu_ld32s(fp0
, t0
, ctx
->mem_idx
);
1219 gen_store_fpr32(fp0
, ft
);
1226 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
1228 gen_load_fpr32(fp0
, ft
);
1229 tcg_gen_qemu_st32(fp0
, t0
, ctx
->mem_idx
);
1236 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
1238 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
1239 gen_store_fpr64(ctx
, fp0
, ft
);
1246 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
1248 gen_load_fpr64(ctx
, fp0
, ft
);
1249 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
1256 generate_exception(ctx
, EXCP_RI
);
1259 MIPS_DEBUG("%s %s, %d(%s)", opn
, fregnames
[ft
], offset
, regnames
[base
]);
1264 /* Arithmetic with immediate operand */
1265 static void gen_arith_imm (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1266 int rt
, int rs
, int16_t imm
)
1269 const char *opn
= "imm arith";
1270 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
1272 if (rt
== 0 && opc
!= OPC_ADDI
&& opc
!= OPC_DADDI
) {
1273 /* If no destination, treat it as a NOP.
1274 For addi, we must generate the overflow exception when needed. */
1278 uimm
= (uint16_t)imm
;
1282 #if defined(TARGET_MIPS64)
1288 uimm
= (target_long
)imm
; /* Sign extend to 32/64 bits */
1293 gen_load_gpr(t0
, rs
);
1296 tcg_gen_movi_tl(t0
, imm
<< 16);
1301 #if defined(TARGET_MIPS64)
1310 gen_load_gpr(t0
, rs
);
1316 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_TL
);
1317 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_TL
);
1318 int l1
= gen_new_label();
1320 save_cpu_state(ctx
, 1);
1321 tcg_gen_ext32s_tl(r_tmp1
, t0
);
1322 tcg_gen_addi_tl(t0
, r_tmp1
, uimm
);
1324 tcg_gen_xori_tl(r_tmp1
, r_tmp1
, ~uimm
);
1325 tcg_gen_xori_tl(r_tmp2
, t0
, uimm
);
1326 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1327 tcg_temp_free(r_tmp2
);
1328 tcg_gen_brcondi_tl(TCG_COND_GE
, r_tmp1
, 0, l1
);
1329 /* operands of same sign, result different sign */
1330 generate_exception(ctx
, EXCP_OVERFLOW
);
1332 tcg_temp_free(r_tmp1
);
1334 tcg_gen_ext32s_tl(t0
, t0
);
1339 tcg_gen_addi_tl(t0
, t0
, uimm
);
1340 tcg_gen_ext32s_tl(t0
, t0
);
1343 #if defined(TARGET_MIPS64)
1346 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_TL
);
1347 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_TL
);
1348 int l1
= gen_new_label();
1350 save_cpu_state(ctx
, 1);
1351 tcg_gen_mov_tl(r_tmp1
, t0
);
1352 tcg_gen_addi_tl(t0
, t0
, uimm
);
1354 tcg_gen_xori_tl(r_tmp1
, r_tmp1
, ~uimm
);
1355 tcg_gen_xori_tl(r_tmp2
, t0
, uimm
);
1356 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1357 tcg_temp_free(r_tmp2
);
1358 tcg_gen_brcondi_tl(TCG_COND_GE
, r_tmp1
, 0, l1
);
1359 /* operands of same sign, result different sign */
1360 generate_exception(ctx
, EXCP_OVERFLOW
);
1362 tcg_temp_free(r_tmp1
);
1367 tcg_gen_addi_tl(t0
, t0
, uimm
);
1372 gen_op_lti(t0
, uimm
);
1376 gen_op_ltiu(t0
, uimm
);
1380 tcg_gen_andi_tl(t0
, t0
, uimm
);
1384 tcg_gen_ori_tl(t0
, t0
, uimm
);
1388 tcg_gen_xori_tl(t0
, t0
, uimm
);
1395 tcg_gen_shli_tl(t0
, t0
, uimm
);
1396 tcg_gen_ext32s_tl(t0
, t0
);
1400 tcg_gen_ext32s_tl(t0
, t0
);
1401 tcg_gen_sari_tl(t0
, t0
, uimm
);
1405 switch ((ctx
->opcode
>> 21) & 0x1f) {
1408 tcg_gen_ext32u_tl(t0
, t0
);
1409 tcg_gen_shri_tl(t0
, t0
, uimm
);
1411 tcg_gen_ext32s_tl(t0
, t0
);
1416 /* rotr is decoded as srl on non-R2 CPUs */
1417 if (env
->insn_flags
& ISA_MIPS32R2
) {
1419 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
1421 tcg_gen_trunc_tl_i32(r_tmp1
, t0
);
1422 tcg_gen_rotri_i32(r_tmp1
, r_tmp1
, uimm
);
1423 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
1424 tcg_temp_free(r_tmp1
);
1429 tcg_gen_ext32u_tl(t0
, t0
);
1430 tcg_gen_shri_tl(t0
, t0
, uimm
);
1432 tcg_gen_ext32s_tl(t0
, t0
);
1438 MIPS_INVAL("invalid srl flag");
1439 generate_exception(ctx
, EXCP_RI
);
1443 #if defined(TARGET_MIPS64)
1445 tcg_gen_shli_tl(t0
, t0
, uimm
);
1449 tcg_gen_sari_tl(t0
, t0
, uimm
);
1453 switch ((ctx
->opcode
>> 21) & 0x1f) {
1455 tcg_gen_shri_tl(t0
, t0
, uimm
);
1459 /* drotr is decoded as dsrl on non-R2 CPUs */
1460 if (env
->insn_flags
& ISA_MIPS32R2
) {
1462 tcg_gen_rotri_tl(t0
, t0
, uimm
);
1466 tcg_gen_shri_tl(t0
, t0
, uimm
);
1471 MIPS_INVAL("invalid dsrl flag");
1472 generate_exception(ctx
, EXCP_RI
);
1477 tcg_gen_shli_tl(t0
, t0
, uimm
+ 32);
1481 tcg_gen_sari_tl(t0
, t0
, uimm
+ 32);
1485 switch ((ctx
->opcode
>> 21) & 0x1f) {
1487 tcg_gen_shri_tl(t0
, t0
, uimm
+ 32);
1491 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */
1492 if (env
->insn_flags
& ISA_MIPS32R2
) {
1493 tcg_gen_rotri_tl(t0
, t0
, uimm
+ 32);
1496 tcg_gen_shri_tl(t0
, t0
, uimm
+ 32);
1501 MIPS_INVAL("invalid dsrl32 flag");
1502 generate_exception(ctx
, EXCP_RI
);
1509 generate_exception(ctx
, EXCP_RI
);
1512 gen_store_gpr(t0
, rt
);
1513 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1519 static void gen_arith (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1520 int rd
, int rs
, int rt
)
1522 const char *opn
= "arith";
1523 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
1524 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
1526 if (rd
== 0 && opc
!= OPC_ADD
&& opc
!= OPC_SUB
1527 && opc
!= OPC_DADD
&& opc
!= OPC_DSUB
) {
1528 /* If no destination, treat it as a NOP.
1529 For add & sub, we must generate the overflow exception when needed. */
1533 gen_load_gpr(t0
, rs
);
1534 /* Specialcase the conventional move operation. */
1535 if (rt
== 0 && (opc
== OPC_ADDU
|| opc
== OPC_DADDU
1536 || opc
== OPC_SUBU
|| opc
== OPC_DSUBU
)) {
1537 gen_store_gpr(t0
, rd
);
1540 gen_load_gpr(t1
, rt
);
1544 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_TL
);
1545 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_TL
);
1546 int l1
= gen_new_label();
1548 save_cpu_state(ctx
, 1);
1549 tcg_gen_ext32s_tl(r_tmp1
, t0
);
1550 tcg_gen_ext32s_tl(r_tmp2
, t1
);
1551 tcg_gen_add_tl(t0
, r_tmp1
, r_tmp2
);
1553 tcg_gen_xor_tl(r_tmp1
, r_tmp1
, t1
);
1554 tcg_gen_xori_tl(r_tmp1
, r_tmp1
, -1);
1555 tcg_gen_xor_tl(r_tmp2
, t0
, t1
);
1556 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1557 tcg_temp_free(r_tmp2
);
1558 tcg_gen_brcondi_tl(TCG_COND_GE
, r_tmp1
, 0, l1
);
1559 /* operands of same sign, result different sign */
1560 generate_exception(ctx
, EXCP_OVERFLOW
);
1562 tcg_temp_free(r_tmp1
);
1564 tcg_gen_ext32s_tl(t0
, t0
);
1569 tcg_gen_add_tl(t0
, t0
, t1
);
1570 tcg_gen_ext32s_tl(t0
, t0
);
1575 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_TL
);
1576 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_TL
);
1577 int l1
= gen_new_label();
1579 save_cpu_state(ctx
, 1);
1580 tcg_gen_ext32s_tl(r_tmp1
, t0
);
1581 tcg_gen_ext32s_tl(r_tmp2
, t1
);
1582 tcg_gen_sub_tl(t0
, r_tmp1
, r_tmp2
);
1584 tcg_gen_xor_tl(r_tmp2
, r_tmp1
, t1
);
1585 tcg_gen_xor_tl(r_tmp1
, r_tmp1
, t0
);
1586 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1587 tcg_temp_free(r_tmp2
);
1588 tcg_gen_brcondi_tl(TCG_COND_GE
, r_tmp1
, 0, l1
);
1589 /* operands of different sign, first operand and result different sign */
1590 generate_exception(ctx
, EXCP_OVERFLOW
);
1592 tcg_temp_free(r_tmp1
);
1594 tcg_gen_ext32s_tl(t0
, t0
);
1599 tcg_gen_sub_tl(t0
, t0
, t1
);
1600 tcg_gen_ext32s_tl(t0
, t0
);
1603 #if defined(TARGET_MIPS64)
1606 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_TL
);
1607 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_TL
);
1608 int l1
= gen_new_label();
1610 save_cpu_state(ctx
, 1);
1611 tcg_gen_mov_tl(r_tmp1
, t0
);
1612 tcg_gen_add_tl(t0
, t0
, t1
);
1614 tcg_gen_xor_tl(r_tmp1
, r_tmp1
, t1
);
1615 tcg_gen_xori_tl(r_tmp1
, r_tmp1
, -1);
1616 tcg_gen_xor_tl(r_tmp2
, t0
, t1
);
1617 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1618 tcg_temp_free(r_tmp2
);
1619 tcg_gen_brcondi_tl(TCG_COND_GE
, r_tmp1
, 0, l1
);
1620 /* operands of same sign, result different sign */
1621 generate_exception(ctx
, EXCP_OVERFLOW
);
1623 tcg_temp_free(r_tmp1
);
1628 tcg_gen_add_tl(t0
, t0
, t1
);
1633 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_TL
);
1634 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_TL
);
1635 int l1
= gen_new_label();
1637 save_cpu_state(ctx
, 1);
1638 tcg_gen_mov_tl(r_tmp1
, t0
);
1639 tcg_gen_sub_tl(t0
, t0
, t1
);
1641 tcg_gen_xor_tl(r_tmp2
, r_tmp1
, t1
);
1642 tcg_gen_xor_tl(r_tmp1
, r_tmp1
, t0
);
1643 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1644 tcg_temp_free(r_tmp2
);
1645 tcg_gen_brcondi_tl(TCG_COND_GE
, r_tmp1
, 0, l1
);
1646 /* operands of different sign, first operand and result different sign */
1647 generate_exception(ctx
, EXCP_OVERFLOW
);
1649 tcg_temp_free(r_tmp1
);
1654 tcg_gen_sub_tl(t0
, t0
, t1
);
1667 tcg_gen_and_tl(t0
, t0
, t1
);
1671 tcg_gen_or_tl(t0
, t0
, t1
);
1672 tcg_gen_not_tl(t0
, t0
);
1676 tcg_gen_or_tl(t0
, t0
, t1
);
1680 tcg_gen_xor_tl(t0
, t0
, t1
);
1684 tcg_gen_mul_tl(t0
, t0
, t1
);
1685 tcg_gen_ext32s_tl(t0
, t0
);
1690 int l1
= gen_new_label();
1692 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
1693 gen_store_gpr(t0
, rd
);
1700 int l1
= gen_new_label();
1702 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, 0, l1
);
1703 gen_store_gpr(t0
, rd
);
1709 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1710 tcg_gen_shl_tl(t0
, t1
, t0
);
1711 tcg_gen_ext32s_tl(t0
, t0
);
1715 tcg_gen_ext32s_tl(t1
, t1
);
1716 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1717 tcg_gen_sar_tl(t0
, t1
, t0
);
1721 switch ((ctx
->opcode
>> 6) & 0x1f) {
1723 tcg_gen_ext32u_tl(t1
, t1
);
1724 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1725 tcg_gen_shr_tl(t0
, t1
, t0
);
1726 tcg_gen_ext32s_tl(t0
, t0
);
1730 /* rotrv is decoded as srlv on non-R2 CPUs */
1731 if (env
->insn_flags
& ISA_MIPS32R2
) {
1732 int l1
= gen_new_label();
1733 int l2
= gen_new_label();
1735 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1736 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
1738 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
1739 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I32
);
1741 tcg_gen_trunc_tl_i32(r_tmp1
, t0
);
1742 tcg_gen_trunc_tl_i32(r_tmp2
, t1
);
1743 tcg_gen_rotr_i32(r_tmp1
, r_tmp1
, r_tmp2
);
1744 tcg_temp_free(r_tmp1
);
1745 tcg_temp_free(r_tmp2
);
1749 tcg_gen_mov_tl(t0
, t1
);
1753 tcg_gen_ext32u_tl(t1
, t1
);
1754 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1755 tcg_gen_shr_tl(t0
, t1
, t0
);
1756 tcg_gen_ext32s_tl(t0
, t0
);
1761 MIPS_INVAL("invalid srlv flag");
1762 generate_exception(ctx
, EXCP_RI
);
1766 #if defined(TARGET_MIPS64)
1768 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1769 tcg_gen_shl_tl(t0
, t1
, t0
);
1773 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1774 tcg_gen_sar_tl(t0
, t1
, t0
);
1778 switch ((ctx
->opcode
>> 6) & 0x1f) {
1780 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1781 tcg_gen_shr_tl(t0
, t1
, t0
);
1785 /* drotrv is decoded as dsrlv on non-R2 CPUs */
1786 if (env
->insn_flags
& ISA_MIPS32R2
) {
1787 int l1
= gen_new_label();
1788 int l2
= gen_new_label();
1790 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1791 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
1793 tcg_gen_rotr_tl(t0
, t1
, t0
);
1797 tcg_gen_mov_tl(t0
, t1
);
1801 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1802 tcg_gen_shr_tl(t0
, t1
, t0
);
1807 MIPS_INVAL("invalid dsrlv flag");
1808 generate_exception(ctx
, EXCP_RI
);
1815 generate_exception(ctx
, EXCP_RI
);
1818 gen_store_gpr(t0
, rd
);
1820 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1826 /* Arithmetic on HI/LO registers */
1827 static void gen_HILO (DisasContext
*ctx
, uint32_t opc
, int reg
)
1829 const char *opn
= "hilo";
1830 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
1832 if (reg
== 0 && (opc
== OPC_MFHI
|| opc
== OPC_MFLO
)) {
1839 tcg_gen_mov_tl(t0
, cpu_HI
[0]);
1840 gen_store_gpr(t0
, reg
);
1844 tcg_gen_mov_tl(t0
, cpu_LO
[0]);
1845 gen_store_gpr(t0
, reg
);
1849 gen_load_gpr(t0
, reg
);
1850 tcg_gen_mov_tl(cpu_HI
[0], t0
);
1854 gen_load_gpr(t0
, reg
);
1855 tcg_gen_mov_tl(cpu_LO
[0], t0
);
1860 generate_exception(ctx
, EXCP_RI
);
1863 MIPS_DEBUG("%s %s", opn
, regnames
[reg
]);
1868 static void gen_muldiv (DisasContext
*ctx
, uint32_t opc
,
1871 const char *opn
= "mul/div";
1872 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
1873 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
1875 gen_load_gpr(t0
, rs
);
1876 gen_load_gpr(t1
, rt
);
1880 int l1
= gen_new_label();
1882 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
1884 int l2
= gen_new_label();
1885 TCGv r_tmp1
= tcg_temp_local_new(TCG_TYPE_I32
);
1886 TCGv r_tmp2
= tcg_temp_local_new(TCG_TYPE_I32
);
1887 TCGv r_tmp3
= tcg_temp_local_new(TCG_TYPE_I32
);
1889 tcg_gen_trunc_tl_i32(r_tmp1
, t0
);
1890 tcg_gen_trunc_tl_i32(r_tmp2
, t1
);
1891 tcg_gen_brcondi_i32(TCG_COND_NE
, r_tmp1
, -1 << 31, l2
);
1892 tcg_gen_brcondi_i32(TCG_COND_NE
, r_tmp2
, -1, l2
);
1893 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
1894 tcg_gen_movi_tl(cpu_HI
[0], 0);
1897 tcg_gen_div_i32(r_tmp3
, r_tmp1
, r_tmp2
);
1898 tcg_gen_rem_i32(r_tmp2
, r_tmp1
, r_tmp2
);
1899 tcg_gen_ext_i32_tl(cpu_LO
[0], r_tmp3
);
1900 tcg_gen_ext_i32_tl(cpu_HI
[0], r_tmp2
);
1901 tcg_temp_free(r_tmp1
);
1902 tcg_temp_free(r_tmp2
);
1903 tcg_temp_free(r_tmp3
);
1911 int l1
= gen_new_label();
1913 tcg_gen_ext32s_tl(t1
, t1
);
1914 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
1916 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
1917 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I32
);
1918 TCGv r_tmp3
= tcg_temp_new(TCG_TYPE_I32
);
1920 tcg_gen_trunc_tl_i32(r_tmp1
, t0
);
1921 tcg_gen_trunc_tl_i32(r_tmp2
, t1
);
1922 tcg_gen_divu_i32(r_tmp3
, r_tmp1
, r_tmp2
);
1923 tcg_gen_remu_i32(r_tmp1
, r_tmp1
, r_tmp2
);
1924 tcg_gen_ext_i32_tl(cpu_LO
[0], r_tmp3
);
1925 tcg_gen_ext_i32_tl(cpu_HI
[0], r_tmp1
);
1926 tcg_temp_free(r_tmp1
);
1927 tcg_temp_free(r_tmp2
);
1928 tcg_temp_free(r_tmp3
);
1936 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I64
);
1937 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I64
);
1939 tcg_gen_ext_tl_i64(r_tmp1
, t0
);
1940 tcg_gen_ext_tl_i64(r_tmp2
, t1
);
1941 tcg_gen_mul_i64(r_tmp1
, r_tmp1
, r_tmp2
);
1942 tcg_temp_free(r_tmp2
);
1943 tcg_gen_trunc_i64_tl(t0
, r_tmp1
);
1944 tcg_gen_shri_i64(r_tmp1
, r_tmp1
, 32);
1945 tcg_gen_trunc_i64_tl(t1
, r_tmp1
);
1946 tcg_temp_free(r_tmp1
);
1947 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
1948 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
1954 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I64
);
1955 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I64
);
1957 tcg_gen_ext32u_tl(t0
, t0
);
1958 tcg_gen_ext32u_tl(t1
, t1
);
1959 tcg_gen_extu_tl_i64(r_tmp1
, t0
);
1960 tcg_gen_extu_tl_i64(r_tmp2
, t1
);
1961 tcg_gen_mul_i64(r_tmp1
, r_tmp1
, r_tmp2
);
1962 tcg_temp_free(r_tmp2
);
1963 tcg_gen_trunc_i64_tl(t0
, r_tmp1
);
1964 tcg_gen_shri_i64(r_tmp1
, r_tmp1
, 32);
1965 tcg_gen_trunc_i64_tl(t1
, r_tmp1
);
1966 tcg_temp_free(r_tmp1
);
1967 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
1968 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
1972 #if defined(TARGET_MIPS64)
1975 int l1
= gen_new_label();
1977 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
1979 int l2
= gen_new_label();
1981 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, -1LL << 63, l2
);
1982 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1LL, l2
);
1983 tcg_gen_mov_tl(cpu_LO
[0], t0
);
1984 tcg_gen_movi_tl(cpu_HI
[0], 0);
1987 tcg_gen_div_i64(cpu_LO
[0], t0
, t1
);
1988 tcg_gen_rem_i64(cpu_HI
[0], t0
, t1
);
1996 int l1
= gen_new_label();
1998 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
1999 tcg_gen_divu_i64(cpu_LO
[0], t0
, t1
);
2000 tcg_gen_remu_i64(cpu_HI
[0], t0
, t1
);
2006 tcg_gen_helper_0_2(do_dmult
, t0
, t1
);
2010 tcg_gen_helper_0_2(do_dmultu
, t0
, t1
);
2016 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I64
);
2017 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I64
);
2019 tcg_gen_ext_tl_i64(r_tmp1
, t0
);
2020 tcg_gen_ext_tl_i64(r_tmp2
, t1
);
2021 tcg_gen_mul_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2022 tcg_gen_concat_tl_i64(r_tmp2
, cpu_LO
[0], cpu_HI
[0]);
2023 tcg_gen_add_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2024 tcg_temp_free(r_tmp2
);
2025 tcg_gen_trunc_i64_tl(t0
, r_tmp1
);
2026 tcg_gen_shri_i64(r_tmp1
, r_tmp1
, 32);
2027 tcg_gen_trunc_i64_tl(t1
, r_tmp1
);
2028 tcg_temp_free(r_tmp1
);
2029 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2030 tcg_gen_ext32s_tl(cpu_LO
[1], t1
);
2036 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I64
);
2037 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I64
);
2039 tcg_gen_ext32u_tl(t0
, t0
);
2040 tcg_gen_ext32u_tl(t1
, t1
);
2041 tcg_gen_extu_tl_i64(r_tmp1
, t0
);
2042 tcg_gen_extu_tl_i64(r_tmp2
, t1
);
2043 tcg_gen_mul_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2044 tcg_gen_concat_tl_i64(r_tmp2
, cpu_LO
[0], cpu_HI
[0]);
2045 tcg_gen_add_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2046 tcg_temp_free(r_tmp2
);
2047 tcg_gen_trunc_i64_tl(t0
, r_tmp1
);
2048 tcg_gen_shri_i64(r_tmp1
, r_tmp1
, 32);
2049 tcg_gen_trunc_i64_tl(t1
, r_tmp1
);
2050 tcg_temp_free(r_tmp1
);
2051 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2052 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2058 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I64
);
2059 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I64
);
2061 tcg_gen_ext_tl_i64(r_tmp1
, t0
);
2062 tcg_gen_ext_tl_i64(r_tmp2
, t1
);
2063 tcg_gen_mul_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2064 tcg_gen_concat_tl_i64(r_tmp2
, cpu_LO
[0], cpu_HI
[0]);
2065 tcg_gen_sub_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2066 tcg_temp_free(r_tmp2
);
2067 tcg_gen_trunc_i64_tl(t0
, r_tmp1
);
2068 tcg_gen_shri_i64(r_tmp1
, r_tmp1
, 32);
2069 tcg_gen_trunc_i64_tl(t1
, r_tmp1
);
2070 tcg_temp_free(r_tmp1
);
2071 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2072 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2078 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I64
);
2079 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I64
);
2081 tcg_gen_ext32u_tl(t0
, t0
);
2082 tcg_gen_ext32u_tl(t1
, t1
);
2083 tcg_gen_extu_tl_i64(r_tmp1
, t0
);
2084 tcg_gen_extu_tl_i64(r_tmp2
, t1
);
2085 tcg_gen_mul_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2086 tcg_gen_concat_tl_i64(r_tmp2
, cpu_LO
[0], cpu_HI
[0]);
2087 tcg_gen_sub_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2088 tcg_temp_free(r_tmp2
);
2089 tcg_gen_trunc_i64_tl(t0
, r_tmp1
);
2090 tcg_gen_shri_i64(r_tmp1
, r_tmp1
, 32);
2091 tcg_gen_trunc_i64_tl(t1
, r_tmp1
);
2092 tcg_temp_free(r_tmp1
);
2093 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2094 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2100 generate_exception(ctx
, EXCP_RI
);
2103 MIPS_DEBUG("%s %s %s", opn
, regnames
[rs
], regnames
[rt
]);
2109 static void gen_mul_vr54xx (DisasContext
*ctx
, uint32_t opc
,
2110 int rd
, int rs
, int rt
)
2112 const char *opn
= "mul vr54xx";
2113 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
2114 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
2116 gen_load_gpr(t0
, rs
);
2117 gen_load_gpr(t1
, rt
);
2120 case OPC_VR54XX_MULS
:
2121 tcg_gen_helper_1_2(do_muls
, t0
, t0
, t1
);
2124 case OPC_VR54XX_MULSU
:
2125 tcg_gen_helper_1_2(do_mulsu
, t0
, t0
, t1
);
2128 case OPC_VR54XX_MACC
:
2129 tcg_gen_helper_1_2(do_macc
, t0
, t0
, t1
);
2132 case OPC_VR54XX_MACCU
:
2133 tcg_gen_helper_1_2(do_maccu
, t0
, t0
, t1
);
2136 case OPC_VR54XX_MSAC
:
2137 tcg_gen_helper_1_2(do_msac
, t0
, t0
, t1
);
2140 case OPC_VR54XX_MSACU
:
2141 tcg_gen_helper_1_2(do_msacu
, t0
, t0
, t1
);
2144 case OPC_VR54XX_MULHI
:
2145 tcg_gen_helper_1_2(do_mulhi
, t0
, t0
, t1
);
2148 case OPC_VR54XX_MULHIU
:
2149 tcg_gen_helper_1_2(do_mulhiu
, t0
, t0
, t1
);
2152 case OPC_VR54XX_MULSHI
:
2153 tcg_gen_helper_1_2(do_mulshi
, t0
, t0
, t1
);
2156 case OPC_VR54XX_MULSHIU
:
2157 tcg_gen_helper_1_2(do_mulshiu
, t0
, t0
, t1
);
2160 case OPC_VR54XX_MACCHI
:
2161 tcg_gen_helper_1_2(do_macchi
, t0
, t0
, t1
);
2164 case OPC_VR54XX_MACCHIU
:
2165 tcg_gen_helper_1_2(do_macchiu
, t0
, t0
, t1
);
2168 case OPC_VR54XX_MSACHI
:
2169 tcg_gen_helper_1_2(do_msachi
, t0
, t0
, t1
);
2172 case OPC_VR54XX_MSACHIU
:
2173 tcg_gen_helper_1_2(do_msachiu
, t0
, t0
, t1
);
2177 MIPS_INVAL("mul vr54xx");
2178 generate_exception(ctx
, EXCP_RI
);
2181 gen_store_gpr(t0
, rd
);
2182 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
2189 static void gen_cl (DisasContext
*ctx
, uint32_t opc
,
2192 const char *opn
= "CLx";
2193 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
2200 gen_load_gpr(t0
, rs
);
2203 tcg_gen_helper_1_1(do_clo
, t0
, t0
);
2207 tcg_gen_helper_1_1(do_clz
, t0
, t0
);
2210 #if defined(TARGET_MIPS64)
2212 tcg_gen_helper_1_1(do_dclo
, t0
, t0
);
2216 tcg_gen_helper_1_1(do_dclz
, t0
, t0
);
2222 generate_exception(ctx
, EXCP_RI
);
2225 gen_store_gpr(t0
, rd
);
2226 MIPS_DEBUG("%s %s, %s", opn
, regnames
[rd
], regnames
[rs
]);
2233 static void gen_trap (DisasContext
*ctx
, uint32_t opc
,
2234 int rs
, int rt
, int16_t imm
)
2237 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
2238 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
2241 /* Load needed operands */
2249 /* Compare two registers */
2251 gen_load_gpr(t0
, rs
);
2252 gen_load_gpr(t1
, rt
);
2262 /* Compare register to immediate */
2263 if (rs
!= 0 || imm
!= 0) {
2264 gen_load_gpr(t0
, rs
);
2265 tcg_gen_movi_tl(t1
, (int32_t)imm
);
2272 case OPC_TEQ
: /* rs == rs */
2273 case OPC_TEQI
: /* r0 == 0 */
2274 case OPC_TGE
: /* rs >= rs */
2275 case OPC_TGEI
: /* r0 >= 0 */
2276 case OPC_TGEU
: /* rs >= rs unsigned */
2277 case OPC_TGEIU
: /* r0 >= 0 unsigned */
2279 tcg_gen_movi_tl(t0
, 1);
2281 case OPC_TLT
: /* rs < rs */
2282 case OPC_TLTI
: /* r0 < 0 */
2283 case OPC_TLTU
: /* rs < rs unsigned */
2284 case OPC_TLTIU
: /* r0 < 0 unsigned */
2285 case OPC_TNE
: /* rs != rs */
2286 case OPC_TNEI
: /* r0 != 0 */
2287 /* Never trap: treat as NOP. */
2291 generate_exception(ctx
, EXCP_RI
);
2322 generate_exception(ctx
, EXCP_RI
);
2326 save_cpu_state(ctx
, 1);
2328 int l1
= gen_new_label();
2330 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
2331 tcg_gen_helper_0_i(do_raise_exception
, EXCP_TRAP
);
2334 ctx
->bstate
= BS_STOP
;
2340 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
2342 TranslationBlock
*tb
;
2344 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
2347 tcg_gen_exit_tb((long)tb
+ n
);
2354 /* Branches (before delay slot) */
2355 static void gen_compute_branch (DisasContext
*ctx
, uint32_t opc
,
2356 int rs
, int rt
, int32_t offset
)
2358 target_ulong btgt
= -1;
2360 int bcond_compute
= 0;
2361 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
2362 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
2364 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
2365 #ifdef MIPS_DEBUG_DISAS
2366 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2368 "Branch in delay slot at PC 0x" TARGET_FMT_lx
"\n",
2372 generate_exception(ctx
, EXCP_RI
);
2376 /* Load needed operands */
2382 /* Compare two registers */
2384 gen_load_gpr(t0
, rs
);
2385 gen_load_gpr(t1
, rt
);
2388 btgt
= ctx
->pc
+ 4 + offset
;
2402 /* Compare to zero */
2404 gen_load_gpr(t0
, rs
);
2407 btgt
= ctx
->pc
+ 4 + offset
;
2411 /* Jump to immediate */
2412 btgt
= ((ctx
->pc
+ 4) & (int32_t)0xF0000000) | (uint32_t)offset
;
2416 /* Jump to register */
2417 if (offset
!= 0 && offset
!= 16) {
2418 /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
2419 others are reserved. */
2420 MIPS_INVAL("jump hint");
2421 generate_exception(ctx
, EXCP_RI
);
2424 gen_load_gpr(btarget
, rs
);
2427 MIPS_INVAL("branch/jump");
2428 generate_exception(ctx
, EXCP_RI
);
2431 if (bcond_compute
== 0) {
2432 /* No condition to be computed */
2434 case OPC_BEQ
: /* rx == rx */
2435 case OPC_BEQL
: /* rx == rx likely */
2436 case OPC_BGEZ
: /* 0 >= 0 */
2437 case OPC_BGEZL
: /* 0 >= 0 likely */
2438 case OPC_BLEZ
: /* 0 <= 0 */
2439 case OPC_BLEZL
: /* 0 <= 0 likely */
2441 ctx
->hflags
|= MIPS_HFLAG_B
;
2442 MIPS_DEBUG("balways");
2444 case OPC_BGEZAL
: /* 0 >= 0 */
2445 case OPC_BGEZALL
: /* 0 >= 0 likely */
2446 /* Always take and link */
2448 ctx
->hflags
|= MIPS_HFLAG_B
;
2449 MIPS_DEBUG("balways and link");
2451 case OPC_BNE
: /* rx != rx */
2452 case OPC_BGTZ
: /* 0 > 0 */
2453 case OPC_BLTZ
: /* 0 < 0 */
2455 MIPS_DEBUG("bnever (NOP)");
2457 case OPC_BLTZAL
: /* 0 < 0 */
2458 tcg_gen_movi_tl(t0
, ctx
->pc
+ 8);
2459 gen_store_gpr(t0
, 31);
2460 MIPS_DEBUG("bnever and link");
2462 case OPC_BLTZALL
: /* 0 < 0 likely */
2463 tcg_gen_movi_tl(t0
, ctx
->pc
+ 8);
2464 gen_store_gpr(t0
, 31);
2465 /* Skip the instruction in the delay slot */
2466 MIPS_DEBUG("bnever, link and skip");
2469 case OPC_BNEL
: /* rx != rx likely */
2470 case OPC_BGTZL
: /* 0 > 0 likely */
2471 case OPC_BLTZL
: /* 0 < 0 likely */
2472 /* Skip the instruction in the delay slot */
2473 MIPS_DEBUG("bnever and skip");
2477 ctx
->hflags
|= MIPS_HFLAG_B
;
2478 MIPS_DEBUG("j " TARGET_FMT_lx
, btgt
);
2482 ctx
->hflags
|= MIPS_HFLAG_B
;
2483 MIPS_DEBUG("jal " TARGET_FMT_lx
, btgt
);
2486 ctx
->hflags
|= MIPS_HFLAG_BR
;
2487 MIPS_DEBUG("jr %s", regnames
[rs
]);
2491 ctx
->hflags
|= MIPS_HFLAG_BR
;
2492 MIPS_DEBUG("jalr %s, %s", regnames
[rt
], regnames
[rs
]);
2495 MIPS_INVAL("branch/jump");
2496 generate_exception(ctx
, EXCP_RI
);
2503 MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx
,
2504 regnames
[rs
], regnames
[rt
], btgt
);
2508 MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx
,
2509 regnames
[rs
], regnames
[rt
], btgt
);
2513 MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx
,
2514 regnames
[rs
], regnames
[rt
], btgt
);
2518 MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx
,
2519 regnames
[rs
], regnames
[rt
], btgt
);
2523 MIPS_DEBUG("bgez %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2527 MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2531 MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2537 MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2541 MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2545 MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2549 MIPS_DEBUG("blez %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2553 MIPS_DEBUG("blezl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2557 MIPS_DEBUG("bltz %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2561 MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2566 MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2568 ctx
->hflags
|= MIPS_HFLAG_BC
;
2569 tcg_gen_trunc_tl_i32(bcond
, t0
);
2574 MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2576 ctx
->hflags
|= MIPS_HFLAG_BL
;
2577 tcg_gen_trunc_tl_i32(bcond
, t0
);
2580 MIPS_INVAL("conditional branch/jump");
2581 generate_exception(ctx
, EXCP_RI
);
2585 MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx
,
2586 blink
, ctx
->hflags
, btgt
);
2588 ctx
->btarget
= btgt
;
2590 tcg_gen_movi_tl(t0
, ctx
->pc
+ 8);
2591 gen_store_gpr(t0
, blink
);
2599 /* special3 bitfield operations */
2600 static void gen_bitops (DisasContext
*ctx
, uint32_t opc
, int rt
,
2601 int rs
, int lsb
, int msb
)
2603 TCGv t0
= tcg_temp_new(TCG_TYPE_TL
);
2604 TCGv t1
= tcg_temp_new(TCG_TYPE_TL
);
2607 gen_load_gpr(t1
, rs
);
2612 tcg_gen_shri_tl(t0
, t1
, lsb
);
2614 tcg_gen_andi_tl(t0
, t0
, (1 << (msb
+ 1)) - 1);
2616 tcg_gen_ext32s_tl(t0
, t0
);
2619 #if defined(TARGET_MIPS64)
2621 tcg_gen_shri_tl(t0
, t1
, lsb
);
2623 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1 + 32)) - 1);
2627 tcg_gen_shri_tl(t0
, t1
, lsb
+ 32);
2628 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1)) - 1);
2631 tcg_gen_shri_tl(t0
, t1
, lsb
);
2632 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1)) - 1);
2638 mask
= ((msb
- lsb
+ 1 < 32) ? ((1 << (msb
- lsb
+ 1)) - 1) : ~0) << lsb
;
2639 gen_load_gpr(t0
, rt
);
2640 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2641 tcg_gen_shli_tl(t1
, t1
, lsb
);
2642 tcg_gen_andi_tl(t1
, t1
, mask
);
2643 tcg_gen_or_tl(t0
, t0
, t1
);
2644 tcg_gen_ext32s_tl(t0
, t0
);
2646 #if defined(TARGET_MIPS64)
2650 mask
= ((msb
- lsb
+ 1 + 32 < 64) ? ((1ULL << (msb
- lsb
+ 1 + 32)) - 1) : ~0ULL) << lsb
;
2651 gen_load_gpr(t0
, rt
);
2652 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2653 tcg_gen_shli_tl(t1
, t1
, lsb
);
2654 tcg_gen_andi_tl(t1
, t1
, mask
);
2655 tcg_gen_or_tl(t0
, t0
, t1
);
2660 mask
= ((1ULL << (msb
- lsb
+ 1)) - 1) << lsb
;
2661 gen_load_gpr(t0
, rt
);
2662 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2663 tcg_gen_shli_tl(t1
, t1
, lsb
+ 32);
2664 tcg_gen_andi_tl(t1
, t1
, mask
);
2665 tcg_gen_or_tl(t0
, t0
, t1
);
2670 gen_load_gpr(t0
, rt
);
2671 mask
= ((1ULL << (msb
- lsb
+ 1)) - 1) << lsb
;
2672 gen_load_gpr(t0
, rt
);
2673 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2674 tcg_gen_shli_tl(t1
, t1
, lsb
);
2675 tcg_gen_andi_tl(t1
, t1
, mask
);
2676 tcg_gen_or_tl(t0
, t0
, t1
);
2681 MIPS_INVAL("bitops");
2682 generate_exception(ctx
, EXCP_RI
);
2687 gen_store_gpr(t0
, rt
);
2692 static void gen_bshfl (DisasContext
*ctx
, uint32_t op2
, int rt
, int rd
)
2694 TCGv t0
= tcg_temp_new(TCG_TYPE_TL
);
2695 TCGv t1
= tcg_temp_new(TCG_TYPE_TL
);
2697 gen_load_gpr(t1
, rt
);
2700 tcg_gen_shri_tl(t0
, t1
, 8);
2701 tcg_gen_andi_tl(t0
, t0
, 0x00FF00FF);
2702 tcg_gen_shli_tl(t1
, t1
, 8);
2703 tcg_gen_andi_tl(t1
, t1
, ~0x00FF00FF);
2704 tcg_gen_or_tl(t0
, t0
, t1
);
2705 tcg_gen_ext32s_tl(t0
, t0
);
2708 tcg_gen_ext8s_tl(t0
, t1
);
2711 tcg_gen_ext16s_tl(t0
, t1
);
2713 #if defined(TARGET_MIPS64)
2715 gen_load_gpr(t1
, rt
);
2716 tcg_gen_shri_tl(t0
, t1
, 8);
2717 tcg_gen_andi_tl(t0
, t0
, 0x00FF00FF00FF00FFULL
);
2718 tcg_gen_shli_tl(t1
, t1
, 8);
2719 tcg_gen_andi_tl(t1
, t1
, ~0x00FF00FF00FF00FFULL
);
2720 tcg_gen_or_tl(t0
, t0
, t1
);
2723 gen_load_gpr(t1
, rt
);
2724 tcg_gen_shri_tl(t0
, t1
, 16);
2725 tcg_gen_andi_tl(t0
, t0
, 0x0000FFFF0000FFFFULL
);
2726 tcg_gen_shli_tl(t1
, t1
, 16);
2727 tcg_gen_andi_tl(t1
, t1
, ~0x0000FFFF0000FFFFULL
);
2728 tcg_gen_or_tl(t1
, t0
, t1
);
2729 tcg_gen_shri_tl(t0
, t1
, 32);
2730 tcg_gen_shli_tl(t1
, t1
, 32);
2731 tcg_gen_or_tl(t0
, t0
, t1
);
2735 MIPS_INVAL("bsfhl");
2736 generate_exception(ctx
, EXCP_RI
);
2741 gen_store_gpr(t0
, rd
);
2746 #ifndef CONFIG_USER_ONLY
2747 /* CP0 (MMU and control) */
2748 static inline void gen_mfc0_load32 (TCGv t
, target_ulong off
)
2750 TCGv r_tmp
= tcg_temp_new(TCG_TYPE_I32
);
2752 tcg_gen_ld_i32(r_tmp
, cpu_env
, off
);
2753 tcg_gen_ext_i32_tl(t
, r_tmp
);
2754 tcg_temp_free(r_tmp
);
2757 static inline void gen_mfc0_load64 (TCGv t
, target_ulong off
)
2759 tcg_gen_ld_tl(t
, cpu_env
, off
);
2760 tcg_gen_ext32s_tl(t
, t
);
2763 static inline void gen_mtc0_store32 (TCGv t
, target_ulong off
)
2765 TCGv r_tmp
= tcg_temp_new(TCG_TYPE_I32
);
2767 tcg_gen_trunc_tl_i32(r_tmp
, t
);
2768 tcg_gen_st_i32(r_tmp
, cpu_env
, off
);
2769 tcg_temp_free(r_tmp
);
2772 static inline void gen_mtc0_store64 (TCGv t
, target_ulong off
)
2774 tcg_gen_ext32s_tl(t
, t
);
2775 tcg_gen_st_tl(t
, cpu_env
, off
);
2778 static void gen_mfc0 (CPUState
*env
, DisasContext
*ctx
, TCGv t0
, int reg
, int sel
)
2780 const char *rn
= "invalid";
2783 check_insn(env
, ctx
, ISA_MIPS32
);
2789 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Index
));
2793 check_insn(env
, ctx
, ASE_MT
);
2794 tcg_gen_helper_1_0(do_mfc0_mvpcontrol
, t0
);
2798 check_insn(env
, ctx
, ASE_MT
);
2799 tcg_gen_helper_1_0(do_mfc0_mvpconf0
, t0
);
2803 check_insn(env
, ctx
, ASE_MT
);
2804 tcg_gen_helper_1_0(do_mfc0_mvpconf1
, t0
);
2814 tcg_gen_helper_1_0(do_mfc0_random
, t0
);
2818 check_insn(env
, ctx
, ASE_MT
);
2819 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEControl
));
2823 check_insn(env
, ctx
, ASE_MT
);
2824 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEConf0
));
2828 check_insn(env
, ctx
, ASE_MT
);
2829 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEConf1
));
2833 check_insn(env
, ctx
, ASE_MT
);
2834 gen_mfc0_load64(t0
, offsetof(CPUState
, CP0_YQMask
));
2838 check_insn(env
, ctx
, ASE_MT
);
2839 gen_mfc0_load64(t0
, offsetof(CPUState
, CP0_VPESchedule
));
2843 check_insn(env
, ctx
, ASE_MT
);
2844 gen_mfc0_load64(t0
, offsetof(CPUState
, CP0_VPEScheFBack
));
2845 rn
= "VPEScheFBack";
2848 check_insn(env
, ctx
, ASE_MT
);
2849 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEOpt
));
2859 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryLo0
));
2860 tcg_gen_ext32s_tl(t0
, t0
);
2864 check_insn(env
, ctx
, ASE_MT
);
2865 tcg_gen_helper_1_0(do_mfc0_tcstatus
, t0
);
2869 check_insn(env
, ctx
, ASE_MT
);
2870 tcg_gen_helper_1_0(do_mfc0_tcbind
, t0
);
2874 check_insn(env
, ctx
, ASE_MT
);
2875 tcg_gen_helper_1_0(do_mfc0_tcrestart
, t0
);
2879 check_insn(env
, ctx
, ASE_MT
);
2880 tcg_gen_helper_1_0(do_mfc0_tchalt
, t0
);
2884 check_insn(env
, ctx
, ASE_MT
);
2885 tcg_gen_helper_1_0(do_mfc0_tccontext
, t0
);
2889 check_insn(env
, ctx
, ASE_MT
);
2890 tcg_gen_helper_1_0(do_mfc0_tcschedule
, t0
);
2894 check_insn(env
, ctx
, ASE_MT
);
2895 tcg_gen_helper_1_0(do_mfc0_tcschefback
, t0
);
2905 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryLo1
));
2906 tcg_gen_ext32s_tl(t0
, t0
);
2916 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_Context
));
2917 tcg_gen_ext32s_tl(t0
, t0
);
2921 // tcg_gen_helper_1_0(do_mfc0_contextconfig, t0); /* SmartMIPS ASE */
2922 rn
= "ContextConfig";
2931 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PageMask
));
2935 check_insn(env
, ctx
, ISA_MIPS32R2
);
2936 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PageGrain
));
2946 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Wired
));
2950 check_insn(env
, ctx
, ISA_MIPS32R2
);
2951 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf0
));
2955 check_insn(env
, ctx
, ISA_MIPS32R2
);
2956 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf1
));
2960 check_insn(env
, ctx
, ISA_MIPS32R2
);
2961 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf2
));
2965 check_insn(env
, ctx
, ISA_MIPS32R2
);
2966 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf3
));
2970 check_insn(env
, ctx
, ISA_MIPS32R2
);
2971 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf4
));
2981 check_insn(env
, ctx
, ISA_MIPS32R2
);
2982 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_HWREna
));
2992 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_BadVAddr
));
2993 tcg_gen_ext32s_tl(t0
, t0
);
3003 /* Mark as an IO operation because we read the time. */
3006 tcg_gen_helper_1_0(do_mfc0_count
, t0
);
3009 ctx
->bstate
= BS_STOP
;
3013 /* 6,7 are implementation dependent */
3021 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryHi
));
3022 tcg_gen_ext32s_tl(t0
, t0
);
3032 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Compare
));
3035 /* 6,7 are implementation dependent */
3043 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Status
));
3047 check_insn(env
, ctx
, ISA_MIPS32R2
);
3048 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_IntCtl
));
3052 check_insn(env
, ctx
, ISA_MIPS32R2
);
3053 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSCtl
));
3057 check_insn(env
, ctx
, ISA_MIPS32R2
);
3058 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSMap
));
3068 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Cause
));
3078 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
3079 tcg_gen_ext32s_tl(t0
, t0
);
3089 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PRid
));
3093 check_insn(env
, ctx
, ISA_MIPS32R2
);
3094 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_EBase
));
3104 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config0
));
3108 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config1
));
3112 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config2
));
3116 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config3
));
3119 /* 4,5 are reserved */
3120 /* 6,7 are implementation dependent */
3122 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config6
));
3126 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config7
));
3136 tcg_gen_helper_1_0(do_mfc0_lladdr
, t0
);
3146 tcg_gen_helper_1_i(do_mfc0_watchlo
, t0
, sel
);
3156 tcg_gen_helper_1_i(do_mfc0_watchhi
, t0
, sel
);
3166 #if defined(TARGET_MIPS64)
3167 check_insn(env
, ctx
, ISA_MIPS3
);
3168 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_XContext
));
3169 tcg_gen_ext32s_tl(t0
, t0
);
3178 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3181 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Framemask
));
3190 rn
= "'Diagnostic"; /* implementation dependent */
3195 tcg_gen_helper_1_0(do_mfc0_debug
, t0
); /* EJTAG support */
3199 // tcg_gen_helper_1_0(do_mfc0_tracecontrol, t0); /* PDtrace support */
3200 rn
= "TraceControl";
3203 // tcg_gen_helper_1_0(do_mfc0_tracecontrol2, t0); /* PDtrace support */
3204 rn
= "TraceControl2";
3207 // tcg_gen_helper_1_0(do_mfc0_usertracedata, t0); /* PDtrace support */
3208 rn
= "UserTraceData";
3211 // tcg_gen_helper_1_0(do_mfc0_tracebpc, t0); /* PDtrace support */
3222 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
3223 tcg_gen_ext32s_tl(t0
, t0
);
3233 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Performance0
));
3234 rn
= "Performance0";
3237 // tcg_gen_helper_1_0(do_mfc0_performance1, t0);
3238 rn
= "Performance1";
3241 // tcg_gen_helper_1_0(do_mfc0_performance2, t0);
3242 rn
= "Performance2";
3245 // tcg_gen_helper_1_0(do_mfc0_performance3, t0);
3246 rn
= "Performance3";
3249 // tcg_gen_helper_1_0(do_mfc0_performance4, t0);
3250 rn
= "Performance4";
3253 // tcg_gen_helper_1_0(do_mfc0_performance5, t0);
3254 rn
= "Performance5";
3257 // tcg_gen_helper_1_0(do_mfc0_performance6, t0);
3258 rn
= "Performance6";
3261 // tcg_gen_helper_1_0(do_mfc0_performance7, t0);
3262 rn
= "Performance7";
3287 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_TagLo
));
3294 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DataLo
));
3307 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_TagHi
));
3314 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DataHi
));
3324 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
3325 tcg_gen_ext32s_tl(t0
, t0
);
3336 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DESAVE
));
3346 #if defined MIPS_DEBUG_DISAS
3347 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3348 fprintf(logfile
, "mfc0 %s (reg %d sel %d)\n",
3355 #if defined MIPS_DEBUG_DISAS
3356 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3357 fprintf(logfile
, "mfc0 %s (reg %d sel %d)\n",
3361 generate_exception(ctx
, EXCP_RI
);
3364 static void gen_mtc0 (CPUState
*env
, DisasContext
*ctx
, TCGv t0
, int reg
, int sel
)
3366 const char *rn
= "invalid";
3369 check_insn(env
, ctx
, ISA_MIPS32
);
3378 tcg_gen_helper_0_1(do_mtc0_index
, t0
);
3382 check_insn(env
, ctx
, ASE_MT
);
3383 tcg_gen_helper_0_1(do_mtc0_mvpcontrol
, t0
);
3387 check_insn(env
, ctx
, ASE_MT
);
3392 check_insn(env
, ctx
, ASE_MT
);
3407 check_insn(env
, ctx
, ASE_MT
);
3408 tcg_gen_helper_0_1(do_mtc0_vpecontrol
, t0
);
3412 check_insn(env
, ctx
, ASE_MT
);
3413 tcg_gen_helper_0_1(do_mtc0_vpeconf0
, t0
);
3417 check_insn(env
, ctx
, ASE_MT
);
3418 tcg_gen_helper_0_1(do_mtc0_vpeconf1
, t0
);
3422 check_insn(env
, ctx
, ASE_MT
);
3423 tcg_gen_helper_0_1(do_mtc0_yqmask
, t0
);
3427 check_insn(env
, ctx
, ASE_MT
);
3428 gen_mtc0_store64(t0
, offsetof(CPUState
, CP0_VPESchedule
));
3432 check_insn(env
, ctx
, ASE_MT
);
3433 gen_mtc0_store64(t0
, offsetof(CPUState
, CP0_VPEScheFBack
));
3434 rn
= "VPEScheFBack";
3437 check_insn(env
, ctx
, ASE_MT
);
3438 tcg_gen_helper_0_1(do_mtc0_vpeopt
, t0
);
3448 tcg_gen_helper_0_1(do_mtc0_entrylo0
, t0
);
3452 check_insn(env
, ctx
, ASE_MT
);
3453 tcg_gen_helper_0_1(do_mtc0_tcstatus
, t0
);
3457 check_insn(env
, ctx
, ASE_MT
);
3458 tcg_gen_helper_0_1(do_mtc0_tcbind
, t0
);
3462 check_insn(env
, ctx
, ASE_MT
);
3463 tcg_gen_helper_0_1(do_mtc0_tcrestart
, t0
);
3467 check_insn(env
, ctx
, ASE_MT
);
3468 tcg_gen_helper_0_1(do_mtc0_tchalt
, t0
);
3472 check_insn(env
, ctx
, ASE_MT
);
3473 tcg_gen_helper_0_1(do_mtc0_tccontext
, t0
);
3477 check_insn(env
, ctx
, ASE_MT
);
3478 tcg_gen_helper_0_1(do_mtc0_tcschedule
, t0
);
3482 check_insn(env
, ctx
, ASE_MT
);
3483 tcg_gen_helper_0_1(do_mtc0_tcschefback
, t0
);
3493 tcg_gen_helper_0_1(do_mtc0_entrylo1
, t0
);
3503 tcg_gen_helper_0_1(do_mtc0_context
, t0
);
3507 // tcg_gen_helper_0_1(do_mtc0_contextconfig, t0); /* SmartMIPS ASE */
3508 rn
= "ContextConfig";
3517 tcg_gen_helper_0_1(do_mtc0_pagemask
, t0
);
3521 check_insn(env
, ctx
, ISA_MIPS32R2
);
3522 tcg_gen_helper_0_1(do_mtc0_pagegrain
, t0
);
3532 tcg_gen_helper_0_1(do_mtc0_wired
, t0
);
3536 check_insn(env
, ctx
, ISA_MIPS32R2
);
3537 tcg_gen_helper_0_1(do_mtc0_srsconf0
, t0
);
3541 check_insn(env
, ctx
, ISA_MIPS32R2
);
3542 tcg_gen_helper_0_1(do_mtc0_srsconf1
, t0
);
3546 check_insn(env
, ctx
, ISA_MIPS32R2
);
3547 tcg_gen_helper_0_1(do_mtc0_srsconf2
, t0
);
3551 check_insn(env
, ctx
, ISA_MIPS32R2
);
3552 tcg_gen_helper_0_1(do_mtc0_srsconf3
, t0
);
3556 check_insn(env
, ctx
, ISA_MIPS32R2
);
3557 tcg_gen_helper_0_1(do_mtc0_srsconf4
, t0
);
3567 check_insn(env
, ctx
, ISA_MIPS32R2
);
3568 tcg_gen_helper_0_1(do_mtc0_hwrena
, t0
);
3582 tcg_gen_helper_0_1(do_mtc0_count
, t0
);
3585 /* 6,7 are implementation dependent */
3589 /* Stop translation as we may have switched the execution mode */
3590 ctx
->bstate
= BS_STOP
;
3595 tcg_gen_helper_0_1(do_mtc0_entryhi
, t0
);
3605 tcg_gen_helper_0_1(do_mtc0_compare
, t0
);
3608 /* 6,7 are implementation dependent */
3612 /* Stop translation as we may have switched the execution mode */
3613 ctx
->bstate
= BS_STOP
;
3618 tcg_gen_helper_0_1(do_mtc0_status
, t0
);
3619 /* BS_STOP isn't good enough here, hflags may have changed. */
3620 gen_save_pc(ctx
->pc
+ 4);
3621 ctx
->bstate
= BS_EXCP
;
3625 check_insn(env
, ctx
, ISA_MIPS32R2
);
3626 tcg_gen_helper_0_1(do_mtc0_intctl
, t0
);
3627 /* Stop translation as we may have switched the execution mode */
3628 ctx
->bstate
= BS_STOP
;
3632 check_insn(env
, ctx
, ISA_MIPS32R2
);
3633 tcg_gen_helper_0_1(do_mtc0_srsctl
, t0
);
3634 /* Stop translation as we may have switched the execution mode */
3635 ctx
->bstate
= BS_STOP
;
3639 check_insn(env
, ctx
, ISA_MIPS32R2
);
3640 gen_mtc0_store32(t0
, offsetof(CPUState
, CP0_SRSMap
));
3641 /* Stop translation as we may have switched the execution mode */
3642 ctx
->bstate
= BS_STOP
;
3652 tcg_gen_helper_0_1(do_mtc0_cause
, t0
);
3658 /* Stop translation as we may have switched the execution mode */
3659 ctx
->bstate
= BS_STOP
;
3664 gen_mtc0_store64(t0
, offsetof(CPUState
, CP0_EPC
));
3678 check_insn(env
, ctx
, ISA_MIPS32R2
);
3679 tcg_gen_helper_0_1(do_mtc0_ebase
, t0
);
3689 tcg_gen_helper_0_1(do_mtc0_config0
, t0
);
3691 /* Stop translation as we may have switched the execution mode */
3692 ctx
->bstate
= BS_STOP
;
3695 /* ignored, read only */
3699 tcg_gen_helper_0_1(do_mtc0_config2
, t0
);
3701 /* Stop translation as we may have switched the execution mode */
3702 ctx
->bstate
= BS_STOP
;
3705 /* ignored, read only */
3708 /* 4,5 are reserved */
3709 /* 6,7 are implementation dependent */
3719 rn
= "Invalid config selector";
3736 tcg_gen_helper_0_1i(do_mtc0_watchlo
, t0
, sel
);
3746 tcg_gen_helper_0_1i(do_mtc0_watchhi
, t0
, sel
);
3756 #if defined(TARGET_MIPS64)
3757 check_insn(env
, ctx
, ISA_MIPS3
);
3758 tcg_gen_helper_0_1(do_mtc0_xcontext
, t0
);
3767 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3770 tcg_gen_helper_0_1(do_mtc0_framemask
, t0
);
3779 rn
= "Diagnostic"; /* implementation dependent */
3784 tcg_gen_helper_0_1(do_mtc0_debug
, t0
); /* EJTAG support */
3785 /* BS_STOP isn't good enough here, hflags may have changed. */
3786 gen_save_pc(ctx
->pc
+ 4);
3787 ctx
->bstate
= BS_EXCP
;
3791 // tcg_gen_helper_0_1(do_mtc0_tracecontrol, t0); /* PDtrace support */
3792 rn
= "TraceControl";
3793 /* Stop translation as we may have switched the execution mode */
3794 ctx
->bstate
= BS_STOP
;
3797 // tcg_gen_helper_0_1(do_mtc0_tracecontrol2, t0); /* PDtrace support */
3798 rn
= "TraceControl2";
3799 /* Stop translation as we may have switched the execution mode */
3800 ctx
->bstate
= BS_STOP
;
3803 /* Stop translation as we may have switched the execution mode */
3804 ctx
->bstate
= BS_STOP
;
3805 // tcg_gen_helper_0_1(do_mtc0_usertracedata, t0); /* PDtrace support */
3806 rn
= "UserTraceData";
3807 /* Stop translation as we may have switched the execution mode */
3808 ctx
->bstate
= BS_STOP
;
3811 // tcg_gen_helper_0_1(do_mtc0_tracebpc, t0); /* PDtrace support */
3812 /* Stop translation as we may have switched the execution mode */
3813 ctx
->bstate
= BS_STOP
;
3824 gen_mtc0_store64(t0
, offsetof(CPUState
, CP0_DEPC
));
3834 tcg_gen_helper_0_1(do_mtc0_performance0
, t0
);
3835 rn
= "Performance0";
3838 // tcg_gen_helper_0_1(do_mtc0_performance1, t0);
3839 rn
= "Performance1";
3842 // tcg_gen_helper_0_1(do_mtc0_performance2, t0);
3843 rn
= "Performance2";
3846 // tcg_gen_helper_0_1(do_mtc0_performance3, t0);
3847 rn
= "Performance3";
3850 // tcg_gen_helper_0_1(do_mtc0_performance4, t0);
3851 rn
= "Performance4";
3854 // tcg_gen_helper_0_1(do_mtc0_performance5, t0);
3855 rn
= "Performance5";
3858 // tcg_gen_helper_0_1(do_mtc0_performance6, t0);
3859 rn
= "Performance6";
3862 // tcg_gen_helper_0_1(do_mtc0_performance7, t0);
3863 rn
= "Performance7";
3889 tcg_gen_helper_0_1(do_mtc0_taglo
, t0
);
3896 tcg_gen_helper_0_1(do_mtc0_datalo
, t0
);
3909 tcg_gen_helper_0_1(do_mtc0_taghi
, t0
);
3916 tcg_gen_helper_0_1(do_mtc0_datahi
, t0
);
3927 gen_mtc0_store64(t0
, offsetof(CPUState
, CP0_ErrorEPC
));
3938 gen_mtc0_store32(t0
, offsetof(CPUState
, CP0_DESAVE
));
3944 /* Stop translation as we may have switched the execution mode */
3945 ctx
->bstate
= BS_STOP
;
3950 #if defined MIPS_DEBUG_DISAS
3951 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3952 fprintf(logfile
, "mtc0 %s (reg %d sel %d)\n",
3956 /* For simplicity assume that all writes can cause interrupts. */
3959 ctx
->bstate
= BS_STOP
;
3964 #if defined MIPS_DEBUG_DISAS
3965 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3966 fprintf(logfile
, "mtc0 %s (reg %d sel %d)\n",
3970 generate_exception(ctx
, EXCP_RI
);
3973 #if defined(TARGET_MIPS64)
3974 static void gen_dmfc0 (CPUState
*env
, DisasContext
*ctx
, TCGv t0
, int reg
, int sel
)
3976 const char *rn
= "invalid";
3979 check_insn(env
, ctx
, ISA_MIPS64
);
3985 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Index
));
3989 check_insn(env
, ctx
, ASE_MT
);
3990 tcg_gen_helper_1_0(do_mfc0_mvpcontrol
, t0
);
3994 check_insn(env
, ctx
, ASE_MT
);
3995 tcg_gen_helper_1_0(do_mfc0_mvpconf0
, t0
);
3999 check_insn(env
, ctx
, ASE_MT
);
4000 tcg_gen_helper_1_0(do_mfc0_mvpconf1
, t0
);
4010 tcg_gen_helper_1_0(do_mfc0_random
, t0
);
4014 check_insn(env
, ctx
, ASE_MT
);
4015 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEControl
));
4019 check_insn(env
, ctx
, ASE_MT
);
4020 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEConf0
));
4024 check_insn(env
, ctx
, ASE_MT
);
4025 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEConf1
));
4029 check_insn(env
, ctx
, ASE_MT
);
4030 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_YQMask
));
4034 check_insn(env
, ctx
, ASE_MT
);
4035 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_VPESchedule
));
4039 check_insn(env
, ctx
, ASE_MT
);
4040 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_VPEScheFBack
));
4041 rn
= "VPEScheFBack";
4044 check_insn(env
, ctx
, ASE_MT
);
4045 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEOpt
));
4055 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryLo0
));
4059 check_insn(env
, ctx
, ASE_MT
);
4060 tcg_gen_helper_1_0(do_mfc0_tcstatus
, t0
);
4064 check_insn(env
, ctx
, ASE_MT
);
4065 tcg_gen_helper_1_0(do_mfc0_tcbind
, t0
);
4069 check_insn(env
, ctx
, ASE_MT
);
4070 tcg_gen_helper_1_0(do_dmfc0_tcrestart
, t0
);
4074 check_insn(env
, ctx
, ASE_MT
);
4075 tcg_gen_helper_1_0(do_dmfc0_tchalt
, t0
);
4079 check_insn(env
, ctx
, ASE_MT
);
4080 tcg_gen_helper_1_0(do_dmfc0_tccontext
, t0
);
4084 check_insn(env
, ctx
, ASE_MT
);
4085 tcg_gen_helper_1_0(do_dmfc0_tcschedule
, t0
);
4089 check_insn(env
, ctx
, ASE_MT
);
4090 tcg_gen_helper_1_0(do_dmfc0_tcschefback
, t0
);
4100 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryLo1
));
4110 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_Context
));
4114 // tcg_gen_helper_1_0(do_dmfc0_contextconfig, t0); /* SmartMIPS ASE */
4115 rn
= "ContextConfig";
4124 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PageMask
));
4128 check_insn(env
, ctx
, ISA_MIPS32R2
);
4129 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PageGrain
));
4139 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Wired
));
4143 check_insn(env
, ctx
, ISA_MIPS32R2
);
4144 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf0
));
4148 check_insn(env
, ctx
, ISA_MIPS32R2
);
4149 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf1
));
4153 check_insn(env
, ctx
, ISA_MIPS32R2
);
4154 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf2
));
4158 check_insn(env
, ctx
, ISA_MIPS32R2
);
4159 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf3
));
4163 check_insn(env
, ctx
, ISA_MIPS32R2
);
4164 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf4
));
4174 check_insn(env
, ctx
, ISA_MIPS32R2
);
4175 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_HWREna
));
4185 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_BadVAddr
));
4195 /* Mark as an IO operation because we read the time. */
4198 tcg_gen_helper_1_0(do_mfc0_count
, t0
);
4201 ctx
->bstate
= BS_STOP
;
4205 /* 6,7 are implementation dependent */
4213 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryHi
));
4223 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Compare
));
4226 /* 6,7 are implementation dependent */
4234 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Status
));
4238 check_insn(env
, ctx
, ISA_MIPS32R2
);
4239 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_IntCtl
));
4243 check_insn(env
, ctx
, ISA_MIPS32R2
);
4244 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSCtl
));
4248 check_insn(env
, ctx
, ISA_MIPS32R2
);
4249 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSMap
));
4259 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Cause
));
4269 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
4279 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PRid
));
4283 check_insn(env
, ctx
, ISA_MIPS32R2
);
4284 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_EBase
));
4294 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config0
));
4298 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config1
));
4302 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config2
));
4306 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config3
));
4309 /* 6,7 are implementation dependent */
4311 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config6
));
4315 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config7
));
4325 tcg_gen_helper_1_0(do_dmfc0_lladdr
, t0
);
4335 tcg_gen_helper_1_i(do_dmfc0_watchlo
, t0
, sel
);
4345 tcg_gen_helper_1_i(do_mfc0_watchhi
, t0
, sel
);
4355 check_insn(env
, ctx
, ISA_MIPS3
);
4356 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_XContext
));
4364 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4367 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Framemask
));
4376 rn
= "'Diagnostic"; /* implementation dependent */
4381 tcg_gen_helper_1_0(do_mfc0_debug
, t0
); /* EJTAG support */
4385 // tcg_gen_helper_1_0(do_dmfc0_tracecontrol, t0); /* PDtrace support */
4386 rn
= "TraceControl";
4389 // tcg_gen_helper_1_0(do_dmfc0_tracecontrol2, t0); /* PDtrace support */
4390 rn
= "TraceControl2";
4393 // tcg_gen_helper_1_0(do_dmfc0_usertracedata, t0); /* PDtrace support */
4394 rn
= "UserTraceData";
4397 // tcg_gen_helper_1_0(do_dmfc0_tracebpc, t0); /* PDtrace support */
4408 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
4418 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Performance0
));
4419 rn
= "Performance0";
4422 // tcg_gen_helper_1_0(do_dmfc0_performance1, t0);
4423 rn
= "Performance1";
4426 // tcg_gen_helper_1_0(do_dmfc0_performance2, t0);
4427 rn
= "Performance2";
4430 // tcg_gen_helper_1_0(do_dmfc0_performance3, t0);
4431 rn
= "Performance3";
4434 // tcg_gen_helper_1_0(do_dmfc0_performance4, t0);
4435 rn
= "Performance4";
4438 // tcg_gen_helper_1_0(do_dmfc0_performance5, t0);
4439 rn
= "Performance5";
4442 // tcg_gen_helper_1_0(do_dmfc0_performance6, t0);
4443 rn
= "Performance6";
4446 // tcg_gen_helper_1_0(do_dmfc0_performance7, t0);
4447 rn
= "Performance7";
4472 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_TagLo
));
4479 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DataLo
));
4492 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_TagHi
));
4499 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DataHi
));
4509 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
4520 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DESAVE
));
4530 #if defined MIPS_DEBUG_DISAS
4531 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4532 fprintf(logfile
, "dmfc0 %s (reg %d sel %d)\n",
4539 #if defined MIPS_DEBUG_DISAS
4540 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4541 fprintf(logfile
, "dmfc0 %s (reg %d sel %d)\n",
4545 generate_exception(ctx
, EXCP_RI
);
4548 static void gen_dmtc0 (CPUState
*env
, DisasContext
*ctx
, TCGv t0
, int reg
, int sel
)
4550 const char *rn
= "invalid";
4553 check_insn(env
, ctx
, ISA_MIPS64
);
4562 tcg_gen_helper_0_1(do_mtc0_index
, t0
);
4566 check_insn(env
, ctx
, ASE_MT
);
4567 tcg_gen_helper_0_1(do_mtc0_mvpcontrol
, t0
);
4571 check_insn(env
, ctx
, ASE_MT
);
4576 check_insn(env
, ctx
, ASE_MT
);
4591 check_insn(env
, ctx
, ASE_MT
);
4592 tcg_gen_helper_0_1(do_mtc0_vpecontrol
, t0
);
4596 check_insn(env
, ctx
, ASE_MT
);
4597 tcg_gen_helper_0_1(do_mtc0_vpeconf0
, t0
);
4601 check_insn(env
, ctx
, ASE_MT
);
4602 tcg_gen_helper_0_1(do_mtc0_vpeconf1
, t0
);
4606 check_insn(env
, ctx
, ASE_MT
);
4607 tcg_gen_helper_0_1(do_mtc0_yqmask
, t0
);
4611 check_insn(env
, ctx
, ASE_MT
);
4612 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_VPESchedule
));
4616 check_insn(env
, ctx
, ASE_MT
);
4617 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_VPEScheFBack
));
4618 rn
= "VPEScheFBack";
4621 check_insn(env
, ctx
, ASE_MT
);
4622 tcg_gen_helper_0_1(do_mtc0_vpeopt
, t0
);
4632 tcg_gen_helper_0_1(do_mtc0_entrylo0
, t0
);
4636 check_insn(env
, ctx
, ASE_MT
);
4637 tcg_gen_helper_0_1(do_mtc0_tcstatus
, t0
);
4641 check_insn(env
, ctx
, ASE_MT
);
4642 tcg_gen_helper_0_1(do_mtc0_tcbind
, t0
);
4646 check_insn(env
, ctx
, ASE_MT
);
4647 tcg_gen_helper_0_1(do_mtc0_tcrestart
, t0
);
4651 check_insn(env
, ctx
, ASE_MT
);
4652 tcg_gen_helper_0_1(do_mtc0_tchalt
, t0
);
4656 check_insn(env
, ctx
, ASE_MT
);
4657 tcg_gen_helper_0_1(do_mtc0_tccontext
, t0
);
4661 check_insn(env
, ctx
, ASE_MT
);
4662 tcg_gen_helper_0_1(do_mtc0_tcschedule
, t0
);
4666 check_insn(env
, ctx
, ASE_MT
);
4667 tcg_gen_helper_0_1(do_mtc0_tcschefback
, t0
);
4677 tcg_gen_helper_0_1(do_mtc0_entrylo1
, t0
);
4687 tcg_gen_helper_0_1(do_mtc0_context
, t0
);
4691 // tcg_gen_helper_0_1(do_mtc0_contextconfig, t0); /* SmartMIPS ASE */
4692 rn
= "ContextConfig";
4701 tcg_gen_helper_0_1(do_mtc0_pagemask
, t0
);
4705 check_insn(env
, ctx
, ISA_MIPS32R2
);
4706 tcg_gen_helper_0_1(do_mtc0_pagegrain
, t0
);
4716 tcg_gen_helper_0_1(do_mtc0_wired
, t0
);
4720 check_insn(env
, ctx
, ISA_MIPS32R2
);
4721 tcg_gen_helper_0_1(do_mtc0_srsconf0
, t0
);
4725 check_insn(env
, ctx
, ISA_MIPS32R2
);
4726 tcg_gen_helper_0_1(do_mtc0_srsconf1
, t0
);
4730 check_insn(env
, ctx
, ISA_MIPS32R2
);
4731 tcg_gen_helper_0_1(do_mtc0_srsconf2
, t0
);
4735 check_insn(env
, ctx
, ISA_MIPS32R2
);
4736 tcg_gen_helper_0_1(do_mtc0_srsconf3
, t0
);
4740 check_insn(env
, ctx
, ISA_MIPS32R2
);
4741 tcg_gen_helper_0_1(do_mtc0_srsconf4
, t0
);
4751 check_insn(env
, ctx
, ISA_MIPS32R2
);
4752 tcg_gen_helper_0_1(do_mtc0_hwrena
, t0
);
4766 tcg_gen_helper_0_1(do_mtc0_count
, t0
);
4769 /* 6,7 are implementation dependent */
4773 /* Stop translation as we may have switched the execution mode */
4774 ctx
->bstate
= BS_STOP
;
4779 tcg_gen_helper_0_1(do_mtc0_entryhi
, t0
);
4789 tcg_gen_helper_0_1(do_mtc0_compare
, t0
);
4792 /* 6,7 are implementation dependent */
4796 /* Stop translation as we may have switched the execution mode */
4797 ctx
->bstate
= BS_STOP
;
4802 tcg_gen_helper_0_1(do_mtc0_status
, t0
);
4803 /* BS_STOP isn't good enough here, hflags may have changed. */
4804 gen_save_pc(ctx
->pc
+ 4);
4805 ctx
->bstate
= BS_EXCP
;
4809 check_insn(env
, ctx
, ISA_MIPS32R2
);
4810 tcg_gen_helper_0_1(do_mtc0_intctl
, t0
);
4811 /* Stop translation as we may have switched the execution mode */
4812 ctx
->bstate
= BS_STOP
;
4816 check_insn(env
, ctx
, ISA_MIPS32R2
);
4817 tcg_gen_helper_0_1(do_mtc0_srsctl
, t0
);
4818 /* Stop translation as we may have switched the execution mode */
4819 ctx
->bstate
= BS_STOP
;
4823 check_insn(env
, ctx
, ISA_MIPS32R2
);
4824 gen_mtc0_store32(t0
, offsetof(CPUState
, CP0_SRSMap
));
4825 /* Stop translation as we may have switched the execution mode */
4826 ctx
->bstate
= BS_STOP
;
4836 tcg_gen_helper_0_1(do_mtc0_cause
, t0
);
4842 /* Stop translation as we may have switched the execution mode */
4843 ctx
->bstate
= BS_STOP
;
4848 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
4862 check_insn(env
, ctx
, ISA_MIPS32R2
);
4863 tcg_gen_helper_0_1(do_mtc0_ebase
, t0
);
4873 tcg_gen_helper_0_1(do_mtc0_config0
, t0
);
4875 /* Stop translation as we may have switched the execution mode */
4876 ctx
->bstate
= BS_STOP
;
4883 tcg_gen_helper_0_1(do_mtc0_config2
, t0
);
4885 /* Stop translation as we may have switched the execution mode */
4886 ctx
->bstate
= BS_STOP
;
4892 /* 6,7 are implementation dependent */
4894 rn
= "Invalid config selector";
4911 tcg_gen_helper_0_1i(do_mtc0_watchlo
, t0
, sel
);
4921 tcg_gen_helper_0_1i(do_mtc0_watchhi
, t0
, sel
);
4931 check_insn(env
, ctx
, ISA_MIPS3
);
4932 tcg_gen_helper_0_1(do_mtc0_xcontext
, t0
);
4940 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4943 tcg_gen_helper_0_1(do_mtc0_framemask
, t0
);
4952 rn
= "Diagnostic"; /* implementation dependent */
4957 tcg_gen_helper_0_1(do_mtc0_debug
, t0
); /* EJTAG support */
4958 /* BS_STOP isn't good enough here, hflags may have changed. */
4959 gen_save_pc(ctx
->pc
+ 4);
4960 ctx
->bstate
= BS_EXCP
;
4964 // tcg_gen_helper_0_1(do_mtc0_tracecontrol, t0); /* PDtrace support */
4965 /* Stop translation as we may have switched the execution mode */
4966 ctx
->bstate
= BS_STOP
;
4967 rn
= "TraceControl";
4970 // tcg_gen_helper_0_1(do_mtc0_tracecontrol2, t0); /* PDtrace support */
4971 /* Stop translation as we may have switched the execution mode */
4972 ctx
->bstate
= BS_STOP
;
4973 rn
= "TraceControl2";
4976 // tcg_gen_helper_0_1(do_mtc0_usertracedata, t0); /* PDtrace support */
4977 /* Stop translation as we may have switched the execution mode */
4978 ctx
->bstate
= BS_STOP
;
4979 rn
= "UserTraceData";
4982 // tcg_gen_helper_0_1(do_mtc0_tracebpc, t0); /* PDtrace support */
4983 /* Stop translation as we may have switched the execution mode */
4984 ctx
->bstate
= BS_STOP
;
4995 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
5005 tcg_gen_helper_0_1(do_mtc0_performance0
, t0
);
5006 rn
= "Performance0";
5009 // tcg_gen_helper_0_1(do_mtc0_performance1, t0);
5010 rn
= "Performance1";
5013 // tcg_gen_helper_0_1(do_mtc0_performance2, t0);
5014 rn
= "Performance2";
5017 // tcg_gen_helper_0_1(do_mtc0_performance3, t0);
5018 rn
= "Performance3";
5021 // tcg_gen_helper_0_1(do_mtc0_performance4, t0);
5022 rn
= "Performance4";
5025 // tcg_gen_helper_0_1(do_mtc0_performance5, t0);
5026 rn
= "Performance5";
5029 // tcg_gen_helper_0_1(do_mtc0_performance6, t0);
5030 rn
= "Performance6";
5033 // tcg_gen_helper_0_1(do_mtc0_performance7, t0);
5034 rn
= "Performance7";
5060 tcg_gen_helper_0_1(do_mtc0_taglo
, t0
);
5067 tcg_gen_helper_0_1(do_mtc0_datalo
, t0
);
5080 tcg_gen_helper_0_1(do_mtc0_taghi
, t0
);
5087 tcg_gen_helper_0_1(do_mtc0_datahi
, t0
);
5098 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
5109 gen_mtc0_store32(t0
, offsetof(CPUState
, CP0_DESAVE
));
5115 /* Stop translation as we may have switched the execution mode */
5116 ctx
->bstate
= BS_STOP
;
5121 #if defined MIPS_DEBUG_DISAS
5122 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
5123 fprintf(logfile
, "dmtc0 %s (reg %d sel %d)\n",
5127 /* For simplicity assume that all writes can cause interrupts. */
5130 ctx
->bstate
= BS_STOP
;
5135 #if defined MIPS_DEBUG_DISAS
5136 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
5137 fprintf(logfile
, "dmtc0 %s (reg %d sel %d)\n",
5141 generate_exception(ctx
, EXCP_RI
);
5143 #endif /* TARGET_MIPS64 */
5145 static void gen_mftr(CPUState
*env
, DisasContext
*ctx
, int rt
, int rd
,
5146 int u
, int sel
, int h
)
5148 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
5149 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
5151 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
5152 ((env
->tcs
[other_tc
].CP0_TCBind
& (0xf << CP0TCBd_CurVPE
)) !=
5153 (env
->active_tc
.CP0_TCBind
& (0xf << CP0TCBd_CurVPE
))))
5154 tcg_gen_movi_tl(t0
, -1);
5155 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
5156 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
5157 tcg_gen_movi_tl(t0
, -1);
5163 tcg_gen_helper_1_0(do_mftc0_tcstatus
, t0
);
5166 tcg_gen_helper_1_0(do_mftc0_tcbind
, t0
);
5169 tcg_gen_helper_1_0(do_mftc0_tcrestart
, t0
);
5172 tcg_gen_helper_1_0(do_mftc0_tchalt
, t0
);
5175 tcg_gen_helper_1_0(do_mftc0_tccontext
, t0
);
5178 tcg_gen_helper_1_0(do_mftc0_tcschedule
, t0
);
5181 tcg_gen_helper_1_0(do_mftc0_tcschefback
, t0
);
5184 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5191 tcg_gen_helper_1_0(do_mftc0_entryhi
, t0
);
5194 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5200 tcg_gen_helper_1_0(do_mftc0_status
, t0
);
5203 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5209 tcg_gen_helper_1_0(do_mftc0_debug
, t0
);
5212 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5217 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5219 } else switch (sel
) {
5220 /* GPR registers. */
5222 tcg_gen_helper_1_i(do_mftgpr
, t0
, rt
);
5224 /* Auxiliary CPU registers */
5228 tcg_gen_helper_1_i(do_mftlo
, t0
, 0);
5231 tcg_gen_helper_1_i(do_mfthi
, t0
, 0);
5234 tcg_gen_helper_1_i(do_mftacx
, t0
, 0);
5237 tcg_gen_helper_1_i(do_mftlo
, t0
, 1);
5240 tcg_gen_helper_1_i(do_mfthi
, t0
, 1);
5243 tcg_gen_helper_1_i(do_mftacx
, t0
, 1);
5246 tcg_gen_helper_1_i(do_mftlo
, t0
, 2);
5249 tcg_gen_helper_1_i(do_mfthi
, t0
, 2);
5252 tcg_gen_helper_1_i(do_mftacx
, t0
, 2);
5255 tcg_gen_helper_1_i(do_mftlo
, t0
, 3);
5258 tcg_gen_helper_1_i(do_mfthi
, t0
, 3);
5261 tcg_gen_helper_1_i(do_mftacx
, t0
, 3);
5264 tcg_gen_helper_1_0(do_mftdsp
, t0
);
5270 /* Floating point (COP1). */
5272 /* XXX: For now we support only a single FPU context. */
5274 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
5276 gen_load_fpr32(fp0
, rt
);
5277 tcg_gen_ext_i32_tl(t0
, fp0
);
5280 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
5282 gen_load_fpr32h(fp0
, rt
);
5283 tcg_gen_ext_i32_tl(t0
, fp0
);
5288 /* XXX: For now we support only a single FPU context. */
5289 tcg_gen_helper_1_1i(do_cfc1
, t0
, t0
, rt
);
5291 /* COP2: Not implemented. */
5298 #if defined MIPS_DEBUG_DISAS
5299 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
5300 fprintf(logfile
, "mftr (reg %d u %d sel %d h %d)\n",
5304 gen_store_gpr(t0
, rd
);
5310 #if defined MIPS_DEBUG_DISAS
5311 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
5312 fprintf(logfile
, "mftr (reg %d u %d sel %d h %d)\n",
5316 generate_exception(ctx
, EXCP_RI
);
5319 static void gen_mttr(CPUState
*env
, DisasContext
*ctx
, int rd
, int rt
,
5320 int u
, int sel
, int h
)
5322 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
5323 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
5325 gen_load_gpr(t0
, rt
);
5326 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
5327 ((env
->tcs
[other_tc
].CP0_TCBind
& (0xf << CP0TCBd_CurVPE
)) !=
5328 (env
->active_tc
.CP0_TCBind
& (0xf << CP0TCBd_CurVPE
))))
5330 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
5331 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
5338 tcg_gen_helper_0_1(do_mttc0_tcstatus
, t0
);
5341 tcg_gen_helper_0_1(do_mttc0_tcbind
, t0
);
5344 tcg_gen_helper_0_1(do_mttc0_tcrestart
, t0
);
5347 tcg_gen_helper_0_1(do_mttc0_tchalt
, t0
);
5350 tcg_gen_helper_0_1(do_mttc0_tccontext
, t0
);
5353 tcg_gen_helper_0_1(do_mttc0_tcschedule
, t0
);
5356 tcg_gen_helper_0_1(do_mttc0_tcschefback
, t0
);
5359 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5366 tcg_gen_helper_0_1(do_mttc0_entryhi
, t0
);
5369 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5375 tcg_gen_helper_0_1(do_mttc0_status
, t0
);
5378 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5384 tcg_gen_helper_0_1(do_mttc0_debug
, t0
);
5387 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5392 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5394 } else switch (sel
) {
5395 /* GPR registers. */
5397 tcg_gen_helper_0_1i(do_mttgpr
, t0
, rd
);
5399 /* Auxiliary CPU registers */
5403 tcg_gen_helper_0_1i(do_mttlo
, t0
, 0);
5406 tcg_gen_helper_0_1i(do_mtthi
, t0
, 0);
5409 tcg_gen_helper_0_1i(do_mttacx
, t0
, 0);
5412 tcg_gen_helper_0_1i(do_mttlo
, t0
, 1);
5415 tcg_gen_helper_0_1i(do_mtthi
, t0
, 1);
5418 tcg_gen_helper_0_1i(do_mttacx
, t0
, 1);
5421 tcg_gen_helper_0_1i(do_mttlo
, t0
, 2);
5424 tcg_gen_helper_0_1i(do_mtthi
, t0
, 2);
5427 tcg_gen_helper_0_1i(do_mttacx
, t0
, 2);
5430 tcg_gen_helper_0_1i(do_mttlo
, t0
, 3);
5433 tcg_gen_helper_0_1i(do_mtthi
, t0
, 3);
5436 tcg_gen_helper_0_1i(do_mttacx
, t0
, 3);
5439 tcg_gen_helper_0_1(do_mttdsp
, t0
);
5445 /* Floating point (COP1). */
5447 /* XXX: For now we support only a single FPU context. */
5449 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
5451 tcg_gen_trunc_tl_i32(fp0
, t0
);
5452 gen_store_fpr32(fp0
, rd
);
5455 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
5457 tcg_gen_trunc_tl_i32(fp0
, t0
);
5458 gen_store_fpr32h(fp0
, rd
);
5463 /* XXX: For now we support only a single FPU context. */
5464 tcg_gen_helper_0_1i(do_ctc1
, t0
, rd
);
5466 /* COP2: Not implemented. */
5473 #if defined MIPS_DEBUG_DISAS
5474 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
5475 fprintf(logfile
, "mttr (reg %d u %d sel %d h %d)\n",
5484 #if defined MIPS_DEBUG_DISAS
5485 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
5486 fprintf(logfile
, "mttr (reg %d u %d sel %d h %d)\n",
5490 generate_exception(ctx
, EXCP_RI
);
5493 static void gen_cp0 (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
, int rt
, int rd
)
5495 const char *opn
= "ldst";
5504 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
5506 gen_mfc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5507 gen_store_gpr(t0
, rt
);
5514 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
5516 gen_load_gpr(t0
, rt
);
5517 save_cpu_state(ctx
, 1);
5518 gen_mtc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5523 #if defined(TARGET_MIPS64)
5525 check_insn(env
, ctx
, ISA_MIPS3
);
5531 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
5533 gen_dmfc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5534 gen_store_gpr(t0
, rt
);
5540 check_insn(env
, ctx
, ISA_MIPS3
);
5542 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
5544 gen_load_gpr(t0
, rt
);
5545 save_cpu_state(ctx
, 1);
5546 gen_dmtc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5553 check_insn(env
, ctx
, ASE_MT
);
5558 gen_mftr(env
, ctx
, rt
, rd
, (ctx
->opcode
>> 5) & 1,
5559 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
5563 check_insn(env
, ctx
, ASE_MT
);
5564 gen_mttr(env
, ctx
, rd
, rt
, (ctx
->opcode
>> 5) & 1,
5565 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
5570 if (!env
->tlb
->do_tlbwi
)
5572 tcg_gen_helper_0_0(env
->tlb
->do_tlbwi
);
5576 if (!env
->tlb
->do_tlbwr
)
5578 tcg_gen_helper_0_0(env
->tlb
->do_tlbwr
);
5582 if (!env
->tlb
->do_tlbp
)
5584 tcg_gen_helper_0_0(env
->tlb
->do_tlbp
);
5588 if (!env
->tlb
->do_tlbr
)
5590 tcg_gen_helper_0_0(env
->tlb
->do_tlbr
);
5594 check_insn(env
, ctx
, ISA_MIPS2
);
5595 save_cpu_state(ctx
, 1);
5596 tcg_gen_helper_0_0(do_eret
);
5597 ctx
->bstate
= BS_EXCP
;
5601 check_insn(env
, ctx
, ISA_MIPS32
);
5602 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
5604 generate_exception(ctx
, EXCP_RI
);
5606 save_cpu_state(ctx
, 1);
5607 tcg_gen_helper_0_0(do_deret
);
5608 ctx
->bstate
= BS_EXCP
;
5613 check_insn(env
, ctx
, ISA_MIPS3
| ISA_MIPS32
);
5614 /* If we get an exception, we want to restart at next instruction */
5616 save_cpu_state(ctx
, 1);
5618 tcg_gen_helper_0_0(do_wait
);
5619 ctx
->bstate
= BS_EXCP
;
5624 generate_exception(ctx
, EXCP_RI
);
5627 MIPS_DEBUG("%s %s %d", opn
, regnames
[rt
], rd
);
5629 #endif /* !CONFIG_USER_ONLY */
5631 /* CP1 Branches (before delay slot) */
5632 static void gen_compute_branch1 (CPUState
*env
, DisasContext
*ctx
, uint32_t op
,
5633 int32_t cc
, int32_t offset
)
5635 target_ulong btarget
;
5636 const char *opn
= "cp1 cond branch";
5637 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
5638 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
5641 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
5643 btarget
= ctx
->pc
+ 4 + offset
;
5648 int l1
= gen_new_label();
5649 int l2
= gen_new_label();
5650 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
5652 get_fp_cond(r_tmp1
);
5653 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
5654 tcg_temp_free(r_tmp1
);
5655 tcg_gen_not_tl(t0
, t0
);
5656 tcg_gen_movi_tl(t1
, 0x1 << cc
);
5657 tcg_gen_and_tl(t0
, t0
, t1
);
5658 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
5659 tcg_gen_movi_tl(t0
, 0);
5662 tcg_gen_movi_tl(t0
, 1);
5669 int l1
= gen_new_label();
5670 int l2
= gen_new_label();
5671 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
5673 get_fp_cond(r_tmp1
);
5674 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
5675 tcg_temp_free(r_tmp1
);
5676 tcg_gen_not_tl(t0
, t0
);
5677 tcg_gen_movi_tl(t1
, 0x1 << cc
);
5678 tcg_gen_and_tl(t0
, t0
, t1
);
5679 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
5680 tcg_gen_movi_tl(t0
, 0);
5683 tcg_gen_movi_tl(t0
, 1);
5690 int l1
= gen_new_label();
5691 int l2
= gen_new_label();
5692 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
5694 get_fp_cond(r_tmp1
);
5695 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
5696 tcg_temp_free(r_tmp1
);
5697 tcg_gen_movi_tl(t1
, 0x1 << cc
);
5698 tcg_gen_and_tl(t0
, t0
, t1
);
5699 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
5700 tcg_gen_movi_tl(t0
, 0);
5703 tcg_gen_movi_tl(t0
, 1);
5710 int l1
= gen_new_label();
5711 int l2
= gen_new_label();
5712 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
5714 get_fp_cond(r_tmp1
);
5715 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
5716 tcg_temp_free(r_tmp1
);
5717 tcg_gen_movi_tl(t1
, 0x1 << cc
);
5718 tcg_gen_and_tl(t0
, t0
, t1
);
5719 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
5720 tcg_gen_movi_tl(t0
, 0);
5723 tcg_gen_movi_tl(t0
, 1);
5728 ctx
->hflags
|= MIPS_HFLAG_BL
;
5729 tcg_gen_trunc_tl_i32(bcond
, t0
);
5733 int l1
= gen_new_label();
5734 int l2
= gen_new_label();
5735 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
5737 get_fp_cond(r_tmp1
);
5738 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
5739 tcg_temp_free(r_tmp1
);
5740 tcg_gen_not_tl(t0
, t0
);
5741 tcg_gen_movi_tl(t1
, 0x3 << cc
);
5742 tcg_gen_and_tl(t0
, t0
, t1
);
5743 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
5744 tcg_gen_movi_tl(t0
, 0);
5747 tcg_gen_movi_tl(t0
, 1);
5754 int l1
= gen_new_label();
5755 int l2
= gen_new_label();
5756 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
5758 get_fp_cond(r_tmp1
);
5759 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
5760 tcg_temp_free(r_tmp1
);
5761 tcg_gen_movi_tl(t1
, 0x3 << cc
);
5762 tcg_gen_and_tl(t0
, t0
, t1
);
5763 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
5764 tcg_gen_movi_tl(t0
, 0);
5767 tcg_gen_movi_tl(t0
, 1);
5774 int l1
= gen_new_label();
5775 int l2
= gen_new_label();
5776 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
5778 get_fp_cond(r_tmp1
);
5779 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
5780 tcg_temp_free(r_tmp1
);
5781 tcg_gen_not_tl(t0
, t0
);
5782 tcg_gen_movi_tl(t1
, 0xf << cc
);
5783 tcg_gen_and_tl(t0
, t0
, t1
);
5784 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
5785 tcg_gen_movi_tl(t0
, 0);
5788 tcg_gen_movi_tl(t0
, 1);
5795 int l1
= gen_new_label();
5796 int l2
= gen_new_label();
5797 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
5799 get_fp_cond(r_tmp1
);
5800 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
5801 tcg_temp_free(r_tmp1
);
5802 tcg_gen_movi_tl(t1
, 0xf << cc
);
5803 tcg_gen_and_tl(t0
, t0
, t1
);
5804 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
5805 tcg_gen_movi_tl(t0
, 0);
5808 tcg_gen_movi_tl(t0
, 1);
5813 ctx
->hflags
|= MIPS_HFLAG_BC
;
5814 tcg_gen_trunc_tl_i32(bcond
, t0
);
5818 generate_exception (ctx
, EXCP_RI
);
5821 MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx
, opn
,
5822 ctx
->hflags
, btarget
);
5823 ctx
->btarget
= btarget
;
5830 /* Coprocessor 1 (FPU) */
5832 #define FOP(func, fmt) (((fmt) << 21) | (func))
5834 static void gen_cp1 (DisasContext
*ctx
, uint32_t opc
, int rt
, int fs
)
5836 const char *opn
= "cp1 move";
5837 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
5842 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
5844 gen_load_fpr32(fp0
, fs
);
5845 tcg_gen_ext_i32_tl(t0
, fp0
);
5848 gen_store_gpr(t0
, rt
);
5852 gen_load_gpr(t0
, rt
);
5854 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
5856 tcg_gen_trunc_tl_i32(fp0
, t0
);
5857 gen_store_fpr32(fp0
, fs
);
5863 tcg_gen_helper_1_i(do_cfc1
, t0
, fs
);
5864 gen_store_gpr(t0
, rt
);
5868 gen_load_gpr(t0
, rt
);
5869 tcg_gen_helper_0_1i(do_ctc1
, t0
, fs
);
5874 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
5876 gen_load_fpr64(ctx
, fp0
, fs
);
5877 tcg_gen_mov_tl(t0
, fp0
);
5880 gen_store_gpr(t0
, rt
);
5884 gen_load_gpr(t0
, rt
);
5886 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
5888 tcg_gen_mov_tl(fp0
, t0
);
5889 gen_store_fpr64(ctx
, fp0
, fs
);
5896 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
5898 gen_load_fpr32h(fp0
, fs
);
5899 tcg_gen_ext_i32_tl(t0
, fp0
);
5902 gen_store_gpr(t0
, rt
);
5906 gen_load_gpr(t0
, rt
);
5908 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
5910 tcg_gen_trunc_tl_i32(fp0
, t0
);
5911 gen_store_fpr32h(fp0
, fs
);
5918 generate_exception (ctx
, EXCP_RI
);
5921 MIPS_DEBUG("%s %s %s", opn
, regnames
[rt
], fregnames
[fs
]);
5927 static void gen_movci (DisasContext
*ctx
, int rd
, int rs
, int cc
, int tf
)
5929 int l1
= gen_new_label();
5932 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
5933 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
5934 TCGv r_tmp
= tcg_temp_local_new(TCG_TYPE_I32
);
5937 ccbit
= 1 << (24 + cc
);
5945 gen_load_gpr(t0
, rd
);
5946 gen_load_gpr(t1
, rs
);
5947 tcg_gen_andi_i32(r_tmp
, fpu_fcr31
, ccbit
);
5948 tcg_gen_brcondi_i32(cond
, r_tmp
, 0, l1
);
5949 tcg_temp_free(r_tmp
);
5951 tcg_gen_mov_tl(t0
, t1
);
5955 gen_store_gpr(t0
, rd
);
5959 static inline void gen_movcf_s (int fs
, int fd
, int cc
, int tf
)
5963 TCGv r_tmp1
= tcg_temp_local_new(TCG_TYPE_I32
);
5964 TCGv fp0
= tcg_temp_local_new(TCG_TYPE_I32
);
5965 TCGv fp1
= tcg_temp_local_new(TCG_TYPE_I32
);
5966 int l1
= gen_new_label();
5969 ccbit
= 1 << (24 + cc
);
5978 gen_load_fpr32(fp0
, fs
);
5979 gen_load_fpr32(fp1
, fd
);
5980 tcg_gen_andi_i32(r_tmp1
, fpu_fcr31
, ccbit
);
5981 tcg_gen_brcondi_i32(cond
, r_tmp1
, 0, l1
);
5982 tcg_gen_mov_i32(fp1
, fp0
);
5985 tcg_temp_free(r_tmp1
);
5986 gen_store_fpr32(fp1
, fd
);
5990 static inline void gen_movcf_d (DisasContext
*ctx
, int fs
, int fd
, int cc
, int tf
)
5994 TCGv r_tmp1
= tcg_temp_local_new(TCG_TYPE_I32
);
5995 TCGv fp0
= tcg_temp_local_new(TCG_TYPE_I64
);
5996 TCGv fp1
= tcg_temp_local_new(TCG_TYPE_I64
);
5997 int l1
= gen_new_label();
6000 ccbit
= 1 << (24 + cc
);
6009 gen_load_fpr64(ctx
, fp0
, fs
);
6010 gen_load_fpr64(ctx
, fp1
, fd
);
6011 tcg_gen_andi_i32(r_tmp1
, fpu_fcr31
, ccbit
);
6012 tcg_gen_brcondi_i32(cond
, r_tmp1
, 0, l1
);
6013 tcg_gen_mov_i64(fp1
, fp0
);
6016 tcg_temp_free(r_tmp1
);
6017 gen_store_fpr64(ctx
, fp1
, fd
);
6021 static inline void gen_movcf_ps (int fs
, int fd
, int cc
, int tf
)
6024 TCGv r_tmp1
= tcg_temp_local_new(TCG_TYPE_I32
);
6025 TCGv r_tmp2
= tcg_temp_local_new(TCG_TYPE_I32
);
6026 TCGv fp0
= tcg_temp_local_new(TCG_TYPE_I32
);
6027 TCGv fph0
= tcg_temp_local_new(TCG_TYPE_I32
);
6028 TCGv fp1
= tcg_temp_local_new(TCG_TYPE_I32
);
6029 TCGv fph1
= tcg_temp_local_new(TCG_TYPE_I32
);
6030 int l1
= gen_new_label();
6031 int l2
= gen_new_label();
6038 gen_load_fpr32(fp0
, fs
);
6039 gen_load_fpr32h(fph0
, fs
);
6040 gen_load_fpr32(fp1
, fd
);
6041 gen_load_fpr32h(fph1
, fd
);
6042 get_fp_cond(r_tmp1
);
6043 tcg_gen_shri_i32(r_tmp1
, r_tmp1
, cc
);
6044 tcg_gen_andi_i32(r_tmp2
, r_tmp1
, 0x1);
6045 tcg_gen_brcondi_i32(cond
, r_tmp2
, 0, l1
);
6046 tcg_gen_mov_i32(fp1
, fp0
);
6049 tcg_gen_andi_i32(r_tmp2
, r_tmp1
, 0x2);
6050 tcg_gen_brcondi_i32(cond
, r_tmp2
, 0, l2
);
6051 tcg_gen_mov_i32(fph1
, fph0
);
6052 tcg_temp_free(fph0
);
6054 tcg_temp_free(r_tmp1
);
6055 tcg_temp_free(r_tmp2
);
6056 gen_store_fpr32(fp1
, fd
);
6057 gen_store_fpr32h(fph1
, fd
);
6059 tcg_temp_free(fph1
);
6063 static void gen_farith (DisasContext
*ctx
, uint32_t op1
,
6064 int ft
, int fs
, int fd
, int cc
)
6066 const char *opn
= "farith";
6067 const char *condnames
[] = {
6085 const char *condnames_abs
[] = {
6103 enum { BINOP
, CMPOP
, OTHEROP
} optype
= OTHEROP
;
6104 uint32_t func
= ctx
->opcode
& 0x3f;
6106 switch (ctx
->opcode
& FOP(0x3f, 0x1f)) {
6109 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6110 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
6112 gen_load_fpr32(fp0
, fs
);
6113 gen_load_fpr32(fp1
, ft
);
6114 tcg_gen_helper_1_2(do_float_add_s
, fp0
, fp0
, fp1
);
6116 gen_store_fpr32(fp0
, fd
);
6124 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6125 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
6127 gen_load_fpr32(fp0
, fs
);
6128 gen_load_fpr32(fp1
, ft
);
6129 tcg_gen_helper_1_2(do_float_sub_s
, fp0
, fp0
, fp1
);
6131 gen_store_fpr32(fp0
, fd
);
6139 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6140 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
6142 gen_load_fpr32(fp0
, fs
);
6143 gen_load_fpr32(fp1
, ft
);
6144 tcg_gen_helper_1_2(do_float_mul_s
, fp0
, fp0
, fp1
);
6146 gen_store_fpr32(fp0
, fd
);
6154 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6155 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
6157 gen_load_fpr32(fp0
, fs
);
6158 gen_load_fpr32(fp1
, ft
);
6159 tcg_gen_helper_1_2(do_float_div_s
, fp0
, fp0
, fp1
);
6161 gen_store_fpr32(fp0
, fd
);
6169 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6171 gen_load_fpr32(fp0
, fs
);
6172 tcg_gen_helper_1_1(do_float_sqrt_s
, fp0
, fp0
);
6173 gen_store_fpr32(fp0
, fd
);
6180 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6182 gen_load_fpr32(fp0
, fs
);
6183 tcg_gen_helper_1_1(do_float_abs_s
, fp0
, fp0
);
6184 gen_store_fpr32(fp0
, fd
);
6191 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6193 gen_load_fpr32(fp0
, fs
);
6194 gen_store_fpr32(fp0
, fd
);
6201 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6203 gen_load_fpr32(fp0
, fs
);
6204 tcg_gen_helper_1_1(do_float_chs_s
, fp0
, fp0
);
6205 gen_store_fpr32(fp0
, fd
);
6211 check_cp1_64bitmode(ctx
);
6213 TCGv fp32
= tcg_temp_new(TCG_TYPE_I32
);
6214 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6216 gen_load_fpr32(fp32
, fs
);
6217 tcg_gen_helper_1_1(do_float_roundl_s
, fp64
, fp32
);
6218 tcg_temp_free(fp32
);
6219 gen_store_fpr64(ctx
, fp64
, fd
);
6220 tcg_temp_free(fp64
);
6225 check_cp1_64bitmode(ctx
);
6227 TCGv fp32
= tcg_temp_new(TCG_TYPE_I32
);
6228 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6230 gen_load_fpr32(fp32
, fs
);
6231 tcg_gen_helper_1_1(do_float_truncl_s
, fp64
, fp32
);
6232 tcg_temp_free(fp32
);
6233 gen_store_fpr64(ctx
, fp64
, fd
);
6234 tcg_temp_free(fp64
);
6239 check_cp1_64bitmode(ctx
);
6241 TCGv fp32
= tcg_temp_new(TCG_TYPE_I32
);
6242 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6244 gen_load_fpr32(fp32
, fs
);
6245 tcg_gen_helper_1_1(do_float_ceill_s
, fp64
, fp32
);
6246 tcg_temp_free(fp32
);
6247 gen_store_fpr64(ctx
, fp64
, fd
);
6248 tcg_temp_free(fp64
);
6253 check_cp1_64bitmode(ctx
);
6255 TCGv fp32
= tcg_temp_new(TCG_TYPE_I32
);
6256 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6258 gen_load_fpr32(fp32
, fs
);
6259 tcg_gen_helper_1_1(do_float_floorl_s
, fp64
, fp32
);
6260 tcg_temp_free(fp32
);
6261 gen_store_fpr64(ctx
, fp64
, fd
);
6262 tcg_temp_free(fp64
);
6268 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6270 gen_load_fpr32(fp0
, fs
);
6271 tcg_gen_helper_1_1(do_float_roundw_s
, fp0
, fp0
);
6272 gen_store_fpr32(fp0
, fd
);
6279 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6281 gen_load_fpr32(fp0
, fs
);
6282 tcg_gen_helper_1_1(do_float_truncw_s
, fp0
, fp0
);
6283 gen_store_fpr32(fp0
, fd
);
6290 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6292 gen_load_fpr32(fp0
, fs
);
6293 tcg_gen_helper_1_1(do_float_ceilw_s
, fp0
, fp0
);
6294 gen_store_fpr32(fp0
, fd
);
6301 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6303 gen_load_fpr32(fp0
, fs
);
6304 tcg_gen_helper_1_1(do_float_floorw_s
, fp0
, fp0
);
6305 gen_store_fpr32(fp0
, fd
);
6311 gen_movcf_s(fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
6316 int l1
= gen_new_label();
6317 TCGv t0
= tcg_temp_new(TCG_TYPE_TL
);
6318 TCGv fp0
= tcg_temp_local_new(TCG_TYPE_I32
);
6320 gen_load_gpr(t0
, ft
);
6321 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
6322 gen_load_fpr32(fp0
, fs
);
6323 gen_store_fpr32(fp0
, fd
);
6332 int l1
= gen_new_label();
6333 TCGv t0
= tcg_temp_new(TCG_TYPE_TL
);
6334 TCGv fp0
= tcg_temp_local_new(TCG_TYPE_I32
);
6336 gen_load_gpr(t0
, ft
);
6337 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
6338 gen_load_fpr32(fp0
, fs
);
6339 gen_store_fpr32(fp0
, fd
);
6349 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6351 gen_load_fpr32(fp0
, fs
);
6352 tcg_gen_helper_1_1(do_float_recip_s
, fp0
, fp0
);
6353 gen_store_fpr32(fp0
, fd
);
6361 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6363 gen_load_fpr32(fp0
, fs
);
6364 tcg_gen_helper_1_1(do_float_rsqrt_s
, fp0
, fp0
);
6365 gen_store_fpr32(fp0
, fd
);
6371 check_cp1_64bitmode(ctx
);
6373 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6374 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
6376 gen_load_fpr32(fp0
, fs
);
6377 gen_load_fpr32(fp1
, fd
);
6378 tcg_gen_helper_1_2(do_float_recip2_s
, fp0
, fp0
, fp1
);
6380 gen_store_fpr32(fp0
, fd
);
6386 check_cp1_64bitmode(ctx
);
6388 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6390 gen_load_fpr32(fp0
, fs
);
6391 tcg_gen_helper_1_1(do_float_recip1_s
, fp0
, fp0
);
6392 gen_store_fpr32(fp0
, fd
);
6398 check_cp1_64bitmode(ctx
);
6400 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6402 gen_load_fpr32(fp0
, fs
);
6403 tcg_gen_helper_1_1(do_float_rsqrt1_s
, fp0
, fp0
);
6404 gen_store_fpr32(fp0
, fd
);
6410 check_cp1_64bitmode(ctx
);
6412 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6413 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
6415 gen_load_fpr32(fp0
, fs
);
6416 gen_load_fpr32(fp1
, ft
);
6417 tcg_gen_helper_1_2(do_float_rsqrt2_s
, fp0
, fp0
, fp1
);
6419 gen_store_fpr32(fp0
, fd
);
6425 check_cp1_registers(ctx
, fd
);
6427 TCGv fp32
= tcg_temp_new(TCG_TYPE_I32
);
6428 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6430 gen_load_fpr32(fp32
, fs
);
6431 tcg_gen_helper_1_1(do_float_cvtd_s
, fp64
, fp32
);
6432 tcg_temp_free(fp32
);
6433 gen_store_fpr64(ctx
, fp64
, fd
);
6434 tcg_temp_free(fp64
);
6440 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6442 gen_load_fpr32(fp0
, fs
);
6443 tcg_gen_helper_1_1(do_float_cvtw_s
, fp0
, fp0
);
6444 gen_store_fpr32(fp0
, fd
);
6450 check_cp1_64bitmode(ctx
);
6452 TCGv fp32
= tcg_temp_new(TCG_TYPE_I32
);
6453 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6455 gen_load_fpr32(fp32
, fs
);
6456 tcg_gen_helper_1_1(do_float_cvtl_s
, fp64
, fp32
);
6457 tcg_temp_free(fp32
);
6458 gen_store_fpr64(ctx
, fp64
, fd
);
6459 tcg_temp_free(fp64
);
6464 check_cp1_64bitmode(ctx
);
6466 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6467 TCGv fp32_0
= tcg_temp_new(TCG_TYPE_I32
);
6468 TCGv fp32_1
= tcg_temp_new(TCG_TYPE_I32
);
6470 gen_load_fpr32(fp32_0
, fs
);
6471 gen_load_fpr32(fp32_1
, ft
);
6472 tcg_gen_concat_i32_i64(fp64
, fp32_0
, fp32_1
);
6473 tcg_temp_free(fp32_1
);
6474 tcg_temp_free(fp32_0
);
6475 gen_store_fpr64(ctx
, fp64
, fd
);
6476 tcg_temp_free(fp64
);
6497 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6498 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
6500 gen_load_fpr32(fp0
, fs
);
6501 gen_load_fpr32(fp1
, ft
);
6502 if (ctx
->opcode
& (1 << 6)) {
6504 gen_cmpabs_s(func
-48, fp0
, fp1
, cc
);
6505 opn
= condnames_abs
[func
-48];
6507 gen_cmp_s(func
-48, fp0
, fp1
, cc
);
6508 opn
= condnames
[func
-48];
6515 check_cp1_registers(ctx
, fs
| ft
| fd
);
6517 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6518 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
6520 gen_load_fpr64(ctx
, fp0
, fs
);
6521 gen_load_fpr64(ctx
, fp1
, ft
);
6522 tcg_gen_helper_1_2(do_float_add_d
, fp0
, fp0
, fp1
);
6524 gen_store_fpr64(ctx
, fp0
, fd
);
6531 check_cp1_registers(ctx
, fs
| ft
| fd
);
6533 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6534 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
6536 gen_load_fpr64(ctx
, fp0
, fs
);
6537 gen_load_fpr64(ctx
, fp1
, ft
);
6538 tcg_gen_helper_1_2(do_float_sub_d
, fp0
, fp0
, fp1
);
6540 gen_store_fpr64(ctx
, fp0
, fd
);
6547 check_cp1_registers(ctx
, fs
| ft
| fd
);
6549 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6550 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
6552 gen_load_fpr64(ctx
, fp0
, fs
);
6553 gen_load_fpr64(ctx
, fp1
, ft
);
6554 tcg_gen_helper_1_2(do_float_mul_d
, fp0
, fp0
, fp1
);
6556 gen_store_fpr64(ctx
, fp0
, fd
);
6563 check_cp1_registers(ctx
, fs
| ft
| fd
);
6565 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6566 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
6568 gen_load_fpr64(ctx
, fp0
, fs
);
6569 gen_load_fpr64(ctx
, fp1
, ft
);
6570 tcg_gen_helper_1_2(do_float_div_d
, fp0
, fp0
, fp1
);
6572 gen_store_fpr64(ctx
, fp0
, fd
);
6579 check_cp1_registers(ctx
, fs
| fd
);
6581 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6583 gen_load_fpr64(ctx
, fp0
, fs
);
6584 tcg_gen_helper_1_1(do_float_sqrt_d
, fp0
, fp0
);
6585 gen_store_fpr64(ctx
, fp0
, fd
);
6591 check_cp1_registers(ctx
, fs
| fd
);
6593 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6595 gen_load_fpr64(ctx
, fp0
, fs
);
6596 tcg_gen_helper_1_1(do_float_abs_d
, fp0
, fp0
);
6597 gen_store_fpr64(ctx
, fp0
, fd
);
6603 check_cp1_registers(ctx
, fs
| fd
);
6605 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6607 gen_load_fpr64(ctx
, fp0
, fs
);
6608 gen_store_fpr64(ctx
, fp0
, fd
);
6614 check_cp1_registers(ctx
, fs
| fd
);
6616 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6618 gen_load_fpr64(ctx
, fp0
, fs
);
6619 tcg_gen_helper_1_1(do_float_chs_d
, fp0
, fp0
);
6620 gen_store_fpr64(ctx
, fp0
, fd
);
6626 check_cp1_64bitmode(ctx
);
6628 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6630 gen_load_fpr64(ctx
, fp0
, fs
);
6631 tcg_gen_helper_1_1(do_float_roundl_d
, fp0
, fp0
);
6632 gen_store_fpr64(ctx
, fp0
, fd
);
6638 check_cp1_64bitmode(ctx
);
6640 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6642 gen_load_fpr64(ctx
, fp0
, fs
);
6643 tcg_gen_helper_1_1(do_float_truncl_d
, fp0
, fp0
);
6644 gen_store_fpr64(ctx
, fp0
, fd
);
6650 check_cp1_64bitmode(ctx
);
6652 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6654 gen_load_fpr64(ctx
, fp0
, fs
);
6655 tcg_gen_helper_1_1(do_float_ceill_d
, fp0
, fp0
);
6656 gen_store_fpr64(ctx
, fp0
, fd
);
6662 check_cp1_64bitmode(ctx
);
6664 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6666 gen_load_fpr64(ctx
, fp0
, fs
);
6667 tcg_gen_helper_1_1(do_float_floorl_d
, fp0
, fp0
);
6668 gen_store_fpr64(ctx
, fp0
, fd
);
6674 check_cp1_registers(ctx
, fs
);
6676 TCGv fp32
= tcg_temp_new(TCG_TYPE_I32
);
6677 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6679 gen_load_fpr64(ctx
, fp64
, fs
);
6680 tcg_gen_helper_1_1(do_float_roundw_d
, fp32
, fp64
);
6681 tcg_temp_free(fp64
);
6682 gen_store_fpr32(fp32
, fd
);
6683 tcg_temp_free(fp32
);
6688 check_cp1_registers(ctx
, fs
);
6690 TCGv fp32
= tcg_temp_new(TCG_TYPE_I32
);
6691 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6693 gen_load_fpr64(ctx
, fp64
, fs
);
6694 tcg_gen_helper_1_1(do_float_truncw_d
, fp32
, fp64
);
6695 tcg_temp_free(fp64
);
6696 gen_store_fpr32(fp32
, fd
);
6697 tcg_temp_free(fp32
);
6702 check_cp1_registers(ctx
, fs
);
6704 TCGv fp32
= tcg_temp_new(TCG_TYPE_I32
);
6705 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6707 gen_load_fpr64(ctx
, fp64
, fs
);
6708 tcg_gen_helper_1_1(do_float_ceilw_d
, fp32
, fp64
);
6709 tcg_temp_free(fp64
);
6710 gen_store_fpr32(fp32
, fd
);
6711 tcg_temp_free(fp32
);
6716 check_cp1_registers(ctx
, fs
);
6718 TCGv fp32
= tcg_temp_new(TCG_TYPE_I32
);
6719 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6721 gen_load_fpr64(ctx
, fp64
, fs
);
6722 tcg_gen_helper_1_1(do_float_floorw_d
, fp32
, fp64
);
6723 tcg_temp_free(fp64
);
6724 gen_store_fpr32(fp32
, fd
);
6725 tcg_temp_free(fp32
);
6730 gen_movcf_d(ctx
, fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
6735 int l1
= gen_new_label();
6736 TCGv t0
= tcg_temp_new(TCG_TYPE_TL
);
6737 TCGv fp0
= tcg_temp_local_new(TCG_TYPE_I64
);
6739 gen_load_gpr(t0
, ft
);
6740 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
6741 gen_load_fpr64(ctx
, fp0
, fs
);
6742 gen_store_fpr64(ctx
, fp0
, fd
);
6751 int l1
= gen_new_label();
6752 TCGv t0
= tcg_temp_new(TCG_TYPE_TL
);
6753 TCGv fp0
= tcg_temp_local_new(TCG_TYPE_I64
);
6755 gen_load_gpr(t0
, ft
);
6756 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
6757 gen_load_fpr64(ctx
, fp0
, fs
);
6758 gen_store_fpr64(ctx
, fp0
, fd
);
6766 check_cp1_64bitmode(ctx
);
6768 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6770 gen_load_fpr64(ctx
, fp0
, fs
);
6771 tcg_gen_helper_1_1(do_float_recip_d
, fp0
, fp0
);
6772 gen_store_fpr64(ctx
, fp0
, fd
);
6778 check_cp1_64bitmode(ctx
);
6780 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6782 gen_load_fpr64(ctx
, fp0
, fs
);
6783 tcg_gen_helper_1_1(do_float_rsqrt_d
, fp0
, fp0
);
6784 gen_store_fpr64(ctx
, fp0
, fd
);
6790 check_cp1_64bitmode(ctx
);
6792 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6793 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
6795 gen_load_fpr64(ctx
, fp0
, fs
);
6796 gen_load_fpr64(ctx
, fp1
, ft
);
6797 tcg_gen_helper_1_2(do_float_recip2_d
, fp0
, fp0
, fp1
);
6799 gen_store_fpr64(ctx
, fp0
, fd
);
6805 check_cp1_64bitmode(ctx
);
6807 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6809 gen_load_fpr64(ctx
, fp0
, fs
);
6810 tcg_gen_helper_1_1(do_float_recip1_d
, fp0
, fp0
);
6811 gen_store_fpr64(ctx
, fp0
, fd
);
6817 check_cp1_64bitmode(ctx
);
6819 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6821 gen_load_fpr64(ctx
, fp0
, fs
);
6822 tcg_gen_helper_1_1(do_float_rsqrt1_d
, fp0
, fp0
);
6823 gen_store_fpr64(ctx
, fp0
, fd
);
6829 check_cp1_64bitmode(ctx
);
6831 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6832 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
6834 gen_load_fpr64(ctx
, fp0
, fs
);
6835 gen_load_fpr64(ctx
, fp1
, ft
);
6836 tcg_gen_helper_1_2(do_float_rsqrt2_d
, fp0
, fp0
, fp1
);
6838 gen_store_fpr64(ctx
, fp0
, fd
);
6860 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6861 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
6863 gen_load_fpr64(ctx
, fp0
, fs
);
6864 gen_load_fpr64(ctx
, fp1
, ft
);
6865 if (ctx
->opcode
& (1 << 6)) {
6867 check_cp1_registers(ctx
, fs
| ft
);
6868 gen_cmpabs_d(func
-48, fp0
, fp1
, cc
);
6869 opn
= condnames_abs
[func
-48];
6871 check_cp1_registers(ctx
, fs
| ft
);
6872 gen_cmp_d(func
-48, fp0
, fp1
, cc
);
6873 opn
= condnames
[func
-48];
6880 check_cp1_registers(ctx
, fs
);
6882 TCGv fp32
= tcg_temp_new(TCG_TYPE_I32
);
6883 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6885 gen_load_fpr64(ctx
, fp64
, fs
);
6886 tcg_gen_helper_1_1(do_float_cvts_d
, fp32
, fp64
);
6887 tcg_temp_free(fp64
);
6888 gen_store_fpr32(fp32
, fd
);
6889 tcg_temp_free(fp32
);
6894 check_cp1_registers(ctx
, fs
);
6896 TCGv fp32
= tcg_temp_new(TCG_TYPE_I32
);
6897 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6899 gen_load_fpr64(ctx
, fp64
, fs
);
6900 tcg_gen_helper_1_1(do_float_cvtw_d
, fp32
, fp64
);
6901 tcg_temp_free(fp64
);
6902 gen_store_fpr32(fp32
, fd
);
6903 tcg_temp_free(fp32
);
6908 check_cp1_64bitmode(ctx
);
6910 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6912 gen_load_fpr64(ctx
, fp0
, fs
);
6913 tcg_gen_helper_1_1(do_float_cvtl_d
, fp0
, fp0
);
6914 gen_store_fpr64(ctx
, fp0
, fd
);
6921 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6923 gen_load_fpr32(fp0
, fs
);
6924 tcg_gen_helper_1_1(do_float_cvts_w
, fp0
, fp0
);
6925 gen_store_fpr32(fp0
, fd
);
6931 check_cp1_registers(ctx
, fd
);
6933 TCGv fp32
= tcg_temp_new(TCG_TYPE_I32
);
6934 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6936 gen_load_fpr32(fp32
, fs
);
6937 tcg_gen_helper_1_1(do_float_cvtd_w
, fp64
, fp32
);
6938 tcg_temp_free(fp32
);
6939 gen_store_fpr64(ctx
, fp64
, fd
);
6940 tcg_temp_free(fp64
);
6945 check_cp1_64bitmode(ctx
);
6947 TCGv fp32
= tcg_temp_new(TCG_TYPE_I32
);
6948 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6950 gen_load_fpr64(ctx
, fp64
, fs
);
6951 tcg_gen_helper_1_1(do_float_cvts_l
, fp32
, fp64
);
6952 tcg_temp_free(fp64
);
6953 gen_store_fpr32(fp32
, fd
);
6954 tcg_temp_free(fp32
);
6959 check_cp1_64bitmode(ctx
);
6961 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6963 gen_load_fpr64(ctx
, fp0
, fs
);
6964 tcg_gen_helper_1_1(do_float_cvtd_l
, fp0
, fp0
);
6965 gen_store_fpr64(ctx
, fp0
, fd
);
6971 check_cp1_64bitmode(ctx
);
6973 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6975 gen_load_fpr64(ctx
, fp0
, fs
);
6976 tcg_gen_helper_1_1(do_float_cvtps_pw
, fp0
, fp0
);
6977 gen_store_fpr64(ctx
, fp0
, fd
);
6983 check_cp1_64bitmode(ctx
);
6985 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6986 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
6988 gen_load_fpr64(ctx
, fp0
, fs
);
6989 gen_load_fpr64(ctx
, fp1
, ft
);
6990 tcg_gen_helper_1_2(do_float_add_ps
, fp0
, fp0
, fp1
);
6992 gen_store_fpr64(ctx
, fp0
, fd
);
6998 check_cp1_64bitmode(ctx
);
7000 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7001 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7003 gen_load_fpr64(ctx
, fp0
, fs
);
7004 gen_load_fpr64(ctx
, fp1
, ft
);
7005 tcg_gen_helper_1_2(do_float_sub_ps
, fp0
, fp0
, fp1
);
7007 gen_store_fpr64(ctx
, fp0
, fd
);
7013 check_cp1_64bitmode(ctx
);
7015 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7016 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7018 gen_load_fpr64(ctx
, fp0
, fs
);
7019 gen_load_fpr64(ctx
, fp1
, ft
);
7020 tcg_gen_helper_1_2(do_float_mul_ps
, fp0
, fp0
, fp1
);
7022 gen_store_fpr64(ctx
, fp0
, fd
);
7028 check_cp1_64bitmode(ctx
);
7030 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7032 gen_load_fpr64(ctx
, fp0
, fs
);
7033 tcg_gen_helper_1_1(do_float_abs_ps
, fp0
, fp0
);
7034 gen_store_fpr64(ctx
, fp0
, fd
);
7040 check_cp1_64bitmode(ctx
);
7042 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7044 gen_load_fpr64(ctx
, fp0
, fs
);
7045 gen_store_fpr64(ctx
, fp0
, fd
);
7051 check_cp1_64bitmode(ctx
);
7053 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7055 gen_load_fpr64(ctx
, fp0
, fs
);
7056 tcg_gen_helper_1_1(do_float_chs_ps
, fp0
, fp0
);
7057 gen_store_fpr64(ctx
, fp0
, fd
);
7063 check_cp1_64bitmode(ctx
);
7064 gen_movcf_ps(fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
7068 check_cp1_64bitmode(ctx
);
7070 int l1
= gen_new_label();
7071 TCGv t0
= tcg_temp_new(TCG_TYPE_TL
);
7072 TCGv fp0
= tcg_temp_local_new(TCG_TYPE_I32
);
7073 TCGv fph0
= tcg_temp_local_new(TCG_TYPE_I32
);
7075 gen_load_gpr(t0
, ft
);
7076 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
7077 gen_load_fpr32(fp0
, fs
);
7078 gen_load_fpr32h(fph0
, fs
);
7079 gen_store_fpr32(fp0
, fd
);
7080 gen_store_fpr32h(fph0
, fd
);
7082 tcg_temp_free(fph0
);
7089 check_cp1_64bitmode(ctx
);
7091 int l1
= gen_new_label();
7092 TCGv t0
= tcg_temp_new(TCG_TYPE_TL
);
7093 TCGv fp0
= tcg_temp_local_new(TCG_TYPE_I32
);
7094 TCGv fph0
= tcg_temp_local_new(TCG_TYPE_I32
);
7096 gen_load_gpr(t0
, ft
);
7097 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
7098 gen_load_fpr32(fp0
, fs
);
7099 gen_load_fpr32h(fph0
, fs
);
7100 gen_store_fpr32(fp0
, fd
);
7101 gen_store_fpr32h(fph0
, fd
);
7103 tcg_temp_free(fph0
);
7110 check_cp1_64bitmode(ctx
);
7112 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7113 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7115 gen_load_fpr64(ctx
, fp0
, ft
);
7116 gen_load_fpr64(ctx
, fp1
, fs
);
7117 tcg_gen_helper_1_2(do_float_addr_ps
, fp0
, fp0
, fp1
);
7119 gen_store_fpr64(ctx
, fp0
, fd
);
7125 check_cp1_64bitmode(ctx
);
7127 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7128 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7130 gen_load_fpr64(ctx
, fp0
, ft
);
7131 gen_load_fpr64(ctx
, fp1
, fs
);
7132 tcg_gen_helper_1_2(do_float_mulr_ps
, fp0
, fp0
, fp1
);
7134 gen_store_fpr64(ctx
, fp0
, fd
);
7140 check_cp1_64bitmode(ctx
);
7142 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7143 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7145 gen_load_fpr64(ctx
, fp0
, fs
);
7146 gen_load_fpr64(ctx
, fp1
, fd
);
7147 tcg_gen_helper_1_2(do_float_recip2_ps
, fp0
, fp0
, fp1
);
7149 gen_store_fpr64(ctx
, fp0
, fd
);
7155 check_cp1_64bitmode(ctx
);
7157 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7159 gen_load_fpr64(ctx
, fp0
, fs
);
7160 tcg_gen_helper_1_1(do_float_recip1_ps
, fp0
, fp0
);
7161 gen_store_fpr64(ctx
, fp0
, fd
);
7167 check_cp1_64bitmode(ctx
);
7169 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7171 gen_load_fpr64(ctx
, fp0
, fs
);
7172 tcg_gen_helper_1_1(do_float_rsqrt1_ps
, fp0
, fp0
);
7173 gen_store_fpr64(ctx
, fp0
, fd
);
7179 check_cp1_64bitmode(ctx
);
7181 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7182 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7184 gen_load_fpr64(ctx
, fp0
, fs
);
7185 gen_load_fpr64(ctx
, fp1
, ft
);
7186 tcg_gen_helper_1_2(do_float_rsqrt2_ps
, fp0
, fp0
, fp1
);
7188 gen_store_fpr64(ctx
, fp0
, fd
);
7194 check_cp1_64bitmode(ctx
);
7196 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
7198 gen_load_fpr32h(fp0
, fs
);
7199 tcg_gen_helper_1_1(do_float_cvts_pu
, fp0
, fp0
);
7200 gen_store_fpr32(fp0
, fd
);
7206 check_cp1_64bitmode(ctx
);
7208 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7210 gen_load_fpr64(ctx
, fp0
, fs
);
7211 tcg_gen_helper_1_1(do_float_cvtpw_ps
, fp0
, fp0
);
7212 gen_store_fpr64(ctx
, fp0
, fd
);
7218 check_cp1_64bitmode(ctx
);
7220 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
7222 gen_load_fpr32(fp0
, fs
);
7223 tcg_gen_helper_1_1(do_float_cvts_pl
, fp0
, fp0
);
7224 gen_store_fpr32(fp0
, fd
);
7230 check_cp1_64bitmode(ctx
);
7232 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
7233 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
7235 gen_load_fpr32(fp0
, fs
);
7236 gen_load_fpr32(fp1
, ft
);
7237 gen_store_fpr32h(fp0
, fd
);
7238 gen_store_fpr32(fp1
, fd
);
7245 check_cp1_64bitmode(ctx
);
7247 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
7248 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
7250 gen_load_fpr32(fp0
, fs
);
7251 gen_load_fpr32h(fp1
, ft
);
7252 gen_store_fpr32(fp1
, fd
);
7253 gen_store_fpr32h(fp0
, fd
);
7260 check_cp1_64bitmode(ctx
);
7262 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
7263 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
7265 gen_load_fpr32h(fp0
, fs
);
7266 gen_load_fpr32(fp1
, ft
);
7267 gen_store_fpr32(fp1
, fd
);
7268 gen_store_fpr32h(fp0
, fd
);
7275 check_cp1_64bitmode(ctx
);
7277 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
7278 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
7280 gen_load_fpr32h(fp0
, fs
);
7281 gen_load_fpr32h(fp1
, ft
);
7282 gen_store_fpr32(fp1
, fd
);
7283 gen_store_fpr32h(fp0
, fd
);
7305 check_cp1_64bitmode(ctx
);
7307 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7308 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7310 gen_load_fpr64(ctx
, fp0
, fs
);
7311 gen_load_fpr64(ctx
, fp1
, ft
);
7312 if (ctx
->opcode
& (1 << 6)) {
7313 gen_cmpabs_ps(func
-48, fp0
, fp1
, cc
);
7314 opn
= condnames_abs
[func
-48];
7316 gen_cmp_ps(func
-48, fp0
, fp1
, cc
);
7317 opn
= condnames
[func
-48];
7325 generate_exception (ctx
, EXCP_RI
);
7330 MIPS_DEBUG("%s %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fs
], fregnames
[ft
]);
7333 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fs
], fregnames
[ft
]);
7336 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fd
], fregnames
[fs
]);
7341 /* Coprocessor 3 (FPU) */
7342 static void gen_flt3_ldst (DisasContext
*ctx
, uint32_t opc
,
7343 int fd
, int fs
, int base
, int index
)
7345 const char *opn
= "extended float load/store";
7347 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
7348 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
7351 gen_load_gpr(t0
, index
);
7352 } else if (index
== 0) {
7353 gen_load_gpr(t0
, base
);
7355 gen_load_gpr(t0
, base
);
7356 gen_load_gpr(t1
, index
);
7357 gen_op_addr_add(ctx
, t0
, t1
);
7359 /* Don't do NOP if destination is zero: we must perform the actual
7365 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
7367 tcg_gen_qemu_ld32s(fp0
, t0
, ctx
->mem_idx
);
7368 gen_store_fpr32(fp0
, fd
);
7375 check_cp1_registers(ctx
, fd
);
7377 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7379 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
7380 gen_store_fpr64(ctx
, fp0
, fd
);
7386 check_cp1_64bitmode(ctx
);
7387 tcg_gen_andi_tl(t0
, t0
, ~0x7);
7389 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7391 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
7392 gen_store_fpr64(ctx
, fp0
, fd
);
7400 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
7402 gen_load_fpr32(fp0
, fs
);
7403 tcg_gen_qemu_st32(fp0
, t0
, ctx
->mem_idx
);
7411 check_cp1_registers(ctx
, fs
);
7413 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7415 gen_load_fpr64(ctx
, fp0
, fs
);
7416 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
7423 check_cp1_64bitmode(ctx
);
7424 tcg_gen_andi_tl(t0
, t0
, ~0x7);
7426 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7428 gen_load_fpr64(ctx
, fp0
, fs
);
7429 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
7437 generate_exception(ctx
, EXCP_RI
);
7444 MIPS_DEBUG("%s %s, %s(%s)", opn
, fregnames
[store
? fs
: fd
],
7445 regnames
[index
], regnames
[base
]);
7448 static void gen_flt3_arith (DisasContext
*ctx
, uint32_t opc
,
7449 int fd
, int fr
, int fs
, int ft
)
7451 const char *opn
= "flt3_arith";
7455 check_cp1_64bitmode(ctx
);
7457 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
7458 TCGv fp0
= tcg_temp_local_new(TCG_TYPE_I32
);
7459 TCGv fph0
= tcg_temp_local_new(TCG_TYPE_I32
);
7460 TCGv fp1
= tcg_temp_local_new(TCG_TYPE_I32
);
7461 TCGv fph1
= tcg_temp_local_new(TCG_TYPE_I32
);
7462 int l1
= gen_new_label();
7463 int l2
= gen_new_label();
7465 gen_load_gpr(t0
, fr
);
7466 tcg_gen_andi_tl(t0
, t0
, 0x7);
7467 gen_load_fpr32(fp0
, fs
);
7468 gen_load_fpr32h(fph0
, fs
);
7469 gen_load_fpr32(fp1
, ft
);
7470 gen_load_fpr32h(fph1
, ft
);
7472 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
7473 gen_store_fpr32(fp0
, fd
);
7474 gen_store_fpr32h(fph0
, fd
);
7477 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 4, l2
);
7479 #ifdef TARGET_WORDS_BIGENDIAN
7480 gen_store_fpr32(fph1
, fd
);
7481 gen_store_fpr32h(fp0
, fd
);
7483 gen_store_fpr32(fph0
, fd
);
7484 gen_store_fpr32h(fp1
, fd
);
7488 tcg_temp_free(fph0
);
7490 tcg_temp_free(fph1
);
7497 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
7498 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
7499 TCGv fp2
= tcg_temp_new(TCG_TYPE_I32
);
7501 gen_load_fpr32(fp0
, fs
);
7502 gen_load_fpr32(fp1
, ft
);
7503 gen_load_fpr32(fp2
, fr
);
7504 tcg_gen_helper_1_3(do_float_muladd_s
, fp2
, fp0
, fp1
, fp2
);
7507 gen_store_fpr32(fp2
, fd
);
7514 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7516 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7517 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7518 TCGv fp2
= tcg_temp_new(TCG_TYPE_I64
);
7520 gen_load_fpr64(ctx
, fp0
, fs
);
7521 gen_load_fpr64(ctx
, fp1
, ft
);
7522 gen_load_fpr64(ctx
, fp2
, fr
);
7523 tcg_gen_helper_1_3(do_float_muladd_d
, fp2
, fp0
, fp1
, fp2
);
7526 gen_store_fpr64(ctx
, fp2
, fd
);
7532 check_cp1_64bitmode(ctx
);
7534 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7535 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7536 TCGv fp2
= tcg_temp_new(TCG_TYPE_I64
);
7538 gen_load_fpr64(ctx
, fp0
, fs
);
7539 gen_load_fpr64(ctx
, fp1
, ft
);
7540 gen_load_fpr64(ctx
, fp2
, fr
);
7541 tcg_gen_helper_1_3(do_float_muladd_ps
, fp2
, fp0
, fp1
, fp2
);
7544 gen_store_fpr64(ctx
, fp2
, fd
);
7552 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
7553 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
7554 TCGv fp2
= tcg_temp_new(TCG_TYPE_I32
);
7556 gen_load_fpr32(fp0
, fs
);
7557 gen_load_fpr32(fp1
, ft
);
7558 gen_load_fpr32(fp2
, fr
);
7559 tcg_gen_helper_1_3(do_float_mulsub_s
, fp2
, fp0
, fp1
, fp2
);
7562 gen_store_fpr32(fp2
, fd
);
7569 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7571 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7572 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7573 TCGv fp2
= tcg_temp_new(TCG_TYPE_I64
);
7575 gen_load_fpr64(ctx
, fp0
, fs
);
7576 gen_load_fpr64(ctx
, fp1
, ft
);
7577 gen_load_fpr64(ctx
, fp2
, fr
);
7578 tcg_gen_helper_1_3(do_float_mulsub_d
, fp2
, fp0
, fp1
, fp2
);
7581 gen_store_fpr64(ctx
, fp2
, fd
);
7587 check_cp1_64bitmode(ctx
);
7589 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7590 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7591 TCGv fp2
= tcg_temp_new(TCG_TYPE_I64
);
7593 gen_load_fpr64(ctx
, fp0
, fs
);
7594 gen_load_fpr64(ctx
, fp1
, ft
);
7595 gen_load_fpr64(ctx
, fp2
, fr
);
7596 tcg_gen_helper_1_3(do_float_mulsub_ps
, fp2
, fp0
, fp1
, fp2
);
7599 gen_store_fpr64(ctx
, fp2
, fd
);
7607 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
7608 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
7609 TCGv fp2
= tcg_temp_new(TCG_TYPE_I32
);
7611 gen_load_fpr32(fp0
, fs
);
7612 gen_load_fpr32(fp1
, ft
);
7613 gen_load_fpr32(fp2
, fr
);
7614 tcg_gen_helper_1_3(do_float_nmuladd_s
, fp2
, fp0
, fp1
, fp2
);
7617 gen_store_fpr32(fp2
, fd
);
7624 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7626 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7627 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7628 TCGv fp2
= tcg_temp_new(TCG_TYPE_I64
);
7630 gen_load_fpr64(ctx
, fp0
, fs
);
7631 gen_load_fpr64(ctx
, fp1
, ft
);
7632 gen_load_fpr64(ctx
, fp2
, fr
);
7633 tcg_gen_helper_1_3(do_float_nmuladd_d
, fp2
, fp0
, fp1
, fp2
);
7636 gen_store_fpr64(ctx
, fp2
, fd
);
7642 check_cp1_64bitmode(ctx
);
7644 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7645 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7646 TCGv fp2
= tcg_temp_new(TCG_TYPE_I64
);
7648 gen_load_fpr64(ctx
, fp0
, fs
);
7649 gen_load_fpr64(ctx
, fp1
, ft
);
7650 gen_load_fpr64(ctx
, fp2
, fr
);
7651 tcg_gen_helper_1_3(do_float_nmuladd_ps
, fp2
, fp0
, fp1
, fp2
);
7654 gen_store_fpr64(ctx
, fp2
, fd
);
7662 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
7663 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
7664 TCGv fp2
= tcg_temp_new(TCG_TYPE_I32
);
7666 gen_load_fpr32(fp0
, fs
);
7667 gen_load_fpr32(fp1
, ft
);
7668 gen_load_fpr32(fp2
, fr
);
7669 tcg_gen_helper_1_3(do_float_nmulsub_s
, fp2
, fp0
, fp1
, fp2
);
7672 gen_store_fpr32(fp2
, fd
);
7679 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7681 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7682 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7683 TCGv fp2
= tcg_temp_new(TCG_TYPE_I64
);
7685 gen_load_fpr64(ctx
, fp0
, fs
);
7686 gen_load_fpr64(ctx
, fp1
, ft
);
7687 gen_load_fpr64(ctx
, fp2
, fr
);
7688 tcg_gen_helper_1_3(do_float_nmulsub_d
, fp2
, fp0
, fp1
, fp2
);
7691 gen_store_fpr64(ctx
, fp2
, fd
);
7697 check_cp1_64bitmode(ctx
);
7699 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7700 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7701 TCGv fp2
= tcg_temp_new(TCG_TYPE_I64
);
7703 gen_load_fpr64(ctx
, fp0
, fs
);
7704 gen_load_fpr64(ctx
, fp1
, ft
);
7705 gen_load_fpr64(ctx
, fp2
, fr
);
7706 tcg_gen_helper_1_3(do_float_nmulsub_ps
, fp2
, fp0
, fp1
, fp2
);
7709 gen_store_fpr64(ctx
, fp2
, fd
);
7716 generate_exception (ctx
, EXCP_RI
);
7719 MIPS_DEBUG("%s %s, %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fr
],
7720 fregnames
[fs
], fregnames
[ft
]);
7723 /* ISA extensions (ASEs) */
7724 /* MIPS16 extension to MIPS32 */
7725 /* SmartMIPS extension to MIPS32 */
7727 #if defined(TARGET_MIPS64)
7729 /* MDMX extension to MIPS64 */
7733 static void decode_opc (CPUState
*env
, DisasContext
*ctx
)
7737 uint32_t op
, op1
, op2
;
7740 /* make sure instructions are on a word boundary */
7741 if (ctx
->pc
& 0x3) {
7742 env
->CP0_BadVAddr
= ctx
->pc
;
7743 generate_exception(ctx
, EXCP_AdEL
);
7747 /* Handle blikely not taken case */
7748 if ((ctx
->hflags
& MIPS_HFLAG_BMASK
) == MIPS_HFLAG_BL
) {
7749 int l1
= gen_new_label();
7751 MIPS_DEBUG("blikely condition (" TARGET_FMT_lx
")", ctx
->pc
+ 4);
7752 tcg_gen_brcondi_i32(TCG_COND_NE
, bcond
, 0, l1
);
7754 TCGv r_tmp
= tcg_temp_new(TCG_TYPE_I32
);
7756 tcg_gen_movi_i32(r_tmp
, ctx
->hflags
& ~MIPS_HFLAG_BMASK
);
7757 tcg_gen_st_i32(r_tmp
, cpu_env
, offsetof(CPUState
, hflags
));
7758 tcg_temp_free(r_tmp
);
7760 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
7763 op
= MASK_OP_MAJOR(ctx
->opcode
);
7764 rs
= (ctx
->opcode
>> 21) & 0x1f;
7765 rt
= (ctx
->opcode
>> 16) & 0x1f;
7766 rd
= (ctx
->opcode
>> 11) & 0x1f;
7767 sa
= (ctx
->opcode
>> 6) & 0x1f;
7768 imm
= (int16_t)ctx
->opcode
;
7771 op1
= MASK_SPECIAL(ctx
->opcode
);
7773 case OPC_SLL
: /* Arithmetic with immediate */
7774 case OPC_SRL
... OPC_SRA
:
7775 gen_arith_imm(env
, ctx
, op1
, rd
, rt
, sa
);
7777 case OPC_MOVZ
... OPC_MOVN
:
7778 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
7779 case OPC_SLLV
: /* Arithmetic */
7780 case OPC_SRLV
... OPC_SRAV
:
7781 case OPC_ADD
... OPC_NOR
:
7782 case OPC_SLT
... OPC_SLTU
:
7783 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
7785 case OPC_MULT
... OPC_DIVU
:
7787 check_insn(env
, ctx
, INSN_VR54XX
);
7788 op1
= MASK_MUL_VR54XX(ctx
->opcode
);
7789 gen_mul_vr54xx(ctx
, op1
, rd
, rs
, rt
);
7791 gen_muldiv(ctx
, op1
, rs
, rt
);
7793 case OPC_JR
... OPC_JALR
:
7794 gen_compute_branch(ctx
, op1
, rs
, rd
, sa
);
7796 case OPC_TGE
... OPC_TEQ
: /* Traps */
7798 gen_trap(ctx
, op1
, rs
, rt
, -1);
7800 case OPC_MFHI
: /* Move from HI/LO */
7802 gen_HILO(ctx
, op1
, rd
);
7805 case OPC_MTLO
: /* Move to HI/LO */
7806 gen_HILO(ctx
, op1
, rs
);
7808 case OPC_PMON
: /* Pmon entry point, also R4010 selsl */
7809 #ifdef MIPS_STRICT_STANDARD
7810 MIPS_INVAL("PMON / selsl");
7811 generate_exception(ctx
, EXCP_RI
);
7813 tcg_gen_helper_0_i(do_pmon
, sa
);
7817 generate_exception(ctx
, EXCP_SYSCALL
);
7820 generate_exception(ctx
, EXCP_BREAK
);
7823 #ifdef MIPS_STRICT_STANDARD
7825 generate_exception(ctx
, EXCP_RI
);
7827 /* Implemented as RI exception for now. */
7828 MIPS_INVAL("spim (unofficial)");
7829 generate_exception(ctx
, EXCP_RI
);
7837 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
7838 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
7839 save_cpu_state(ctx
, 1);
7840 check_cp1_enabled(ctx
);
7841 gen_movci(ctx
, rd
, rs
, (ctx
->opcode
>> 18) & 0x7,
7842 (ctx
->opcode
>> 16) & 1);
7844 generate_exception_err(ctx
, EXCP_CpU
, 1);
7848 #if defined(TARGET_MIPS64)
7849 /* MIPS64 specific opcodes */
7851 case OPC_DSRL
... OPC_DSRA
:
7853 case OPC_DSRL32
... OPC_DSRA32
:
7854 check_insn(env
, ctx
, ISA_MIPS3
);
7856 gen_arith_imm(env
, ctx
, op1
, rd
, rt
, sa
);
7859 case OPC_DSRLV
... OPC_DSRAV
:
7860 case OPC_DADD
... OPC_DSUBU
:
7861 check_insn(env
, ctx
, ISA_MIPS3
);
7863 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
7865 case OPC_DMULT
... OPC_DDIVU
:
7866 check_insn(env
, ctx
, ISA_MIPS3
);
7868 gen_muldiv(ctx
, op1
, rs
, rt
);
7871 default: /* Invalid */
7872 MIPS_INVAL("special");
7873 generate_exception(ctx
, EXCP_RI
);
7878 op1
= MASK_SPECIAL2(ctx
->opcode
);
7880 case OPC_MADD
... OPC_MADDU
: /* Multiply and add/sub */
7881 case OPC_MSUB
... OPC_MSUBU
:
7882 check_insn(env
, ctx
, ISA_MIPS32
);
7883 gen_muldiv(ctx
, op1
, rs
, rt
);
7886 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
7888 case OPC_CLZ
... OPC_CLO
:
7889 check_insn(env
, ctx
, ISA_MIPS32
);
7890 gen_cl(ctx
, op1
, rd
, rs
);
7893 /* XXX: not clear which exception should be raised
7894 * when in debug mode...
7896 check_insn(env
, ctx
, ISA_MIPS32
);
7897 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
7898 generate_exception(ctx
, EXCP_DBp
);
7900 generate_exception(ctx
, EXCP_DBp
);
7904 #if defined(TARGET_MIPS64)
7905 case OPC_DCLZ
... OPC_DCLO
:
7906 check_insn(env
, ctx
, ISA_MIPS64
);
7908 gen_cl(ctx
, op1
, rd
, rs
);
7911 default: /* Invalid */
7912 MIPS_INVAL("special2");
7913 generate_exception(ctx
, EXCP_RI
);
7918 op1
= MASK_SPECIAL3(ctx
->opcode
);
7922 check_insn(env
, ctx
, ISA_MIPS32R2
);
7923 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
7926 check_insn(env
, ctx
, ISA_MIPS32R2
);
7927 op2
= MASK_BSHFL(ctx
->opcode
);
7928 gen_bshfl(ctx
, op2
, rt
, rd
);
7931 check_insn(env
, ctx
, ISA_MIPS32R2
);
7933 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
7937 save_cpu_state(ctx
, 1);
7938 tcg_gen_helper_1_0(do_rdhwr_cpunum
, t0
);
7941 save_cpu_state(ctx
, 1);
7942 tcg_gen_helper_1_0(do_rdhwr_synci_step
, t0
);
7945 save_cpu_state(ctx
, 1);
7946 tcg_gen_helper_1_0(do_rdhwr_cc
, t0
);
7949 save_cpu_state(ctx
, 1);
7950 tcg_gen_helper_1_0(do_rdhwr_ccres
, t0
);
7953 if (env
->user_mode_only
) {
7954 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, tls_value
));
7957 /* XXX: Some CPUs implement this in hardware.
7958 Not supported yet. */
7960 default: /* Invalid */
7961 MIPS_INVAL("rdhwr");
7962 generate_exception(ctx
, EXCP_RI
);
7965 gen_store_gpr(t0
, rt
);
7970 check_insn(env
, ctx
, ASE_MT
);
7972 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
7973 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
7975 gen_load_gpr(t0
, rt
);
7976 gen_load_gpr(t1
, rs
);
7977 tcg_gen_helper_0_2(do_fork
, t0
, t1
);
7983 check_insn(env
, ctx
, ASE_MT
);
7985 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
7987 gen_load_gpr(t0
, rs
);
7988 tcg_gen_helper_1_1(do_yield
, t0
, t0
);
7989 gen_store_gpr(t0
, rd
);
7993 #if defined(TARGET_MIPS64)
7994 case OPC_DEXTM
... OPC_DEXT
:
7995 case OPC_DINSM
... OPC_DINS
:
7996 check_insn(env
, ctx
, ISA_MIPS64R2
);
7998 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
8001 check_insn(env
, ctx
, ISA_MIPS64R2
);
8003 op2
= MASK_DBSHFL(ctx
->opcode
);
8004 gen_bshfl(ctx
, op2
, rt
, rd
);
8007 default: /* Invalid */
8008 MIPS_INVAL("special3");
8009 generate_exception(ctx
, EXCP_RI
);
8014 op1
= MASK_REGIMM(ctx
->opcode
);
8016 case OPC_BLTZ
... OPC_BGEZL
: /* REGIMM branches */
8017 case OPC_BLTZAL
... OPC_BGEZALL
:
8018 gen_compute_branch(ctx
, op1
, rs
, -1, imm
<< 2);
8020 case OPC_TGEI
... OPC_TEQI
: /* REGIMM traps */
8022 gen_trap(ctx
, op1
, rs
, -1, imm
);
8025 check_insn(env
, ctx
, ISA_MIPS32R2
);
8028 default: /* Invalid */
8029 MIPS_INVAL("regimm");
8030 generate_exception(ctx
, EXCP_RI
);
8035 check_cp0_enabled(ctx
);
8036 op1
= MASK_CP0(ctx
->opcode
);
8042 #if defined(TARGET_MIPS64)
8046 #ifndef CONFIG_USER_ONLY
8047 if (!env
->user_mode_only
)
8048 gen_cp0(env
, ctx
, op1
, rt
, rd
);
8049 #endif /* !CONFIG_USER_ONLY */
8051 case OPC_C0_FIRST
... OPC_C0_LAST
:
8052 #ifndef CONFIG_USER_ONLY
8053 if (!env
->user_mode_only
)
8054 gen_cp0(env
, ctx
, MASK_C0(ctx
->opcode
), rt
, rd
);
8055 #endif /* !CONFIG_USER_ONLY */
8058 #ifndef CONFIG_USER_ONLY
8059 if (!env
->user_mode_only
) {
8060 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
8062 op2
= MASK_MFMC0(ctx
->opcode
);
8065 check_insn(env
, ctx
, ASE_MT
);
8066 tcg_gen_helper_1_1(do_dmt
, t0
, t0
);
8069 check_insn(env
, ctx
, ASE_MT
);
8070 tcg_gen_helper_1_1(do_emt
, t0
, t0
);
8073 check_insn(env
, ctx
, ASE_MT
);
8074 tcg_gen_helper_1_1(do_dvpe
, t0
, t0
);
8077 check_insn(env
, ctx
, ASE_MT
);
8078 tcg_gen_helper_1_1(do_evpe
, t0
, t0
);
8081 check_insn(env
, ctx
, ISA_MIPS32R2
);
8082 save_cpu_state(ctx
, 1);
8083 tcg_gen_helper_1_0(do_di
, t0
);
8084 /* Stop translation as we may have switched the execution mode */
8085 ctx
->bstate
= BS_STOP
;
8088 check_insn(env
, ctx
, ISA_MIPS32R2
);
8089 save_cpu_state(ctx
, 1);
8090 tcg_gen_helper_1_0(do_ei
, t0
);
8091 /* Stop translation as we may have switched the execution mode */
8092 ctx
->bstate
= BS_STOP
;
8094 default: /* Invalid */
8095 MIPS_INVAL("mfmc0");
8096 generate_exception(ctx
, EXCP_RI
);
8099 gen_store_gpr(t0
, rt
);
8102 #endif /* !CONFIG_USER_ONLY */
8105 check_insn(env
, ctx
, ISA_MIPS32R2
);
8106 gen_load_srsgpr(rt
, rd
);
8109 check_insn(env
, ctx
, ISA_MIPS32R2
);
8110 gen_store_srsgpr(rt
, rd
);
8114 generate_exception(ctx
, EXCP_RI
);
8118 case OPC_ADDI
... OPC_LUI
: /* Arithmetic with immediate opcode */
8119 gen_arith_imm(env
, ctx
, op
, rt
, rs
, imm
);
8121 case OPC_J
... OPC_JAL
: /* Jump */
8122 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 2;
8123 gen_compute_branch(ctx
, op
, rs
, rt
, offset
);
8125 case OPC_BEQ
... OPC_BGTZ
: /* Branch */
8126 case OPC_BEQL
... OPC_BGTZL
:
8127 gen_compute_branch(ctx
, op
, rs
, rt
, imm
<< 2);
8129 case OPC_LB
... OPC_LWR
: /* Load and stores */
8130 case OPC_SB
... OPC_SW
:
8134 gen_ldst(ctx
, op
, rt
, rs
, imm
);
8137 check_insn(env
, ctx
, ISA_MIPS3
| ISA_MIPS32
);
8141 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
8145 /* Floating point (COP1). */
8150 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
8151 save_cpu_state(ctx
, 1);
8152 check_cp1_enabled(ctx
);
8153 gen_flt_ldst(ctx
, op
, rt
, rs
, imm
);
8155 generate_exception_err(ctx
, EXCP_CpU
, 1);
8160 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
8161 save_cpu_state(ctx
, 1);
8162 check_cp1_enabled(ctx
);
8163 op1
= MASK_CP1(ctx
->opcode
);
8167 check_insn(env
, ctx
, ISA_MIPS32R2
);
8172 gen_cp1(ctx
, op1
, rt
, rd
);
8174 #if defined(TARGET_MIPS64)
8177 check_insn(env
, ctx
, ISA_MIPS3
);
8178 gen_cp1(ctx
, op1
, rt
, rd
);
8184 check_insn(env
, ctx
, ASE_MIPS3D
);
8187 gen_compute_branch1(env
, ctx
, MASK_BC1(ctx
->opcode
),
8188 (rt
>> 2) & 0x7, imm
<< 2);
8195 gen_farith(ctx
, MASK_CP1_FUNC(ctx
->opcode
), rt
, rd
, sa
,
8200 generate_exception (ctx
, EXCP_RI
);
8204 generate_exception_err(ctx
, EXCP_CpU
, 1);
8214 /* COP2: Not implemented. */
8215 generate_exception_err(ctx
, EXCP_CpU
, 2);
8219 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
8220 save_cpu_state(ctx
, 1);
8221 check_cp1_enabled(ctx
);
8222 op1
= MASK_CP3(ctx
->opcode
);
8230 gen_flt3_ldst(ctx
, op1
, sa
, rd
, rs
, rt
);
8248 gen_flt3_arith(ctx
, op1
, sa
, rs
, rd
, rt
);
8252 generate_exception (ctx
, EXCP_RI
);
8256 generate_exception_err(ctx
, EXCP_CpU
, 1);
8260 #if defined(TARGET_MIPS64)
8261 /* MIPS64 opcodes */
8263 case OPC_LDL
... OPC_LDR
:
8264 case OPC_SDL
... OPC_SDR
:
8269 check_insn(env
, ctx
, ISA_MIPS3
);
8271 gen_ldst(ctx
, op
, rt
, rs
, imm
);
8273 case OPC_DADDI
... OPC_DADDIU
:
8274 check_insn(env
, ctx
, ISA_MIPS3
);
8276 gen_arith_imm(env
, ctx
, op
, rt
, rs
, imm
);
8280 check_insn(env
, ctx
, ASE_MIPS16
);
8281 /* MIPS16: Not implemented. */
8283 check_insn(env
, ctx
, ASE_MDMX
);
8284 /* MDMX: Not implemented. */
8285 default: /* Invalid */
8286 MIPS_INVAL("major opcode");
8287 generate_exception(ctx
, EXCP_RI
);
8290 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
8291 int hflags
= ctx
->hflags
& MIPS_HFLAG_BMASK
;
8292 /* Branches completion */
8293 ctx
->hflags
&= ~MIPS_HFLAG_BMASK
;
8294 ctx
->bstate
= BS_BRANCH
;
8295 save_cpu_state(ctx
, 0);
8296 /* FIXME: Need to clear can_do_io. */
8299 /* unconditional branch */
8300 MIPS_DEBUG("unconditional branch");
8301 gen_goto_tb(ctx
, 0, ctx
->btarget
);
8304 /* blikely taken case */
8305 MIPS_DEBUG("blikely branch taken");
8306 gen_goto_tb(ctx
, 0, ctx
->btarget
);
8309 /* Conditional branch */
8310 MIPS_DEBUG("conditional branch");
8312 int l1
= gen_new_label();
8314 tcg_gen_brcondi_i32(TCG_COND_NE
, bcond
, 0, l1
);
8315 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
8317 gen_goto_tb(ctx
, 0, ctx
->btarget
);
8321 /* unconditional branch to register */
8322 MIPS_DEBUG("branch to register");
8323 tcg_gen_mov_tl(cpu_PC
, btarget
);
8327 MIPS_DEBUG("unknown branch");
8334 gen_intermediate_code_internal (CPUState
*env
, TranslationBlock
*tb
,
8338 target_ulong pc_start
;
8339 uint16_t *gen_opc_end
;
8344 if (search_pc
&& loglevel
)
8345 fprintf (logfile
, "search pc %d\n", search_pc
);
8348 /* Leave some spare opc slots for branch handling. */
8349 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
- 16;
8353 ctx
.bstate
= BS_NONE
;
8354 /* Restore delay slot state from the tb context. */
8355 ctx
.hflags
= (uint32_t)tb
->flags
; /* FIXME: maybe use 64 bits here? */
8356 restore_cpu_state(env
, &ctx
);
8357 if (env
->user_mode_only
)
8358 ctx
.mem_idx
= MIPS_HFLAG_UM
;
8360 ctx
.mem_idx
= ctx
.hflags
& MIPS_HFLAG_KSU
;
8362 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
8364 max_insns
= CF_COUNT_MASK
;
8366 if (loglevel
& CPU_LOG_TB_CPU
) {
8367 fprintf(logfile
, "------------------------------------------------\n");
8368 /* FIXME: This may print out stale hflags from env... */
8369 cpu_dump_state(env
, logfile
, fprintf
, 0);
8372 #ifdef MIPS_DEBUG_DISAS
8373 if (loglevel
& CPU_LOG_TB_IN_ASM
)
8374 fprintf(logfile
, "\ntb %p idx %d hflags %04x\n",
8375 tb
, ctx
.mem_idx
, ctx
.hflags
);
8378 while (ctx
.bstate
== BS_NONE
) {
8379 if (env
->nb_breakpoints
> 0) {
8380 for(j
= 0; j
< env
->nb_breakpoints
; j
++) {
8381 if (env
->breakpoints
[j
] == ctx
.pc
) {
8382 save_cpu_state(&ctx
, 1);
8383 ctx
.bstate
= BS_BRANCH
;
8384 tcg_gen_helper_0_i(do_raise_exception
, EXCP_DEBUG
);
8385 /* Include the breakpoint location or the tb won't
8386 * be flushed when it must be. */
8388 goto done_generating
;
8394 j
= gen_opc_ptr
- gen_opc_buf
;
8398 gen_opc_instr_start
[lj
++] = 0;
8400 gen_opc_pc
[lj
] = ctx
.pc
;
8401 gen_opc_hflags
[lj
] = ctx
.hflags
& MIPS_HFLAG_BMASK
;
8402 gen_opc_instr_start
[lj
] = 1;
8403 gen_opc_icount
[lj
] = num_insns
;
8405 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
8407 ctx
.opcode
= ldl_code(ctx
.pc
);
8408 decode_opc(env
, &ctx
);
8412 if (env
->singlestep_enabled
)
8415 if ((ctx
.pc
& (TARGET_PAGE_SIZE
- 1)) == 0)
8418 if (gen_opc_ptr
>= gen_opc_end
)
8421 if (num_insns
>= max_insns
)
8423 #if defined (MIPS_SINGLE_STEP)
8427 if (tb
->cflags
& CF_LAST_IO
)
8429 if (env
->singlestep_enabled
) {
8430 save_cpu_state(&ctx
, ctx
.bstate
== BS_NONE
);
8431 tcg_gen_helper_0_i(do_raise_exception
, EXCP_DEBUG
);
8433 switch (ctx
.bstate
) {
8435 tcg_gen_helper_0_0(do_interrupt_restart
);
8436 gen_goto_tb(&ctx
, 0, ctx
.pc
);
8439 save_cpu_state(&ctx
, 0);
8440 gen_goto_tb(&ctx
, 0, ctx
.pc
);
8443 tcg_gen_helper_0_0(do_interrupt_restart
);
8452 gen_icount_end(tb
, num_insns
);
8453 *gen_opc_ptr
= INDEX_op_end
;
8455 j
= gen_opc_ptr
- gen_opc_buf
;
8458 gen_opc_instr_start
[lj
++] = 0;
8460 tb
->size
= ctx
.pc
- pc_start
;
8461 tb
->icount
= num_insns
;
8464 #if defined MIPS_DEBUG_DISAS
8465 if (loglevel
& CPU_LOG_TB_IN_ASM
)
8466 fprintf(logfile
, "\n");
8468 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
8469 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
8470 target_disas(logfile
, pc_start
, ctx
.pc
- pc_start
, 0);
8471 fprintf(logfile
, "\n");
8473 if (loglevel
& CPU_LOG_TB_CPU
) {
8474 fprintf(logfile
, "---------------- %d %08x\n", ctx
.bstate
, ctx
.hflags
);
8479 void gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
8481 gen_intermediate_code_internal(env
, tb
, 0);
8484 void gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
8486 gen_intermediate_code_internal(env
, tb
, 1);
8489 static void fpu_dump_state(CPUState
*env
, FILE *f
,
8490 int (*fpu_fprintf
)(FILE *f
, const char *fmt
, ...),
8494 int is_fpu64
= !!(env
->hflags
& MIPS_HFLAG_F64
);
8496 #define printfpr(fp) \
8499 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu: %13g\n", \
8500 (fp)->w[FP_ENDIAN_IDX], (fp)->d, (fp)->fd, \
8501 (fp)->fs[FP_ENDIAN_IDX], (fp)->fs[!FP_ENDIAN_IDX]); \
8504 tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \
8505 tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \
8506 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu:%13g\n", \
8507 tmp.w[FP_ENDIAN_IDX], tmp.d, tmp.fd, \
8508 tmp.fs[FP_ENDIAN_IDX], tmp.fs[!FP_ENDIAN_IDX]); \
8513 fpu_fprintf(f
, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n",
8514 env
->active_fpu
.fcr0
, env
->active_fpu
.fcr31
, is_fpu64
, env
->active_fpu
.fp_status
,
8515 get_float_exception_flags(&env
->active_fpu
.fp_status
));
8516 for (i
= 0; i
< 32; (is_fpu64
) ? i
++ : (i
+= 2)) {
8517 fpu_fprintf(f
, "%3s: ", fregnames
[i
]);
8518 printfpr(&env
->active_fpu
.fpr
[i
]);
8524 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
8525 /* Debug help: The architecture requires 32bit code to maintain proper
8526 sign-extended values on 64bit machines. */
8528 #define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff))
8531 cpu_mips_check_sign_extensions (CPUState
*env
, FILE *f
,
8532 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
8537 if (!SIGN_EXT_P(env
->active_tc
.PC
))
8538 cpu_fprintf(f
, "BROKEN: pc=0x" TARGET_FMT_lx
"\n", env
->active_tc
.PC
);
8539 if (!SIGN_EXT_P(env
->active_tc
.HI
[0]))
8540 cpu_fprintf(f
, "BROKEN: HI=0x" TARGET_FMT_lx
"\n", env
->active_tc
.HI
[0]);
8541 if (!SIGN_EXT_P(env
->active_tc
.LO
[0]))
8542 cpu_fprintf(f
, "BROKEN: LO=0x" TARGET_FMT_lx
"\n", env
->active_tc
.LO
[0]);
8543 if (!SIGN_EXT_P(env
->btarget
))
8544 cpu_fprintf(f
, "BROKEN: btarget=0x" TARGET_FMT_lx
"\n", env
->btarget
);
8546 for (i
= 0; i
< 32; i
++) {
8547 if (!SIGN_EXT_P(env
->active_tc
.gpr
[i
]))
8548 cpu_fprintf(f
, "BROKEN: %s=0x" TARGET_FMT_lx
"\n", regnames
[i
], env
->active_tc
.gpr
[i
]);
8551 if (!SIGN_EXT_P(env
->CP0_EPC
))
8552 cpu_fprintf(f
, "BROKEN: EPC=0x" TARGET_FMT_lx
"\n", env
->CP0_EPC
);
8553 if (!SIGN_EXT_P(env
->CP0_LLAddr
))
8554 cpu_fprintf(f
, "BROKEN: LLAddr=0x" TARGET_FMT_lx
"\n", env
->CP0_LLAddr
);
8558 void cpu_dump_state (CPUState
*env
, FILE *f
,
8559 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
8564 cpu_fprintf(f
, "pc=0x" TARGET_FMT_lx
" HI=0x" TARGET_FMT_lx
" LO=0x" TARGET_FMT_lx
" ds %04x " TARGET_FMT_lx
" %d\n",
8565 env
->active_tc
.PC
, env
->active_tc
.HI
[0], env
->active_tc
.LO
[0],
8566 env
->hflags
, env
->btarget
, env
->bcond
);
8567 for (i
= 0; i
< 32; i
++) {
8569 cpu_fprintf(f
, "GPR%02d:", i
);
8570 cpu_fprintf(f
, " %s " TARGET_FMT_lx
, regnames
[i
], env
->active_tc
.gpr
[i
]);
8572 cpu_fprintf(f
, "\n");
8575 cpu_fprintf(f
, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx
"\n",
8576 env
->CP0_Status
, env
->CP0_Cause
, env
->CP0_EPC
);
8577 cpu_fprintf(f
, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx
"\n",
8578 env
->CP0_Config0
, env
->CP0_Config1
, env
->CP0_LLAddr
);
8579 if (env
->hflags
& MIPS_HFLAG_FPU
)
8580 fpu_dump_state(env
, f
, cpu_fprintf
, flags
);
8581 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
8582 cpu_mips_check_sign_extensions(env
, f
, cpu_fprintf
, flags
);
8586 static void mips_tcg_init(void)
8591 /* Initialize various static tables. */
8595 cpu_env
= tcg_global_reg_new(TCG_TYPE_PTR
, TCG_AREG0
, "env");
8596 for (i
= 0; i
< 32; i
++)
8597 cpu_gpr
[i
] = tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
8598 offsetof(CPUState
, active_tc
.gpr
[i
]),
8600 cpu_PC
= tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
8601 offsetof(CPUState
, active_tc
.PC
), "PC");
8602 for (i
= 0; i
< MIPS_DSP_ACC
; i
++) {
8603 cpu_HI
[i
] = tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
8604 offsetof(CPUState
, active_tc
.HI
[i
]),
8606 cpu_LO
[i
] = tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
8607 offsetof(CPUState
, active_tc
.LO
[i
]),
8609 cpu_ACX
[i
] = tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
8610 offsetof(CPUState
, active_tc
.ACX
[i
]),
8613 cpu_dspctrl
= tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
8614 offsetof(CPUState
, active_tc
.DSPControl
),
8616 bcond
= tcg_global_mem_new(TCG_TYPE_I32
, TCG_AREG0
,
8617 offsetof(CPUState
, bcond
), "bcond");
8618 btarget
= tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
8619 offsetof(CPUState
, btarget
), "btarget");
8620 for (i
= 0; i
< 32; i
++)
8621 fpu_fpr32
[i
] = tcg_global_mem_new(TCG_TYPE_I32
, TCG_AREG0
,
8622 offsetof(CPUState
, active_fpu
.fpr
[i
].w
[FP_ENDIAN_IDX
]),
8624 for (i
= 0; i
< 32; i
++)
8625 fpu_fpr64
[i
] = tcg_global_mem_new(TCG_TYPE_I64
, TCG_AREG0
,
8626 offsetof(CPUState
, active_fpu
.fpr
[i
]),
8628 for (i
= 0; i
< 32; i
++)
8629 fpu_fpr32h
[i
] = tcg_global_mem_new(TCG_TYPE_I32
, TCG_AREG0
,
8630 offsetof(CPUState
, active_fpu
.fpr
[i
].w
[!FP_ENDIAN_IDX
]),
8632 fpu_fcr0
= tcg_global_mem_new(TCG_TYPE_I32
, TCG_AREG0
,
8633 offsetof(CPUState
, active_fpu
.fcr0
),
8635 fpu_fcr31
= tcg_global_mem_new(TCG_TYPE_I32
, TCG_AREG0
,
8636 offsetof(CPUState
, active_fpu
.fcr31
),
8639 /* register helpers */
8641 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
8647 #include "translate_init.c"
8649 CPUMIPSState
*cpu_mips_init (const char *cpu_model
)
8652 const mips_def_t
*def
;
8654 def
= cpu_mips_find_by_name(cpu_model
);
8657 env
= qemu_mallocz(sizeof(CPUMIPSState
));
8660 env
->cpu_model
= def
;
8663 env
->cpu_model_str
= cpu_model
;
8669 void cpu_reset (CPUMIPSState
*env
)
8671 memset(env
, 0, offsetof(CPUMIPSState
, breakpoints
));
8676 #if defined(CONFIG_USER_ONLY)
8677 env
->user_mode_only
= 1;
8679 if (env
->user_mode_only
) {
8680 env
->hflags
= MIPS_HFLAG_UM
;
8682 if (env
->hflags
& MIPS_HFLAG_BMASK
) {
8683 /* If the exception was raised from a delay slot,
8684 come back to the jump. */
8685 env
->CP0_ErrorEPC
= env
->active_tc
.PC
- 4;
8687 env
->CP0_ErrorEPC
= env
->active_tc
.PC
;
8689 env
->active_tc
.PC
= (int32_t)0xBFC00000;
8691 /* SMP not implemented */
8692 env
->CP0_EBase
= 0x80000000;
8693 env
->CP0_Status
= (1 << CP0St_BEV
) | (1 << CP0St_ERL
);
8694 /* vectored interrupts not implemented, timer on int 7,
8695 no performance counters. */
8696 env
->CP0_IntCtl
= 0xe0000000;
8700 for (i
= 0; i
< 7; i
++) {
8701 env
->CP0_WatchLo
[i
] = 0;
8702 env
->CP0_WatchHi
[i
] = 0x80000000;
8704 env
->CP0_WatchLo
[7] = 0;
8705 env
->CP0_WatchHi
[7] = 0;
8707 /* Count register increments in debug mode, EJTAG version 1 */
8708 env
->CP0_Debug
= (1 << CP0DB_CNT
) | (0x1 << CP0DB_VER
);
8709 env
->hflags
= MIPS_HFLAG_CP0
;
8711 env
->exception_index
= EXCP_NONE
;
8712 cpu_mips_register(env
, env
->cpu_model
);
8715 void gen_pc_load(CPUState
*env
, TranslationBlock
*tb
,
8716 unsigned long searched_pc
, int pc_pos
, void *puc
)
8718 env
->active_tc
.PC
= gen_opc_pc
[pc_pos
];
8719 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
8720 env
->hflags
|= gen_opc_hflags
[pc_pos
];