]>
git.proxmox.com Git - mirror_qemu.git/blob - target-mips/translate.c
2 * MIPS32 emulation for qemu: main translation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 #include "qemu-common.h"
36 //#define MIPS_DEBUG_DISAS
37 //#define MIPS_DEBUG_SIGN_EXTENSIONS
38 //#define MIPS_SINGLE_STEP
40 /* MIPS major opcodes */
41 #define MASK_OP_MAJOR(op) (op & (0x3F << 26))
44 /* indirect opcode tables */
45 OPC_SPECIAL
= (0x00 << 26),
46 OPC_REGIMM
= (0x01 << 26),
47 OPC_CP0
= (0x10 << 26),
48 OPC_CP1
= (0x11 << 26),
49 OPC_CP2
= (0x12 << 26),
50 OPC_CP3
= (0x13 << 26),
51 OPC_SPECIAL2
= (0x1C << 26),
52 OPC_SPECIAL3
= (0x1F << 26),
53 /* arithmetic with immediate */
54 OPC_ADDI
= (0x08 << 26),
55 OPC_ADDIU
= (0x09 << 26),
56 OPC_SLTI
= (0x0A << 26),
57 OPC_SLTIU
= (0x0B << 26),
58 OPC_ANDI
= (0x0C << 26),
59 OPC_ORI
= (0x0D << 26),
60 OPC_XORI
= (0x0E << 26),
61 OPC_LUI
= (0x0F << 26),
62 OPC_DADDI
= (0x18 << 26),
63 OPC_DADDIU
= (0x19 << 26),
64 /* Jump and branches */
66 OPC_JAL
= (0x03 << 26),
67 OPC_BEQ
= (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
68 OPC_BEQL
= (0x14 << 26),
69 OPC_BNE
= (0x05 << 26),
70 OPC_BNEL
= (0x15 << 26),
71 OPC_BLEZ
= (0x06 << 26),
72 OPC_BLEZL
= (0x16 << 26),
73 OPC_BGTZ
= (0x07 << 26),
74 OPC_BGTZL
= (0x17 << 26),
75 OPC_JALX
= (0x1D << 26), /* MIPS 16 only */
77 OPC_LDL
= (0x1A << 26),
78 OPC_LDR
= (0x1B << 26),
79 OPC_LB
= (0x20 << 26),
80 OPC_LH
= (0x21 << 26),
81 OPC_LWL
= (0x22 << 26),
82 OPC_LW
= (0x23 << 26),
83 OPC_LBU
= (0x24 << 26),
84 OPC_LHU
= (0x25 << 26),
85 OPC_LWR
= (0x26 << 26),
86 OPC_LWU
= (0x27 << 26),
87 OPC_SB
= (0x28 << 26),
88 OPC_SH
= (0x29 << 26),
89 OPC_SWL
= (0x2A << 26),
90 OPC_SW
= (0x2B << 26),
91 OPC_SDL
= (0x2C << 26),
92 OPC_SDR
= (0x2D << 26),
93 OPC_SWR
= (0x2E << 26),
94 OPC_LL
= (0x30 << 26),
95 OPC_LLD
= (0x34 << 26),
96 OPC_LD
= (0x37 << 26),
97 OPC_SC
= (0x38 << 26),
98 OPC_SCD
= (0x3C << 26),
99 OPC_SD
= (0x3F << 26),
100 /* Floating point load/store */
101 OPC_LWC1
= (0x31 << 26),
102 OPC_LWC2
= (0x32 << 26),
103 OPC_LDC1
= (0x35 << 26),
104 OPC_LDC2
= (0x36 << 26),
105 OPC_SWC1
= (0x39 << 26),
106 OPC_SWC2
= (0x3A << 26),
107 OPC_SDC1
= (0x3D << 26),
108 OPC_SDC2
= (0x3E << 26),
109 /* MDMX ASE specific */
110 OPC_MDMX
= (0x1E << 26),
111 /* Cache and prefetch */
112 OPC_CACHE
= (0x2F << 26),
113 OPC_PREF
= (0x33 << 26),
114 /* Reserved major opcode */
115 OPC_MAJOR3B_RESERVED
= (0x3B << 26),
118 /* MIPS special opcodes */
119 #define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F)
123 OPC_SLL
= 0x00 | OPC_SPECIAL
,
124 /* NOP is SLL r0, r0, 0 */
125 /* SSNOP is SLL r0, r0, 1 */
126 /* EHB is SLL r0, r0, 3 */
127 OPC_SRL
= 0x02 | OPC_SPECIAL
, /* also ROTR */
128 OPC_SRA
= 0x03 | OPC_SPECIAL
,
129 OPC_SLLV
= 0x04 | OPC_SPECIAL
,
130 OPC_SRLV
= 0x06 | OPC_SPECIAL
, /* also ROTRV */
131 OPC_SRAV
= 0x07 | OPC_SPECIAL
,
132 OPC_DSLLV
= 0x14 | OPC_SPECIAL
,
133 OPC_DSRLV
= 0x16 | OPC_SPECIAL
, /* also DROTRV */
134 OPC_DSRAV
= 0x17 | OPC_SPECIAL
,
135 OPC_DSLL
= 0x38 | OPC_SPECIAL
,
136 OPC_DSRL
= 0x3A | OPC_SPECIAL
, /* also DROTR */
137 OPC_DSRA
= 0x3B | OPC_SPECIAL
,
138 OPC_DSLL32
= 0x3C | OPC_SPECIAL
,
139 OPC_DSRL32
= 0x3E | OPC_SPECIAL
, /* also DROTR32 */
140 OPC_DSRA32
= 0x3F | OPC_SPECIAL
,
141 /* Multiplication / division */
142 OPC_MULT
= 0x18 | OPC_SPECIAL
,
143 OPC_MULTU
= 0x19 | OPC_SPECIAL
,
144 OPC_DIV
= 0x1A | OPC_SPECIAL
,
145 OPC_DIVU
= 0x1B | OPC_SPECIAL
,
146 OPC_DMULT
= 0x1C | OPC_SPECIAL
,
147 OPC_DMULTU
= 0x1D | OPC_SPECIAL
,
148 OPC_DDIV
= 0x1E | OPC_SPECIAL
,
149 OPC_DDIVU
= 0x1F | OPC_SPECIAL
,
150 /* 2 registers arithmetic / logic */
151 OPC_ADD
= 0x20 | OPC_SPECIAL
,
152 OPC_ADDU
= 0x21 | OPC_SPECIAL
,
153 OPC_SUB
= 0x22 | OPC_SPECIAL
,
154 OPC_SUBU
= 0x23 | OPC_SPECIAL
,
155 OPC_AND
= 0x24 | OPC_SPECIAL
,
156 OPC_OR
= 0x25 | OPC_SPECIAL
,
157 OPC_XOR
= 0x26 | OPC_SPECIAL
,
158 OPC_NOR
= 0x27 | OPC_SPECIAL
,
159 OPC_SLT
= 0x2A | OPC_SPECIAL
,
160 OPC_SLTU
= 0x2B | OPC_SPECIAL
,
161 OPC_DADD
= 0x2C | OPC_SPECIAL
,
162 OPC_DADDU
= 0x2D | OPC_SPECIAL
,
163 OPC_DSUB
= 0x2E | OPC_SPECIAL
,
164 OPC_DSUBU
= 0x2F | OPC_SPECIAL
,
166 OPC_JR
= 0x08 | OPC_SPECIAL
, /* Also JR.HB */
167 OPC_JALR
= 0x09 | OPC_SPECIAL
, /* Also JALR.HB */
169 OPC_TGE
= 0x30 | OPC_SPECIAL
,
170 OPC_TGEU
= 0x31 | OPC_SPECIAL
,
171 OPC_TLT
= 0x32 | OPC_SPECIAL
,
172 OPC_TLTU
= 0x33 | OPC_SPECIAL
,
173 OPC_TEQ
= 0x34 | OPC_SPECIAL
,
174 OPC_TNE
= 0x36 | OPC_SPECIAL
,
175 /* HI / LO registers load & stores */
176 OPC_MFHI
= 0x10 | OPC_SPECIAL
,
177 OPC_MTHI
= 0x11 | OPC_SPECIAL
,
178 OPC_MFLO
= 0x12 | OPC_SPECIAL
,
179 OPC_MTLO
= 0x13 | OPC_SPECIAL
,
180 /* Conditional moves */
181 OPC_MOVZ
= 0x0A | OPC_SPECIAL
,
182 OPC_MOVN
= 0x0B | OPC_SPECIAL
,
184 OPC_MOVCI
= 0x01 | OPC_SPECIAL
,
187 OPC_PMON
= 0x05 | OPC_SPECIAL
, /* inofficial */
188 OPC_SYSCALL
= 0x0C | OPC_SPECIAL
,
189 OPC_BREAK
= 0x0D | OPC_SPECIAL
,
190 OPC_SPIM
= 0x0E | OPC_SPECIAL
, /* inofficial */
191 OPC_SYNC
= 0x0F | OPC_SPECIAL
,
193 OPC_SPECIAL15_RESERVED
= 0x15 | OPC_SPECIAL
,
194 OPC_SPECIAL28_RESERVED
= 0x28 | OPC_SPECIAL
,
195 OPC_SPECIAL29_RESERVED
= 0x29 | OPC_SPECIAL
,
196 OPC_SPECIAL35_RESERVED
= 0x35 | OPC_SPECIAL
,
197 OPC_SPECIAL37_RESERVED
= 0x37 | OPC_SPECIAL
,
198 OPC_SPECIAL39_RESERVED
= 0x39 | OPC_SPECIAL
,
199 OPC_SPECIAL3D_RESERVED
= 0x3D | OPC_SPECIAL
,
202 /* Multiplication variants of the vr54xx. */
203 #define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6))
206 OPC_VR54XX_MULS
= (0x03 << 6) | OPC_MULT
,
207 OPC_VR54XX_MULSU
= (0x03 << 6) | OPC_MULTU
,
208 OPC_VR54XX_MACC
= (0x05 << 6) | OPC_MULT
,
209 OPC_VR54XX_MACCU
= (0x05 << 6) | OPC_MULTU
,
210 OPC_VR54XX_MSAC
= (0x07 << 6) | OPC_MULT
,
211 OPC_VR54XX_MSACU
= (0x07 << 6) | OPC_MULTU
,
212 OPC_VR54XX_MULHI
= (0x09 << 6) | OPC_MULT
,
213 OPC_VR54XX_MULHIU
= (0x09 << 6) | OPC_MULTU
,
214 OPC_VR54XX_MULSHI
= (0x0B << 6) | OPC_MULT
,
215 OPC_VR54XX_MULSHIU
= (0x0B << 6) | OPC_MULTU
,
216 OPC_VR54XX_MACCHI
= (0x0D << 6) | OPC_MULT
,
217 OPC_VR54XX_MACCHIU
= (0x0D << 6) | OPC_MULTU
,
218 OPC_VR54XX_MSACHI
= (0x0F << 6) | OPC_MULT
,
219 OPC_VR54XX_MSACHIU
= (0x0F << 6) | OPC_MULTU
,
222 /* REGIMM (rt field) opcodes */
223 #define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
226 OPC_BLTZ
= (0x00 << 16) | OPC_REGIMM
,
227 OPC_BLTZL
= (0x02 << 16) | OPC_REGIMM
,
228 OPC_BGEZ
= (0x01 << 16) | OPC_REGIMM
,
229 OPC_BGEZL
= (0x03 << 16) | OPC_REGIMM
,
230 OPC_BLTZAL
= (0x10 << 16) | OPC_REGIMM
,
231 OPC_BLTZALL
= (0x12 << 16) | OPC_REGIMM
,
232 OPC_BGEZAL
= (0x11 << 16) | OPC_REGIMM
,
233 OPC_BGEZALL
= (0x13 << 16) | OPC_REGIMM
,
234 OPC_TGEI
= (0x08 << 16) | OPC_REGIMM
,
235 OPC_TGEIU
= (0x09 << 16) | OPC_REGIMM
,
236 OPC_TLTI
= (0x0A << 16) | OPC_REGIMM
,
237 OPC_TLTIU
= (0x0B << 16) | OPC_REGIMM
,
238 OPC_TEQI
= (0x0C << 16) | OPC_REGIMM
,
239 OPC_TNEI
= (0x0E << 16) | OPC_REGIMM
,
240 OPC_SYNCI
= (0x1F << 16) | OPC_REGIMM
,
243 /* Special2 opcodes */
244 #define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F)
247 /* Multiply & xxx operations */
248 OPC_MADD
= 0x00 | OPC_SPECIAL2
,
249 OPC_MADDU
= 0x01 | OPC_SPECIAL2
,
250 OPC_MUL
= 0x02 | OPC_SPECIAL2
,
251 OPC_MSUB
= 0x04 | OPC_SPECIAL2
,
252 OPC_MSUBU
= 0x05 | OPC_SPECIAL2
,
254 OPC_CLZ
= 0x20 | OPC_SPECIAL2
,
255 OPC_CLO
= 0x21 | OPC_SPECIAL2
,
256 OPC_DCLZ
= 0x24 | OPC_SPECIAL2
,
257 OPC_DCLO
= 0x25 | OPC_SPECIAL2
,
259 OPC_SDBBP
= 0x3F | OPC_SPECIAL2
,
262 /* Special3 opcodes */
263 #define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
266 OPC_EXT
= 0x00 | OPC_SPECIAL3
,
267 OPC_DEXTM
= 0x01 | OPC_SPECIAL3
,
268 OPC_DEXTU
= 0x02 | OPC_SPECIAL3
,
269 OPC_DEXT
= 0x03 | OPC_SPECIAL3
,
270 OPC_INS
= 0x04 | OPC_SPECIAL3
,
271 OPC_DINSM
= 0x05 | OPC_SPECIAL3
,
272 OPC_DINSU
= 0x06 | OPC_SPECIAL3
,
273 OPC_DINS
= 0x07 | OPC_SPECIAL3
,
274 OPC_FORK
= 0x08 | OPC_SPECIAL3
,
275 OPC_YIELD
= 0x09 | OPC_SPECIAL3
,
276 OPC_BSHFL
= 0x20 | OPC_SPECIAL3
,
277 OPC_DBSHFL
= 0x24 | OPC_SPECIAL3
,
278 OPC_RDHWR
= 0x3B | OPC_SPECIAL3
,
282 #define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
285 OPC_WSBH
= (0x02 << 6) | OPC_BSHFL
,
286 OPC_SEB
= (0x10 << 6) | OPC_BSHFL
,
287 OPC_SEH
= (0x18 << 6) | OPC_BSHFL
,
291 #define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
294 OPC_DSBH
= (0x02 << 6) | OPC_DBSHFL
,
295 OPC_DSHD
= (0x05 << 6) | OPC_DBSHFL
,
298 /* Coprocessor 0 (rs field) */
299 #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
302 OPC_MFC0
= (0x00 << 21) | OPC_CP0
,
303 OPC_DMFC0
= (0x01 << 21) | OPC_CP0
,
304 OPC_MTC0
= (0x04 << 21) | OPC_CP0
,
305 OPC_DMTC0
= (0x05 << 21) | OPC_CP0
,
306 OPC_MFTR
= (0x08 << 21) | OPC_CP0
,
307 OPC_RDPGPR
= (0x0A << 21) | OPC_CP0
,
308 OPC_MFMC0
= (0x0B << 21) | OPC_CP0
,
309 OPC_MTTR
= (0x0C << 21) | OPC_CP0
,
310 OPC_WRPGPR
= (0x0E << 21) | OPC_CP0
,
311 OPC_C0
= (0x10 << 21) | OPC_CP0
,
312 OPC_C0_FIRST
= (0x10 << 21) | OPC_CP0
,
313 OPC_C0_LAST
= (0x1F << 21) | OPC_CP0
,
317 #define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
320 OPC_DMT
= 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
321 OPC_EMT
= 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
322 OPC_DVPE
= 0x01 | (0 << 5) | OPC_MFMC0
,
323 OPC_EVPE
= 0x01 | (1 << 5) | OPC_MFMC0
,
324 OPC_DI
= (0 << 5) | (0x0C << 11) | OPC_MFMC0
,
325 OPC_EI
= (1 << 5) | (0x0C << 11) | OPC_MFMC0
,
328 /* Coprocessor 0 (with rs == C0) */
329 #define MASK_C0(op) MASK_CP0(op) | (op & 0x3F)
332 OPC_TLBR
= 0x01 | OPC_C0
,
333 OPC_TLBWI
= 0x02 | OPC_C0
,
334 OPC_TLBWR
= 0x06 | OPC_C0
,
335 OPC_TLBP
= 0x08 | OPC_C0
,
336 OPC_RFE
= 0x10 | OPC_C0
,
337 OPC_ERET
= 0x18 | OPC_C0
,
338 OPC_DERET
= 0x1F | OPC_C0
,
339 OPC_WAIT
= 0x20 | OPC_C0
,
342 /* Coprocessor 1 (rs field) */
343 #define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
346 OPC_MFC1
= (0x00 << 21) | OPC_CP1
,
347 OPC_DMFC1
= (0x01 << 21) | OPC_CP1
,
348 OPC_CFC1
= (0x02 << 21) | OPC_CP1
,
349 OPC_MFHC1
= (0x03 << 21) | OPC_CP1
,
350 OPC_MTC1
= (0x04 << 21) | OPC_CP1
,
351 OPC_DMTC1
= (0x05 << 21) | OPC_CP1
,
352 OPC_CTC1
= (0x06 << 21) | OPC_CP1
,
353 OPC_MTHC1
= (0x07 << 21) | OPC_CP1
,
354 OPC_BC1
= (0x08 << 21) | OPC_CP1
, /* bc */
355 OPC_BC1ANY2
= (0x09 << 21) | OPC_CP1
,
356 OPC_BC1ANY4
= (0x0A << 21) | OPC_CP1
,
357 OPC_S_FMT
= (0x10 << 21) | OPC_CP1
, /* 16: fmt=single fp */
358 OPC_D_FMT
= (0x11 << 21) | OPC_CP1
, /* 17: fmt=double fp */
359 OPC_E_FMT
= (0x12 << 21) | OPC_CP1
, /* 18: fmt=extended fp */
360 OPC_Q_FMT
= (0x13 << 21) | OPC_CP1
, /* 19: fmt=quad fp */
361 OPC_W_FMT
= (0x14 << 21) | OPC_CP1
, /* 20: fmt=32bit fixed */
362 OPC_L_FMT
= (0x15 << 21) | OPC_CP1
, /* 21: fmt=64bit fixed */
363 OPC_PS_FMT
= (0x16 << 21) | OPC_CP1
, /* 22: fmt=paired single fp */
366 #define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
367 #define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16))
370 OPC_BC1F
= (0x00 << 16) | OPC_BC1
,
371 OPC_BC1T
= (0x01 << 16) | OPC_BC1
,
372 OPC_BC1FL
= (0x02 << 16) | OPC_BC1
,
373 OPC_BC1TL
= (0x03 << 16) | OPC_BC1
,
377 OPC_BC1FANY2
= (0x00 << 16) | OPC_BC1ANY2
,
378 OPC_BC1TANY2
= (0x01 << 16) | OPC_BC1ANY2
,
382 OPC_BC1FANY4
= (0x00 << 16) | OPC_BC1ANY4
,
383 OPC_BC1TANY4
= (0x01 << 16) | OPC_BC1ANY4
,
386 #define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
389 OPC_MFC2
= (0x00 << 21) | OPC_CP2
,
390 OPC_DMFC2
= (0x01 << 21) | OPC_CP2
,
391 OPC_CFC2
= (0x02 << 21) | OPC_CP2
,
392 OPC_MFHC2
= (0x03 << 21) | OPC_CP2
,
393 OPC_MTC2
= (0x04 << 21) | OPC_CP2
,
394 OPC_DMTC2
= (0x05 << 21) | OPC_CP2
,
395 OPC_CTC2
= (0x06 << 21) | OPC_CP2
,
396 OPC_MTHC2
= (0x07 << 21) | OPC_CP2
,
397 OPC_BC2
= (0x08 << 21) | OPC_CP2
,
400 #define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
403 OPC_LWXC1
= 0x00 | OPC_CP3
,
404 OPC_LDXC1
= 0x01 | OPC_CP3
,
405 OPC_LUXC1
= 0x05 | OPC_CP3
,
406 OPC_SWXC1
= 0x08 | OPC_CP3
,
407 OPC_SDXC1
= 0x09 | OPC_CP3
,
408 OPC_SUXC1
= 0x0D | OPC_CP3
,
409 OPC_PREFX
= 0x0F | OPC_CP3
,
410 OPC_ALNV_PS
= 0x1E | OPC_CP3
,
411 OPC_MADD_S
= 0x20 | OPC_CP3
,
412 OPC_MADD_D
= 0x21 | OPC_CP3
,
413 OPC_MADD_PS
= 0x26 | OPC_CP3
,
414 OPC_MSUB_S
= 0x28 | OPC_CP3
,
415 OPC_MSUB_D
= 0x29 | OPC_CP3
,
416 OPC_MSUB_PS
= 0x2E | OPC_CP3
,
417 OPC_NMADD_S
= 0x30 | OPC_CP3
,
418 OPC_NMADD_D
= 0x31 | OPC_CP3
,
419 OPC_NMADD_PS
= 0x36 | OPC_CP3
,
420 OPC_NMSUB_S
= 0x38 | OPC_CP3
,
421 OPC_NMSUB_D
= 0x39 | OPC_CP3
,
422 OPC_NMSUB_PS
= 0x3E | OPC_CP3
,
425 /* global register indices */
426 static TCGv cpu_env
, bcond
, btarget
, current_fpu
;
428 /* FPU TNs, global for now. */
429 static TCGv fpu32_T
[3], fpu64_T
[3], fpu32h_T
[3];
431 #include "gen-icount.h"
433 static inline void tcg_gen_helper_0_i(void *func
, TCGv arg
)
435 TCGv tmp
= tcg_const_i32(arg
);
437 tcg_gen_helper_0_1(func
, tmp
);
441 static inline void tcg_gen_helper_0_ii(void *func
, TCGv arg1
, TCGv arg2
)
443 TCGv tmp1
= tcg_const_i32(arg1
);
444 TCGv tmp2
= tcg_const_i32(arg2
);
446 tcg_gen_helper_0_2(func
, tmp1
, tmp2
);
451 static inline void tcg_gen_helper_0_1i(void *func
, TCGv arg1
, TCGv arg2
)
453 TCGv tmp
= tcg_const_i32(arg2
);
455 tcg_gen_helper_0_2(func
, arg1
, tmp
);
459 static inline void tcg_gen_helper_0_2i(void *func
, TCGv arg1
, TCGv arg2
, TCGv arg3
)
461 TCGv tmp
= tcg_const_i32(arg3
);
463 tcg_gen_helper_0_3(func
, arg1
, arg2
, tmp
);
467 static inline void tcg_gen_helper_0_1ii(void *func
, TCGv arg1
, TCGv arg2
, TCGv arg3
)
469 TCGv tmp1
= tcg_const_i32(arg2
);
470 TCGv tmp2
= tcg_const_i32(arg3
);
472 tcg_gen_helper_0_3(func
, arg1
, tmp1
, tmp2
);
477 static inline void tcg_gen_helper_1_i(void *func
, TCGv ret
, TCGv arg
)
479 TCGv tmp
= tcg_const_i32(arg
);
481 tcg_gen_helper_1_1(func
, ret
, tmp
);
485 static inline void tcg_gen_helper_1_1i(void *func
, TCGv ret
, TCGv arg1
, TCGv arg2
)
487 TCGv tmp
= tcg_const_i32(arg2
);
489 tcg_gen_helper_1_2(func
, ret
, arg1
, tmp
);
493 static inline void tcg_gen_helper_1_1ii(void *func
, TCGv ret
, TCGv arg1
, TCGv arg2
, TCGv arg3
)
495 TCGv tmp1
= tcg_const_i32(arg2
);
496 TCGv tmp2
= tcg_const_i32(arg3
);
498 tcg_gen_helper_1_3(func
, ret
, arg1
, tmp1
, tmp2
);
503 static inline void tcg_gen_helper_1_2i(void *func
, TCGv ret
, TCGv arg1
, TCGv arg2
, TCGv arg3
)
505 TCGv tmp
= tcg_const_i32(arg3
);
507 tcg_gen_helper_1_3(func
, ret
, arg1
, arg2
, tmp
);
511 static inline void tcg_gen_helper_1_2ii(void *func
, TCGv ret
, TCGv arg1
, TCGv arg2
, TCGv arg3
, TCGv arg4
)
513 TCGv tmp1
= tcg_const_i32(arg3
);
514 TCGv tmp2
= tcg_const_i32(arg4
);
516 tcg_gen_helper_1_4(func
, ret
, arg1
, arg2
, tmp1
, tmp2
);
521 typedef struct DisasContext
{
522 struct TranslationBlock
*tb
;
523 target_ulong pc
, saved_pc
;
526 /* Routine used to access memory */
528 uint32_t hflags
, saved_hflags
;
530 target_ulong btarget
;
534 BS_NONE
= 0, /* We go out of the TB without reaching a branch or an
535 * exception condition */
536 BS_STOP
= 1, /* We want to stop translation for any reason */
537 BS_BRANCH
= 2, /* We reached a branch condition */
538 BS_EXCP
= 3, /* We reached an exception condition */
541 static const char *regnames
[] =
542 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
543 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
544 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
545 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
547 static const char *fregnames
[] =
548 { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
549 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
550 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
551 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
553 #ifdef MIPS_DEBUG_DISAS
554 #define MIPS_DEBUG(fmt, args...) \
556 if (loglevel & CPU_LOG_TB_IN_ASM) { \
557 fprintf(logfile, TARGET_FMT_lx ": %08x " fmt "\n", \
558 ctx->pc, ctx->opcode , ##args); \
562 #define MIPS_DEBUG(fmt, args...) do { } while(0)
565 #define MIPS_INVAL(op) \
567 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
568 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
571 /* General purpose registers moves. */
572 static inline void gen_load_gpr (TCGv t
, int reg
)
575 tcg_gen_movi_tl(t
, 0);
577 tcg_gen_ld_tl(t
, cpu_env
, offsetof(CPUState
, active_tc
.gpr
) +
578 sizeof(target_ulong
) * reg
);
581 static inline void gen_store_gpr (TCGv t
, int reg
)
584 tcg_gen_st_tl(t
, cpu_env
, offsetof(CPUState
, active_tc
.gpr
) +
585 sizeof(target_ulong
) * reg
);
588 /* Moves to/from HI and LO registers. */
589 static inline void gen_load_LO (TCGv t
, int reg
)
591 tcg_gen_ld_tl(t
, cpu_env
, offsetof(CPUState
, active_tc
.LO
) +
592 sizeof(target_ulong
) * reg
);
595 static inline void gen_store_LO (TCGv t
, int reg
)
597 tcg_gen_st_tl(t
, cpu_env
, offsetof(CPUState
, active_tc
.LO
) +
598 sizeof(target_ulong
) * reg
);
601 static inline void gen_load_HI (TCGv t
, int reg
)
603 tcg_gen_ld_tl(t
, cpu_env
, offsetof(CPUState
, active_tc
.HI
) +
604 sizeof(target_ulong
) * reg
);
607 static inline void gen_store_HI (TCGv t
, int reg
)
609 tcg_gen_st_tl(t
, cpu_env
, offsetof(CPUState
, active_tc
.HI
) +
610 sizeof(target_ulong
) * reg
);
613 /* Moves to/from shadow registers. */
614 static inline void gen_load_srsgpr (int from
, int to
)
616 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_TL
);
619 tcg_gen_movi_tl(r_tmp1
, 0);
621 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I32
);
623 tcg_gen_ld_i32(r_tmp2
, cpu_env
, offsetof(CPUState
, CP0_SRSCtl
));
624 tcg_gen_shri_i32(r_tmp2
, r_tmp2
, CP0SRSCtl_PSS
);
625 tcg_gen_andi_i32(r_tmp2
, r_tmp2
, 0xf);
626 tcg_gen_muli_i32(r_tmp2
, r_tmp2
, sizeof(target_ulong
) * 32);
627 tcg_gen_add_i32(r_tmp2
, cpu_env
, r_tmp2
);
629 tcg_gen_ld_tl(r_tmp1
, r_tmp2
, sizeof(target_ulong
) * from
);
630 tcg_temp_free(r_tmp2
);
632 gen_store_gpr(r_tmp1
, to
);
633 tcg_temp_free(r_tmp1
);
636 static inline void gen_store_srsgpr (int from
, int to
)
639 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_TL
);
640 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I32
);
642 gen_load_gpr(r_tmp1
, from
);
643 tcg_gen_ld_i32(r_tmp2
, cpu_env
, offsetof(CPUState
, CP0_SRSCtl
));
644 tcg_gen_shri_i32(r_tmp2
, r_tmp2
, CP0SRSCtl_PSS
);
645 tcg_gen_andi_i32(r_tmp2
, r_tmp2
, 0xf);
646 tcg_gen_muli_i32(r_tmp2
, r_tmp2
, sizeof(target_ulong
) * 32);
647 tcg_gen_add_i32(r_tmp2
, cpu_env
, r_tmp2
);
649 tcg_gen_st_tl(r_tmp1
, r_tmp2
, sizeof(target_ulong
) * to
);
650 tcg_temp_free(r_tmp1
);
651 tcg_temp_free(r_tmp2
);
655 /* Floating point register moves. */
656 static inline void gen_load_fpr32 (TCGv t
, int reg
)
658 tcg_gen_ld_i32(t
, current_fpu
, 8 * reg
+ 4 * FP_ENDIAN_IDX
);
661 static inline void gen_store_fpr32 (TCGv t
, int reg
)
663 tcg_gen_st_i32(t
, current_fpu
, 8 * reg
+ 4 * FP_ENDIAN_IDX
);
666 static inline void gen_load_fpr64 (DisasContext
*ctx
, TCGv t
, int reg
)
668 if (ctx
->hflags
& MIPS_HFLAG_F64
) {
669 tcg_gen_ld_i64(t
, current_fpu
, 8 * reg
);
671 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
672 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I64
);
674 tcg_gen_ld_i32(r_tmp1
, current_fpu
, 8 * (reg
| 1) + 4 * FP_ENDIAN_IDX
);
675 tcg_gen_extu_i32_i64(t
, r_tmp1
);
676 tcg_gen_shli_i64(t
, t
, 32);
677 tcg_gen_ld_i32(r_tmp1
, current_fpu
, 8 * (reg
& ~1) + 4 * FP_ENDIAN_IDX
);
678 tcg_gen_extu_i32_i64(r_tmp2
, r_tmp1
);
679 tcg_gen_or_i64(t
, t
, r_tmp2
);
680 tcg_temp_free(r_tmp1
);
681 tcg_temp_free(r_tmp2
);
685 static inline void gen_store_fpr64 (DisasContext
*ctx
, TCGv t
, int reg
)
687 if (ctx
->hflags
& MIPS_HFLAG_F64
) {
688 tcg_gen_st_i64(t
, current_fpu
, 8 * reg
);
690 TCGv r_tmp
= tcg_temp_new(TCG_TYPE_I32
);
692 tcg_gen_trunc_i64_i32(r_tmp
, t
);
693 tcg_gen_st_i32(r_tmp
, current_fpu
, 8 * (reg
& ~1) + 4 * FP_ENDIAN_IDX
);
694 tcg_gen_shri_i64(t
, t
, 32);
695 tcg_gen_trunc_i64_i32(r_tmp
, t
);
696 tcg_gen_st_i32(r_tmp
, current_fpu
, 8 * (reg
| 1) + 4 * FP_ENDIAN_IDX
);
697 tcg_temp_free(r_tmp
);
701 static inline void gen_load_fpr32h (TCGv t
, int reg
)
703 tcg_gen_ld_i32(t
, current_fpu
, 8 * reg
+ 4 * !FP_ENDIAN_IDX
);
706 static inline void gen_store_fpr32h (TCGv t
, int reg
)
708 tcg_gen_st_i32(t
, current_fpu
, 8 * reg
+ 4 * !FP_ENDIAN_IDX
);
711 static inline void get_fp_cond (TCGv t
)
713 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
714 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I32
);
716 tcg_gen_ld_i32(r_tmp1
, current_fpu
, offsetof(CPUMIPSFPUContext
, fcr31
));
717 tcg_gen_shri_i32(r_tmp2
, r_tmp1
, 24);
718 tcg_gen_andi_i32(r_tmp2
, r_tmp2
, 0xfe);
719 tcg_gen_shri_i32(r_tmp1
, r_tmp1
, 23);
720 tcg_gen_andi_i32(r_tmp1
, r_tmp1
, 0x1);
721 tcg_gen_or_i32(t
, r_tmp1
, r_tmp2
);
722 tcg_temp_free(r_tmp1
);
723 tcg_temp_free(r_tmp2
);
726 #define FOP_CONDS(type, fmt) \
727 static GenOpFunc1 * fcmp ## type ## _ ## fmt ## _table[16] = { \
728 do_cmp ## type ## _ ## fmt ## _f, \
729 do_cmp ## type ## _ ## fmt ## _un, \
730 do_cmp ## type ## _ ## fmt ## _eq, \
731 do_cmp ## type ## _ ## fmt ## _ueq, \
732 do_cmp ## type ## _ ## fmt ## _olt, \
733 do_cmp ## type ## _ ## fmt ## _ult, \
734 do_cmp ## type ## _ ## fmt ## _ole, \
735 do_cmp ## type ## _ ## fmt ## _ule, \
736 do_cmp ## type ## _ ## fmt ## _sf, \
737 do_cmp ## type ## _ ## fmt ## _ngle, \
738 do_cmp ## type ## _ ## fmt ## _seq, \
739 do_cmp ## type ## _ ## fmt ## _ngl, \
740 do_cmp ## type ## _ ## fmt ## _lt, \
741 do_cmp ## type ## _ ## fmt ## _nge, \
742 do_cmp ## type ## _ ## fmt ## _le, \
743 do_cmp ## type ## _ ## fmt ## _ngt, \
745 static inline void gen_cmp ## type ## _ ## fmt(int n, long cc) \
747 tcg_gen_helper_0_i(fcmp ## type ## _ ## fmt ## _table[n], cc); \
759 #define OP_COND(name, cond) \
760 void glue(gen_op_, name) (TCGv t0, TCGv t1) \
762 int l1 = gen_new_label(); \
763 int l2 = gen_new_label(); \
765 tcg_gen_brcond_tl(cond, t0, t1, l1); \
766 tcg_gen_movi_tl(t0, 0); \
769 tcg_gen_movi_tl(t0, 1); \
772 OP_COND(eq
, TCG_COND_EQ
);
773 OP_COND(ne
, TCG_COND_NE
);
774 OP_COND(ge
, TCG_COND_GE
);
775 OP_COND(geu
, TCG_COND_GEU
);
776 OP_COND(lt
, TCG_COND_LT
);
777 OP_COND(ltu
, TCG_COND_LTU
);
780 #define OP_CONDI(name, cond) \
781 void glue(gen_op_, name) (TCGv t, target_ulong val) \
783 int l1 = gen_new_label(); \
784 int l2 = gen_new_label(); \
786 tcg_gen_brcondi_tl(cond, t, val, l1); \
787 tcg_gen_movi_tl(t, 0); \
790 tcg_gen_movi_tl(t, 1); \
793 OP_CONDI(lti
, TCG_COND_LT
);
794 OP_CONDI(ltiu
, TCG_COND_LTU
);
797 #define OP_CONDZ(name, cond) \
798 void glue(gen_op_, name) (TCGv t) \
800 int l1 = gen_new_label(); \
801 int l2 = gen_new_label(); \
803 tcg_gen_brcondi_tl(cond, t, 0, l1); \
804 tcg_gen_movi_tl(t, 0); \
807 tcg_gen_movi_tl(t, 1); \
810 OP_CONDZ(gez
, TCG_COND_GE
);
811 OP_CONDZ(gtz
, TCG_COND_GT
);
812 OP_CONDZ(lez
, TCG_COND_LE
);
813 OP_CONDZ(ltz
, TCG_COND_LT
);
816 static inline void gen_save_pc(target_ulong pc
)
818 TCGv r_tmp
= tcg_temp_new(TCG_TYPE_TL
);
820 tcg_gen_movi_tl(r_tmp
, pc
);
821 tcg_gen_st_tl(r_tmp
, cpu_env
, offsetof(CPUState
, active_tc
.PC
));
822 tcg_temp_free(r_tmp
);
825 static always_inline
void save_cpu_state (DisasContext
*ctx
, int do_save_pc
)
827 #if defined MIPS_DEBUG_DISAS
828 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
829 fprintf(logfile
, "hflags %08x saved %08x\n",
830 ctx
->hflags
, ctx
->saved_hflags
);
833 if (do_save_pc
&& ctx
->pc
!= ctx
->saved_pc
) {
834 gen_save_pc(ctx
->pc
);
835 ctx
->saved_pc
= ctx
->pc
;
837 if (ctx
->hflags
!= ctx
->saved_hflags
) {
838 TCGv r_tmp
= tcg_temp_new(TCG_TYPE_I32
);
840 tcg_gen_movi_i32(r_tmp
, ctx
->hflags
);
841 tcg_gen_st_i32(r_tmp
, cpu_env
, offsetof(CPUState
, hflags
));
842 tcg_temp_free(r_tmp
);
843 ctx
->saved_hflags
= ctx
->hflags
;
844 switch (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
850 tcg_gen_movi_tl(btarget
, ctx
->btarget
);
856 static always_inline
void restore_cpu_state (CPUState
*env
, DisasContext
*ctx
)
858 ctx
->saved_hflags
= ctx
->hflags
;
859 switch (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
865 ctx
->btarget
= env
->btarget
;
870 static always_inline
void
871 generate_exception_err (DisasContext
*ctx
, int excp
, int err
)
873 save_cpu_state(ctx
, 1);
874 tcg_gen_helper_0_ii(do_raise_exception_err
, excp
, err
);
875 tcg_gen_helper_0_0(do_interrupt_restart
);
879 static always_inline
void
880 generate_exception (DisasContext
*ctx
, int excp
)
882 save_cpu_state(ctx
, 1);
883 tcg_gen_helper_0_i(do_raise_exception
, excp
);
884 tcg_gen_helper_0_0(do_interrupt_restart
);
888 /* Addresses computation */
889 static inline void gen_op_addr_add (TCGv t0
, TCGv t1
)
891 tcg_gen_add_tl(t0
, t0
, t1
);
893 #if defined(TARGET_MIPS64)
894 /* For compatibility with 32-bit code, data reference in user mode
895 with Status_UX = 0 should be casted to 32-bit and sign extended.
896 See the MIPS64 PRA manual, section 4.10. */
898 int l1
= gen_new_label();
899 TCGv r_tmp
= tcg_temp_local_new(TCG_TYPE_I32
);
901 tcg_gen_ld_i32(r_tmp
, cpu_env
, offsetof(CPUState
, hflags
));
902 tcg_gen_andi_i32(r_tmp
, r_tmp
, MIPS_HFLAG_KSU
);
903 tcg_gen_brcondi_i32(TCG_COND_NE
, r_tmp
, MIPS_HFLAG_UM
, l1
);
904 tcg_gen_ld_i32(r_tmp
, cpu_env
, offsetof(CPUState
, CP0_Status
));
905 tcg_gen_andi_i32(r_tmp
, r_tmp
, (1 << CP0St_UX
));
906 tcg_gen_brcondi_i32(TCG_COND_NE
, r_tmp
, 0, l1
);
907 tcg_temp_free(r_tmp
);
908 tcg_gen_ext32s_i64(t0
, t0
);
914 static always_inline
void check_cp0_enabled(DisasContext
*ctx
)
916 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_CP0
)))
917 generate_exception_err(ctx
, EXCP_CpU
, 1);
920 static always_inline
void check_cp1_enabled(DisasContext
*ctx
)
922 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_FPU
)))
923 generate_exception_err(ctx
, EXCP_CpU
, 1);
926 /* Verify that the processor is running with COP1X instructions enabled.
927 This is associated with the nabla symbol in the MIPS32 and MIPS64
930 static always_inline
void check_cop1x(DisasContext
*ctx
)
932 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_COP1X
)))
933 generate_exception(ctx
, EXCP_RI
);
936 /* Verify that the processor is running with 64-bit floating-point
937 operations enabled. */
939 static always_inline
void check_cp1_64bitmode(DisasContext
*ctx
)
941 if (unlikely(~ctx
->hflags
& (MIPS_HFLAG_F64
| MIPS_HFLAG_COP1X
)))
942 generate_exception(ctx
, EXCP_RI
);
946 * Verify if floating point register is valid; an operation is not defined
947 * if bit 0 of any register specification is set and the FR bit in the
948 * Status register equals zero, since the register numbers specify an
949 * even-odd pair of adjacent coprocessor general registers. When the FR bit
950 * in the Status register equals one, both even and odd register numbers
951 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
953 * Multiple 64 bit wide registers can be checked by calling
954 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
956 void check_cp1_registers(DisasContext
*ctx
, int regs
)
958 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_F64
) && (regs
& 1)))
959 generate_exception(ctx
, EXCP_RI
);
962 /* This code generates a "reserved instruction" exception if the
963 CPU does not support the instruction set corresponding to flags. */
964 static always_inline
void check_insn(CPUState
*env
, DisasContext
*ctx
, int flags
)
966 if (unlikely(!(env
->insn_flags
& flags
)))
967 generate_exception(ctx
, EXCP_RI
);
970 /* This code generates a "reserved instruction" exception if 64-bit
971 instructions are not enabled. */
972 static always_inline
void check_mips_64(DisasContext
*ctx
)
974 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_64
)))
975 generate_exception(ctx
, EXCP_RI
);
978 /* load/store instructions. */
979 #define OP_LD(insn,fname) \
980 void inline op_ldst_##insn(TCGv t0, DisasContext *ctx) \
982 tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx); \
989 #if defined(TARGET_MIPS64)
995 #define OP_ST(insn,fname) \
996 void inline op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
998 tcg_gen_qemu_##fname(t1, t0, ctx->mem_idx); \
1003 #if defined(TARGET_MIPS64)
1008 #define OP_LD_ATOMIC(insn,fname) \
1009 void inline op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
1011 tcg_gen_mov_tl(t1, t0); \
1012 tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx); \
1013 tcg_gen_st_tl(t1, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
1015 OP_LD_ATOMIC(ll
,ld32s
);
1016 #if defined(TARGET_MIPS64)
1017 OP_LD_ATOMIC(lld
,ld64
);
1021 #define OP_ST_ATOMIC(insn,fname,almask) \
1022 void inline op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
1024 TCGv r_tmp = tcg_temp_local_new(TCG_TYPE_TL); \
1025 int l1 = gen_new_label(); \
1026 int l2 = gen_new_label(); \
1027 int l3 = gen_new_label(); \
1029 tcg_gen_andi_tl(r_tmp, t0, almask); \
1030 tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp, 0, l1); \
1031 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
1032 generate_exception(ctx, EXCP_AdES); \
1033 gen_set_label(l1); \
1034 tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
1035 tcg_gen_brcond_tl(TCG_COND_NE, t0, r_tmp, l2); \
1036 tcg_temp_free(r_tmp); \
1037 tcg_gen_qemu_##fname(t1, t0, ctx->mem_idx); \
1038 tcg_gen_movi_tl(t0, 1); \
1040 gen_set_label(l2); \
1041 tcg_gen_movi_tl(t0, 0); \
1042 gen_set_label(l3); \
1044 OP_ST_ATOMIC(sc
,st32
,0x3);
1045 #if defined(TARGET_MIPS64)
1046 OP_ST_ATOMIC(scd
,st64
,0x7);
1050 /* Load and store */
1051 static void gen_ldst (DisasContext
*ctx
, uint32_t opc
, int rt
,
1052 int base
, int16_t offset
)
1054 const char *opn
= "ldst";
1055 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
1056 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
1059 tcg_gen_movi_tl(t0
, offset
);
1060 } else if (offset
== 0) {
1061 gen_load_gpr(t0
, base
);
1063 gen_load_gpr(t0
, base
);
1064 tcg_gen_movi_tl(t1
, offset
);
1065 gen_op_addr_add(t0
, t1
);
1067 /* Don't do NOP if destination is zero: we must perform the actual
1070 #if defined(TARGET_MIPS64)
1072 op_ldst_lwu(t0
, ctx
);
1073 gen_store_gpr(t0
, rt
);
1077 op_ldst_ld(t0
, ctx
);
1078 gen_store_gpr(t0
, rt
);
1082 op_ldst_lld(t0
, t1
, ctx
);
1083 gen_store_gpr(t0
, rt
);
1087 gen_load_gpr(t1
, rt
);
1088 op_ldst_sd(t0
, t1
, ctx
);
1092 save_cpu_state(ctx
, 1);
1093 gen_load_gpr(t1
, rt
);
1094 op_ldst_scd(t0
, t1
, ctx
);
1095 gen_store_gpr(t0
, rt
);
1099 save_cpu_state(ctx
, 1);
1100 gen_load_gpr(t1
, rt
);
1101 tcg_gen_helper_1_2i(do_ldl
, t1
, t0
, t1
, ctx
->mem_idx
);
1102 gen_store_gpr(t1
, rt
);
1106 save_cpu_state(ctx
, 1);
1107 gen_load_gpr(t1
, rt
);
1108 tcg_gen_helper_0_2i(do_sdl
, t0
, t1
, ctx
->mem_idx
);
1112 save_cpu_state(ctx
, 1);
1113 gen_load_gpr(t1
, rt
);
1114 tcg_gen_helper_1_2i(do_ldr
, t1
, t0
, t1
, ctx
->mem_idx
);
1115 gen_store_gpr(t1
, rt
);
1119 save_cpu_state(ctx
, 1);
1120 gen_load_gpr(t1
, rt
);
1121 tcg_gen_helper_0_2i(do_sdr
, t0
, t1
, ctx
->mem_idx
);
1126 op_ldst_lw(t0
, ctx
);
1127 gen_store_gpr(t0
, rt
);
1131 gen_load_gpr(t1
, rt
);
1132 op_ldst_sw(t0
, t1
, ctx
);
1136 op_ldst_lh(t0
, ctx
);
1137 gen_store_gpr(t0
, rt
);
1141 gen_load_gpr(t1
, rt
);
1142 op_ldst_sh(t0
, t1
, ctx
);
1146 op_ldst_lhu(t0
, ctx
);
1147 gen_store_gpr(t0
, rt
);
1151 op_ldst_lb(t0
, ctx
);
1152 gen_store_gpr(t0
, rt
);
1156 gen_load_gpr(t1
, rt
);
1157 op_ldst_sb(t0
, t1
, ctx
);
1161 op_ldst_lbu(t0
, ctx
);
1162 gen_store_gpr(t0
, rt
);
1166 save_cpu_state(ctx
, 1);
1167 gen_load_gpr(t1
, rt
);
1168 tcg_gen_helper_1_2i(do_lwl
, t1
, t0
, t1
, ctx
->mem_idx
);
1169 gen_store_gpr(t1
, rt
);
1173 save_cpu_state(ctx
, 1);
1174 gen_load_gpr(t1
, rt
);
1175 tcg_gen_helper_0_2i(do_swl
, t0
, t1
, ctx
->mem_idx
);
1179 save_cpu_state(ctx
, 1);
1180 gen_load_gpr(t1
, rt
);
1181 tcg_gen_helper_1_2i(do_lwr
, t1
, t0
, t1
, ctx
->mem_idx
);
1182 gen_store_gpr(t1
, rt
);
1186 save_cpu_state(ctx
, 1);
1187 gen_load_gpr(t1
, rt
);
1188 tcg_gen_helper_0_2i(do_swr
, t0
, t1
, ctx
->mem_idx
);
1192 op_ldst_ll(t0
, t1
, ctx
);
1193 gen_store_gpr(t0
, rt
);
1197 save_cpu_state(ctx
, 1);
1198 gen_load_gpr(t1
, rt
);
1199 op_ldst_sc(t0
, t1
, ctx
);
1200 gen_store_gpr(t0
, rt
);
1205 generate_exception(ctx
, EXCP_RI
);
1208 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
1214 /* Load and store */
1215 static void gen_flt_ldst (DisasContext
*ctx
, uint32_t opc
, int ft
,
1216 int base
, int16_t offset
)
1218 const char *opn
= "flt_ldst";
1219 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
1222 tcg_gen_movi_tl(t0
, offset
);
1223 } else if (offset
== 0) {
1224 gen_load_gpr(t0
, base
);
1226 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
1228 gen_load_gpr(t0
, base
);
1229 tcg_gen_movi_tl(t1
, offset
);
1230 gen_op_addr_add(t0
, t1
);
1233 /* Don't do NOP if destination is zero: we must perform the actual
1237 tcg_gen_qemu_ld32s(fpu32_T
[0], t0
, ctx
->mem_idx
);
1238 gen_store_fpr32(fpu32_T
[0], ft
);
1242 gen_load_fpr32(fpu32_T
[0], ft
);
1243 tcg_gen_qemu_st32(fpu32_T
[0], t0
, ctx
->mem_idx
);
1247 tcg_gen_qemu_ld64(fpu64_T
[0], t0
, ctx
->mem_idx
);
1248 gen_store_fpr64(ctx
, fpu64_T
[0], ft
);
1252 gen_load_fpr64(ctx
, fpu64_T
[0], ft
);
1253 tcg_gen_qemu_st64(fpu64_T
[0], t0
, ctx
->mem_idx
);
1258 generate_exception(ctx
, EXCP_RI
);
1261 MIPS_DEBUG("%s %s, %d(%s)", opn
, fregnames
[ft
], offset
, regnames
[base
]);
1266 /* Arithmetic with immediate operand */
1267 static void gen_arith_imm (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1268 int rt
, int rs
, int16_t imm
)
1271 const char *opn
= "imm arith";
1272 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
1274 if (rt
== 0 && opc
!= OPC_ADDI
&& opc
!= OPC_DADDI
) {
1275 /* If no destination, treat it as a NOP.
1276 For addi, we must generate the overflow exception when needed. */
1280 uimm
= (uint16_t)imm
;
1284 #if defined(TARGET_MIPS64)
1290 uimm
= (target_long
)imm
; /* Sign extend to 32/64 bits */
1295 gen_load_gpr(t0
, rs
);
1298 tcg_gen_movi_tl(t0
, imm
<< 16);
1303 #if defined(TARGET_MIPS64)
1312 gen_load_gpr(t0
, rs
);
1318 TCGv r_tmp1
= tcg_temp_local_new(TCG_TYPE_TL
);
1319 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_TL
);
1320 int l1
= gen_new_label();
1322 save_cpu_state(ctx
, 1);
1323 tcg_gen_ext32s_tl(r_tmp1
, t0
);
1324 tcg_gen_addi_tl(t0
, r_tmp1
, uimm
);
1326 tcg_gen_xori_tl(r_tmp1
, r_tmp1
, uimm
);
1327 tcg_gen_xori_tl(r_tmp1
, r_tmp1
, -1);
1328 tcg_gen_xori_tl(r_tmp2
, t0
, uimm
);
1329 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1330 tcg_temp_free(r_tmp2
);
1331 tcg_gen_shri_tl(r_tmp1
, r_tmp1
, 31);
1332 tcg_gen_brcondi_tl(TCG_COND_EQ
, r_tmp1
, 0, l1
);
1333 tcg_temp_free(r_tmp1
);
1334 /* operands of same sign, result different sign */
1335 generate_exception(ctx
, EXCP_OVERFLOW
);
1338 tcg_gen_ext32s_tl(t0
, t0
);
1343 tcg_gen_ext32s_tl(t0
, t0
);
1344 tcg_gen_addi_tl(t0
, t0
, uimm
);
1345 tcg_gen_ext32s_tl(t0
, t0
);
1348 #if defined(TARGET_MIPS64)
1351 TCGv r_tmp1
= tcg_temp_local_new(TCG_TYPE_TL
);
1352 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_TL
);
1353 int l1
= gen_new_label();
1355 save_cpu_state(ctx
, 1);
1356 tcg_gen_mov_tl(r_tmp1
, t0
);
1357 tcg_gen_addi_tl(t0
, t0
, uimm
);
1359 tcg_gen_xori_tl(r_tmp1
, r_tmp1
, uimm
);
1360 tcg_gen_xori_tl(r_tmp1
, r_tmp1
, -1);
1361 tcg_gen_xori_tl(r_tmp2
, t0
, uimm
);
1362 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1363 tcg_temp_free(r_tmp2
);
1364 tcg_gen_shri_tl(r_tmp1
, r_tmp1
, 63);
1365 tcg_gen_brcondi_tl(TCG_COND_EQ
, r_tmp1
, 0, l1
);
1366 tcg_temp_free(r_tmp1
);
1367 /* operands of same sign, result different sign */
1368 generate_exception(ctx
, EXCP_OVERFLOW
);
1374 tcg_gen_addi_tl(t0
, t0
, uimm
);
1379 gen_op_lti(t0
, uimm
);
1383 gen_op_ltiu(t0
, uimm
);
1387 tcg_gen_andi_tl(t0
, t0
, uimm
);
1391 tcg_gen_ori_tl(t0
, t0
, uimm
);
1395 tcg_gen_xori_tl(t0
, t0
, uimm
);
1402 tcg_gen_ext32u_tl(t0
, t0
);
1403 tcg_gen_shli_tl(t0
, t0
, uimm
);
1404 tcg_gen_ext32s_tl(t0
, t0
);
1408 tcg_gen_ext32s_tl(t0
, t0
);
1409 tcg_gen_sari_tl(t0
, t0
, uimm
);
1410 tcg_gen_ext32s_tl(t0
, t0
);
1414 switch ((ctx
->opcode
>> 21) & 0x1f) {
1416 tcg_gen_ext32u_tl(t0
, t0
);
1417 tcg_gen_shri_tl(t0
, t0
, uimm
);
1418 tcg_gen_ext32s_tl(t0
, t0
);
1422 /* rotr is decoded as srl on non-R2 CPUs */
1423 if (env
->insn_flags
& ISA_MIPS32R2
) {
1425 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
1426 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I32
);
1428 tcg_gen_trunc_tl_i32(r_tmp1
, t0
);
1429 tcg_gen_movi_i32(r_tmp2
, 0x20);
1430 tcg_gen_subi_i32(r_tmp2
, r_tmp2
, uimm
);
1431 tcg_gen_shl_i32(r_tmp2
, r_tmp1
, r_tmp2
);
1432 tcg_gen_shri_i32(r_tmp1
, r_tmp1
, uimm
);
1433 tcg_gen_or_i32(r_tmp1
, r_tmp1
, r_tmp2
);
1434 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
1435 tcg_temp_free(r_tmp1
);
1436 tcg_temp_free(r_tmp2
);
1440 tcg_gen_ext32u_tl(t0
, t0
);
1441 tcg_gen_shri_tl(t0
, t0
, uimm
);
1442 tcg_gen_ext32s_tl(t0
, t0
);
1447 MIPS_INVAL("invalid srl flag");
1448 generate_exception(ctx
, EXCP_RI
);
1452 #if defined(TARGET_MIPS64)
1454 tcg_gen_shli_tl(t0
, t0
, uimm
);
1458 tcg_gen_sari_tl(t0
, t0
, uimm
);
1462 switch ((ctx
->opcode
>> 21) & 0x1f) {
1464 tcg_gen_shri_tl(t0
, t0
, uimm
);
1468 /* drotr is decoded as dsrl on non-R2 CPUs */
1469 if (env
->insn_flags
& ISA_MIPS32R2
) {
1471 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_TL
);
1473 tcg_gen_movi_tl(r_tmp1
, 0x40);
1474 tcg_gen_subi_tl(r_tmp1
, r_tmp1
, uimm
);
1475 tcg_gen_shl_tl(r_tmp1
, t0
, r_tmp1
);
1476 tcg_gen_shri_tl(t0
, t0
, uimm
);
1477 tcg_gen_or_tl(t0
, t0
, r_tmp1
);
1478 tcg_temp_free(r_tmp1
);
1482 tcg_gen_shri_tl(t0
, t0
, uimm
);
1487 MIPS_INVAL("invalid dsrl flag");
1488 generate_exception(ctx
, EXCP_RI
);
1493 tcg_gen_shli_tl(t0
, t0
, uimm
+ 32);
1497 tcg_gen_sari_tl(t0
, t0
, uimm
+ 32);
1501 switch ((ctx
->opcode
>> 21) & 0x1f) {
1503 tcg_gen_shri_tl(t0
, t0
, uimm
+ 32);
1507 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */
1508 if (env
->insn_flags
& ISA_MIPS32R2
) {
1509 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_TL
);
1510 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_TL
);
1512 tcg_gen_movi_tl(r_tmp1
, 0x40);
1513 tcg_gen_movi_tl(r_tmp2
, 32);
1514 tcg_gen_addi_tl(r_tmp2
, r_tmp2
, uimm
);
1515 tcg_gen_sub_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1516 tcg_gen_shl_tl(r_tmp1
, t0
, r_tmp1
);
1517 tcg_gen_shr_tl(t0
, t0
, r_tmp2
);
1518 tcg_gen_or_tl(t0
, t0
, r_tmp1
);
1519 tcg_temp_free(r_tmp1
);
1520 tcg_temp_free(r_tmp2
);
1523 tcg_gen_shri_tl(t0
, t0
, uimm
+ 32);
1528 MIPS_INVAL("invalid dsrl32 flag");
1529 generate_exception(ctx
, EXCP_RI
);
1536 generate_exception(ctx
, EXCP_RI
);
1539 gen_store_gpr(t0
, rt
);
1540 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1546 static void gen_arith (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1547 int rd
, int rs
, int rt
)
1549 const char *opn
= "arith";
1550 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
1551 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
1553 if (rd
== 0 && opc
!= OPC_ADD
&& opc
!= OPC_SUB
1554 && opc
!= OPC_DADD
&& opc
!= OPC_DSUB
) {
1555 /* If no destination, treat it as a NOP.
1556 For add & sub, we must generate the overflow exception when needed. */
1560 gen_load_gpr(t0
, rs
);
1561 /* Specialcase the conventional move operation. */
1562 if (rt
== 0 && (opc
== OPC_ADDU
|| opc
== OPC_DADDU
1563 || opc
== OPC_SUBU
|| opc
== OPC_DSUBU
)) {
1564 gen_store_gpr(t0
, rd
);
1567 gen_load_gpr(t1
, rt
);
1571 TCGv r_tmp1
= tcg_temp_local_new(TCG_TYPE_TL
);
1572 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_TL
);
1573 int l1
= gen_new_label();
1575 save_cpu_state(ctx
, 1);
1576 tcg_gen_ext32s_tl(r_tmp1
, t0
);
1577 tcg_gen_ext32s_tl(r_tmp2
, t1
);
1578 tcg_gen_add_tl(t0
, r_tmp1
, r_tmp2
);
1580 tcg_gen_xor_tl(r_tmp1
, r_tmp1
, t1
);
1581 tcg_gen_xori_tl(r_tmp1
, r_tmp1
, -1);
1582 tcg_gen_xor_tl(r_tmp2
, t0
, t1
);
1583 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1584 tcg_temp_free(r_tmp2
);
1585 tcg_gen_shri_tl(r_tmp1
, r_tmp1
, 31);
1586 tcg_gen_brcondi_tl(TCG_COND_EQ
, r_tmp1
, 0, l1
);
1587 tcg_temp_free(r_tmp1
);
1588 /* operands of same sign, result different sign */
1589 generate_exception(ctx
, EXCP_OVERFLOW
);
1592 tcg_gen_ext32s_tl(t0
, t0
);
1597 tcg_gen_ext32s_tl(t0
, t0
);
1598 tcg_gen_ext32s_tl(t1
, t1
);
1599 tcg_gen_add_tl(t0
, t0
, t1
);
1600 tcg_gen_ext32s_tl(t0
, t0
);
1605 TCGv r_tmp1
= tcg_temp_local_new(TCG_TYPE_TL
);
1606 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_TL
);
1607 int l1
= gen_new_label();
1609 save_cpu_state(ctx
, 1);
1610 tcg_gen_ext32s_tl(r_tmp1
, t0
);
1611 tcg_gen_ext32s_tl(r_tmp2
, t1
);
1612 tcg_gen_sub_tl(t0
, r_tmp1
, r_tmp2
);
1614 tcg_gen_xor_tl(r_tmp2
, r_tmp1
, t1
);
1615 tcg_gen_xor_tl(r_tmp1
, r_tmp1
, t0
);
1616 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1617 tcg_temp_free(r_tmp2
);
1618 tcg_gen_shri_tl(r_tmp1
, r_tmp1
, 31);
1619 tcg_gen_brcondi_tl(TCG_COND_EQ
, r_tmp1
, 0, l1
);
1620 tcg_temp_free(r_tmp1
);
1621 /* operands of different sign, first operand and result different sign */
1622 generate_exception(ctx
, EXCP_OVERFLOW
);
1625 tcg_gen_ext32s_tl(t0
, t0
);
1630 tcg_gen_ext32s_tl(t0
, t0
);
1631 tcg_gen_ext32s_tl(t1
, t1
);
1632 tcg_gen_sub_tl(t0
, t0
, t1
);
1633 tcg_gen_ext32s_tl(t0
, t0
);
1636 #if defined(TARGET_MIPS64)
1639 TCGv r_tmp1
= tcg_temp_local_new(TCG_TYPE_TL
);
1640 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_TL
);
1641 int l1
= gen_new_label();
1643 save_cpu_state(ctx
, 1);
1644 tcg_gen_mov_tl(r_tmp1
, t0
);
1645 tcg_gen_add_tl(t0
, t0
, t1
);
1647 tcg_gen_xor_tl(r_tmp1
, r_tmp1
, t1
);
1648 tcg_gen_xori_tl(r_tmp1
, r_tmp1
, -1);
1649 tcg_gen_xor_tl(r_tmp2
, t0
, t1
);
1650 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1651 tcg_temp_free(r_tmp2
);
1652 tcg_gen_shri_tl(r_tmp1
, r_tmp1
, 63);
1653 tcg_gen_brcondi_tl(TCG_COND_EQ
, r_tmp1
, 0, l1
);
1654 tcg_temp_free(r_tmp1
);
1655 /* operands of same sign, result different sign */
1656 generate_exception(ctx
, EXCP_OVERFLOW
);
1662 tcg_gen_add_tl(t0
, t0
, t1
);
1667 TCGv r_tmp1
= tcg_temp_local_new(TCG_TYPE_TL
);
1668 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_TL
);
1669 int l1
= gen_new_label();
1671 save_cpu_state(ctx
, 1);
1672 tcg_gen_mov_tl(r_tmp1
, t0
);
1673 tcg_gen_sub_tl(t0
, t0
, t1
);
1675 tcg_gen_xor_tl(r_tmp2
, r_tmp1
, t1
);
1676 tcg_gen_xor_tl(r_tmp1
, r_tmp1
, t0
);
1677 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1678 tcg_temp_free(r_tmp2
);
1679 tcg_gen_shri_tl(r_tmp1
, r_tmp1
, 63);
1680 tcg_gen_brcondi_tl(TCG_COND_EQ
, r_tmp1
, 0, l1
);
1681 tcg_temp_free(r_tmp1
);
1682 /* operands of different sign, first operand and result different sign */
1683 generate_exception(ctx
, EXCP_OVERFLOW
);
1689 tcg_gen_sub_tl(t0
, t0
, t1
);
1702 tcg_gen_and_tl(t0
, t0
, t1
);
1706 tcg_gen_or_tl(t0
, t0
, t1
);
1707 tcg_gen_not_tl(t0
, t0
);
1711 tcg_gen_or_tl(t0
, t0
, t1
);
1715 tcg_gen_xor_tl(t0
, t0
, t1
);
1719 tcg_gen_ext32s_tl(t0
, t0
);
1720 tcg_gen_ext32s_tl(t1
, t1
);
1721 tcg_gen_mul_tl(t0
, t0
, t1
);
1722 tcg_gen_ext32s_tl(t0
, t0
);
1727 int l1
= gen_new_label();
1729 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
1730 gen_store_gpr(t0
, rd
);
1737 int l1
= gen_new_label();
1739 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, 0, l1
);
1740 gen_store_gpr(t0
, rd
);
1746 tcg_gen_ext32u_tl(t0
, t0
);
1747 tcg_gen_ext32u_tl(t1
, t1
);
1748 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1749 tcg_gen_shl_tl(t0
, t1
, t0
);
1750 tcg_gen_ext32s_tl(t0
, t0
);
1754 tcg_gen_ext32s_tl(t1
, t1
);
1755 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1756 tcg_gen_sar_tl(t0
, t1
, t0
);
1757 tcg_gen_ext32s_tl(t0
, t0
);
1761 switch ((ctx
->opcode
>> 6) & 0x1f) {
1763 tcg_gen_ext32u_tl(t1
, t1
);
1764 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1765 tcg_gen_shr_tl(t0
, t1
, t0
);
1766 tcg_gen_ext32s_tl(t0
, t0
);
1770 /* rotrv is decoded as srlv on non-R2 CPUs */
1771 if (env
->insn_flags
& ISA_MIPS32R2
) {
1772 int l1
= gen_new_label();
1773 int l2
= gen_new_label();
1775 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1776 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
1778 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
1779 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I32
);
1780 TCGv r_tmp3
= tcg_temp_new(TCG_TYPE_I32
);
1782 tcg_gen_trunc_tl_i32(r_tmp1
, t0
);
1783 tcg_gen_trunc_tl_i32(r_tmp2
, t1
);
1784 tcg_gen_movi_i32(r_tmp3
, 0x20);
1785 tcg_gen_sub_i32(r_tmp3
, r_tmp3
, r_tmp1
);
1786 tcg_gen_shl_i32(r_tmp3
, r_tmp2
, r_tmp3
);
1787 tcg_gen_shr_i32(r_tmp1
, r_tmp2
, r_tmp1
);
1788 tcg_gen_or_i32(r_tmp1
, r_tmp1
, r_tmp3
);
1789 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
1790 tcg_temp_free(r_tmp1
);
1791 tcg_temp_free(r_tmp2
);
1792 tcg_temp_free(r_tmp3
);
1796 tcg_gen_mov_tl(t0
, t1
);
1800 tcg_gen_ext32u_tl(t1
, t1
);
1801 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1802 tcg_gen_shr_tl(t0
, t1
, t0
);
1803 tcg_gen_ext32s_tl(t0
, t0
);
1808 MIPS_INVAL("invalid srlv flag");
1809 generate_exception(ctx
, EXCP_RI
);
1813 #if defined(TARGET_MIPS64)
1815 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1816 tcg_gen_shl_tl(t0
, t1
, t0
);
1820 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1821 tcg_gen_sar_tl(t0
, t1
, t0
);
1825 switch ((ctx
->opcode
>> 6) & 0x1f) {
1827 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1828 tcg_gen_shr_tl(t0
, t1
, t0
);
1832 /* drotrv is decoded as dsrlv on non-R2 CPUs */
1833 if (env
->insn_flags
& ISA_MIPS32R2
) {
1834 int l1
= gen_new_label();
1835 int l2
= gen_new_label();
1837 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1838 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
1840 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_TL
);
1842 tcg_gen_movi_tl(r_tmp1
, 0x40);
1843 tcg_gen_sub_tl(r_tmp1
, r_tmp1
, t0
);
1844 tcg_gen_shl_tl(r_tmp1
, t1
, r_tmp1
);
1845 tcg_gen_shr_tl(t0
, t1
, t0
);
1846 tcg_gen_or_tl(t0
, t0
, r_tmp1
);
1847 tcg_temp_free(r_tmp1
);
1851 tcg_gen_mov_tl(t0
, t1
);
1855 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1856 tcg_gen_shr_tl(t0
, t1
, t0
);
1861 MIPS_INVAL("invalid dsrlv flag");
1862 generate_exception(ctx
, EXCP_RI
);
1869 generate_exception(ctx
, EXCP_RI
);
1872 gen_store_gpr(t0
, rd
);
1874 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1880 /* Arithmetic on HI/LO registers */
1881 static void gen_HILO (DisasContext
*ctx
, uint32_t opc
, int reg
)
1883 const char *opn
= "hilo";
1884 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
1886 if (reg
== 0 && (opc
== OPC_MFHI
|| opc
== OPC_MFLO
)) {
1894 gen_store_gpr(t0
, reg
);
1899 gen_store_gpr(t0
, reg
);
1903 gen_load_gpr(t0
, reg
);
1904 gen_store_HI(t0
, 0);
1908 gen_load_gpr(t0
, reg
);
1909 gen_store_LO(t0
, 0);
1914 generate_exception(ctx
, EXCP_RI
);
1917 MIPS_DEBUG("%s %s", opn
, regnames
[reg
]);
1922 static void gen_muldiv (DisasContext
*ctx
, uint32_t opc
,
1925 const char *opn
= "mul/div";
1926 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
1927 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
1929 gen_load_gpr(t0
, rs
);
1930 gen_load_gpr(t1
, rt
);
1934 int l1
= gen_new_label();
1936 tcg_gen_ext32s_tl(t0
, t0
);
1937 tcg_gen_ext32s_tl(t1
, t1
);
1938 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
1940 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I64
);
1941 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I64
);
1942 TCGv r_tmp3
= tcg_temp_new(TCG_TYPE_I64
);
1944 tcg_gen_ext_tl_i64(r_tmp1
, t0
);
1945 tcg_gen_ext_tl_i64(r_tmp2
, t1
);
1946 tcg_gen_div_i64(r_tmp3
, r_tmp1
, r_tmp2
);
1947 tcg_gen_rem_i64(r_tmp2
, r_tmp1
, r_tmp2
);
1948 tcg_gen_trunc_i64_tl(t0
, r_tmp3
);
1949 tcg_gen_trunc_i64_tl(t1
, r_tmp2
);
1950 tcg_temp_free(r_tmp1
);
1951 tcg_temp_free(r_tmp2
);
1952 tcg_temp_free(r_tmp3
);
1953 tcg_gen_ext32s_tl(t0
, t0
);
1954 tcg_gen_ext32s_tl(t1
, t1
);
1955 gen_store_LO(t0
, 0);
1956 gen_store_HI(t1
, 0);
1964 int l1
= gen_new_label();
1966 tcg_gen_ext32s_tl(t1
, t1
);
1967 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
1969 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
1970 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I32
);
1971 TCGv r_tmp3
= tcg_temp_new(TCG_TYPE_I32
);
1973 tcg_gen_trunc_tl_i32(r_tmp1
, t0
);
1974 tcg_gen_trunc_tl_i32(r_tmp2
, t1
);
1975 tcg_gen_divu_i32(r_tmp3
, r_tmp1
, r_tmp2
);
1976 tcg_gen_remu_i32(r_tmp1
, r_tmp1
, r_tmp2
);
1977 tcg_gen_ext_i32_tl(t0
, r_tmp3
);
1978 tcg_gen_ext_i32_tl(t1
, r_tmp1
);
1979 tcg_temp_free(r_tmp1
);
1980 tcg_temp_free(r_tmp2
);
1981 tcg_temp_free(r_tmp3
);
1982 gen_store_LO(t0
, 0);
1983 gen_store_HI(t1
, 0);
1991 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I64
);
1992 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I64
);
1994 tcg_gen_ext32s_tl(t0
, t0
);
1995 tcg_gen_ext32s_tl(t1
, t1
);
1996 tcg_gen_ext_tl_i64(r_tmp1
, t0
);
1997 tcg_gen_ext_tl_i64(r_tmp2
, t1
);
1998 tcg_gen_mul_i64(r_tmp1
, r_tmp1
, r_tmp2
);
1999 tcg_temp_free(r_tmp2
);
2000 tcg_gen_trunc_i64_tl(t0
, r_tmp1
);
2001 tcg_gen_shri_i64(r_tmp1
, r_tmp1
, 32);
2002 tcg_gen_trunc_i64_tl(t1
, r_tmp1
);
2003 tcg_temp_free(r_tmp1
);
2004 tcg_gen_ext32s_tl(t0
, t0
);
2005 tcg_gen_ext32s_tl(t1
, t1
);
2006 gen_store_LO(t0
, 0);
2007 gen_store_HI(t1
, 0);
2013 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I64
);
2014 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I64
);
2016 tcg_gen_ext32u_tl(t0
, t0
);
2017 tcg_gen_ext32u_tl(t1
, t1
);
2018 tcg_gen_extu_tl_i64(r_tmp1
, t0
);
2019 tcg_gen_extu_tl_i64(r_tmp2
, t1
);
2020 tcg_gen_mul_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2021 tcg_temp_free(r_tmp2
);
2022 tcg_gen_trunc_i64_tl(t0
, r_tmp1
);
2023 tcg_gen_shri_i64(r_tmp1
, r_tmp1
, 32);
2024 tcg_gen_trunc_i64_tl(t1
, r_tmp1
);
2025 tcg_temp_free(r_tmp1
);
2026 tcg_gen_ext32s_tl(t0
, t0
);
2027 tcg_gen_ext32s_tl(t1
, t1
);
2028 gen_store_LO(t0
, 0);
2029 gen_store_HI(t1
, 0);
2033 #if defined(TARGET_MIPS64)
2036 int l1
= gen_new_label();
2038 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
2040 int l2
= gen_new_label();
2042 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, -1LL << 63, l2
);
2043 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1LL, l2
);
2045 tcg_gen_movi_tl(t1
, 0);
2046 gen_store_LO(t0
, 0);
2047 gen_store_HI(t1
, 0);
2052 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I64
);
2053 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I64
);
2055 tcg_gen_div_i64(r_tmp1
, t0
, t1
);
2056 tcg_gen_rem_i64(r_tmp2
, t0
, t1
);
2057 gen_store_LO(r_tmp1
, 0);
2058 gen_store_HI(r_tmp2
, 0);
2059 tcg_temp_free(r_tmp1
);
2060 tcg_temp_free(r_tmp2
);
2069 int l1
= gen_new_label();
2071 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
2073 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I64
);
2074 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I64
);
2076 tcg_gen_divu_i64(r_tmp1
, t0
, t1
);
2077 tcg_gen_remu_i64(r_tmp2
, t0
, t1
);
2078 tcg_temp_free(r_tmp1
);
2079 tcg_temp_free(r_tmp2
);
2080 gen_store_LO(r_tmp1
, 0);
2081 gen_store_HI(r_tmp2
, 0);
2088 tcg_gen_helper_0_2(do_dmult
, t0
, t1
);
2092 tcg_gen_helper_0_2(do_dmultu
, t0
, t1
);
2098 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I64
);
2099 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I64
);
2100 TCGv r_tmp3
= tcg_temp_new(TCG_TYPE_I64
);
2102 tcg_gen_ext32s_tl(t0
, t0
);
2103 tcg_gen_ext32s_tl(t1
, t1
);
2104 tcg_gen_ext_tl_i64(r_tmp1
, t0
);
2105 tcg_gen_ext_tl_i64(r_tmp2
, t1
);
2106 tcg_gen_mul_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2109 tcg_gen_extu_tl_i64(r_tmp2
, t0
);
2110 tcg_gen_extu_tl_i64(r_tmp3
, t1
);
2111 tcg_gen_shli_i64(r_tmp3
, r_tmp3
, 32);
2112 tcg_gen_or_i64(r_tmp2
, r_tmp2
, r_tmp3
);
2113 tcg_temp_free(r_tmp3
);
2114 tcg_gen_add_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2115 tcg_temp_free(r_tmp2
);
2116 tcg_gen_trunc_i64_tl(t0
, r_tmp1
);
2117 tcg_gen_shri_i64(r_tmp1
, r_tmp1
, 32);
2118 tcg_gen_trunc_i64_tl(t1
, r_tmp1
);
2119 tcg_temp_free(r_tmp1
);
2120 tcg_gen_ext32s_tl(t0
, t0
);
2121 tcg_gen_ext32s_tl(t1
, t1
);
2122 gen_store_LO(t0
, 0);
2123 gen_store_HI(t1
, 0);
2129 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I64
);
2130 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I64
);
2131 TCGv r_tmp3
= tcg_temp_new(TCG_TYPE_I64
);
2133 tcg_gen_ext32u_tl(t0
, t0
);
2134 tcg_gen_ext32u_tl(t1
, t1
);
2135 tcg_gen_extu_tl_i64(r_tmp1
, t0
);
2136 tcg_gen_extu_tl_i64(r_tmp2
, t1
);
2137 tcg_gen_mul_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2140 tcg_gen_extu_tl_i64(r_tmp2
, t0
);
2141 tcg_gen_extu_tl_i64(r_tmp3
, t1
);
2142 tcg_gen_shli_i64(r_tmp3
, r_tmp3
, 32);
2143 tcg_gen_or_i64(r_tmp2
, r_tmp2
, r_tmp3
);
2144 tcg_temp_free(r_tmp3
);
2145 tcg_gen_add_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2146 tcg_temp_free(r_tmp2
);
2147 tcg_gen_trunc_i64_tl(t0
, r_tmp1
);
2148 tcg_gen_shri_i64(r_tmp1
, r_tmp1
, 32);
2149 tcg_gen_trunc_i64_tl(t1
, r_tmp1
);
2150 tcg_temp_free(r_tmp1
);
2151 tcg_gen_ext32s_tl(t0
, t0
);
2152 tcg_gen_ext32s_tl(t1
, t1
);
2153 gen_store_LO(t0
, 0);
2154 gen_store_HI(t1
, 0);
2160 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I64
);
2161 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I64
);
2162 TCGv r_tmp3
= tcg_temp_new(TCG_TYPE_I64
);
2164 tcg_gen_ext32s_tl(t0
, t0
);
2165 tcg_gen_ext32s_tl(t1
, t1
);
2166 tcg_gen_ext_tl_i64(r_tmp1
, t0
);
2167 tcg_gen_ext_tl_i64(r_tmp2
, t1
);
2168 tcg_gen_mul_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2171 tcg_gen_extu_tl_i64(r_tmp2
, t0
);
2172 tcg_gen_extu_tl_i64(r_tmp3
, t1
);
2173 tcg_gen_shli_i64(r_tmp3
, r_tmp3
, 32);
2174 tcg_gen_or_i64(r_tmp2
, r_tmp2
, r_tmp3
);
2175 tcg_temp_free(r_tmp3
);
2176 tcg_gen_sub_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2177 tcg_temp_free(r_tmp2
);
2178 tcg_gen_trunc_i64_tl(t0
, r_tmp1
);
2179 tcg_gen_shri_i64(r_tmp1
, r_tmp1
, 32);
2180 tcg_gen_trunc_i64_tl(t1
, r_tmp1
);
2181 tcg_temp_free(r_tmp1
);
2182 tcg_gen_ext32s_tl(t0
, t0
);
2183 tcg_gen_ext32s_tl(t1
, t1
);
2184 gen_store_LO(t0
, 0);
2185 gen_store_HI(t1
, 0);
2191 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I64
);
2192 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I64
);
2193 TCGv r_tmp3
= tcg_temp_new(TCG_TYPE_I64
);
2195 tcg_gen_ext32u_tl(t0
, t0
);
2196 tcg_gen_ext32u_tl(t1
, t1
);
2197 tcg_gen_extu_tl_i64(r_tmp1
, t0
);
2198 tcg_gen_extu_tl_i64(r_tmp2
, t1
);
2199 tcg_gen_mul_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2202 tcg_gen_extu_tl_i64(r_tmp2
, t0
);
2203 tcg_gen_extu_tl_i64(r_tmp3
, t1
);
2204 tcg_gen_shli_i64(r_tmp3
, r_tmp3
, 32);
2205 tcg_gen_or_i64(r_tmp2
, r_tmp2
, r_tmp3
);
2206 tcg_temp_free(r_tmp3
);
2207 tcg_gen_sub_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2208 tcg_temp_free(r_tmp2
);
2209 tcg_gen_trunc_i64_tl(t0
, r_tmp1
);
2210 tcg_gen_shri_i64(r_tmp1
, r_tmp1
, 32);
2211 tcg_gen_trunc_i64_tl(t1
, r_tmp1
);
2212 tcg_temp_free(r_tmp1
);
2213 tcg_gen_ext32s_tl(t0
, t0
);
2214 tcg_gen_ext32s_tl(t1
, t1
);
2215 gen_store_LO(t0
, 0);
2216 gen_store_HI(t1
, 0);
2222 generate_exception(ctx
, EXCP_RI
);
2225 MIPS_DEBUG("%s %s %s", opn
, regnames
[rs
], regnames
[rt
]);
2231 static void gen_mul_vr54xx (DisasContext
*ctx
, uint32_t opc
,
2232 int rd
, int rs
, int rt
)
2234 const char *opn
= "mul vr54xx";
2235 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
2236 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
2238 gen_load_gpr(t0
, rs
);
2239 gen_load_gpr(t1
, rt
);
2242 case OPC_VR54XX_MULS
:
2243 tcg_gen_helper_1_2(do_muls
, t0
, t0
, t1
);
2246 case OPC_VR54XX_MULSU
:
2247 tcg_gen_helper_1_2(do_mulsu
, t0
, t0
, t1
);
2250 case OPC_VR54XX_MACC
:
2251 tcg_gen_helper_1_2(do_macc
, t0
, t0
, t1
);
2254 case OPC_VR54XX_MACCU
:
2255 tcg_gen_helper_1_2(do_maccu
, t0
, t0
, t1
);
2258 case OPC_VR54XX_MSAC
:
2259 tcg_gen_helper_1_2(do_msac
, t0
, t0
, t1
);
2262 case OPC_VR54XX_MSACU
:
2263 tcg_gen_helper_1_2(do_msacu
, t0
, t0
, t1
);
2266 case OPC_VR54XX_MULHI
:
2267 tcg_gen_helper_1_2(do_mulhi
, t0
, t0
, t1
);
2270 case OPC_VR54XX_MULHIU
:
2271 tcg_gen_helper_1_2(do_mulhiu
, t0
, t0
, t1
);
2274 case OPC_VR54XX_MULSHI
:
2275 tcg_gen_helper_1_2(do_mulshi
, t0
, t0
, t1
);
2278 case OPC_VR54XX_MULSHIU
:
2279 tcg_gen_helper_1_2(do_mulshiu
, t0
, t0
, t1
);
2282 case OPC_VR54XX_MACCHI
:
2283 tcg_gen_helper_1_2(do_macchi
, t0
, t0
, t1
);
2286 case OPC_VR54XX_MACCHIU
:
2287 tcg_gen_helper_1_2(do_macchiu
, t0
, t0
, t1
);
2290 case OPC_VR54XX_MSACHI
:
2291 tcg_gen_helper_1_2(do_msachi
, t0
, t0
, t1
);
2294 case OPC_VR54XX_MSACHIU
:
2295 tcg_gen_helper_1_2(do_msachiu
, t0
, t0
, t1
);
2299 MIPS_INVAL("mul vr54xx");
2300 generate_exception(ctx
, EXCP_RI
);
2303 gen_store_gpr(t0
, rd
);
2304 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
2311 static void gen_cl (DisasContext
*ctx
, uint32_t opc
,
2314 const char *opn
= "CLx";
2315 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
2322 gen_load_gpr(t0
, rs
);
2325 tcg_gen_helper_1_1(do_clo
, t0
, t0
);
2329 tcg_gen_helper_1_1(do_clz
, t0
, t0
);
2332 #if defined(TARGET_MIPS64)
2334 tcg_gen_helper_1_1(do_dclo
, t0
, t0
);
2338 tcg_gen_helper_1_1(do_dclz
, t0
, t0
);
2344 generate_exception(ctx
, EXCP_RI
);
2347 gen_store_gpr(t0
, rd
);
2348 MIPS_DEBUG("%s %s, %s", opn
, regnames
[rd
], regnames
[rs
]);
2355 static void gen_trap (DisasContext
*ctx
, uint32_t opc
,
2356 int rs
, int rt
, int16_t imm
)
2359 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
2360 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
2363 /* Load needed operands */
2371 /* Compare two registers */
2373 gen_load_gpr(t0
, rs
);
2374 gen_load_gpr(t1
, rt
);
2384 /* Compare register to immediate */
2385 if (rs
!= 0 || imm
!= 0) {
2386 gen_load_gpr(t0
, rs
);
2387 tcg_gen_movi_tl(t1
, (int32_t)imm
);
2394 case OPC_TEQ
: /* rs == rs */
2395 case OPC_TEQI
: /* r0 == 0 */
2396 case OPC_TGE
: /* rs >= rs */
2397 case OPC_TGEI
: /* r0 >= 0 */
2398 case OPC_TGEU
: /* rs >= rs unsigned */
2399 case OPC_TGEIU
: /* r0 >= 0 unsigned */
2401 tcg_gen_movi_tl(t0
, 1);
2403 case OPC_TLT
: /* rs < rs */
2404 case OPC_TLTI
: /* r0 < 0 */
2405 case OPC_TLTU
: /* rs < rs unsigned */
2406 case OPC_TLTIU
: /* r0 < 0 unsigned */
2407 case OPC_TNE
: /* rs != rs */
2408 case OPC_TNEI
: /* r0 != 0 */
2409 /* Never trap: treat as NOP. */
2413 generate_exception(ctx
, EXCP_RI
);
2444 generate_exception(ctx
, EXCP_RI
);
2448 save_cpu_state(ctx
, 1);
2450 int l1
= gen_new_label();
2452 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
2453 tcg_gen_helper_0_i(do_raise_exception
, EXCP_TRAP
);
2456 ctx
->bstate
= BS_STOP
;
2462 static always_inline
void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
2464 TranslationBlock
*tb
;
2466 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
2469 tcg_gen_exit_tb((long)tb
+ n
);
2476 /* Branches (before delay slot) */
2477 static void gen_compute_branch (DisasContext
*ctx
, uint32_t opc
,
2478 int rs
, int rt
, int32_t offset
)
2480 target_ulong btgt
= -1;
2483 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
2484 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
2486 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
2487 #ifdef MIPS_DEBUG_DISAS
2488 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2490 "Branch in delay slot at PC 0x" TARGET_FMT_lx
"\n",
2494 generate_exception(ctx
, EXCP_RI
);
2498 /* Load needed operands */
2504 /* Compare two registers */
2506 gen_load_gpr(t0
, rs
);
2507 gen_load_gpr(t1
, rt
);
2510 btgt
= ctx
->pc
+ 4 + offset
;
2524 /* Compare to zero */
2526 gen_load_gpr(t0
, rs
);
2529 btgt
= ctx
->pc
+ 4 + offset
;
2533 /* Jump to immediate */
2534 btgt
= ((ctx
->pc
+ 4) & (int32_t)0xF0000000) | (uint32_t)offset
;
2538 /* Jump to register */
2539 if (offset
!= 0 && offset
!= 16) {
2540 /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
2541 others are reserved. */
2542 MIPS_INVAL("jump hint");
2543 generate_exception(ctx
, EXCP_RI
);
2546 gen_load_gpr(btarget
, rs
);
2549 MIPS_INVAL("branch/jump");
2550 generate_exception(ctx
, EXCP_RI
);
2554 /* No condition to be computed */
2556 case OPC_BEQ
: /* rx == rx */
2557 case OPC_BEQL
: /* rx == rx likely */
2558 case OPC_BGEZ
: /* 0 >= 0 */
2559 case OPC_BGEZL
: /* 0 >= 0 likely */
2560 case OPC_BLEZ
: /* 0 <= 0 */
2561 case OPC_BLEZL
: /* 0 <= 0 likely */
2563 ctx
->hflags
|= MIPS_HFLAG_B
;
2564 MIPS_DEBUG("balways");
2566 case OPC_BGEZAL
: /* 0 >= 0 */
2567 case OPC_BGEZALL
: /* 0 >= 0 likely */
2568 /* Always take and link */
2570 ctx
->hflags
|= MIPS_HFLAG_B
;
2571 MIPS_DEBUG("balways and link");
2573 case OPC_BNE
: /* rx != rx */
2574 case OPC_BGTZ
: /* 0 > 0 */
2575 case OPC_BLTZ
: /* 0 < 0 */
2577 MIPS_DEBUG("bnever (NOP)");
2579 case OPC_BLTZAL
: /* 0 < 0 */
2580 tcg_gen_movi_tl(t0
, ctx
->pc
+ 8);
2581 gen_store_gpr(t0
, 31);
2582 MIPS_DEBUG("bnever and link");
2584 case OPC_BLTZALL
: /* 0 < 0 likely */
2585 tcg_gen_movi_tl(t0
, ctx
->pc
+ 8);
2586 gen_store_gpr(t0
, 31);
2587 /* Skip the instruction in the delay slot */
2588 MIPS_DEBUG("bnever, link and skip");
2591 case OPC_BNEL
: /* rx != rx likely */
2592 case OPC_BGTZL
: /* 0 > 0 likely */
2593 case OPC_BLTZL
: /* 0 < 0 likely */
2594 /* Skip the instruction in the delay slot */
2595 MIPS_DEBUG("bnever and skip");
2599 ctx
->hflags
|= MIPS_HFLAG_B
;
2600 MIPS_DEBUG("j " TARGET_FMT_lx
, btgt
);
2604 ctx
->hflags
|= MIPS_HFLAG_B
;
2605 MIPS_DEBUG("jal " TARGET_FMT_lx
, btgt
);
2608 ctx
->hflags
|= MIPS_HFLAG_BR
;
2609 MIPS_DEBUG("jr %s", regnames
[rs
]);
2613 ctx
->hflags
|= MIPS_HFLAG_BR
;
2614 MIPS_DEBUG("jalr %s, %s", regnames
[rt
], regnames
[rs
]);
2617 MIPS_INVAL("branch/jump");
2618 generate_exception(ctx
, EXCP_RI
);
2625 MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx
,
2626 regnames
[rs
], regnames
[rt
], btgt
);
2630 MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx
,
2631 regnames
[rs
], regnames
[rt
], btgt
);
2635 MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx
,
2636 regnames
[rs
], regnames
[rt
], btgt
);
2640 MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx
,
2641 regnames
[rs
], regnames
[rt
], btgt
);
2645 MIPS_DEBUG("bgez %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2649 MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2653 MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2659 MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2663 MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2667 MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2671 MIPS_DEBUG("blez %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2675 MIPS_DEBUG("blezl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2679 MIPS_DEBUG("bltz %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2683 MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2688 MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2690 ctx
->hflags
|= MIPS_HFLAG_BC
;
2691 tcg_gen_trunc_tl_i32(bcond
, t0
);
2696 MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2698 ctx
->hflags
|= MIPS_HFLAG_BL
;
2699 tcg_gen_trunc_tl_i32(bcond
, t0
);
2702 MIPS_INVAL("conditional branch/jump");
2703 generate_exception(ctx
, EXCP_RI
);
2707 MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx
,
2708 blink
, ctx
->hflags
, btgt
);
2710 ctx
->btarget
= btgt
;
2712 tcg_gen_movi_tl(t0
, ctx
->pc
+ 8);
2713 gen_store_gpr(t0
, blink
);
2721 /* special3 bitfield operations */
2722 static void gen_bitops (DisasContext
*ctx
, uint32_t opc
, int rt
,
2723 int rs
, int lsb
, int msb
)
2725 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
2726 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
2728 gen_load_gpr(t1
, rs
);
2733 tcg_gen_helper_1_1ii(do_ext
, t0
, t1
, lsb
, msb
+ 1);
2735 #if defined(TARGET_MIPS64)
2739 tcg_gen_helper_1_1ii(do_dext
, t0
, t1
, lsb
, msb
+ 1 + 32);
2744 tcg_gen_helper_1_1ii(do_dext
, t0
, t1
, lsb
+ 32, msb
+ 1);
2749 tcg_gen_helper_1_1ii(do_dext
, t0
, t1
, lsb
, msb
+ 1);
2755 gen_load_gpr(t0
, rt
);
2756 tcg_gen_helper_1_2ii(do_ins
, t0
, t0
, t1
, lsb
, msb
- lsb
+ 1);
2758 #if defined(TARGET_MIPS64)
2762 gen_load_gpr(t0
, rt
);
2763 tcg_gen_helper_1_2ii(do_dins
, t0
, t0
, t1
, lsb
, msb
- lsb
+ 1 + 32);
2768 gen_load_gpr(t0
, rt
);
2769 tcg_gen_helper_1_2ii(do_dins
, t0
, t0
, t1
, lsb
+ 32, msb
- lsb
+ 1);
2774 gen_load_gpr(t0
, rt
);
2775 tcg_gen_helper_1_2ii(do_dins
, t0
, t0
, t1
, lsb
, msb
- lsb
+ 1);
2780 MIPS_INVAL("bitops");
2781 generate_exception(ctx
, EXCP_RI
);
2786 gen_store_gpr(t0
, rt
);
2791 /* CP0 (MMU and control) */
2792 #ifndef CONFIG_USER_ONLY
2793 static inline void gen_mfc0_load32 (TCGv t
, target_ulong off
)
2795 TCGv r_tmp
= tcg_temp_new(TCG_TYPE_I32
);
2797 tcg_gen_ld_i32(r_tmp
, cpu_env
, off
);
2798 tcg_gen_ext_i32_tl(t
, r_tmp
);
2799 tcg_temp_free(r_tmp
);
2802 static inline void gen_mfc0_load64 (TCGv t
, target_ulong off
)
2804 tcg_gen_ld_tl(t
, cpu_env
, off
);
2805 tcg_gen_ext32s_tl(t
, t
);
2808 static inline void gen_mtc0_store32 (TCGv t
, target_ulong off
)
2810 TCGv r_tmp
= tcg_temp_new(TCG_TYPE_I32
);
2812 tcg_gen_trunc_tl_i32(r_tmp
, t
);
2813 tcg_gen_st_i32(r_tmp
, cpu_env
, off
);
2814 tcg_temp_free(r_tmp
);
2817 static inline void gen_mtc0_store64 (TCGv t
, target_ulong off
)
2819 tcg_gen_ext32s_tl(t
, t
);
2820 tcg_gen_st_tl(t
, cpu_env
, off
);
2823 static void gen_mfc0 (CPUState
*env
, DisasContext
*ctx
, TCGv t0
, int reg
, int sel
)
2825 const char *rn
= "invalid";
2828 check_insn(env
, ctx
, ISA_MIPS32
);
2834 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Index
));
2838 check_insn(env
, ctx
, ASE_MT
);
2839 tcg_gen_helper_1_0(do_mfc0_mvpcontrol
, t0
);
2843 check_insn(env
, ctx
, ASE_MT
);
2844 tcg_gen_helper_1_0(do_mfc0_mvpconf0
, t0
);
2848 check_insn(env
, ctx
, ASE_MT
);
2849 tcg_gen_helper_1_0(do_mfc0_mvpconf1
, t0
);
2859 tcg_gen_helper_1_0(do_mfc0_random
, t0
);
2863 check_insn(env
, ctx
, ASE_MT
);
2864 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEControl
));
2868 check_insn(env
, ctx
, ASE_MT
);
2869 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEConf0
));
2873 check_insn(env
, ctx
, ASE_MT
);
2874 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEConf1
));
2878 check_insn(env
, ctx
, ASE_MT
);
2879 gen_mfc0_load64(t0
, offsetof(CPUState
, CP0_YQMask
));
2883 check_insn(env
, ctx
, ASE_MT
);
2884 gen_mfc0_load64(t0
, offsetof(CPUState
, CP0_VPESchedule
));
2888 check_insn(env
, ctx
, ASE_MT
);
2889 gen_mfc0_load64(t0
, offsetof(CPUState
, CP0_VPEScheFBack
));
2890 rn
= "VPEScheFBack";
2893 check_insn(env
, ctx
, ASE_MT
);
2894 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEOpt
));
2904 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryLo0
));
2905 tcg_gen_ext32s_tl(t0
, t0
);
2909 check_insn(env
, ctx
, ASE_MT
);
2910 tcg_gen_helper_1_0(do_mfc0_tcstatus
, t0
);
2914 check_insn(env
, ctx
, ASE_MT
);
2915 tcg_gen_helper_1_0(do_mfc0_tcbind
, t0
);
2919 check_insn(env
, ctx
, ASE_MT
);
2920 tcg_gen_helper_1_0(do_mfc0_tcrestart
, t0
);
2924 check_insn(env
, ctx
, ASE_MT
);
2925 tcg_gen_helper_1_0(do_mfc0_tchalt
, t0
);
2929 check_insn(env
, ctx
, ASE_MT
);
2930 tcg_gen_helper_1_0(do_mfc0_tccontext
, t0
);
2934 check_insn(env
, ctx
, ASE_MT
);
2935 tcg_gen_helper_1_0(do_mfc0_tcschedule
, t0
);
2939 check_insn(env
, ctx
, ASE_MT
);
2940 tcg_gen_helper_1_0(do_mfc0_tcschefback
, t0
);
2950 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryLo1
));
2951 tcg_gen_ext32s_tl(t0
, t0
);
2961 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_Context
));
2962 tcg_gen_ext32s_tl(t0
, t0
);
2966 // tcg_gen_helper_1_0(do_mfc0_contextconfig, t0); /* SmartMIPS ASE */
2967 rn
= "ContextConfig";
2976 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PageMask
));
2980 check_insn(env
, ctx
, ISA_MIPS32R2
);
2981 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PageGrain
));
2991 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Wired
));
2995 check_insn(env
, ctx
, ISA_MIPS32R2
);
2996 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf0
));
3000 check_insn(env
, ctx
, ISA_MIPS32R2
);
3001 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf1
));
3005 check_insn(env
, ctx
, ISA_MIPS32R2
);
3006 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf2
));
3010 check_insn(env
, ctx
, ISA_MIPS32R2
);
3011 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf3
));
3015 check_insn(env
, ctx
, ISA_MIPS32R2
);
3016 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf4
));
3026 check_insn(env
, ctx
, ISA_MIPS32R2
);
3027 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_HWREna
));
3037 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_BadVAddr
));
3038 tcg_gen_ext32s_tl(t0
, t0
);
3048 /* Mark as an IO operation because we read the time. */
3051 tcg_gen_helper_1_0(do_mfc0_count
, t0
);
3054 ctx
->bstate
= BS_STOP
;
3058 /* 6,7 are implementation dependent */
3066 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryHi
));
3067 tcg_gen_ext32s_tl(t0
, t0
);
3077 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Compare
));
3080 /* 6,7 are implementation dependent */
3088 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Status
));
3092 check_insn(env
, ctx
, ISA_MIPS32R2
);
3093 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_IntCtl
));
3097 check_insn(env
, ctx
, ISA_MIPS32R2
);
3098 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSCtl
));
3102 check_insn(env
, ctx
, ISA_MIPS32R2
);
3103 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSMap
));
3113 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Cause
));
3123 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
3124 tcg_gen_ext32s_tl(t0
, t0
);
3134 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PRid
));
3138 check_insn(env
, ctx
, ISA_MIPS32R2
);
3139 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_EBase
));
3149 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config0
));
3153 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config1
));
3157 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config2
));
3161 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config3
));
3164 /* 4,5 are reserved */
3165 /* 6,7 are implementation dependent */
3167 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config6
));
3171 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config7
));
3181 tcg_gen_helper_1_0(do_mfc0_lladdr
, t0
);
3191 tcg_gen_helper_1_i(do_mfc0_watchlo
, t0
, sel
);
3201 tcg_gen_helper_1_i(do_mfc0_watchhi
, t0
, sel
);
3211 #if defined(TARGET_MIPS64)
3212 check_insn(env
, ctx
, ISA_MIPS3
);
3213 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_XContext
));
3214 tcg_gen_ext32s_tl(t0
, t0
);
3223 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3226 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Framemask
));
3235 rn
= "'Diagnostic"; /* implementation dependent */
3240 tcg_gen_helper_1_0(do_mfc0_debug
, t0
); /* EJTAG support */
3244 // tcg_gen_helper_1_0(do_mfc0_tracecontrol, t0); /* PDtrace support */
3245 rn
= "TraceControl";
3248 // tcg_gen_helper_1_0(do_mfc0_tracecontrol2, t0); /* PDtrace support */
3249 rn
= "TraceControl2";
3252 // tcg_gen_helper_1_0(do_mfc0_usertracedata, t0); /* PDtrace support */
3253 rn
= "UserTraceData";
3256 // tcg_gen_helper_1_0(do_mfc0_tracebpc, t0); /* PDtrace support */
3267 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
3268 tcg_gen_ext32s_tl(t0
, t0
);
3278 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Performance0
));
3279 rn
= "Performance0";
3282 // tcg_gen_helper_1_0(do_mfc0_performance1, t0);
3283 rn
= "Performance1";
3286 // tcg_gen_helper_1_0(do_mfc0_performance2, t0);
3287 rn
= "Performance2";
3290 // tcg_gen_helper_1_0(do_mfc0_performance3, t0);
3291 rn
= "Performance3";
3294 // tcg_gen_helper_1_0(do_mfc0_performance4, t0);
3295 rn
= "Performance4";
3298 // tcg_gen_helper_1_0(do_mfc0_performance5, t0);
3299 rn
= "Performance5";
3302 // tcg_gen_helper_1_0(do_mfc0_performance6, t0);
3303 rn
= "Performance6";
3306 // tcg_gen_helper_1_0(do_mfc0_performance7, t0);
3307 rn
= "Performance7";
3332 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_TagLo
));
3339 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DataLo
));
3352 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_TagHi
));
3359 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DataHi
));
3369 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
3370 tcg_gen_ext32s_tl(t0
, t0
);
3381 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DESAVE
));
3391 #if defined MIPS_DEBUG_DISAS
3392 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3393 fprintf(logfile
, "mfc0 %s (reg %d sel %d)\n",
3400 #if defined MIPS_DEBUG_DISAS
3401 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3402 fprintf(logfile
, "mfc0 %s (reg %d sel %d)\n",
3406 generate_exception(ctx
, EXCP_RI
);
3409 static void gen_mtc0 (CPUState
*env
, DisasContext
*ctx
, TCGv t0
, int reg
, int sel
)
3411 const char *rn
= "invalid";
3414 check_insn(env
, ctx
, ISA_MIPS32
);
3423 tcg_gen_helper_0_1(do_mtc0_index
, t0
);
3427 check_insn(env
, ctx
, ASE_MT
);
3428 tcg_gen_helper_0_1(do_mtc0_mvpcontrol
, t0
);
3432 check_insn(env
, ctx
, ASE_MT
);
3437 check_insn(env
, ctx
, ASE_MT
);
3452 check_insn(env
, ctx
, ASE_MT
);
3453 tcg_gen_helper_0_1(do_mtc0_vpecontrol
, t0
);
3457 check_insn(env
, ctx
, ASE_MT
);
3458 tcg_gen_helper_0_1(do_mtc0_vpeconf0
, t0
);
3462 check_insn(env
, ctx
, ASE_MT
);
3463 tcg_gen_helper_0_1(do_mtc0_vpeconf1
, t0
);
3467 check_insn(env
, ctx
, ASE_MT
);
3468 tcg_gen_helper_0_1(do_mtc0_yqmask
, t0
);
3472 check_insn(env
, ctx
, ASE_MT
);
3473 gen_mtc0_store64(t0
, offsetof(CPUState
, CP0_VPESchedule
));
3477 check_insn(env
, ctx
, ASE_MT
);
3478 gen_mtc0_store64(t0
, offsetof(CPUState
, CP0_VPEScheFBack
));
3479 rn
= "VPEScheFBack";
3482 check_insn(env
, ctx
, ASE_MT
);
3483 tcg_gen_helper_0_1(do_mtc0_vpeopt
, t0
);
3493 tcg_gen_helper_0_1(do_mtc0_entrylo0
, t0
);
3497 check_insn(env
, ctx
, ASE_MT
);
3498 tcg_gen_helper_0_1(do_mtc0_tcstatus
, t0
);
3502 check_insn(env
, ctx
, ASE_MT
);
3503 tcg_gen_helper_0_1(do_mtc0_tcbind
, t0
);
3507 check_insn(env
, ctx
, ASE_MT
);
3508 tcg_gen_helper_0_1(do_mtc0_tcrestart
, t0
);
3512 check_insn(env
, ctx
, ASE_MT
);
3513 tcg_gen_helper_0_1(do_mtc0_tchalt
, t0
);
3517 check_insn(env
, ctx
, ASE_MT
);
3518 tcg_gen_helper_0_1(do_mtc0_tccontext
, t0
);
3522 check_insn(env
, ctx
, ASE_MT
);
3523 tcg_gen_helper_0_1(do_mtc0_tcschedule
, t0
);
3527 check_insn(env
, ctx
, ASE_MT
);
3528 tcg_gen_helper_0_1(do_mtc0_tcschefback
, t0
);
3538 tcg_gen_helper_0_1(do_mtc0_entrylo1
, t0
);
3548 tcg_gen_helper_0_1(do_mtc0_context
, t0
);
3552 // tcg_gen_helper_0_1(do_mtc0_contextconfig, t0); /* SmartMIPS ASE */
3553 rn
= "ContextConfig";
3562 tcg_gen_helper_0_1(do_mtc0_pagemask
, t0
);
3566 check_insn(env
, ctx
, ISA_MIPS32R2
);
3567 tcg_gen_helper_0_1(do_mtc0_pagegrain
, t0
);
3577 tcg_gen_helper_0_1(do_mtc0_wired
, t0
);
3581 check_insn(env
, ctx
, ISA_MIPS32R2
);
3582 tcg_gen_helper_0_1(do_mtc0_srsconf0
, t0
);
3586 check_insn(env
, ctx
, ISA_MIPS32R2
);
3587 tcg_gen_helper_0_1(do_mtc0_srsconf1
, t0
);
3591 check_insn(env
, ctx
, ISA_MIPS32R2
);
3592 tcg_gen_helper_0_1(do_mtc0_srsconf2
, t0
);
3596 check_insn(env
, ctx
, ISA_MIPS32R2
);
3597 tcg_gen_helper_0_1(do_mtc0_srsconf3
, t0
);
3601 check_insn(env
, ctx
, ISA_MIPS32R2
);
3602 tcg_gen_helper_0_1(do_mtc0_srsconf4
, t0
);
3612 check_insn(env
, ctx
, ISA_MIPS32R2
);
3613 tcg_gen_helper_0_1(do_mtc0_hwrena
, t0
);
3627 tcg_gen_helper_0_1(do_mtc0_count
, t0
);
3630 /* 6,7 are implementation dependent */
3634 /* Stop translation as we may have switched the execution mode */
3635 ctx
->bstate
= BS_STOP
;
3640 tcg_gen_helper_0_1(do_mtc0_entryhi
, t0
);
3650 tcg_gen_helper_0_1(do_mtc0_compare
, t0
);
3653 /* 6,7 are implementation dependent */
3657 /* Stop translation as we may have switched the execution mode */
3658 ctx
->bstate
= BS_STOP
;
3663 tcg_gen_helper_0_1(do_mtc0_status
, t0
);
3664 /* BS_STOP isn't good enough here, hflags may have changed. */
3665 gen_save_pc(ctx
->pc
+ 4);
3666 ctx
->bstate
= BS_EXCP
;
3670 check_insn(env
, ctx
, ISA_MIPS32R2
);
3671 tcg_gen_helper_0_1(do_mtc0_intctl
, t0
);
3672 /* Stop translation as we may have switched the execution mode */
3673 ctx
->bstate
= BS_STOP
;
3677 check_insn(env
, ctx
, ISA_MIPS32R2
);
3678 tcg_gen_helper_0_1(do_mtc0_srsctl
, t0
);
3679 /* Stop translation as we may have switched the execution mode */
3680 ctx
->bstate
= BS_STOP
;
3684 check_insn(env
, ctx
, ISA_MIPS32R2
);
3685 gen_mtc0_store32(t0
, offsetof(CPUState
, CP0_SRSMap
));
3686 /* Stop translation as we may have switched the execution mode */
3687 ctx
->bstate
= BS_STOP
;
3697 tcg_gen_helper_0_1(do_mtc0_cause
, t0
);
3703 /* Stop translation as we may have switched the execution mode */
3704 ctx
->bstate
= BS_STOP
;
3709 gen_mtc0_store64(t0
, offsetof(CPUState
, CP0_EPC
));
3723 check_insn(env
, ctx
, ISA_MIPS32R2
);
3724 tcg_gen_helper_0_1(do_mtc0_ebase
, t0
);
3734 tcg_gen_helper_0_1(do_mtc0_config0
, t0
);
3736 /* Stop translation as we may have switched the execution mode */
3737 ctx
->bstate
= BS_STOP
;
3740 /* ignored, read only */
3744 tcg_gen_helper_0_1(do_mtc0_config2
, t0
);
3746 /* Stop translation as we may have switched the execution mode */
3747 ctx
->bstate
= BS_STOP
;
3750 /* ignored, read only */
3753 /* 4,5 are reserved */
3754 /* 6,7 are implementation dependent */
3764 rn
= "Invalid config selector";
3781 tcg_gen_helper_0_1i(do_mtc0_watchlo
, t0
, sel
);
3791 tcg_gen_helper_0_1i(do_mtc0_watchhi
, t0
, sel
);
3801 #if defined(TARGET_MIPS64)
3802 check_insn(env
, ctx
, ISA_MIPS3
);
3803 tcg_gen_helper_0_1(do_mtc0_xcontext
, t0
);
3812 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3815 tcg_gen_helper_0_1(do_mtc0_framemask
, t0
);
3824 rn
= "Diagnostic"; /* implementation dependent */
3829 tcg_gen_helper_0_1(do_mtc0_debug
, t0
); /* EJTAG support */
3830 /* BS_STOP isn't good enough here, hflags may have changed. */
3831 gen_save_pc(ctx
->pc
+ 4);
3832 ctx
->bstate
= BS_EXCP
;
3836 // tcg_gen_helper_0_1(do_mtc0_tracecontrol, t0); /* PDtrace support */
3837 rn
= "TraceControl";
3838 /* Stop translation as we may have switched the execution mode */
3839 ctx
->bstate
= BS_STOP
;
3842 // tcg_gen_helper_0_1(do_mtc0_tracecontrol2, t0); /* PDtrace support */
3843 rn
= "TraceControl2";
3844 /* Stop translation as we may have switched the execution mode */
3845 ctx
->bstate
= BS_STOP
;
3848 /* Stop translation as we may have switched the execution mode */
3849 ctx
->bstate
= BS_STOP
;
3850 // tcg_gen_helper_0_1(do_mtc0_usertracedata, t0); /* PDtrace support */
3851 rn
= "UserTraceData";
3852 /* Stop translation as we may have switched the execution mode */
3853 ctx
->bstate
= BS_STOP
;
3856 // tcg_gen_helper_0_1(do_mtc0_tracebpc, t0); /* PDtrace support */
3857 /* Stop translation as we may have switched the execution mode */
3858 ctx
->bstate
= BS_STOP
;
3869 gen_mtc0_store64(t0
, offsetof(CPUState
, CP0_DEPC
));
3879 tcg_gen_helper_0_1(do_mtc0_performance0
, t0
);
3880 rn
= "Performance0";
3883 // tcg_gen_helper_0_1(do_mtc0_performance1, t0);
3884 rn
= "Performance1";
3887 // tcg_gen_helper_0_1(do_mtc0_performance2, t0);
3888 rn
= "Performance2";
3891 // tcg_gen_helper_0_1(do_mtc0_performance3, t0);
3892 rn
= "Performance3";
3895 // tcg_gen_helper_0_1(do_mtc0_performance4, t0);
3896 rn
= "Performance4";
3899 // tcg_gen_helper_0_1(do_mtc0_performance5, t0);
3900 rn
= "Performance5";
3903 // tcg_gen_helper_0_1(do_mtc0_performance6, t0);
3904 rn
= "Performance6";
3907 // tcg_gen_helper_0_1(do_mtc0_performance7, t0);
3908 rn
= "Performance7";
3934 tcg_gen_helper_0_1(do_mtc0_taglo
, t0
);
3941 tcg_gen_helper_0_1(do_mtc0_datalo
, t0
);
3954 tcg_gen_helper_0_1(do_mtc0_taghi
, t0
);
3961 tcg_gen_helper_0_1(do_mtc0_datahi
, t0
);
3972 gen_mtc0_store64(t0
, offsetof(CPUState
, CP0_ErrorEPC
));
3983 gen_mtc0_store32(t0
, offsetof(CPUState
, CP0_DESAVE
));
3989 /* Stop translation as we may have switched the execution mode */
3990 ctx
->bstate
= BS_STOP
;
3995 #if defined MIPS_DEBUG_DISAS
3996 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3997 fprintf(logfile
, "mtc0 %s (reg %d sel %d)\n",
4001 /* For simplicitly assume that all writes can cause interrupts. */
4004 ctx
->bstate
= BS_STOP
;
4009 #if defined MIPS_DEBUG_DISAS
4010 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4011 fprintf(logfile
, "mtc0 %s (reg %d sel %d)\n",
4015 generate_exception(ctx
, EXCP_RI
);
4018 #if defined(TARGET_MIPS64)
4019 static void gen_dmfc0 (CPUState
*env
, DisasContext
*ctx
, TCGv t0
, int reg
, int sel
)
4021 const char *rn
= "invalid";
4024 check_insn(env
, ctx
, ISA_MIPS64
);
4030 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Index
));
4034 check_insn(env
, ctx
, ASE_MT
);
4035 tcg_gen_helper_1_0(do_mfc0_mvpcontrol
, t0
);
4039 check_insn(env
, ctx
, ASE_MT
);
4040 tcg_gen_helper_1_0(do_mfc0_mvpconf0
, t0
);
4044 check_insn(env
, ctx
, ASE_MT
);
4045 tcg_gen_helper_1_0(do_mfc0_mvpconf1
, t0
);
4055 tcg_gen_helper_1_0(do_mfc0_random
, t0
);
4059 check_insn(env
, ctx
, ASE_MT
);
4060 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEControl
));
4064 check_insn(env
, ctx
, ASE_MT
);
4065 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEConf0
));
4069 check_insn(env
, ctx
, ASE_MT
);
4070 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEConf1
));
4074 check_insn(env
, ctx
, ASE_MT
);
4075 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_YQMask
));
4079 check_insn(env
, ctx
, ASE_MT
);
4080 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_VPESchedule
));
4084 check_insn(env
, ctx
, ASE_MT
);
4085 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_VPEScheFBack
));
4086 rn
= "VPEScheFBack";
4089 check_insn(env
, ctx
, ASE_MT
);
4090 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEOpt
));
4100 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryLo0
));
4104 check_insn(env
, ctx
, ASE_MT
);
4105 tcg_gen_helper_1_0(do_mfc0_tcstatus
, t0
);
4109 check_insn(env
, ctx
, ASE_MT
);
4110 tcg_gen_helper_1_0(do_mfc0_tcbind
, t0
);
4114 check_insn(env
, ctx
, ASE_MT
);
4115 tcg_gen_helper_1_0(do_dmfc0_tcrestart
, t0
);
4119 check_insn(env
, ctx
, ASE_MT
);
4120 tcg_gen_helper_1_0(do_dmfc0_tchalt
, t0
);
4124 check_insn(env
, ctx
, ASE_MT
);
4125 tcg_gen_helper_1_0(do_dmfc0_tccontext
, t0
);
4129 check_insn(env
, ctx
, ASE_MT
);
4130 tcg_gen_helper_1_0(do_dmfc0_tcschedule
, t0
);
4134 check_insn(env
, ctx
, ASE_MT
);
4135 tcg_gen_helper_1_0(do_dmfc0_tcschefback
, t0
);
4145 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryLo1
));
4155 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_Context
));
4159 // tcg_gen_helper_1_0(do_dmfc0_contextconfig, t0); /* SmartMIPS ASE */
4160 rn
= "ContextConfig";
4169 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PageMask
));
4173 check_insn(env
, ctx
, ISA_MIPS32R2
);
4174 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PageGrain
));
4184 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Wired
));
4188 check_insn(env
, ctx
, ISA_MIPS32R2
);
4189 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf0
));
4193 check_insn(env
, ctx
, ISA_MIPS32R2
);
4194 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf1
));
4198 check_insn(env
, ctx
, ISA_MIPS32R2
);
4199 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf2
));
4203 check_insn(env
, ctx
, ISA_MIPS32R2
);
4204 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf3
));
4208 check_insn(env
, ctx
, ISA_MIPS32R2
);
4209 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf4
));
4219 check_insn(env
, ctx
, ISA_MIPS32R2
);
4220 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_HWREna
));
4230 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_BadVAddr
));
4240 /* Mark as an IO operation because we read the time. */
4243 tcg_gen_helper_1_0(do_mfc0_count
, t0
);
4246 ctx
->bstate
= BS_STOP
;
4250 /* 6,7 are implementation dependent */
4258 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryHi
));
4268 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Compare
));
4271 /* 6,7 are implementation dependent */
4279 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Status
));
4283 check_insn(env
, ctx
, ISA_MIPS32R2
);
4284 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_IntCtl
));
4288 check_insn(env
, ctx
, ISA_MIPS32R2
);
4289 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSCtl
));
4293 check_insn(env
, ctx
, ISA_MIPS32R2
);
4294 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSMap
));
4304 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Cause
));
4314 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
4324 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PRid
));
4328 check_insn(env
, ctx
, ISA_MIPS32R2
);
4329 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_EBase
));
4339 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config0
));
4343 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config1
));
4347 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config2
));
4351 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config3
));
4354 /* 6,7 are implementation dependent */
4356 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config6
));
4360 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config7
));
4370 tcg_gen_helper_1_0(do_dmfc0_lladdr
, t0
);
4380 tcg_gen_helper_1_i(do_dmfc0_watchlo
, t0
, sel
);
4390 tcg_gen_helper_1_i(do_mfc0_watchhi
, t0
, sel
);
4400 check_insn(env
, ctx
, ISA_MIPS3
);
4401 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_XContext
));
4409 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4412 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Framemask
));
4421 rn
= "'Diagnostic"; /* implementation dependent */
4426 tcg_gen_helper_1_0(do_mfc0_debug
, t0
); /* EJTAG support */
4430 // tcg_gen_helper_1_0(do_dmfc0_tracecontrol, t0); /* PDtrace support */
4431 rn
= "TraceControl";
4434 // tcg_gen_helper_1_0(do_dmfc0_tracecontrol2, t0); /* PDtrace support */
4435 rn
= "TraceControl2";
4438 // tcg_gen_helper_1_0(do_dmfc0_usertracedata, t0); /* PDtrace support */
4439 rn
= "UserTraceData";
4442 // tcg_gen_helper_1_0(do_dmfc0_tracebpc, t0); /* PDtrace support */
4453 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
4463 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Performance0
));
4464 rn
= "Performance0";
4467 // tcg_gen_helper_1_0(do_dmfc0_performance1, t0);
4468 rn
= "Performance1";
4471 // tcg_gen_helper_1_0(do_dmfc0_performance2, t0);
4472 rn
= "Performance2";
4475 // tcg_gen_helper_1_0(do_dmfc0_performance3, t0);
4476 rn
= "Performance3";
4479 // tcg_gen_helper_1_0(do_dmfc0_performance4, t0);
4480 rn
= "Performance4";
4483 // tcg_gen_helper_1_0(do_dmfc0_performance5, t0);
4484 rn
= "Performance5";
4487 // tcg_gen_helper_1_0(do_dmfc0_performance6, t0);
4488 rn
= "Performance6";
4491 // tcg_gen_helper_1_0(do_dmfc0_performance7, t0);
4492 rn
= "Performance7";
4517 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_TagLo
));
4524 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DataLo
));
4537 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_TagHi
));
4544 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DataHi
));
4554 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
4565 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DESAVE
));
4575 #if defined MIPS_DEBUG_DISAS
4576 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4577 fprintf(logfile
, "dmfc0 %s (reg %d sel %d)\n",
4584 #if defined MIPS_DEBUG_DISAS
4585 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4586 fprintf(logfile
, "dmfc0 %s (reg %d sel %d)\n",
4590 generate_exception(ctx
, EXCP_RI
);
4593 static void gen_dmtc0 (CPUState
*env
, DisasContext
*ctx
, TCGv t0
, int reg
, int sel
)
4595 const char *rn
= "invalid";
4598 check_insn(env
, ctx
, ISA_MIPS64
);
4607 tcg_gen_helper_0_1(do_mtc0_index
, t0
);
4611 check_insn(env
, ctx
, ASE_MT
);
4612 tcg_gen_helper_0_1(do_mtc0_mvpcontrol
, t0
);
4616 check_insn(env
, ctx
, ASE_MT
);
4621 check_insn(env
, ctx
, ASE_MT
);
4636 check_insn(env
, ctx
, ASE_MT
);
4637 tcg_gen_helper_0_1(do_mtc0_vpecontrol
, t0
);
4641 check_insn(env
, ctx
, ASE_MT
);
4642 tcg_gen_helper_0_1(do_mtc0_vpeconf0
, t0
);
4646 check_insn(env
, ctx
, ASE_MT
);
4647 tcg_gen_helper_0_1(do_mtc0_vpeconf1
, t0
);
4651 check_insn(env
, ctx
, ASE_MT
);
4652 tcg_gen_helper_0_1(do_mtc0_yqmask
, t0
);
4656 check_insn(env
, ctx
, ASE_MT
);
4657 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_VPESchedule
));
4661 check_insn(env
, ctx
, ASE_MT
);
4662 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_VPEScheFBack
));
4663 rn
= "VPEScheFBack";
4666 check_insn(env
, ctx
, ASE_MT
);
4667 tcg_gen_helper_0_1(do_mtc0_vpeopt
, t0
);
4677 tcg_gen_helper_0_1(do_mtc0_entrylo0
, t0
);
4681 check_insn(env
, ctx
, ASE_MT
);
4682 tcg_gen_helper_0_1(do_mtc0_tcstatus
, t0
);
4686 check_insn(env
, ctx
, ASE_MT
);
4687 tcg_gen_helper_0_1(do_mtc0_tcbind
, t0
);
4691 check_insn(env
, ctx
, ASE_MT
);
4692 tcg_gen_helper_0_1(do_mtc0_tcrestart
, t0
);
4696 check_insn(env
, ctx
, ASE_MT
);
4697 tcg_gen_helper_0_1(do_mtc0_tchalt
, t0
);
4701 check_insn(env
, ctx
, ASE_MT
);
4702 tcg_gen_helper_0_1(do_mtc0_tccontext
, t0
);
4706 check_insn(env
, ctx
, ASE_MT
);
4707 tcg_gen_helper_0_1(do_mtc0_tcschedule
, t0
);
4711 check_insn(env
, ctx
, ASE_MT
);
4712 tcg_gen_helper_0_1(do_mtc0_tcschefback
, t0
);
4722 tcg_gen_helper_0_1(do_mtc0_entrylo1
, t0
);
4732 tcg_gen_helper_0_1(do_mtc0_context
, t0
);
4736 // tcg_gen_helper_0_1(do_mtc0_contextconfig, t0); /* SmartMIPS ASE */
4737 rn
= "ContextConfig";
4746 tcg_gen_helper_0_1(do_mtc0_pagemask
, t0
);
4750 check_insn(env
, ctx
, ISA_MIPS32R2
);
4751 tcg_gen_helper_0_1(do_mtc0_pagegrain
, t0
);
4761 tcg_gen_helper_0_1(do_mtc0_wired
, t0
);
4765 check_insn(env
, ctx
, ISA_MIPS32R2
);
4766 tcg_gen_helper_0_1(do_mtc0_srsconf0
, t0
);
4770 check_insn(env
, ctx
, ISA_MIPS32R2
);
4771 tcg_gen_helper_0_1(do_mtc0_srsconf1
, t0
);
4775 check_insn(env
, ctx
, ISA_MIPS32R2
);
4776 tcg_gen_helper_0_1(do_mtc0_srsconf2
, t0
);
4780 check_insn(env
, ctx
, ISA_MIPS32R2
);
4781 tcg_gen_helper_0_1(do_mtc0_srsconf3
, t0
);
4785 check_insn(env
, ctx
, ISA_MIPS32R2
);
4786 tcg_gen_helper_0_1(do_mtc0_srsconf4
, t0
);
4796 check_insn(env
, ctx
, ISA_MIPS32R2
);
4797 tcg_gen_helper_0_1(do_mtc0_hwrena
, t0
);
4811 tcg_gen_helper_0_1(do_mtc0_count
, t0
);
4814 /* 6,7 are implementation dependent */
4818 /* Stop translation as we may have switched the execution mode */
4819 ctx
->bstate
= BS_STOP
;
4824 tcg_gen_helper_0_1(do_mtc0_entryhi
, t0
);
4834 tcg_gen_helper_0_1(do_mtc0_compare
, t0
);
4837 /* 6,7 are implementation dependent */
4841 /* Stop translation as we may have switched the execution mode */
4842 ctx
->bstate
= BS_STOP
;
4847 tcg_gen_helper_0_1(do_mtc0_status
, t0
);
4848 /* BS_STOP isn't good enough here, hflags may have changed. */
4849 gen_save_pc(ctx
->pc
+ 4);
4850 ctx
->bstate
= BS_EXCP
;
4854 check_insn(env
, ctx
, ISA_MIPS32R2
);
4855 tcg_gen_helper_0_1(do_mtc0_intctl
, t0
);
4856 /* Stop translation as we may have switched the execution mode */
4857 ctx
->bstate
= BS_STOP
;
4861 check_insn(env
, ctx
, ISA_MIPS32R2
);
4862 tcg_gen_helper_0_1(do_mtc0_srsctl
, t0
);
4863 /* Stop translation as we may have switched the execution mode */
4864 ctx
->bstate
= BS_STOP
;
4868 check_insn(env
, ctx
, ISA_MIPS32R2
);
4869 gen_mtc0_store32(t0
, offsetof(CPUState
, CP0_SRSMap
));
4870 /* Stop translation as we may have switched the execution mode */
4871 ctx
->bstate
= BS_STOP
;
4881 tcg_gen_helper_0_1(do_mtc0_cause
, t0
);
4887 /* Stop translation as we may have switched the execution mode */
4888 ctx
->bstate
= BS_STOP
;
4893 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
4907 check_insn(env
, ctx
, ISA_MIPS32R2
);
4908 tcg_gen_helper_0_1(do_mtc0_ebase
, t0
);
4918 tcg_gen_helper_0_1(do_mtc0_config0
, t0
);
4920 /* Stop translation as we may have switched the execution mode */
4921 ctx
->bstate
= BS_STOP
;
4928 tcg_gen_helper_0_1(do_mtc0_config2
, t0
);
4930 /* Stop translation as we may have switched the execution mode */
4931 ctx
->bstate
= BS_STOP
;
4937 /* 6,7 are implementation dependent */
4939 rn
= "Invalid config selector";
4956 tcg_gen_helper_0_1i(do_mtc0_watchlo
, t0
, sel
);
4966 tcg_gen_helper_0_1i(do_mtc0_watchhi
, t0
, sel
);
4976 check_insn(env
, ctx
, ISA_MIPS3
);
4977 tcg_gen_helper_0_1(do_mtc0_xcontext
, t0
);
4985 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4988 tcg_gen_helper_0_1(do_mtc0_framemask
, t0
);
4997 rn
= "Diagnostic"; /* implementation dependent */
5002 tcg_gen_helper_0_1(do_mtc0_debug
, t0
); /* EJTAG support */
5003 /* BS_STOP isn't good enough here, hflags may have changed. */
5004 gen_save_pc(ctx
->pc
+ 4);
5005 ctx
->bstate
= BS_EXCP
;
5009 // tcg_gen_helper_0_1(do_mtc0_tracecontrol, t0); /* PDtrace support */
5010 /* Stop translation as we may have switched the execution mode */
5011 ctx
->bstate
= BS_STOP
;
5012 rn
= "TraceControl";
5015 // tcg_gen_helper_0_1(do_mtc0_tracecontrol2, t0); /* PDtrace support */
5016 /* Stop translation as we may have switched the execution mode */
5017 ctx
->bstate
= BS_STOP
;
5018 rn
= "TraceControl2";
5021 // tcg_gen_helper_0_1(do_mtc0_usertracedata, t0); /* PDtrace support */
5022 /* Stop translation as we may have switched the execution mode */
5023 ctx
->bstate
= BS_STOP
;
5024 rn
= "UserTraceData";
5027 // tcg_gen_helper_0_1(do_mtc0_tracebpc, t0); /* PDtrace support */
5028 /* Stop translation as we may have switched the execution mode */
5029 ctx
->bstate
= BS_STOP
;
5040 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
5050 tcg_gen_helper_0_1(do_mtc0_performance0
, t0
);
5051 rn
= "Performance0";
5054 // tcg_gen_helper_0_1(do_mtc0_performance1, t0);
5055 rn
= "Performance1";
5058 // tcg_gen_helper_0_1(do_mtc0_performance2, t0);
5059 rn
= "Performance2";
5062 // tcg_gen_helper_0_1(do_mtc0_performance3, t0);
5063 rn
= "Performance3";
5066 // tcg_gen_helper_0_1(do_mtc0_performance4, t0);
5067 rn
= "Performance4";
5070 // tcg_gen_helper_0_1(do_mtc0_performance5, t0);
5071 rn
= "Performance5";
5074 // tcg_gen_helper_0_1(do_mtc0_performance6, t0);
5075 rn
= "Performance6";
5078 // tcg_gen_helper_0_1(do_mtc0_performance7, t0);
5079 rn
= "Performance7";
5105 tcg_gen_helper_0_1(do_mtc0_taglo
, t0
);
5112 tcg_gen_helper_0_1(do_mtc0_datalo
, t0
);
5125 tcg_gen_helper_0_1(do_mtc0_taghi
, t0
);
5132 tcg_gen_helper_0_1(do_mtc0_datahi
, t0
);
5143 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
5154 gen_mtc0_store32(t0
, offsetof(CPUState
, CP0_DESAVE
));
5160 /* Stop translation as we may have switched the execution mode */
5161 ctx
->bstate
= BS_STOP
;
5166 #if defined MIPS_DEBUG_DISAS
5167 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
5168 fprintf(logfile
, "dmtc0 %s (reg %d sel %d)\n",
5173 /* For simplicitly assume that all writes can cause interrupts. */
5176 ctx
->bstate
= BS_STOP
;
5182 #if defined MIPS_DEBUG_DISAS
5183 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
5184 fprintf(logfile
, "dmtc0 %s (reg %d sel %d)\n",
5188 generate_exception(ctx
, EXCP_RI
);
5190 #endif /* TARGET_MIPS64 */
5192 static void gen_mftr(CPUState
*env
, DisasContext
*ctx
, int rt
, int rd
,
5193 int u
, int sel
, int h
)
5195 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
5196 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
5198 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
5199 ((env
->tcs
[other_tc
].CP0_TCBind
& (0xf << CP0TCBd_CurVPE
)) !=
5200 (env
->active_tc
.CP0_TCBind
& (0xf << CP0TCBd_CurVPE
))))
5201 tcg_gen_movi_tl(t0
, -1);
5202 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
5203 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
5204 tcg_gen_movi_tl(t0
, -1);
5210 tcg_gen_helper_1_1(do_mftc0_tcstatus
, t0
, t0
);
5213 tcg_gen_helper_1_1(do_mftc0_tcbind
, t0
, t0
);
5216 tcg_gen_helper_1_1(do_mftc0_tcrestart
, t0
, t0
);
5219 tcg_gen_helper_1_1(do_mftc0_tchalt
, t0
, t0
);
5222 tcg_gen_helper_1_1(do_mftc0_tccontext
, t0
, t0
);
5225 tcg_gen_helper_1_1(do_mftc0_tcschedule
, t0
, t0
);
5228 tcg_gen_helper_1_1(do_mftc0_tcschefback
, t0
, t0
);
5231 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5238 tcg_gen_helper_1_1(do_mftc0_entryhi
, t0
, t0
);
5241 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5247 tcg_gen_helper_1_1(do_mftc0_status
, t0
, t0
);
5250 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5256 tcg_gen_helper_1_1(do_mftc0_debug
, t0
, t0
);
5259 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5264 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5266 } else switch (sel
) {
5267 /* GPR registers. */
5269 tcg_gen_helper_1_1i(do_mftgpr
, t0
, t0
, rt
);
5271 /* Auxiliary CPU registers */
5275 tcg_gen_helper_1_1i(do_mftlo
, t0
, t0
, 0);
5278 tcg_gen_helper_1_1i(do_mfthi
, t0
, t0
, 0);
5281 tcg_gen_helper_1_1i(do_mftacx
, t0
, t0
, 0);
5284 tcg_gen_helper_1_1i(do_mftlo
, t0
, t0
, 1);
5287 tcg_gen_helper_1_1i(do_mfthi
, t0
, t0
, 1);
5290 tcg_gen_helper_1_1i(do_mftacx
, t0
, t0
, 1);
5293 tcg_gen_helper_1_1i(do_mftlo
, t0
, t0
, 2);
5296 tcg_gen_helper_1_1i(do_mfthi
, t0
, t0
, 2);
5299 tcg_gen_helper_1_1i(do_mftacx
, t0
, t0
, 2);
5302 tcg_gen_helper_1_1i(do_mftlo
, t0
, t0
, 3);
5305 tcg_gen_helper_1_1i(do_mfthi
, t0
, t0
, 3);
5308 tcg_gen_helper_1_1i(do_mftacx
, t0
, t0
, 3);
5311 tcg_gen_helper_1_1(do_mftdsp
, t0
, t0
);
5317 /* Floating point (COP1). */
5319 /* XXX: For now we support only a single FPU context. */
5321 gen_load_fpr32(fpu32_T
[0], rt
);
5322 tcg_gen_ext_i32_tl(t0
, fpu32_T
[0]);
5324 gen_load_fpr32h(fpu32h_T
[0], rt
);
5325 tcg_gen_ext_i32_tl(t0
, fpu32h_T
[0]);
5329 /* XXX: For now we support only a single FPU context. */
5330 tcg_gen_helper_1_1i(do_cfc1
, t0
, t0
, rt
);
5332 /* COP2: Not implemented. */
5339 #if defined MIPS_DEBUG_DISAS
5340 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
5341 fprintf(logfile
, "mftr (reg %d u %d sel %d h %d)\n",
5345 gen_store_gpr(t0
, rd
);
5351 #if defined MIPS_DEBUG_DISAS
5352 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
5353 fprintf(logfile
, "mftr (reg %d u %d sel %d h %d)\n",
5357 generate_exception(ctx
, EXCP_RI
);
5360 static void gen_mttr(CPUState
*env
, DisasContext
*ctx
, int rd
, int rt
,
5361 int u
, int sel
, int h
)
5363 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
5364 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
5366 gen_load_gpr(t0
, rt
);
5367 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
5368 ((env
->tcs
[other_tc
].CP0_TCBind
& (0xf << CP0TCBd_CurVPE
)) !=
5369 (env
->active_tc
.CP0_TCBind
& (0xf << CP0TCBd_CurVPE
))))
5371 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
5372 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
5379 tcg_gen_helper_0_1(do_mttc0_tcstatus
, t0
);
5382 tcg_gen_helper_0_1(do_mttc0_tcbind
, t0
);
5385 tcg_gen_helper_0_1(do_mttc0_tcrestart
, t0
);
5388 tcg_gen_helper_0_1(do_mttc0_tchalt
, t0
);
5391 tcg_gen_helper_0_1(do_mttc0_tccontext
, t0
);
5394 tcg_gen_helper_0_1(do_mttc0_tcschedule
, t0
);
5397 tcg_gen_helper_0_1(do_mttc0_tcschefback
, t0
);
5400 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5407 tcg_gen_helper_0_1(do_mttc0_entryhi
, t0
);
5410 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5416 tcg_gen_helper_0_1(do_mttc0_status
, t0
);
5419 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5425 tcg_gen_helper_0_1(do_mttc0_debug
, t0
);
5428 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5433 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5435 } else switch (sel
) {
5436 /* GPR registers. */
5438 tcg_gen_helper_0_1i(do_mttgpr
, t0
, rd
);
5440 /* Auxiliary CPU registers */
5444 tcg_gen_helper_0_1i(do_mttlo
, t0
, 0);
5447 tcg_gen_helper_0_1i(do_mtthi
, t0
, 0);
5450 tcg_gen_helper_0_1i(do_mttacx
, t0
, 0);
5453 tcg_gen_helper_0_1i(do_mttlo
, t0
, 1);
5456 tcg_gen_helper_0_1i(do_mtthi
, t0
, 1);
5459 tcg_gen_helper_0_1i(do_mttacx
, t0
, 1);
5462 tcg_gen_helper_0_1i(do_mttlo
, t0
, 2);
5465 tcg_gen_helper_0_1i(do_mtthi
, t0
, 2);
5468 tcg_gen_helper_0_1i(do_mttacx
, t0
, 2);
5471 tcg_gen_helper_0_1i(do_mttlo
, t0
, 3);
5474 tcg_gen_helper_0_1i(do_mtthi
, t0
, 3);
5477 tcg_gen_helper_0_1i(do_mttacx
, t0
, 3);
5480 tcg_gen_helper_0_1(do_mttdsp
, t0
);
5486 /* Floating point (COP1). */
5488 /* XXX: For now we support only a single FPU context. */
5490 tcg_gen_trunc_tl_i32(fpu32_T
[0], t0
);
5491 gen_store_fpr32(fpu32_T
[0], rd
);
5493 tcg_gen_trunc_tl_i32(fpu32h_T
[0], t0
);
5494 gen_store_fpr32h(fpu32h_T
[0], rd
);
5498 /* XXX: For now we support only a single FPU context. */
5499 tcg_gen_helper_0_1i(do_ctc1
, t0
, rd
);
5501 /* COP2: Not implemented. */
5508 #if defined MIPS_DEBUG_DISAS
5509 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
5510 fprintf(logfile
, "mttr (reg %d u %d sel %d h %d)\n",
5519 #if defined MIPS_DEBUG_DISAS
5520 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
5521 fprintf(logfile
, "mttr (reg %d u %d sel %d h %d)\n",
5525 generate_exception(ctx
, EXCP_RI
);
5528 static void gen_cp0 (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
, int rt
, int rd
)
5530 const char *opn
= "ldst";
5539 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
5541 gen_mfc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5542 gen_store_gpr(t0
, rt
);
5549 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
5551 gen_load_gpr(t0
, rt
);
5552 save_cpu_state(ctx
, 1);
5553 gen_mtc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5558 #if defined(TARGET_MIPS64)
5560 check_insn(env
, ctx
, ISA_MIPS3
);
5566 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
5568 gen_dmfc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5569 gen_store_gpr(t0
, rt
);
5575 check_insn(env
, ctx
, ISA_MIPS3
);
5577 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
5579 gen_load_gpr(t0
, rt
);
5580 save_cpu_state(ctx
, 1);
5581 gen_dmtc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5588 check_insn(env
, ctx
, ASE_MT
);
5593 gen_mftr(env
, ctx
, rt
, rd
, (ctx
->opcode
>> 5) & 1,
5594 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
5598 check_insn(env
, ctx
, ASE_MT
);
5599 gen_mttr(env
, ctx
, rd
, rt
, (ctx
->opcode
>> 5) & 1,
5600 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
5605 if (!env
->tlb
->do_tlbwi
)
5607 tcg_gen_helper_0_0(env
->tlb
->do_tlbwi
);
5611 if (!env
->tlb
->do_tlbwr
)
5613 tcg_gen_helper_0_0(env
->tlb
->do_tlbwr
);
5617 if (!env
->tlb
->do_tlbp
)
5619 tcg_gen_helper_0_0(env
->tlb
->do_tlbp
);
5623 if (!env
->tlb
->do_tlbr
)
5625 tcg_gen_helper_0_0(env
->tlb
->do_tlbr
);
5629 check_insn(env
, ctx
, ISA_MIPS2
);
5630 save_cpu_state(ctx
, 1);
5631 tcg_gen_helper_0_0(do_eret
);
5632 ctx
->bstate
= BS_EXCP
;
5636 check_insn(env
, ctx
, ISA_MIPS32
);
5637 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
5639 generate_exception(ctx
, EXCP_RI
);
5641 save_cpu_state(ctx
, 1);
5642 tcg_gen_helper_0_0(do_deret
);
5643 ctx
->bstate
= BS_EXCP
;
5648 check_insn(env
, ctx
, ISA_MIPS3
| ISA_MIPS32
);
5649 /* If we get an exception, we want to restart at next instruction */
5651 save_cpu_state(ctx
, 1);
5653 tcg_gen_helper_0_0(do_wait
);
5654 ctx
->bstate
= BS_EXCP
;
5659 generate_exception(ctx
, EXCP_RI
);
5662 MIPS_DEBUG("%s %s %d", opn
, regnames
[rt
], rd
);
5664 #endif /* !CONFIG_USER_ONLY */
5666 /* CP1 Branches (before delay slot) */
5667 static void gen_compute_branch1 (CPUState
*env
, DisasContext
*ctx
, uint32_t op
,
5668 int32_t cc
, int32_t offset
)
5670 target_ulong btarget
;
5671 const char *opn
= "cp1 cond branch";
5672 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
5673 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
5676 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
5678 btarget
= ctx
->pc
+ 4 + offset
;
5683 int l1
= gen_new_label();
5684 int l2
= gen_new_label();
5685 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
5687 get_fp_cond(r_tmp1
);
5688 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
5689 tcg_temp_free(r_tmp1
);
5690 tcg_gen_not_tl(t0
, t0
);
5691 tcg_gen_movi_tl(t1
, 0x1 << cc
);
5692 tcg_gen_and_tl(t0
, t0
, t1
);
5693 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
5694 tcg_gen_movi_tl(t0
, 0);
5697 tcg_gen_movi_tl(t0
, 1);
5704 int l1
= gen_new_label();
5705 int l2
= gen_new_label();
5706 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
5708 get_fp_cond(r_tmp1
);
5709 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
5710 tcg_temp_free(r_tmp1
);
5711 tcg_gen_not_tl(t0
, t0
);
5712 tcg_gen_movi_tl(t1
, 0x1 << cc
);
5713 tcg_gen_and_tl(t0
, t0
, t1
);
5714 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
5715 tcg_gen_movi_tl(t0
, 0);
5718 tcg_gen_movi_tl(t0
, 1);
5725 int l1
= gen_new_label();
5726 int l2
= gen_new_label();
5727 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
5729 get_fp_cond(r_tmp1
);
5730 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
5731 tcg_temp_free(r_tmp1
);
5732 tcg_gen_movi_tl(t1
, 0x1 << cc
);
5733 tcg_gen_and_tl(t0
, t0
, t1
);
5734 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
5735 tcg_gen_movi_tl(t0
, 0);
5738 tcg_gen_movi_tl(t0
, 1);
5745 int l1
= gen_new_label();
5746 int l2
= gen_new_label();
5747 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
5749 get_fp_cond(r_tmp1
);
5750 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
5751 tcg_temp_free(r_tmp1
);
5752 tcg_gen_movi_tl(t1
, 0x1 << cc
);
5753 tcg_gen_and_tl(t0
, t0
, t1
);
5754 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
5755 tcg_gen_movi_tl(t0
, 0);
5758 tcg_gen_movi_tl(t0
, 1);
5763 ctx
->hflags
|= MIPS_HFLAG_BL
;
5764 tcg_gen_trunc_tl_i32(bcond
, t0
);
5768 int l1
= gen_new_label();
5769 int l2
= gen_new_label();
5770 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
5772 get_fp_cond(r_tmp1
);
5773 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
5774 tcg_temp_free(r_tmp1
);
5775 tcg_gen_not_tl(t0
, t0
);
5776 tcg_gen_movi_tl(t1
, 0x3 << cc
);
5777 tcg_gen_and_tl(t0
, t0
, t1
);
5778 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
5779 tcg_gen_movi_tl(t0
, 0);
5782 tcg_gen_movi_tl(t0
, 1);
5789 int l1
= gen_new_label();
5790 int l2
= gen_new_label();
5791 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
5793 get_fp_cond(r_tmp1
);
5794 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
5795 tcg_temp_free(r_tmp1
);
5796 tcg_gen_movi_tl(t1
, 0x3 << cc
);
5797 tcg_gen_and_tl(t0
, t0
, t1
);
5798 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
5799 tcg_gen_movi_tl(t0
, 0);
5802 tcg_gen_movi_tl(t0
, 1);
5809 int l1
= gen_new_label();
5810 int l2
= gen_new_label();
5811 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
5813 get_fp_cond(r_tmp1
);
5814 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
5815 tcg_temp_free(r_tmp1
);
5816 tcg_gen_not_tl(t0
, t0
);
5817 tcg_gen_movi_tl(t1
, 0xf << cc
);
5818 tcg_gen_and_tl(t0
, t0
, t1
);
5819 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
5820 tcg_gen_movi_tl(t0
, 0);
5823 tcg_gen_movi_tl(t0
, 1);
5830 int l1
= gen_new_label();
5831 int l2
= gen_new_label();
5832 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
5834 get_fp_cond(r_tmp1
);
5835 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
5836 tcg_temp_free(r_tmp1
);
5837 tcg_gen_movi_tl(t1
, 0xf << cc
);
5838 tcg_gen_and_tl(t0
, t0
, t1
);
5839 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
5840 tcg_gen_movi_tl(t0
, 0);
5843 tcg_gen_movi_tl(t0
, 1);
5848 ctx
->hflags
|= MIPS_HFLAG_BC
;
5849 tcg_gen_trunc_tl_i32(bcond
, t0
);
5853 generate_exception (ctx
, EXCP_RI
);
5856 MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx
, opn
,
5857 ctx
->hflags
, btarget
);
5858 ctx
->btarget
= btarget
;
5865 /* Coprocessor 1 (FPU) */
5867 #define FOP(func, fmt) (((fmt) << 21) | (func))
5869 static void gen_cp1 (DisasContext
*ctx
, uint32_t opc
, int rt
, int fs
)
5871 const char *opn
= "cp1 move";
5872 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
5876 gen_load_fpr32(fpu32_T
[0], fs
);
5877 tcg_gen_ext_i32_tl(t0
, fpu32_T
[0]);
5878 gen_store_gpr(t0
, rt
);
5882 gen_load_gpr(t0
, rt
);
5883 tcg_gen_trunc_tl_i32(fpu32_T
[0], t0
);
5884 gen_store_fpr32(fpu32_T
[0], fs
);
5888 tcg_gen_helper_1_i(do_cfc1
, t0
, fs
);
5889 gen_store_gpr(t0
, rt
);
5893 gen_load_gpr(t0
, rt
);
5894 tcg_gen_helper_0_1i(do_ctc1
, t0
, fs
);
5898 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
5899 tcg_gen_mov_tl(t0
, fpu64_T
[0]);
5900 gen_store_gpr(t0
, rt
);
5904 gen_load_gpr(t0
, rt
);
5905 tcg_gen_mov_tl(fpu64_T
[0], t0
);
5906 gen_store_fpr64(ctx
, fpu64_T
[0], fs
);
5910 gen_load_fpr32h(fpu32h_T
[0], fs
);
5911 tcg_gen_ext_i32_tl(t0
, fpu32h_T
[0]);
5912 gen_store_gpr(t0
, rt
);
5916 gen_load_gpr(t0
, rt
);
5917 tcg_gen_trunc_tl_i32(fpu32h_T
[0], t0
);
5918 gen_store_fpr32h(fpu32h_T
[0], fs
);
5923 generate_exception (ctx
, EXCP_RI
);
5926 MIPS_DEBUG("%s %s %s", opn
, regnames
[rt
], fregnames
[fs
]);
5932 static void gen_movci (DisasContext
*ctx
, int rd
, int rs
, int cc
, int tf
)
5934 int l1
= gen_new_label();
5937 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
5938 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
5941 ccbit
= 1 << (24 + cc
);
5949 gen_load_gpr(t0
, rd
);
5950 gen_load_gpr(t1
, rs
);
5952 TCGv r_ptr
= tcg_temp_new(TCG_TYPE_PTR
);
5953 TCGv r_tmp
= tcg_temp_local_new(TCG_TYPE_I32
);
5955 tcg_gen_ld_ptr(r_ptr
, cpu_env
, offsetof(CPUState
, fpu
));
5956 tcg_gen_ld_i32(r_tmp
, r_ptr
, offsetof(CPUMIPSFPUContext
, fcr31
));
5957 tcg_temp_free(r_ptr
);
5958 tcg_gen_andi_i32(r_tmp
, r_tmp
, ccbit
);
5959 tcg_gen_brcondi_i32(cond
, r_tmp
, 0, l1
);
5960 tcg_temp_free(r_tmp
);
5962 tcg_gen_mov_tl(t0
, t1
);
5966 gen_store_gpr(t0
, rd
);
5970 static inline void gen_movcf_s (int cc
, int tf
)
5974 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
5975 int l1
= gen_new_label();
5978 ccbit
= 1 << (24 + cc
);
5987 tcg_gen_ld_i32(r_tmp1
, current_fpu
, offsetof(CPUMIPSFPUContext
, fcr31
));
5988 tcg_gen_andi_i32(r_tmp1
, r_tmp1
, ccbit
);
5989 tcg_gen_brcondi_i32(cond
, r_tmp1
, 0, l1
);
5990 tcg_gen_movi_i32(fpu32_T
[2], fpu32_T
[0]);
5992 tcg_temp_free(r_tmp1
);
5995 static inline void gen_movcf_d (int cc
, int tf
)
5999 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
6000 int l1
= gen_new_label();
6003 ccbit
= 1 << (24 + cc
);
6012 tcg_gen_ld_i32(r_tmp1
, current_fpu
, offsetof(CPUMIPSFPUContext
, fcr31
));
6013 tcg_gen_andi_i32(r_tmp1
, r_tmp1
, ccbit
);
6014 tcg_gen_brcondi_i32(cond
, r_tmp1
, 0, l1
);
6015 tcg_gen_movi_i64(fpu64_T
[2], fpu64_T
[0]);
6017 tcg_temp_free(r_tmp1
);
6020 static inline void gen_movcf_ps (int cc
, int tf
)
6023 TCGv r_tmp1
= tcg_temp_local_new(TCG_TYPE_I32
);
6024 TCGv r_tmp2
= tcg_temp_local_new(TCG_TYPE_I32
);
6025 int l1
= gen_new_label();
6026 int l2
= gen_new_label();
6033 get_fp_cond(r_tmp1
);
6034 tcg_gen_shri_i32(r_tmp1
, r_tmp1
, cc
);
6035 tcg_gen_andi_i32(r_tmp2
, r_tmp1
, 0x1);
6036 tcg_gen_brcondi_i32(cond
, r_tmp2
, 0, l1
);
6037 tcg_gen_movi_i32(fpu32_T
[2], fpu32_T
[0]);
6039 tcg_gen_andi_i32(r_tmp2
, r_tmp1
, 0x2);
6040 tcg_gen_brcondi_i32(cond
, r_tmp2
, 0, l2
);
6041 tcg_gen_movi_i32(fpu32h_T
[2], fpu32h_T
[0]);
6043 tcg_temp_free(r_tmp1
);
6044 tcg_temp_free(r_tmp2
);
6048 static void gen_farith (DisasContext
*ctx
, uint32_t op1
,
6049 int ft
, int fs
, int fd
, int cc
)
6051 const char *opn
= "farith";
6052 const char *condnames
[] = {
6070 const char *condnames_abs
[] = {
6088 enum { BINOP
, CMPOP
, OTHEROP
} optype
= OTHEROP
;
6089 uint32_t func
= ctx
->opcode
& 0x3f;
6091 switch (ctx
->opcode
& FOP(0x3f, 0x1f)) {
6093 gen_load_fpr32(fpu32_T
[0], fs
);
6094 gen_load_fpr32(fpu32_T
[1], ft
);
6095 tcg_gen_helper_0_0(do_float_add_s
);
6096 gen_store_fpr32(fpu32_T
[2], fd
);
6101 gen_load_fpr32(fpu32_T
[0], fs
);
6102 gen_load_fpr32(fpu32_T
[1], ft
);
6103 tcg_gen_helper_0_0(do_float_sub_s
);
6104 gen_store_fpr32(fpu32_T
[2], fd
);
6109 gen_load_fpr32(fpu32_T
[0], fs
);
6110 gen_load_fpr32(fpu32_T
[1], ft
);
6111 tcg_gen_helper_0_0(do_float_mul_s
);
6112 gen_store_fpr32(fpu32_T
[2], fd
);
6117 gen_load_fpr32(fpu32_T
[0], fs
);
6118 gen_load_fpr32(fpu32_T
[1], ft
);
6119 tcg_gen_helper_0_0(do_float_div_s
);
6120 gen_store_fpr32(fpu32_T
[2], fd
);
6125 gen_load_fpr32(fpu32_T
[0], fs
);
6126 tcg_gen_helper_0_0(do_float_sqrt_s
);
6127 gen_store_fpr32(fpu32_T
[2], fd
);
6131 gen_load_fpr32(fpu32_T
[0], fs
);
6132 tcg_gen_helper_0_0(do_float_abs_s
);
6133 gen_store_fpr32(fpu32_T
[2], fd
);
6137 gen_load_fpr32(fpu32_T
[0], fs
);
6138 gen_store_fpr32(fpu32_T
[0], fd
);
6142 gen_load_fpr32(fpu32_T
[0], fs
);
6143 tcg_gen_helper_0_0(do_float_chs_s
);
6144 gen_store_fpr32(fpu32_T
[2], fd
);
6148 check_cp1_64bitmode(ctx
);
6149 gen_load_fpr32(fpu32_T
[0], fs
);
6150 tcg_gen_helper_0_0(do_float_roundl_s
);
6151 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6155 check_cp1_64bitmode(ctx
);
6156 gen_load_fpr32(fpu32_T
[0], fs
);
6157 tcg_gen_helper_0_0(do_float_truncl_s
);
6158 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6162 check_cp1_64bitmode(ctx
);
6163 gen_load_fpr32(fpu32_T
[0], fs
);
6164 tcg_gen_helper_0_0(do_float_ceill_s
);
6165 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6169 check_cp1_64bitmode(ctx
);
6170 gen_load_fpr32(fpu32_T
[0], fs
);
6171 tcg_gen_helper_0_0(do_float_floorl_s
);
6172 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6176 gen_load_fpr32(fpu32_T
[0], fs
);
6177 tcg_gen_helper_0_0(do_float_roundw_s
);
6178 gen_store_fpr32(fpu32_T
[2], fd
);
6182 gen_load_fpr32(fpu32_T
[0], fs
);
6183 tcg_gen_helper_0_0(do_float_truncw_s
);
6184 gen_store_fpr32(fpu32_T
[2], fd
);
6188 gen_load_fpr32(fpu32_T
[0], fs
);
6189 tcg_gen_helper_0_0(do_float_ceilw_s
);
6190 gen_store_fpr32(fpu32_T
[2], fd
);
6194 gen_load_fpr32(fpu32_T
[0], fs
);
6195 tcg_gen_helper_0_0(do_float_floorw_s
);
6196 gen_store_fpr32(fpu32_T
[2], fd
);
6200 gen_load_fpr32(fpu32_T
[0], fs
);
6201 gen_load_fpr32(fpu32_T
[2], fd
);
6202 gen_movcf_s((ft
>> 2) & 0x7, ft
& 0x1);
6203 gen_store_fpr32(fpu32_T
[2], fd
);
6207 gen_load_fpr32(fpu32_T
[0], fs
);
6208 gen_load_fpr32(fpu32_T
[2], fd
);
6210 int l1
= gen_new_label();
6211 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
6213 gen_load_gpr(t0
, ft
);
6214 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
6216 tcg_gen_mov_i32(fpu32_T
[2], fpu32_T
[0]);
6219 gen_store_fpr32(fpu32_T
[2], fd
);
6223 gen_load_fpr32(fpu32_T
[0], fs
);
6224 gen_load_fpr32(fpu32_T
[2], fd
);
6226 int l1
= gen_new_label();
6227 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
6229 gen_load_gpr(t0
, ft
);
6230 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
6232 tcg_gen_mov_i32(fpu32_T
[2], fpu32_T
[0]);
6235 gen_store_fpr32(fpu32_T
[2], fd
);
6240 gen_load_fpr32(fpu32_T
[0], fs
);
6241 tcg_gen_helper_0_0(do_float_recip_s
);
6242 gen_store_fpr32(fpu32_T
[2], fd
);
6247 gen_load_fpr32(fpu32_T
[0], fs
);
6248 tcg_gen_helper_0_0(do_float_rsqrt_s
);
6249 gen_store_fpr32(fpu32_T
[2], fd
);
6253 check_cp1_64bitmode(ctx
);
6254 gen_load_fpr32(fpu32_T
[0], fs
);
6255 gen_load_fpr32(fpu32_T
[2], fd
);
6256 tcg_gen_helper_0_0(do_float_recip2_s
);
6257 gen_store_fpr32(fpu32_T
[2], fd
);
6261 check_cp1_64bitmode(ctx
);
6262 gen_load_fpr32(fpu32_T
[0], fs
);
6263 tcg_gen_helper_0_0(do_float_recip1_s
);
6264 gen_store_fpr32(fpu32_T
[2], fd
);
6268 check_cp1_64bitmode(ctx
);
6269 gen_load_fpr32(fpu32_T
[0], fs
);
6270 tcg_gen_helper_0_0(do_float_rsqrt1_s
);
6271 gen_store_fpr32(fpu32_T
[2], fd
);
6275 check_cp1_64bitmode(ctx
);
6276 gen_load_fpr32(fpu32_T
[0], fs
);
6277 gen_load_fpr32(fpu32_T
[2], ft
);
6278 tcg_gen_helper_0_0(do_float_rsqrt2_s
);
6279 gen_store_fpr32(fpu32_T
[2], fd
);
6283 check_cp1_registers(ctx
, fd
);
6284 gen_load_fpr32(fpu32_T
[0], fs
);
6285 tcg_gen_helper_0_0(do_float_cvtd_s
);
6286 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6290 gen_load_fpr32(fpu32_T
[0], fs
);
6291 tcg_gen_helper_0_0(do_float_cvtw_s
);
6292 gen_store_fpr32(fpu32_T
[2], fd
);
6296 check_cp1_64bitmode(ctx
);
6297 gen_load_fpr32(fpu32_T
[0], fs
);
6298 tcg_gen_helper_0_0(do_float_cvtl_s
);
6299 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6303 check_cp1_64bitmode(ctx
);
6304 gen_load_fpr32(fpu32_T
[0], fs
);
6305 gen_load_fpr32(fpu32_T
[1], ft
);
6306 tcg_gen_extu_i32_i64(fpu64_T
[0], fpu32_T
[0]);
6307 tcg_gen_extu_i32_i64(fpu64_T
[1], fpu32_T
[1]);
6308 tcg_gen_shli_i64(fpu64_T
[1], fpu64_T
[1], 32);
6309 tcg_gen_or_i64(fpu64_T
[2], fpu64_T
[0], fpu64_T
[1]);
6310 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6329 gen_load_fpr32(fpu32_T
[0], fs
);
6330 gen_load_fpr32(fpu32_T
[1], ft
);
6331 if (ctx
->opcode
& (1 << 6)) {
6333 gen_cmpabs_s(func
-48, cc
);
6334 opn
= condnames_abs
[func
-48];
6336 gen_cmp_s(func
-48, cc
);
6337 opn
= condnames
[func
-48];
6341 check_cp1_registers(ctx
, fs
| ft
| fd
);
6342 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6343 gen_load_fpr64(ctx
, fpu64_T
[1], ft
);
6344 tcg_gen_helper_0_0(do_float_add_d
);
6345 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6350 check_cp1_registers(ctx
, fs
| ft
| fd
);
6351 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6352 gen_load_fpr64(ctx
, fpu64_T
[1], ft
);
6353 tcg_gen_helper_0_0(do_float_sub_d
);
6354 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6359 check_cp1_registers(ctx
, fs
| ft
| fd
);
6360 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6361 gen_load_fpr64(ctx
, fpu64_T
[1], ft
);
6362 tcg_gen_helper_0_0(do_float_mul_d
);
6363 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6368 check_cp1_registers(ctx
, fs
| ft
| fd
);
6369 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6370 gen_load_fpr64(ctx
, fpu64_T
[1], ft
);
6371 tcg_gen_helper_0_0(do_float_div_d
);
6372 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6377 check_cp1_registers(ctx
, fs
| fd
);
6378 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6379 tcg_gen_helper_0_0(do_float_sqrt_d
);
6380 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6384 check_cp1_registers(ctx
, fs
| fd
);
6385 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6386 tcg_gen_helper_0_0(do_float_abs_d
);
6387 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6391 check_cp1_registers(ctx
, fs
| fd
);
6392 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6393 gen_store_fpr64(ctx
, fpu64_T
[0], fd
);
6397 check_cp1_registers(ctx
, fs
| fd
);
6398 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6399 tcg_gen_helper_0_0(do_float_chs_d
);
6400 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6404 check_cp1_64bitmode(ctx
);
6405 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6406 tcg_gen_helper_0_0(do_float_roundl_d
);
6407 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6411 check_cp1_64bitmode(ctx
);
6412 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6413 tcg_gen_helper_0_0(do_float_truncl_d
);
6414 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6418 check_cp1_64bitmode(ctx
);
6419 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6420 tcg_gen_helper_0_0(do_float_ceill_d
);
6421 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6425 check_cp1_64bitmode(ctx
);
6426 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6427 tcg_gen_helper_0_0(do_float_floorl_d
);
6428 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6432 check_cp1_registers(ctx
, fs
);
6433 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6434 tcg_gen_helper_0_0(do_float_roundw_d
);
6435 gen_store_fpr32(fpu32_T
[2], fd
);
6439 check_cp1_registers(ctx
, fs
);
6440 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6441 tcg_gen_helper_0_0(do_float_truncw_d
);
6442 gen_store_fpr32(fpu32_T
[2], fd
);
6446 check_cp1_registers(ctx
, fs
);
6447 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6448 tcg_gen_helper_0_0(do_float_ceilw_d
);
6449 gen_store_fpr32(fpu32_T
[2], fd
);
6453 check_cp1_registers(ctx
, fs
);
6454 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6455 tcg_gen_helper_0_0(do_float_floorw_d
);
6456 gen_store_fpr32(fpu32_T
[2], fd
);
6460 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6461 gen_load_fpr64(ctx
, fpu64_T
[2], fd
);
6462 gen_movcf_d((ft
>> 2) & 0x7, ft
& 0x1);
6463 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6467 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6468 gen_load_fpr64(ctx
, fpu64_T
[2], fd
);
6470 int l1
= gen_new_label();
6471 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
6473 gen_load_gpr(t0
, ft
);
6474 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
6476 tcg_gen_mov_i64(fpu64_T
[2], fpu64_T
[0]);
6479 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6483 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6484 gen_load_fpr64(ctx
, fpu64_T
[2], fd
);
6486 int l1
= gen_new_label();
6487 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
6489 gen_load_gpr(t0
, ft
);
6490 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
6492 tcg_gen_mov_i64(fpu64_T
[2], fpu64_T
[0]);
6495 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6499 check_cp1_64bitmode(ctx
);
6500 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6501 tcg_gen_helper_0_0(do_float_recip_d
);
6502 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6506 check_cp1_64bitmode(ctx
);
6507 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6508 tcg_gen_helper_0_0(do_float_rsqrt_d
);
6509 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6513 check_cp1_64bitmode(ctx
);
6514 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6515 gen_load_fpr64(ctx
, fpu64_T
[2], ft
);
6516 tcg_gen_helper_0_0(do_float_recip2_d
);
6517 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6521 check_cp1_64bitmode(ctx
);
6522 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6523 tcg_gen_helper_0_0(do_float_recip1_d
);
6524 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6528 check_cp1_64bitmode(ctx
);
6529 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6530 tcg_gen_helper_0_0(do_float_rsqrt1_d
);
6531 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6535 check_cp1_64bitmode(ctx
);
6536 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6537 gen_load_fpr64(ctx
, fpu64_T
[2], ft
);
6538 tcg_gen_helper_0_0(do_float_rsqrt2_d
);
6539 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6558 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6559 gen_load_fpr64(ctx
, fpu64_T
[1], ft
);
6560 if (ctx
->opcode
& (1 << 6)) {
6562 check_cp1_registers(ctx
, fs
| ft
);
6563 gen_cmpabs_d(func
-48, cc
);
6564 opn
= condnames_abs
[func
-48];
6566 check_cp1_registers(ctx
, fs
| ft
);
6567 gen_cmp_d(func
-48, cc
);
6568 opn
= condnames
[func
-48];
6572 check_cp1_registers(ctx
, fs
);
6573 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6574 tcg_gen_helper_0_0(do_float_cvts_d
);
6575 gen_store_fpr32(fpu32_T
[2], fd
);
6579 check_cp1_registers(ctx
, fs
);
6580 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6581 tcg_gen_helper_0_0(do_float_cvtw_d
);
6582 gen_store_fpr32(fpu32_T
[2], fd
);
6586 check_cp1_64bitmode(ctx
);
6587 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6588 tcg_gen_helper_0_0(do_float_cvtl_d
);
6589 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6593 gen_load_fpr32(fpu32_T
[0], fs
);
6594 tcg_gen_helper_0_0(do_float_cvts_w
);
6595 gen_store_fpr32(fpu32_T
[2], fd
);
6599 check_cp1_registers(ctx
, fd
);
6600 gen_load_fpr32(fpu32_T
[0], fs
);
6601 tcg_gen_helper_0_0(do_float_cvtd_w
);
6602 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6606 check_cp1_64bitmode(ctx
);
6607 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6608 tcg_gen_helper_0_0(do_float_cvts_l
);
6609 gen_store_fpr32(fpu32_T
[2], fd
);
6613 check_cp1_64bitmode(ctx
);
6614 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6615 tcg_gen_helper_0_0(do_float_cvtd_l
);
6616 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
6620 check_cp1_64bitmode(ctx
);
6621 gen_load_fpr32(fpu32_T
[0], fs
);
6622 gen_load_fpr32h(fpu32h_T
[0], fs
);
6623 tcg_gen_helper_0_0(do_float_cvtps_pw
);
6624 gen_store_fpr32(fpu32_T
[2], fd
);
6625 gen_store_fpr32h(fpu32h_T
[2], fd
);
6629 check_cp1_64bitmode(ctx
);
6630 gen_load_fpr32(fpu32_T
[0], fs
);
6631 gen_load_fpr32h(fpu32h_T
[0], fs
);
6632 gen_load_fpr32(fpu32_T
[1], ft
);
6633 gen_load_fpr32h(fpu32h_T
[1], ft
);
6634 tcg_gen_helper_0_0(do_float_add_ps
);
6635 gen_store_fpr32(fpu32_T
[2], fd
);
6636 gen_store_fpr32h(fpu32h_T
[2], fd
);
6640 check_cp1_64bitmode(ctx
);
6641 gen_load_fpr32(fpu32_T
[0], fs
);
6642 gen_load_fpr32h(fpu32h_T
[0], fs
);
6643 gen_load_fpr32(fpu32_T
[1], ft
);
6644 gen_load_fpr32h(fpu32h_T
[1], ft
);
6645 tcg_gen_helper_0_0(do_float_sub_ps
);
6646 gen_store_fpr32(fpu32_T
[2], fd
);
6647 gen_store_fpr32h(fpu32h_T
[2], fd
);
6651 check_cp1_64bitmode(ctx
);
6652 gen_load_fpr32(fpu32_T
[0], fs
);
6653 gen_load_fpr32h(fpu32h_T
[0], fs
);
6654 gen_load_fpr32(fpu32_T
[1], ft
);
6655 gen_load_fpr32h(fpu32h_T
[1], ft
);
6656 tcg_gen_helper_0_0(do_float_mul_ps
);
6657 gen_store_fpr32(fpu32_T
[2], fd
);
6658 gen_store_fpr32h(fpu32h_T
[2], fd
);
6662 check_cp1_64bitmode(ctx
);
6663 gen_load_fpr32(fpu32_T
[0], fs
);
6664 gen_load_fpr32h(fpu32h_T
[0], fs
);
6665 tcg_gen_helper_0_0(do_float_abs_ps
);
6666 gen_store_fpr32(fpu32_T
[2], fd
);
6667 gen_store_fpr32h(fpu32h_T
[2], fd
);
6671 check_cp1_64bitmode(ctx
);
6672 gen_load_fpr32(fpu32_T
[0], fs
);
6673 gen_load_fpr32h(fpu32h_T
[0], fs
);
6674 gen_store_fpr32(fpu32_T
[0], fd
);
6675 gen_store_fpr32h(fpu32h_T
[0], fd
);
6679 check_cp1_64bitmode(ctx
);
6680 gen_load_fpr32(fpu32_T
[0], fs
);
6681 gen_load_fpr32h(fpu32h_T
[0], fs
);
6682 tcg_gen_helper_0_0(do_float_chs_ps
);
6683 gen_store_fpr32(fpu32_T
[2], fd
);
6684 gen_store_fpr32h(fpu32h_T
[2], fd
);
6688 check_cp1_64bitmode(ctx
);
6689 gen_load_fpr32(fpu32_T
[0], fs
);
6690 gen_load_fpr32h(fpu32h_T
[0], fs
);
6691 gen_load_fpr32(fpu32_T
[2], fd
);
6692 gen_load_fpr32h(fpu32h_T
[2], fd
);
6693 gen_movcf_ps((ft
>> 2) & 0x7, ft
& 0x1);
6694 gen_store_fpr32(fpu32_T
[2], fd
);
6695 gen_store_fpr32h(fpu32h_T
[2], fd
);
6699 check_cp1_64bitmode(ctx
);
6700 gen_load_fpr32(fpu32_T
[0], fs
);
6701 gen_load_fpr32h(fpu32h_T
[0], fs
);
6702 gen_load_fpr32(fpu32_T
[2], fd
);
6703 gen_load_fpr32h(fpu32h_T
[2], fd
);
6705 int l1
= gen_new_label();
6706 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
6708 gen_load_gpr(t0
, ft
);
6709 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
6711 tcg_gen_mov_i32(fpu32_T
[2], fpu32_T
[0]);
6712 tcg_gen_mov_i32(fpu32h_T
[2], fpu32h_T
[0]);
6715 gen_store_fpr32(fpu32_T
[2], fd
);
6716 gen_store_fpr32h(fpu32h_T
[2], fd
);
6720 check_cp1_64bitmode(ctx
);
6721 gen_load_fpr32(fpu32_T
[0], fs
);
6722 gen_load_fpr32h(fpu32h_T
[0], fs
);
6723 gen_load_fpr32(fpu32_T
[2], fd
);
6724 gen_load_fpr32h(fpu32h_T
[2], fd
);
6726 int l1
= gen_new_label();
6727 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
6729 gen_load_gpr(t0
, ft
);
6730 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
6732 tcg_gen_mov_i32(fpu32_T
[2], fpu32_T
[0]);
6733 tcg_gen_mov_i32(fpu32h_T
[2], fpu32h_T
[0]);
6736 gen_store_fpr32(fpu32_T
[2], fd
);
6737 gen_store_fpr32h(fpu32h_T
[2], fd
);
6741 check_cp1_64bitmode(ctx
);
6742 gen_load_fpr32(fpu32_T
[0], ft
);
6743 gen_load_fpr32h(fpu32h_T
[0], ft
);
6744 gen_load_fpr32(fpu32_T
[1], fs
);
6745 gen_load_fpr32h(fpu32h_T
[1], fs
);
6746 tcg_gen_helper_0_0(do_float_addr_ps
);
6747 gen_store_fpr32(fpu32_T
[2], fd
);
6748 gen_store_fpr32h(fpu32h_T
[2], fd
);
6752 check_cp1_64bitmode(ctx
);
6753 gen_load_fpr32(fpu32_T
[0], ft
);
6754 gen_load_fpr32h(fpu32h_T
[0], ft
);
6755 gen_load_fpr32(fpu32_T
[1], fs
);
6756 gen_load_fpr32h(fpu32h_T
[1], fs
);
6757 tcg_gen_helper_0_0(do_float_mulr_ps
);
6758 gen_store_fpr32(fpu32_T
[2], fd
);
6759 gen_store_fpr32h(fpu32h_T
[2], fd
);
6763 check_cp1_64bitmode(ctx
);
6764 gen_load_fpr32(fpu32_T
[0], fs
);
6765 gen_load_fpr32h(fpu32h_T
[0], fs
);
6766 gen_load_fpr32(fpu32_T
[2], fd
);
6767 gen_load_fpr32h(fpu32h_T
[2], fd
);
6768 tcg_gen_helper_0_0(do_float_recip2_ps
);
6769 gen_store_fpr32(fpu32_T
[2], fd
);
6770 gen_store_fpr32h(fpu32h_T
[2], fd
);
6774 check_cp1_64bitmode(ctx
);
6775 gen_load_fpr32(fpu32_T
[0], fs
);
6776 gen_load_fpr32h(fpu32h_T
[0], fs
);
6777 tcg_gen_helper_0_0(do_float_recip1_ps
);
6778 gen_store_fpr32(fpu32_T
[2], fd
);
6779 gen_store_fpr32h(fpu32h_T
[2], fd
);
6783 check_cp1_64bitmode(ctx
);
6784 gen_load_fpr32(fpu32_T
[0], fs
);
6785 gen_load_fpr32h(fpu32h_T
[0], fs
);
6786 tcg_gen_helper_0_0(do_float_rsqrt1_ps
);
6787 gen_store_fpr32(fpu32_T
[2], fd
);
6788 gen_store_fpr32h(fpu32h_T
[2], fd
);
6792 check_cp1_64bitmode(ctx
);
6793 gen_load_fpr32(fpu32_T
[0], fs
);
6794 gen_load_fpr32h(fpu32h_T
[0], fs
);
6795 gen_load_fpr32(fpu32_T
[2], ft
);
6796 gen_load_fpr32h(fpu32h_T
[2], ft
);
6797 tcg_gen_helper_0_0(do_float_rsqrt2_ps
);
6798 gen_store_fpr32(fpu32_T
[2], fd
);
6799 gen_store_fpr32h(fpu32h_T
[2], fd
);
6803 check_cp1_64bitmode(ctx
);
6804 gen_load_fpr32h(fpu32h_T
[0], fs
);
6805 tcg_gen_helper_0_0(do_float_cvts_pu
);
6806 gen_store_fpr32(fpu32_T
[2], fd
);
6810 check_cp1_64bitmode(ctx
);
6811 gen_load_fpr32(fpu32_T
[0], fs
);
6812 gen_load_fpr32h(fpu32h_T
[0], fs
);
6813 tcg_gen_helper_0_0(do_float_cvtpw_ps
);
6814 gen_store_fpr32(fpu32_T
[2], fd
);
6815 gen_store_fpr32h(fpu32h_T
[2], fd
);
6819 check_cp1_64bitmode(ctx
);
6820 gen_load_fpr32(fpu32_T
[0], fs
);
6821 tcg_gen_helper_0_0(do_float_cvts_pl
);
6822 gen_store_fpr32(fpu32_T
[2], fd
);
6826 check_cp1_64bitmode(ctx
);
6827 gen_load_fpr32(fpu32_T
[0], fs
);
6828 gen_load_fpr32(fpu32_T
[1], ft
);
6829 gen_store_fpr32h(fpu32_T
[0], fd
);
6830 gen_store_fpr32(fpu32_T
[1], fd
);
6834 check_cp1_64bitmode(ctx
);
6835 gen_load_fpr32(fpu32_T
[0], fs
);
6836 gen_load_fpr32h(fpu32h_T
[1], ft
);
6837 gen_store_fpr32(fpu32h_T
[1], fd
);
6838 gen_store_fpr32h(fpu32_T
[0], fd
);
6842 check_cp1_64bitmode(ctx
);
6843 gen_load_fpr32h(fpu32h_T
[0], fs
);
6844 gen_load_fpr32(fpu32_T
[1], ft
);
6845 gen_store_fpr32(fpu32_T
[1], fd
);
6846 gen_store_fpr32h(fpu32h_T
[0], fd
);
6850 check_cp1_64bitmode(ctx
);
6851 gen_load_fpr32h(fpu32h_T
[0], fs
);
6852 gen_load_fpr32h(fpu32h_T
[1], ft
);
6853 gen_store_fpr32(fpu32h_T
[1], fd
);
6854 gen_store_fpr32h(fpu32h_T
[0], fd
);
6873 check_cp1_64bitmode(ctx
);
6874 gen_load_fpr32(fpu32_T
[0], fs
);
6875 gen_load_fpr32h(fpu32h_T
[0], fs
);
6876 gen_load_fpr32(fpu32_T
[1], ft
);
6877 gen_load_fpr32h(fpu32h_T
[1], ft
);
6878 if (ctx
->opcode
& (1 << 6)) {
6879 gen_cmpabs_ps(func
-48, cc
);
6880 opn
= condnames_abs
[func
-48];
6882 gen_cmp_ps(func
-48, cc
);
6883 opn
= condnames
[func
-48];
6888 generate_exception (ctx
, EXCP_RI
);
6893 MIPS_DEBUG("%s %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fs
], fregnames
[ft
]);
6896 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fs
], fregnames
[ft
]);
6899 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fd
], fregnames
[fs
]);
6904 /* Coprocessor 3 (FPU) */
6905 static void gen_flt3_ldst (DisasContext
*ctx
, uint32_t opc
,
6906 int fd
, int fs
, int base
, int index
)
6908 const char *opn
= "extended float load/store";
6910 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
6911 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
6914 gen_load_gpr(t0
, index
);
6915 } else if (index
== 0) {
6916 gen_load_gpr(t0
, base
);
6918 gen_load_gpr(t0
, base
);
6919 gen_load_gpr(t1
, index
);
6920 gen_op_addr_add(t0
, t1
);
6922 /* Don't do NOP if destination is zero: we must perform the actual
6927 tcg_gen_qemu_ld32s(fpu32_T
[0], t0
, ctx
->mem_idx
);
6928 gen_store_fpr32(fpu32_T
[0], fd
);
6933 check_cp1_registers(ctx
, fd
);
6934 tcg_gen_qemu_ld64(fpu64_T
[0], t0
, ctx
->mem_idx
);
6935 gen_store_fpr64(ctx
, fpu64_T
[0], fd
);
6939 check_cp1_64bitmode(ctx
);
6940 tcg_gen_andi_tl(t0
, t0
, ~0x7);
6941 tcg_gen_qemu_ld64(fpu64_T
[0], t0
, ctx
->mem_idx
);
6942 gen_store_fpr64(ctx
, fpu64_T
[0], fd
);
6947 gen_load_fpr32(fpu32_T
[0], fs
);
6948 tcg_gen_qemu_st32(fpu32_T
[0], t0
, ctx
->mem_idx
);
6954 check_cp1_registers(ctx
, fs
);
6955 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6956 tcg_gen_qemu_st64(fpu64_T
[0], t0
, ctx
->mem_idx
);
6961 check_cp1_64bitmode(ctx
);
6962 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
6963 tcg_gen_andi_tl(t0
, t0
, ~0x7);
6964 tcg_gen_qemu_st64(fpu64_T
[0], t0
, ctx
->mem_idx
);
6970 generate_exception(ctx
, EXCP_RI
);
6977 MIPS_DEBUG("%s %s, %s(%s)", opn
, fregnames
[store
? fs
: fd
],
6978 regnames
[index
], regnames
[base
]);
6981 static void gen_flt3_arith (DisasContext
*ctx
, uint32_t opc
,
6982 int fd
, int fr
, int fs
, int ft
)
6984 const char *opn
= "flt3_arith";
6988 check_cp1_64bitmode(ctx
);
6990 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
6991 int l1
= gen_new_label();
6992 int l2
= gen_new_label();
6994 gen_load_gpr(t0
, fr
);
6995 tcg_gen_andi_tl(t0
, t0
, 0x7);
6996 gen_load_fpr32(fpu32_T
[0], fs
);
6997 gen_load_fpr32h(fpu32h_T
[0], fs
);
6998 gen_load_fpr32(fpu32_T
[1], ft
);
6999 gen_load_fpr32h(fpu32h_T
[1], ft
);
7001 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
7002 tcg_gen_mov_i32(fpu32_T
[2], fpu32_T
[0]);
7003 tcg_gen_mov_i32(fpu32h_T
[2], fpu32h_T
[0]);
7006 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 4, l2
);
7008 #ifdef TARGET_WORDS_BIGENDIAN
7009 tcg_gen_mov_i32(fpu32h_T
[2], fpu32_T
[0]);
7010 tcg_gen_mov_i32(fpu32_T
[2], fpu32h_T
[1]);
7012 tcg_gen_mov_i32(fpu32h_T
[2], fpu32_T
[1]);
7013 tcg_gen_mov_i32(fpu32_T
[2], fpu32h_T
[0]);
7017 gen_store_fpr32(fpu32_T
[2], fd
);
7018 gen_store_fpr32h(fpu32h_T
[2], fd
);
7023 gen_load_fpr32(fpu32_T
[0], fs
);
7024 gen_load_fpr32(fpu32_T
[1], ft
);
7025 gen_load_fpr32(fpu32_T
[2], fr
);
7026 tcg_gen_helper_0_0(do_float_muladd_s
);
7027 gen_store_fpr32(fpu32_T
[2], fd
);
7032 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7033 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
7034 gen_load_fpr64(ctx
, fpu64_T
[1], ft
);
7035 gen_load_fpr64(ctx
, fpu64_T
[2], fr
);
7036 tcg_gen_helper_0_0(do_float_muladd_d
);
7037 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
7041 check_cp1_64bitmode(ctx
);
7042 gen_load_fpr32(fpu32_T
[0], fs
);
7043 gen_load_fpr32h(fpu32h_T
[0], fs
);
7044 gen_load_fpr32(fpu32_T
[1], ft
);
7045 gen_load_fpr32h(fpu32h_T
[1], ft
);
7046 gen_load_fpr32(fpu32_T
[2], fr
);
7047 gen_load_fpr32h(fpu32h_T
[2], fr
);
7048 tcg_gen_helper_0_0(do_float_muladd_ps
);
7049 gen_store_fpr32(fpu32_T
[2], fd
);
7050 gen_store_fpr32h(fpu32h_T
[2], fd
);
7055 gen_load_fpr32(fpu32_T
[0], fs
);
7056 gen_load_fpr32(fpu32_T
[1], ft
);
7057 gen_load_fpr32(fpu32_T
[2], fr
);
7058 tcg_gen_helper_0_0(do_float_mulsub_s
);
7059 gen_store_fpr32(fpu32_T
[2], fd
);
7064 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7065 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
7066 gen_load_fpr64(ctx
, fpu64_T
[1], ft
);
7067 gen_load_fpr64(ctx
, fpu64_T
[2], fr
);
7068 tcg_gen_helper_0_0(do_float_mulsub_d
);
7069 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
7073 check_cp1_64bitmode(ctx
);
7074 gen_load_fpr32(fpu32_T
[0], fs
);
7075 gen_load_fpr32h(fpu32h_T
[0], fs
);
7076 gen_load_fpr32(fpu32_T
[1], ft
);
7077 gen_load_fpr32h(fpu32h_T
[1], ft
);
7078 gen_load_fpr32(fpu32_T
[2], fr
);
7079 gen_load_fpr32h(fpu32h_T
[2], fr
);
7080 tcg_gen_helper_0_0(do_float_mulsub_ps
);
7081 gen_store_fpr32(fpu32_T
[2], fd
);
7082 gen_store_fpr32h(fpu32h_T
[2], fd
);
7087 gen_load_fpr32(fpu32_T
[0], fs
);
7088 gen_load_fpr32(fpu32_T
[1], ft
);
7089 gen_load_fpr32(fpu32_T
[2], fr
);
7090 tcg_gen_helper_0_0(do_float_nmuladd_s
);
7091 gen_store_fpr32(fpu32_T
[2], fd
);
7096 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7097 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
7098 gen_load_fpr64(ctx
, fpu64_T
[1], ft
);
7099 gen_load_fpr64(ctx
, fpu64_T
[2], fr
);
7100 tcg_gen_helper_0_0(do_float_nmuladd_d
);
7101 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
7105 check_cp1_64bitmode(ctx
);
7106 gen_load_fpr32(fpu32_T
[0], fs
);
7107 gen_load_fpr32h(fpu32h_T
[0], fs
);
7108 gen_load_fpr32(fpu32_T
[1], ft
);
7109 gen_load_fpr32h(fpu32h_T
[1], ft
);
7110 gen_load_fpr32(fpu32_T
[2], fr
);
7111 gen_load_fpr32h(fpu32h_T
[2], fr
);
7112 tcg_gen_helper_0_0(do_float_nmuladd_ps
);
7113 gen_store_fpr32(fpu32_T
[2], fd
);
7114 gen_store_fpr32h(fpu32h_T
[2], fd
);
7119 gen_load_fpr32(fpu32_T
[0], fs
);
7120 gen_load_fpr32(fpu32_T
[1], ft
);
7121 gen_load_fpr32(fpu32_T
[2], fr
);
7122 tcg_gen_helper_0_0(do_float_nmulsub_s
);
7123 gen_store_fpr32(fpu32_T
[2], fd
);
7128 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7129 gen_load_fpr64(ctx
, fpu64_T
[0], fs
);
7130 gen_load_fpr64(ctx
, fpu64_T
[1], ft
);
7131 gen_load_fpr64(ctx
, fpu64_T
[2], fr
);
7132 tcg_gen_helper_0_0(do_float_nmulsub_d
);
7133 gen_store_fpr64(ctx
, fpu64_T
[2], fd
);
7137 check_cp1_64bitmode(ctx
);
7138 gen_load_fpr32(fpu32_T
[0], fs
);
7139 gen_load_fpr32h(fpu32h_T
[0], fs
);
7140 gen_load_fpr32(fpu32_T
[1], ft
);
7141 gen_load_fpr32h(fpu32h_T
[1], ft
);
7142 gen_load_fpr32(fpu32_T
[2], fr
);
7143 gen_load_fpr32h(fpu32h_T
[2], fr
);
7144 tcg_gen_helper_0_0(do_float_nmulsub_ps
);
7145 gen_store_fpr32(fpu32_T
[2], fd
);
7146 gen_store_fpr32h(fpu32h_T
[2], fd
);
7151 generate_exception (ctx
, EXCP_RI
);
7154 MIPS_DEBUG("%s %s, %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fr
],
7155 fregnames
[fs
], fregnames
[ft
]);
7158 /* ISA extensions (ASEs) */
7159 /* MIPS16 extension to MIPS32 */
7160 /* SmartMIPS extension to MIPS32 */
7162 #if defined(TARGET_MIPS64)
7164 /* MDMX extension to MIPS64 */
7168 static void decode_opc (CPUState
*env
, DisasContext
*ctx
)
7172 uint32_t op
, op1
, op2
;
7175 /* make sure instructions are on a word boundary */
7176 if (ctx
->pc
& 0x3) {
7177 env
->CP0_BadVAddr
= ctx
->pc
;
7178 generate_exception(ctx
, EXCP_AdEL
);
7182 /* Handle blikely not taken case */
7183 if ((ctx
->hflags
& MIPS_HFLAG_BMASK
) == MIPS_HFLAG_BL
) {
7184 int l1
= gen_new_label();
7186 MIPS_DEBUG("blikely condition (" TARGET_FMT_lx
")", ctx
->pc
+ 4);
7187 tcg_gen_brcondi_i32(TCG_COND_NE
, bcond
, 0, l1
);
7189 TCGv r_tmp
= tcg_temp_new(TCG_TYPE_I32
);
7191 tcg_gen_movi_i32(r_tmp
, ctx
->hflags
& ~MIPS_HFLAG_BMASK
);
7192 tcg_gen_st_i32(r_tmp
, cpu_env
, offsetof(CPUState
, hflags
));
7193 tcg_temp_free(r_tmp
);
7195 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
7198 op
= MASK_OP_MAJOR(ctx
->opcode
);
7199 rs
= (ctx
->opcode
>> 21) & 0x1f;
7200 rt
= (ctx
->opcode
>> 16) & 0x1f;
7201 rd
= (ctx
->opcode
>> 11) & 0x1f;
7202 sa
= (ctx
->opcode
>> 6) & 0x1f;
7203 imm
= (int16_t)ctx
->opcode
;
7206 op1
= MASK_SPECIAL(ctx
->opcode
);
7208 case OPC_SLL
: /* Arithmetic with immediate */
7209 case OPC_SRL
... OPC_SRA
:
7210 gen_arith_imm(env
, ctx
, op1
, rd
, rt
, sa
);
7212 case OPC_MOVZ
... OPC_MOVN
:
7213 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
7214 case OPC_SLLV
: /* Arithmetic */
7215 case OPC_SRLV
... OPC_SRAV
:
7216 case OPC_ADD
... OPC_NOR
:
7217 case OPC_SLT
... OPC_SLTU
:
7218 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
7220 case OPC_MULT
... OPC_DIVU
:
7222 check_insn(env
, ctx
, INSN_VR54XX
);
7223 op1
= MASK_MUL_VR54XX(ctx
->opcode
);
7224 gen_mul_vr54xx(ctx
, op1
, rd
, rs
, rt
);
7226 gen_muldiv(ctx
, op1
, rs
, rt
);
7228 case OPC_JR
... OPC_JALR
:
7229 gen_compute_branch(ctx
, op1
, rs
, rd
, sa
);
7231 case OPC_TGE
... OPC_TEQ
: /* Traps */
7233 gen_trap(ctx
, op1
, rs
, rt
, -1);
7235 case OPC_MFHI
: /* Move from HI/LO */
7237 gen_HILO(ctx
, op1
, rd
);
7240 case OPC_MTLO
: /* Move to HI/LO */
7241 gen_HILO(ctx
, op1
, rs
);
7243 case OPC_PMON
: /* Pmon entry point, also R4010 selsl */
7244 #ifdef MIPS_STRICT_STANDARD
7245 MIPS_INVAL("PMON / selsl");
7246 generate_exception(ctx
, EXCP_RI
);
7248 tcg_gen_helper_0_i(do_pmon
, sa
);
7252 generate_exception(ctx
, EXCP_SYSCALL
);
7255 generate_exception(ctx
, EXCP_BREAK
);
7258 #ifdef MIPS_STRICT_STANDARD
7260 generate_exception(ctx
, EXCP_RI
);
7262 /* Implemented as RI exception for now. */
7263 MIPS_INVAL("spim (unofficial)");
7264 generate_exception(ctx
, EXCP_RI
);
7272 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
7273 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
7274 save_cpu_state(ctx
, 1);
7275 check_cp1_enabled(ctx
);
7276 gen_movci(ctx
, rd
, rs
, (ctx
->opcode
>> 18) & 0x7,
7277 (ctx
->opcode
>> 16) & 1);
7279 generate_exception_err(ctx
, EXCP_CpU
, 1);
7283 #if defined(TARGET_MIPS64)
7284 /* MIPS64 specific opcodes */
7286 case OPC_DSRL
... OPC_DSRA
:
7288 case OPC_DSRL32
... OPC_DSRA32
:
7289 check_insn(env
, ctx
, ISA_MIPS3
);
7291 gen_arith_imm(env
, ctx
, op1
, rd
, rt
, sa
);
7294 case OPC_DSRLV
... OPC_DSRAV
:
7295 case OPC_DADD
... OPC_DSUBU
:
7296 check_insn(env
, ctx
, ISA_MIPS3
);
7298 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
7300 case OPC_DMULT
... OPC_DDIVU
:
7301 check_insn(env
, ctx
, ISA_MIPS3
);
7303 gen_muldiv(ctx
, op1
, rs
, rt
);
7306 default: /* Invalid */
7307 MIPS_INVAL("special");
7308 generate_exception(ctx
, EXCP_RI
);
7313 op1
= MASK_SPECIAL2(ctx
->opcode
);
7315 case OPC_MADD
... OPC_MADDU
: /* Multiply and add/sub */
7316 case OPC_MSUB
... OPC_MSUBU
:
7317 check_insn(env
, ctx
, ISA_MIPS32
);
7318 gen_muldiv(ctx
, op1
, rs
, rt
);
7321 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
7323 case OPC_CLZ
... OPC_CLO
:
7324 check_insn(env
, ctx
, ISA_MIPS32
);
7325 gen_cl(ctx
, op1
, rd
, rs
);
7328 /* XXX: not clear which exception should be raised
7329 * when in debug mode...
7331 check_insn(env
, ctx
, ISA_MIPS32
);
7332 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
7333 generate_exception(ctx
, EXCP_DBp
);
7335 generate_exception(ctx
, EXCP_DBp
);
7339 #if defined(TARGET_MIPS64)
7340 case OPC_DCLZ
... OPC_DCLO
:
7341 check_insn(env
, ctx
, ISA_MIPS64
);
7343 gen_cl(ctx
, op1
, rd
, rs
);
7346 default: /* Invalid */
7347 MIPS_INVAL("special2");
7348 generate_exception(ctx
, EXCP_RI
);
7353 op1
= MASK_SPECIAL3(ctx
->opcode
);
7357 check_insn(env
, ctx
, ISA_MIPS32R2
);
7358 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
7361 check_insn(env
, ctx
, ISA_MIPS32R2
);
7362 op2
= MASK_BSHFL(ctx
->opcode
);
7364 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
7365 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
7369 gen_load_gpr(t1
, rt
);
7370 tcg_gen_helper_1_1(do_wsbh
, t0
, t1
);
7371 gen_store_gpr(t0
, rd
);
7374 gen_load_gpr(t1
, rt
);
7375 tcg_gen_ext8s_tl(t0
, t1
);
7376 gen_store_gpr(t0
, rd
);
7379 gen_load_gpr(t1
, rt
);
7380 tcg_gen_ext16s_tl(t0
, t1
);
7381 gen_store_gpr(t0
, rd
);
7383 default: /* Invalid */
7384 MIPS_INVAL("bshfl");
7385 generate_exception(ctx
, EXCP_RI
);
7393 check_insn(env
, ctx
, ISA_MIPS32R2
);
7395 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
7399 save_cpu_state(ctx
, 1);
7400 tcg_gen_helper_1_0(do_rdhwr_cpunum
, t0
);
7403 save_cpu_state(ctx
, 1);
7404 tcg_gen_helper_1_0(do_rdhwr_synci_step
, t0
);
7407 save_cpu_state(ctx
, 1);
7408 tcg_gen_helper_1_0(do_rdhwr_cc
, t0
);
7411 save_cpu_state(ctx
, 1);
7412 tcg_gen_helper_1_0(do_rdhwr_ccres
, t0
);
7415 #if defined (CONFIG_USER_ONLY)
7416 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, tls_value
));
7419 /* XXX: Some CPUs implement this in hardware. Not supported yet. */
7421 default: /* Invalid */
7422 MIPS_INVAL("rdhwr");
7423 generate_exception(ctx
, EXCP_RI
);
7426 gen_store_gpr(t0
, rt
);
7431 check_insn(env
, ctx
, ASE_MT
);
7433 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
7434 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
7436 gen_load_gpr(t0
, rt
);
7437 gen_load_gpr(t1
, rs
);
7438 tcg_gen_helper_0_2(do_fork
, t0
, t1
);
7444 check_insn(env
, ctx
, ASE_MT
);
7446 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
7448 gen_load_gpr(t0
, rs
);
7449 tcg_gen_helper_1_1(do_yield
, t0
, t0
);
7450 gen_store_gpr(t0
, rd
);
7454 #if defined(TARGET_MIPS64)
7455 case OPC_DEXTM
... OPC_DEXT
:
7456 case OPC_DINSM
... OPC_DINS
:
7457 check_insn(env
, ctx
, ISA_MIPS64R2
);
7459 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
7462 check_insn(env
, ctx
, ISA_MIPS64R2
);
7464 op2
= MASK_DBSHFL(ctx
->opcode
);
7466 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
7467 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
7471 gen_load_gpr(t1
, rt
);
7472 tcg_gen_helper_1_1(do_dsbh
, t0
, t1
);
7475 gen_load_gpr(t1
, rt
);
7476 tcg_gen_helper_1_1(do_dshd
, t0
, t1
);
7478 default: /* Invalid */
7479 MIPS_INVAL("dbshfl");
7480 generate_exception(ctx
, EXCP_RI
);
7483 gen_store_gpr(t0
, rd
);
7489 default: /* Invalid */
7490 MIPS_INVAL("special3");
7491 generate_exception(ctx
, EXCP_RI
);
7496 op1
= MASK_REGIMM(ctx
->opcode
);
7498 case OPC_BLTZ
... OPC_BGEZL
: /* REGIMM branches */
7499 case OPC_BLTZAL
... OPC_BGEZALL
:
7500 gen_compute_branch(ctx
, op1
, rs
, -1, imm
<< 2);
7502 case OPC_TGEI
... OPC_TEQI
: /* REGIMM traps */
7504 gen_trap(ctx
, op1
, rs
, -1, imm
);
7507 check_insn(env
, ctx
, ISA_MIPS32R2
);
7510 default: /* Invalid */
7511 MIPS_INVAL("regimm");
7512 generate_exception(ctx
, EXCP_RI
);
7517 check_cp0_enabled(ctx
);
7518 op1
= MASK_CP0(ctx
->opcode
);
7524 #if defined(TARGET_MIPS64)
7528 #ifndef CONFIG_USER_ONLY
7529 gen_cp0(env
, ctx
, op1
, rt
, rd
);
7532 case OPC_C0_FIRST
... OPC_C0_LAST
:
7533 #ifndef CONFIG_USER_ONLY
7534 gen_cp0(env
, ctx
, MASK_C0(ctx
->opcode
), rt
, rd
);
7538 op2
= MASK_MFMC0(ctx
->opcode
);
7540 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
7544 check_insn(env
, ctx
, ASE_MT
);
7545 tcg_gen_helper_1_1(do_dmt
, t0
, t0
);
7548 check_insn(env
, ctx
, ASE_MT
);
7549 tcg_gen_helper_1_1(do_emt
, t0
, t0
);
7552 check_insn(env
, ctx
, ASE_MT
);
7553 tcg_gen_helper_1_1(do_dvpe
, t0
, t0
);
7556 check_insn(env
, ctx
, ASE_MT
);
7557 tcg_gen_helper_1_1(do_evpe
, t0
, t0
);
7560 check_insn(env
, ctx
, ISA_MIPS32R2
);
7561 save_cpu_state(ctx
, 1);
7562 tcg_gen_helper_1_0(do_di
, t0
);
7563 /* Stop translation as we may have switched the execution mode */
7564 ctx
->bstate
= BS_STOP
;
7567 check_insn(env
, ctx
, ISA_MIPS32R2
);
7568 save_cpu_state(ctx
, 1);
7569 tcg_gen_helper_1_0(do_ei
, t0
);
7570 /* Stop translation as we may have switched the execution mode */
7571 ctx
->bstate
= BS_STOP
;
7573 default: /* Invalid */
7574 MIPS_INVAL("mfmc0");
7575 generate_exception(ctx
, EXCP_RI
);
7578 gen_store_gpr(t0
, rt
);
7583 check_insn(env
, ctx
, ISA_MIPS32R2
);
7584 gen_load_srsgpr(rt
, rd
);
7587 check_insn(env
, ctx
, ISA_MIPS32R2
);
7588 gen_store_srsgpr(rt
, rd
);
7592 generate_exception(ctx
, EXCP_RI
);
7596 case OPC_ADDI
... OPC_LUI
: /* Arithmetic with immediate opcode */
7597 gen_arith_imm(env
, ctx
, op
, rt
, rs
, imm
);
7599 case OPC_J
... OPC_JAL
: /* Jump */
7600 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 2;
7601 gen_compute_branch(ctx
, op
, rs
, rt
, offset
);
7603 case OPC_BEQ
... OPC_BGTZ
: /* Branch */
7604 case OPC_BEQL
... OPC_BGTZL
:
7605 gen_compute_branch(ctx
, op
, rs
, rt
, imm
<< 2);
7607 case OPC_LB
... OPC_LWR
: /* Load and stores */
7608 case OPC_SB
... OPC_SW
:
7612 gen_ldst(ctx
, op
, rt
, rs
, imm
);
7615 check_insn(env
, ctx
, ISA_MIPS3
| ISA_MIPS32
);
7619 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
7623 /* Floating point (COP1). */
7628 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
7629 save_cpu_state(ctx
, 1);
7630 check_cp1_enabled(ctx
);
7631 gen_flt_ldst(ctx
, op
, rt
, rs
, imm
);
7633 generate_exception_err(ctx
, EXCP_CpU
, 1);
7638 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
7639 save_cpu_state(ctx
, 1);
7640 check_cp1_enabled(ctx
);
7641 op1
= MASK_CP1(ctx
->opcode
);
7645 check_insn(env
, ctx
, ISA_MIPS32R2
);
7650 gen_cp1(ctx
, op1
, rt
, rd
);
7652 #if defined(TARGET_MIPS64)
7655 check_insn(env
, ctx
, ISA_MIPS3
);
7656 gen_cp1(ctx
, op1
, rt
, rd
);
7662 check_insn(env
, ctx
, ASE_MIPS3D
);
7665 gen_compute_branch1(env
, ctx
, MASK_BC1(ctx
->opcode
),
7666 (rt
>> 2) & 0x7, imm
<< 2);
7673 gen_farith(ctx
, MASK_CP1_FUNC(ctx
->opcode
), rt
, rd
, sa
,
7678 generate_exception (ctx
, EXCP_RI
);
7682 generate_exception_err(ctx
, EXCP_CpU
, 1);
7692 /* COP2: Not implemented. */
7693 generate_exception_err(ctx
, EXCP_CpU
, 2);
7697 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
7698 save_cpu_state(ctx
, 1);
7699 check_cp1_enabled(ctx
);
7700 op1
= MASK_CP3(ctx
->opcode
);
7708 gen_flt3_ldst(ctx
, op1
, sa
, rd
, rs
, rt
);
7726 gen_flt3_arith(ctx
, op1
, sa
, rs
, rd
, rt
);
7730 generate_exception (ctx
, EXCP_RI
);
7734 generate_exception_err(ctx
, EXCP_CpU
, 1);
7738 #if defined(TARGET_MIPS64)
7739 /* MIPS64 opcodes */
7741 case OPC_LDL
... OPC_LDR
:
7742 case OPC_SDL
... OPC_SDR
:
7747 check_insn(env
, ctx
, ISA_MIPS3
);
7749 gen_ldst(ctx
, op
, rt
, rs
, imm
);
7751 case OPC_DADDI
... OPC_DADDIU
:
7752 check_insn(env
, ctx
, ISA_MIPS3
);
7754 gen_arith_imm(env
, ctx
, op
, rt
, rs
, imm
);
7758 check_insn(env
, ctx
, ASE_MIPS16
);
7759 /* MIPS16: Not implemented. */
7761 check_insn(env
, ctx
, ASE_MDMX
);
7762 /* MDMX: Not implemented. */
7763 default: /* Invalid */
7764 MIPS_INVAL("major opcode");
7765 generate_exception(ctx
, EXCP_RI
);
7768 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
7769 int hflags
= ctx
->hflags
& MIPS_HFLAG_BMASK
;
7770 /* Branches completion */
7771 ctx
->hflags
&= ~MIPS_HFLAG_BMASK
;
7772 ctx
->bstate
= BS_BRANCH
;
7773 save_cpu_state(ctx
, 0);
7774 /* FIXME: Need to clear can_do_io. */
7777 /* unconditional branch */
7778 MIPS_DEBUG("unconditional branch");
7779 gen_goto_tb(ctx
, 0, ctx
->btarget
);
7782 /* blikely taken case */
7783 MIPS_DEBUG("blikely branch taken");
7784 gen_goto_tb(ctx
, 0, ctx
->btarget
);
7787 /* Conditional branch */
7788 MIPS_DEBUG("conditional branch");
7790 int l1
= gen_new_label();
7792 tcg_gen_brcondi_i32(TCG_COND_NE
, bcond
, 0, l1
);
7793 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
7795 gen_goto_tb(ctx
, 0, ctx
->btarget
);
7799 /* unconditional branch to register */
7800 MIPS_DEBUG("branch to register");
7801 tcg_gen_st_tl(btarget
, cpu_env
, offsetof(CPUState
, active_tc
.PC
));
7805 MIPS_DEBUG("unknown branch");
7811 static always_inline
int
7812 gen_intermediate_code_internal (CPUState
*env
, TranslationBlock
*tb
,
7816 target_ulong pc_start
;
7817 uint16_t *gen_opc_end
;
7822 if (search_pc
&& loglevel
)
7823 fprintf (logfile
, "search pc %d\n", search_pc
);
7826 /* Leave some spare opc slots for branch handling. */
7827 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
- 16;
7831 ctx
.bstate
= BS_NONE
;
7832 /* Restore delay slot state from the tb context. */
7833 ctx
.hflags
= (uint32_t)tb
->flags
; /* FIXME: maybe use 64 bits here? */
7834 restore_cpu_state(env
, &ctx
);
7835 #if defined(CONFIG_USER_ONLY)
7836 ctx
.mem_idx
= MIPS_HFLAG_UM
;
7838 ctx
.mem_idx
= ctx
.hflags
& MIPS_HFLAG_KSU
;
7841 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
7843 max_insns
= CF_COUNT_MASK
;
7845 if (loglevel
& CPU_LOG_TB_CPU
) {
7846 fprintf(logfile
, "------------------------------------------------\n");
7847 /* FIXME: This may print out stale hflags from env... */
7848 cpu_dump_state(env
, logfile
, fprintf
, 0);
7851 #ifdef MIPS_DEBUG_DISAS
7852 if (loglevel
& CPU_LOG_TB_IN_ASM
)
7853 fprintf(logfile
, "\ntb %p idx %d hflags %04x\n",
7854 tb
, ctx
.mem_idx
, ctx
.hflags
);
7857 while (ctx
.bstate
== BS_NONE
) {
7858 if (env
->nb_breakpoints
> 0) {
7859 for(j
= 0; j
< env
->nb_breakpoints
; j
++) {
7860 if (env
->breakpoints
[j
] == ctx
.pc
) {
7861 save_cpu_state(&ctx
, 1);
7862 ctx
.bstate
= BS_BRANCH
;
7863 tcg_gen_helper_0_i(do_raise_exception
, EXCP_DEBUG
);
7864 /* Include the breakpoint location or the tb won't
7865 * be flushed when it must be. */
7867 goto done_generating
;
7873 j
= gen_opc_ptr
- gen_opc_buf
;
7877 gen_opc_instr_start
[lj
++] = 0;
7879 gen_opc_pc
[lj
] = ctx
.pc
;
7880 gen_opc_hflags
[lj
] = ctx
.hflags
& MIPS_HFLAG_BMASK
;
7881 gen_opc_instr_start
[lj
] = 1;
7882 gen_opc_icount
[lj
] = num_insns
;
7884 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
7886 ctx
.opcode
= ldl_code(ctx
.pc
);
7887 decode_opc(env
, &ctx
);
7891 if (env
->singlestep_enabled
)
7894 if ((ctx
.pc
& (TARGET_PAGE_SIZE
- 1)) == 0)
7897 if (gen_opc_ptr
>= gen_opc_end
)
7900 if (gen_opc_ptr
>= gen_opc_end
)
7903 if (num_insns
>= max_insns
)
7905 #if defined (MIPS_SINGLE_STEP)
7909 if (tb
->cflags
& CF_LAST_IO
)
7911 if (env
->singlestep_enabled
) {
7912 save_cpu_state(&ctx
, ctx
.bstate
== BS_NONE
);
7913 tcg_gen_helper_0_i(do_raise_exception
, EXCP_DEBUG
);
7915 switch (ctx
.bstate
) {
7917 tcg_gen_helper_0_0(do_interrupt_restart
);
7918 gen_goto_tb(&ctx
, 0, ctx
.pc
);
7921 save_cpu_state(&ctx
, 0);
7922 gen_goto_tb(&ctx
, 0, ctx
.pc
);
7925 tcg_gen_helper_0_0(do_interrupt_restart
);
7934 gen_icount_end(tb
, num_insns
);
7935 *gen_opc_ptr
= INDEX_op_end
;
7937 j
= gen_opc_ptr
- gen_opc_buf
;
7940 gen_opc_instr_start
[lj
++] = 0;
7942 tb
->size
= ctx
.pc
- pc_start
;
7943 tb
->icount
= num_insns
;
7946 #if defined MIPS_DEBUG_DISAS
7947 if (loglevel
& CPU_LOG_TB_IN_ASM
)
7948 fprintf(logfile
, "\n");
7950 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
7951 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
7952 target_disas(logfile
, pc_start
, ctx
.pc
- pc_start
, 0);
7953 fprintf(logfile
, "\n");
7955 if (loglevel
& CPU_LOG_TB_CPU
) {
7956 fprintf(logfile
, "---------------- %d %08x\n", ctx
.bstate
, ctx
.hflags
);
7963 int gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
7965 return gen_intermediate_code_internal(env
, tb
, 0);
7968 int gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
7970 return gen_intermediate_code_internal(env
, tb
, 1);
7973 void fpu_dump_state(CPUState
*env
, FILE *f
,
7974 int (*fpu_fprintf
)(FILE *f
, const char *fmt
, ...),
7978 int is_fpu64
= !!(env
->hflags
& MIPS_HFLAG_F64
);
7980 #define printfpr(fp) \
7983 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu: %13g\n", \
7984 (fp)->w[FP_ENDIAN_IDX], (fp)->d, (fp)->fd, \
7985 (fp)->fs[FP_ENDIAN_IDX], (fp)->fs[!FP_ENDIAN_IDX]); \
7988 tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \
7989 tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \
7990 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu:%13g\n", \
7991 tmp.w[FP_ENDIAN_IDX], tmp.d, tmp.fd, \
7992 tmp.fs[FP_ENDIAN_IDX], tmp.fs[!FP_ENDIAN_IDX]); \
7997 fpu_fprintf(f
, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n",
7998 env
->fpu
->fcr0
, env
->fpu
->fcr31
, is_fpu64
, env
->fpu
->fp_status
,
7999 get_float_exception_flags(&env
->fpu
->fp_status
));
8000 fpu_fprintf(f
, "FT0: "); printfpr(&env
->ft0
);
8001 fpu_fprintf(f
, "FT1: "); printfpr(&env
->ft1
);
8002 fpu_fprintf(f
, "FT2: "); printfpr(&env
->ft2
);
8003 for (i
= 0; i
< 32; (is_fpu64
) ? i
++ : (i
+= 2)) {
8004 fpu_fprintf(f
, "%3s: ", fregnames
[i
]);
8005 printfpr(&env
->fpu
->fpr
[i
]);
8011 void dump_fpu (CPUState
*env
)
8015 "pc=0x" TARGET_FMT_lx
" HI=0x" TARGET_FMT_lx
8016 " LO=0x" TARGET_FMT_lx
" ds %04x " TARGET_FMT_lx
8018 env
->active_tc
.PC
, env
->active_tc
.HI
[0],
8019 env
->active_tc
.LO
[0], env
->hflags
, env
->btarget
,
8021 fpu_dump_state(env
, logfile
, fprintf
, 0);
8025 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
8026 /* Debug help: The architecture requires 32bit code to maintain proper
8027 sign-extened values on 64bit machines. */
8029 #define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff))
8031 void cpu_mips_check_sign_extensions (CPUState
*env
, FILE *f
,
8032 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
8037 if (!SIGN_EXT_P(env
->active_tc
.PC
))
8038 cpu_fprintf(f
, "BROKEN: pc=0x" TARGET_FMT_lx
"\n", env
->active_tc
.PC
);
8039 if (!SIGN_EXT_P(env
->active_tc
.HI
[0]))
8040 cpu_fprintf(f
, "BROKEN: HI=0x" TARGET_FMT_lx
"\n", env
->active_tc
.HI
[0]);
8041 if (!SIGN_EXT_P(env
->active_tc
.LO
[0]))
8042 cpu_fprintf(f
, "BROKEN: LO=0x" TARGET_FMT_lx
"\n", env
->active_tc
.LO
[0]);
8043 if (!SIGN_EXT_P(env
->btarget
))
8044 cpu_fprintf(f
, "BROKEN: btarget=0x" TARGET_FMT_lx
"\n", env
->btarget
);
8046 for (i
= 0; i
< 32; i
++) {
8047 if (!SIGN_EXT_P(env
->active_tc
.gpr
[i
]))
8048 cpu_fprintf(f
, "BROKEN: %s=0x" TARGET_FMT_lx
"\n", regnames
[i
], env
->active_tc
.gpr
[i
]);
8051 if (!SIGN_EXT_P(env
->CP0_EPC
))
8052 cpu_fprintf(f
, "BROKEN: EPC=0x" TARGET_FMT_lx
"\n", env
->CP0_EPC
);
8053 if (!SIGN_EXT_P(env
->CP0_LLAddr
))
8054 cpu_fprintf(f
, "BROKEN: LLAddr=0x" TARGET_FMT_lx
"\n", env
->CP0_LLAddr
);
8058 void cpu_dump_state (CPUState
*env
, FILE *f
,
8059 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
8064 cpu_fprintf(f
, "pc=0x" TARGET_FMT_lx
" HI=0x" TARGET_FMT_lx
" LO=0x" TARGET_FMT_lx
" ds %04x " TARGET_FMT_lx
" %d\n",
8065 env
->active_tc
.PC
, env
->active_tc
.HI
, env
->active_tc
.LO
, env
->hflags
, env
->btarget
, env
->bcond
);
8066 for (i
= 0; i
< 32; i
++) {
8068 cpu_fprintf(f
, "GPR%02d:", i
);
8069 cpu_fprintf(f
, " %s " TARGET_FMT_lx
, regnames
[i
], env
->active_tc
.gpr
[i
]);
8071 cpu_fprintf(f
, "\n");
8074 cpu_fprintf(f
, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx
"\n",
8075 env
->CP0_Status
, env
->CP0_Cause
, env
->CP0_EPC
);
8076 cpu_fprintf(f
, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx
"\n",
8077 env
->CP0_Config0
, env
->CP0_Config1
, env
->CP0_LLAddr
);
8078 if (env
->hflags
& MIPS_HFLAG_FPU
)
8079 fpu_dump_state(env
, f
, cpu_fprintf
, flags
);
8080 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
8081 cpu_mips_check_sign_extensions(env
, f
, cpu_fprintf
, flags
);
8085 static void mips_tcg_init(void)
8089 /* Initialize various static tables. */
8093 cpu_env
= tcg_global_reg_new(TCG_TYPE_PTR
, TCG_AREG0
, "env");
8094 bcond
= tcg_global_mem_new(TCG_TYPE_I32
, TCG_AREG0
,
8095 offsetof(CPUState
, bcond
), "bcond");
8096 btarget
= tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
8097 offsetof(CPUState
, btarget
), "btarget");
8098 current_fpu
= tcg_global_mem_new(TCG_TYPE_PTR
,
8100 offsetof(CPUState
, fpu
),
8103 /* register helpers */
8105 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
8108 fpu32_T
[0] = tcg_global_mem_new(TCG_TYPE_I32
, TCG_AREG0
, offsetof(CPUState
, ft0
.w
[FP_ENDIAN_IDX
]), "WT0");
8109 fpu32_T
[1] = tcg_global_mem_new(TCG_TYPE_I32
, TCG_AREG0
, offsetof(CPUState
, ft1
.w
[FP_ENDIAN_IDX
]), "WT1");
8110 fpu32_T
[2] = tcg_global_mem_new(TCG_TYPE_I32
, TCG_AREG0
, offsetof(CPUState
, ft2
.w
[FP_ENDIAN_IDX
]), "WT2");
8111 fpu64_T
[0] = tcg_global_mem_new(TCG_TYPE_I64
, TCG_AREG0
, offsetof(CPUState
, ft0
.d
), "DT0");
8112 fpu64_T
[1] = tcg_global_mem_new(TCG_TYPE_I64
, TCG_AREG0
, offsetof(CPUState
, ft1
.d
), "DT1");
8113 fpu64_T
[2] = tcg_global_mem_new(TCG_TYPE_I64
, TCG_AREG0
, offsetof(CPUState
, ft2
.d
), "DT2");
8114 fpu32h_T
[0] = tcg_global_mem_new(TCG_TYPE_I32
, TCG_AREG0
, offsetof(CPUState
, ft0
.w
[!FP_ENDIAN_IDX
]), "WTH0");
8115 fpu32h_T
[1] = tcg_global_mem_new(TCG_TYPE_I32
, TCG_AREG0
, offsetof(CPUState
, ft1
.w
[!FP_ENDIAN_IDX
]), "WTH1");
8116 fpu32h_T
[2] = tcg_global_mem_new(TCG_TYPE_I32
, TCG_AREG0
, offsetof(CPUState
, ft2
.w
[!FP_ENDIAN_IDX
]), "WTH2");
8121 #include "translate_init.c"
8123 CPUMIPSState
*cpu_mips_init (const char *cpu_model
)
8126 const mips_def_t
*def
;
8128 def
= cpu_mips_find_by_name(cpu_model
);
8131 env
= qemu_mallocz(sizeof(CPUMIPSState
));
8134 env
->cpu_model
= def
;
8137 env
->cpu_model_str
= cpu_model
;
8143 void cpu_reset (CPUMIPSState
*env
)
8145 memset(env
, 0, offsetof(CPUMIPSState
, breakpoints
));
8150 #if !defined(CONFIG_USER_ONLY)
8151 if (env
->hflags
& MIPS_HFLAG_BMASK
) {
8152 /* If the exception was raised from a delay slot,
8153 * come back to the jump. */
8154 env
->CP0_ErrorEPC
= env
->active_tc
.PC
- 4;
8156 env
->CP0_ErrorEPC
= env
->active_tc
.PC
;
8158 env
->active_tc
.PC
= (int32_t)0xBFC00000;
8160 /* SMP not implemented */
8161 env
->CP0_EBase
= 0x80000000;
8162 env
->CP0_Status
= (1 << CP0St_BEV
) | (1 << CP0St_ERL
);
8163 /* vectored interrupts not implemented, timer on int 7,
8164 no performance counters. */
8165 env
->CP0_IntCtl
= 0xe0000000;
8169 for (i
= 0; i
< 7; i
++) {
8170 env
->CP0_WatchLo
[i
] = 0;
8171 env
->CP0_WatchHi
[i
] = 0x80000000;
8173 env
->CP0_WatchLo
[7] = 0;
8174 env
->CP0_WatchHi
[7] = 0;
8176 /* Count register increments in debug mode, EJTAG version 1 */
8177 env
->CP0_Debug
= (1 << CP0DB_CNT
) | (0x1 << CP0DB_VER
);
8179 env
->exception_index
= EXCP_NONE
;
8180 #if defined(CONFIG_USER_ONLY)
8181 env
->hflags
= MIPS_HFLAG_UM
;
8182 env
->user_mode_only
= 1;
8184 env
->hflags
= MIPS_HFLAG_CP0
;
8186 cpu_mips_register(env
, env
->cpu_model
);
8189 void gen_pc_load(CPUState
*env
, TranslationBlock
*tb
,
8190 unsigned long searched_pc
, int pc_pos
, void *puc
)
8192 env
->active_tc
.PC
= gen_opc_pc
[pc_pos
];
8193 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
8194 env
->hflags
|= gen_opc_hflags
[pc_pos
];