]>
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2 * MIPS32 emulation for qemu: main translation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 #include "qemu-common.h"
36 //#define MIPS_DEBUG_DISAS
37 //#define MIPS_DEBUG_SIGN_EXTENSIONS
38 //#define MIPS_SINGLE_STEP
40 /* MIPS major opcodes */
41 #define MASK_OP_MAJOR(op) (op & (0x3F << 26))
44 /* indirect opcode tables */
45 OPC_SPECIAL
= (0x00 << 26),
46 OPC_REGIMM
= (0x01 << 26),
47 OPC_CP0
= (0x10 << 26),
48 OPC_CP1
= (0x11 << 26),
49 OPC_CP2
= (0x12 << 26),
50 OPC_CP3
= (0x13 << 26),
51 OPC_SPECIAL2
= (0x1C << 26),
52 OPC_SPECIAL3
= (0x1F << 26),
53 /* arithmetic with immediate */
54 OPC_ADDI
= (0x08 << 26),
55 OPC_ADDIU
= (0x09 << 26),
56 OPC_SLTI
= (0x0A << 26),
57 OPC_SLTIU
= (0x0B << 26),
58 OPC_ANDI
= (0x0C << 26),
59 OPC_ORI
= (0x0D << 26),
60 OPC_XORI
= (0x0E << 26),
61 OPC_LUI
= (0x0F << 26),
62 OPC_DADDI
= (0x18 << 26),
63 OPC_DADDIU
= (0x19 << 26),
64 /* Jump and branches */
66 OPC_JAL
= (0x03 << 26),
67 OPC_BEQ
= (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
68 OPC_BEQL
= (0x14 << 26),
69 OPC_BNE
= (0x05 << 26),
70 OPC_BNEL
= (0x15 << 26),
71 OPC_BLEZ
= (0x06 << 26),
72 OPC_BLEZL
= (0x16 << 26),
73 OPC_BGTZ
= (0x07 << 26),
74 OPC_BGTZL
= (0x17 << 26),
75 OPC_JALX
= (0x1D << 26), /* MIPS 16 only */
77 OPC_LDL
= (0x1A << 26),
78 OPC_LDR
= (0x1B << 26),
79 OPC_LB
= (0x20 << 26),
80 OPC_LH
= (0x21 << 26),
81 OPC_LWL
= (0x22 << 26),
82 OPC_LW
= (0x23 << 26),
83 OPC_LBU
= (0x24 << 26),
84 OPC_LHU
= (0x25 << 26),
85 OPC_LWR
= (0x26 << 26),
86 OPC_LWU
= (0x27 << 26),
87 OPC_SB
= (0x28 << 26),
88 OPC_SH
= (0x29 << 26),
89 OPC_SWL
= (0x2A << 26),
90 OPC_SW
= (0x2B << 26),
91 OPC_SDL
= (0x2C << 26),
92 OPC_SDR
= (0x2D << 26),
93 OPC_SWR
= (0x2E << 26),
94 OPC_LL
= (0x30 << 26),
95 OPC_LLD
= (0x34 << 26),
96 OPC_LD
= (0x37 << 26),
97 OPC_SC
= (0x38 << 26),
98 OPC_SCD
= (0x3C << 26),
99 OPC_SD
= (0x3F << 26),
100 /* Floating point load/store */
101 OPC_LWC1
= (0x31 << 26),
102 OPC_LWC2
= (0x32 << 26),
103 OPC_LDC1
= (0x35 << 26),
104 OPC_LDC2
= (0x36 << 26),
105 OPC_SWC1
= (0x39 << 26),
106 OPC_SWC2
= (0x3A << 26),
107 OPC_SDC1
= (0x3D << 26),
108 OPC_SDC2
= (0x3E << 26),
109 /* MDMX ASE specific */
110 OPC_MDMX
= (0x1E << 26),
111 /* Cache and prefetch */
112 OPC_CACHE
= (0x2F << 26),
113 OPC_PREF
= (0x33 << 26),
114 /* Reserved major opcode */
115 OPC_MAJOR3B_RESERVED
= (0x3B << 26),
118 /* MIPS special opcodes */
119 #define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F)
123 OPC_SLL
= 0x00 | OPC_SPECIAL
,
124 /* NOP is SLL r0, r0, 0 */
125 /* SSNOP is SLL r0, r0, 1 */
126 /* EHB is SLL r0, r0, 3 */
127 OPC_SRL
= 0x02 | OPC_SPECIAL
, /* also ROTR */
128 OPC_SRA
= 0x03 | OPC_SPECIAL
,
129 OPC_SLLV
= 0x04 | OPC_SPECIAL
,
130 OPC_SRLV
= 0x06 | OPC_SPECIAL
, /* also ROTRV */
131 OPC_SRAV
= 0x07 | OPC_SPECIAL
,
132 OPC_DSLLV
= 0x14 | OPC_SPECIAL
,
133 OPC_DSRLV
= 0x16 | OPC_SPECIAL
, /* also DROTRV */
134 OPC_DSRAV
= 0x17 | OPC_SPECIAL
,
135 OPC_DSLL
= 0x38 | OPC_SPECIAL
,
136 OPC_DSRL
= 0x3A | OPC_SPECIAL
, /* also DROTR */
137 OPC_DSRA
= 0x3B | OPC_SPECIAL
,
138 OPC_DSLL32
= 0x3C | OPC_SPECIAL
,
139 OPC_DSRL32
= 0x3E | OPC_SPECIAL
, /* also DROTR32 */
140 OPC_DSRA32
= 0x3F | OPC_SPECIAL
,
141 /* Multiplication / division */
142 OPC_MULT
= 0x18 | OPC_SPECIAL
,
143 OPC_MULTU
= 0x19 | OPC_SPECIAL
,
144 OPC_DIV
= 0x1A | OPC_SPECIAL
,
145 OPC_DIVU
= 0x1B | OPC_SPECIAL
,
146 OPC_DMULT
= 0x1C | OPC_SPECIAL
,
147 OPC_DMULTU
= 0x1D | OPC_SPECIAL
,
148 OPC_DDIV
= 0x1E | OPC_SPECIAL
,
149 OPC_DDIVU
= 0x1F | OPC_SPECIAL
,
150 /* 2 registers arithmetic / logic */
151 OPC_ADD
= 0x20 | OPC_SPECIAL
,
152 OPC_ADDU
= 0x21 | OPC_SPECIAL
,
153 OPC_SUB
= 0x22 | OPC_SPECIAL
,
154 OPC_SUBU
= 0x23 | OPC_SPECIAL
,
155 OPC_AND
= 0x24 | OPC_SPECIAL
,
156 OPC_OR
= 0x25 | OPC_SPECIAL
,
157 OPC_XOR
= 0x26 | OPC_SPECIAL
,
158 OPC_NOR
= 0x27 | OPC_SPECIAL
,
159 OPC_SLT
= 0x2A | OPC_SPECIAL
,
160 OPC_SLTU
= 0x2B | OPC_SPECIAL
,
161 OPC_DADD
= 0x2C | OPC_SPECIAL
,
162 OPC_DADDU
= 0x2D | OPC_SPECIAL
,
163 OPC_DSUB
= 0x2E | OPC_SPECIAL
,
164 OPC_DSUBU
= 0x2F | OPC_SPECIAL
,
166 OPC_JR
= 0x08 | OPC_SPECIAL
, /* Also JR.HB */
167 OPC_JALR
= 0x09 | OPC_SPECIAL
, /* Also JALR.HB */
169 OPC_TGE
= 0x30 | OPC_SPECIAL
,
170 OPC_TGEU
= 0x31 | OPC_SPECIAL
,
171 OPC_TLT
= 0x32 | OPC_SPECIAL
,
172 OPC_TLTU
= 0x33 | OPC_SPECIAL
,
173 OPC_TEQ
= 0x34 | OPC_SPECIAL
,
174 OPC_TNE
= 0x36 | OPC_SPECIAL
,
175 /* HI / LO registers load & stores */
176 OPC_MFHI
= 0x10 | OPC_SPECIAL
,
177 OPC_MTHI
= 0x11 | OPC_SPECIAL
,
178 OPC_MFLO
= 0x12 | OPC_SPECIAL
,
179 OPC_MTLO
= 0x13 | OPC_SPECIAL
,
180 /* Conditional moves */
181 OPC_MOVZ
= 0x0A | OPC_SPECIAL
,
182 OPC_MOVN
= 0x0B | OPC_SPECIAL
,
184 OPC_MOVCI
= 0x01 | OPC_SPECIAL
,
187 OPC_PMON
= 0x05 | OPC_SPECIAL
, /* inofficial */
188 OPC_SYSCALL
= 0x0C | OPC_SPECIAL
,
189 OPC_BREAK
= 0x0D | OPC_SPECIAL
,
190 OPC_SPIM
= 0x0E | OPC_SPECIAL
, /* inofficial */
191 OPC_SYNC
= 0x0F | OPC_SPECIAL
,
193 OPC_SPECIAL15_RESERVED
= 0x15 | OPC_SPECIAL
,
194 OPC_SPECIAL28_RESERVED
= 0x28 | OPC_SPECIAL
,
195 OPC_SPECIAL29_RESERVED
= 0x29 | OPC_SPECIAL
,
196 OPC_SPECIAL35_RESERVED
= 0x35 | OPC_SPECIAL
,
197 OPC_SPECIAL37_RESERVED
= 0x37 | OPC_SPECIAL
,
198 OPC_SPECIAL39_RESERVED
= 0x39 | OPC_SPECIAL
,
199 OPC_SPECIAL3D_RESERVED
= 0x3D | OPC_SPECIAL
,
202 /* Multiplication variants of the vr54xx. */
203 #define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6))
206 OPC_VR54XX_MULS
= (0x03 << 6) | OPC_MULT
,
207 OPC_VR54XX_MULSU
= (0x03 << 6) | OPC_MULTU
,
208 OPC_VR54XX_MACC
= (0x05 << 6) | OPC_MULT
,
209 OPC_VR54XX_MACCU
= (0x05 << 6) | OPC_MULTU
,
210 OPC_VR54XX_MSAC
= (0x07 << 6) | OPC_MULT
,
211 OPC_VR54XX_MSACU
= (0x07 << 6) | OPC_MULTU
,
212 OPC_VR54XX_MULHI
= (0x09 << 6) | OPC_MULT
,
213 OPC_VR54XX_MULHIU
= (0x09 << 6) | OPC_MULTU
,
214 OPC_VR54XX_MULSHI
= (0x0B << 6) | OPC_MULT
,
215 OPC_VR54XX_MULSHIU
= (0x0B << 6) | OPC_MULTU
,
216 OPC_VR54XX_MACCHI
= (0x0D << 6) | OPC_MULT
,
217 OPC_VR54XX_MACCHIU
= (0x0D << 6) | OPC_MULTU
,
218 OPC_VR54XX_MSACHI
= (0x0F << 6) | OPC_MULT
,
219 OPC_VR54XX_MSACHIU
= (0x0F << 6) | OPC_MULTU
,
222 /* REGIMM (rt field) opcodes */
223 #define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
226 OPC_BLTZ
= (0x00 << 16) | OPC_REGIMM
,
227 OPC_BLTZL
= (0x02 << 16) | OPC_REGIMM
,
228 OPC_BGEZ
= (0x01 << 16) | OPC_REGIMM
,
229 OPC_BGEZL
= (0x03 << 16) | OPC_REGIMM
,
230 OPC_BLTZAL
= (0x10 << 16) | OPC_REGIMM
,
231 OPC_BLTZALL
= (0x12 << 16) | OPC_REGIMM
,
232 OPC_BGEZAL
= (0x11 << 16) | OPC_REGIMM
,
233 OPC_BGEZALL
= (0x13 << 16) | OPC_REGIMM
,
234 OPC_TGEI
= (0x08 << 16) | OPC_REGIMM
,
235 OPC_TGEIU
= (0x09 << 16) | OPC_REGIMM
,
236 OPC_TLTI
= (0x0A << 16) | OPC_REGIMM
,
237 OPC_TLTIU
= (0x0B << 16) | OPC_REGIMM
,
238 OPC_TEQI
= (0x0C << 16) | OPC_REGIMM
,
239 OPC_TNEI
= (0x0E << 16) | OPC_REGIMM
,
240 OPC_SYNCI
= (0x1F << 16) | OPC_REGIMM
,
243 /* Special2 opcodes */
244 #define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F)
247 /* Multiply & xxx operations */
248 OPC_MADD
= 0x00 | OPC_SPECIAL2
,
249 OPC_MADDU
= 0x01 | OPC_SPECIAL2
,
250 OPC_MUL
= 0x02 | OPC_SPECIAL2
,
251 OPC_MSUB
= 0x04 | OPC_SPECIAL2
,
252 OPC_MSUBU
= 0x05 | OPC_SPECIAL2
,
254 OPC_CLZ
= 0x20 | OPC_SPECIAL2
,
255 OPC_CLO
= 0x21 | OPC_SPECIAL2
,
256 OPC_DCLZ
= 0x24 | OPC_SPECIAL2
,
257 OPC_DCLO
= 0x25 | OPC_SPECIAL2
,
259 OPC_SDBBP
= 0x3F | OPC_SPECIAL2
,
262 /* Special3 opcodes */
263 #define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
266 OPC_EXT
= 0x00 | OPC_SPECIAL3
,
267 OPC_DEXTM
= 0x01 | OPC_SPECIAL3
,
268 OPC_DEXTU
= 0x02 | OPC_SPECIAL3
,
269 OPC_DEXT
= 0x03 | OPC_SPECIAL3
,
270 OPC_INS
= 0x04 | OPC_SPECIAL3
,
271 OPC_DINSM
= 0x05 | OPC_SPECIAL3
,
272 OPC_DINSU
= 0x06 | OPC_SPECIAL3
,
273 OPC_DINS
= 0x07 | OPC_SPECIAL3
,
274 OPC_FORK
= 0x08 | OPC_SPECIAL3
,
275 OPC_YIELD
= 0x09 | OPC_SPECIAL3
,
276 OPC_BSHFL
= 0x20 | OPC_SPECIAL3
,
277 OPC_DBSHFL
= 0x24 | OPC_SPECIAL3
,
278 OPC_RDHWR
= 0x3B | OPC_SPECIAL3
,
282 #define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
285 OPC_WSBH
= (0x02 << 6) | OPC_BSHFL
,
286 OPC_SEB
= (0x10 << 6) | OPC_BSHFL
,
287 OPC_SEH
= (0x18 << 6) | OPC_BSHFL
,
291 #define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
294 OPC_DSBH
= (0x02 << 6) | OPC_DBSHFL
,
295 OPC_DSHD
= (0x05 << 6) | OPC_DBSHFL
,
298 /* Coprocessor 0 (rs field) */
299 #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
302 OPC_MFC0
= (0x00 << 21) | OPC_CP0
,
303 OPC_DMFC0
= (0x01 << 21) | OPC_CP0
,
304 OPC_MTC0
= (0x04 << 21) | OPC_CP0
,
305 OPC_DMTC0
= (0x05 << 21) | OPC_CP0
,
306 OPC_MFTR
= (0x08 << 21) | OPC_CP0
,
307 OPC_RDPGPR
= (0x0A << 21) | OPC_CP0
,
308 OPC_MFMC0
= (0x0B << 21) | OPC_CP0
,
309 OPC_MTTR
= (0x0C << 21) | OPC_CP0
,
310 OPC_WRPGPR
= (0x0E << 21) | OPC_CP0
,
311 OPC_C0
= (0x10 << 21) | OPC_CP0
,
312 OPC_C0_FIRST
= (0x10 << 21) | OPC_CP0
,
313 OPC_C0_LAST
= (0x1F << 21) | OPC_CP0
,
317 #define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
320 OPC_DMT
= 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
321 OPC_EMT
= 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
322 OPC_DVPE
= 0x01 | (0 << 5) | OPC_MFMC0
,
323 OPC_EVPE
= 0x01 | (1 << 5) | OPC_MFMC0
,
324 OPC_DI
= (0 << 5) | (0x0C << 11) | OPC_MFMC0
,
325 OPC_EI
= (1 << 5) | (0x0C << 11) | OPC_MFMC0
,
328 /* Coprocessor 0 (with rs == C0) */
329 #define MASK_C0(op) MASK_CP0(op) | (op & 0x3F)
332 OPC_TLBR
= 0x01 | OPC_C0
,
333 OPC_TLBWI
= 0x02 | OPC_C0
,
334 OPC_TLBWR
= 0x06 | OPC_C0
,
335 OPC_TLBP
= 0x08 | OPC_C0
,
336 OPC_RFE
= 0x10 | OPC_C0
,
337 OPC_ERET
= 0x18 | OPC_C0
,
338 OPC_DERET
= 0x1F | OPC_C0
,
339 OPC_WAIT
= 0x20 | OPC_C0
,
342 /* Coprocessor 1 (rs field) */
343 #define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
346 OPC_MFC1
= (0x00 << 21) | OPC_CP1
,
347 OPC_DMFC1
= (0x01 << 21) | OPC_CP1
,
348 OPC_CFC1
= (0x02 << 21) | OPC_CP1
,
349 OPC_MFHC1
= (0x03 << 21) | OPC_CP1
,
350 OPC_MTC1
= (0x04 << 21) | OPC_CP1
,
351 OPC_DMTC1
= (0x05 << 21) | OPC_CP1
,
352 OPC_CTC1
= (0x06 << 21) | OPC_CP1
,
353 OPC_MTHC1
= (0x07 << 21) | OPC_CP1
,
354 OPC_BC1
= (0x08 << 21) | OPC_CP1
, /* bc */
355 OPC_BC1ANY2
= (0x09 << 21) | OPC_CP1
,
356 OPC_BC1ANY4
= (0x0A << 21) | OPC_CP1
,
357 OPC_S_FMT
= (0x10 << 21) | OPC_CP1
, /* 16: fmt=single fp */
358 OPC_D_FMT
= (0x11 << 21) | OPC_CP1
, /* 17: fmt=double fp */
359 OPC_E_FMT
= (0x12 << 21) | OPC_CP1
, /* 18: fmt=extended fp */
360 OPC_Q_FMT
= (0x13 << 21) | OPC_CP1
, /* 19: fmt=quad fp */
361 OPC_W_FMT
= (0x14 << 21) | OPC_CP1
, /* 20: fmt=32bit fixed */
362 OPC_L_FMT
= (0x15 << 21) | OPC_CP1
, /* 21: fmt=64bit fixed */
363 OPC_PS_FMT
= (0x16 << 21) | OPC_CP1
, /* 22: fmt=paired single fp */
366 #define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
367 #define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16))
370 OPC_BC1F
= (0x00 << 16) | OPC_BC1
,
371 OPC_BC1T
= (0x01 << 16) | OPC_BC1
,
372 OPC_BC1FL
= (0x02 << 16) | OPC_BC1
,
373 OPC_BC1TL
= (0x03 << 16) | OPC_BC1
,
377 OPC_BC1FANY2
= (0x00 << 16) | OPC_BC1ANY2
,
378 OPC_BC1TANY2
= (0x01 << 16) | OPC_BC1ANY2
,
382 OPC_BC1FANY4
= (0x00 << 16) | OPC_BC1ANY4
,
383 OPC_BC1TANY4
= (0x01 << 16) | OPC_BC1ANY4
,
386 #define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
389 OPC_MFC2
= (0x00 << 21) | OPC_CP2
,
390 OPC_DMFC2
= (0x01 << 21) | OPC_CP2
,
391 OPC_CFC2
= (0x02 << 21) | OPC_CP2
,
392 OPC_MFHC2
= (0x03 << 21) | OPC_CP2
,
393 OPC_MTC2
= (0x04 << 21) | OPC_CP2
,
394 OPC_DMTC2
= (0x05 << 21) | OPC_CP2
,
395 OPC_CTC2
= (0x06 << 21) | OPC_CP2
,
396 OPC_MTHC2
= (0x07 << 21) | OPC_CP2
,
397 OPC_BC2
= (0x08 << 21) | OPC_CP2
,
400 #define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
403 OPC_LWXC1
= 0x00 | OPC_CP3
,
404 OPC_LDXC1
= 0x01 | OPC_CP3
,
405 OPC_LUXC1
= 0x05 | OPC_CP3
,
406 OPC_SWXC1
= 0x08 | OPC_CP3
,
407 OPC_SDXC1
= 0x09 | OPC_CP3
,
408 OPC_SUXC1
= 0x0D | OPC_CP3
,
409 OPC_PREFX
= 0x0F | OPC_CP3
,
410 OPC_ALNV_PS
= 0x1E | OPC_CP3
,
411 OPC_MADD_S
= 0x20 | OPC_CP3
,
412 OPC_MADD_D
= 0x21 | OPC_CP3
,
413 OPC_MADD_PS
= 0x26 | OPC_CP3
,
414 OPC_MSUB_S
= 0x28 | OPC_CP3
,
415 OPC_MSUB_D
= 0x29 | OPC_CP3
,
416 OPC_MSUB_PS
= 0x2E | OPC_CP3
,
417 OPC_NMADD_S
= 0x30 | OPC_CP3
,
418 OPC_NMADD_D
= 0x31 | OPC_CP3
,
419 OPC_NMADD_PS
= 0x36 | OPC_CP3
,
420 OPC_NMSUB_S
= 0x38 | OPC_CP3
,
421 OPC_NMSUB_D
= 0x39 | OPC_CP3
,
422 OPC_NMSUB_PS
= 0x3E | OPC_CP3
,
425 /* global register indices */
426 static TCGv cpu_env
, cpu_gpr
[32], cpu_PC
;
427 static TCGv cpu_HI
[MIPS_DSP_ACC
], cpu_LO
[MIPS_DSP_ACC
], cpu_ACX
[MIPS_DSP_ACC
];
428 static TCGv cpu_dspctrl
, bcond
, btarget
;
429 static TCGv fpu_fpr32
[32], fpu_fpr32h
[32], fpu_fpr64
[32], fpu_fcr0
, fpu_fcr31
;
431 #include "gen-icount.h"
433 static inline void tcg_gen_helper_0_i(void *func
, uint32_t arg
)
436 TCGv tmp
= tcg_const_i32(arg
);
438 tcg_gen_helper_0_1(func
, tmp
);
442 static inline void tcg_gen_helper_0_ii(void *func
, uint32_t arg1
, uint32_t arg2
)
444 TCGv tmp1
= tcg_const_i32(arg1
);
445 TCGv tmp2
= tcg_const_i32(arg2
);
447 tcg_gen_helper_0_2(func
, tmp1
, tmp2
);
452 static inline void tcg_gen_helper_0_1i(void *func
, TCGv arg1
, uint32_t arg2
)
454 TCGv tmp
= tcg_const_i32(arg2
);
456 tcg_gen_helper_0_2(func
, arg1
, tmp
);
460 static inline void tcg_gen_helper_0_2i(void *func
, TCGv arg1
, TCGv arg2
, uint32_t arg3
)
462 TCGv tmp
= tcg_const_i32(arg3
);
464 tcg_gen_helper_0_3(func
, arg1
, arg2
, tmp
);
468 static inline void tcg_gen_helper_0_1ii(void *func
, TCGv arg1
, uint32_t arg2
, uint32_t arg3
)
470 TCGv tmp1
= tcg_const_i32(arg2
);
471 TCGv tmp2
= tcg_const_i32(arg3
);
473 tcg_gen_helper_0_3(func
, arg1
, tmp1
, tmp2
);
478 static inline void tcg_gen_helper_1_i(void *func
, TCGv ret
, uint32_t arg
)
480 TCGv tmp
= tcg_const_i32(arg
);
482 tcg_gen_helper_1_1(func
, ret
, tmp
);
486 static inline void tcg_gen_helper_1_1i(void *func
, TCGv ret
, TCGv arg1
, uint32_t arg2
)
488 TCGv tmp
= tcg_const_i32(arg2
);
490 tcg_gen_helper_1_2(func
, ret
, arg1
, tmp
);
494 static inline void tcg_gen_helper_1_1ii(void *func
, TCGv ret
, TCGv arg1
, uint32_t arg2
, uint32_t arg3
)
496 TCGv tmp1
= tcg_const_i32(arg2
);
497 TCGv tmp2
= tcg_const_i32(arg3
);
499 tcg_gen_helper_1_3(func
, ret
, arg1
, tmp1
, tmp2
);
504 static inline void tcg_gen_helper_1_2i(void *func
, TCGv ret
, TCGv arg1
, TCGv arg2
, uint32_t arg3
)
506 TCGv tmp
= tcg_const_i32(arg3
);
508 tcg_gen_helper_1_3(func
, ret
, arg1
, arg2
, tmp
);
512 static inline void tcg_gen_helper_1_2ii(void *func
, TCGv ret
, TCGv arg1
, TCGv arg2
, uint32_t arg3
, uint32_t arg4
)
514 TCGv tmp1
= tcg_const_i32(arg3
);
515 TCGv tmp2
= tcg_const_i32(arg4
);
517 tcg_gen_helper_1_4(func
, ret
, arg1
, arg2
, tmp1
, tmp2
);
522 typedef struct DisasContext
{
523 struct TranslationBlock
*tb
;
524 target_ulong pc
, saved_pc
;
526 /* Routine used to access memory */
528 uint32_t hflags
, saved_hflags
;
530 target_ulong btarget
;
534 BS_NONE
= 0, /* We go out of the TB without reaching a branch or an
535 * exception condition */
536 BS_STOP
= 1, /* We want to stop translation for any reason */
537 BS_BRANCH
= 2, /* We reached a branch condition */
538 BS_EXCP
= 3, /* We reached an exception condition */
541 static const char *regnames
[] =
542 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
543 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
544 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
545 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
547 static const char *regnames_HI
[] =
548 { "HI0", "HI1", "HI2", "HI3", };
550 static const char *regnames_LO
[] =
551 { "LO0", "LO1", "LO2", "LO3", };
553 static const char *regnames_ACX
[] =
554 { "ACX0", "ACX1", "ACX2", "ACX3", };
556 static const char *fregnames
[] =
557 { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
558 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
559 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
560 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
562 static const char *fregnames_64
[] =
563 { "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7",
564 "F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15",
565 "F16", "F17", "F18", "F19", "F20", "F21", "F22", "F23",
566 "F24", "F25", "F26", "F27", "F28", "F29", "F30", "F31", };
568 static const char *fregnames_h
[] =
569 { "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7",
570 "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15",
571 "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23",
572 "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31", };
574 #ifdef MIPS_DEBUG_DISAS
575 #define MIPS_DEBUG(fmt, args...) \
577 if (loglevel & CPU_LOG_TB_IN_ASM) { \
578 fprintf(logfile, TARGET_FMT_lx ": %08x " fmt "\n", \
579 ctx->pc, ctx->opcode , ##args); \
583 #define MIPS_DEBUG(fmt, args...) do { } while(0)
586 #define MIPS_INVAL(op) \
588 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
589 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
592 /* General purpose registers moves. */
593 static inline void gen_load_gpr (TCGv t
, int reg
)
596 tcg_gen_movi_tl(t
, 0);
598 tcg_gen_mov_tl(t
, cpu_gpr
[reg
]);
601 static inline void gen_store_gpr (TCGv t
, int reg
)
604 tcg_gen_mov_tl(cpu_gpr
[reg
], t
);
607 /* Moves to/from HI and LO registers. */
608 static inline void gen_load_HI (TCGv t
, int reg
)
610 tcg_gen_mov_tl(t
, cpu_HI
[reg
]);
613 static inline void gen_store_HI (TCGv t
, int reg
)
615 tcg_gen_mov_tl(cpu_HI
[reg
], t
);
618 static inline void gen_load_LO (TCGv t
, int reg
)
620 tcg_gen_mov_tl(t
, cpu_LO
[reg
]);
623 static inline void gen_store_LO (TCGv t
, int reg
)
625 tcg_gen_mov_tl(cpu_LO
[reg
], t
);
628 static inline void gen_load_ACX (TCGv t
, int reg
)
630 tcg_gen_mov_tl(t
, cpu_ACX
[reg
]);
633 static inline void gen_store_ACX (TCGv t
, int reg
)
635 tcg_gen_mov_tl(cpu_ACX
[reg
], t
);
638 /* Moves to/from shadow registers. */
639 static inline void gen_load_srsgpr (int from
, int to
)
641 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_TL
);
644 tcg_gen_movi_tl(r_tmp1
, 0);
646 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I32
);
648 tcg_gen_ld_i32(r_tmp2
, cpu_env
, offsetof(CPUState
, CP0_SRSCtl
));
649 tcg_gen_shri_i32(r_tmp2
, r_tmp2
, CP0SRSCtl_PSS
);
650 tcg_gen_andi_i32(r_tmp2
, r_tmp2
, 0xf);
651 tcg_gen_muli_i32(r_tmp2
, r_tmp2
, sizeof(target_ulong
) * 32);
652 tcg_gen_add_i32(r_tmp2
, cpu_env
, r_tmp2
);
654 tcg_gen_ld_tl(r_tmp1
, r_tmp2
, sizeof(target_ulong
) * from
);
655 tcg_temp_free(r_tmp2
);
657 gen_store_gpr(r_tmp1
, to
);
658 tcg_temp_free(r_tmp1
);
661 static inline void gen_store_srsgpr (int from
, int to
)
664 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_TL
);
665 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I32
);
667 gen_load_gpr(r_tmp1
, from
);
668 tcg_gen_ld_i32(r_tmp2
, cpu_env
, offsetof(CPUState
, CP0_SRSCtl
));
669 tcg_gen_shri_i32(r_tmp2
, r_tmp2
, CP0SRSCtl_PSS
);
670 tcg_gen_andi_i32(r_tmp2
, r_tmp2
, 0xf);
671 tcg_gen_muli_i32(r_tmp2
, r_tmp2
, sizeof(target_ulong
) * 32);
672 tcg_gen_add_i32(r_tmp2
, cpu_env
, r_tmp2
);
674 tcg_gen_st_tl(r_tmp1
, r_tmp2
, sizeof(target_ulong
) * to
);
675 tcg_temp_free(r_tmp1
);
676 tcg_temp_free(r_tmp2
);
680 /* Floating point register moves. */
681 static inline void gen_load_fpr32 (TCGv t
, int reg
)
683 tcg_gen_mov_i32(t
, fpu_fpr32
[reg
]);
686 static inline void gen_store_fpr32 (TCGv t
, int reg
)
688 tcg_gen_mov_i32(fpu_fpr32
[reg
], t
);
691 static inline void gen_load_fpr64 (DisasContext
*ctx
, TCGv t
, int reg
)
693 if (ctx
->hflags
& MIPS_HFLAG_F64
)
694 tcg_gen_mov_i64(t
, fpu_fpr64
[reg
]);
696 tcg_gen_concat_i32_i64(t
, fpu_fpr32
[reg
& ~1], fpu_fpr32
[reg
| 1]);
700 static inline void gen_store_fpr64 (DisasContext
*ctx
, TCGv t
, int reg
)
702 if (ctx
->hflags
& MIPS_HFLAG_F64
)
703 tcg_gen_mov_i64(fpu_fpr64
[reg
], t
);
705 tcg_gen_trunc_i64_i32(fpu_fpr32
[reg
& ~1], t
);
706 tcg_gen_shri_i64(t
, t
, 32);
707 tcg_gen_trunc_i64_i32(fpu_fpr32
[reg
| 1], t
);
711 static inline void gen_load_fpr32h (TCGv t
, int reg
)
713 tcg_gen_mov_i32(t
, fpu_fpr32h
[reg
]);
716 static inline void gen_store_fpr32h (TCGv t
, int reg
)
718 tcg_gen_mov_i32(fpu_fpr32h
[reg
], t
);
721 static inline void get_fp_cond (TCGv t
)
723 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
724 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I32
);
726 tcg_gen_shri_i32(r_tmp2
, fpu_fcr31
, 24);
727 tcg_gen_andi_i32(r_tmp2
, r_tmp2
, 0xfe);
728 tcg_gen_shri_i32(r_tmp1
, fpu_fcr31
, 23);
729 tcg_gen_andi_i32(r_tmp1
, r_tmp1
, 0x1);
730 tcg_gen_or_i32(t
, r_tmp1
, r_tmp2
);
731 tcg_temp_free(r_tmp1
);
732 tcg_temp_free(r_tmp2
);
735 typedef void (fcmp_fun32
)(uint32_t, uint32_t, int);
736 typedef void (fcmp_fun64
)(uint64_t, uint64_t, int);
738 #define FOP_CONDS(fcmp_fun, type, fmt) \
739 static fcmp_fun * fcmp ## type ## _ ## fmt ## _table[16] = { \
740 do_cmp ## type ## _ ## fmt ## _f, \
741 do_cmp ## type ## _ ## fmt ## _un, \
742 do_cmp ## type ## _ ## fmt ## _eq, \
743 do_cmp ## type ## _ ## fmt ## _ueq, \
744 do_cmp ## type ## _ ## fmt ## _olt, \
745 do_cmp ## type ## _ ## fmt ## _ult, \
746 do_cmp ## type ## _ ## fmt ## _ole, \
747 do_cmp ## type ## _ ## fmt ## _ule, \
748 do_cmp ## type ## _ ## fmt ## _sf, \
749 do_cmp ## type ## _ ## fmt ## _ngle, \
750 do_cmp ## type ## _ ## fmt ## _seq, \
751 do_cmp ## type ## _ ## fmt ## _ngl, \
752 do_cmp ## type ## _ ## fmt ## _lt, \
753 do_cmp ## type ## _ ## fmt ## _nge, \
754 do_cmp ## type ## _ ## fmt ## _le, \
755 do_cmp ## type ## _ ## fmt ## _ngt, \
757 static inline void gen_cmp ## type ## _ ## fmt(int n, TCGv a, TCGv b, int cc) \
759 tcg_gen_helper_0_2i(fcmp ## type ## _ ## fmt ## _table[n], a, b, cc); \
762 FOP_CONDS(fcmp_fun64
, , d
)
763 FOP_CONDS(fcmp_fun64
, abs
, d
)
764 FOP_CONDS(fcmp_fun32
, , s
)
765 FOP_CONDS(fcmp_fun32
, abs
, s
)
766 FOP_CONDS(fcmp_fun64
, , ps
)
767 FOP_CONDS(fcmp_fun64
, abs
, ps
)
771 #define OP_COND(name, cond) \
772 static inline void glue(gen_op_, name) (TCGv t0, TCGv t1) \
774 int l1 = gen_new_label(); \
775 int l2 = gen_new_label(); \
777 tcg_gen_brcond_tl(cond, t0, t1, l1); \
778 tcg_gen_movi_tl(t0, 0); \
781 tcg_gen_movi_tl(t0, 1); \
784 OP_COND(eq
, TCG_COND_EQ
);
785 OP_COND(ne
, TCG_COND_NE
);
786 OP_COND(ge
, TCG_COND_GE
);
787 OP_COND(geu
, TCG_COND_GEU
);
788 OP_COND(lt
, TCG_COND_LT
);
789 OP_COND(ltu
, TCG_COND_LTU
);
792 #define OP_CONDI(name, cond) \
793 static inline void glue(gen_op_, name) (TCGv t, target_ulong val) \
795 int l1 = gen_new_label(); \
796 int l2 = gen_new_label(); \
798 tcg_gen_brcondi_tl(cond, t, val, l1); \
799 tcg_gen_movi_tl(t, 0); \
802 tcg_gen_movi_tl(t, 1); \
805 OP_CONDI(lti
, TCG_COND_LT
);
806 OP_CONDI(ltiu
, TCG_COND_LTU
);
809 #define OP_CONDZ(name, cond) \
810 static inline void glue(gen_op_, name) (TCGv t) \
812 int l1 = gen_new_label(); \
813 int l2 = gen_new_label(); \
815 tcg_gen_brcondi_tl(cond, t, 0, l1); \
816 tcg_gen_movi_tl(t, 0); \
819 tcg_gen_movi_tl(t, 1); \
822 OP_CONDZ(gez
, TCG_COND_GE
);
823 OP_CONDZ(gtz
, TCG_COND_GT
);
824 OP_CONDZ(lez
, TCG_COND_LE
);
825 OP_CONDZ(ltz
, TCG_COND_LT
);
828 static inline void gen_save_pc(target_ulong pc
)
830 TCGv r_tmp
= tcg_temp_new(TCG_TYPE_TL
);
832 tcg_gen_movi_tl(r_tmp
, pc
);
833 tcg_gen_mov_tl(cpu_PC
, r_tmp
);
834 tcg_temp_free(r_tmp
);
837 static inline void save_cpu_state (DisasContext
*ctx
, int do_save_pc
)
839 #if defined MIPS_DEBUG_DISAS
840 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
841 fprintf(logfile
, "hflags %08x saved %08x\n",
842 ctx
->hflags
, ctx
->saved_hflags
);
845 if (do_save_pc
&& ctx
->pc
!= ctx
->saved_pc
) {
846 gen_save_pc(ctx
->pc
);
847 ctx
->saved_pc
= ctx
->pc
;
849 if (ctx
->hflags
!= ctx
->saved_hflags
) {
850 TCGv r_tmp
= tcg_temp_new(TCG_TYPE_I32
);
852 tcg_gen_movi_i32(r_tmp
, ctx
->hflags
);
853 tcg_gen_st_i32(r_tmp
, cpu_env
, offsetof(CPUState
, hflags
));
854 tcg_temp_free(r_tmp
);
855 ctx
->saved_hflags
= ctx
->hflags
;
856 switch (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
862 tcg_gen_movi_tl(btarget
, ctx
->btarget
);
868 static inline void restore_cpu_state (CPUState
*env
, DisasContext
*ctx
)
870 ctx
->saved_hflags
= ctx
->hflags
;
871 switch (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
877 ctx
->btarget
= env
->btarget
;
883 generate_exception_err (DisasContext
*ctx
, int excp
, int err
)
885 save_cpu_state(ctx
, 1);
886 tcg_gen_helper_0_ii(do_raise_exception_err
, excp
, err
);
887 tcg_gen_helper_0_0(do_interrupt_restart
);
892 generate_exception (DisasContext
*ctx
, int excp
)
894 save_cpu_state(ctx
, 1);
895 tcg_gen_helper_0_i(do_raise_exception
, excp
);
896 tcg_gen_helper_0_0(do_interrupt_restart
);
900 /* Addresses computation */
901 static inline void gen_op_addr_add (TCGv t0
, TCGv t1
)
903 tcg_gen_add_tl(t0
, t0
, t1
);
905 #if defined(TARGET_MIPS64)
906 /* For compatibility with 32-bit code, data reference in user mode
907 with Status_UX = 0 should be casted to 32-bit and sign extended.
908 See the MIPS64 PRA manual, section 4.10. */
910 int l1
= gen_new_label();
911 TCGv r_tmp
= tcg_temp_local_new(TCG_TYPE_I32
);
913 tcg_gen_ld_i32(r_tmp
, cpu_env
, offsetof(CPUState
, hflags
));
914 tcg_gen_andi_i32(r_tmp
, r_tmp
, MIPS_HFLAG_KSU
);
915 tcg_gen_brcondi_i32(TCG_COND_NE
, r_tmp
, MIPS_HFLAG_UM
, l1
);
916 tcg_gen_ld_i32(r_tmp
, cpu_env
, offsetof(CPUState
, CP0_Status
));
917 tcg_gen_andi_i32(r_tmp
, r_tmp
, (1 << CP0St_UX
));
918 tcg_gen_brcondi_i32(TCG_COND_NE
, r_tmp
, 0, l1
);
919 tcg_temp_free(r_tmp
);
920 tcg_gen_ext32s_i64(t0
, t0
);
926 static inline void check_cp0_enabled(DisasContext
*ctx
)
928 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_CP0
)))
929 generate_exception_err(ctx
, EXCP_CpU
, 1);
932 static inline void check_cp1_enabled(DisasContext
*ctx
)
934 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_FPU
)))
935 generate_exception_err(ctx
, EXCP_CpU
, 1);
938 /* Verify that the processor is running with COP1X instructions enabled.
939 This is associated with the nabla symbol in the MIPS32 and MIPS64
942 static inline void check_cop1x(DisasContext
*ctx
)
944 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_COP1X
)))
945 generate_exception(ctx
, EXCP_RI
);
948 /* Verify that the processor is running with 64-bit floating-point
949 operations enabled. */
951 static inline void check_cp1_64bitmode(DisasContext
*ctx
)
953 if (unlikely(~ctx
->hflags
& (MIPS_HFLAG_F64
| MIPS_HFLAG_COP1X
)))
954 generate_exception(ctx
, EXCP_RI
);
958 * Verify if floating point register is valid; an operation is not defined
959 * if bit 0 of any register specification is set and the FR bit in the
960 * Status register equals zero, since the register numbers specify an
961 * even-odd pair of adjacent coprocessor general registers. When the FR bit
962 * in the Status register equals one, both even and odd register numbers
963 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
965 * Multiple 64 bit wide registers can be checked by calling
966 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
968 static inline void check_cp1_registers(DisasContext
*ctx
, int regs
)
970 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_F64
) && (regs
& 1)))
971 generate_exception(ctx
, EXCP_RI
);
974 /* This code generates a "reserved instruction" exception if the
975 CPU does not support the instruction set corresponding to flags. */
976 static inline void check_insn(CPUState
*env
, DisasContext
*ctx
, int flags
)
978 if (unlikely(!(env
->insn_flags
& flags
)))
979 generate_exception(ctx
, EXCP_RI
);
982 /* This code generates a "reserved instruction" exception if 64-bit
983 instructions are not enabled. */
984 static inline void check_mips_64(DisasContext
*ctx
)
986 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_64
)))
987 generate_exception(ctx
, EXCP_RI
);
990 /* load/store instructions. */
991 #define OP_LD(insn,fname) \
992 static inline void op_ldst_##insn(TCGv t0, DisasContext *ctx) \
994 tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx); \
1001 #if defined(TARGET_MIPS64)
1007 #define OP_ST(insn,fname) \
1008 static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
1010 tcg_gen_qemu_##fname(t1, t0, ctx->mem_idx); \
1015 #if defined(TARGET_MIPS64)
1020 #define OP_LD_ATOMIC(insn,fname) \
1021 static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
1023 tcg_gen_mov_tl(t1, t0); \
1024 tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx); \
1025 tcg_gen_st_tl(t1, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
1027 OP_LD_ATOMIC(ll
,ld32s
);
1028 #if defined(TARGET_MIPS64)
1029 OP_LD_ATOMIC(lld
,ld64
);
1033 #define OP_ST_ATOMIC(insn,fname,almask) \
1034 static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
1036 TCGv r_tmp = tcg_temp_local_new(TCG_TYPE_TL); \
1037 int l1 = gen_new_label(); \
1038 int l2 = gen_new_label(); \
1039 int l3 = gen_new_label(); \
1041 tcg_gen_andi_tl(r_tmp, t0, almask); \
1042 tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp, 0, l1); \
1043 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
1044 generate_exception(ctx, EXCP_AdES); \
1045 gen_set_label(l1); \
1046 tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
1047 tcg_gen_brcond_tl(TCG_COND_NE, t0, r_tmp, l2); \
1048 tcg_temp_free(r_tmp); \
1049 tcg_gen_qemu_##fname(t1, t0, ctx->mem_idx); \
1050 tcg_gen_movi_tl(t0, 1); \
1052 gen_set_label(l2); \
1053 tcg_gen_movi_tl(t0, 0); \
1054 gen_set_label(l3); \
1056 OP_ST_ATOMIC(sc
,st32
,0x3);
1057 #if defined(TARGET_MIPS64)
1058 OP_ST_ATOMIC(scd
,st64
,0x7);
1062 /* Load and store */
1063 static void gen_ldst (DisasContext
*ctx
, uint32_t opc
, int rt
,
1064 int base
, int16_t offset
)
1066 const char *opn
= "ldst";
1067 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
1068 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
1071 tcg_gen_movi_tl(t0
, offset
);
1072 } else if (offset
== 0) {
1073 gen_load_gpr(t0
, base
);
1075 gen_load_gpr(t0
, base
);
1076 tcg_gen_movi_tl(t1
, offset
);
1077 gen_op_addr_add(t0
, t1
);
1079 /* Don't do NOP if destination is zero: we must perform the actual
1082 #if defined(TARGET_MIPS64)
1084 op_ldst_lwu(t0
, ctx
);
1085 gen_store_gpr(t0
, rt
);
1089 op_ldst_ld(t0
, ctx
);
1090 gen_store_gpr(t0
, rt
);
1094 op_ldst_lld(t0
, t1
, ctx
);
1095 gen_store_gpr(t0
, rt
);
1099 gen_load_gpr(t1
, rt
);
1100 op_ldst_sd(t0
, t1
, ctx
);
1104 save_cpu_state(ctx
, 1);
1105 gen_load_gpr(t1
, rt
);
1106 op_ldst_scd(t0
, t1
, ctx
);
1107 gen_store_gpr(t0
, rt
);
1111 save_cpu_state(ctx
, 1);
1112 gen_load_gpr(t1
, rt
);
1113 tcg_gen_helper_1_2i(do_ldl
, t1
, t0
, t1
, ctx
->mem_idx
);
1114 gen_store_gpr(t1
, rt
);
1118 save_cpu_state(ctx
, 1);
1119 gen_load_gpr(t1
, rt
);
1120 tcg_gen_helper_0_2i(do_sdl
, t0
, t1
, ctx
->mem_idx
);
1124 save_cpu_state(ctx
, 1);
1125 gen_load_gpr(t1
, rt
);
1126 tcg_gen_helper_1_2i(do_ldr
, t1
, t0
, t1
, ctx
->mem_idx
);
1127 gen_store_gpr(t1
, rt
);
1131 save_cpu_state(ctx
, 1);
1132 gen_load_gpr(t1
, rt
);
1133 tcg_gen_helper_0_2i(do_sdr
, t0
, t1
, ctx
->mem_idx
);
1138 op_ldst_lw(t0
, ctx
);
1139 gen_store_gpr(t0
, rt
);
1143 gen_load_gpr(t1
, rt
);
1144 op_ldst_sw(t0
, t1
, ctx
);
1148 op_ldst_lh(t0
, ctx
);
1149 gen_store_gpr(t0
, rt
);
1153 gen_load_gpr(t1
, rt
);
1154 op_ldst_sh(t0
, t1
, ctx
);
1158 op_ldst_lhu(t0
, ctx
);
1159 gen_store_gpr(t0
, rt
);
1163 op_ldst_lb(t0
, ctx
);
1164 gen_store_gpr(t0
, rt
);
1168 gen_load_gpr(t1
, rt
);
1169 op_ldst_sb(t0
, t1
, ctx
);
1173 op_ldst_lbu(t0
, ctx
);
1174 gen_store_gpr(t0
, rt
);
1178 save_cpu_state(ctx
, 1);
1179 gen_load_gpr(t1
, rt
);
1180 tcg_gen_helper_1_2i(do_lwl
, t1
, t0
, t1
, ctx
->mem_idx
);
1181 gen_store_gpr(t1
, rt
);
1185 save_cpu_state(ctx
, 1);
1186 gen_load_gpr(t1
, rt
);
1187 tcg_gen_helper_0_2i(do_swl
, t0
, t1
, ctx
->mem_idx
);
1191 save_cpu_state(ctx
, 1);
1192 gen_load_gpr(t1
, rt
);
1193 tcg_gen_helper_1_2i(do_lwr
, t1
, t0
, t1
, ctx
->mem_idx
);
1194 gen_store_gpr(t1
, rt
);
1198 save_cpu_state(ctx
, 1);
1199 gen_load_gpr(t1
, rt
);
1200 tcg_gen_helper_0_2i(do_swr
, t0
, t1
, ctx
->mem_idx
);
1204 op_ldst_ll(t0
, t1
, ctx
);
1205 gen_store_gpr(t0
, rt
);
1209 save_cpu_state(ctx
, 1);
1210 gen_load_gpr(t1
, rt
);
1211 op_ldst_sc(t0
, t1
, ctx
);
1212 gen_store_gpr(t0
, rt
);
1217 generate_exception(ctx
, EXCP_RI
);
1220 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
1226 /* Load and store */
1227 static void gen_flt_ldst (DisasContext
*ctx
, uint32_t opc
, int ft
,
1228 int base
, int16_t offset
)
1230 const char *opn
= "flt_ldst";
1231 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
1234 tcg_gen_movi_tl(t0
, offset
);
1235 } else if (offset
== 0) {
1236 gen_load_gpr(t0
, base
);
1238 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
1240 gen_load_gpr(t0
, base
);
1241 tcg_gen_movi_tl(t1
, offset
);
1242 gen_op_addr_add(t0
, t1
);
1245 /* Don't do NOP if destination is zero: we must perform the actual
1250 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
1252 tcg_gen_qemu_ld32s(fp0
, t0
, ctx
->mem_idx
);
1253 gen_store_fpr32(fp0
, ft
);
1260 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
1262 gen_load_fpr32(fp0
, ft
);
1263 tcg_gen_qemu_st32(fp0
, t0
, ctx
->mem_idx
);
1270 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
1272 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
1273 gen_store_fpr64(ctx
, fp0
, ft
);
1280 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
1282 gen_load_fpr64(ctx
, fp0
, ft
);
1283 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
1290 generate_exception(ctx
, EXCP_RI
);
1293 MIPS_DEBUG("%s %s, %d(%s)", opn
, fregnames
[ft
], offset
, regnames
[base
]);
1298 /* Arithmetic with immediate operand */
1299 static void gen_arith_imm (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1300 int rt
, int rs
, int16_t imm
)
1303 const char *opn
= "imm arith";
1304 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
1306 if (rt
== 0 && opc
!= OPC_ADDI
&& opc
!= OPC_DADDI
) {
1307 /* If no destination, treat it as a NOP.
1308 For addi, we must generate the overflow exception when needed. */
1312 uimm
= (uint16_t)imm
;
1316 #if defined(TARGET_MIPS64)
1322 uimm
= (target_long
)imm
; /* Sign extend to 32/64 bits */
1327 gen_load_gpr(t0
, rs
);
1330 tcg_gen_movi_tl(t0
, imm
<< 16);
1335 #if defined(TARGET_MIPS64)
1344 gen_load_gpr(t0
, rs
);
1350 TCGv r_tmp1
= tcg_temp_local_new(TCG_TYPE_TL
);
1351 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_TL
);
1352 int l1
= gen_new_label();
1354 save_cpu_state(ctx
, 1);
1355 tcg_gen_ext32s_tl(r_tmp1
, t0
);
1356 tcg_gen_addi_tl(t0
, r_tmp1
, uimm
);
1358 tcg_gen_xori_tl(r_tmp1
, r_tmp1
, uimm
);
1359 tcg_gen_xori_tl(r_tmp1
, r_tmp1
, -1);
1360 tcg_gen_xori_tl(r_tmp2
, t0
, uimm
);
1361 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1362 tcg_temp_free(r_tmp2
);
1363 tcg_gen_shri_tl(r_tmp1
, r_tmp1
, 31);
1364 tcg_gen_brcondi_tl(TCG_COND_EQ
, r_tmp1
, 0, l1
);
1365 tcg_temp_free(r_tmp1
);
1366 /* operands of same sign, result different sign */
1367 generate_exception(ctx
, EXCP_OVERFLOW
);
1370 tcg_gen_ext32s_tl(t0
, t0
);
1375 tcg_gen_ext32s_tl(t0
, t0
);
1376 tcg_gen_addi_tl(t0
, t0
, uimm
);
1377 tcg_gen_ext32s_tl(t0
, t0
);
1380 #if defined(TARGET_MIPS64)
1383 TCGv r_tmp1
= tcg_temp_local_new(TCG_TYPE_TL
);
1384 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_TL
);
1385 int l1
= gen_new_label();
1387 save_cpu_state(ctx
, 1);
1388 tcg_gen_mov_tl(r_tmp1
, t0
);
1389 tcg_gen_addi_tl(t0
, t0
, uimm
);
1391 tcg_gen_xori_tl(r_tmp1
, r_tmp1
, uimm
);
1392 tcg_gen_xori_tl(r_tmp1
, r_tmp1
, -1);
1393 tcg_gen_xori_tl(r_tmp2
, t0
, uimm
);
1394 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1395 tcg_temp_free(r_tmp2
);
1396 tcg_gen_shri_tl(r_tmp1
, r_tmp1
, 63);
1397 tcg_gen_brcondi_tl(TCG_COND_EQ
, r_tmp1
, 0, l1
);
1398 tcg_temp_free(r_tmp1
);
1399 /* operands of same sign, result different sign */
1400 generate_exception(ctx
, EXCP_OVERFLOW
);
1406 tcg_gen_addi_tl(t0
, t0
, uimm
);
1411 gen_op_lti(t0
, uimm
);
1415 gen_op_ltiu(t0
, uimm
);
1419 tcg_gen_andi_tl(t0
, t0
, uimm
);
1423 tcg_gen_ori_tl(t0
, t0
, uimm
);
1427 tcg_gen_xori_tl(t0
, t0
, uimm
);
1434 tcg_gen_ext32u_tl(t0
, t0
);
1435 tcg_gen_shli_tl(t0
, t0
, uimm
);
1436 tcg_gen_ext32s_tl(t0
, t0
);
1440 tcg_gen_ext32s_tl(t0
, t0
);
1441 tcg_gen_sari_tl(t0
, t0
, uimm
);
1442 tcg_gen_ext32s_tl(t0
, t0
);
1446 switch ((ctx
->opcode
>> 21) & 0x1f) {
1448 tcg_gen_ext32u_tl(t0
, t0
);
1449 tcg_gen_shri_tl(t0
, t0
, uimm
);
1450 tcg_gen_ext32s_tl(t0
, t0
);
1454 /* rotr is decoded as srl on non-R2 CPUs */
1455 if (env
->insn_flags
& ISA_MIPS32R2
) {
1457 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
1459 tcg_gen_trunc_tl_i32(r_tmp1
, t0
);
1460 tcg_gen_rotri_i32(r_tmp1
, r_tmp1
, uimm
);
1461 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
1462 tcg_temp_free(r_tmp1
);
1466 tcg_gen_ext32u_tl(t0
, t0
);
1467 tcg_gen_shri_tl(t0
, t0
, uimm
);
1468 tcg_gen_ext32s_tl(t0
, t0
);
1473 MIPS_INVAL("invalid srl flag");
1474 generate_exception(ctx
, EXCP_RI
);
1478 #if defined(TARGET_MIPS64)
1480 tcg_gen_shli_tl(t0
, t0
, uimm
);
1484 tcg_gen_sari_tl(t0
, t0
, uimm
);
1488 switch ((ctx
->opcode
>> 21) & 0x1f) {
1490 tcg_gen_shri_tl(t0
, t0
, uimm
);
1494 /* drotr is decoded as dsrl on non-R2 CPUs */
1495 if (env
->insn_flags
& ISA_MIPS32R2
) {
1497 tcg_gen_rotri_tl(t0
, t0
, uimm
);
1501 tcg_gen_shri_tl(t0
, t0
, uimm
);
1506 MIPS_INVAL("invalid dsrl flag");
1507 generate_exception(ctx
, EXCP_RI
);
1512 tcg_gen_shli_tl(t0
, t0
, uimm
+ 32);
1516 tcg_gen_sari_tl(t0
, t0
, uimm
+ 32);
1520 switch ((ctx
->opcode
>> 21) & 0x1f) {
1522 tcg_gen_shri_tl(t0
, t0
, uimm
+ 32);
1526 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */
1527 if (env
->insn_flags
& ISA_MIPS32R2
) {
1528 tcg_gen_rotri_tl(t0
, t0
, uimm
+ 32);
1531 tcg_gen_shri_tl(t0
, t0
, uimm
+ 32);
1536 MIPS_INVAL("invalid dsrl32 flag");
1537 generate_exception(ctx
, EXCP_RI
);
1544 generate_exception(ctx
, EXCP_RI
);
1547 gen_store_gpr(t0
, rt
);
1548 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1554 static void gen_arith (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1555 int rd
, int rs
, int rt
)
1557 const char *opn
= "arith";
1558 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
1559 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
1561 if (rd
== 0 && opc
!= OPC_ADD
&& opc
!= OPC_SUB
1562 && opc
!= OPC_DADD
&& opc
!= OPC_DSUB
) {
1563 /* If no destination, treat it as a NOP.
1564 For add & sub, we must generate the overflow exception when needed. */
1568 gen_load_gpr(t0
, rs
);
1569 /* Specialcase the conventional move operation. */
1570 if (rt
== 0 && (opc
== OPC_ADDU
|| opc
== OPC_DADDU
1571 || opc
== OPC_SUBU
|| opc
== OPC_DSUBU
)) {
1572 gen_store_gpr(t0
, rd
);
1575 gen_load_gpr(t1
, rt
);
1579 TCGv r_tmp1
= tcg_temp_local_new(TCG_TYPE_TL
);
1580 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_TL
);
1581 int l1
= gen_new_label();
1583 save_cpu_state(ctx
, 1);
1584 tcg_gen_ext32s_tl(r_tmp1
, t0
);
1585 tcg_gen_ext32s_tl(r_tmp2
, t1
);
1586 tcg_gen_add_tl(t0
, r_tmp1
, r_tmp2
);
1588 tcg_gen_xor_tl(r_tmp1
, r_tmp1
, t1
);
1589 tcg_gen_xori_tl(r_tmp1
, r_tmp1
, -1);
1590 tcg_gen_xor_tl(r_tmp2
, t0
, t1
);
1591 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1592 tcg_temp_free(r_tmp2
);
1593 tcg_gen_shri_tl(r_tmp1
, r_tmp1
, 31);
1594 tcg_gen_brcondi_tl(TCG_COND_EQ
, r_tmp1
, 0, l1
);
1595 tcg_temp_free(r_tmp1
);
1596 /* operands of same sign, result different sign */
1597 generate_exception(ctx
, EXCP_OVERFLOW
);
1600 tcg_gen_ext32s_tl(t0
, t0
);
1605 tcg_gen_ext32s_tl(t0
, t0
);
1606 tcg_gen_ext32s_tl(t1
, t1
);
1607 tcg_gen_add_tl(t0
, t0
, t1
);
1608 tcg_gen_ext32s_tl(t0
, t0
);
1613 TCGv r_tmp1
= tcg_temp_local_new(TCG_TYPE_TL
);
1614 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_TL
);
1615 int l1
= gen_new_label();
1617 save_cpu_state(ctx
, 1);
1618 tcg_gen_ext32s_tl(r_tmp1
, t0
);
1619 tcg_gen_ext32s_tl(r_tmp2
, t1
);
1620 tcg_gen_sub_tl(t0
, r_tmp1
, r_tmp2
);
1622 tcg_gen_xor_tl(r_tmp2
, r_tmp1
, t1
);
1623 tcg_gen_xor_tl(r_tmp1
, r_tmp1
, t0
);
1624 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1625 tcg_temp_free(r_tmp2
);
1626 tcg_gen_shri_tl(r_tmp1
, r_tmp1
, 31);
1627 tcg_gen_brcondi_tl(TCG_COND_EQ
, r_tmp1
, 0, l1
);
1628 tcg_temp_free(r_tmp1
);
1629 /* operands of different sign, first operand and result different sign */
1630 generate_exception(ctx
, EXCP_OVERFLOW
);
1633 tcg_gen_ext32s_tl(t0
, t0
);
1638 tcg_gen_ext32s_tl(t0
, t0
);
1639 tcg_gen_ext32s_tl(t1
, t1
);
1640 tcg_gen_sub_tl(t0
, t0
, t1
);
1641 tcg_gen_ext32s_tl(t0
, t0
);
1644 #if defined(TARGET_MIPS64)
1647 TCGv r_tmp1
= tcg_temp_local_new(TCG_TYPE_TL
);
1648 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_TL
);
1649 int l1
= gen_new_label();
1651 save_cpu_state(ctx
, 1);
1652 tcg_gen_mov_tl(r_tmp1
, t0
);
1653 tcg_gen_add_tl(t0
, t0
, t1
);
1655 tcg_gen_xor_tl(r_tmp1
, r_tmp1
, t1
);
1656 tcg_gen_xori_tl(r_tmp1
, r_tmp1
, -1);
1657 tcg_gen_xor_tl(r_tmp2
, t0
, t1
);
1658 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1659 tcg_temp_free(r_tmp2
);
1660 tcg_gen_shri_tl(r_tmp1
, r_tmp1
, 63);
1661 tcg_gen_brcondi_tl(TCG_COND_EQ
, r_tmp1
, 0, l1
);
1662 tcg_temp_free(r_tmp1
);
1663 /* operands of same sign, result different sign */
1664 generate_exception(ctx
, EXCP_OVERFLOW
);
1670 tcg_gen_add_tl(t0
, t0
, t1
);
1675 TCGv r_tmp1
= tcg_temp_local_new(TCG_TYPE_TL
);
1676 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_TL
);
1677 int l1
= gen_new_label();
1679 save_cpu_state(ctx
, 1);
1680 tcg_gen_mov_tl(r_tmp1
, t0
);
1681 tcg_gen_sub_tl(t0
, t0
, t1
);
1683 tcg_gen_xor_tl(r_tmp2
, r_tmp1
, t1
);
1684 tcg_gen_xor_tl(r_tmp1
, r_tmp1
, t0
);
1685 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1686 tcg_temp_free(r_tmp2
);
1687 tcg_gen_shri_tl(r_tmp1
, r_tmp1
, 63);
1688 tcg_gen_brcondi_tl(TCG_COND_EQ
, r_tmp1
, 0, l1
);
1689 tcg_temp_free(r_tmp1
);
1690 /* operands of different sign, first operand and result different sign */
1691 generate_exception(ctx
, EXCP_OVERFLOW
);
1697 tcg_gen_sub_tl(t0
, t0
, t1
);
1710 tcg_gen_and_tl(t0
, t0
, t1
);
1714 tcg_gen_or_tl(t0
, t0
, t1
);
1715 tcg_gen_not_tl(t0
, t0
);
1719 tcg_gen_or_tl(t0
, t0
, t1
);
1723 tcg_gen_xor_tl(t0
, t0
, t1
);
1727 tcg_gen_ext32s_tl(t0
, t0
);
1728 tcg_gen_ext32s_tl(t1
, t1
);
1729 tcg_gen_mul_tl(t0
, t0
, t1
);
1730 tcg_gen_ext32s_tl(t0
, t0
);
1735 int l1
= gen_new_label();
1737 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
1738 gen_store_gpr(t0
, rd
);
1745 int l1
= gen_new_label();
1747 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, 0, l1
);
1748 gen_store_gpr(t0
, rd
);
1754 tcg_gen_ext32u_tl(t0
, t0
);
1755 tcg_gen_ext32u_tl(t1
, t1
);
1756 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1757 tcg_gen_shl_tl(t0
, t1
, t0
);
1758 tcg_gen_ext32s_tl(t0
, t0
);
1762 tcg_gen_ext32s_tl(t1
, t1
);
1763 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1764 tcg_gen_sar_tl(t0
, t1
, t0
);
1765 tcg_gen_ext32s_tl(t0
, t0
);
1769 switch ((ctx
->opcode
>> 6) & 0x1f) {
1771 tcg_gen_ext32u_tl(t1
, t1
);
1772 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1773 tcg_gen_shr_tl(t0
, t1
, t0
);
1774 tcg_gen_ext32s_tl(t0
, t0
);
1778 /* rotrv is decoded as srlv on non-R2 CPUs */
1779 if (env
->insn_flags
& ISA_MIPS32R2
) {
1780 int l1
= gen_new_label();
1781 int l2
= gen_new_label();
1783 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1784 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
1786 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
1787 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I32
);
1789 tcg_gen_trunc_tl_i32(r_tmp1
, t0
);
1790 tcg_gen_trunc_tl_i32(r_tmp2
, t1
);
1791 tcg_gen_rotr_i32(r_tmp1
, r_tmp1
, r_tmp2
);
1792 tcg_temp_free(r_tmp1
);
1793 tcg_temp_free(r_tmp2
);
1797 tcg_gen_mov_tl(t0
, t1
);
1801 tcg_gen_ext32u_tl(t1
, t1
);
1802 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1803 tcg_gen_shr_tl(t0
, t1
, t0
);
1804 tcg_gen_ext32s_tl(t0
, t0
);
1809 MIPS_INVAL("invalid srlv flag");
1810 generate_exception(ctx
, EXCP_RI
);
1814 #if defined(TARGET_MIPS64)
1816 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1817 tcg_gen_shl_tl(t0
, t1
, t0
);
1821 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1822 tcg_gen_sar_tl(t0
, t1
, t0
);
1826 switch ((ctx
->opcode
>> 6) & 0x1f) {
1828 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1829 tcg_gen_shr_tl(t0
, t1
, t0
);
1833 /* drotrv is decoded as dsrlv on non-R2 CPUs */
1834 if (env
->insn_flags
& ISA_MIPS32R2
) {
1835 int l1
= gen_new_label();
1836 int l2
= gen_new_label();
1838 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1839 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
1841 tcg_gen_rotr_tl(t0
, t1
, t0
);
1845 tcg_gen_mov_tl(t0
, t1
);
1849 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1850 tcg_gen_shr_tl(t0
, t1
, t0
);
1855 MIPS_INVAL("invalid dsrlv flag");
1856 generate_exception(ctx
, EXCP_RI
);
1863 generate_exception(ctx
, EXCP_RI
);
1866 gen_store_gpr(t0
, rd
);
1868 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1874 /* Arithmetic on HI/LO registers */
1875 static void gen_HILO (DisasContext
*ctx
, uint32_t opc
, int reg
)
1877 const char *opn
= "hilo";
1878 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
1880 if (reg
== 0 && (opc
== OPC_MFHI
|| opc
== OPC_MFLO
)) {
1888 gen_store_gpr(t0
, reg
);
1893 gen_store_gpr(t0
, reg
);
1897 gen_load_gpr(t0
, reg
);
1898 gen_store_HI(t0
, 0);
1902 gen_load_gpr(t0
, reg
);
1903 gen_store_LO(t0
, 0);
1908 generate_exception(ctx
, EXCP_RI
);
1911 MIPS_DEBUG("%s %s", opn
, regnames
[reg
]);
1916 static void gen_muldiv (DisasContext
*ctx
, uint32_t opc
,
1919 const char *opn
= "mul/div";
1920 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
1921 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
1923 gen_load_gpr(t0
, rs
);
1924 gen_load_gpr(t1
, rt
);
1928 int l1
= gen_new_label();
1930 tcg_gen_ext32s_tl(t0
, t0
);
1931 tcg_gen_ext32s_tl(t1
, t1
);
1932 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
1934 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I64
);
1935 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I64
);
1936 TCGv r_tmp3
= tcg_temp_new(TCG_TYPE_I64
);
1938 tcg_gen_ext_tl_i64(r_tmp1
, t0
);
1939 tcg_gen_ext_tl_i64(r_tmp2
, t1
);
1940 tcg_gen_div_i64(r_tmp3
, r_tmp1
, r_tmp2
);
1941 tcg_gen_rem_i64(r_tmp2
, r_tmp1
, r_tmp2
);
1942 tcg_gen_trunc_i64_tl(t0
, r_tmp3
);
1943 tcg_gen_trunc_i64_tl(t1
, r_tmp2
);
1944 tcg_temp_free(r_tmp1
);
1945 tcg_temp_free(r_tmp2
);
1946 tcg_temp_free(r_tmp3
);
1947 tcg_gen_ext32s_tl(t0
, t0
);
1948 tcg_gen_ext32s_tl(t1
, t1
);
1949 gen_store_LO(t0
, 0);
1950 gen_store_HI(t1
, 0);
1958 int l1
= gen_new_label();
1960 tcg_gen_ext32s_tl(t1
, t1
);
1961 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
1963 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
1964 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I32
);
1965 TCGv r_tmp3
= tcg_temp_new(TCG_TYPE_I32
);
1967 tcg_gen_trunc_tl_i32(r_tmp1
, t0
);
1968 tcg_gen_trunc_tl_i32(r_tmp2
, t1
);
1969 tcg_gen_divu_i32(r_tmp3
, r_tmp1
, r_tmp2
);
1970 tcg_gen_remu_i32(r_tmp1
, r_tmp1
, r_tmp2
);
1971 tcg_gen_ext_i32_tl(t0
, r_tmp3
);
1972 tcg_gen_ext_i32_tl(t1
, r_tmp1
);
1973 tcg_temp_free(r_tmp1
);
1974 tcg_temp_free(r_tmp2
);
1975 tcg_temp_free(r_tmp3
);
1976 gen_store_LO(t0
, 0);
1977 gen_store_HI(t1
, 0);
1985 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I64
);
1986 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I64
);
1988 tcg_gen_ext32s_tl(t0
, t0
);
1989 tcg_gen_ext32s_tl(t1
, t1
);
1990 tcg_gen_ext_tl_i64(r_tmp1
, t0
);
1991 tcg_gen_ext_tl_i64(r_tmp2
, t1
);
1992 tcg_gen_mul_i64(r_tmp1
, r_tmp1
, r_tmp2
);
1993 tcg_temp_free(r_tmp2
);
1994 tcg_gen_trunc_i64_tl(t0
, r_tmp1
);
1995 tcg_gen_shri_i64(r_tmp1
, r_tmp1
, 32);
1996 tcg_gen_trunc_i64_tl(t1
, r_tmp1
);
1997 tcg_temp_free(r_tmp1
);
1998 tcg_gen_ext32s_tl(t0
, t0
);
1999 tcg_gen_ext32s_tl(t1
, t1
);
2000 gen_store_LO(t0
, 0);
2001 gen_store_HI(t1
, 0);
2007 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I64
);
2008 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I64
);
2010 tcg_gen_ext32u_tl(t0
, t0
);
2011 tcg_gen_ext32u_tl(t1
, t1
);
2012 tcg_gen_extu_tl_i64(r_tmp1
, t0
);
2013 tcg_gen_extu_tl_i64(r_tmp2
, t1
);
2014 tcg_gen_mul_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2015 tcg_temp_free(r_tmp2
);
2016 tcg_gen_trunc_i64_tl(t0
, r_tmp1
);
2017 tcg_gen_shri_i64(r_tmp1
, r_tmp1
, 32);
2018 tcg_gen_trunc_i64_tl(t1
, r_tmp1
);
2019 tcg_temp_free(r_tmp1
);
2020 tcg_gen_ext32s_tl(t0
, t0
);
2021 tcg_gen_ext32s_tl(t1
, t1
);
2022 gen_store_LO(t0
, 0);
2023 gen_store_HI(t1
, 0);
2027 #if defined(TARGET_MIPS64)
2030 int l1
= gen_new_label();
2032 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
2034 int l2
= gen_new_label();
2036 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, -1LL << 63, l2
);
2037 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1LL, l2
);
2039 tcg_gen_movi_tl(t1
, 0);
2040 gen_store_LO(t0
, 0);
2041 gen_store_HI(t1
, 0);
2046 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I64
);
2047 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I64
);
2049 tcg_gen_div_i64(r_tmp1
, t0
, t1
);
2050 tcg_gen_rem_i64(r_tmp2
, t0
, t1
);
2051 gen_store_LO(r_tmp1
, 0);
2052 gen_store_HI(r_tmp2
, 0);
2053 tcg_temp_free(r_tmp1
);
2054 tcg_temp_free(r_tmp2
);
2063 int l1
= gen_new_label();
2065 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
2067 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I64
);
2068 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I64
);
2070 tcg_gen_divu_i64(r_tmp1
, t0
, t1
);
2071 tcg_gen_remu_i64(r_tmp2
, t0
, t1
);
2072 tcg_temp_free(r_tmp1
);
2073 tcg_temp_free(r_tmp2
);
2074 gen_store_LO(r_tmp1
, 0);
2075 gen_store_HI(r_tmp2
, 0);
2082 tcg_gen_helper_0_2(do_dmult
, t0
, t1
);
2086 tcg_gen_helper_0_2(do_dmultu
, t0
, t1
);
2092 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I64
);
2093 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I64
);
2095 tcg_gen_ext32s_tl(t0
, t0
);
2096 tcg_gen_ext32s_tl(t1
, t1
);
2097 tcg_gen_ext_tl_i64(r_tmp1
, t0
);
2098 tcg_gen_ext_tl_i64(r_tmp2
, t1
);
2099 tcg_gen_mul_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2102 tcg_gen_concat_tl_i64(r_tmp2
, t0
, t1
);
2103 tcg_gen_add_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2104 tcg_temp_free(r_tmp2
);
2105 tcg_gen_trunc_i64_tl(t0
, r_tmp1
);
2106 tcg_gen_shri_i64(r_tmp1
, r_tmp1
, 32);
2107 tcg_gen_trunc_i64_tl(t1
, r_tmp1
);
2108 tcg_temp_free(r_tmp1
);
2109 tcg_gen_ext32s_tl(t0
, t0
);
2110 tcg_gen_ext32s_tl(t1
, t1
);
2111 gen_store_LO(t0
, 0);
2112 gen_store_HI(t1
, 0);
2118 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I64
);
2119 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I64
);
2121 tcg_gen_ext32u_tl(t0
, t0
);
2122 tcg_gen_ext32u_tl(t1
, t1
);
2123 tcg_gen_extu_tl_i64(r_tmp1
, t0
);
2124 tcg_gen_extu_tl_i64(r_tmp2
, t1
);
2125 tcg_gen_mul_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2128 tcg_gen_concat_tl_i64(r_tmp2
, t0
, t1
);
2129 tcg_gen_add_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2130 tcg_temp_free(r_tmp2
);
2131 tcg_gen_trunc_i64_tl(t0
, r_tmp1
);
2132 tcg_gen_shri_i64(r_tmp1
, r_tmp1
, 32);
2133 tcg_gen_trunc_i64_tl(t1
, r_tmp1
);
2134 tcg_temp_free(r_tmp1
);
2135 tcg_gen_ext32s_tl(t0
, t0
);
2136 tcg_gen_ext32s_tl(t1
, t1
);
2137 gen_store_LO(t0
, 0);
2138 gen_store_HI(t1
, 0);
2144 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I64
);
2145 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I64
);
2147 tcg_gen_ext32s_tl(t0
, t0
);
2148 tcg_gen_ext32s_tl(t1
, t1
);
2149 tcg_gen_ext_tl_i64(r_tmp1
, t0
);
2150 tcg_gen_ext_tl_i64(r_tmp2
, t1
);
2151 tcg_gen_mul_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2154 tcg_gen_concat_tl_i64(r_tmp2
, t0
, t1
);
2155 tcg_gen_sub_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2156 tcg_temp_free(r_tmp2
);
2157 tcg_gen_trunc_i64_tl(t0
, r_tmp1
);
2158 tcg_gen_shri_i64(r_tmp1
, r_tmp1
, 32);
2159 tcg_gen_trunc_i64_tl(t1
, r_tmp1
);
2160 tcg_temp_free(r_tmp1
);
2161 tcg_gen_ext32s_tl(t0
, t0
);
2162 tcg_gen_ext32s_tl(t1
, t1
);
2163 gen_store_LO(t0
, 0);
2164 gen_store_HI(t1
, 0);
2170 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I64
);
2171 TCGv r_tmp2
= tcg_temp_new(TCG_TYPE_I64
);
2173 tcg_gen_ext32u_tl(t0
, t0
);
2174 tcg_gen_ext32u_tl(t1
, t1
);
2175 tcg_gen_extu_tl_i64(r_tmp1
, t0
);
2176 tcg_gen_extu_tl_i64(r_tmp2
, t1
);
2177 tcg_gen_mul_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2180 tcg_gen_concat_tl_i64(r_tmp2
, t0
, t1
);
2181 tcg_gen_sub_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2182 tcg_temp_free(r_tmp2
);
2183 tcg_gen_trunc_i64_tl(t0
, r_tmp1
);
2184 tcg_gen_shri_i64(r_tmp1
, r_tmp1
, 32);
2185 tcg_gen_trunc_i64_tl(t1
, r_tmp1
);
2186 tcg_temp_free(r_tmp1
);
2187 tcg_gen_ext32s_tl(t0
, t0
);
2188 tcg_gen_ext32s_tl(t1
, t1
);
2189 gen_store_LO(t0
, 0);
2190 gen_store_HI(t1
, 0);
2196 generate_exception(ctx
, EXCP_RI
);
2199 MIPS_DEBUG("%s %s %s", opn
, regnames
[rs
], regnames
[rt
]);
2205 static void gen_mul_vr54xx (DisasContext
*ctx
, uint32_t opc
,
2206 int rd
, int rs
, int rt
)
2208 const char *opn
= "mul vr54xx";
2209 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
2210 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
2212 gen_load_gpr(t0
, rs
);
2213 gen_load_gpr(t1
, rt
);
2216 case OPC_VR54XX_MULS
:
2217 tcg_gen_helper_1_2(do_muls
, t0
, t0
, t1
);
2220 case OPC_VR54XX_MULSU
:
2221 tcg_gen_helper_1_2(do_mulsu
, t0
, t0
, t1
);
2224 case OPC_VR54XX_MACC
:
2225 tcg_gen_helper_1_2(do_macc
, t0
, t0
, t1
);
2228 case OPC_VR54XX_MACCU
:
2229 tcg_gen_helper_1_2(do_maccu
, t0
, t0
, t1
);
2232 case OPC_VR54XX_MSAC
:
2233 tcg_gen_helper_1_2(do_msac
, t0
, t0
, t1
);
2236 case OPC_VR54XX_MSACU
:
2237 tcg_gen_helper_1_2(do_msacu
, t0
, t0
, t1
);
2240 case OPC_VR54XX_MULHI
:
2241 tcg_gen_helper_1_2(do_mulhi
, t0
, t0
, t1
);
2244 case OPC_VR54XX_MULHIU
:
2245 tcg_gen_helper_1_2(do_mulhiu
, t0
, t0
, t1
);
2248 case OPC_VR54XX_MULSHI
:
2249 tcg_gen_helper_1_2(do_mulshi
, t0
, t0
, t1
);
2252 case OPC_VR54XX_MULSHIU
:
2253 tcg_gen_helper_1_2(do_mulshiu
, t0
, t0
, t1
);
2256 case OPC_VR54XX_MACCHI
:
2257 tcg_gen_helper_1_2(do_macchi
, t0
, t0
, t1
);
2260 case OPC_VR54XX_MACCHIU
:
2261 tcg_gen_helper_1_2(do_macchiu
, t0
, t0
, t1
);
2264 case OPC_VR54XX_MSACHI
:
2265 tcg_gen_helper_1_2(do_msachi
, t0
, t0
, t1
);
2268 case OPC_VR54XX_MSACHIU
:
2269 tcg_gen_helper_1_2(do_msachiu
, t0
, t0
, t1
);
2273 MIPS_INVAL("mul vr54xx");
2274 generate_exception(ctx
, EXCP_RI
);
2277 gen_store_gpr(t0
, rd
);
2278 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
2285 static void gen_cl (DisasContext
*ctx
, uint32_t opc
,
2288 const char *opn
= "CLx";
2289 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
2296 gen_load_gpr(t0
, rs
);
2299 tcg_gen_helper_1_1(do_clo
, t0
, t0
);
2303 tcg_gen_helper_1_1(do_clz
, t0
, t0
);
2306 #if defined(TARGET_MIPS64)
2308 tcg_gen_helper_1_1(do_dclo
, t0
, t0
);
2312 tcg_gen_helper_1_1(do_dclz
, t0
, t0
);
2318 generate_exception(ctx
, EXCP_RI
);
2321 gen_store_gpr(t0
, rd
);
2322 MIPS_DEBUG("%s %s, %s", opn
, regnames
[rd
], regnames
[rs
]);
2329 static void gen_trap (DisasContext
*ctx
, uint32_t opc
,
2330 int rs
, int rt
, int16_t imm
)
2333 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
2334 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
2337 /* Load needed operands */
2345 /* Compare two registers */
2347 gen_load_gpr(t0
, rs
);
2348 gen_load_gpr(t1
, rt
);
2358 /* Compare register to immediate */
2359 if (rs
!= 0 || imm
!= 0) {
2360 gen_load_gpr(t0
, rs
);
2361 tcg_gen_movi_tl(t1
, (int32_t)imm
);
2368 case OPC_TEQ
: /* rs == rs */
2369 case OPC_TEQI
: /* r0 == 0 */
2370 case OPC_TGE
: /* rs >= rs */
2371 case OPC_TGEI
: /* r0 >= 0 */
2372 case OPC_TGEU
: /* rs >= rs unsigned */
2373 case OPC_TGEIU
: /* r0 >= 0 unsigned */
2375 tcg_gen_movi_tl(t0
, 1);
2377 case OPC_TLT
: /* rs < rs */
2378 case OPC_TLTI
: /* r0 < 0 */
2379 case OPC_TLTU
: /* rs < rs unsigned */
2380 case OPC_TLTIU
: /* r0 < 0 unsigned */
2381 case OPC_TNE
: /* rs != rs */
2382 case OPC_TNEI
: /* r0 != 0 */
2383 /* Never trap: treat as NOP. */
2387 generate_exception(ctx
, EXCP_RI
);
2418 generate_exception(ctx
, EXCP_RI
);
2422 save_cpu_state(ctx
, 1);
2424 int l1
= gen_new_label();
2426 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
2427 tcg_gen_helper_0_i(do_raise_exception
, EXCP_TRAP
);
2430 ctx
->bstate
= BS_STOP
;
2436 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
2438 TranslationBlock
*tb
;
2440 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
2443 tcg_gen_exit_tb((long)tb
+ n
);
2450 /* Branches (before delay slot) */
2451 static void gen_compute_branch (DisasContext
*ctx
, uint32_t opc
,
2452 int rs
, int rt
, int32_t offset
)
2454 target_ulong btgt
= -1;
2456 int bcond_compute
= 0;
2457 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
2458 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
2460 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
2461 #ifdef MIPS_DEBUG_DISAS
2462 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2464 "Branch in delay slot at PC 0x" TARGET_FMT_lx
"\n",
2468 generate_exception(ctx
, EXCP_RI
);
2472 /* Load needed operands */
2478 /* Compare two registers */
2480 gen_load_gpr(t0
, rs
);
2481 gen_load_gpr(t1
, rt
);
2484 btgt
= ctx
->pc
+ 4 + offset
;
2498 /* Compare to zero */
2500 gen_load_gpr(t0
, rs
);
2503 btgt
= ctx
->pc
+ 4 + offset
;
2507 /* Jump to immediate */
2508 btgt
= ((ctx
->pc
+ 4) & (int32_t)0xF0000000) | (uint32_t)offset
;
2512 /* Jump to register */
2513 if (offset
!= 0 && offset
!= 16) {
2514 /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
2515 others are reserved. */
2516 MIPS_INVAL("jump hint");
2517 generate_exception(ctx
, EXCP_RI
);
2520 gen_load_gpr(btarget
, rs
);
2523 MIPS_INVAL("branch/jump");
2524 generate_exception(ctx
, EXCP_RI
);
2527 if (bcond_compute
== 0) {
2528 /* No condition to be computed */
2530 case OPC_BEQ
: /* rx == rx */
2531 case OPC_BEQL
: /* rx == rx likely */
2532 case OPC_BGEZ
: /* 0 >= 0 */
2533 case OPC_BGEZL
: /* 0 >= 0 likely */
2534 case OPC_BLEZ
: /* 0 <= 0 */
2535 case OPC_BLEZL
: /* 0 <= 0 likely */
2537 ctx
->hflags
|= MIPS_HFLAG_B
;
2538 MIPS_DEBUG("balways");
2540 case OPC_BGEZAL
: /* 0 >= 0 */
2541 case OPC_BGEZALL
: /* 0 >= 0 likely */
2542 /* Always take and link */
2544 ctx
->hflags
|= MIPS_HFLAG_B
;
2545 MIPS_DEBUG("balways and link");
2547 case OPC_BNE
: /* rx != rx */
2548 case OPC_BGTZ
: /* 0 > 0 */
2549 case OPC_BLTZ
: /* 0 < 0 */
2551 MIPS_DEBUG("bnever (NOP)");
2553 case OPC_BLTZAL
: /* 0 < 0 */
2554 tcg_gen_movi_tl(t0
, ctx
->pc
+ 8);
2555 gen_store_gpr(t0
, 31);
2556 MIPS_DEBUG("bnever and link");
2558 case OPC_BLTZALL
: /* 0 < 0 likely */
2559 tcg_gen_movi_tl(t0
, ctx
->pc
+ 8);
2560 gen_store_gpr(t0
, 31);
2561 /* Skip the instruction in the delay slot */
2562 MIPS_DEBUG("bnever, link and skip");
2565 case OPC_BNEL
: /* rx != rx likely */
2566 case OPC_BGTZL
: /* 0 > 0 likely */
2567 case OPC_BLTZL
: /* 0 < 0 likely */
2568 /* Skip the instruction in the delay slot */
2569 MIPS_DEBUG("bnever and skip");
2573 ctx
->hflags
|= MIPS_HFLAG_B
;
2574 MIPS_DEBUG("j " TARGET_FMT_lx
, btgt
);
2578 ctx
->hflags
|= MIPS_HFLAG_B
;
2579 MIPS_DEBUG("jal " TARGET_FMT_lx
, btgt
);
2582 ctx
->hflags
|= MIPS_HFLAG_BR
;
2583 MIPS_DEBUG("jr %s", regnames
[rs
]);
2587 ctx
->hflags
|= MIPS_HFLAG_BR
;
2588 MIPS_DEBUG("jalr %s, %s", regnames
[rt
], regnames
[rs
]);
2591 MIPS_INVAL("branch/jump");
2592 generate_exception(ctx
, EXCP_RI
);
2599 MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx
,
2600 regnames
[rs
], regnames
[rt
], btgt
);
2604 MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx
,
2605 regnames
[rs
], regnames
[rt
], btgt
);
2609 MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx
,
2610 regnames
[rs
], regnames
[rt
], btgt
);
2614 MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx
,
2615 regnames
[rs
], regnames
[rt
], btgt
);
2619 MIPS_DEBUG("bgez %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2623 MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2627 MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2633 MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2637 MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2641 MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2645 MIPS_DEBUG("blez %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2649 MIPS_DEBUG("blezl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2653 MIPS_DEBUG("bltz %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2657 MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2662 MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2664 ctx
->hflags
|= MIPS_HFLAG_BC
;
2665 tcg_gen_trunc_tl_i32(bcond
, t0
);
2670 MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2672 ctx
->hflags
|= MIPS_HFLAG_BL
;
2673 tcg_gen_trunc_tl_i32(bcond
, t0
);
2676 MIPS_INVAL("conditional branch/jump");
2677 generate_exception(ctx
, EXCP_RI
);
2681 MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx
,
2682 blink
, ctx
->hflags
, btgt
);
2684 ctx
->btarget
= btgt
;
2686 tcg_gen_movi_tl(t0
, ctx
->pc
+ 8);
2687 gen_store_gpr(t0
, blink
);
2695 /* special3 bitfield operations */
2696 static void gen_bitops (DisasContext
*ctx
, uint32_t opc
, int rt
,
2697 int rs
, int lsb
, int msb
)
2699 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
2700 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
2702 gen_load_gpr(t1
, rs
);
2707 tcg_gen_helper_1_1ii(do_ext
, t0
, t1
, lsb
, msb
+ 1);
2709 #if defined(TARGET_MIPS64)
2713 tcg_gen_helper_1_1ii(do_dext
, t0
, t1
, lsb
, msb
+ 1 + 32);
2718 tcg_gen_helper_1_1ii(do_dext
, t0
, t1
, lsb
+ 32, msb
+ 1);
2723 tcg_gen_helper_1_1ii(do_dext
, t0
, t1
, lsb
, msb
+ 1);
2729 gen_load_gpr(t0
, rt
);
2730 tcg_gen_helper_1_2ii(do_ins
, t0
, t0
, t1
, lsb
, msb
- lsb
+ 1);
2732 #if defined(TARGET_MIPS64)
2736 gen_load_gpr(t0
, rt
);
2737 tcg_gen_helper_1_2ii(do_dins
, t0
, t0
, t1
, lsb
, msb
- lsb
+ 1 + 32);
2742 gen_load_gpr(t0
, rt
);
2743 tcg_gen_helper_1_2ii(do_dins
, t0
, t0
, t1
, lsb
+ 32, msb
- lsb
+ 1);
2748 gen_load_gpr(t0
, rt
);
2749 tcg_gen_helper_1_2ii(do_dins
, t0
, t0
, t1
, lsb
, msb
- lsb
+ 1);
2754 MIPS_INVAL("bitops");
2755 generate_exception(ctx
, EXCP_RI
);
2760 gen_store_gpr(t0
, rt
);
2765 #ifndef CONFIG_USER_ONLY
2766 /* CP0 (MMU and control) */
2767 static inline void gen_mfc0_load32 (TCGv t
, target_ulong off
)
2769 TCGv r_tmp
= tcg_temp_new(TCG_TYPE_I32
);
2771 tcg_gen_ld_i32(r_tmp
, cpu_env
, off
);
2772 tcg_gen_ext_i32_tl(t
, r_tmp
);
2773 tcg_temp_free(r_tmp
);
2776 static inline void gen_mfc0_load64 (TCGv t
, target_ulong off
)
2778 tcg_gen_ld_tl(t
, cpu_env
, off
);
2779 tcg_gen_ext32s_tl(t
, t
);
2782 static inline void gen_mtc0_store32 (TCGv t
, target_ulong off
)
2784 TCGv r_tmp
= tcg_temp_new(TCG_TYPE_I32
);
2786 tcg_gen_trunc_tl_i32(r_tmp
, t
);
2787 tcg_gen_st_i32(r_tmp
, cpu_env
, off
);
2788 tcg_temp_free(r_tmp
);
2791 static inline void gen_mtc0_store64 (TCGv t
, target_ulong off
)
2793 tcg_gen_ext32s_tl(t
, t
);
2794 tcg_gen_st_tl(t
, cpu_env
, off
);
2797 static void gen_mfc0 (CPUState
*env
, DisasContext
*ctx
, TCGv t0
, int reg
, int sel
)
2799 const char *rn
= "invalid";
2802 check_insn(env
, ctx
, ISA_MIPS32
);
2808 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Index
));
2812 check_insn(env
, ctx
, ASE_MT
);
2813 tcg_gen_helper_1_0(do_mfc0_mvpcontrol
, t0
);
2817 check_insn(env
, ctx
, ASE_MT
);
2818 tcg_gen_helper_1_0(do_mfc0_mvpconf0
, t0
);
2822 check_insn(env
, ctx
, ASE_MT
);
2823 tcg_gen_helper_1_0(do_mfc0_mvpconf1
, t0
);
2833 tcg_gen_helper_1_0(do_mfc0_random
, t0
);
2837 check_insn(env
, ctx
, ASE_MT
);
2838 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEControl
));
2842 check_insn(env
, ctx
, ASE_MT
);
2843 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEConf0
));
2847 check_insn(env
, ctx
, ASE_MT
);
2848 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEConf1
));
2852 check_insn(env
, ctx
, ASE_MT
);
2853 gen_mfc0_load64(t0
, offsetof(CPUState
, CP0_YQMask
));
2857 check_insn(env
, ctx
, ASE_MT
);
2858 gen_mfc0_load64(t0
, offsetof(CPUState
, CP0_VPESchedule
));
2862 check_insn(env
, ctx
, ASE_MT
);
2863 gen_mfc0_load64(t0
, offsetof(CPUState
, CP0_VPEScheFBack
));
2864 rn
= "VPEScheFBack";
2867 check_insn(env
, ctx
, ASE_MT
);
2868 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEOpt
));
2878 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryLo0
));
2879 tcg_gen_ext32s_tl(t0
, t0
);
2883 check_insn(env
, ctx
, ASE_MT
);
2884 tcg_gen_helper_1_0(do_mfc0_tcstatus
, t0
);
2888 check_insn(env
, ctx
, ASE_MT
);
2889 tcg_gen_helper_1_0(do_mfc0_tcbind
, t0
);
2893 check_insn(env
, ctx
, ASE_MT
);
2894 tcg_gen_helper_1_0(do_mfc0_tcrestart
, t0
);
2898 check_insn(env
, ctx
, ASE_MT
);
2899 tcg_gen_helper_1_0(do_mfc0_tchalt
, t0
);
2903 check_insn(env
, ctx
, ASE_MT
);
2904 tcg_gen_helper_1_0(do_mfc0_tccontext
, t0
);
2908 check_insn(env
, ctx
, ASE_MT
);
2909 tcg_gen_helper_1_0(do_mfc0_tcschedule
, t0
);
2913 check_insn(env
, ctx
, ASE_MT
);
2914 tcg_gen_helper_1_0(do_mfc0_tcschefback
, t0
);
2924 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryLo1
));
2925 tcg_gen_ext32s_tl(t0
, t0
);
2935 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_Context
));
2936 tcg_gen_ext32s_tl(t0
, t0
);
2940 // tcg_gen_helper_1_0(do_mfc0_contextconfig, t0); /* SmartMIPS ASE */
2941 rn
= "ContextConfig";
2950 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PageMask
));
2954 check_insn(env
, ctx
, ISA_MIPS32R2
);
2955 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PageGrain
));
2965 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Wired
));
2969 check_insn(env
, ctx
, ISA_MIPS32R2
);
2970 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf0
));
2974 check_insn(env
, ctx
, ISA_MIPS32R2
);
2975 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf1
));
2979 check_insn(env
, ctx
, ISA_MIPS32R2
);
2980 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf2
));
2984 check_insn(env
, ctx
, ISA_MIPS32R2
);
2985 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf3
));
2989 check_insn(env
, ctx
, ISA_MIPS32R2
);
2990 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf4
));
3000 check_insn(env
, ctx
, ISA_MIPS32R2
);
3001 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_HWREna
));
3011 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_BadVAddr
));
3012 tcg_gen_ext32s_tl(t0
, t0
);
3022 /* Mark as an IO operation because we read the time. */
3025 tcg_gen_helper_1_0(do_mfc0_count
, t0
);
3028 ctx
->bstate
= BS_STOP
;
3032 /* 6,7 are implementation dependent */
3040 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryHi
));
3041 tcg_gen_ext32s_tl(t0
, t0
);
3051 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Compare
));
3054 /* 6,7 are implementation dependent */
3062 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Status
));
3066 check_insn(env
, ctx
, ISA_MIPS32R2
);
3067 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_IntCtl
));
3071 check_insn(env
, ctx
, ISA_MIPS32R2
);
3072 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSCtl
));
3076 check_insn(env
, ctx
, ISA_MIPS32R2
);
3077 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSMap
));
3087 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Cause
));
3097 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
3098 tcg_gen_ext32s_tl(t0
, t0
);
3108 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PRid
));
3112 check_insn(env
, ctx
, ISA_MIPS32R2
);
3113 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_EBase
));
3123 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config0
));
3127 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config1
));
3131 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config2
));
3135 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config3
));
3138 /* 4,5 are reserved */
3139 /* 6,7 are implementation dependent */
3141 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config6
));
3145 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config7
));
3155 tcg_gen_helper_1_0(do_mfc0_lladdr
, t0
);
3165 tcg_gen_helper_1_i(do_mfc0_watchlo
, t0
, sel
);
3175 tcg_gen_helper_1_i(do_mfc0_watchhi
, t0
, sel
);
3185 #if defined(TARGET_MIPS64)
3186 check_insn(env
, ctx
, ISA_MIPS3
);
3187 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_XContext
));
3188 tcg_gen_ext32s_tl(t0
, t0
);
3197 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3200 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Framemask
));
3209 rn
= "'Diagnostic"; /* implementation dependent */
3214 tcg_gen_helper_1_0(do_mfc0_debug
, t0
); /* EJTAG support */
3218 // tcg_gen_helper_1_0(do_mfc0_tracecontrol, t0); /* PDtrace support */
3219 rn
= "TraceControl";
3222 // tcg_gen_helper_1_0(do_mfc0_tracecontrol2, t0); /* PDtrace support */
3223 rn
= "TraceControl2";
3226 // tcg_gen_helper_1_0(do_mfc0_usertracedata, t0); /* PDtrace support */
3227 rn
= "UserTraceData";
3230 // tcg_gen_helper_1_0(do_mfc0_tracebpc, t0); /* PDtrace support */
3241 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
3242 tcg_gen_ext32s_tl(t0
, t0
);
3252 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Performance0
));
3253 rn
= "Performance0";
3256 // tcg_gen_helper_1_0(do_mfc0_performance1, t0);
3257 rn
= "Performance1";
3260 // tcg_gen_helper_1_0(do_mfc0_performance2, t0);
3261 rn
= "Performance2";
3264 // tcg_gen_helper_1_0(do_mfc0_performance3, t0);
3265 rn
= "Performance3";
3268 // tcg_gen_helper_1_0(do_mfc0_performance4, t0);
3269 rn
= "Performance4";
3272 // tcg_gen_helper_1_0(do_mfc0_performance5, t0);
3273 rn
= "Performance5";
3276 // tcg_gen_helper_1_0(do_mfc0_performance6, t0);
3277 rn
= "Performance6";
3280 // tcg_gen_helper_1_0(do_mfc0_performance7, t0);
3281 rn
= "Performance7";
3306 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_TagLo
));
3313 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DataLo
));
3326 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_TagHi
));
3333 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DataHi
));
3343 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
3344 tcg_gen_ext32s_tl(t0
, t0
);
3355 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DESAVE
));
3365 #if defined MIPS_DEBUG_DISAS
3366 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3367 fprintf(logfile
, "mfc0 %s (reg %d sel %d)\n",
3374 #if defined MIPS_DEBUG_DISAS
3375 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3376 fprintf(logfile
, "mfc0 %s (reg %d sel %d)\n",
3380 generate_exception(ctx
, EXCP_RI
);
3383 static void gen_mtc0 (CPUState
*env
, DisasContext
*ctx
, TCGv t0
, int reg
, int sel
)
3385 const char *rn
= "invalid";
3388 check_insn(env
, ctx
, ISA_MIPS32
);
3397 tcg_gen_helper_0_1(do_mtc0_index
, t0
);
3401 check_insn(env
, ctx
, ASE_MT
);
3402 tcg_gen_helper_0_1(do_mtc0_mvpcontrol
, t0
);
3406 check_insn(env
, ctx
, ASE_MT
);
3411 check_insn(env
, ctx
, ASE_MT
);
3426 check_insn(env
, ctx
, ASE_MT
);
3427 tcg_gen_helper_0_1(do_mtc0_vpecontrol
, t0
);
3431 check_insn(env
, ctx
, ASE_MT
);
3432 tcg_gen_helper_0_1(do_mtc0_vpeconf0
, t0
);
3436 check_insn(env
, ctx
, ASE_MT
);
3437 tcg_gen_helper_0_1(do_mtc0_vpeconf1
, t0
);
3441 check_insn(env
, ctx
, ASE_MT
);
3442 tcg_gen_helper_0_1(do_mtc0_yqmask
, t0
);
3446 check_insn(env
, ctx
, ASE_MT
);
3447 gen_mtc0_store64(t0
, offsetof(CPUState
, CP0_VPESchedule
));
3451 check_insn(env
, ctx
, ASE_MT
);
3452 gen_mtc0_store64(t0
, offsetof(CPUState
, CP0_VPEScheFBack
));
3453 rn
= "VPEScheFBack";
3456 check_insn(env
, ctx
, ASE_MT
);
3457 tcg_gen_helper_0_1(do_mtc0_vpeopt
, t0
);
3467 tcg_gen_helper_0_1(do_mtc0_entrylo0
, t0
);
3471 check_insn(env
, ctx
, ASE_MT
);
3472 tcg_gen_helper_0_1(do_mtc0_tcstatus
, t0
);
3476 check_insn(env
, ctx
, ASE_MT
);
3477 tcg_gen_helper_0_1(do_mtc0_tcbind
, t0
);
3481 check_insn(env
, ctx
, ASE_MT
);
3482 tcg_gen_helper_0_1(do_mtc0_tcrestart
, t0
);
3486 check_insn(env
, ctx
, ASE_MT
);
3487 tcg_gen_helper_0_1(do_mtc0_tchalt
, t0
);
3491 check_insn(env
, ctx
, ASE_MT
);
3492 tcg_gen_helper_0_1(do_mtc0_tccontext
, t0
);
3496 check_insn(env
, ctx
, ASE_MT
);
3497 tcg_gen_helper_0_1(do_mtc0_tcschedule
, t0
);
3501 check_insn(env
, ctx
, ASE_MT
);
3502 tcg_gen_helper_0_1(do_mtc0_tcschefback
, t0
);
3512 tcg_gen_helper_0_1(do_mtc0_entrylo1
, t0
);
3522 tcg_gen_helper_0_1(do_mtc0_context
, t0
);
3526 // tcg_gen_helper_0_1(do_mtc0_contextconfig, t0); /* SmartMIPS ASE */
3527 rn
= "ContextConfig";
3536 tcg_gen_helper_0_1(do_mtc0_pagemask
, t0
);
3540 check_insn(env
, ctx
, ISA_MIPS32R2
);
3541 tcg_gen_helper_0_1(do_mtc0_pagegrain
, t0
);
3551 tcg_gen_helper_0_1(do_mtc0_wired
, t0
);
3555 check_insn(env
, ctx
, ISA_MIPS32R2
);
3556 tcg_gen_helper_0_1(do_mtc0_srsconf0
, t0
);
3560 check_insn(env
, ctx
, ISA_MIPS32R2
);
3561 tcg_gen_helper_0_1(do_mtc0_srsconf1
, t0
);
3565 check_insn(env
, ctx
, ISA_MIPS32R2
);
3566 tcg_gen_helper_0_1(do_mtc0_srsconf2
, t0
);
3570 check_insn(env
, ctx
, ISA_MIPS32R2
);
3571 tcg_gen_helper_0_1(do_mtc0_srsconf3
, t0
);
3575 check_insn(env
, ctx
, ISA_MIPS32R2
);
3576 tcg_gen_helper_0_1(do_mtc0_srsconf4
, t0
);
3586 check_insn(env
, ctx
, ISA_MIPS32R2
);
3587 tcg_gen_helper_0_1(do_mtc0_hwrena
, t0
);
3601 tcg_gen_helper_0_1(do_mtc0_count
, t0
);
3604 /* 6,7 are implementation dependent */
3608 /* Stop translation as we may have switched the execution mode */
3609 ctx
->bstate
= BS_STOP
;
3614 tcg_gen_helper_0_1(do_mtc0_entryhi
, t0
);
3624 tcg_gen_helper_0_1(do_mtc0_compare
, t0
);
3627 /* 6,7 are implementation dependent */
3631 /* Stop translation as we may have switched the execution mode */
3632 ctx
->bstate
= BS_STOP
;
3637 tcg_gen_helper_0_1(do_mtc0_status
, t0
);
3638 /* BS_STOP isn't good enough here, hflags may have changed. */
3639 gen_save_pc(ctx
->pc
+ 4);
3640 ctx
->bstate
= BS_EXCP
;
3644 check_insn(env
, ctx
, ISA_MIPS32R2
);
3645 tcg_gen_helper_0_1(do_mtc0_intctl
, t0
);
3646 /* Stop translation as we may have switched the execution mode */
3647 ctx
->bstate
= BS_STOP
;
3651 check_insn(env
, ctx
, ISA_MIPS32R2
);
3652 tcg_gen_helper_0_1(do_mtc0_srsctl
, t0
);
3653 /* Stop translation as we may have switched the execution mode */
3654 ctx
->bstate
= BS_STOP
;
3658 check_insn(env
, ctx
, ISA_MIPS32R2
);
3659 gen_mtc0_store32(t0
, offsetof(CPUState
, CP0_SRSMap
));
3660 /* Stop translation as we may have switched the execution mode */
3661 ctx
->bstate
= BS_STOP
;
3671 tcg_gen_helper_0_1(do_mtc0_cause
, t0
);
3677 /* Stop translation as we may have switched the execution mode */
3678 ctx
->bstate
= BS_STOP
;
3683 gen_mtc0_store64(t0
, offsetof(CPUState
, CP0_EPC
));
3697 check_insn(env
, ctx
, ISA_MIPS32R2
);
3698 tcg_gen_helper_0_1(do_mtc0_ebase
, t0
);
3708 tcg_gen_helper_0_1(do_mtc0_config0
, t0
);
3710 /* Stop translation as we may have switched the execution mode */
3711 ctx
->bstate
= BS_STOP
;
3714 /* ignored, read only */
3718 tcg_gen_helper_0_1(do_mtc0_config2
, t0
);
3720 /* Stop translation as we may have switched the execution mode */
3721 ctx
->bstate
= BS_STOP
;
3724 /* ignored, read only */
3727 /* 4,5 are reserved */
3728 /* 6,7 are implementation dependent */
3738 rn
= "Invalid config selector";
3755 tcg_gen_helper_0_1i(do_mtc0_watchlo
, t0
, sel
);
3765 tcg_gen_helper_0_1i(do_mtc0_watchhi
, t0
, sel
);
3775 #if defined(TARGET_MIPS64)
3776 check_insn(env
, ctx
, ISA_MIPS3
);
3777 tcg_gen_helper_0_1(do_mtc0_xcontext
, t0
);
3786 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3789 tcg_gen_helper_0_1(do_mtc0_framemask
, t0
);
3798 rn
= "Diagnostic"; /* implementation dependent */
3803 tcg_gen_helper_0_1(do_mtc0_debug
, t0
); /* EJTAG support */
3804 /* BS_STOP isn't good enough here, hflags may have changed. */
3805 gen_save_pc(ctx
->pc
+ 4);
3806 ctx
->bstate
= BS_EXCP
;
3810 // tcg_gen_helper_0_1(do_mtc0_tracecontrol, t0); /* PDtrace support */
3811 rn
= "TraceControl";
3812 /* Stop translation as we may have switched the execution mode */
3813 ctx
->bstate
= BS_STOP
;
3816 // tcg_gen_helper_0_1(do_mtc0_tracecontrol2, t0); /* PDtrace support */
3817 rn
= "TraceControl2";
3818 /* Stop translation as we may have switched the execution mode */
3819 ctx
->bstate
= BS_STOP
;
3822 /* Stop translation as we may have switched the execution mode */
3823 ctx
->bstate
= BS_STOP
;
3824 // tcg_gen_helper_0_1(do_mtc0_usertracedata, t0); /* PDtrace support */
3825 rn
= "UserTraceData";
3826 /* Stop translation as we may have switched the execution mode */
3827 ctx
->bstate
= BS_STOP
;
3830 // tcg_gen_helper_0_1(do_mtc0_tracebpc, t0); /* PDtrace support */
3831 /* Stop translation as we may have switched the execution mode */
3832 ctx
->bstate
= BS_STOP
;
3843 gen_mtc0_store64(t0
, offsetof(CPUState
, CP0_DEPC
));
3853 tcg_gen_helper_0_1(do_mtc0_performance0
, t0
);
3854 rn
= "Performance0";
3857 // tcg_gen_helper_0_1(do_mtc0_performance1, t0);
3858 rn
= "Performance1";
3861 // tcg_gen_helper_0_1(do_mtc0_performance2, t0);
3862 rn
= "Performance2";
3865 // tcg_gen_helper_0_1(do_mtc0_performance3, t0);
3866 rn
= "Performance3";
3869 // tcg_gen_helper_0_1(do_mtc0_performance4, t0);
3870 rn
= "Performance4";
3873 // tcg_gen_helper_0_1(do_mtc0_performance5, t0);
3874 rn
= "Performance5";
3877 // tcg_gen_helper_0_1(do_mtc0_performance6, t0);
3878 rn
= "Performance6";
3881 // tcg_gen_helper_0_1(do_mtc0_performance7, t0);
3882 rn
= "Performance7";
3908 tcg_gen_helper_0_1(do_mtc0_taglo
, t0
);
3915 tcg_gen_helper_0_1(do_mtc0_datalo
, t0
);
3928 tcg_gen_helper_0_1(do_mtc0_taghi
, t0
);
3935 tcg_gen_helper_0_1(do_mtc0_datahi
, t0
);
3946 gen_mtc0_store64(t0
, offsetof(CPUState
, CP0_ErrorEPC
));
3957 gen_mtc0_store32(t0
, offsetof(CPUState
, CP0_DESAVE
));
3963 /* Stop translation as we may have switched the execution mode */
3964 ctx
->bstate
= BS_STOP
;
3969 #if defined MIPS_DEBUG_DISAS
3970 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3971 fprintf(logfile
, "mtc0 %s (reg %d sel %d)\n",
3975 /* For simplicity assume that all writes can cause interrupts. */
3978 ctx
->bstate
= BS_STOP
;
3983 #if defined MIPS_DEBUG_DISAS
3984 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3985 fprintf(logfile
, "mtc0 %s (reg %d sel %d)\n",
3989 generate_exception(ctx
, EXCP_RI
);
3992 #if defined(TARGET_MIPS64)
3993 static void gen_dmfc0 (CPUState
*env
, DisasContext
*ctx
, TCGv t0
, int reg
, int sel
)
3995 const char *rn
= "invalid";
3998 check_insn(env
, ctx
, ISA_MIPS64
);
4004 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Index
));
4008 check_insn(env
, ctx
, ASE_MT
);
4009 tcg_gen_helper_1_0(do_mfc0_mvpcontrol
, t0
);
4013 check_insn(env
, ctx
, ASE_MT
);
4014 tcg_gen_helper_1_0(do_mfc0_mvpconf0
, t0
);
4018 check_insn(env
, ctx
, ASE_MT
);
4019 tcg_gen_helper_1_0(do_mfc0_mvpconf1
, t0
);
4029 tcg_gen_helper_1_0(do_mfc0_random
, t0
);
4033 check_insn(env
, ctx
, ASE_MT
);
4034 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEControl
));
4038 check_insn(env
, ctx
, ASE_MT
);
4039 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEConf0
));
4043 check_insn(env
, ctx
, ASE_MT
);
4044 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEConf1
));
4048 check_insn(env
, ctx
, ASE_MT
);
4049 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_YQMask
));
4053 check_insn(env
, ctx
, ASE_MT
);
4054 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_VPESchedule
));
4058 check_insn(env
, ctx
, ASE_MT
);
4059 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_VPEScheFBack
));
4060 rn
= "VPEScheFBack";
4063 check_insn(env
, ctx
, ASE_MT
);
4064 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEOpt
));
4074 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryLo0
));
4078 check_insn(env
, ctx
, ASE_MT
);
4079 tcg_gen_helper_1_0(do_mfc0_tcstatus
, t0
);
4083 check_insn(env
, ctx
, ASE_MT
);
4084 tcg_gen_helper_1_0(do_mfc0_tcbind
, t0
);
4088 check_insn(env
, ctx
, ASE_MT
);
4089 tcg_gen_helper_1_0(do_dmfc0_tcrestart
, t0
);
4093 check_insn(env
, ctx
, ASE_MT
);
4094 tcg_gen_helper_1_0(do_dmfc0_tchalt
, t0
);
4098 check_insn(env
, ctx
, ASE_MT
);
4099 tcg_gen_helper_1_0(do_dmfc0_tccontext
, t0
);
4103 check_insn(env
, ctx
, ASE_MT
);
4104 tcg_gen_helper_1_0(do_dmfc0_tcschedule
, t0
);
4108 check_insn(env
, ctx
, ASE_MT
);
4109 tcg_gen_helper_1_0(do_dmfc0_tcschefback
, t0
);
4119 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryLo1
));
4129 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_Context
));
4133 // tcg_gen_helper_1_0(do_dmfc0_contextconfig, t0); /* SmartMIPS ASE */
4134 rn
= "ContextConfig";
4143 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PageMask
));
4147 check_insn(env
, ctx
, ISA_MIPS32R2
);
4148 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PageGrain
));
4158 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Wired
));
4162 check_insn(env
, ctx
, ISA_MIPS32R2
);
4163 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf0
));
4167 check_insn(env
, ctx
, ISA_MIPS32R2
);
4168 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf1
));
4172 check_insn(env
, ctx
, ISA_MIPS32R2
);
4173 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf2
));
4177 check_insn(env
, ctx
, ISA_MIPS32R2
);
4178 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf3
));
4182 check_insn(env
, ctx
, ISA_MIPS32R2
);
4183 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf4
));
4193 check_insn(env
, ctx
, ISA_MIPS32R2
);
4194 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_HWREna
));
4204 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_BadVAddr
));
4214 /* Mark as an IO operation because we read the time. */
4217 tcg_gen_helper_1_0(do_mfc0_count
, t0
);
4220 ctx
->bstate
= BS_STOP
;
4224 /* 6,7 are implementation dependent */
4232 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryHi
));
4242 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Compare
));
4245 /* 6,7 are implementation dependent */
4253 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Status
));
4257 check_insn(env
, ctx
, ISA_MIPS32R2
);
4258 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_IntCtl
));
4262 check_insn(env
, ctx
, ISA_MIPS32R2
);
4263 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSCtl
));
4267 check_insn(env
, ctx
, ISA_MIPS32R2
);
4268 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSMap
));
4278 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Cause
));
4288 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
4298 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PRid
));
4302 check_insn(env
, ctx
, ISA_MIPS32R2
);
4303 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_EBase
));
4313 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config0
));
4317 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config1
));
4321 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config2
));
4325 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config3
));
4328 /* 6,7 are implementation dependent */
4330 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config6
));
4334 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config7
));
4344 tcg_gen_helper_1_0(do_dmfc0_lladdr
, t0
);
4354 tcg_gen_helper_1_i(do_dmfc0_watchlo
, t0
, sel
);
4364 tcg_gen_helper_1_i(do_mfc0_watchhi
, t0
, sel
);
4374 check_insn(env
, ctx
, ISA_MIPS3
);
4375 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_XContext
));
4383 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4386 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Framemask
));
4395 rn
= "'Diagnostic"; /* implementation dependent */
4400 tcg_gen_helper_1_0(do_mfc0_debug
, t0
); /* EJTAG support */
4404 // tcg_gen_helper_1_0(do_dmfc0_tracecontrol, t0); /* PDtrace support */
4405 rn
= "TraceControl";
4408 // tcg_gen_helper_1_0(do_dmfc0_tracecontrol2, t0); /* PDtrace support */
4409 rn
= "TraceControl2";
4412 // tcg_gen_helper_1_0(do_dmfc0_usertracedata, t0); /* PDtrace support */
4413 rn
= "UserTraceData";
4416 // tcg_gen_helper_1_0(do_dmfc0_tracebpc, t0); /* PDtrace support */
4427 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
4437 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Performance0
));
4438 rn
= "Performance0";
4441 // tcg_gen_helper_1_0(do_dmfc0_performance1, t0);
4442 rn
= "Performance1";
4445 // tcg_gen_helper_1_0(do_dmfc0_performance2, t0);
4446 rn
= "Performance2";
4449 // tcg_gen_helper_1_0(do_dmfc0_performance3, t0);
4450 rn
= "Performance3";
4453 // tcg_gen_helper_1_0(do_dmfc0_performance4, t0);
4454 rn
= "Performance4";
4457 // tcg_gen_helper_1_0(do_dmfc0_performance5, t0);
4458 rn
= "Performance5";
4461 // tcg_gen_helper_1_0(do_dmfc0_performance6, t0);
4462 rn
= "Performance6";
4465 // tcg_gen_helper_1_0(do_dmfc0_performance7, t0);
4466 rn
= "Performance7";
4491 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_TagLo
));
4498 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DataLo
));
4511 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_TagHi
));
4518 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DataHi
));
4528 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
4539 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DESAVE
));
4549 #if defined MIPS_DEBUG_DISAS
4550 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4551 fprintf(logfile
, "dmfc0 %s (reg %d sel %d)\n",
4558 #if defined MIPS_DEBUG_DISAS
4559 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4560 fprintf(logfile
, "dmfc0 %s (reg %d sel %d)\n",
4564 generate_exception(ctx
, EXCP_RI
);
4567 static void gen_dmtc0 (CPUState
*env
, DisasContext
*ctx
, TCGv t0
, int reg
, int sel
)
4569 const char *rn
= "invalid";
4572 check_insn(env
, ctx
, ISA_MIPS64
);
4581 tcg_gen_helper_0_1(do_mtc0_index
, t0
);
4585 check_insn(env
, ctx
, ASE_MT
);
4586 tcg_gen_helper_0_1(do_mtc0_mvpcontrol
, t0
);
4590 check_insn(env
, ctx
, ASE_MT
);
4595 check_insn(env
, ctx
, ASE_MT
);
4610 check_insn(env
, ctx
, ASE_MT
);
4611 tcg_gen_helper_0_1(do_mtc0_vpecontrol
, t0
);
4615 check_insn(env
, ctx
, ASE_MT
);
4616 tcg_gen_helper_0_1(do_mtc0_vpeconf0
, t0
);
4620 check_insn(env
, ctx
, ASE_MT
);
4621 tcg_gen_helper_0_1(do_mtc0_vpeconf1
, t0
);
4625 check_insn(env
, ctx
, ASE_MT
);
4626 tcg_gen_helper_0_1(do_mtc0_yqmask
, t0
);
4630 check_insn(env
, ctx
, ASE_MT
);
4631 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_VPESchedule
));
4635 check_insn(env
, ctx
, ASE_MT
);
4636 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_VPEScheFBack
));
4637 rn
= "VPEScheFBack";
4640 check_insn(env
, ctx
, ASE_MT
);
4641 tcg_gen_helper_0_1(do_mtc0_vpeopt
, t0
);
4651 tcg_gen_helper_0_1(do_mtc0_entrylo0
, t0
);
4655 check_insn(env
, ctx
, ASE_MT
);
4656 tcg_gen_helper_0_1(do_mtc0_tcstatus
, t0
);
4660 check_insn(env
, ctx
, ASE_MT
);
4661 tcg_gen_helper_0_1(do_mtc0_tcbind
, t0
);
4665 check_insn(env
, ctx
, ASE_MT
);
4666 tcg_gen_helper_0_1(do_mtc0_tcrestart
, t0
);
4670 check_insn(env
, ctx
, ASE_MT
);
4671 tcg_gen_helper_0_1(do_mtc0_tchalt
, t0
);
4675 check_insn(env
, ctx
, ASE_MT
);
4676 tcg_gen_helper_0_1(do_mtc0_tccontext
, t0
);
4680 check_insn(env
, ctx
, ASE_MT
);
4681 tcg_gen_helper_0_1(do_mtc0_tcschedule
, t0
);
4685 check_insn(env
, ctx
, ASE_MT
);
4686 tcg_gen_helper_0_1(do_mtc0_tcschefback
, t0
);
4696 tcg_gen_helper_0_1(do_mtc0_entrylo1
, t0
);
4706 tcg_gen_helper_0_1(do_mtc0_context
, t0
);
4710 // tcg_gen_helper_0_1(do_mtc0_contextconfig, t0); /* SmartMIPS ASE */
4711 rn
= "ContextConfig";
4720 tcg_gen_helper_0_1(do_mtc0_pagemask
, t0
);
4724 check_insn(env
, ctx
, ISA_MIPS32R2
);
4725 tcg_gen_helper_0_1(do_mtc0_pagegrain
, t0
);
4735 tcg_gen_helper_0_1(do_mtc0_wired
, t0
);
4739 check_insn(env
, ctx
, ISA_MIPS32R2
);
4740 tcg_gen_helper_0_1(do_mtc0_srsconf0
, t0
);
4744 check_insn(env
, ctx
, ISA_MIPS32R2
);
4745 tcg_gen_helper_0_1(do_mtc0_srsconf1
, t0
);
4749 check_insn(env
, ctx
, ISA_MIPS32R2
);
4750 tcg_gen_helper_0_1(do_mtc0_srsconf2
, t0
);
4754 check_insn(env
, ctx
, ISA_MIPS32R2
);
4755 tcg_gen_helper_0_1(do_mtc0_srsconf3
, t0
);
4759 check_insn(env
, ctx
, ISA_MIPS32R2
);
4760 tcg_gen_helper_0_1(do_mtc0_srsconf4
, t0
);
4770 check_insn(env
, ctx
, ISA_MIPS32R2
);
4771 tcg_gen_helper_0_1(do_mtc0_hwrena
, t0
);
4785 tcg_gen_helper_0_1(do_mtc0_count
, t0
);
4788 /* 6,7 are implementation dependent */
4792 /* Stop translation as we may have switched the execution mode */
4793 ctx
->bstate
= BS_STOP
;
4798 tcg_gen_helper_0_1(do_mtc0_entryhi
, t0
);
4808 tcg_gen_helper_0_1(do_mtc0_compare
, t0
);
4811 /* 6,7 are implementation dependent */
4815 /* Stop translation as we may have switched the execution mode */
4816 ctx
->bstate
= BS_STOP
;
4821 tcg_gen_helper_0_1(do_mtc0_status
, t0
);
4822 /* BS_STOP isn't good enough here, hflags may have changed. */
4823 gen_save_pc(ctx
->pc
+ 4);
4824 ctx
->bstate
= BS_EXCP
;
4828 check_insn(env
, ctx
, ISA_MIPS32R2
);
4829 tcg_gen_helper_0_1(do_mtc0_intctl
, t0
);
4830 /* Stop translation as we may have switched the execution mode */
4831 ctx
->bstate
= BS_STOP
;
4835 check_insn(env
, ctx
, ISA_MIPS32R2
);
4836 tcg_gen_helper_0_1(do_mtc0_srsctl
, t0
);
4837 /* Stop translation as we may have switched the execution mode */
4838 ctx
->bstate
= BS_STOP
;
4842 check_insn(env
, ctx
, ISA_MIPS32R2
);
4843 gen_mtc0_store32(t0
, offsetof(CPUState
, CP0_SRSMap
));
4844 /* Stop translation as we may have switched the execution mode */
4845 ctx
->bstate
= BS_STOP
;
4855 tcg_gen_helper_0_1(do_mtc0_cause
, t0
);
4861 /* Stop translation as we may have switched the execution mode */
4862 ctx
->bstate
= BS_STOP
;
4867 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
4881 check_insn(env
, ctx
, ISA_MIPS32R2
);
4882 tcg_gen_helper_0_1(do_mtc0_ebase
, t0
);
4892 tcg_gen_helper_0_1(do_mtc0_config0
, t0
);
4894 /* Stop translation as we may have switched the execution mode */
4895 ctx
->bstate
= BS_STOP
;
4902 tcg_gen_helper_0_1(do_mtc0_config2
, t0
);
4904 /* Stop translation as we may have switched the execution mode */
4905 ctx
->bstate
= BS_STOP
;
4911 /* 6,7 are implementation dependent */
4913 rn
= "Invalid config selector";
4930 tcg_gen_helper_0_1i(do_mtc0_watchlo
, t0
, sel
);
4940 tcg_gen_helper_0_1i(do_mtc0_watchhi
, t0
, sel
);
4950 check_insn(env
, ctx
, ISA_MIPS3
);
4951 tcg_gen_helper_0_1(do_mtc0_xcontext
, t0
);
4959 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4962 tcg_gen_helper_0_1(do_mtc0_framemask
, t0
);
4971 rn
= "Diagnostic"; /* implementation dependent */
4976 tcg_gen_helper_0_1(do_mtc0_debug
, t0
); /* EJTAG support */
4977 /* BS_STOP isn't good enough here, hflags may have changed. */
4978 gen_save_pc(ctx
->pc
+ 4);
4979 ctx
->bstate
= BS_EXCP
;
4983 // tcg_gen_helper_0_1(do_mtc0_tracecontrol, t0); /* PDtrace support */
4984 /* Stop translation as we may have switched the execution mode */
4985 ctx
->bstate
= BS_STOP
;
4986 rn
= "TraceControl";
4989 // tcg_gen_helper_0_1(do_mtc0_tracecontrol2, t0); /* PDtrace support */
4990 /* Stop translation as we may have switched the execution mode */
4991 ctx
->bstate
= BS_STOP
;
4992 rn
= "TraceControl2";
4995 // tcg_gen_helper_0_1(do_mtc0_usertracedata, t0); /* PDtrace support */
4996 /* Stop translation as we may have switched the execution mode */
4997 ctx
->bstate
= BS_STOP
;
4998 rn
= "UserTraceData";
5001 // tcg_gen_helper_0_1(do_mtc0_tracebpc, t0); /* PDtrace support */
5002 /* Stop translation as we may have switched the execution mode */
5003 ctx
->bstate
= BS_STOP
;
5014 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
5024 tcg_gen_helper_0_1(do_mtc0_performance0
, t0
);
5025 rn
= "Performance0";
5028 // tcg_gen_helper_0_1(do_mtc0_performance1, t0);
5029 rn
= "Performance1";
5032 // tcg_gen_helper_0_1(do_mtc0_performance2, t0);
5033 rn
= "Performance2";
5036 // tcg_gen_helper_0_1(do_mtc0_performance3, t0);
5037 rn
= "Performance3";
5040 // tcg_gen_helper_0_1(do_mtc0_performance4, t0);
5041 rn
= "Performance4";
5044 // tcg_gen_helper_0_1(do_mtc0_performance5, t0);
5045 rn
= "Performance5";
5048 // tcg_gen_helper_0_1(do_mtc0_performance6, t0);
5049 rn
= "Performance6";
5052 // tcg_gen_helper_0_1(do_mtc0_performance7, t0);
5053 rn
= "Performance7";
5079 tcg_gen_helper_0_1(do_mtc0_taglo
, t0
);
5086 tcg_gen_helper_0_1(do_mtc0_datalo
, t0
);
5099 tcg_gen_helper_0_1(do_mtc0_taghi
, t0
);
5106 tcg_gen_helper_0_1(do_mtc0_datahi
, t0
);
5117 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
5128 gen_mtc0_store32(t0
, offsetof(CPUState
, CP0_DESAVE
));
5134 /* Stop translation as we may have switched the execution mode */
5135 ctx
->bstate
= BS_STOP
;
5140 #if defined MIPS_DEBUG_DISAS
5141 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
5142 fprintf(logfile
, "dmtc0 %s (reg %d sel %d)\n",
5146 /* For simplicity assume that all writes can cause interrupts. */
5149 ctx
->bstate
= BS_STOP
;
5154 #if defined MIPS_DEBUG_DISAS
5155 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
5156 fprintf(logfile
, "dmtc0 %s (reg %d sel %d)\n",
5160 generate_exception(ctx
, EXCP_RI
);
5162 #endif /* TARGET_MIPS64 */
5164 static void gen_mftr(CPUState
*env
, DisasContext
*ctx
, int rt
, int rd
,
5165 int u
, int sel
, int h
)
5167 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
5168 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
5170 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
5171 ((env
->tcs
[other_tc
].CP0_TCBind
& (0xf << CP0TCBd_CurVPE
)) !=
5172 (env
->active_tc
.CP0_TCBind
& (0xf << CP0TCBd_CurVPE
))))
5173 tcg_gen_movi_tl(t0
, -1);
5174 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
5175 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
5176 tcg_gen_movi_tl(t0
, -1);
5182 tcg_gen_helper_1_1(do_mftc0_tcstatus
, t0
, t0
);
5185 tcg_gen_helper_1_1(do_mftc0_tcbind
, t0
, t0
);
5188 tcg_gen_helper_1_1(do_mftc0_tcrestart
, t0
, t0
);
5191 tcg_gen_helper_1_1(do_mftc0_tchalt
, t0
, t0
);
5194 tcg_gen_helper_1_1(do_mftc0_tccontext
, t0
, t0
);
5197 tcg_gen_helper_1_1(do_mftc0_tcschedule
, t0
, t0
);
5200 tcg_gen_helper_1_1(do_mftc0_tcschefback
, t0
, t0
);
5203 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5210 tcg_gen_helper_1_1(do_mftc0_entryhi
, t0
, t0
);
5213 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5219 tcg_gen_helper_1_1(do_mftc0_status
, t0
, t0
);
5222 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5228 tcg_gen_helper_1_1(do_mftc0_debug
, t0
, t0
);
5231 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5236 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5238 } else switch (sel
) {
5239 /* GPR registers. */
5241 tcg_gen_helper_1_1i(do_mftgpr
, t0
, t0
, rt
);
5243 /* Auxiliary CPU registers */
5247 tcg_gen_helper_1_1i(do_mftlo
, t0
, t0
, 0);
5250 tcg_gen_helper_1_1i(do_mfthi
, t0
, t0
, 0);
5253 tcg_gen_helper_1_1i(do_mftacx
, t0
, t0
, 0);
5256 tcg_gen_helper_1_1i(do_mftlo
, t0
, t0
, 1);
5259 tcg_gen_helper_1_1i(do_mfthi
, t0
, t0
, 1);
5262 tcg_gen_helper_1_1i(do_mftacx
, t0
, t0
, 1);
5265 tcg_gen_helper_1_1i(do_mftlo
, t0
, t0
, 2);
5268 tcg_gen_helper_1_1i(do_mfthi
, t0
, t0
, 2);
5271 tcg_gen_helper_1_1i(do_mftacx
, t0
, t0
, 2);
5274 tcg_gen_helper_1_1i(do_mftlo
, t0
, t0
, 3);
5277 tcg_gen_helper_1_1i(do_mfthi
, t0
, t0
, 3);
5280 tcg_gen_helper_1_1i(do_mftacx
, t0
, t0
, 3);
5283 tcg_gen_helper_1_1(do_mftdsp
, t0
, t0
);
5289 /* Floating point (COP1). */
5291 /* XXX: For now we support only a single FPU context. */
5293 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
5295 gen_load_fpr32(fp0
, rt
);
5296 tcg_gen_ext_i32_tl(t0
, fp0
);
5299 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
5301 gen_load_fpr32h(fp0
, rt
);
5302 tcg_gen_ext_i32_tl(t0
, fp0
);
5307 /* XXX: For now we support only a single FPU context. */
5308 tcg_gen_helper_1_1i(do_cfc1
, t0
, t0
, rt
);
5310 /* COP2: Not implemented. */
5317 #if defined MIPS_DEBUG_DISAS
5318 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
5319 fprintf(logfile
, "mftr (reg %d u %d sel %d h %d)\n",
5323 gen_store_gpr(t0
, rd
);
5329 #if defined MIPS_DEBUG_DISAS
5330 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
5331 fprintf(logfile
, "mftr (reg %d u %d sel %d h %d)\n",
5335 generate_exception(ctx
, EXCP_RI
);
5338 static void gen_mttr(CPUState
*env
, DisasContext
*ctx
, int rd
, int rt
,
5339 int u
, int sel
, int h
)
5341 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
5342 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
5344 gen_load_gpr(t0
, rt
);
5345 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
5346 ((env
->tcs
[other_tc
].CP0_TCBind
& (0xf << CP0TCBd_CurVPE
)) !=
5347 (env
->active_tc
.CP0_TCBind
& (0xf << CP0TCBd_CurVPE
))))
5349 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
5350 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
5357 tcg_gen_helper_0_1(do_mttc0_tcstatus
, t0
);
5360 tcg_gen_helper_0_1(do_mttc0_tcbind
, t0
);
5363 tcg_gen_helper_0_1(do_mttc0_tcrestart
, t0
);
5366 tcg_gen_helper_0_1(do_mttc0_tchalt
, t0
);
5369 tcg_gen_helper_0_1(do_mttc0_tccontext
, t0
);
5372 tcg_gen_helper_0_1(do_mttc0_tcschedule
, t0
);
5375 tcg_gen_helper_0_1(do_mttc0_tcschefback
, t0
);
5378 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5385 tcg_gen_helper_0_1(do_mttc0_entryhi
, t0
);
5388 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5394 tcg_gen_helper_0_1(do_mttc0_status
, t0
);
5397 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5403 tcg_gen_helper_0_1(do_mttc0_debug
, t0
);
5406 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5411 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5413 } else switch (sel
) {
5414 /* GPR registers. */
5416 tcg_gen_helper_0_1i(do_mttgpr
, t0
, rd
);
5418 /* Auxiliary CPU registers */
5422 tcg_gen_helper_0_1i(do_mttlo
, t0
, 0);
5425 tcg_gen_helper_0_1i(do_mtthi
, t0
, 0);
5428 tcg_gen_helper_0_1i(do_mttacx
, t0
, 0);
5431 tcg_gen_helper_0_1i(do_mttlo
, t0
, 1);
5434 tcg_gen_helper_0_1i(do_mtthi
, t0
, 1);
5437 tcg_gen_helper_0_1i(do_mttacx
, t0
, 1);
5440 tcg_gen_helper_0_1i(do_mttlo
, t0
, 2);
5443 tcg_gen_helper_0_1i(do_mtthi
, t0
, 2);
5446 tcg_gen_helper_0_1i(do_mttacx
, t0
, 2);
5449 tcg_gen_helper_0_1i(do_mttlo
, t0
, 3);
5452 tcg_gen_helper_0_1i(do_mtthi
, t0
, 3);
5455 tcg_gen_helper_0_1i(do_mttacx
, t0
, 3);
5458 tcg_gen_helper_0_1(do_mttdsp
, t0
);
5464 /* Floating point (COP1). */
5466 /* XXX: For now we support only a single FPU context. */
5468 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
5470 tcg_gen_trunc_tl_i32(fp0
, t0
);
5471 gen_store_fpr32(fp0
, rd
);
5474 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
5476 tcg_gen_trunc_tl_i32(fp0
, t0
);
5477 gen_store_fpr32h(fp0
, rd
);
5482 /* XXX: For now we support only a single FPU context. */
5483 tcg_gen_helper_0_1i(do_ctc1
, t0
, rd
);
5485 /* COP2: Not implemented. */
5492 #if defined MIPS_DEBUG_DISAS
5493 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
5494 fprintf(logfile
, "mttr (reg %d u %d sel %d h %d)\n",
5503 #if defined MIPS_DEBUG_DISAS
5504 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
5505 fprintf(logfile
, "mttr (reg %d u %d sel %d h %d)\n",
5509 generate_exception(ctx
, EXCP_RI
);
5512 static void gen_cp0 (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
, int rt
, int rd
)
5514 const char *opn
= "ldst";
5523 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
5525 gen_mfc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5526 gen_store_gpr(t0
, rt
);
5533 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
5535 gen_load_gpr(t0
, rt
);
5536 save_cpu_state(ctx
, 1);
5537 gen_mtc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5542 #if defined(TARGET_MIPS64)
5544 check_insn(env
, ctx
, ISA_MIPS3
);
5550 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
5552 gen_dmfc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5553 gen_store_gpr(t0
, rt
);
5559 check_insn(env
, ctx
, ISA_MIPS3
);
5561 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
5563 gen_load_gpr(t0
, rt
);
5564 save_cpu_state(ctx
, 1);
5565 gen_dmtc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5572 check_insn(env
, ctx
, ASE_MT
);
5577 gen_mftr(env
, ctx
, rt
, rd
, (ctx
->opcode
>> 5) & 1,
5578 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
5582 check_insn(env
, ctx
, ASE_MT
);
5583 gen_mttr(env
, ctx
, rd
, rt
, (ctx
->opcode
>> 5) & 1,
5584 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
5589 if (!env
->tlb
->do_tlbwi
)
5591 tcg_gen_helper_0_0(env
->tlb
->do_tlbwi
);
5595 if (!env
->tlb
->do_tlbwr
)
5597 tcg_gen_helper_0_0(env
->tlb
->do_tlbwr
);
5601 if (!env
->tlb
->do_tlbp
)
5603 tcg_gen_helper_0_0(env
->tlb
->do_tlbp
);
5607 if (!env
->tlb
->do_tlbr
)
5609 tcg_gen_helper_0_0(env
->tlb
->do_tlbr
);
5613 check_insn(env
, ctx
, ISA_MIPS2
);
5614 save_cpu_state(ctx
, 1);
5615 tcg_gen_helper_0_0(do_eret
);
5616 ctx
->bstate
= BS_EXCP
;
5620 check_insn(env
, ctx
, ISA_MIPS32
);
5621 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
5623 generate_exception(ctx
, EXCP_RI
);
5625 save_cpu_state(ctx
, 1);
5626 tcg_gen_helper_0_0(do_deret
);
5627 ctx
->bstate
= BS_EXCP
;
5632 check_insn(env
, ctx
, ISA_MIPS3
| ISA_MIPS32
);
5633 /* If we get an exception, we want to restart at next instruction */
5635 save_cpu_state(ctx
, 1);
5637 tcg_gen_helper_0_0(do_wait
);
5638 ctx
->bstate
= BS_EXCP
;
5643 generate_exception(ctx
, EXCP_RI
);
5646 MIPS_DEBUG("%s %s %d", opn
, regnames
[rt
], rd
);
5648 #endif /* !CONFIG_USER_ONLY */
5650 /* CP1 Branches (before delay slot) */
5651 static void gen_compute_branch1 (CPUState
*env
, DisasContext
*ctx
, uint32_t op
,
5652 int32_t cc
, int32_t offset
)
5654 target_ulong btarget
;
5655 const char *opn
= "cp1 cond branch";
5656 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
5657 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
5660 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
5662 btarget
= ctx
->pc
+ 4 + offset
;
5667 int l1
= gen_new_label();
5668 int l2
= gen_new_label();
5669 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
5671 get_fp_cond(r_tmp1
);
5672 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
5673 tcg_temp_free(r_tmp1
);
5674 tcg_gen_not_tl(t0
, t0
);
5675 tcg_gen_movi_tl(t1
, 0x1 << cc
);
5676 tcg_gen_and_tl(t0
, t0
, t1
);
5677 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
5678 tcg_gen_movi_tl(t0
, 0);
5681 tcg_gen_movi_tl(t0
, 1);
5688 int l1
= gen_new_label();
5689 int l2
= gen_new_label();
5690 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
5692 get_fp_cond(r_tmp1
);
5693 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
5694 tcg_temp_free(r_tmp1
);
5695 tcg_gen_not_tl(t0
, t0
);
5696 tcg_gen_movi_tl(t1
, 0x1 << cc
);
5697 tcg_gen_and_tl(t0
, t0
, t1
);
5698 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
5699 tcg_gen_movi_tl(t0
, 0);
5702 tcg_gen_movi_tl(t0
, 1);
5709 int l1
= gen_new_label();
5710 int l2
= gen_new_label();
5711 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
5713 get_fp_cond(r_tmp1
);
5714 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
5715 tcg_temp_free(r_tmp1
);
5716 tcg_gen_movi_tl(t1
, 0x1 << cc
);
5717 tcg_gen_and_tl(t0
, t0
, t1
);
5718 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
5719 tcg_gen_movi_tl(t0
, 0);
5722 tcg_gen_movi_tl(t0
, 1);
5729 int l1
= gen_new_label();
5730 int l2
= gen_new_label();
5731 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
5733 get_fp_cond(r_tmp1
);
5734 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
5735 tcg_temp_free(r_tmp1
);
5736 tcg_gen_movi_tl(t1
, 0x1 << cc
);
5737 tcg_gen_and_tl(t0
, t0
, t1
);
5738 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
5739 tcg_gen_movi_tl(t0
, 0);
5742 tcg_gen_movi_tl(t0
, 1);
5747 ctx
->hflags
|= MIPS_HFLAG_BL
;
5748 tcg_gen_trunc_tl_i32(bcond
, t0
);
5752 int l1
= gen_new_label();
5753 int l2
= gen_new_label();
5754 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
5756 get_fp_cond(r_tmp1
);
5757 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
5758 tcg_temp_free(r_tmp1
);
5759 tcg_gen_not_tl(t0
, t0
);
5760 tcg_gen_movi_tl(t1
, 0x3 << cc
);
5761 tcg_gen_and_tl(t0
, t0
, t1
);
5762 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
5763 tcg_gen_movi_tl(t0
, 0);
5766 tcg_gen_movi_tl(t0
, 1);
5773 int l1
= gen_new_label();
5774 int l2
= gen_new_label();
5775 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
5777 get_fp_cond(r_tmp1
);
5778 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
5779 tcg_temp_free(r_tmp1
);
5780 tcg_gen_movi_tl(t1
, 0x3 << cc
);
5781 tcg_gen_and_tl(t0
, t0
, t1
);
5782 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
5783 tcg_gen_movi_tl(t0
, 0);
5786 tcg_gen_movi_tl(t0
, 1);
5793 int l1
= gen_new_label();
5794 int l2
= gen_new_label();
5795 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
5797 get_fp_cond(r_tmp1
);
5798 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
5799 tcg_temp_free(r_tmp1
);
5800 tcg_gen_not_tl(t0
, t0
);
5801 tcg_gen_movi_tl(t1
, 0xf << cc
);
5802 tcg_gen_and_tl(t0
, t0
, t1
);
5803 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
5804 tcg_gen_movi_tl(t0
, 0);
5807 tcg_gen_movi_tl(t0
, 1);
5814 int l1
= gen_new_label();
5815 int l2
= gen_new_label();
5816 TCGv r_tmp1
= tcg_temp_new(TCG_TYPE_I32
);
5818 get_fp_cond(r_tmp1
);
5819 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
5820 tcg_temp_free(r_tmp1
);
5821 tcg_gen_movi_tl(t1
, 0xf << cc
);
5822 tcg_gen_and_tl(t0
, t0
, t1
);
5823 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
5824 tcg_gen_movi_tl(t0
, 0);
5827 tcg_gen_movi_tl(t0
, 1);
5832 ctx
->hflags
|= MIPS_HFLAG_BC
;
5833 tcg_gen_trunc_tl_i32(bcond
, t0
);
5837 generate_exception (ctx
, EXCP_RI
);
5840 MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx
, opn
,
5841 ctx
->hflags
, btarget
);
5842 ctx
->btarget
= btarget
;
5849 /* Coprocessor 1 (FPU) */
5851 #define FOP(func, fmt) (((fmt) << 21) | (func))
5853 static void gen_cp1 (DisasContext
*ctx
, uint32_t opc
, int rt
, int fs
)
5855 const char *opn
= "cp1 move";
5856 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
5861 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
5863 gen_load_fpr32(fp0
, fs
);
5864 tcg_gen_ext_i32_tl(t0
, fp0
);
5867 gen_store_gpr(t0
, rt
);
5871 gen_load_gpr(t0
, rt
);
5873 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
5875 tcg_gen_trunc_tl_i32(fp0
, t0
);
5876 gen_store_fpr32(fp0
, fs
);
5882 tcg_gen_helper_1_i(do_cfc1
, t0
, fs
);
5883 gen_store_gpr(t0
, rt
);
5887 gen_load_gpr(t0
, rt
);
5888 tcg_gen_helper_0_1i(do_ctc1
, t0
, fs
);
5893 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
5895 gen_load_fpr64(ctx
, fp0
, fs
);
5896 tcg_gen_mov_tl(t0
, fp0
);
5899 gen_store_gpr(t0
, rt
);
5903 gen_load_gpr(t0
, rt
);
5905 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
5907 tcg_gen_mov_tl(fp0
, t0
);
5908 gen_store_fpr64(ctx
, fp0
, fs
);
5915 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
5917 gen_load_fpr32h(fp0
, fs
);
5918 tcg_gen_ext_i32_tl(t0
, fp0
);
5921 gen_store_gpr(t0
, rt
);
5925 gen_load_gpr(t0
, rt
);
5927 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
5929 tcg_gen_trunc_tl_i32(fp0
, t0
);
5930 gen_store_fpr32h(fp0
, fs
);
5937 generate_exception (ctx
, EXCP_RI
);
5940 MIPS_DEBUG("%s %s %s", opn
, regnames
[rt
], fregnames
[fs
]);
5946 static void gen_movci (DisasContext
*ctx
, int rd
, int rs
, int cc
, int tf
)
5948 int l1
= gen_new_label();
5951 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
5952 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
5953 TCGv r_tmp
= tcg_temp_local_new(TCG_TYPE_I32
);
5956 ccbit
= 1 << (24 + cc
);
5964 gen_load_gpr(t0
, rd
);
5965 gen_load_gpr(t1
, rs
);
5966 tcg_gen_andi_i32(r_tmp
, fpu_fcr31
, ccbit
);
5967 tcg_gen_brcondi_i32(cond
, r_tmp
, 0, l1
);
5968 tcg_temp_free(r_tmp
);
5970 tcg_gen_mov_tl(t0
, t1
);
5974 gen_store_gpr(t0
, rd
);
5978 static inline void gen_movcf_s (int fs
, int fd
, int cc
, int tf
)
5982 TCGv r_tmp1
= tcg_temp_local_new(TCG_TYPE_I32
);
5983 TCGv fp0
= tcg_temp_local_new(TCG_TYPE_I32
);
5984 TCGv fp1
= tcg_temp_local_new(TCG_TYPE_I32
);
5985 int l1
= gen_new_label();
5988 ccbit
= 1 << (24 + cc
);
5997 gen_load_fpr32(fp0
, fs
);
5998 gen_load_fpr32(fp1
, fd
);
5999 tcg_gen_andi_i32(r_tmp1
, fpu_fcr31
, ccbit
);
6000 tcg_gen_brcondi_i32(cond
, r_tmp1
, 0, l1
);
6001 tcg_gen_mov_i32(fp1
, fp0
);
6004 tcg_temp_free(r_tmp1
);
6005 gen_store_fpr32(fp1
, fd
);
6009 static inline void gen_movcf_d (DisasContext
*ctx
, int fs
, int fd
, int cc
, int tf
)
6013 TCGv r_tmp1
= tcg_temp_local_new(TCG_TYPE_I32
);
6014 TCGv fp0
= tcg_temp_local_new(TCG_TYPE_I64
);
6015 TCGv fp1
= tcg_temp_local_new(TCG_TYPE_I64
);
6016 int l1
= gen_new_label();
6019 ccbit
= 1 << (24 + cc
);
6028 gen_load_fpr64(ctx
, fp0
, fs
);
6029 gen_load_fpr64(ctx
, fp1
, fd
);
6030 tcg_gen_andi_i32(r_tmp1
, fpu_fcr31
, ccbit
);
6031 tcg_gen_brcondi_i32(cond
, r_tmp1
, 0, l1
);
6032 tcg_gen_mov_i64(fp1
, fp0
);
6035 tcg_temp_free(r_tmp1
);
6036 gen_store_fpr64(ctx
, fp1
, fd
);
6040 static inline void gen_movcf_ps (int fs
, int fd
, int cc
, int tf
)
6043 TCGv r_tmp1
= tcg_temp_local_new(TCG_TYPE_I32
);
6044 TCGv r_tmp2
= tcg_temp_local_new(TCG_TYPE_I32
);
6045 TCGv fp0
= tcg_temp_local_new(TCG_TYPE_I32
);
6046 TCGv fph0
= tcg_temp_local_new(TCG_TYPE_I32
);
6047 TCGv fp1
= tcg_temp_local_new(TCG_TYPE_I32
);
6048 TCGv fph1
= tcg_temp_local_new(TCG_TYPE_I32
);
6049 int l1
= gen_new_label();
6050 int l2
= gen_new_label();
6057 gen_load_fpr32(fp0
, fs
);
6058 gen_load_fpr32h(fph0
, fs
);
6059 gen_load_fpr32(fp1
, fd
);
6060 gen_load_fpr32h(fph1
, fd
);
6061 get_fp_cond(r_tmp1
);
6062 tcg_gen_shri_i32(r_tmp1
, r_tmp1
, cc
);
6063 tcg_gen_andi_i32(r_tmp2
, r_tmp1
, 0x1);
6064 tcg_gen_brcondi_i32(cond
, r_tmp2
, 0, l1
);
6065 tcg_gen_mov_i32(fp1
, fp0
);
6068 tcg_gen_andi_i32(r_tmp2
, r_tmp1
, 0x2);
6069 tcg_gen_brcondi_i32(cond
, r_tmp2
, 0, l2
);
6070 tcg_gen_mov_i32(fph1
, fph0
);
6071 tcg_temp_free(fph0
);
6073 tcg_temp_free(r_tmp1
);
6074 tcg_temp_free(r_tmp2
);
6075 gen_store_fpr32(fp1
, fd
);
6076 gen_store_fpr32h(fph1
, fd
);
6078 tcg_temp_free(fph1
);
6082 static void gen_farith (DisasContext
*ctx
, uint32_t op1
,
6083 int ft
, int fs
, int fd
, int cc
)
6085 const char *opn
= "farith";
6086 const char *condnames
[] = {
6104 const char *condnames_abs
[] = {
6122 enum { BINOP
, CMPOP
, OTHEROP
} optype
= OTHEROP
;
6123 uint32_t func
= ctx
->opcode
& 0x3f;
6125 switch (ctx
->opcode
& FOP(0x3f, 0x1f)) {
6128 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6129 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
6131 gen_load_fpr32(fp0
, fs
);
6132 gen_load_fpr32(fp1
, ft
);
6133 tcg_gen_helper_1_2(do_float_add_s
, fp0
, fp0
, fp1
);
6135 gen_store_fpr32(fp0
, fd
);
6143 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6144 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
6146 gen_load_fpr32(fp0
, fs
);
6147 gen_load_fpr32(fp1
, ft
);
6148 tcg_gen_helper_1_2(do_float_sub_s
, fp0
, fp0
, fp1
);
6150 gen_store_fpr32(fp0
, fd
);
6158 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6159 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
6161 gen_load_fpr32(fp0
, fs
);
6162 gen_load_fpr32(fp1
, ft
);
6163 tcg_gen_helper_1_2(do_float_mul_s
, fp0
, fp0
, fp1
);
6165 gen_store_fpr32(fp0
, fd
);
6173 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6174 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
6176 gen_load_fpr32(fp0
, fs
);
6177 gen_load_fpr32(fp1
, ft
);
6178 tcg_gen_helper_1_2(do_float_div_s
, fp0
, fp0
, fp1
);
6180 gen_store_fpr32(fp0
, fd
);
6188 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6190 gen_load_fpr32(fp0
, fs
);
6191 tcg_gen_helper_1_1(do_float_sqrt_s
, fp0
, fp0
);
6192 gen_store_fpr32(fp0
, fd
);
6199 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6201 gen_load_fpr32(fp0
, fs
);
6202 tcg_gen_helper_1_1(do_float_abs_s
, fp0
, fp0
);
6203 gen_store_fpr32(fp0
, fd
);
6210 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6212 gen_load_fpr32(fp0
, fs
);
6213 gen_store_fpr32(fp0
, fd
);
6220 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6222 gen_load_fpr32(fp0
, fs
);
6223 tcg_gen_helper_1_1(do_float_chs_s
, fp0
, fp0
);
6224 gen_store_fpr32(fp0
, fd
);
6230 check_cp1_64bitmode(ctx
);
6232 TCGv fp32
= tcg_temp_new(TCG_TYPE_I32
);
6233 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6235 gen_load_fpr32(fp32
, fs
);
6236 tcg_gen_helper_1_1(do_float_roundl_s
, fp64
, fp32
);
6237 tcg_temp_free(fp32
);
6238 gen_store_fpr64(ctx
, fp64
, fd
);
6239 tcg_temp_free(fp64
);
6244 check_cp1_64bitmode(ctx
);
6246 TCGv fp32
= tcg_temp_new(TCG_TYPE_I32
);
6247 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6249 gen_load_fpr32(fp32
, fs
);
6250 tcg_gen_helper_1_1(do_float_truncl_s
, fp64
, fp32
);
6251 tcg_temp_free(fp32
);
6252 gen_store_fpr64(ctx
, fp64
, fd
);
6253 tcg_temp_free(fp64
);
6258 check_cp1_64bitmode(ctx
);
6260 TCGv fp32
= tcg_temp_new(TCG_TYPE_I32
);
6261 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6263 gen_load_fpr32(fp32
, fs
);
6264 tcg_gen_helper_1_1(do_float_ceill_s
, fp64
, fp32
);
6265 tcg_temp_free(fp32
);
6266 gen_store_fpr64(ctx
, fp64
, fd
);
6267 tcg_temp_free(fp64
);
6272 check_cp1_64bitmode(ctx
);
6274 TCGv fp32
= tcg_temp_new(TCG_TYPE_I32
);
6275 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6277 gen_load_fpr32(fp32
, fs
);
6278 tcg_gen_helper_1_1(do_float_floorl_s
, fp64
, fp32
);
6279 tcg_temp_free(fp32
);
6280 gen_store_fpr64(ctx
, fp64
, fd
);
6281 tcg_temp_free(fp64
);
6287 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6289 gen_load_fpr32(fp0
, fs
);
6290 tcg_gen_helper_1_1(do_float_roundw_s
, fp0
, fp0
);
6291 gen_store_fpr32(fp0
, fd
);
6298 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6300 gen_load_fpr32(fp0
, fs
);
6301 tcg_gen_helper_1_1(do_float_truncw_s
, fp0
, fp0
);
6302 gen_store_fpr32(fp0
, fd
);
6309 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6311 gen_load_fpr32(fp0
, fs
);
6312 tcg_gen_helper_1_1(do_float_ceilw_s
, fp0
, fp0
);
6313 gen_store_fpr32(fp0
, fd
);
6320 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6322 gen_load_fpr32(fp0
, fs
);
6323 tcg_gen_helper_1_1(do_float_floorw_s
, fp0
, fp0
);
6324 gen_store_fpr32(fp0
, fd
);
6330 gen_movcf_s(fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
6335 int l1
= gen_new_label();
6336 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
6337 TCGv fp0
= tcg_temp_local_new(TCG_TYPE_I32
);
6339 gen_load_gpr(t0
, ft
);
6340 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
6342 gen_load_fpr32(fp0
, fs
);
6343 gen_store_fpr32(fp0
, fd
);
6351 int l1
= gen_new_label();
6352 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
6353 TCGv fp0
= tcg_temp_local_new(TCG_TYPE_I32
);
6355 gen_load_gpr(t0
, ft
);
6356 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
6358 gen_load_fpr32(fp0
, fs
);
6359 gen_store_fpr32(fp0
, fd
);
6368 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6370 gen_load_fpr32(fp0
, fs
);
6371 tcg_gen_helper_1_1(do_float_recip_s
, fp0
, fp0
);
6372 gen_store_fpr32(fp0
, fd
);
6380 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6382 gen_load_fpr32(fp0
, fs
);
6383 tcg_gen_helper_1_1(do_float_rsqrt_s
, fp0
, fp0
);
6384 gen_store_fpr32(fp0
, fd
);
6390 check_cp1_64bitmode(ctx
);
6392 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6393 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
6395 gen_load_fpr32(fp0
, fs
);
6396 gen_load_fpr32(fp1
, fd
);
6397 tcg_gen_helper_1_2(do_float_recip2_s
, fp0
, fp0
, fp1
);
6399 gen_store_fpr32(fp0
, fd
);
6405 check_cp1_64bitmode(ctx
);
6407 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6409 gen_load_fpr32(fp0
, fs
);
6410 tcg_gen_helper_1_1(do_float_recip1_s
, fp0
, fp0
);
6411 gen_store_fpr32(fp0
, fd
);
6417 check_cp1_64bitmode(ctx
);
6419 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6421 gen_load_fpr32(fp0
, fs
);
6422 tcg_gen_helper_1_1(do_float_rsqrt1_s
, fp0
, fp0
);
6423 gen_store_fpr32(fp0
, fd
);
6429 check_cp1_64bitmode(ctx
);
6431 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6432 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
6434 gen_load_fpr32(fp0
, fs
);
6435 gen_load_fpr32(fp1
, ft
);
6436 tcg_gen_helper_1_2(do_float_rsqrt2_s
, fp0
, fp0
, fp1
);
6438 gen_store_fpr32(fp0
, fd
);
6444 check_cp1_registers(ctx
, fd
);
6446 TCGv fp32
= tcg_temp_new(TCG_TYPE_I32
);
6447 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6449 gen_load_fpr32(fp32
, fs
);
6450 tcg_gen_helper_1_1(do_float_cvtd_s
, fp64
, fp32
);
6451 tcg_temp_free(fp32
);
6452 gen_store_fpr64(ctx
, fp64
, fd
);
6453 tcg_temp_free(fp64
);
6459 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6461 gen_load_fpr32(fp0
, fs
);
6462 tcg_gen_helper_1_1(do_float_cvtw_s
, fp0
, fp0
);
6463 gen_store_fpr32(fp0
, fd
);
6469 check_cp1_64bitmode(ctx
);
6471 TCGv fp32
= tcg_temp_new(TCG_TYPE_I32
);
6472 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6474 gen_load_fpr32(fp32
, fs
);
6475 tcg_gen_helper_1_1(do_float_cvtl_s
, fp64
, fp32
);
6476 tcg_temp_free(fp32
);
6477 gen_store_fpr64(ctx
, fp64
, fd
);
6478 tcg_temp_free(fp64
);
6483 check_cp1_64bitmode(ctx
);
6485 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6486 TCGv fp32_0
= tcg_temp_new(TCG_TYPE_I32
);
6487 TCGv fp32_1
= tcg_temp_new(TCG_TYPE_I32
);
6489 gen_load_fpr32(fp32_0
, fs
);
6490 gen_load_fpr32(fp32_1
, ft
);
6491 tcg_gen_concat_i32_i64(fp64
, fp32_0
, fp32_1
);
6492 tcg_temp_free(fp32_1
);
6493 tcg_temp_free(fp32_0
);
6494 gen_store_fpr64(ctx
, fp64
, fd
);
6495 tcg_temp_free(fp64
);
6516 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6517 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
6519 gen_load_fpr32(fp0
, fs
);
6520 gen_load_fpr32(fp1
, ft
);
6521 if (ctx
->opcode
& (1 << 6)) {
6523 gen_cmpabs_s(func
-48, fp0
, fp1
, cc
);
6524 opn
= condnames_abs
[func
-48];
6526 gen_cmp_s(func
-48, fp0
, fp1
, cc
);
6527 opn
= condnames
[func
-48];
6534 check_cp1_registers(ctx
, fs
| ft
| fd
);
6536 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6537 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
6539 gen_load_fpr64(ctx
, fp0
, fs
);
6540 gen_load_fpr64(ctx
, fp1
, ft
);
6541 tcg_gen_helper_1_2(do_float_add_d
, fp0
, fp0
, fp1
);
6543 gen_store_fpr64(ctx
, fp0
, fd
);
6550 check_cp1_registers(ctx
, fs
| ft
| fd
);
6552 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6553 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
6555 gen_load_fpr64(ctx
, fp0
, fs
);
6556 gen_load_fpr64(ctx
, fp1
, ft
);
6557 tcg_gen_helper_1_2(do_float_sub_d
, fp0
, fp0
, fp1
);
6559 gen_store_fpr64(ctx
, fp0
, fd
);
6566 check_cp1_registers(ctx
, fs
| ft
| fd
);
6568 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6569 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
6571 gen_load_fpr64(ctx
, fp0
, fs
);
6572 gen_load_fpr64(ctx
, fp1
, ft
);
6573 tcg_gen_helper_1_2(do_float_mul_d
, fp0
, fp0
, fp1
);
6575 gen_store_fpr64(ctx
, fp0
, fd
);
6582 check_cp1_registers(ctx
, fs
| ft
| fd
);
6584 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6585 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
6587 gen_load_fpr64(ctx
, fp0
, fs
);
6588 gen_load_fpr64(ctx
, fp1
, ft
);
6589 tcg_gen_helper_1_2(do_float_div_d
, fp0
, fp0
, fp1
);
6591 gen_store_fpr64(ctx
, fp0
, fd
);
6598 check_cp1_registers(ctx
, fs
| fd
);
6600 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6602 gen_load_fpr64(ctx
, fp0
, fs
);
6603 tcg_gen_helper_1_1(do_float_sqrt_d
, fp0
, fp0
);
6604 gen_store_fpr64(ctx
, fp0
, fd
);
6610 check_cp1_registers(ctx
, fs
| fd
);
6612 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6614 gen_load_fpr64(ctx
, fp0
, fs
);
6615 tcg_gen_helper_1_1(do_float_abs_d
, fp0
, fp0
);
6616 gen_store_fpr64(ctx
, fp0
, fd
);
6622 check_cp1_registers(ctx
, fs
| fd
);
6624 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6626 gen_load_fpr64(ctx
, fp0
, fs
);
6627 gen_store_fpr64(ctx
, fp0
, fd
);
6633 check_cp1_registers(ctx
, fs
| fd
);
6635 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6637 gen_load_fpr64(ctx
, fp0
, fs
);
6638 tcg_gen_helper_1_1(do_float_chs_d
, fp0
, fp0
);
6639 gen_store_fpr64(ctx
, fp0
, fd
);
6645 check_cp1_64bitmode(ctx
);
6647 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6649 gen_load_fpr64(ctx
, fp0
, fs
);
6650 tcg_gen_helper_1_1(do_float_roundl_d
, fp0
, fp0
);
6651 gen_store_fpr64(ctx
, fp0
, fd
);
6657 check_cp1_64bitmode(ctx
);
6659 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6661 gen_load_fpr64(ctx
, fp0
, fs
);
6662 tcg_gen_helper_1_1(do_float_truncl_d
, fp0
, fp0
);
6663 gen_store_fpr64(ctx
, fp0
, fd
);
6669 check_cp1_64bitmode(ctx
);
6671 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6673 gen_load_fpr64(ctx
, fp0
, fs
);
6674 tcg_gen_helper_1_1(do_float_ceill_d
, fp0
, fp0
);
6675 gen_store_fpr64(ctx
, fp0
, fd
);
6681 check_cp1_64bitmode(ctx
);
6683 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6685 gen_load_fpr64(ctx
, fp0
, fs
);
6686 tcg_gen_helper_1_1(do_float_floorl_d
, fp0
, fp0
);
6687 gen_store_fpr64(ctx
, fp0
, fd
);
6693 check_cp1_registers(ctx
, fs
);
6695 TCGv fp32
= tcg_temp_new(TCG_TYPE_I32
);
6696 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6698 gen_load_fpr64(ctx
, fp64
, fs
);
6699 tcg_gen_helper_1_1(do_float_roundw_d
, fp32
, fp64
);
6700 tcg_temp_free(fp64
);
6701 gen_store_fpr32(fp32
, fd
);
6702 tcg_temp_free(fp32
);
6707 check_cp1_registers(ctx
, fs
);
6709 TCGv fp32
= tcg_temp_new(TCG_TYPE_I32
);
6710 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6712 gen_load_fpr64(ctx
, fp64
, fs
);
6713 tcg_gen_helper_1_1(do_float_truncw_d
, fp32
, fp64
);
6714 tcg_temp_free(fp64
);
6715 gen_store_fpr32(fp32
, fd
);
6716 tcg_temp_free(fp32
);
6721 check_cp1_registers(ctx
, fs
);
6723 TCGv fp32
= tcg_temp_new(TCG_TYPE_I32
);
6724 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6726 gen_load_fpr64(ctx
, fp64
, fs
);
6727 tcg_gen_helper_1_1(do_float_ceilw_d
, fp32
, fp64
);
6728 tcg_temp_free(fp64
);
6729 gen_store_fpr32(fp32
, fd
);
6730 tcg_temp_free(fp32
);
6735 check_cp1_registers(ctx
, fs
);
6737 TCGv fp32
= tcg_temp_new(TCG_TYPE_I32
);
6738 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6740 gen_load_fpr64(ctx
, fp64
, fs
);
6741 tcg_gen_helper_1_1(do_float_floorw_d
, fp32
, fp64
);
6742 tcg_temp_free(fp64
);
6743 gen_store_fpr32(fp32
, fd
);
6744 tcg_temp_free(fp32
);
6749 gen_movcf_d(ctx
, fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
6754 int l1
= gen_new_label();
6755 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
6756 TCGv fp0
= tcg_temp_local_new(TCG_TYPE_I64
);
6758 gen_load_gpr(t0
, ft
);
6759 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
6761 gen_load_fpr64(ctx
, fp0
, fs
);
6762 gen_store_fpr64(ctx
, fp0
, fd
);
6770 int l1
= gen_new_label();
6771 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
6772 TCGv fp0
= tcg_temp_local_new(TCG_TYPE_I64
);
6774 gen_load_gpr(t0
, ft
);
6775 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
6777 gen_load_fpr64(ctx
, fp0
, fs
);
6778 gen_store_fpr64(ctx
, fp0
, fd
);
6785 check_cp1_64bitmode(ctx
);
6787 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6789 gen_load_fpr64(ctx
, fp0
, fs
);
6790 tcg_gen_helper_1_1(do_float_recip_d
, fp0
, fp0
);
6791 gen_store_fpr64(ctx
, fp0
, fd
);
6797 check_cp1_64bitmode(ctx
);
6799 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6801 gen_load_fpr64(ctx
, fp0
, fs
);
6802 tcg_gen_helper_1_1(do_float_rsqrt_d
, fp0
, fp0
);
6803 gen_store_fpr64(ctx
, fp0
, fd
);
6809 check_cp1_64bitmode(ctx
);
6811 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6812 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
6814 gen_load_fpr64(ctx
, fp0
, fs
);
6815 gen_load_fpr64(ctx
, fp1
, ft
);
6816 tcg_gen_helper_1_2(do_float_recip2_d
, fp0
, fp0
, fp1
);
6818 gen_store_fpr64(ctx
, fp0
, fd
);
6824 check_cp1_64bitmode(ctx
);
6826 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6828 gen_load_fpr64(ctx
, fp0
, fs
);
6829 tcg_gen_helper_1_1(do_float_recip1_d
, fp0
, fp0
);
6830 gen_store_fpr64(ctx
, fp0
, fd
);
6836 check_cp1_64bitmode(ctx
);
6838 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6840 gen_load_fpr64(ctx
, fp0
, fs
);
6841 tcg_gen_helper_1_1(do_float_rsqrt1_d
, fp0
, fp0
);
6842 gen_store_fpr64(ctx
, fp0
, fd
);
6848 check_cp1_64bitmode(ctx
);
6850 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6851 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
6853 gen_load_fpr64(ctx
, fp0
, fs
);
6854 gen_load_fpr64(ctx
, fp1
, ft
);
6855 tcg_gen_helper_1_2(do_float_rsqrt2_d
, fp0
, fp0
, fp1
);
6857 gen_store_fpr64(ctx
, fp0
, fd
);
6879 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6880 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
6882 gen_load_fpr64(ctx
, fp0
, fs
);
6883 gen_load_fpr64(ctx
, fp1
, ft
);
6884 if (ctx
->opcode
& (1 << 6)) {
6886 check_cp1_registers(ctx
, fs
| ft
);
6887 gen_cmpabs_d(func
-48, fp0
, fp1
, cc
);
6888 opn
= condnames_abs
[func
-48];
6890 check_cp1_registers(ctx
, fs
| ft
);
6891 gen_cmp_d(func
-48, fp0
, fp1
, cc
);
6892 opn
= condnames
[func
-48];
6899 check_cp1_registers(ctx
, fs
);
6901 TCGv fp32
= tcg_temp_new(TCG_TYPE_I32
);
6902 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6904 gen_load_fpr64(ctx
, fp64
, fs
);
6905 tcg_gen_helper_1_1(do_float_cvts_d
, fp32
, fp64
);
6906 tcg_temp_free(fp64
);
6907 gen_store_fpr32(fp32
, fd
);
6908 tcg_temp_free(fp32
);
6913 check_cp1_registers(ctx
, fs
);
6915 TCGv fp32
= tcg_temp_new(TCG_TYPE_I32
);
6916 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6918 gen_load_fpr64(ctx
, fp64
, fs
);
6919 tcg_gen_helper_1_1(do_float_cvtw_d
, fp32
, fp64
);
6920 tcg_temp_free(fp64
);
6921 gen_store_fpr32(fp32
, fd
);
6922 tcg_temp_free(fp32
);
6927 check_cp1_64bitmode(ctx
);
6929 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6931 gen_load_fpr64(ctx
, fp0
, fs
);
6932 tcg_gen_helper_1_1(do_float_cvtl_d
, fp0
, fp0
);
6933 gen_store_fpr64(ctx
, fp0
, fd
);
6940 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
6942 gen_load_fpr32(fp0
, fs
);
6943 tcg_gen_helper_1_1(do_float_cvts_w
, fp0
, fp0
);
6944 gen_store_fpr32(fp0
, fd
);
6950 check_cp1_registers(ctx
, fd
);
6952 TCGv fp32
= tcg_temp_new(TCG_TYPE_I32
);
6953 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6955 gen_load_fpr32(fp32
, fs
);
6956 tcg_gen_helper_1_1(do_float_cvtd_w
, fp64
, fp32
);
6957 tcg_temp_free(fp32
);
6958 gen_store_fpr64(ctx
, fp64
, fd
);
6959 tcg_temp_free(fp64
);
6964 check_cp1_64bitmode(ctx
);
6966 TCGv fp32
= tcg_temp_new(TCG_TYPE_I32
);
6967 TCGv fp64
= tcg_temp_new(TCG_TYPE_I64
);
6969 gen_load_fpr64(ctx
, fp64
, fs
);
6970 tcg_gen_helper_1_1(do_float_cvts_l
, fp32
, fp64
);
6971 tcg_temp_free(fp64
);
6972 gen_store_fpr32(fp32
, fd
);
6973 tcg_temp_free(fp32
);
6978 check_cp1_64bitmode(ctx
);
6980 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6982 gen_load_fpr64(ctx
, fp0
, fs
);
6983 tcg_gen_helper_1_1(do_float_cvtd_l
, fp0
, fp0
);
6984 gen_store_fpr64(ctx
, fp0
, fd
);
6990 check_cp1_64bitmode(ctx
);
6992 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
6994 gen_load_fpr64(ctx
, fp0
, fs
);
6995 tcg_gen_helper_1_1(do_float_cvtps_pw
, fp0
, fp0
);
6996 gen_store_fpr64(ctx
, fp0
, fd
);
7002 check_cp1_64bitmode(ctx
);
7004 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7005 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7007 gen_load_fpr64(ctx
, fp0
, fs
);
7008 gen_load_fpr64(ctx
, fp1
, ft
);
7009 tcg_gen_helper_1_2(do_float_add_ps
, fp0
, fp0
, fp1
);
7011 gen_store_fpr64(ctx
, fp0
, fd
);
7017 check_cp1_64bitmode(ctx
);
7019 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7020 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7022 gen_load_fpr64(ctx
, fp0
, fs
);
7023 gen_load_fpr64(ctx
, fp1
, ft
);
7024 tcg_gen_helper_1_2(do_float_sub_ps
, fp0
, fp0
, fp1
);
7026 gen_store_fpr64(ctx
, fp0
, fd
);
7032 check_cp1_64bitmode(ctx
);
7034 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7035 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7037 gen_load_fpr64(ctx
, fp0
, fs
);
7038 gen_load_fpr64(ctx
, fp1
, ft
);
7039 tcg_gen_helper_1_2(do_float_mul_ps
, fp0
, fp0
, fp1
);
7041 gen_store_fpr64(ctx
, fp0
, fd
);
7047 check_cp1_64bitmode(ctx
);
7049 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7051 gen_load_fpr64(ctx
, fp0
, fs
);
7052 tcg_gen_helper_1_1(do_float_abs_ps
, fp0
, fp0
);
7053 gen_store_fpr64(ctx
, fp0
, fd
);
7059 check_cp1_64bitmode(ctx
);
7061 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7063 gen_load_fpr64(ctx
, fp0
, fs
);
7064 gen_store_fpr64(ctx
, fp0
, fd
);
7070 check_cp1_64bitmode(ctx
);
7072 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7074 gen_load_fpr64(ctx
, fp0
, fs
);
7075 tcg_gen_helper_1_1(do_float_chs_ps
, fp0
, fp0
);
7076 gen_store_fpr64(ctx
, fp0
, fd
);
7082 check_cp1_64bitmode(ctx
);
7083 gen_movcf_ps(fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
7087 check_cp1_64bitmode(ctx
);
7089 int l1
= gen_new_label();
7090 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
7091 TCGv fp0
= tcg_temp_local_new(TCG_TYPE_I32
);
7092 TCGv fph0
= tcg_temp_local_new(TCG_TYPE_I32
);
7094 gen_load_gpr(t0
, ft
);
7095 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
7097 gen_load_fpr32(fp0
, fs
);
7098 gen_load_fpr32h(fph0
, fs
);
7099 gen_store_fpr32(fp0
, fd
);
7100 gen_store_fpr32h(fph0
, fd
);
7102 tcg_temp_free(fph0
);
7108 check_cp1_64bitmode(ctx
);
7110 int l1
= gen_new_label();
7111 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
7112 TCGv fp0
= tcg_temp_local_new(TCG_TYPE_I32
);
7113 TCGv fph0
= tcg_temp_local_new(TCG_TYPE_I32
);
7115 gen_load_gpr(t0
, ft
);
7116 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
7118 gen_load_fpr32(fp0
, fs
);
7119 gen_load_fpr32h(fph0
, fs
);
7120 gen_store_fpr32(fp0
, fd
);
7121 gen_store_fpr32h(fph0
, fd
);
7123 tcg_temp_free(fph0
);
7129 check_cp1_64bitmode(ctx
);
7131 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7132 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7134 gen_load_fpr64(ctx
, fp0
, ft
);
7135 gen_load_fpr64(ctx
, fp1
, fs
);
7136 tcg_gen_helper_1_2(do_float_addr_ps
, fp0
, fp0
, fp1
);
7138 gen_store_fpr64(ctx
, fp0
, fd
);
7144 check_cp1_64bitmode(ctx
);
7146 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7147 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7149 gen_load_fpr64(ctx
, fp0
, ft
);
7150 gen_load_fpr64(ctx
, fp1
, fs
);
7151 tcg_gen_helper_1_2(do_float_mulr_ps
, fp0
, fp0
, fp1
);
7153 gen_store_fpr64(ctx
, fp0
, fd
);
7159 check_cp1_64bitmode(ctx
);
7161 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7162 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7164 gen_load_fpr64(ctx
, fp0
, fs
);
7165 gen_load_fpr64(ctx
, fp1
, fd
);
7166 tcg_gen_helper_1_2(do_float_recip2_ps
, fp0
, fp0
, fp1
);
7168 gen_store_fpr64(ctx
, fp0
, fd
);
7174 check_cp1_64bitmode(ctx
);
7176 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7178 gen_load_fpr64(ctx
, fp0
, fs
);
7179 tcg_gen_helper_1_1(do_float_recip1_ps
, fp0
, fp0
);
7180 gen_store_fpr64(ctx
, fp0
, fd
);
7186 check_cp1_64bitmode(ctx
);
7188 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7190 gen_load_fpr64(ctx
, fp0
, fs
);
7191 tcg_gen_helper_1_1(do_float_rsqrt1_ps
, fp0
, fp0
);
7192 gen_store_fpr64(ctx
, fp0
, fd
);
7198 check_cp1_64bitmode(ctx
);
7200 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7201 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7203 gen_load_fpr64(ctx
, fp0
, fs
);
7204 gen_load_fpr64(ctx
, fp1
, ft
);
7205 tcg_gen_helper_1_2(do_float_rsqrt2_ps
, fp0
, fp0
, fp1
);
7207 gen_store_fpr64(ctx
, fp0
, fd
);
7213 check_cp1_64bitmode(ctx
);
7215 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
7217 gen_load_fpr32h(fp0
, fs
);
7218 tcg_gen_helper_1_1(do_float_cvts_pu
, fp0
, fp0
);
7219 gen_store_fpr32(fp0
, fd
);
7225 check_cp1_64bitmode(ctx
);
7227 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7229 gen_load_fpr64(ctx
, fp0
, fs
);
7230 tcg_gen_helper_1_1(do_float_cvtpw_ps
, fp0
, fp0
);
7231 gen_store_fpr64(ctx
, fp0
, fd
);
7237 check_cp1_64bitmode(ctx
);
7239 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
7241 gen_load_fpr32(fp0
, fs
);
7242 tcg_gen_helper_1_1(do_float_cvts_pl
, fp0
, fp0
);
7243 gen_store_fpr32(fp0
, fd
);
7249 check_cp1_64bitmode(ctx
);
7251 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
7252 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
7254 gen_load_fpr32(fp0
, fs
);
7255 gen_load_fpr32(fp1
, ft
);
7256 gen_store_fpr32h(fp0
, fd
);
7257 gen_store_fpr32(fp1
, fd
);
7264 check_cp1_64bitmode(ctx
);
7266 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
7267 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
7269 gen_load_fpr32(fp0
, fs
);
7270 gen_load_fpr32h(fp1
, ft
);
7271 gen_store_fpr32(fp1
, fd
);
7272 gen_store_fpr32h(fp0
, fd
);
7279 check_cp1_64bitmode(ctx
);
7281 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
7282 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
7284 gen_load_fpr32h(fp0
, fs
);
7285 gen_load_fpr32(fp1
, ft
);
7286 gen_store_fpr32(fp1
, fd
);
7287 gen_store_fpr32h(fp0
, fd
);
7294 check_cp1_64bitmode(ctx
);
7296 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
7297 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
7299 gen_load_fpr32h(fp0
, fs
);
7300 gen_load_fpr32h(fp1
, ft
);
7301 gen_store_fpr32(fp1
, fd
);
7302 gen_store_fpr32h(fp0
, fd
);
7324 check_cp1_64bitmode(ctx
);
7326 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7327 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7329 gen_load_fpr64(ctx
, fp0
, fs
);
7330 gen_load_fpr64(ctx
, fp1
, ft
);
7331 if (ctx
->opcode
& (1 << 6)) {
7332 gen_cmpabs_ps(func
-48, fp0
, fp1
, cc
);
7333 opn
= condnames_abs
[func
-48];
7335 gen_cmp_ps(func
-48, fp0
, fp1
, cc
);
7336 opn
= condnames
[func
-48];
7344 generate_exception (ctx
, EXCP_RI
);
7349 MIPS_DEBUG("%s %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fs
], fregnames
[ft
]);
7352 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fs
], fregnames
[ft
]);
7355 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fd
], fregnames
[fs
]);
7360 /* Coprocessor 3 (FPU) */
7361 static void gen_flt3_ldst (DisasContext
*ctx
, uint32_t opc
,
7362 int fd
, int fs
, int base
, int index
)
7364 const char *opn
= "extended float load/store";
7366 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
7367 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
7370 gen_load_gpr(t0
, index
);
7371 } else if (index
== 0) {
7372 gen_load_gpr(t0
, base
);
7374 gen_load_gpr(t0
, base
);
7375 gen_load_gpr(t1
, index
);
7376 gen_op_addr_add(t0
, t1
);
7378 /* Don't do NOP if destination is zero: we must perform the actual
7384 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
7386 tcg_gen_qemu_ld32s(fp0
, t0
, ctx
->mem_idx
);
7387 gen_store_fpr32(fp0
, fd
);
7394 check_cp1_registers(ctx
, fd
);
7396 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7398 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
7399 gen_store_fpr64(ctx
, fp0
, fd
);
7405 check_cp1_64bitmode(ctx
);
7406 tcg_gen_andi_tl(t0
, t0
, ~0x7);
7408 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7410 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
7411 gen_store_fpr64(ctx
, fp0
, fd
);
7419 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
7421 gen_load_fpr32(fp0
, fs
);
7422 tcg_gen_qemu_st32(fp0
, t0
, ctx
->mem_idx
);
7430 check_cp1_registers(ctx
, fs
);
7432 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7434 gen_load_fpr64(ctx
, fp0
, fs
);
7435 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
7442 check_cp1_64bitmode(ctx
);
7443 tcg_gen_andi_tl(t0
, t0
, ~0x7);
7445 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7447 gen_load_fpr64(ctx
, fp0
, fs
);
7448 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
7456 generate_exception(ctx
, EXCP_RI
);
7463 MIPS_DEBUG("%s %s, %s(%s)", opn
, fregnames
[store
? fs
: fd
],
7464 regnames
[index
], regnames
[base
]);
7467 static void gen_flt3_arith (DisasContext
*ctx
, uint32_t opc
,
7468 int fd
, int fr
, int fs
, int ft
)
7470 const char *opn
= "flt3_arith";
7474 check_cp1_64bitmode(ctx
);
7476 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
7477 TCGv fp0
= tcg_temp_local_new(TCG_TYPE_I32
);
7478 TCGv fph0
= tcg_temp_local_new(TCG_TYPE_I32
);
7479 TCGv fp1
= tcg_temp_local_new(TCG_TYPE_I32
);
7480 TCGv fph1
= tcg_temp_local_new(TCG_TYPE_I32
);
7481 int l1
= gen_new_label();
7482 int l2
= gen_new_label();
7484 gen_load_gpr(t0
, fr
);
7485 tcg_gen_andi_tl(t0
, t0
, 0x7);
7486 gen_load_fpr32(fp0
, fs
);
7487 gen_load_fpr32h(fph0
, fs
);
7488 gen_load_fpr32(fp1
, ft
);
7489 gen_load_fpr32h(fph1
, ft
);
7491 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
7492 gen_store_fpr32(fp0
, fd
);
7493 gen_store_fpr32h(fph0
, fd
);
7496 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 4, l2
);
7498 #ifdef TARGET_WORDS_BIGENDIAN
7499 gen_store_fpr32(fph1
, fd
);
7500 gen_store_fpr32h(fp0
, fd
);
7502 gen_store_fpr32(fph0
, fd
);
7503 gen_store_fpr32h(fp1
, fd
);
7507 tcg_temp_free(fph0
);
7509 tcg_temp_free(fph1
);
7516 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
7517 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
7518 TCGv fp2
= tcg_temp_new(TCG_TYPE_I32
);
7520 gen_load_fpr32(fp0
, fs
);
7521 gen_load_fpr32(fp1
, ft
);
7522 gen_load_fpr32(fp2
, fr
);
7523 tcg_gen_helper_1_3(do_float_muladd_s
, fp2
, fp0
, fp1
, fp2
);
7526 gen_store_fpr32(fp2
, fd
);
7533 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7535 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7536 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7537 TCGv fp2
= tcg_temp_new(TCG_TYPE_I64
);
7539 gen_load_fpr64(ctx
, fp0
, fs
);
7540 gen_load_fpr64(ctx
, fp1
, ft
);
7541 gen_load_fpr64(ctx
, fp2
, fr
);
7542 tcg_gen_helper_1_3(do_float_muladd_d
, fp2
, fp0
, fp1
, fp2
);
7545 gen_store_fpr64(ctx
, fp2
, fd
);
7551 check_cp1_64bitmode(ctx
);
7553 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7554 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7555 TCGv fp2
= tcg_temp_new(TCG_TYPE_I64
);
7557 gen_load_fpr64(ctx
, fp0
, fs
);
7558 gen_load_fpr64(ctx
, fp1
, ft
);
7559 gen_load_fpr64(ctx
, fp2
, fr
);
7560 tcg_gen_helper_1_3(do_float_muladd_ps
, fp2
, fp0
, fp1
, fp2
);
7563 gen_store_fpr64(ctx
, fp2
, fd
);
7571 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
7572 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
7573 TCGv fp2
= tcg_temp_new(TCG_TYPE_I32
);
7575 gen_load_fpr32(fp0
, fs
);
7576 gen_load_fpr32(fp1
, ft
);
7577 gen_load_fpr32(fp2
, fr
);
7578 tcg_gen_helper_1_3(do_float_mulsub_s
, fp2
, fp0
, fp1
, fp2
);
7581 gen_store_fpr32(fp2
, fd
);
7588 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7590 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7591 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7592 TCGv fp2
= tcg_temp_new(TCG_TYPE_I64
);
7594 gen_load_fpr64(ctx
, fp0
, fs
);
7595 gen_load_fpr64(ctx
, fp1
, ft
);
7596 gen_load_fpr64(ctx
, fp2
, fr
);
7597 tcg_gen_helper_1_3(do_float_mulsub_d
, fp2
, fp0
, fp1
, fp2
);
7600 gen_store_fpr64(ctx
, fp2
, fd
);
7606 check_cp1_64bitmode(ctx
);
7608 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7609 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7610 TCGv fp2
= tcg_temp_new(TCG_TYPE_I64
);
7612 gen_load_fpr64(ctx
, fp0
, fs
);
7613 gen_load_fpr64(ctx
, fp1
, ft
);
7614 gen_load_fpr64(ctx
, fp2
, fr
);
7615 tcg_gen_helper_1_3(do_float_mulsub_ps
, fp2
, fp0
, fp1
, fp2
);
7618 gen_store_fpr64(ctx
, fp2
, fd
);
7626 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
7627 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
7628 TCGv fp2
= tcg_temp_new(TCG_TYPE_I32
);
7630 gen_load_fpr32(fp0
, fs
);
7631 gen_load_fpr32(fp1
, ft
);
7632 gen_load_fpr32(fp2
, fr
);
7633 tcg_gen_helper_1_3(do_float_nmuladd_s
, fp2
, fp0
, fp1
, fp2
);
7636 gen_store_fpr32(fp2
, fd
);
7643 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7645 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7646 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7647 TCGv fp2
= tcg_temp_new(TCG_TYPE_I64
);
7649 gen_load_fpr64(ctx
, fp0
, fs
);
7650 gen_load_fpr64(ctx
, fp1
, ft
);
7651 gen_load_fpr64(ctx
, fp2
, fr
);
7652 tcg_gen_helper_1_3(do_float_nmuladd_d
, fp2
, fp0
, fp1
, fp2
);
7655 gen_store_fpr64(ctx
, fp2
, fd
);
7661 check_cp1_64bitmode(ctx
);
7663 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7664 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7665 TCGv fp2
= tcg_temp_new(TCG_TYPE_I64
);
7667 gen_load_fpr64(ctx
, fp0
, fs
);
7668 gen_load_fpr64(ctx
, fp1
, ft
);
7669 gen_load_fpr64(ctx
, fp2
, fr
);
7670 tcg_gen_helper_1_3(do_float_nmuladd_ps
, fp2
, fp0
, fp1
, fp2
);
7673 gen_store_fpr64(ctx
, fp2
, fd
);
7681 TCGv fp0
= tcg_temp_new(TCG_TYPE_I32
);
7682 TCGv fp1
= tcg_temp_new(TCG_TYPE_I32
);
7683 TCGv fp2
= tcg_temp_new(TCG_TYPE_I32
);
7685 gen_load_fpr32(fp0
, fs
);
7686 gen_load_fpr32(fp1
, ft
);
7687 gen_load_fpr32(fp2
, fr
);
7688 tcg_gen_helper_1_3(do_float_nmulsub_s
, fp2
, fp0
, fp1
, fp2
);
7691 gen_store_fpr32(fp2
, fd
);
7698 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7700 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7701 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7702 TCGv fp2
= tcg_temp_new(TCG_TYPE_I64
);
7704 gen_load_fpr64(ctx
, fp0
, fs
);
7705 gen_load_fpr64(ctx
, fp1
, ft
);
7706 gen_load_fpr64(ctx
, fp2
, fr
);
7707 tcg_gen_helper_1_3(do_float_nmulsub_d
, fp2
, fp0
, fp1
, fp2
);
7710 gen_store_fpr64(ctx
, fp2
, fd
);
7716 check_cp1_64bitmode(ctx
);
7718 TCGv fp0
= tcg_temp_new(TCG_TYPE_I64
);
7719 TCGv fp1
= tcg_temp_new(TCG_TYPE_I64
);
7720 TCGv fp2
= tcg_temp_new(TCG_TYPE_I64
);
7722 gen_load_fpr64(ctx
, fp0
, fs
);
7723 gen_load_fpr64(ctx
, fp1
, ft
);
7724 gen_load_fpr64(ctx
, fp2
, fr
);
7725 tcg_gen_helper_1_3(do_float_nmulsub_ps
, fp2
, fp0
, fp1
, fp2
);
7728 gen_store_fpr64(ctx
, fp2
, fd
);
7735 generate_exception (ctx
, EXCP_RI
);
7738 MIPS_DEBUG("%s %s, %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fr
],
7739 fregnames
[fs
], fregnames
[ft
]);
7742 /* ISA extensions (ASEs) */
7743 /* MIPS16 extension to MIPS32 */
7744 /* SmartMIPS extension to MIPS32 */
7746 #if defined(TARGET_MIPS64)
7748 /* MDMX extension to MIPS64 */
7752 static void decode_opc (CPUState
*env
, DisasContext
*ctx
)
7756 uint32_t op
, op1
, op2
;
7759 /* make sure instructions are on a word boundary */
7760 if (ctx
->pc
& 0x3) {
7761 env
->CP0_BadVAddr
= ctx
->pc
;
7762 generate_exception(ctx
, EXCP_AdEL
);
7766 /* Handle blikely not taken case */
7767 if ((ctx
->hflags
& MIPS_HFLAG_BMASK
) == MIPS_HFLAG_BL
) {
7768 int l1
= gen_new_label();
7770 MIPS_DEBUG("blikely condition (" TARGET_FMT_lx
")", ctx
->pc
+ 4);
7771 tcg_gen_brcondi_i32(TCG_COND_NE
, bcond
, 0, l1
);
7773 TCGv r_tmp
= tcg_temp_new(TCG_TYPE_I32
);
7775 tcg_gen_movi_i32(r_tmp
, ctx
->hflags
& ~MIPS_HFLAG_BMASK
);
7776 tcg_gen_st_i32(r_tmp
, cpu_env
, offsetof(CPUState
, hflags
));
7777 tcg_temp_free(r_tmp
);
7779 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
7782 op
= MASK_OP_MAJOR(ctx
->opcode
);
7783 rs
= (ctx
->opcode
>> 21) & 0x1f;
7784 rt
= (ctx
->opcode
>> 16) & 0x1f;
7785 rd
= (ctx
->opcode
>> 11) & 0x1f;
7786 sa
= (ctx
->opcode
>> 6) & 0x1f;
7787 imm
= (int16_t)ctx
->opcode
;
7790 op1
= MASK_SPECIAL(ctx
->opcode
);
7792 case OPC_SLL
: /* Arithmetic with immediate */
7793 case OPC_SRL
... OPC_SRA
:
7794 gen_arith_imm(env
, ctx
, op1
, rd
, rt
, sa
);
7796 case OPC_MOVZ
... OPC_MOVN
:
7797 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
7798 case OPC_SLLV
: /* Arithmetic */
7799 case OPC_SRLV
... OPC_SRAV
:
7800 case OPC_ADD
... OPC_NOR
:
7801 case OPC_SLT
... OPC_SLTU
:
7802 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
7804 case OPC_MULT
... OPC_DIVU
:
7806 check_insn(env
, ctx
, INSN_VR54XX
);
7807 op1
= MASK_MUL_VR54XX(ctx
->opcode
);
7808 gen_mul_vr54xx(ctx
, op1
, rd
, rs
, rt
);
7810 gen_muldiv(ctx
, op1
, rs
, rt
);
7812 case OPC_JR
... OPC_JALR
:
7813 gen_compute_branch(ctx
, op1
, rs
, rd
, sa
);
7815 case OPC_TGE
... OPC_TEQ
: /* Traps */
7817 gen_trap(ctx
, op1
, rs
, rt
, -1);
7819 case OPC_MFHI
: /* Move from HI/LO */
7821 gen_HILO(ctx
, op1
, rd
);
7824 case OPC_MTLO
: /* Move to HI/LO */
7825 gen_HILO(ctx
, op1
, rs
);
7827 case OPC_PMON
: /* Pmon entry point, also R4010 selsl */
7828 #ifdef MIPS_STRICT_STANDARD
7829 MIPS_INVAL("PMON / selsl");
7830 generate_exception(ctx
, EXCP_RI
);
7832 tcg_gen_helper_0_i(do_pmon
, sa
);
7836 generate_exception(ctx
, EXCP_SYSCALL
);
7839 generate_exception(ctx
, EXCP_BREAK
);
7842 #ifdef MIPS_STRICT_STANDARD
7844 generate_exception(ctx
, EXCP_RI
);
7846 /* Implemented as RI exception for now. */
7847 MIPS_INVAL("spim (unofficial)");
7848 generate_exception(ctx
, EXCP_RI
);
7856 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
7857 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
7858 save_cpu_state(ctx
, 1);
7859 check_cp1_enabled(ctx
);
7860 gen_movci(ctx
, rd
, rs
, (ctx
->opcode
>> 18) & 0x7,
7861 (ctx
->opcode
>> 16) & 1);
7863 generate_exception_err(ctx
, EXCP_CpU
, 1);
7867 #if defined(TARGET_MIPS64)
7868 /* MIPS64 specific opcodes */
7870 case OPC_DSRL
... OPC_DSRA
:
7872 case OPC_DSRL32
... OPC_DSRA32
:
7873 check_insn(env
, ctx
, ISA_MIPS3
);
7875 gen_arith_imm(env
, ctx
, op1
, rd
, rt
, sa
);
7878 case OPC_DSRLV
... OPC_DSRAV
:
7879 case OPC_DADD
... OPC_DSUBU
:
7880 check_insn(env
, ctx
, ISA_MIPS3
);
7882 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
7884 case OPC_DMULT
... OPC_DDIVU
:
7885 check_insn(env
, ctx
, ISA_MIPS3
);
7887 gen_muldiv(ctx
, op1
, rs
, rt
);
7890 default: /* Invalid */
7891 MIPS_INVAL("special");
7892 generate_exception(ctx
, EXCP_RI
);
7897 op1
= MASK_SPECIAL2(ctx
->opcode
);
7899 case OPC_MADD
... OPC_MADDU
: /* Multiply and add/sub */
7900 case OPC_MSUB
... OPC_MSUBU
:
7901 check_insn(env
, ctx
, ISA_MIPS32
);
7902 gen_muldiv(ctx
, op1
, rs
, rt
);
7905 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
7907 case OPC_CLZ
... OPC_CLO
:
7908 check_insn(env
, ctx
, ISA_MIPS32
);
7909 gen_cl(ctx
, op1
, rd
, rs
);
7912 /* XXX: not clear which exception should be raised
7913 * when in debug mode...
7915 check_insn(env
, ctx
, ISA_MIPS32
);
7916 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
7917 generate_exception(ctx
, EXCP_DBp
);
7919 generate_exception(ctx
, EXCP_DBp
);
7923 #if defined(TARGET_MIPS64)
7924 case OPC_DCLZ
... OPC_DCLO
:
7925 check_insn(env
, ctx
, ISA_MIPS64
);
7927 gen_cl(ctx
, op1
, rd
, rs
);
7930 default: /* Invalid */
7931 MIPS_INVAL("special2");
7932 generate_exception(ctx
, EXCP_RI
);
7937 op1
= MASK_SPECIAL3(ctx
->opcode
);
7941 check_insn(env
, ctx
, ISA_MIPS32R2
);
7942 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
7945 check_insn(env
, ctx
, ISA_MIPS32R2
);
7946 op2
= MASK_BSHFL(ctx
->opcode
);
7948 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
7949 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
7953 gen_load_gpr(t1
, rt
);
7954 tcg_gen_helper_1_1(do_wsbh
, t0
, t1
);
7955 gen_store_gpr(t0
, rd
);
7958 gen_load_gpr(t1
, rt
);
7959 tcg_gen_ext8s_tl(t0
, t1
);
7960 gen_store_gpr(t0
, rd
);
7963 gen_load_gpr(t1
, rt
);
7964 tcg_gen_ext16s_tl(t0
, t1
);
7965 gen_store_gpr(t0
, rd
);
7967 default: /* Invalid */
7968 MIPS_INVAL("bshfl");
7969 generate_exception(ctx
, EXCP_RI
);
7977 check_insn(env
, ctx
, ISA_MIPS32R2
);
7979 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
7983 save_cpu_state(ctx
, 1);
7984 tcg_gen_helper_1_0(do_rdhwr_cpunum
, t0
);
7987 save_cpu_state(ctx
, 1);
7988 tcg_gen_helper_1_0(do_rdhwr_synci_step
, t0
);
7991 save_cpu_state(ctx
, 1);
7992 tcg_gen_helper_1_0(do_rdhwr_cc
, t0
);
7995 save_cpu_state(ctx
, 1);
7996 tcg_gen_helper_1_0(do_rdhwr_ccres
, t0
);
7999 if (env
->user_mode_only
) {
8000 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, tls_value
));
8003 /* XXX: Some CPUs implement this in hardware.
8004 Not supported yet. */
8006 default: /* Invalid */
8007 MIPS_INVAL("rdhwr");
8008 generate_exception(ctx
, EXCP_RI
);
8011 gen_store_gpr(t0
, rt
);
8016 check_insn(env
, ctx
, ASE_MT
);
8018 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
8019 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
8021 gen_load_gpr(t0
, rt
);
8022 gen_load_gpr(t1
, rs
);
8023 tcg_gen_helper_0_2(do_fork
, t0
, t1
);
8029 check_insn(env
, ctx
, ASE_MT
);
8031 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
8033 gen_load_gpr(t0
, rs
);
8034 tcg_gen_helper_1_1(do_yield
, t0
, t0
);
8035 gen_store_gpr(t0
, rd
);
8039 #if defined(TARGET_MIPS64)
8040 case OPC_DEXTM
... OPC_DEXT
:
8041 case OPC_DINSM
... OPC_DINS
:
8042 check_insn(env
, ctx
, ISA_MIPS64R2
);
8044 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
8047 check_insn(env
, ctx
, ISA_MIPS64R2
);
8049 op2
= MASK_DBSHFL(ctx
->opcode
);
8051 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
8052 TCGv t1
= tcg_temp_local_new(TCG_TYPE_TL
);
8056 gen_load_gpr(t1
, rt
);
8057 tcg_gen_helper_1_1(do_dsbh
, t0
, t1
);
8060 gen_load_gpr(t1
, rt
);
8061 tcg_gen_helper_1_1(do_dshd
, t0
, t1
);
8063 default: /* Invalid */
8064 MIPS_INVAL("dbshfl");
8065 generate_exception(ctx
, EXCP_RI
);
8068 gen_store_gpr(t0
, rd
);
8074 default: /* Invalid */
8075 MIPS_INVAL("special3");
8076 generate_exception(ctx
, EXCP_RI
);
8081 op1
= MASK_REGIMM(ctx
->opcode
);
8083 case OPC_BLTZ
... OPC_BGEZL
: /* REGIMM branches */
8084 case OPC_BLTZAL
... OPC_BGEZALL
:
8085 gen_compute_branch(ctx
, op1
, rs
, -1, imm
<< 2);
8087 case OPC_TGEI
... OPC_TEQI
: /* REGIMM traps */
8089 gen_trap(ctx
, op1
, rs
, -1, imm
);
8092 check_insn(env
, ctx
, ISA_MIPS32R2
);
8095 default: /* Invalid */
8096 MIPS_INVAL("regimm");
8097 generate_exception(ctx
, EXCP_RI
);
8102 check_cp0_enabled(ctx
);
8103 op1
= MASK_CP0(ctx
->opcode
);
8109 #if defined(TARGET_MIPS64)
8113 #ifndef CONFIG_USER_ONLY
8114 if (!env
->user_mode_only
)
8115 gen_cp0(env
, ctx
, op1
, rt
, rd
);
8116 #endif /* !CONFIG_USER_ONLY */
8118 case OPC_C0_FIRST
... OPC_C0_LAST
:
8119 #ifndef CONFIG_USER_ONLY
8120 if (!env
->user_mode_only
)
8121 gen_cp0(env
, ctx
, MASK_C0(ctx
->opcode
), rt
, rd
);
8122 #endif /* !CONFIG_USER_ONLY */
8125 #ifndef CONFIG_USER_ONLY
8126 if (!env
->user_mode_only
) {
8127 TCGv t0
= tcg_temp_local_new(TCG_TYPE_TL
);
8129 op2
= MASK_MFMC0(ctx
->opcode
);
8132 check_insn(env
, ctx
, ASE_MT
);
8133 tcg_gen_helper_1_1(do_dmt
, t0
, t0
);
8136 check_insn(env
, ctx
, ASE_MT
);
8137 tcg_gen_helper_1_1(do_emt
, t0
, t0
);
8140 check_insn(env
, ctx
, ASE_MT
);
8141 tcg_gen_helper_1_1(do_dvpe
, t0
, t0
);
8144 check_insn(env
, ctx
, ASE_MT
);
8145 tcg_gen_helper_1_1(do_evpe
, t0
, t0
);
8148 check_insn(env
, ctx
, ISA_MIPS32R2
);
8149 save_cpu_state(ctx
, 1);
8150 tcg_gen_helper_1_0(do_di
, t0
);
8151 /* Stop translation as we may have switched the execution mode */
8152 ctx
->bstate
= BS_STOP
;
8155 check_insn(env
, ctx
, ISA_MIPS32R2
);
8156 save_cpu_state(ctx
, 1);
8157 tcg_gen_helper_1_0(do_ei
, t0
);
8158 /* Stop translation as we may have switched the execution mode */
8159 ctx
->bstate
= BS_STOP
;
8161 default: /* Invalid */
8162 MIPS_INVAL("mfmc0");
8163 generate_exception(ctx
, EXCP_RI
);
8166 gen_store_gpr(t0
, rt
);
8169 #endif /* !CONFIG_USER_ONLY */
8172 check_insn(env
, ctx
, ISA_MIPS32R2
);
8173 gen_load_srsgpr(rt
, rd
);
8176 check_insn(env
, ctx
, ISA_MIPS32R2
);
8177 gen_store_srsgpr(rt
, rd
);
8181 generate_exception(ctx
, EXCP_RI
);
8185 case OPC_ADDI
... OPC_LUI
: /* Arithmetic with immediate opcode */
8186 gen_arith_imm(env
, ctx
, op
, rt
, rs
, imm
);
8188 case OPC_J
... OPC_JAL
: /* Jump */
8189 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 2;
8190 gen_compute_branch(ctx
, op
, rs
, rt
, offset
);
8192 case OPC_BEQ
... OPC_BGTZ
: /* Branch */
8193 case OPC_BEQL
... OPC_BGTZL
:
8194 gen_compute_branch(ctx
, op
, rs
, rt
, imm
<< 2);
8196 case OPC_LB
... OPC_LWR
: /* Load and stores */
8197 case OPC_SB
... OPC_SW
:
8201 gen_ldst(ctx
, op
, rt
, rs
, imm
);
8204 check_insn(env
, ctx
, ISA_MIPS3
| ISA_MIPS32
);
8208 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
8212 /* Floating point (COP1). */
8217 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
8218 save_cpu_state(ctx
, 1);
8219 check_cp1_enabled(ctx
);
8220 gen_flt_ldst(ctx
, op
, rt
, rs
, imm
);
8222 generate_exception_err(ctx
, EXCP_CpU
, 1);
8227 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
8228 save_cpu_state(ctx
, 1);
8229 check_cp1_enabled(ctx
);
8230 op1
= MASK_CP1(ctx
->opcode
);
8234 check_insn(env
, ctx
, ISA_MIPS32R2
);
8239 gen_cp1(ctx
, op1
, rt
, rd
);
8241 #if defined(TARGET_MIPS64)
8244 check_insn(env
, ctx
, ISA_MIPS3
);
8245 gen_cp1(ctx
, op1
, rt
, rd
);
8251 check_insn(env
, ctx
, ASE_MIPS3D
);
8254 gen_compute_branch1(env
, ctx
, MASK_BC1(ctx
->opcode
),
8255 (rt
>> 2) & 0x7, imm
<< 2);
8262 gen_farith(ctx
, MASK_CP1_FUNC(ctx
->opcode
), rt
, rd
, sa
,
8267 generate_exception (ctx
, EXCP_RI
);
8271 generate_exception_err(ctx
, EXCP_CpU
, 1);
8281 /* COP2: Not implemented. */
8282 generate_exception_err(ctx
, EXCP_CpU
, 2);
8286 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
8287 save_cpu_state(ctx
, 1);
8288 check_cp1_enabled(ctx
);
8289 op1
= MASK_CP3(ctx
->opcode
);
8297 gen_flt3_ldst(ctx
, op1
, sa
, rd
, rs
, rt
);
8315 gen_flt3_arith(ctx
, op1
, sa
, rs
, rd
, rt
);
8319 generate_exception (ctx
, EXCP_RI
);
8323 generate_exception_err(ctx
, EXCP_CpU
, 1);
8327 #if defined(TARGET_MIPS64)
8328 /* MIPS64 opcodes */
8330 case OPC_LDL
... OPC_LDR
:
8331 case OPC_SDL
... OPC_SDR
:
8336 check_insn(env
, ctx
, ISA_MIPS3
);
8338 gen_ldst(ctx
, op
, rt
, rs
, imm
);
8340 case OPC_DADDI
... OPC_DADDIU
:
8341 check_insn(env
, ctx
, ISA_MIPS3
);
8343 gen_arith_imm(env
, ctx
, op
, rt
, rs
, imm
);
8347 check_insn(env
, ctx
, ASE_MIPS16
);
8348 /* MIPS16: Not implemented. */
8350 check_insn(env
, ctx
, ASE_MDMX
);
8351 /* MDMX: Not implemented. */
8352 default: /* Invalid */
8353 MIPS_INVAL("major opcode");
8354 generate_exception(ctx
, EXCP_RI
);
8357 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
8358 int hflags
= ctx
->hflags
& MIPS_HFLAG_BMASK
;
8359 /* Branches completion */
8360 ctx
->hflags
&= ~MIPS_HFLAG_BMASK
;
8361 ctx
->bstate
= BS_BRANCH
;
8362 save_cpu_state(ctx
, 0);
8363 /* FIXME: Need to clear can_do_io. */
8366 /* unconditional branch */
8367 MIPS_DEBUG("unconditional branch");
8368 gen_goto_tb(ctx
, 0, ctx
->btarget
);
8371 /* blikely taken case */
8372 MIPS_DEBUG("blikely branch taken");
8373 gen_goto_tb(ctx
, 0, ctx
->btarget
);
8376 /* Conditional branch */
8377 MIPS_DEBUG("conditional branch");
8379 int l1
= gen_new_label();
8381 tcg_gen_brcondi_i32(TCG_COND_NE
, bcond
, 0, l1
);
8382 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
8384 gen_goto_tb(ctx
, 0, ctx
->btarget
);
8388 /* unconditional branch to register */
8389 MIPS_DEBUG("branch to register");
8390 tcg_gen_mov_tl(cpu_PC
, btarget
);
8394 MIPS_DEBUG("unknown branch");
8401 gen_intermediate_code_internal (CPUState
*env
, TranslationBlock
*tb
,
8405 target_ulong pc_start
;
8406 uint16_t *gen_opc_end
;
8411 if (search_pc
&& loglevel
)
8412 fprintf (logfile
, "search pc %d\n", search_pc
);
8415 /* Leave some spare opc slots for branch handling. */
8416 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
- 16;
8420 ctx
.bstate
= BS_NONE
;
8421 /* Restore delay slot state from the tb context. */
8422 ctx
.hflags
= (uint32_t)tb
->flags
; /* FIXME: maybe use 64 bits here? */
8423 restore_cpu_state(env
, &ctx
);
8424 if (env
->user_mode_only
)
8425 ctx
.mem_idx
= MIPS_HFLAG_UM
;
8427 ctx
.mem_idx
= ctx
.hflags
& MIPS_HFLAG_KSU
;
8429 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
8431 max_insns
= CF_COUNT_MASK
;
8433 if (loglevel
& CPU_LOG_TB_CPU
) {
8434 fprintf(logfile
, "------------------------------------------------\n");
8435 /* FIXME: This may print out stale hflags from env... */
8436 cpu_dump_state(env
, logfile
, fprintf
, 0);
8439 #ifdef MIPS_DEBUG_DISAS
8440 if (loglevel
& CPU_LOG_TB_IN_ASM
)
8441 fprintf(logfile
, "\ntb %p idx %d hflags %04x\n",
8442 tb
, ctx
.mem_idx
, ctx
.hflags
);
8445 while (ctx
.bstate
== BS_NONE
) {
8446 if (env
->nb_breakpoints
> 0) {
8447 for(j
= 0; j
< env
->nb_breakpoints
; j
++) {
8448 if (env
->breakpoints
[j
] == ctx
.pc
) {
8449 save_cpu_state(&ctx
, 1);
8450 ctx
.bstate
= BS_BRANCH
;
8451 tcg_gen_helper_0_i(do_raise_exception
, EXCP_DEBUG
);
8452 /* Include the breakpoint location or the tb won't
8453 * be flushed when it must be. */
8455 goto done_generating
;
8461 j
= gen_opc_ptr
- gen_opc_buf
;
8465 gen_opc_instr_start
[lj
++] = 0;
8467 gen_opc_pc
[lj
] = ctx
.pc
;
8468 gen_opc_hflags
[lj
] = ctx
.hflags
& MIPS_HFLAG_BMASK
;
8469 gen_opc_instr_start
[lj
] = 1;
8470 gen_opc_icount
[lj
] = num_insns
;
8472 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
8474 ctx
.opcode
= ldl_code(ctx
.pc
);
8475 decode_opc(env
, &ctx
);
8479 if (env
->singlestep_enabled
)
8482 if ((ctx
.pc
& (TARGET_PAGE_SIZE
- 1)) == 0)
8485 if (gen_opc_ptr
>= gen_opc_end
)
8488 if (num_insns
>= max_insns
)
8490 #if defined (MIPS_SINGLE_STEP)
8494 if (tb
->cflags
& CF_LAST_IO
)
8496 if (env
->singlestep_enabled
) {
8497 save_cpu_state(&ctx
, ctx
.bstate
== BS_NONE
);
8498 tcg_gen_helper_0_i(do_raise_exception
, EXCP_DEBUG
);
8500 switch (ctx
.bstate
) {
8502 tcg_gen_helper_0_0(do_interrupt_restart
);
8503 gen_goto_tb(&ctx
, 0, ctx
.pc
);
8506 save_cpu_state(&ctx
, 0);
8507 gen_goto_tb(&ctx
, 0, ctx
.pc
);
8510 tcg_gen_helper_0_0(do_interrupt_restart
);
8519 gen_icount_end(tb
, num_insns
);
8520 *gen_opc_ptr
= INDEX_op_end
;
8522 j
= gen_opc_ptr
- gen_opc_buf
;
8525 gen_opc_instr_start
[lj
++] = 0;
8527 tb
->size
= ctx
.pc
- pc_start
;
8528 tb
->icount
= num_insns
;
8531 #if defined MIPS_DEBUG_DISAS
8532 if (loglevel
& CPU_LOG_TB_IN_ASM
)
8533 fprintf(logfile
, "\n");
8535 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
8536 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
8537 target_disas(logfile
, pc_start
, ctx
.pc
- pc_start
, 0);
8538 fprintf(logfile
, "\n");
8540 if (loglevel
& CPU_LOG_TB_CPU
) {
8541 fprintf(logfile
, "---------------- %d %08x\n", ctx
.bstate
, ctx
.hflags
);
8546 void gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
8548 gen_intermediate_code_internal(env
, tb
, 0);
8551 void gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
8553 gen_intermediate_code_internal(env
, tb
, 1);
8556 static void fpu_dump_state(CPUState
*env
, FILE *f
,
8557 int (*fpu_fprintf
)(FILE *f
, const char *fmt
, ...),
8561 int is_fpu64
= !!(env
->hflags
& MIPS_HFLAG_F64
);
8563 #define printfpr(fp) \
8566 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu: %13g\n", \
8567 (fp)->w[FP_ENDIAN_IDX], (fp)->d, (fp)->fd, \
8568 (fp)->fs[FP_ENDIAN_IDX], (fp)->fs[!FP_ENDIAN_IDX]); \
8571 tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \
8572 tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \
8573 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu:%13g\n", \
8574 tmp.w[FP_ENDIAN_IDX], tmp.d, tmp.fd, \
8575 tmp.fs[FP_ENDIAN_IDX], tmp.fs[!FP_ENDIAN_IDX]); \
8580 fpu_fprintf(f
, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n",
8581 env
->active_fpu
.fcr0
, env
->active_fpu
.fcr31
, is_fpu64
, env
->active_fpu
.fp_status
,
8582 get_float_exception_flags(&env
->active_fpu
.fp_status
));
8583 for (i
= 0; i
< 32; (is_fpu64
) ? i
++ : (i
+= 2)) {
8584 fpu_fprintf(f
, "%3s: ", fregnames
[i
]);
8585 printfpr(&env
->active_fpu
.fpr
[i
]);
8591 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
8592 /* Debug help: The architecture requires 32bit code to maintain proper
8593 sign-extended values on 64bit machines. */
8595 #define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff))
8598 cpu_mips_check_sign_extensions (CPUState
*env
, FILE *f
,
8599 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
8604 if (!SIGN_EXT_P(env
->active_tc
.PC
))
8605 cpu_fprintf(f
, "BROKEN: pc=0x" TARGET_FMT_lx
"\n", env
->active_tc
.PC
);
8606 if (!SIGN_EXT_P(env
->active_tc
.HI
[0]))
8607 cpu_fprintf(f
, "BROKEN: HI=0x" TARGET_FMT_lx
"\n", env
->active_tc
.HI
[0]);
8608 if (!SIGN_EXT_P(env
->active_tc
.LO
[0]))
8609 cpu_fprintf(f
, "BROKEN: LO=0x" TARGET_FMT_lx
"\n", env
->active_tc
.LO
[0]);
8610 if (!SIGN_EXT_P(env
->btarget
))
8611 cpu_fprintf(f
, "BROKEN: btarget=0x" TARGET_FMT_lx
"\n", env
->btarget
);
8613 for (i
= 0; i
< 32; i
++) {
8614 if (!SIGN_EXT_P(env
->active_tc
.gpr
[i
]))
8615 cpu_fprintf(f
, "BROKEN: %s=0x" TARGET_FMT_lx
"\n", regnames
[i
], env
->active_tc
.gpr
[i
]);
8618 if (!SIGN_EXT_P(env
->CP0_EPC
))
8619 cpu_fprintf(f
, "BROKEN: EPC=0x" TARGET_FMT_lx
"\n", env
->CP0_EPC
);
8620 if (!SIGN_EXT_P(env
->CP0_LLAddr
))
8621 cpu_fprintf(f
, "BROKEN: LLAddr=0x" TARGET_FMT_lx
"\n", env
->CP0_LLAddr
);
8625 void cpu_dump_state (CPUState
*env
, FILE *f
,
8626 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
8631 cpu_fprintf(f
, "pc=0x" TARGET_FMT_lx
" HI=0x" TARGET_FMT_lx
" LO=0x" TARGET_FMT_lx
" ds %04x " TARGET_FMT_lx
" %d\n",
8632 env
->active_tc
.PC
, env
->active_tc
.HI
[0], env
->active_tc
.LO
[0],
8633 env
->hflags
, env
->btarget
, env
->bcond
);
8634 for (i
= 0; i
< 32; i
++) {
8636 cpu_fprintf(f
, "GPR%02d:", i
);
8637 cpu_fprintf(f
, " %s " TARGET_FMT_lx
, regnames
[i
], env
->active_tc
.gpr
[i
]);
8639 cpu_fprintf(f
, "\n");
8642 cpu_fprintf(f
, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx
"\n",
8643 env
->CP0_Status
, env
->CP0_Cause
, env
->CP0_EPC
);
8644 cpu_fprintf(f
, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx
"\n",
8645 env
->CP0_Config0
, env
->CP0_Config1
, env
->CP0_LLAddr
);
8646 if (env
->hflags
& MIPS_HFLAG_FPU
)
8647 fpu_dump_state(env
, f
, cpu_fprintf
, flags
);
8648 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
8649 cpu_mips_check_sign_extensions(env
, f
, cpu_fprintf
, flags
);
8653 static void mips_tcg_init(void)
8658 /* Initialize various static tables. */
8662 cpu_env
= tcg_global_reg_new(TCG_TYPE_PTR
, TCG_AREG0
, "env");
8663 for (i
= 0; i
< 32; i
++)
8664 cpu_gpr
[i
] = tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
8665 offsetof(CPUState
, active_tc
.gpr
[i
]),
8667 cpu_PC
= tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
8668 offsetof(CPUState
, active_tc
.PC
), "PC");
8669 for (i
= 0; i
< MIPS_DSP_ACC
; i
++) {
8670 cpu_HI
[i
] = tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
8671 offsetof(CPUState
, active_tc
.HI
[i
]),
8673 cpu_LO
[i
] = tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
8674 offsetof(CPUState
, active_tc
.LO
[i
]),
8676 cpu_ACX
[i
] = tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
8677 offsetof(CPUState
, active_tc
.ACX
[i
]),
8680 cpu_dspctrl
= tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
8681 offsetof(CPUState
, active_tc
.DSPControl
),
8683 bcond
= tcg_global_mem_new(TCG_TYPE_I32
, TCG_AREG0
,
8684 offsetof(CPUState
, bcond
), "bcond");
8685 btarget
= tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
8686 offsetof(CPUState
, btarget
), "btarget");
8687 for (i
= 0; i
< 32; i
++)
8688 fpu_fpr32
[i
] = tcg_global_mem_new(TCG_TYPE_I32
, TCG_AREG0
,
8689 offsetof(CPUState
, active_fpu
.fpr
[i
].w
[FP_ENDIAN_IDX
]),
8691 for (i
= 0; i
< 32; i
++)
8692 fpu_fpr64
[i
] = tcg_global_mem_new(TCG_TYPE_I64
, TCG_AREG0
,
8693 offsetof(CPUState
, active_fpu
.fpr
[i
]),
8695 for (i
= 0; i
< 32; i
++)
8696 fpu_fpr32h
[i
] = tcg_global_mem_new(TCG_TYPE_I32
, TCG_AREG0
,
8697 offsetof(CPUState
, active_fpu
.fpr
[i
].w
[!FP_ENDIAN_IDX
]),
8699 fpu_fcr0
= tcg_global_mem_new(TCG_TYPE_I32
, TCG_AREG0
,
8700 offsetof(CPUState
, active_fpu
.fcr0
),
8702 fpu_fcr31
= tcg_global_mem_new(TCG_TYPE_I32
, TCG_AREG0
,
8703 offsetof(CPUState
, active_fpu
.fcr31
),
8706 /* register helpers */
8708 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
8714 #include "translate_init.c"
8716 CPUMIPSState
*cpu_mips_init (const char *cpu_model
)
8719 const mips_def_t
*def
;
8721 def
= cpu_mips_find_by_name(cpu_model
);
8724 env
= qemu_mallocz(sizeof(CPUMIPSState
));
8727 env
->cpu_model
= def
;
8730 env
->cpu_model_str
= cpu_model
;
8736 void cpu_reset (CPUMIPSState
*env
)
8738 memset(env
, 0, offsetof(CPUMIPSState
, breakpoints
));
8743 #if defined(CONFIG_USER_ONLY)
8744 env
->user_mode_only
= 1;
8746 if (env
->user_mode_only
) {
8747 env
->hflags
= MIPS_HFLAG_UM
;
8749 if (env
->hflags
& MIPS_HFLAG_BMASK
) {
8750 /* If the exception was raised from a delay slot,
8751 come back to the jump. */
8752 env
->CP0_ErrorEPC
= env
->active_tc
.PC
- 4;
8754 env
->CP0_ErrorEPC
= env
->active_tc
.PC
;
8756 env
->active_tc
.PC
= (int32_t)0xBFC00000;
8758 /* SMP not implemented */
8759 env
->CP0_EBase
= 0x80000000;
8760 env
->CP0_Status
= (1 << CP0St_BEV
) | (1 << CP0St_ERL
);
8761 /* vectored interrupts not implemented, timer on int 7,
8762 no performance counters. */
8763 env
->CP0_IntCtl
= 0xe0000000;
8767 for (i
= 0; i
< 7; i
++) {
8768 env
->CP0_WatchLo
[i
] = 0;
8769 env
->CP0_WatchHi
[i
] = 0x80000000;
8771 env
->CP0_WatchLo
[7] = 0;
8772 env
->CP0_WatchHi
[7] = 0;
8774 /* Count register increments in debug mode, EJTAG version 1 */
8775 env
->CP0_Debug
= (1 << CP0DB_CNT
) | (0x1 << CP0DB_VER
);
8776 env
->hflags
= MIPS_HFLAG_CP0
;
8778 env
->exception_index
= EXCP_NONE
;
8779 cpu_mips_register(env
, env
->cpu_model
);
8782 void gen_pc_load(CPUState
*env
, TranslationBlock
*tb
,
8783 unsigned long searched_pc
, int pc_pos
, void *puc
)
8785 env
->active_tc
.PC
= gen_opc_pc
[pc_pos
];
8786 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
8787 env
->hflags
|= gen_opc_hflags
[pc_pos
];