2 * MIPS32 emulation for qemu: main translation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 //#define MIPS_DEBUG_DISAS
34 //#define MIPS_DEBUG_SIGN_EXTENSIONS
35 //#define MIPS_SINGLE_STEP
37 #ifdef USE_DIRECT_JUMP
40 #define TBPARAM(x) (long)(x)
44 #define DEF(s, n, copy_size) INDEX_op_ ## s,
50 static uint16_t *gen_opc_ptr
;
51 static uint32_t *gen_opparam_ptr
;
55 /* MIPS major opcodes */
56 #define MASK_OP_MAJOR(op) (op & (0x3F << 26))
59 /* indirect opcode tables */
60 OPC_SPECIAL
= (0x00 << 26),
61 OPC_REGIMM
= (0x01 << 26),
62 OPC_CP0
= (0x10 << 26),
63 OPC_CP1
= (0x11 << 26),
64 OPC_CP2
= (0x12 << 26),
65 OPC_CP3
= (0x13 << 26),
66 OPC_SPECIAL2
= (0x1C << 26),
67 OPC_SPECIAL3
= (0x1F << 26),
68 /* arithmetic with immediate */
69 OPC_ADDI
= (0x08 << 26),
70 OPC_ADDIU
= (0x09 << 26),
71 OPC_SLTI
= (0x0A << 26),
72 OPC_SLTIU
= (0x0B << 26),
73 OPC_ANDI
= (0x0C << 26),
74 OPC_ORI
= (0x0D << 26),
75 OPC_XORI
= (0x0E << 26),
76 OPC_LUI
= (0x0F << 26),
77 OPC_DADDI
= (0x18 << 26),
78 OPC_DADDIU
= (0x19 << 26),
79 /* Jump and branches */
81 OPC_JAL
= (0x03 << 26),
82 OPC_BEQ
= (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
83 OPC_BEQL
= (0x14 << 26),
84 OPC_BNE
= (0x05 << 26),
85 OPC_BNEL
= (0x15 << 26),
86 OPC_BLEZ
= (0x06 << 26),
87 OPC_BLEZL
= (0x16 << 26),
88 OPC_BGTZ
= (0x07 << 26),
89 OPC_BGTZL
= (0x17 << 26),
90 OPC_JALX
= (0x1D << 26), /* MIPS 16 only */
92 OPC_LDL
= (0x1A << 26),
93 OPC_LDR
= (0x1B << 26),
94 OPC_LB
= (0x20 << 26),
95 OPC_LH
= (0x21 << 26),
96 OPC_LWL
= (0x22 << 26),
97 OPC_LW
= (0x23 << 26),
98 OPC_LBU
= (0x24 << 26),
99 OPC_LHU
= (0x25 << 26),
100 OPC_LWR
= (0x26 << 26),
101 OPC_LWU
= (0x27 << 26),
102 OPC_SB
= (0x28 << 26),
103 OPC_SH
= (0x29 << 26),
104 OPC_SWL
= (0x2A << 26),
105 OPC_SW
= (0x2B << 26),
106 OPC_SDL
= (0x2C << 26),
107 OPC_SDR
= (0x2D << 26),
108 OPC_SWR
= (0x2E << 26),
109 OPC_LL
= (0x30 << 26),
110 OPC_LLD
= (0x34 << 26),
111 OPC_LD
= (0x37 << 26),
112 OPC_SC
= (0x38 << 26),
113 OPC_SCD
= (0x3C << 26),
114 OPC_SD
= (0x3F << 26),
115 /* Floating point load/store */
116 OPC_LWC1
= (0x31 << 26),
117 OPC_LWC2
= (0x32 << 26),
118 OPC_LDC1
= (0x35 << 26),
119 OPC_LDC2
= (0x36 << 26),
120 OPC_SWC1
= (0x39 << 26),
121 OPC_SWC2
= (0x3A << 26),
122 OPC_SDC1
= (0x3D << 26),
123 OPC_SDC2
= (0x3E << 26),
124 /* MDMX ASE specific */
125 OPC_MDMX
= (0x1E << 26),
126 /* Cache and prefetch */
127 OPC_CACHE
= (0x2F << 26),
128 OPC_PREF
= (0x33 << 26),
129 /* Reserved major opcode */
130 OPC_MAJOR3B_RESERVED
= (0x3B << 26),
133 /* MIPS special opcodes */
134 #define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F)
138 OPC_SLL
= 0x00 | OPC_SPECIAL
,
139 /* NOP is SLL r0, r0, 0 */
140 /* SSNOP is SLL r0, r0, 1 */
141 /* EHB is SLL r0, r0, 3 */
142 OPC_SRL
= 0x02 | OPC_SPECIAL
, /* also ROTR */
143 OPC_SRA
= 0x03 | OPC_SPECIAL
,
144 OPC_SLLV
= 0x04 | OPC_SPECIAL
,
145 OPC_SRLV
= 0x06 | OPC_SPECIAL
,
146 OPC_SRAV
= 0x07 | OPC_SPECIAL
,
147 OPC_DSLLV
= 0x14 | OPC_SPECIAL
,
148 OPC_DSRLV
= 0x16 | OPC_SPECIAL
, /* also DROTRV */
149 OPC_DSRAV
= 0x17 | OPC_SPECIAL
,
150 OPC_DSLL
= 0x38 | OPC_SPECIAL
,
151 OPC_DSRL
= 0x3A | OPC_SPECIAL
, /* also DROTR */
152 OPC_DSRA
= 0x3B | OPC_SPECIAL
,
153 OPC_DSLL32
= 0x3C | OPC_SPECIAL
,
154 OPC_DSRL32
= 0x3E | OPC_SPECIAL
, /* also DROTR32 */
155 OPC_DSRA32
= 0x3F | OPC_SPECIAL
,
156 /* Multiplication / division */
157 OPC_MULT
= 0x18 | OPC_SPECIAL
,
158 OPC_MULTU
= 0x19 | OPC_SPECIAL
,
159 OPC_DIV
= 0x1A | OPC_SPECIAL
,
160 OPC_DIVU
= 0x1B | OPC_SPECIAL
,
161 OPC_DMULT
= 0x1C | OPC_SPECIAL
,
162 OPC_DMULTU
= 0x1D | OPC_SPECIAL
,
163 OPC_DDIV
= 0x1E | OPC_SPECIAL
,
164 OPC_DDIVU
= 0x1F | OPC_SPECIAL
,
165 /* 2 registers arithmetic / logic */
166 OPC_ADD
= 0x20 | OPC_SPECIAL
,
167 OPC_ADDU
= 0x21 | OPC_SPECIAL
,
168 OPC_SUB
= 0x22 | OPC_SPECIAL
,
169 OPC_SUBU
= 0x23 | OPC_SPECIAL
,
170 OPC_AND
= 0x24 | OPC_SPECIAL
,
171 OPC_OR
= 0x25 | OPC_SPECIAL
,
172 OPC_XOR
= 0x26 | OPC_SPECIAL
,
173 OPC_NOR
= 0x27 | OPC_SPECIAL
,
174 OPC_SLT
= 0x2A | OPC_SPECIAL
,
175 OPC_SLTU
= 0x2B | OPC_SPECIAL
,
176 OPC_DADD
= 0x2C | OPC_SPECIAL
,
177 OPC_DADDU
= 0x2D | OPC_SPECIAL
,
178 OPC_DSUB
= 0x2E | OPC_SPECIAL
,
179 OPC_DSUBU
= 0x2F | OPC_SPECIAL
,
181 OPC_JR
= 0x08 | OPC_SPECIAL
, /* Also JR.HB */
182 OPC_JALR
= 0x09 | OPC_SPECIAL
, /* Also JALR.HB */
184 OPC_TGE
= 0x30 | OPC_SPECIAL
,
185 OPC_TGEU
= 0x31 | OPC_SPECIAL
,
186 OPC_TLT
= 0x32 | OPC_SPECIAL
,
187 OPC_TLTU
= 0x33 | OPC_SPECIAL
,
188 OPC_TEQ
= 0x34 | OPC_SPECIAL
,
189 OPC_TNE
= 0x36 | OPC_SPECIAL
,
190 /* HI / LO registers load & stores */
191 OPC_MFHI
= 0x10 | OPC_SPECIAL
,
192 OPC_MTHI
= 0x11 | OPC_SPECIAL
,
193 OPC_MFLO
= 0x12 | OPC_SPECIAL
,
194 OPC_MTLO
= 0x13 | OPC_SPECIAL
,
195 /* Conditional moves */
196 OPC_MOVZ
= 0x0A | OPC_SPECIAL
,
197 OPC_MOVN
= 0x0B | OPC_SPECIAL
,
199 OPC_MOVCI
= 0x01 | OPC_SPECIAL
,
202 OPC_PMON
= 0x05 | OPC_SPECIAL
, /* inofficial */
203 OPC_SYSCALL
= 0x0C | OPC_SPECIAL
,
204 OPC_BREAK
= 0x0D | OPC_SPECIAL
,
205 OPC_SPIM
= 0x0E | OPC_SPECIAL
, /* inofficial */
206 OPC_SYNC
= 0x0F | OPC_SPECIAL
,
208 OPC_SPECIAL15_RESERVED
= 0x15 | OPC_SPECIAL
,
209 OPC_SPECIAL28_RESERVED
= 0x28 | OPC_SPECIAL
,
210 OPC_SPECIAL29_RESERVED
= 0x29 | OPC_SPECIAL
,
211 OPC_SPECIAL35_RESERVED
= 0x35 | OPC_SPECIAL
,
212 OPC_SPECIAL37_RESERVED
= 0x37 | OPC_SPECIAL
,
213 OPC_SPECIAL39_RESERVED
= 0x39 | OPC_SPECIAL
,
214 OPC_SPECIAL3D_RESERVED
= 0x3D | OPC_SPECIAL
,
217 /* REGIMM (rt field) opcodes */
218 #define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
221 OPC_BLTZ
= (0x00 << 16) | OPC_REGIMM
,
222 OPC_BLTZL
= (0x02 << 16) | OPC_REGIMM
,
223 OPC_BGEZ
= (0x01 << 16) | OPC_REGIMM
,
224 OPC_BGEZL
= (0x03 << 16) | OPC_REGIMM
,
225 OPC_BLTZAL
= (0x10 << 16) | OPC_REGIMM
,
226 OPC_BLTZALL
= (0x12 << 16) | OPC_REGIMM
,
227 OPC_BGEZAL
= (0x11 << 16) | OPC_REGIMM
,
228 OPC_BGEZALL
= (0x13 << 16) | OPC_REGIMM
,
229 OPC_TGEI
= (0x08 << 16) | OPC_REGIMM
,
230 OPC_TGEIU
= (0x09 << 16) | OPC_REGIMM
,
231 OPC_TLTI
= (0x0A << 16) | OPC_REGIMM
,
232 OPC_TLTIU
= (0x0B << 16) | OPC_REGIMM
,
233 OPC_TEQI
= (0x0C << 16) | OPC_REGIMM
,
234 OPC_TNEI
= (0x0E << 16) | OPC_REGIMM
,
235 OPC_SYNCI
= (0x1F << 16) | OPC_REGIMM
,
238 /* Special2 opcodes */
239 #define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F)
242 /* Multiply & xxx operations */
243 OPC_MADD
= 0x00 | OPC_SPECIAL2
,
244 OPC_MADDU
= 0x01 | OPC_SPECIAL2
,
245 OPC_MUL
= 0x02 | OPC_SPECIAL2
,
246 OPC_MSUB
= 0x04 | OPC_SPECIAL2
,
247 OPC_MSUBU
= 0x05 | OPC_SPECIAL2
,
249 OPC_CLZ
= 0x20 | OPC_SPECIAL2
,
250 OPC_CLO
= 0x21 | OPC_SPECIAL2
,
251 OPC_DCLZ
= 0x24 | OPC_SPECIAL2
,
252 OPC_DCLO
= 0x25 | OPC_SPECIAL2
,
254 OPC_SDBBP
= 0x3F | OPC_SPECIAL2
,
257 /* Special3 opcodes */
258 #define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
261 OPC_EXT
= 0x00 | OPC_SPECIAL3
,
262 OPC_DEXTM
= 0x01 | OPC_SPECIAL3
,
263 OPC_DEXTU
= 0x02 | OPC_SPECIAL3
,
264 OPC_DEXT
= 0x03 | OPC_SPECIAL3
,
265 OPC_INS
= 0x04 | OPC_SPECIAL3
,
266 OPC_DINSM
= 0x05 | OPC_SPECIAL3
,
267 OPC_DINSU
= 0x06 | OPC_SPECIAL3
,
268 OPC_DINS
= 0x07 | OPC_SPECIAL3
,
269 OPC_FORK
= 0x08 | OPC_SPECIAL3
,
270 OPC_YIELD
= 0x09 | OPC_SPECIAL3
,
271 OPC_BSHFL
= 0x20 | OPC_SPECIAL3
,
272 OPC_DBSHFL
= 0x24 | OPC_SPECIAL3
,
273 OPC_RDHWR
= 0x3B | OPC_SPECIAL3
,
277 #define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
280 OPC_WSBH
= (0x02 << 6) | OPC_BSHFL
,
281 OPC_SEB
= (0x10 << 6) | OPC_BSHFL
,
282 OPC_SEH
= (0x18 << 6) | OPC_BSHFL
,
286 #define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
289 OPC_DSBH
= (0x02 << 6) | OPC_DBSHFL
,
290 OPC_DSHD
= (0x05 << 6) | OPC_DBSHFL
,
293 /* Coprocessor 0 (rs field) */
294 #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
297 OPC_MFC0
= (0x00 << 21) | OPC_CP0
,
298 OPC_DMFC0
= (0x01 << 21) | OPC_CP0
,
299 OPC_MTC0
= (0x04 << 21) | OPC_CP0
,
300 OPC_DMTC0
= (0x05 << 21) | OPC_CP0
,
301 OPC_MFTR
= (0x08 << 21) | OPC_CP0
,
302 OPC_RDPGPR
= (0x0A << 21) | OPC_CP0
,
303 OPC_MFMC0
= (0x0B << 21) | OPC_CP0
,
304 OPC_MTTR
= (0x0C << 21) | OPC_CP0
,
305 OPC_WRPGPR
= (0x0E << 21) | OPC_CP0
,
306 OPC_C0
= (0x10 << 21) | OPC_CP0
,
307 OPC_C0_FIRST
= (0x10 << 21) | OPC_CP0
,
308 OPC_C0_LAST
= (0x1F << 21) | OPC_CP0
,
312 #define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
315 OPC_DMT
= 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
316 OPC_EMT
= 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
317 OPC_DVPE
= 0x01 | (0 << 5) | OPC_MFMC0
,
318 OPC_EVPE
= 0x01 | (1 << 5) | OPC_MFMC0
,
319 OPC_DI
= (0 << 5) | (0x0C << 11) | OPC_MFMC0
,
320 OPC_EI
= (1 << 5) | (0x0C << 11) | OPC_MFMC0
,
323 /* Coprocessor 0 (with rs == C0) */
324 #define MASK_C0(op) MASK_CP0(op) | (op & 0x3F)
327 OPC_TLBR
= 0x01 | OPC_C0
,
328 OPC_TLBWI
= 0x02 | OPC_C0
,
329 OPC_TLBWR
= 0x06 | OPC_C0
,
330 OPC_TLBP
= 0x08 | OPC_C0
,
331 OPC_RFE
= 0x10 | OPC_C0
,
332 OPC_ERET
= 0x18 | OPC_C0
,
333 OPC_DERET
= 0x1F | OPC_C0
,
334 OPC_WAIT
= 0x20 | OPC_C0
,
337 /* Coprocessor 1 (rs field) */
338 #define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
341 OPC_MFC1
= (0x00 << 21) | OPC_CP1
,
342 OPC_DMFC1
= (0x01 << 21) | OPC_CP1
,
343 OPC_CFC1
= (0x02 << 21) | OPC_CP1
,
344 OPC_MFHC1
= (0x03 << 21) | OPC_CP1
,
345 OPC_MTC1
= (0x04 << 21) | OPC_CP1
,
346 OPC_DMTC1
= (0x05 << 21) | OPC_CP1
,
347 OPC_CTC1
= (0x06 << 21) | OPC_CP1
,
348 OPC_MTHC1
= (0x07 << 21) | OPC_CP1
,
349 OPC_BC1
= (0x08 << 21) | OPC_CP1
, /* bc */
350 OPC_BC1ANY2
= (0x09 << 21) | OPC_CP1
,
351 OPC_BC1ANY4
= (0x0A << 21) | OPC_CP1
,
352 OPC_S_FMT
= (0x10 << 21) | OPC_CP1
, /* 16: fmt=single fp */
353 OPC_D_FMT
= (0x11 << 21) | OPC_CP1
, /* 17: fmt=double fp */
354 OPC_E_FMT
= (0x12 << 21) | OPC_CP1
, /* 18: fmt=extended fp */
355 OPC_Q_FMT
= (0x13 << 21) | OPC_CP1
, /* 19: fmt=quad fp */
356 OPC_W_FMT
= (0x14 << 21) | OPC_CP1
, /* 20: fmt=32bit fixed */
357 OPC_L_FMT
= (0x15 << 21) | OPC_CP1
, /* 21: fmt=64bit fixed */
358 OPC_PS_FMT
= (0x16 << 21) | OPC_CP1
, /* 22: fmt=paired single fp */
361 #define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
362 #define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16))
365 OPC_BC1F
= (0x00 << 16) | OPC_BC1
,
366 OPC_BC1T
= (0x01 << 16) | OPC_BC1
,
367 OPC_BC1FL
= (0x02 << 16) | OPC_BC1
,
368 OPC_BC1TL
= (0x03 << 16) | OPC_BC1
,
372 OPC_BC1FANY2
= (0x00 << 16) | OPC_BC1ANY2
,
373 OPC_BC1TANY2
= (0x01 << 16) | OPC_BC1ANY2
,
377 OPC_BC1FANY4
= (0x00 << 16) | OPC_BC1ANY4
,
378 OPC_BC1TANY4
= (0x01 << 16) | OPC_BC1ANY4
,
381 #define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
384 OPC_MFC2
= (0x00 << 21) | OPC_CP2
,
385 OPC_DMFC2
= (0x01 << 21) | OPC_CP2
,
386 OPC_CFC2
= (0x02 << 21) | OPC_CP2
,
387 OPC_MFHC2
= (0x03 << 21) | OPC_CP2
,
388 OPC_MTC2
= (0x04 << 21) | OPC_CP2
,
389 OPC_DMTC2
= (0x05 << 21) | OPC_CP2
,
390 OPC_CTC2
= (0x06 << 21) | OPC_CP2
,
391 OPC_MTHC2
= (0x07 << 21) | OPC_CP2
,
392 OPC_BC2
= (0x08 << 21) | OPC_CP2
,
395 #define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
398 OPC_LWXC1
= 0x00 | OPC_CP3
,
399 OPC_LDXC1
= 0x01 | OPC_CP3
,
400 OPC_LUXC1
= 0x05 | OPC_CP3
,
401 OPC_SWXC1
= 0x08 | OPC_CP3
,
402 OPC_SDXC1
= 0x09 | OPC_CP3
,
403 OPC_SUXC1
= 0x0D | OPC_CP3
,
404 OPC_PREFX
= 0x0F | OPC_CP3
,
405 OPC_ALNV_PS
= 0x1E | OPC_CP3
,
406 OPC_MADD_S
= 0x20 | OPC_CP3
,
407 OPC_MADD_D
= 0x21 | OPC_CP3
,
408 OPC_MADD_PS
= 0x26 | OPC_CP3
,
409 OPC_MSUB_S
= 0x28 | OPC_CP3
,
410 OPC_MSUB_D
= 0x29 | OPC_CP3
,
411 OPC_MSUB_PS
= 0x2E | OPC_CP3
,
412 OPC_NMADD_S
= 0x30 | OPC_CP3
,
413 OPC_NMADD_D
= 0x31 | OPC_CP3
,
414 OPC_NMADD_PS
= 0x36 | OPC_CP3
,
415 OPC_NMSUB_S
= 0x38 | OPC_CP3
,
416 OPC_NMSUB_D
= 0x39 | OPC_CP3
,
417 OPC_NMSUB_PS
= 0x3E | OPC_CP3
,
421 const unsigned char *regnames
[] =
422 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
423 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
424 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
425 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
427 /* Warning: no function for r0 register (hard wired to zero) */
428 #define GEN32(func, NAME) \
429 static GenOpFunc *NAME ## _table [32] = { \
430 NULL, NAME ## 1, NAME ## 2, NAME ## 3, \
431 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
432 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
433 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
434 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
435 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
436 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
437 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
439 static inline void func(int n) \
441 NAME ## _table[n](); \
444 /* General purpose registers moves */
445 GEN32(gen_op_load_gpr_T0
, gen_op_load_gpr_T0_gpr
);
446 GEN32(gen_op_load_gpr_T1
, gen_op_load_gpr_T1_gpr
);
447 GEN32(gen_op_load_gpr_T2
, gen_op_load_gpr_T2_gpr
);
449 GEN32(gen_op_store_T0_gpr
, gen_op_store_T0_gpr_gpr
);
450 GEN32(gen_op_store_T1_gpr
, gen_op_store_T1_gpr_gpr
);
452 /* Moves to/from shadow registers */
453 GEN32(gen_op_load_srsgpr_T0
, gen_op_load_srsgpr_T0_gpr
);
454 GEN32(gen_op_store_T0_srsgpr
, gen_op_store_T0_srsgpr_gpr
);
456 static const char *fregnames
[] =
457 { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
458 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
459 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
460 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
462 #define FGEN32(func, NAME) \
463 static GenOpFunc *NAME ## _table [32] = { \
464 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
465 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
466 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
467 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
468 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
469 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
470 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
471 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
473 static inline void func(int n) \
475 NAME ## _table[n](); \
478 FGEN32(gen_op_load_fpr_WT0
, gen_op_load_fpr_WT0_fpr
);
479 FGEN32(gen_op_store_fpr_WT0
, gen_op_store_fpr_WT0_fpr
);
481 FGEN32(gen_op_load_fpr_WT1
, gen_op_load_fpr_WT1_fpr
);
482 FGEN32(gen_op_store_fpr_WT1
, gen_op_store_fpr_WT1_fpr
);
484 FGEN32(gen_op_load_fpr_WT2
, gen_op_load_fpr_WT2_fpr
);
485 FGEN32(gen_op_store_fpr_WT2
, gen_op_store_fpr_WT2_fpr
);
487 FGEN32(gen_op_load_fpr_DT0
, gen_op_load_fpr_DT0_fpr
);
488 FGEN32(gen_op_store_fpr_DT0
, gen_op_store_fpr_DT0_fpr
);
490 FGEN32(gen_op_load_fpr_DT1
, gen_op_load_fpr_DT1_fpr
);
491 FGEN32(gen_op_store_fpr_DT1
, gen_op_store_fpr_DT1_fpr
);
493 FGEN32(gen_op_load_fpr_DT2
, gen_op_load_fpr_DT2_fpr
);
494 FGEN32(gen_op_store_fpr_DT2
, gen_op_store_fpr_DT2_fpr
);
496 FGEN32(gen_op_load_fpr_WTH0
, gen_op_load_fpr_WTH0_fpr
);
497 FGEN32(gen_op_store_fpr_WTH0
, gen_op_store_fpr_WTH0_fpr
);
499 FGEN32(gen_op_load_fpr_WTH1
, gen_op_load_fpr_WTH1_fpr
);
500 FGEN32(gen_op_store_fpr_WTH1
, gen_op_store_fpr_WTH1_fpr
);
502 FGEN32(gen_op_load_fpr_WTH2
, gen_op_load_fpr_WTH2_fpr
);
503 FGEN32(gen_op_store_fpr_WTH2
, gen_op_store_fpr_WTH2_fpr
);
505 #define FOP_CONDS(type, fmt) \
506 static GenOpFunc1 * gen_op_cmp ## type ## _ ## fmt ## _table[16] = { \
507 gen_op_cmp ## type ## _ ## fmt ## _f, \
508 gen_op_cmp ## type ## _ ## fmt ## _un, \
509 gen_op_cmp ## type ## _ ## fmt ## _eq, \
510 gen_op_cmp ## type ## _ ## fmt ## _ueq, \
511 gen_op_cmp ## type ## _ ## fmt ## _olt, \
512 gen_op_cmp ## type ## _ ## fmt ## _ult, \
513 gen_op_cmp ## type ## _ ## fmt ## _ole, \
514 gen_op_cmp ## type ## _ ## fmt ## _ule, \
515 gen_op_cmp ## type ## _ ## fmt ## _sf, \
516 gen_op_cmp ## type ## _ ## fmt ## _ngle, \
517 gen_op_cmp ## type ## _ ## fmt ## _seq, \
518 gen_op_cmp ## type ## _ ## fmt ## _ngl, \
519 gen_op_cmp ## type ## _ ## fmt ## _lt, \
520 gen_op_cmp ## type ## _ ## fmt ## _nge, \
521 gen_op_cmp ## type ## _ ## fmt ## _le, \
522 gen_op_cmp ## type ## _ ## fmt ## _ngt, \
524 static inline void gen_cmp ## type ## _ ## fmt(int n, long cc) \
526 gen_op_cmp ## type ## _ ## fmt ## _table[n](cc); \
536 typedef struct DisasContext
{
537 struct TranslationBlock
*tb
;
538 target_ulong pc
, saved_pc
;
541 /* Routine used to access memory */
543 uint32_t hflags
, saved_hflags
;
545 target_ulong btarget
;
549 BS_NONE
= 0, /* We go out of the TB without reaching a branch or an
550 * exception condition
552 BS_STOP
= 1, /* We want to stop translation for any reason */
553 BS_BRANCH
= 2, /* We reached a branch condition */
554 BS_EXCP
= 3, /* We reached an exception condition */
557 #ifdef MIPS_DEBUG_DISAS
558 #define MIPS_DEBUG(fmt, args...) \
560 if (loglevel & CPU_LOG_TB_IN_ASM) { \
561 fprintf(logfile, TARGET_FMT_lx ": %08x " fmt "\n", \
562 ctx->pc, ctx->opcode , ##args); \
566 #define MIPS_DEBUG(fmt, args...) do { } while(0)
569 #define MIPS_INVAL(op) \
571 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
572 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
575 #define GEN_LOAD_REG_TN(Tn, Rn) \
578 glue(gen_op_reset_, Tn)(); \
580 glue(gen_op_load_gpr_, Tn)(Rn); \
584 #define GEN_LOAD_SRSREG_TN(Tn, Rn) \
587 glue(gen_op_reset_, Tn)(); \
589 glue(gen_op_load_srsgpr_, Tn)(Rn); \
594 #define GEN_LOAD_IMM_TN(Tn, Imm) \
597 glue(gen_op_reset_, Tn)(); \
598 } else if ((int32_t)Imm == Imm) { \
599 glue(gen_op_set_, Tn)(Imm); \
601 glue(gen_op_set64_, Tn)(((uint64_t)Imm) >> 32, (uint32_t)Imm); \
605 #define GEN_LOAD_IMM_TN(Tn, Imm) \
608 glue(gen_op_reset_, Tn)(); \
610 glue(gen_op_set_, Tn)(Imm); \
615 #define GEN_STORE_TN_REG(Rn, Tn) \
618 glue(glue(gen_op_store_, Tn),_gpr)(Rn); \
622 #define GEN_STORE_TN_SRSREG(Rn, Tn) \
625 glue(glue(gen_op_store_, Tn),_srsgpr)(Rn); \
629 #define GEN_LOAD_FREG_FTN(FTn, Fn) \
631 glue(gen_op_load_fpr_, FTn)(Fn); \
634 #define GEN_STORE_FTN_FREG(Fn, FTn) \
636 glue(gen_op_store_fpr_, FTn)(Fn); \
639 static inline void gen_save_pc(target_ulong pc
)
642 if (pc
== (int32_t)pc
) {
645 gen_op_save_pc64(pc
>> 32, (uint32_t)pc
);
652 static inline void gen_save_btarget(target_ulong btarget
)
655 if (btarget
== (int32_t)btarget
) {
656 gen_op_save_btarget(btarget
);
658 gen_op_save_btarget64(btarget
>> 32, (uint32_t)btarget
);
661 gen_op_save_btarget(btarget
);
665 static inline void save_cpu_state (DisasContext
*ctx
, int do_save_pc
)
667 #if defined MIPS_DEBUG_DISAS
668 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
669 fprintf(logfile
, "hflags %08x saved %08x\n",
670 ctx
->hflags
, ctx
->saved_hflags
);
673 if (do_save_pc
&& ctx
->pc
!= ctx
->saved_pc
) {
674 gen_save_pc(ctx
->pc
);
675 ctx
->saved_pc
= ctx
->pc
;
677 if (ctx
->hflags
!= ctx
->saved_hflags
) {
678 gen_op_save_state(ctx
->hflags
);
679 ctx
->saved_hflags
= ctx
->hflags
;
680 switch (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
682 gen_op_save_breg_target();
688 /* bcond was already saved by the BL insn */
691 gen_save_btarget(ctx
->btarget
);
697 static inline void restore_cpu_state (CPUState
*env
, DisasContext
*ctx
)
699 ctx
->saved_hflags
= ctx
->hflags
;
700 switch (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
702 gen_op_restore_breg_target();
705 ctx
->btarget
= env
->btarget
;
709 ctx
->btarget
= env
->btarget
;
710 gen_op_restore_bcond();
715 static inline void generate_exception_err (DisasContext
*ctx
, int excp
, int err
)
717 #if defined MIPS_DEBUG_DISAS
718 if (loglevel
& CPU_LOG_TB_IN_ASM
)
719 fprintf(logfile
, "%s: raise exception %d\n", __func__
, excp
);
721 save_cpu_state(ctx
, 1);
723 gen_op_raise_exception(excp
);
725 gen_op_raise_exception_err(excp
, err
);
726 ctx
->bstate
= BS_EXCP
;
729 static inline void generate_exception (DisasContext
*ctx
, int excp
)
731 generate_exception_err (ctx
, excp
, 0);
734 static inline void check_cp1_enabled(DisasContext
*ctx
)
736 if (!(ctx
->hflags
& MIPS_HFLAG_FPU
))
737 generate_exception_err(ctx
, EXCP_CpU
, 1);
740 static inline void check_cp1_64bitmode(DisasContext
*ctx
)
742 if (!(ctx
->hflags
& MIPS_HFLAG_F64
))
743 generate_exception(ctx
, EXCP_RI
);
747 * Verify if floating point register is valid; an operation is not defined
748 * if bit 0 of any register specification is set and the FR bit in the
749 * Status register equals zero, since the register numbers specify an
750 * even-odd pair of adjacent coprocessor general registers. When the FR bit
751 * in the Status register equals one, both even and odd register numbers
752 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
754 * Multiple 64 bit wide registers can be checked by calling
755 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
757 void check_cp1_registers(DisasContext
*ctx
, int regs
)
759 if (!(ctx
->hflags
& MIPS_HFLAG_F64
) && (regs
& 1))
760 generate_exception(ctx
, EXCP_RI
);
763 /* This code generates a "reserved instruction" exception if the
764 CPU is not a MIPS R2 (or higher) CPU. */
765 static inline void check_mips_r2(CPUState
*env
, DisasContext
*ctx
)
767 if ((env
->CP0_Config0
& (0x7 << CP0C0_AR
)) < (1 << CP0C0_AR
))
768 generate_exception(ctx
, EXCP_RI
);
771 /* This code generates a "reserved instruction" exception if the
772 CPU is not MIPS MT capable. */
773 static inline void check_mips_mt(CPUState
*env
, DisasContext
*ctx
)
775 if (!(env
->CP0_Config3
& (1 << CP0C3_MT
)))
776 generate_exception(ctx
, EXCP_RI
);
779 #if defined(CONFIG_USER_ONLY)
780 #define op_ldst(name) gen_op_##name##_raw()
781 #define OP_LD_TABLE(width)
782 #define OP_ST_TABLE(width)
784 #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
785 #define OP_LD_TABLE(width) \
786 static GenOpFunc *gen_op_l##width[] = { \
787 &gen_op_l##width##_user, \
788 &gen_op_l##width##_kernel, \
790 #define OP_ST_TABLE(width) \
791 static GenOpFunc *gen_op_s##width[] = { \
792 &gen_op_s##width##_user, \
793 &gen_op_s##width##_kernel, \
830 static void gen_ldst (DisasContext
*ctx
, uint32_t opc
, int rt
,
831 int base
, int16_t offset
)
833 const char *opn
= "ldst";
836 GEN_LOAD_IMM_TN(T0
, offset
);
837 } else if (offset
== 0) {
838 gen_op_load_gpr_T0(base
);
840 gen_op_load_gpr_T0(base
);
841 gen_op_set_T1(offset
);
844 /* Don't do NOP if destination is zero: we must perform the actual
850 GEN_STORE_TN_REG(rt
, T0
);
855 GEN_STORE_TN_REG(rt
, T0
);
860 GEN_STORE_TN_REG(rt
, T0
);
864 GEN_LOAD_REG_TN(T1
, rt
);
869 save_cpu_state(ctx
, 1);
870 GEN_LOAD_REG_TN(T1
, rt
);
872 GEN_STORE_TN_REG(rt
, T0
);
876 GEN_LOAD_REG_TN(T1
, rt
);
878 GEN_STORE_TN_REG(rt
, T0
);
882 GEN_LOAD_REG_TN(T1
, rt
);
887 GEN_LOAD_REG_TN(T1
, rt
);
889 GEN_STORE_TN_REG(rt
, T0
);
893 GEN_LOAD_REG_TN(T1
, rt
);
900 GEN_STORE_TN_REG(rt
, T0
);
904 GEN_LOAD_REG_TN(T1
, rt
);
910 GEN_STORE_TN_REG(rt
, T0
);
914 GEN_LOAD_REG_TN(T1
, rt
);
920 GEN_STORE_TN_REG(rt
, T0
);
925 GEN_STORE_TN_REG(rt
, T0
);
929 GEN_LOAD_REG_TN(T1
, rt
);
935 GEN_STORE_TN_REG(rt
, T0
);
939 GEN_LOAD_REG_TN(T1
, rt
);
941 GEN_STORE_TN_REG(rt
, T0
);
945 GEN_LOAD_REG_TN(T1
, rt
);
950 GEN_LOAD_REG_TN(T1
, rt
);
952 GEN_STORE_TN_REG(rt
, T0
);
956 GEN_LOAD_REG_TN(T1
, rt
);
962 GEN_STORE_TN_REG(rt
, T0
);
966 save_cpu_state(ctx
, 1);
967 GEN_LOAD_REG_TN(T1
, rt
);
969 GEN_STORE_TN_REG(rt
, T0
);
974 generate_exception(ctx
, EXCP_RI
);
977 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
981 static void gen_flt_ldst (DisasContext
*ctx
, uint32_t opc
, int ft
,
982 int base
, int16_t offset
)
984 const char *opn
= "flt_ldst";
987 GEN_LOAD_IMM_TN(T0
, offset
);
988 } else if (offset
== 0) {
989 gen_op_load_gpr_T0(base
);
991 gen_op_load_gpr_T0(base
);
992 gen_op_set_T1(offset
);
995 /* Don't do NOP if destination is zero: we must perform the actual
1000 GEN_STORE_FTN_FREG(ft
, WT0
);
1004 GEN_LOAD_FREG_FTN(WT0
, ft
);
1010 GEN_STORE_FTN_FREG(ft
, DT0
);
1014 GEN_LOAD_FREG_FTN(DT0
, ft
);
1020 generate_exception(ctx
, EXCP_RI
);
1023 MIPS_DEBUG("%s %s, %d(%s)", opn
, fregnames
[ft
], offset
, regnames
[base
]);
1026 /* Arithmetic with immediate operand */
1027 static void gen_arith_imm (DisasContext
*ctx
, uint32_t opc
, int rt
,
1028 int rs
, int16_t imm
)
1031 const char *opn
= "imm arith";
1033 if (rt
== 0 && opc
!= OPC_ADDI
&& opc
!= OPC_DADDI
) {
1034 /* If no destination, treat it as a NOP.
1035 For addi, we must generate the overflow exception when needed. */
1039 uimm
= (uint16_t)imm
;
1043 #ifdef TARGET_MIPS64
1049 uimm
= (target_long
)imm
; /* Sign extend to 32/64 bits */
1054 GEN_LOAD_REG_TN(T0
, rs
);
1055 GEN_LOAD_IMM_TN(T1
, uimm
);
1058 GEN_LOAD_IMM_TN(T0
, imm
<< 16);
1063 #ifdef TARGET_MIPS64
1072 GEN_LOAD_REG_TN(T0
, rs
);
1073 GEN_LOAD_IMM_TN(T1
, uimm
);
1078 save_cpu_state(ctx
, 1);
1086 #ifdef TARGET_MIPS64
1088 save_cpu_state(ctx
, 1);
1129 switch ((ctx
->opcode
>> 21) & 0x1f) {
1139 MIPS_INVAL("invalid srl flag");
1140 generate_exception(ctx
, EXCP_RI
);
1144 #ifdef TARGET_MIPS64
1154 switch ((ctx
->opcode
>> 21) & 0x1f) {
1164 MIPS_INVAL("invalid dsrl flag");
1165 generate_exception(ctx
, EXCP_RI
);
1178 switch ((ctx
->opcode
>> 21) & 0x1f) {
1188 MIPS_INVAL("invalid dsrl32 flag");
1189 generate_exception(ctx
, EXCP_RI
);
1196 generate_exception(ctx
, EXCP_RI
);
1199 GEN_STORE_TN_REG(rt
, T0
);
1200 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1204 static void gen_arith (DisasContext
*ctx
, uint32_t opc
,
1205 int rd
, int rs
, int rt
)
1207 const char *opn
= "arith";
1209 if (rd
== 0 && opc
!= OPC_ADD
&& opc
!= OPC_SUB
1210 && opc
!= OPC_DADD
&& opc
!= OPC_DSUB
) {
1211 /* If no destination, treat it as a NOP.
1212 For add & sub, we must generate the overflow exception when needed. */
1216 GEN_LOAD_REG_TN(T0
, rs
);
1217 GEN_LOAD_REG_TN(T1
, rt
);
1220 save_cpu_state(ctx
, 1);
1229 save_cpu_state(ctx
, 1);
1237 #ifdef TARGET_MIPS64
1239 save_cpu_state(ctx
, 1);
1248 save_cpu_state(ctx
, 1);
1302 switch ((ctx
->opcode
>> 6) & 0x1f) {
1312 MIPS_INVAL("invalid srlv flag");
1313 generate_exception(ctx
, EXCP_RI
);
1317 #ifdef TARGET_MIPS64
1327 switch ((ctx
->opcode
>> 6) & 0x1f) {
1337 MIPS_INVAL("invalid dsrlv flag");
1338 generate_exception(ctx
, EXCP_RI
);
1345 generate_exception(ctx
, EXCP_RI
);
1348 GEN_STORE_TN_REG(rd
, T0
);
1350 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1353 /* Arithmetic on HI/LO registers */
1354 static void gen_HILO (DisasContext
*ctx
, uint32_t opc
, int reg
)
1356 const char *opn
= "hilo";
1358 if (reg
== 0 && (opc
== OPC_MFHI
|| opc
== OPC_MFLO
)) {
1366 GEN_STORE_TN_REG(reg
, T0
);
1371 GEN_STORE_TN_REG(reg
, T0
);
1375 GEN_LOAD_REG_TN(T0
, reg
);
1380 GEN_LOAD_REG_TN(T0
, reg
);
1386 generate_exception(ctx
, EXCP_RI
);
1389 MIPS_DEBUG("%s %s", opn
, regnames
[reg
]);
1392 static void gen_muldiv (DisasContext
*ctx
, uint32_t opc
,
1395 const char *opn
= "mul/div";
1397 GEN_LOAD_REG_TN(T0
, rs
);
1398 GEN_LOAD_REG_TN(T1
, rt
);
1416 #ifdef TARGET_MIPS64
1452 generate_exception(ctx
, EXCP_RI
);
1455 MIPS_DEBUG("%s %s %s", opn
, regnames
[rs
], regnames
[rt
]);
1458 static void gen_cl (DisasContext
*ctx
, uint32_t opc
,
1461 const char *opn
= "CLx";
1467 GEN_LOAD_REG_TN(T0
, rs
);
1477 #ifdef TARGET_MIPS64
1489 generate_exception(ctx
, EXCP_RI
);
1492 gen_op_store_T0_gpr(rd
);
1493 MIPS_DEBUG("%s %s, %s", opn
, regnames
[rd
], regnames
[rs
]);
1497 static void gen_trap (DisasContext
*ctx
, uint32_t opc
,
1498 int rs
, int rt
, int16_t imm
)
1503 /* Load needed operands */
1511 /* Compare two registers */
1513 GEN_LOAD_REG_TN(T0
, rs
);
1514 GEN_LOAD_REG_TN(T1
, rt
);
1524 /* Compare register to immediate */
1525 if (rs
!= 0 || imm
!= 0) {
1526 GEN_LOAD_REG_TN(T0
, rs
);
1527 GEN_LOAD_IMM_TN(T1
, (int32_t)imm
);
1534 case OPC_TEQ
: /* rs == rs */
1535 case OPC_TEQI
: /* r0 == 0 */
1536 case OPC_TGE
: /* rs >= rs */
1537 case OPC_TGEI
: /* r0 >= 0 */
1538 case OPC_TGEU
: /* rs >= rs unsigned */
1539 case OPC_TGEIU
: /* r0 >= 0 unsigned */
1543 case OPC_TLT
: /* rs < rs */
1544 case OPC_TLTI
: /* r0 < 0 */
1545 case OPC_TLTU
: /* rs < rs unsigned */
1546 case OPC_TLTIU
: /* r0 < 0 unsigned */
1547 case OPC_TNE
: /* rs != rs */
1548 case OPC_TNEI
: /* r0 != 0 */
1549 /* Never trap: treat as NOP. */
1553 generate_exception(ctx
, EXCP_RI
);
1584 generate_exception(ctx
, EXCP_RI
);
1588 save_cpu_state(ctx
, 1);
1590 ctx
->bstate
= BS_STOP
;
1593 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
1595 TranslationBlock
*tb
;
1597 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
1599 gen_op_goto_tb0(TBPARAM(tb
));
1601 gen_op_goto_tb1(TBPARAM(tb
));
1603 gen_op_set_T0((long)tb
+ n
);
1611 /* Branches (before delay slot) */
1612 static void gen_compute_branch (DisasContext
*ctx
, uint32_t opc
,
1613 int rs
, int rt
, int32_t offset
)
1615 target_ulong btarget
= -1;
1619 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
1620 #ifdef MIPS_DEBUG_DISAS
1621 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
1623 "Branch in delay slot at PC 0x" TARGET_FMT_lx
"\n",
1627 generate_exception(ctx
, EXCP_RI
);
1631 /* Load needed operands */
1637 /* Compare two registers */
1639 GEN_LOAD_REG_TN(T0
, rs
);
1640 GEN_LOAD_REG_TN(T1
, rt
);
1643 btarget
= ctx
->pc
+ 4 + offset
;
1657 /* Compare to zero */
1659 gen_op_load_gpr_T0(rs
);
1662 btarget
= ctx
->pc
+ 4 + offset
;
1666 /* Jump to immediate */
1667 btarget
= ((ctx
->pc
+ 4) & (int32_t)0xF0000000) | (uint32_t)offset
;
1671 /* Jump to register */
1672 if (offset
!= 0 && offset
!= 16) {
1673 /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
1674 others are reserved. */
1675 MIPS_INVAL("jump hint");
1676 generate_exception(ctx
, EXCP_RI
);
1679 GEN_LOAD_REG_TN(T2
, rs
);
1682 MIPS_INVAL("branch/jump");
1683 generate_exception(ctx
, EXCP_RI
);
1687 /* No condition to be computed */
1689 case OPC_BEQ
: /* rx == rx */
1690 case OPC_BEQL
: /* rx == rx likely */
1691 case OPC_BGEZ
: /* 0 >= 0 */
1692 case OPC_BGEZL
: /* 0 >= 0 likely */
1693 case OPC_BLEZ
: /* 0 <= 0 */
1694 case OPC_BLEZL
: /* 0 <= 0 likely */
1696 ctx
->hflags
|= MIPS_HFLAG_B
;
1697 MIPS_DEBUG("balways");
1699 case OPC_BGEZAL
: /* 0 >= 0 */
1700 case OPC_BGEZALL
: /* 0 >= 0 likely */
1701 /* Always take and link */
1703 ctx
->hflags
|= MIPS_HFLAG_B
;
1704 MIPS_DEBUG("balways and link");
1706 case OPC_BNE
: /* rx != rx */
1707 case OPC_BGTZ
: /* 0 > 0 */
1708 case OPC_BLTZ
: /* 0 < 0 */
1710 MIPS_DEBUG("bnever (NOP)");
1712 case OPC_BLTZAL
: /* 0 < 0 */
1713 GEN_LOAD_IMM_TN(T0
, ctx
->pc
+ 8);
1714 gen_op_store_T0_gpr(31);
1715 MIPS_DEBUG("bnever and link");
1717 case OPC_BLTZALL
: /* 0 < 0 likely */
1718 GEN_LOAD_IMM_TN(T0
, ctx
->pc
+ 8);
1719 gen_op_store_T0_gpr(31);
1720 /* Skip the instruction in the delay slot */
1721 MIPS_DEBUG("bnever, link and skip");
1724 case OPC_BNEL
: /* rx != rx likely */
1725 case OPC_BGTZL
: /* 0 > 0 likely */
1726 case OPC_BLTZL
: /* 0 < 0 likely */
1727 /* Skip the instruction in the delay slot */
1728 MIPS_DEBUG("bnever and skip");
1732 ctx
->hflags
|= MIPS_HFLAG_B
;
1733 MIPS_DEBUG("j " TARGET_FMT_lx
, btarget
);
1737 ctx
->hflags
|= MIPS_HFLAG_B
;
1738 MIPS_DEBUG("jal " TARGET_FMT_lx
, btarget
);
1741 ctx
->hflags
|= MIPS_HFLAG_BR
;
1742 MIPS_DEBUG("jr %s", regnames
[rs
]);
1746 ctx
->hflags
|= MIPS_HFLAG_BR
;
1747 MIPS_DEBUG("jalr %s, %s", regnames
[rt
], regnames
[rs
]);
1750 MIPS_INVAL("branch/jump");
1751 generate_exception(ctx
, EXCP_RI
);
1758 MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx
,
1759 regnames
[rs
], regnames
[rt
], btarget
);
1763 MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx
,
1764 regnames
[rs
], regnames
[rt
], btarget
);
1768 MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx
,
1769 regnames
[rs
], regnames
[rt
], btarget
);
1773 MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx
,
1774 regnames
[rs
], regnames
[rt
], btarget
);
1778 MIPS_DEBUG("bgez %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1782 MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1786 MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1792 MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1796 MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1800 MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1804 MIPS_DEBUG("blez %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1808 MIPS_DEBUG("blezl %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1812 MIPS_DEBUG("bltz %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1816 MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1821 MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1823 ctx
->hflags
|= MIPS_HFLAG_BC
;
1829 MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1831 ctx
->hflags
|= MIPS_HFLAG_BL
;
1833 gen_op_save_bcond();
1836 MIPS_INVAL("conditional branch/jump");
1837 generate_exception(ctx
, EXCP_RI
);
1841 MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx
,
1842 blink
, ctx
->hflags
, btarget
);
1844 ctx
->btarget
= btarget
;
1846 GEN_LOAD_IMM_TN(T0
, ctx
->pc
+ 8);
1847 gen_op_store_T0_gpr(blink
);
1851 /* special3 bitfield operations */
1852 static void gen_bitops (DisasContext
*ctx
, uint32_t opc
, int rt
,
1853 int rs
, int lsb
, int msb
)
1855 GEN_LOAD_REG_TN(T1
, rs
);
1860 gen_op_ext(lsb
, msb
+ 1);
1865 gen_op_ext(lsb
, msb
+ 1 + 32);
1870 gen_op_ext(lsb
+ 32, msb
+ 1);
1873 gen_op_ext(lsb
, msb
+ 1);
1878 GEN_LOAD_REG_TN(T0
, rt
);
1879 gen_op_ins(lsb
, msb
- lsb
+ 1);
1884 GEN_LOAD_REG_TN(T0
, rt
);
1885 gen_op_ins(lsb
, msb
- lsb
+ 1 + 32);
1890 GEN_LOAD_REG_TN(T0
, rt
);
1891 gen_op_ins(lsb
+ 32, msb
- lsb
+ 1);
1896 GEN_LOAD_REG_TN(T0
, rt
);
1897 gen_op_ins(lsb
, msb
- lsb
+ 1);
1901 MIPS_INVAL("bitops");
1902 generate_exception(ctx
, EXCP_RI
);
1905 GEN_STORE_TN_REG(rt
, T0
);
1908 /* CP0 (MMU and control) */
1909 static void gen_mfc0 (CPUState
*env
, DisasContext
*ctx
, int reg
, int sel
)
1911 const char *rn
= "invalid";
1917 gen_op_mfc0_index();
1921 check_mips_mt(env
, ctx
);
1922 gen_op_mfc0_mvpcontrol();
1926 check_mips_mt(env
, ctx
);
1927 gen_op_mfc0_mvpconf0();
1931 check_mips_mt(env
, ctx
);
1932 gen_op_mfc0_mvpconf1();
1942 gen_op_mfc0_random();
1946 check_mips_mt(env
, ctx
);
1947 gen_op_mfc0_vpecontrol();
1951 check_mips_mt(env
, ctx
);
1952 gen_op_mfc0_vpeconf0();
1956 check_mips_mt(env
, ctx
);
1957 gen_op_mfc0_vpeconf1();
1961 check_mips_mt(env
, ctx
);
1962 gen_op_mfc0_yqmask();
1966 check_mips_mt(env
, ctx
);
1967 gen_op_mfc0_vpeschedule();
1971 check_mips_mt(env
, ctx
);
1972 gen_op_mfc0_vpeschefback();
1973 rn
= "VPEScheFBack";
1976 check_mips_mt(env
, ctx
);
1977 gen_op_mfc0_vpeopt();
1987 gen_op_mfc0_entrylo0();
1991 check_mips_mt(env
, ctx
);
1992 gen_op_mfc0_tcstatus();
1996 check_mips_mt(env
, ctx
);
1997 gen_op_mfc0_tcbind();
2001 check_mips_mt(env
, ctx
);
2002 gen_op_mfc0_tcrestart();
2006 check_mips_mt(env
, ctx
);
2007 gen_op_mfc0_tchalt();
2011 check_mips_mt(env
, ctx
);
2012 gen_op_mfc0_tccontext();
2016 check_mips_mt(env
, ctx
);
2017 gen_op_mfc0_tcschedule();
2021 check_mips_mt(env
, ctx
);
2022 gen_op_mfc0_tcschefback();
2032 gen_op_mfc0_entrylo1();
2042 gen_op_mfc0_context();
2046 // gen_op_mfc0_contextconfig(); /* SmartMIPS ASE */
2047 rn
= "ContextConfig";
2056 gen_op_mfc0_pagemask();
2060 check_mips_r2(env
, ctx
);
2061 gen_op_mfc0_pagegrain();
2071 gen_op_mfc0_wired();
2075 gen_op_mfc0_srsconf0();
2079 gen_op_mfc0_srsconf1();
2083 gen_op_mfc0_srsconf2();
2087 gen_op_mfc0_srsconf3();
2091 gen_op_mfc0_srsconf4();
2101 check_mips_r2(env
, ctx
);
2102 gen_op_mfc0_hwrena();
2112 gen_op_mfc0_badvaddr();
2122 gen_op_mfc0_count();
2125 /* 6,7 are implementation dependent */
2133 gen_op_mfc0_entryhi();
2143 gen_op_mfc0_compare();
2146 /* 6,7 are implementation dependent */
2154 gen_op_mfc0_status();
2158 check_mips_r2(env
, ctx
);
2159 gen_op_mfc0_intctl();
2163 check_mips_r2(env
, ctx
);
2164 gen_op_mfc0_srsctl();
2168 check_mips_r2(env
, ctx
);
2169 gen_op_mfc0_srsmap();
2179 gen_op_mfc0_cause();
2203 check_mips_r2(env
, ctx
);
2204 gen_op_mfc0_ebase();
2214 gen_op_mfc0_config0();
2218 gen_op_mfc0_config1();
2222 gen_op_mfc0_config2();
2226 gen_op_mfc0_config3();
2229 /* 4,5 are reserved */
2230 /* 6,7 are implementation dependent */
2232 gen_op_mfc0_config6();
2236 gen_op_mfc0_config7();
2246 gen_op_mfc0_lladdr();
2256 gen_op_mfc0_watchlo(sel
);
2266 gen_op_mfc0_watchhi(sel
);
2276 #ifdef TARGET_MIPS64
2277 if (!(ctx
->hflags
& MIPS_HFLAG_64
))
2279 gen_op_mfc0_xcontext();
2288 /* Officially reserved, but sel 0 is used for R1x000 framemask */
2291 gen_op_mfc0_framemask();
2300 rn
= "'Diagnostic"; /* implementation dependent */
2305 gen_op_mfc0_debug(); /* EJTAG support */
2309 // gen_op_mfc0_tracecontrol(); /* PDtrace support */
2310 rn
= "TraceControl";
2313 // gen_op_mfc0_tracecontrol2(); /* PDtrace support */
2314 rn
= "TraceControl2";
2317 // gen_op_mfc0_usertracedata(); /* PDtrace support */
2318 rn
= "UserTraceData";
2321 // gen_op_mfc0_debug(); /* PDtrace support */
2331 gen_op_mfc0_depc(); /* EJTAG support */
2341 gen_op_mfc0_performance0();
2342 rn
= "Performance0";
2345 // gen_op_mfc0_performance1();
2346 rn
= "Performance1";
2349 // gen_op_mfc0_performance2();
2350 rn
= "Performance2";
2353 // gen_op_mfc0_performance3();
2354 rn
= "Performance3";
2357 // gen_op_mfc0_performance4();
2358 rn
= "Performance4";
2361 // gen_op_mfc0_performance5();
2362 rn
= "Performance5";
2365 // gen_op_mfc0_performance6();
2366 rn
= "Performance6";
2369 // gen_op_mfc0_performance7();
2370 rn
= "Performance7";
2395 gen_op_mfc0_taglo();
2402 gen_op_mfc0_datalo();
2415 gen_op_mfc0_taghi();
2422 gen_op_mfc0_datahi();
2432 gen_op_mfc0_errorepc();
2442 gen_op_mfc0_desave(); /* EJTAG support */
2452 #if defined MIPS_DEBUG_DISAS
2453 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2454 fprintf(logfile
, "mfc0 %s (reg %d sel %d)\n",
2461 #if defined MIPS_DEBUG_DISAS
2462 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2463 fprintf(logfile
, "mfc0 %s (reg %d sel %d)\n",
2467 generate_exception(ctx
, EXCP_RI
);
2470 static void gen_mtc0 (CPUState
*env
, DisasContext
*ctx
, int reg
, int sel
)
2472 const char *rn
= "invalid";
2478 gen_op_mtc0_index();
2482 check_mips_mt(env
, ctx
);
2483 gen_op_mtc0_mvpcontrol();
2487 check_mips_mt(env
, ctx
);
2492 check_mips_mt(env
, ctx
);
2507 check_mips_mt(env
, ctx
);
2508 gen_op_mtc0_vpecontrol();
2512 check_mips_mt(env
, ctx
);
2513 gen_op_mtc0_vpeconf0();
2517 check_mips_mt(env
, ctx
);
2518 gen_op_mtc0_vpeconf1();
2522 check_mips_mt(env
, ctx
);
2523 gen_op_mtc0_yqmask();
2527 check_mips_mt(env
, ctx
);
2528 gen_op_mtc0_vpeschedule();
2532 check_mips_mt(env
, ctx
);
2533 gen_op_mtc0_vpeschefback();
2534 rn
= "VPEScheFBack";
2537 check_mips_mt(env
, ctx
);
2538 gen_op_mtc0_vpeopt();
2548 gen_op_mtc0_entrylo0();
2552 check_mips_mt(env
, ctx
);
2553 gen_op_mtc0_tcstatus();
2557 check_mips_mt(env
, ctx
);
2558 gen_op_mtc0_tcbind();
2562 check_mips_mt(env
, ctx
);
2563 gen_op_mtc0_tcrestart();
2567 check_mips_mt(env
, ctx
);
2568 gen_op_mtc0_tchalt();
2572 check_mips_mt(env
, ctx
);
2573 gen_op_mtc0_tccontext();
2577 check_mips_mt(env
, ctx
);
2578 gen_op_mtc0_tcschedule();
2582 check_mips_mt(env
, ctx
);
2583 gen_op_mtc0_tcschefback();
2593 gen_op_mtc0_entrylo1();
2603 gen_op_mtc0_context();
2607 // gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */
2608 rn
= "ContextConfig";
2617 gen_op_mtc0_pagemask();
2621 check_mips_r2(env
, ctx
);
2622 gen_op_mtc0_pagegrain();
2632 gen_op_mtc0_wired();
2636 gen_op_mtc0_srsconf0();
2640 gen_op_mtc0_srsconf1();
2644 gen_op_mtc0_srsconf2();
2648 gen_op_mtc0_srsconf3();
2652 gen_op_mtc0_srsconf4();
2662 check_mips_r2(env
, ctx
);
2663 gen_op_mtc0_hwrena();
2677 gen_op_mtc0_count();
2680 /* 6,7 are implementation dependent */
2684 /* Stop translation as we may have switched the execution mode */
2685 ctx
->bstate
= BS_STOP
;
2690 gen_op_mtc0_entryhi();
2700 gen_op_mtc0_compare();
2703 /* 6,7 are implementation dependent */
2707 /* Stop translation as we may have switched the execution mode */
2708 ctx
->bstate
= BS_STOP
;
2713 gen_op_mtc0_status();
2714 /* BS_STOP isn't good enough here, hflags may have changed. */
2715 gen_save_pc(ctx
->pc
+ 4);
2716 ctx
->bstate
= BS_EXCP
;
2720 check_mips_r2(env
, ctx
);
2721 gen_op_mtc0_intctl();
2722 /* Stop translation as we may have switched the execution mode */
2723 ctx
->bstate
= BS_STOP
;
2727 check_mips_r2(env
, ctx
);
2728 gen_op_mtc0_srsctl();
2729 /* Stop translation as we may have switched the execution mode */
2730 ctx
->bstate
= BS_STOP
;
2734 check_mips_r2(env
, ctx
);
2735 gen_op_mtc0_srsmap();
2736 /* Stop translation as we may have switched the execution mode */
2737 ctx
->bstate
= BS_STOP
;
2747 gen_op_mtc0_cause();
2753 /* Stop translation as we may have switched the execution mode */
2754 ctx
->bstate
= BS_STOP
;
2773 check_mips_r2(env
, ctx
);
2774 gen_op_mtc0_ebase();
2784 gen_op_mtc0_config0();
2786 /* Stop translation as we may have switched the execution mode */
2787 ctx
->bstate
= BS_STOP
;
2790 /* ignored, read only */
2794 gen_op_mtc0_config2();
2796 /* Stop translation as we may have switched the execution mode */
2797 ctx
->bstate
= BS_STOP
;
2800 /* ignored, read only */
2803 /* 4,5 are reserved */
2804 /* 6,7 are implementation dependent */
2814 rn
= "Invalid config selector";
2831 gen_op_mtc0_watchlo(sel
);
2841 gen_op_mtc0_watchhi(sel
);
2851 #ifdef TARGET_MIPS64
2852 if (!(ctx
->hflags
& MIPS_HFLAG_64
))
2854 gen_op_mtc0_xcontext();
2863 /* Officially reserved, but sel 0 is used for R1x000 framemask */
2866 gen_op_mtc0_framemask();
2875 rn
= "Diagnostic"; /* implementation dependent */
2880 gen_op_mtc0_debug(); /* EJTAG support */
2881 /* BS_STOP isn't good enough here, hflags may have changed. */
2882 gen_save_pc(ctx
->pc
+ 4);
2883 ctx
->bstate
= BS_EXCP
;
2887 // gen_op_mtc0_tracecontrol(); /* PDtrace support */
2888 rn
= "TraceControl";
2889 /* Stop translation as we may have switched the execution mode */
2890 ctx
->bstate
= BS_STOP
;
2893 // gen_op_mtc0_tracecontrol2(); /* PDtrace support */
2894 rn
= "TraceControl2";
2895 /* Stop translation as we may have switched the execution mode */
2896 ctx
->bstate
= BS_STOP
;
2899 /* Stop translation as we may have switched the execution mode */
2900 ctx
->bstate
= BS_STOP
;
2901 // gen_op_mtc0_usertracedata(); /* PDtrace support */
2902 rn
= "UserTraceData";
2903 /* Stop translation as we may have switched the execution mode */
2904 ctx
->bstate
= BS_STOP
;
2907 // gen_op_mtc0_debug(); /* PDtrace support */
2908 /* Stop translation as we may have switched the execution mode */
2909 ctx
->bstate
= BS_STOP
;
2919 gen_op_mtc0_depc(); /* EJTAG support */
2929 gen_op_mtc0_performance0();
2930 rn
= "Performance0";
2933 // gen_op_mtc0_performance1();
2934 rn
= "Performance1";
2937 // gen_op_mtc0_performance2();
2938 rn
= "Performance2";
2941 // gen_op_mtc0_performance3();
2942 rn
= "Performance3";
2945 // gen_op_mtc0_performance4();
2946 rn
= "Performance4";
2949 // gen_op_mtc0_performance5();
2950 rn
= "Performance5";
2953 // gen_op_mtc0_performance6();
2954 rn
= "Performance6";
2957 // gen_op_mtc0_performance7();
2958 rn
= "Performance7";
2984 gen_op_mtc0_taglo();
2991 gen_op_mtc0_datalo();
3004 gen_op_mtc0_taghi();
3011 gen_op_mtc0_datahi();
3022 gen_op_mtc0_errorepc();
3032 gen_op_mtc0_desave(); /* EJTAG support */
3038 /* Stop translation as we may have switched the execution mode */
3039 ctx
->bstate
= BS_STOP
;
3044 #if defined MIPS_DEBUG_DISAS
3045 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3046 fprintf(logfile
, "mtc0 %s (reg %d sel %d)\n",
3053 #if defined MIPS_DEBUG_DISAS
3054 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3055 fprintf(logfile
, "mtc0 %s (reg %d sel %d)\n",
3059 generate_exception(ctx
, EXCP_RI
);
3062 #ifdef TARGET_MIPS64
3063 static void gen_dmfc0 (CPUState
*env
, DisasContext
*ctx
, int reg
, int sel
)
3065 const char *rn
= "invalid";
3071 gen_op_mfc0_index();
3075 check_mips_mt(env
, ctx
);
3076 gen_op_mfc0_mvpcontrol();
3080 check_mips_mt(env
, ctx
);
3081 gen_op_mfc0_mvpconf0();
3085 check_mips_mt(env
, ctx
);
3086 gen_op_mfc0_mvpconf1();
3096 gen_op_mfc0_random();
3100 check_mips_mt(env
, ctx
);
3101 gen_op_mfc0_vpecontrol();
3105 check_mips_mt(env
, ctx
);
3106 gen_op_mfc0_vpeconf0();
3110 check_mips_mt(env
, ctx
);
3111 gen_op_mfc0_vpeconf1();
3115 check_mips_mt(env
, ctx
);
3116 gen_op_dmfc0_yqmask();
3120 check_mips_mt(env
, ctx
);
3121 gen_op_dmfc0_vpeschedule();
3125 check_mips_mt(env
, ctx
);
3126 gen_op_dmfc0_vpeschefback();
3127 rn
= "VPEScheFBack";
3130 check_mips_mt(env
, ctx
);
3131 gen_op_mfc0_vpeopt();
3141 gen_op_dmfc0_entrylo0();
3145 check_mips_mt(env
, ctx
);
3146 gen_op_mfc0_tcstatus();
3150 check_mips_mt(env
, ctx
);
3151 gen_op_mfc0_tcbind();
3155 check_mips_mt(env
, ctx
);
3156 gen_op_dmfc0_tcrestart();
3160 check_mips_mt(env
, ctx
);
3161 gen_op_dmfc0_tchalt();
3165 check_mips_mt(env
, ctx
);
3166 gen_op_dmfc0_tccontext();
3170 check_mips_mt(env
, ctx
);
3171 gen_op_dmfc0_tcschedule();
3175 check_mips_mt(env
, ctx
);
3176 gen_op_dmfc0_tcschefback();
3186 gen_op_dmfc0_entrylo1();
3196 gen_op_dmfc0_context();
3200 // gen_op_dmfc0_contextconfig(); /* SmartMIPS ASE */
3201 rn
= "ContextConfig";
3210 gen_op_mfc0_pagemask();
3214 check_mips_r2(env
, ctx
);
3215 gen_op_mfc0_pagegrain();
3225 gen_op_mfc0_wired();
3229 gen_op_mfc0_srsconf0();
3233 gen_op_mfc0_srsconf1();
3237 gen_op_mfc0_srsconf2();
3241 gen_op_mfc0_srsconf3();
3245 gen_op_mfc0_srsconf4();
3255 check_mips_r2(env
, ctx
);
3256 gen_op_mfc0_hwrena();
3266 gen_op_dmfc0_badvaddr();
3276 gen_op_mfc0_count();
3279 /* 6,7 are implementation dependent */
3287 gen_op_dmfc0_entryhi();
3297 gen_op_mfc0_compare();
3300 /* 6,7 are implementation dependent */
3308 gen_op_mfc0_status();
3312 check_mips_r2(env
, ctx
);
3313 gen_op_mfc0_intctl();
3317 check_mips_r2(env
, ctx
);
3318 gen_op_mfc0_srsctl();
3322 check_mips_r2(env
, ctx
);
3323 gen_op_mfc0_srsmap();
3333 gen_op_mfc0_cause();
3357 check_mips_r2(env
, ctx
);
3358 gen_op_mfc0_ebase();
3368 gen_op_mfc0_config0();
3372 gen_op_mfc0_config1();
3376 gen_op_mfc0_config2();
3380 gen_op_mfc0_config3();
3383 /* 6,7 are implementation dependent */
3391 gen_op_dmfc0_lladdr();
3401 gen_op_dmfc0_watchlo(sel
);
3411 gen_op_mfc0_watchhi(sel
);
3421 gen_op_dmfc0_xcontext();
3429 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3432 gen_op_mfc0_framemask();
3441 rn
= "'Diagnostic"; /* implementation dependent */
3446 gen_op_mfc0_debug(); /* EJTAG support */
3450 // gen_op_dmfc0_tracecontrol(); /* PDtrace support */
3451 rn
= "TraceControl";
3454 // gen_op_dmfc0_tracecontrol2(); /* PDtrace support */
3455 rn
= "TraceControl2";
3458 // gen_op_dmfc0_usertracedata(); /* PDtrace support */
3459 rn
= "UserTraceData";
3462 // gen_op_dmfc0_debug(); /* PDtrace support */
3472 gen_op_dmfc0_depc(); /* EJTAG support */
3482 gen_op_mfc0_performance0();
3483 rn
= "Performance0";
3486 // gen_op_dmfc0_performance1();
3487 rn
= "Performance1";
3490 // gen_op_dmfc0_performance2();
3491 rn
= "Performance2";
3494 // gen_op_dmfc0_performance3();
3495 rn
= "Performance3";
3498 // gen_op_dmfc0_performance4();
3499 rn
= "Performance4";
3502 // gen_op_dmfc0_performance5();
3503 rn
= "Performance5";
3506 // gen_op_dmfc0_performance6();
3507 rn
= "Performance6";
3510 // gen_op_dmfc0_performance7();
3511 rn
= "Performance7";
3536 gen_op_mfc0_taglo();
3543 gen_op_mfc0_datalo();
3556 gen_op_mfc0_taghi();
3563 gen_op_mfc0_datahi();
3573 gen_op_dmfc0_errorepc();
3583 gen_op_mfc0_desave(); /* EJTAG support */
3593 #if defined MIPS_DEBUG_DISAS
3594 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3595 fprintf(logfile
, "dmfc0 %s (reg %d sel %d)\n",
3602 #if defined MIPS_DEBUG_DISAS
3603 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3604 fprintf(logfile
, "dmfc0 %s (reg %d sel %d)\n",
3608 generate_exception(ctx
, EXCP_RI
);
3611 static void gen_dmtc0 (CPUState
*env
, DisasContext
*ctx
, int reg
, int sel
)
3613 const char *rn
= "invalid";
3619 gen_op_mtc0_index();
3623 check_mips_mt(env
, ctx
);
3624 gen_op_mtc0_mvpcontrol();
3628 check_mips_mt(env
, ctx
);
3633 check_mips_mt(env
, ctx
);
3648 check_mips_mt(env
, ctx
);
3649 gen_op_mtc0_vpecontrol();
3653 check_mips_mt(env
, ctx
);
3654 gen_op_mtc0_vpeconf0();
3658 check_mips_mt(env
, ctx
);
3659 gen_op_mtc0_vpeconf1();
3663 check_mips_mt(env
, ctx
);
3664 gen_op_mtc0_yqmask();
3668 check_mips_mt(env
, ctx
);
3669 gen_op_mtc0_vpeschedule();
3673 check_mips_mt(env
, ctx
);
3674 gen_op_mtc0_vpeschefback();
3675 rn
= "VPEScheFBack";
3678 check_mips_mt(env
, ctx
);
3679 gen_op_mtc0_vpeopt();
3689 gen_op_mtc0_entrylo0();
3693 check_mips_mt(env
, ctx
);
3694 gen_op_mtc0_tcstatus();
3698 check_mips_mt(env
, ctx
);
3699 gen_op_mtc0_tcbind();
3703 check_mips_mt(env
, ctx
);
3704 gen_op_mtc0_tcrestart();
3708 check_mips_mt(env
, ctx
);
3709 gen_op_mtc0_tchalt();
3713 check_mips_mt(env
, ctx
);
3714 gen_op_mtc0_tccontext();
3718 check_mips_mt(env
, ctx
);
3719 gen_op_mtc0_tcschedule();
3723 check_mips_mt(env
, ctx
);
3724 gen_op_mtc0_tcschefback();
3734 gen_op_mtc0_entrylo1();
3744 gen_op_mtc0_context();
3748 // gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */
3749 rn
= "ContextConfig";
3758 gen_op_mtc0_pagemask();
3762 check_mips_r2(env
, ctx
);
3763 gen_op_mtc0_pagegrain();
3773 gen_op_mtc0_wired();
3777 gen_op_mtc0_srsconf0();
3781 gen_op_mtc0_srsconf1();
3785 gen_op_mtc0_srsconf2();
3789 gen_op_mtc0_srsconf3();
3793 gen_op_mtc0_srsconf4();
3803 check_mips_r2(env
, ctx
);
3804 gen_op_mtc0_hwrena();
3818 gen_op_mtc0_count();
3821 /* 6,7 are implementation dependent */
3825 /* Stop translation as we may have switched the execution mode */
3826 ctx
->bstate
= BS_STOP
;
3831 gen_op_mtc0_entryhi();
3841 gen_op_mtc0_compare();
3844 /* 6,7 are implementation dependent */
3848 /* Stop translation as we may have switched the execution mode */
3849 ctx
->bstate
= BS_STOP
;
3854 gen_op_mtc0_status();
3855 /* BS_STOP isn't good enough here, hflags may have changed. */
3856 gen_save_pc(ctx
->pc
+ 4);
3857 ctx
->bstate
= BS_EXCP
;
3861 check_mips_r2(env
, ctx
);
3862 gen_op_mtc0_intctl();
3863 /* Stop translation as we may have switched the execution mode */
3864 ctx
->bstate
= BS_STOP
;
3868 check_mips_r2(env
, ctx
);
3869 gen_op_mtc0_srsctl();
3870 /* Stop translation as we may have switched the execution mode */
3871 ctx
->bstate
= BS_STOP
;
3875 check_mips_r2(env
, ctx
);
3876 gen_op_mtc0_srsmap();
3877 /* Stop translation as we may have switched the execution mode */
3878 ctx
->bstate
= BS_STOP
;
3888 gen_op_mtc0_cause();
3894 /* Stop translation as we may have switched the execution mode */
3895 ctx
->bstate
= BS_STOP
;
3914 check_mips_r2(env
, ctx
);
3915 gen_op_mtc0_ebase();
3925 gen_op_mtc0_config0();
3927 /* Stop translation as we may have switched the execution mode */
3928 ctx
->bstate
= BS_STOP
;
3935 gen_op_mtc0_config2();
3937 /* Stop translation as we may have switched the execution mode */
3938 ctx
->bstate
= BS_STOP
;
3944 /* 6,7 are implementation dependent */
3946 rn
= "Invalid config selector";
3963 gen_op_mtc0_watchlo(sel
);
3973 gen_op_mtc0_watchhi(sel
);
3983 gen_op_mtc0_xcontext();
3991 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3994 gen_op_mtc0_framemask();
4003 rn
= "Diagnostic"; /* implementation dependent */
4008 gen_op_mtc0_debug(); /* EJTAG support */
4009 /* BS_STOP isn't good enough here, hflags may have changed. */
4010 gen_save_pc(ctx
->pc
+ 4);
4011 ctx
->bstate
= BS_EXCP
;
4015 // gen_op_mtc0_tracecontrol(); /* PDtrace support */
4016 /* Stop translation as we may have switched the execution mode */
4017 ctx
->bstate
= BS_STOP
;
4018 rn
= "TraceControl";
4021 // gen_op_mtc0_tracecontrol2(); /* PDtrace support */
4022 /* Stop translation as we may have switched the execution mode */
4023 ctx
->bstate
= BS_STOP
;
4024 rn
= "TraceControl2";
4027 // gen_op_mtc0_usertracedata(); /* PDtrace support */
4028 /* Stop translation as we may have switched the execution mode */
4029 ctx
->bstate
= BS_STOP
;
4030 rn
= "UserTraceData";
4033 // gen_op_mtc0_debug(); /* PDtrace support */
4034 /* Stop translation as we may have switched the execution mode */
4035 ctx
->bstate
= BS_STOP
;
4045 gen_op_mtc0_depc(); /* EJTAG support */
4055 gen_op_mtc0_performance0();
4056 rn
= "Performance0";
4059 // gen_op_mtc0_performance1();
4060 rn
= "Performance1";
4063 // gen_op_mtc0_performance2();
4064 rn
= "Performance2";
4067 // gen_op_mtc0_performance3();
4068 rn
= "Performance3";
4071 // gen_op_mtc0_performance4();
4072 rn
= "Performance4";
4075 // gen_op_mtc0_performance5();
4076 rn
= "Performance5";
4079 // gen_op_mtc0_performance6();
4080 rn
= "Performance6";
4083 // gen_op_mtc0_performance7();
4084 rn
= "Performance7";
4110 gen_op_mtc0_taglo();
4117 gen_op_mtc0_datalo();
4130 gen_op_mtc0_taghi();
4137 gen_op_mtc0_datahi();
4148 gen_op_mtc0_errorepc();
4158 gen_op_mtc0_desave(); /* EJTAG support */
4164 /* Stop translation as we may have switched the execution mode */
4165 ctx
->bstate
= BS_STOP
;
4170 #if defined MIPS_DEBUG_DISAS
4171 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4172 fprintf(logfile
, "dmtc0 %s (reg %d sel %d)\n",
4179 #if defined MIPS_DEBUG_DISAS
4180 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4181 fprintf(logfile
, "dmtc0 %s (reg %d sel %d)\n",
4185 generate_exception(ctx
, EXCP_RI
);
4187 #endif /* TARGET_MIPS64 */
4189 static void gen_mftr(CPUState
*env
, DisasContext
*ctx
, int rt
,
4190 int u
, int sel
, int h
)
4192 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
4194 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
4195 ((env
->CP0_TCBind
[other_tc
] & (0xf << CP0TCBd_CurVPE
)) !=
4196 (env
->CP0_TCBind
[env
->current_tc
] & (0xf << CP0TCBd_CurVPE
))))
4198 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
4199 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
4206 gen_op_mftc0_tcstatus();
4209 gen_op_mftc0_tcbind();
4212 gen_op_mftc0_tcrestart();
4215 gen_op_mftc0_tchalt();
4218 gen_op_mftc0_tccontext();
4221 gen_op_mftc0_tcschedule();
4224 gen_op_mftc0_tcschefback();
4227 gen_mfc0(env
, ctx
, rt
, sel
);
4234 gen_op_mftc0_entryhi();
4237 gen_mfc0(env
, ctx
, rt
, sel
);
4243 gen_op_mftc0_status();
4246 gen_mfc0(env
, ctx
, rt
, sel
);
4252 gen_op_mftc0_debug();
4255 gen_mfc0(env
, ctx
, rt
, sel
);
4260 gen_mfc0(env
, ctx
, rt
, sel
);
4262 } else switch (sel
) {
4263 /* GPR registers. */
4267 /* Auxiliary CPU registers */
4313 /* Floating point (COP1). */
4315 /* XXX: For now we support only a single FPU context. */
4317 GEN_LOAD_FREG_FTN(WT0
, rt
);
4320 GEN_LOAD_FREG_FTN(WTH0
, rt
);
4325 /* XXX: For now we support only a single FPU context. */
4328 /* COP2: Not implemented. */
4335 #if defined MIPS_DEBUG_DISAS
4336 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4337 fprintf(logfile
, "mftr (reg %d u %d sel %d h %d)\n",
4344 #if defined MIPS_DEBUG_DISAS
4345 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4346 fprintf(logfile
, "mftr (reg %d u %d sel %d h %d)\n",
4350 generate_exception(ctx
, EXCP_RI
);
4353 static void gen_mttr(CPUState
*env
, DisasContext
*ctx
, int rd
,
4354 int u
, int sel
, int h
)
4356 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
4358 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
4359 ((env
->CP0_TCBind
[other_tc
] & (0xf << CP0TCBd_CurVPE
)) !=
4360 (env
->CP0_TCBind
[env
->current_tc
] & (0xf << CP0TCBd_CurVPE
))))
4362 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
4363 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
4370 gen_op_mttc0_tcstatus();
4373 gen_op_mttc0_tcbind();
4376 gen_op_mttc0_tcrestart();
4379 gen_op_mttc0_tchalt();
4382 gen_op_mttc0_tccontext();
4385 gen_op_mttc0_tcschedule();
4388 gen_op_mttc0_tcschefback();
4391 gen_mtc0(env
, ctx
, rd
, sel
);
4398 gen_op_mttc0_entryhi();
4401 gen_mtc0(env
, ctx
, rd
, sel
);
4407 gen_op_mttc0_status();
4410 gen_mtc0(env
, ctx
, rd
, sel
);
4416 gen_op_mttc0_debug();
4419 gen_mtc0(env
, ctx
, rd
, sel
);
4424 gen_mtc0(env
, ctx
, rd
, sel
);
4426 } else switch (sel
) {
4427 /* GPR registers. */
4431 /* Auxiliary CPU registers */
4477 /* Floating point (COP1). */
4479 /* XXX: For now we support only a single FPU context. */
4482 GEN_STORE_FTN_FREG(rd
, WT0
);
4485 GEN_STORE_FTN_FREG(rd
, WTH0
);
4489 /* XXX: For now we support only a single FPU context. */
4492 /* COP2: Not implemented. */
4499 #if defined MIPS_DEBUG_DISAS
4500 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4501 fprintf(logfile
, "mttr (reg %d u %d sel %d h %d)\n",
4508 #if defined MIPS_DEBUG_DISAS
4509 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4510 fprintf(logfile
, "mttr (reg %d u %d sel %d h %d)\n",
4514 generate_exception(ctx
, EXCP_RI
);
4517 static void gen_cp0 (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
, int rt
, int rd
)
4519 const char *opn
= "ldst";
4527 gen_mfc0(env
, ctx
, rd
, ctx
->opcode
& 0x7);
4528 gen_op_store_T0_gpr(rt
);
4532 GEN_LOAD_REG_TN(T0
, rt
);
4533 gen_mtc0(env
, ctx
, rd
, ctx
->opcode
& 0x7);
4536 #ifdef TARGET_MIPS64
4538 if (!(ctx
->hflags
& MIPS_HFLAG_64
))
4539 generate_exception(ctx
, EXCP_RI
);
4544 gen_dmfc0(env
, ctx
, rd
, ctx
->opcode
& 0x7);
4545 gen_op_store_T0_gpr(rt
);
4549 if (!(ctx
->hflags
& MIPS_HFLAG_64
))
4550 generate_exception(ctx
, EXCP_RI
);
4551 GEN_LOAD_REG_TN(T0
, rt
);
4552 gen_dmtc0(env
, ctx
, rd
, ctx
->opcode
& 0x7);
4557 check_mips_mt(env
, ctx
);
4562 gen_mftr(env
, ctx
, rt
, (ctx
->opcode
>> 5) & 1,
4563 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
4564 gen_op_store_T0_gpr(rd
);
4568 check_mips_mt(env
, ctx
);
4569 GEN_LOAD_REG_TN(T0
, rt
);
4570 gen_mttr(env
, ctx
, rd
, (ctx
->opcode
>> 5) & 1,
4571 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
4576 if (!env
->tlb
->do_tlbwi
)
4582 if (!env
->tlb
->do_tlbwr
)
4588 if (!env
->tlb
->do_tlbp
)
4594 if (!env
->tlb
->do_tlbr
)
4601 ctx
->bstate
= BS_EXCP
;
4605 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
4607 generate_exception(ctx
, EXCP_RI
);
4610 ctx
->bstate
= BS_EXCP
;
4615 /* If we get an exception, we want to restart at next instruction */
4617 save_cpu_state(ctx
, 1);
4620 ctx
->bstate
= BS_EXCP
;
4625 generate_exception(ctx
, EXCP_RI
);
4628 MIPS_DEBUG("%s %s %d", opn
, regnames
[rt
], rd
);
4631 /* CP1 Branches (before delay slot) */
4632 static void gen_compute_branch1 (DisasContext
*ctx
, uint32_t op
,
4633 int32_t cc
, int32_t offset
)
4635 target_ulong btarget
;
4636 const char *opn
= "cp1 cond branch";
4638 btarget
= ctx
->pc
+ 4 + offset
;
4657 ctx
->hflags
|= MIPS_HFLAG_BL
;
4659 gen_op_save_bcond();
4662 gen_op_bc1any2f(cc
);
4666 gen_op_bc1any2t(cc
);
4670 gen_op_bc1any4f(cc
);
4674 gen_op_bc1any4t(cc
);
4677 ctx
->hflags
|= MIPS_HFLAG_BC
;
4682 generate_exception (ctx
, EXCP_RI
);
4685 MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx
, opn
,
4686 ctx
->hflags
, btarget
);
4687 ctx
->btarget
= btarget
;
4690 /* Coprocessor 1 (FPU) */
4692 #define FOP(func, fmt) (((fmt) << 21) | (func))
4694 static void gen_cp1 (DisasContext
*ctx
, uint32_t opc
, int rt
, int fs
)
4696 const char *opn
= "cp1 move";
4700 GEN_LOAD_FREG_FTN(WT0
, fs
);
4702 GEN_STORE_TN_REG(rt
, T0
);
4706 GEN_LOAD_REG_TN(T0
, rt
);
4708 GEN_STORE_FTN_FREG(fs
, WT0
);
4713 GEN_STORE_TN_REG(rt
, T0
);
4717 GEN_LOAD_REG_TN(T0
, rt
);
4722 GEN_LOAD_FREG_FTN(DT0
, fs
);
4724 GEN_STORE_TN_REG(rt
, T0
);
4728 GEN_LOAD_REG_TN(T0
, rt
);
4730 GEN_STORE_FTN_FREG(fs
, DT0
);
4734 GEN_LOAD_FREG_FTN(WTH0
, fs
);
4736 GEN_STORE_TN_REG(rt
, T0
);
4740 GEN_LOAD_REG_TN(T0
, rt
);
4742 GEN_STORE_FTN_FREG(fs
, WTH0
);
4747 generate_exception (ctx
, EXCP_RI
);
4750 MIPS_DEBUG("%s %s %s", opn
, regnames
[rt
], fregnames
[fs
]);
4753 static void gen_movci (DisasContext
*ctx
, int rd
, int rs
, int cc
, int tf
)
4757 GEN_LOAD_REG_TN(T0
, rd
);
4758 GEN_LOAD_REG_TN(T1
, rs
);
4760 ccbit
= 1 << (24 + cc
);
4767 GEN_STORE_TN_REG(rd
, T0
);
4770 #define GEN_MOVCF(fmt) \
4771 static void glue(gen_movcf_, fmt) (DisasContext *ctx, int cc, int tf) \
4776 ccbit = 1 << (24 + cc); \
4780 glue(gen_op_float_movf_, fmt)(ccbit); \
4782 glue(gen_op_float_movt_, fmt)(ccbit); \
4789 static void gen_farith (DisasContext
*ctx
, uint32_t op1
,
4790 int ft
, int fs
, int fd
, int cc
)
4792 const char *opn
= "farith";
4793 const char *condnames
[] = {
4811 const char *condnames_abs
[] = {
4829 enum { BINOP
, CMPOP
, OTHEROP
} optype
= OTHEROP
;
4830 uint32_t func
= ctx
->opcode
& 0x3f;
4832 switch (ctx
->opcode
& FOP(0x3f, 0x1f)) {
4834 GEN_LOAD_FREG_FTN(WT0
, fs
);
4835 GEN_LOAD_FREG_FTN(WT1
, ft
);
4836 gen_op_float_add_s();
4837 GEN_STORE_FTN_FREG(fd
, WT2
);
4842 GEN_LOAD_FREG_FTN(WT0
, fs
);
4843 GEN_LOAD_FREG_FTN(WT1
, ft
);
4844 gen_op_float_sub_s();
4845 GEN_STORE_FTN_FREG(fd
, WT2
);
4850 GEN_LOAD_FREG_FTN(WT0
, fs
);
4851 GEN_LOAD_FREG_FTN(WT1
, ft
);
4852 gen_op_float_mul_s();
4853 GEN_STORE_FTN_FREG(fd
, WT2
);
4858 GEN_LOAD_FREG_FTN(WT0
, fs
);
4859 GEN_LOAD_FREG_FTN(WT1
, ft
);
4860 gen_op_float_div_s();
4861 GEN_STORE_FTN_FREG(fd
, WT2
);
4866 GEN_LOAD_FREG_FTN(WT0
, fs
);
4867 gen_op_float_sqrt_s();
4868 GEN_STORE_FTN_FREG(fd
, WT2
);
4872 GEN_LOAD_FREG_FTN(WT0
, fs
);
4873 gen_op_float_abs_s();
4874 GEN_STORE_FTN_FREG(fd
, WT2
);
4878 GEN_LOAD_FREG_FTN(WT0
, fs
);
4879 gen_op_float_mov_s();
4880 GEN_STORE_FTN_FREG(fd
, WT2
);
4884 GEN_LOAD_FREG_FTN(WT0
, fs
);
4885 gen_op_float_chs_s();
4886 GEN_STORE_FTN_FREG(fd
, WT2
);
4890 check_cp1_64bitmode(ctx
);
4891 GEN_LOAD_FREG_FTN(WT0
, fs
);
4892 gen_op_float_roundl_s();
4893 GEN_STORE_FTN_FREG(fd
, DT2
);
4897 check_cp1_64bitmode(ctx
);
4898 GEN_LOAD_FREG_FTN(WT0
, fs
);
4899 gen_op_float_truncl_s();
4900 GEN_STORE_FTN_FREG(fd
, DT2
);
4904 check_cp1_64bitmode(ctx
);
4905 GEN_LOAD_FREG_FTN(WT0
, fs
);
4906 gen_op_float_ceill_s();
4907 GEN_STORE_FTN_FREG(fd
, DT2
);
4911 check_cp1_64bitmode(ctx
);
4912 GEN_LOAD_FREG_FTN(WT0
, fs
);
4913 gen_op_float_floorl_s();
4914 GEN_STORE_FTN_FREG(fd
, DT2
);
4918 GEN_LOAD_FREG_FTN(WT0
, fs
);
4919 gen_op_float_roundw_s();
4920 GEN_STORE_FTN_FREG(fd
, WT2
);
4924 GEN_LOAD_FREG_FTN(WT0
, fs
);
4925 gen_op_float_truncw_s();
4926 GEN_STORE_FTN_FREG(fd
, WT2
);
4930 GEN_LOAD_FREG_FTN(WT0
, fs
);
4931 gen_op_float_ceilw_s();
4932 GEN_STORE_FTN_FREG(fd
, WT2
);
4936 GEN_LOAD_FREG_FTN(WT0
, fs
);
4937 gen_op_float_floorw_s();
4938 GEN_STORE_FTN_FREG(fd
, WT2
);
4942 GEN_LOAD_REG_TN(T0
, ft
);
4943 GEN_LOAD_FREG_FTN(WT0
, fs
);
4944 GEN_LOAD_FREG_FTN(WT2
, fd
);
4945 gen_movcf_s(ctx
, (ft
>> 2) & 0x7, ft
& 0x1);
4946 GEN_STORE_FTN_FREG(fd
, WT2
);
4950 GEN_LOAD_REG_TN(T0
, ft
);
4951 GEN_LOAD_FREG_FTN(WT0
, fs
);
4952 GEN_LOAD_FREG_FTN(WT2
, fd
);
4953 gen_op_float_movz_s();
4954 GEN_STORE_FTN_FREG(fd
, WT2
);
4958 GEN_LOAD_REG_TN(T0
, ft
);
4959 GEN_LOAD_FREG_FTN(WT0
, fs
);
4960 GEN_LOAD_FREG_FTN(WT2
, fd
);
4961 gen_op_float_movn_s();
4962 GEN_STORE_FTN_FREG(fd
, WT2
);
4966 GEN_LOAD_FREG_FTN(WT0
, fs
);
4967 gen_op_float_recip_s();
4968 GEN_STORE_FTN_FREG(fd
, WT2
);
4972 GEN_LOAD_FREG_FTN(WT0
, fs
);
4973 gen_op_float_rsqrt_s();
4974 GEN_STORE_FTN_FREG(fd
, WT2
);
4978 check_cp1_64bitmode(ctx
);
4979 GEN_LOAD_FREG_FTN(WT0
, fs
);
4980 GEN_LOAD_FREG_FTN(WT2
, fd
);
4981 gen_op_float_recip2_s();
4982 GEN_STORE_FTN_FREG(fd
, WT2
);
4986 check_cp1_64bitmode(ctx
);
4987 GEN_LOAD_FREG_FTN(WT0
, fs
);
4988 gen_op_float_recip1_s();
4989 GEN_STORE_FTN_FREG(fd
, WT2
);
4993 check_cp1_64bitmode(ctx
);
4994 GEN_LOAD_FREG_FTN(WT0
, fs
);
4995 gen_op_float_rsqrt1_s();
4996 GEN_STORE_FTN_FREG(fd
, WT2
);
5000 check_cp1_64bitmode(ctx
);
5001 GEN_LOAD_FREG_FTN(WT0
, fs
);
5002 GEN_LOAD_FREG_FTN(WT2
, ft
);
5003 gen_op_float_rsqrt2_s();
5004 GEN_STORE_FTN_FREG(fd
, WT2
);
5008 check_cp1_registers(ctx
, fd
);
5009 GEN_LOAD_FREG_FTN(WT0
, fs
);
5010 gen_op_float_cvtd_s();
5011 GEN_STORE_FTN_FREG(fd
, DT2
);
5015 GEN_LOAD_FREG_FTN(WT0
, fs
);
5016 gen_op_float_cvtw_s();
5017 GEN_STORE_FTN_FREG(fd
, WT2
);
5021 check_cp1_64bitmode(ctx
);
5022 GEN_LOAD_FREG_FTN(WT0
, fs
);
5023 gen_op_float_cvtl_s();
5024 GEN_STORE_FTN_FREG(fd
, DT2
);
5028 check_cp1_64bitmode(ctx
);
5029 GEN_LOAD_FREG_FTN(WT1
, fs
);
5030 GEN_LOAD_FREG_FTN(WT0
, ft
);
5031 gen_op_float_cvtps_s();
5032 GEN_STORE_FTN_FREG(fd
, DT2
);
5051 GEN_LOAD_FREG_FTN(WT0
, fs
);
5052 GEN_LOAD_FREG_FTN(WT1
, ft
);
5053 if (ctx
->opcode
& (1 << 6)) {
5054 check_cp1_64bitmode(ctx
);
5055 gen_cmpabs_s(func
-48, cc
);
5056 opn
= condnames_abs
[func
-48];
5058 gen_cmp_s(func
-48, cc
);
5059 opn
= condnames
[func
-48];
5063 check_cp1_registers(ctx
, fs
| ft
| fd
);
5064 GEN_LOAD_FREG_FTN(DT0
, fs
);
5065 GEN_LOAD_FREG_FTN(DT1
, ft
);
5066 gen_op_float_add_d();
5067 GEN_STORE_FTN_FREG(fd
, DT2
);
5072 check_cp1_registers(ctx
, fs
| ft
| fd
);
5073 GEN_LOAD_FREG_FTN(DT0
, fs
);
5074 GEN_LOAD_FREG_FTN(DT1
, ft
);
5075 gen_op_float_sub_d();
5076 GEN_STORE_FTN_FREG(fd
, DT2
);
5081 check_cp1_registers(ctx
, fs
| ft
| fd
);
5082 GEN_LOAD_FREG_FTN(DT0
, fs
);
5083 GEN_LOAD_FREG_FTN(DT1
, ft
);
5084 gen_op_float_mul_d();
5085 GEN_STORE_FTN_FREG(fd
, DT2
);
5090 check_cp1_registers(ctx
, fs
| ft
| fd
);
5091 GEN_LOAD_FREG_FTN(DT0
, fs
);
5092 GEN_LOAD_FREG_FTN(DT1
, ft
);
5093 gen_op_float_div_d();
5094 GEN_STORE_FTN_FREG(fd
, DT2
);
5099 check_cp1_registers(ctx
, fs
| fd
);
5100 GEN_LOAD_FREG_FTN(DT0
, fs
);
5101 gen_op_float_sqrt_d();
5102 GEN_STORE_FTN_FREG(fd
, DT2
);
5106 check_cp1_registers(ctx
, fs
| fd
);
5107 GEN_LOAD_FREG_FTN(DT0
, fs
);
5108 gen_op_float_abs_d();
5109 GEN_STORE_FTN_FREG(fd
, DT2
);
5113 check_cp1_registers(ctx
, fs
| fd
);
5114 GEN_LOAD_FREG_FTN(DT0
, fs
);
5115 gen_op_float_mov_d();
5116 GEN_STORE_FTN_FREG(fd
, DT2
);
5120 check_cp1_registers(ctx
, fs
| fd
);
5121 GEN_LOAD_FREG_FTN(DT0
, fs
);
5122 gen_op_float_chs_d();
5123 GEN_STORE_FTN_FREG(fd
, DT2
);
5127 check_cp1_64bitmode(ctx
);
5128 GEN_LOAD_FREG_FTN(DT0
, fs
);
5129 gen_op_float_roundl_d();
5130 GEN_STORE_FTN_FREG(fd
, DT2
);
5134 check_cp1_64bitmode(ctx
);
5135 GEN_LOAD_FREG_FTN(DT0
, fs
);
5136 gen_op_float_truncl_d();
5137 GEN_STORE_FTN_FREG(fd
, DT2
);
5141 check_cp1_64bitmode(ctx
);
5142 GEN_LOAD_FREG_FTN(DT0
, fs
);
5143 gen_op_float_ceill_d();
5144 GEN_STORE_FTN_FREG(fd
, DT2
);
5148 check_cp1_64bitmode(ctx
);
5149 GEN_LOAD_FREG_FTN(DT0
, fs
);
5150 gen_op_float_floorl_d();
5151 GEN_STORE_FTN_FREG(fd
, DT2
);
5155 check_cp1_registers(ctx
, fs
);
5156 GEN_LOAD_FREG_FTN(DT0
, fs
);
5157 gen_op_float_roundw_d();
5158 GEN_STORE_FTN_FREG(fd
, WT2
);
5162 check_cp1_registers(ctx
, fs
);
5163 GEN_LOAD_FREG_FTN(DT0
, fs
);
5164 gen_op_float_truncw_d();
5165 GEN_STORE_FTN_FREG(fd
, WT2
);
5169 check_cp1_registers(ctx
, fs
);
5170 GEN_LOAD_FREG_FTN(DT0
, fs
);
5171 gen_op_float_ceilw_d();
5172 GEN_STORE_FTN_FREG(fd
, WT2
);
5176 check_cp1_registers(ctx
, fs
);
5177 GEN_LOAD_FREG_FTN(DT0
, fs
);
5178 gen_op_float_floorw_d();
5179 GEN_STORE_FTN_FREG(fd
, WT2
);
5183 GEN_LOAD_REG_TN(T0
, ft
);
5184 GEN_LOAD_FREG_FTN(DT0
, fs
);
5185 GEN_LOAD_FREG_FTN(DT2
, fd
);
5186 gen_movcf_d(ctx
, (ft
>> 2) & 0x7, ft
& 0x1);
5187 GEN_STORE_FTN_FREG(fd
, DT2
);
5191 GEN_LOAD_REG_TN(T0
, ft
);
5192 GEN_LOAD_FREG_FTN(DT0
, fs
);
5193 GEN_LOAD_FREG_FTN(DT2
, fd
);
5194 gen_op_float_movz_d();
5195 GEN_STORE_FTN_FREG(fd
, DT2
);
5199 GEN_LOAD_REG_TN(T0
, ft
);
5200 GEN_LOAD_FREG_FTN(DT0
, fs
);
5201 GEN_LOAD_FREG_FTN(DT2
, fd
);
5202 gen_op_float_movn_d();
5203 GEN_STORE_FTN_FREG(fd
, DT2
);
5207 check_cp1_registers(ctx
, fs
| fd
);
5208 GEN_LOAD_FREG_FTN(DT0
, fs
);
5209 gen_op_float_recip_d();
5210 GEN_STORE_FTN_FREG(fd
, DT2
);
5214 check_cp1_registers(ctx
, fs
| fd
);
5215 GEN_LOAD_FREG_FTN(DT0
, fs
);
5216 gen_op_float_rsqrt_d();
5217 GEN_STORE_FTN_FREG(fd
, DT2
);
5221 check_cp1_64bitmode(ctx
);
5222 GEN_LOAD_FREG_FTN(DT0
, fs
);
5223 GEN_LOAD_FREG_FTN(DT2
, ft
);
5224 gen_op_float_recip2_d();
5225 GEN_STORE_FTN_FREG(fd
, DT2
);
5229 check_cp1_64bitmode(ctx
);
5230 GEN_LOAD_FREG_FTN(DT0
, fs
);
5231 gen_op_float_recip1_d();
5232 GEN_STORE_FTN_FREG(fd
, DT2
);
5236 check_cp1_64bitmode(ctx
);
5237 GEN_LOAD_FREG_FTN(DT0
, fs
);
5238 gen_op_float_rsqrt1_d();
5239 GEN_STORE_FTN_FREG(fd
, DT2
);
5243 check_cp1_64bitmode(ctx
);
5244 GEN_LOAD_FREG_FTN(DT0
, fs
);
5245 GEN_LOAD_FREG_FTN(DT2
, ft
);
5246 gen_op_float_rsqrt2_d();
5247 GEN_STORE_FTN_FREG(fd
, DT2
);
5266 GEN_LOAD_FREG_FTN(DT0
, fs
);
5267 GEN_LOAD_FREG_FTN(DT1
, ft
);
5268 if (ctx
->opcode
& (1 << 6)) {
5269 check_cp1_64bitmode(ctx
);
5270 gen_cmpabs_d(func
-48, cc
);
5271 opn
= condnames_abs
[func
-48];
5273 check_cp1_registers(ctx
, fs
| ft
);
5274 gen_cmp_d(func
-48, cc
);
5275 opn
= condnames
[func
-48];
5279 check_cp1_registers(ctx
, fs
);
5280 GEN_LOAD_FREG_FTN(DT0
, fs
);
5281 gen_op_float_cvts_d();
5282 GEN_STORE_FTN_FREG(fd
, WT2
);
5286 check_cp1_registers(ctx
, fs
);
5287 GEN_LOAD_FREG_FTN(DT0
, fs
);
5288 gen_op_float_cvtw_d();
5289 GEN_STORE_FTN_FREG(fd
, WT2
);
5293 check_cp1_64bitmode(ctx
);
5294 GEN_LOAD_FREG_FTN(DT0
, fs
);
5295 gen_op_float_cvtl_d();
5296 GEN_STORE_FTN_FREG(fd
, DT2
);
5300 GEN_LOAD_FREG_FTN(WT0
, fs
);
5301 gen_op_float_cvts_w();
5302 GEN_STORE_FTN_FREG(fd
, WT2
);
5306 check_cp1_registers(ctx
, fd
);
5307 GEN_LOAD_FREG_FTN(WT0
, fs
);
5308 gen_op_float_cvtd_w();
5309 GEN_STORE_FTN_FREG(fd
, DT2
);
5313 check_cp1_64bitmode(ctx
);
5314 GEN_LOAD_FREG_FTN(DT0
, fs
);
5315 gen_op_float_cvts_l();
5316 GEN_STORE_FTN_FREG(fd
, WT2
);
5320 check_cp1_64bitmode(ctx
);
5321 GEN_LOAD_FREG_FTN(DT0
, fs
);
5322 gen_op_float_cvtd_l();
5323 GEN_STORE_FTN_FREG(fd
, DT2
);
5328 check_cp1_64bitmode(ctx
);
5329 GEN_LOAD_FREG_FTN(WT0
, fs
);
5330 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5331 gen_op_float_cvtps_pw();
5332 GEN_STORE_FTN_FREG(fd
, WT2
);
5333 GEN_STORE_FTN_FREG(fd
, WTH2
);
5337 check_cp1_64bitmode(ctx
);
5338 GEN_LOAD_FREG_FTN(WT0
, fs
);
5339 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5340 GEN_LOAD_FREG_FTN(WT1
, ft
);
5341 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5342 gen_op_float_add_ps();
5343 GEN_STORE_FTN_FREG(fd
, WT2
);
5344 GEN_STORE_FTN_FREG(fd
, WTH2
);
5348 check_cp1_64bitmode(ctx
);
5349 GEN_LOAD_FREG_FTN(WT0
, fs
);
5350 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5351 GEN_LOAD_FREG_FTN(WT1
, ft
);
5352 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5353 gen_op_float_sub_ps();
5354 GEN_STORE_FTN_FREG(fd
, WT2
);
5355 GEN_STORE_FTN_FREG(fd
, WTH2
);
5359 check_cp1_64bitmode(ctx
);
5360 GEN_LOAD_FREG_FTN(WT0
, fs
);
5361 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5362 GEN_LOAD_FREG_FTN(WT1
, ft
);
5363 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5364 gen_op_float_mul_ps();
5365 GEN_STORE_FTN_FREG(fd
, WT2
);
5366 GEN_STORE_FTN_FREG(fd
, WTH2
);
5370 check_cp1_64bitmode(ctx
);
5371 GEN_LOAD_FREG_FTN(WT0
, fs
);
5372 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5373 gen_op_float_abs_ps();
5374 GEN_STORE_FTN_FREG(fd
, WT2
);
5375 GEN_STORE_FTN_FREG(fd
, WTH2
);
5379 check_cp1_64bitmode(ctx
);
5380 GEN_LOAD_FREG_FTN(WT0
, fs
);
5381 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5382 gen_op_float_mov_ps();
5383 GEN_STORE_FTN_FREG(fd
, WT2
);
5384 GEN_STORE_FTN_FREG(fd
, WTH2
);
5388 check_cp1_64bitmode(ctx
);
5389 GEN_LOAD_FREG_FTN(WT0
, fs
);
5390 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5391 gen_op_float_chs_ps();
5392 GEN_STORE_FTN_FREG(fd
, WT2
);
5393 GEN_STORE_FTN_FREG(fd
, WTH2
);
5397 check_cp1_64bitmode(ctx
);
5398 GEN_LOAD_REG_TN(T0
, ft
);
5399 GEN_LOAD_FREG_FTN(WT0
, fs
);
5400 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5401 GEN_LOAD_FREG_FTN(WT2
, fd
);
5402 GEN_LOAD_FREG_FTN(WTH2
, fd
);
5403 gen_movcf_ps(ctx
, (ft
>> 2) & 0x7, ft
& 0x1);
5404 GEN_STORE_FTN_FREG(fd
, WT2
);
5405 GEN_STORE_FTN_FREG(fd
, WTH2
);
5409 check_cp1_64bitmode(ctx
);
5410 GEN_LOAD_REG_TN(T0
, ft
);
5411 GEN_LOAD_FREG_FTN(WT0
, fs
);
5412 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5413 GEN_LOAD_FREG_FTN(WT2
, fd
);
5414 GEN_LOAD_FREG_FTN(WTH2
, fd
);
5415 gen_op_float_movz_ps();
5416 GEN_STORE_FTN_FREG(fd
, WT2
);
5417 GEN_STORE_FTN_FREG(fd
, WTH2
);
5421 check_cp1_64bitmode(ctx
);
5422 GEN_LOAD_REG_TN(T0
, ft
);
5423 GEN_LOAD_FREG_FTN(WT0
, fs
);
5424 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5425 GEN_LOAD_FREG_FTN(WT2
, fd
);
5426 GEN_LOAD_FREG_FTN(WTH2
, fd
);
5427 gen_op_float_movn_ps();
5428 GEN_STORE_FTN_FREG(fd
, WT2
);
5429 GEN_STORE_FTN_FREG(fd
, WTH2
);
5433 check_cp1_64bitmode(ctx
);
5434 GEN_LOAD_FREG_FTN(WT0
, ft
);
5435 GEN_LOAD_FREG_FTN(WTH0
, ft
);
5436 GEN_LOAD_FREG_FTN(WT1
, fs
);
5437 GEN_LOAD_FREG_FTN(WTH1
, fs
);
5438 gen_op_float_addr_ps();
5439 GEN_STORE_FTN_FREG(fd
, WT2
);
5440 GEN_STORE_FTN_FREG(fd
, WTH2
);
5444 check_cp1_64bitmode(ctx
);
5445 GEN_LOAD_FREG_FTN(WT0
, ft
);
5446 GEN_LOAD_FREG_FTN(WTH0
, ft
);
5447 GEN_LOAD_FREG_FTN(WT1
, fs
);
5448 GEN_LOAD_FREG_FTN(WTH1
, fs
);
5449 gen_op_float_mulr_ps();
5450 GEN_STORE_FTN_FREG(fd
, WT2
);
5451 GEN_STORE_FTN_FREG(fd
, WTH2
);
5455 check_cp1_64bitmode(ctx
);
5456 GEN_LOAD_FREG_FTN(WT0
, fs
);
5457 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5458 GEN_LOAD_FREG_FTN(WT2
, fd
);
5459 GEN_LOAD_FREG_FTN(WTH2
, fd
);
5460 gen_op_float_recip2_ps();
5461 GEN_STORE_FTN_FREG(fd
, WT2
);
5462 GEN_STORE_FTN_FREG(fd
, WTH2
);
5466 check_cp1_64bitmode(ctx
);
5467 GEN_LOAD_FREG_FTN(WT0
, fs
);
5468 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5469 gen_op_float_recip1_ps();
5470 GEN_STORE_FTN_FREG(fd
, WT2
);
5471 GEN_STORE_FTN_FREG(fd
, WTH2
);
5475 check_cp1_64bitmode(ctx
);
5476 GEN_LOAD_FREG_FTN(WT0
, fs
);
5477 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5478 gen_op_float_rsqrt1_ps();
5479 GEN_STORE_FTN_FREG(fd
, WT2
);
5480 GEN_STORE_FTN_FREG(fd
, WTH2
);
5484 check_cp1_64bitmode(ctx
);
5485 GEN_LOAD_FREG_FTN(WT0
, fs
);
5486 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5487 GEN_LOAD_FREG_FTN(WT2
, ft
);
5488 GEN_LOAD_FREG_FTN(WTH2
, ft
);
5489 gen_op_float_rsqrt2_ps();
5490 GEN_STORE_FTN_FREG(fd
, WT2
);
5491 GEN_STORE_FTN_FREG(fd
, WTH2
);
5495 check_cp1_64bitmode(ctx
);
5496 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5497 gen_op_float_cvts_pu();
5498 GEN_STORE_FTN_FREG(fd
, WT2
);
5502 check_cp1_64bitmode(ctx
);
5503 GEN_LOAD_FREG_FTN(WT0
, fs
);
5504 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5505 gen_op_float_cvtpw_ps();
5506 GEN_STORE_FTN_FREG(fd
, WT2
);
5507 GEN_STORE_FTN_FREG(fd
, WTH2
);
5511 check_cp1_64bitmode(ctx
);
5512 GEN_LOAD_FREG_FTN(WT0
, fs
);
5513 gen_op_float_cvts_pl();
5514 GEN_STORE_FTN_FREG(fd
, WT2
);
5518 check_cp1_64bitmode(ctx
);
5519 GEN_LOAD_FREG_FTN(WT0
, fs
);
5520 GEN_LOAD_FREG_FTN(WT1
, ft
);
5521 gen_op_float_pll_ps();
5522 GEN_STORE_FTN_FREG(fd
, DT2
);
5526 check_cp1_64bitmode(ctx
);
5527 GEN_LOAD_FREG_FTN(WT0
, fs
);
5528 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5529 gen_op_float_plu_ps();
5530 GEN_STORE_FTN_FREG(fd
, DT2
);
5534 check_cp1_64bitmode(ctx
);
5535 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5536 GEN_LOAD_FREG_FTN(WT1
, ft
);
5537 gen_op_float_pul_ps();
5538 GEN_STORE_FTN_FREG(fd
, DT2
);
5542 check_cp1_64bitmode(ctx
);
5543 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5544 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5545 gen_op_float_puu_ps();
5546 GEN_STORE_FTN_FREG(fd
, DT2
);
5565 check_cp1_64bitmode(ctx
);
5566 GEN_LOAD_FREG_FTN(WT0
, fs
);
5567 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5568 GEN_LOAD_FREG_FTN(WT1
, ft
);
5569 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5570 if (ctx
->opcode
& (1 << 6)) {
5571 gen_cmpabs_ps(func
-48, cc
);
5572 opn
= condnames_abs
[func
-48];
5574 gen_cmp_ps(func
-48, cc
);
5575 opn
= condnames
[func
-48];
5580 generate_exception (ctx
, EXCP_RI
);
5585 MIPS_DEBUG("%s %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fs
], fregnames
[ft
]);
5588 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fs
], fregnames
[ft
]);
5591 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fd
], fregnames
[fs
]);
5596 /* Coprocessor 3 (FPU) */
5597 static void gen_flt3_ldst (DisasContext
*ctx
, uint32_t opc
,
5598 int fd
, int fs
, int base
, int index
)
5600 const char *opn
= "extended float load/store";
5603 /* All of those work only on 64bit FPUs. */
5604 check_cp1_64bitmode(ctx
);
5609 GEN_LOAD_REG_TN(T0
, index
);
5610 } else if (index
== 0) {
5611 GEN_LOAD_REG_TN(T0
, base
);
5613 GEN_LOAD_REG_TN(T0
, base
);
5614 GEN_LOAD_REG_TN(T1
, index
);
5617 /* Don't do NOP if destination is zero: we must perform the actual
5622 GEN_STORE_FTN_FREG(fd
, WT0
);
5627 GEN_STORE_FTN_FREG(fd
, DT0
);
5632 GEN_STORE_FTN_FREG(fd
, DT0
);
5636 GEN_LOAD_FREG_FTN(WT0
, fs
);
5642 GEN_LOAD_FREG_FTN(DT0
, fs
);
5648 GEN_LOAD_FREG_FTN(DT0
, fs
);
5655 generate_exception(ctx
, EXCP_RI
);
5658 MIPS_DEBUG("%s %s, %s(%s)", opn
, fregnames
[store
? fs
: fd
],
5659 regnames
[index
], regnames
[base
]);
5662 static void gen_flt3_arith (DisasContext
*ctx
, uint32_t opc
,
5663 int fd
, int fr
, int fs
, int ft
)
5665 const char *opn
= "flt3_arith";
5667 /* All of those work only on 64bit FPUs. */
5668 check_cp1_64bitmode(ctx
);
5671 GEN_LOAD_REG_TN(T0
, fr
);
5672 GEN_LOAD_FREG_FTN(DT0
, fs
);
5673 GEN_LOAD_FREG_FTN(DT1
, ft
);
5674 gen_op_float_alnv_ps();
5675 GEN_STORE_FTN_FREG(fd
, DT2
);
5679 GEN_LOAD_FREG_FTN(WT0
, fs
);
5680 GEN_LOAD_FREG_FTN(WT1
, ft
);
5681 GEN_LOAD_FREG_FTN(WT2
, fr
);
5682 gen_op_float_muladd_s();
5683 GEN_STORE_FTN_FREG(fd
, WT2
);
5687 GEN_LOAD_FREG_FTN(DT0
, fs
);
5688 GEN_LOAD_FREG_FTN(DT1
, ft
);
5689 GEN_LOAD_FREG_FTN(DT2
, fr
);
5690 gen_op_float_muladd_d();
5691 GEN_STORE_FTN_FREG(fd
, DT2
);
5695 GEN_LOAD_FREG_FTN(WT0
, fs
);
5696 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5697 GEN_LOAD_FREG_FTN(WT1
, ft
);
5698 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5699 GEN_LOAD_FREG_FTN(WT2
, fr
);
5700 GEN_LOAD_FREG_FTN(WTH2
, fr
);
5701 gen_op_float_muladd_ps();
5702 GEN_STORE_FTN_FREG(fd
, WT2
);
5703 GEN_STORE_FTN_FREG(fd
, WTH2
);
5707 GEN_LOAD_FREG_FTN(WT0
, fs
);
5708 GEN_LOAD_FREG_FTN(WT1
, ft
);
5709 GEN_LOAD_FREG_FTN(WT2
, fr
);
5710 gen_op_float_mulsub_s();
5711 GEN_STORE_FTN_FREG(fd
, WT2
);
5715 GEN_LOAD_FREG_FTN(DT0
, fs
);
5716 GEN_LOAD_FREG_FTN(DT1
, ft
);
5717 GEN_LOAD_FREG_FTN(DT2
, fr
);
5718 gen_op_float_mulsub_d();
5719 GEN_STORE_FTN_FREG(fd
, DT2
);
5723 GEN_LOAD_FREG_FTN(WT0
, fs
);
5724 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5725 GEN_LOAD_FREG_FTN(WT1
, ft
);
5726 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5727 GEN_LOAD_FREG_FTN(WT2
, fr
);
5728 GEN_LOAD_FREG_FTN(WTH2
, fr
);
5729 gen_op_float_mulsub_ps();
5730 GEN_STORE_FTN_FREG(fd
, WT2
);
5731 GEN_STORE_FTN_FREG(fd
, WTH2
);
5735 GEN_LOAD_FREG_FTN(WT0
, fs
);
5736 GEN_LOAD_FREG_FTN(WT1
, ft
);
5737 GEN_LOAD_FREG_FTN(WT2
, fr
);
5738 gen_op_float_nmuladd_s();
5739 GEN_STORE_FTN_FREG(fd
, WT2
);
5743 GEN_LOAD_FREG_FTN(DT0
, fs
);
5744 GEN_LOAD_FREG_FTN(DT1
, ft
);
5745 GEN_LOAD_FREG_FTN(DT2
, fr
);
5746 gen_op_float_nmuladd_d();
5747 GEN_STORE_FTN_FREG(fd
, DT2
);
5751 GEN_LOAD_FREG_FTN(WT0
, fs
);
5752 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5753 GEN_LOAD_FREG_FTN(WT1
, ft
);
5754 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5755 GEN_LOAD_FREG_FTN(WT2
, fr
);
5756 GEN_LOAD_FREG_FTN(WTH2
, fr
);
5757 gen_op_float_nmuladd_ps();
5758 GEN_STORE_FTN_FREG(fd
, WT2
);
5759 GEN_STORE_FTN_FREG(fd
, WTH2
);
5763 GEN_LOAD_FREG_FTN(WT0
, fs
);
5764 GEN_LOAD_FREG_FTN(WT1
, ft
);
5765 GEN_LOAD_FREG_FTN(WT2
, fr
);
5766 gen_op_float_nmulsub_s();
5767 GEN_STORE_FTN_FREG(fd
, WT2
);
5771 GEN_LOAD_FREG_FTN(DT0
, fs
);
5772 GEN_LOAD_FREG_FTN(DT1
, ft
);
5773 GEN_LOAD_FREG_FTN(DT2
, fr
);
5774 gen_op_float_nmulsub_d();
5775 GEN_STORE_FTN_FREG(fd
, DT2
);
5779 GEN_LOAD_FREG_FTN(WT0
, fs
);
5780 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5781 GEN_LOAD_FREG_FTN(WT1
, ft
);
5782 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5783 GEN_LOAD_FREG_FTN(WT2
, fr
);
5784 GEN_LOAD_FREG_FTN(WTH2
, fr
);
5785 gen_op_float_nmulsub_ps();
5786 GEN_STORE_FTN_FREG(fd
, WT2
);
5787 GEN_STORE_FTN_FREG(fd
, WTH2
);
5792 generate_exception (ctx
, EXCP_RI
);
5795 MIPS_DEBUG("%s %s, %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fr
],
5796 fregnames
[fs
], fregnames
[ft
]);
5799 /* ISA extensions (ASEs) */
5800 /* MIPS16 extension to MIPS32 */
5801 /* SmartMIPS extension to MIPS32 */
5803 #ifdef TARGET_MIPS64
5805 /* MDMX extension to MIPS64 */
5806 /* MIPS-3D extension to MIPS64 */
5810 static void decode_opc (CPUState
*env
, DisasContext
*ctx
)
5814 uint32_t op
, op1
, op2
;
5817 /* make sure instructions are on a word boundary */
5818 if (ctx
->pc
& 0x3) {
5819 env
->CP0_BadVAddr
= ctx
->pc
;
5820 generate_exception(ctx
, EXCP_AdEL
);
5824 if ((ctx
->hflags
& MIPS_HFLAG_BMASK
) == MIPS_HFLAG_BL
) {
5826 /* Handle blikely not taken case */
5827 MIPS_DEBUG("blikely condition (" TARGET_FMT_lx
")", ctx
->pc
+ 4);
5828 l1
= gen_new_label();
5830 gen_op_save_state(ctx
->hflags
& ~MIPS_HFLAG_BMASK
);
5831 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
5834 op
= MASK_OP_MAJOR(ctx
->opcode
);
5835 rs
= (ctx
->opcode
>> 21) & 0x1f;
5836 rt
= (ctx
->opcode
>> 16) & 0x1f;
5837 rd
= (ctx
->opcode
>> 11) & 0x1f;
5838 sa
= (ctx
->opcode
>> 6) & 0x1f;
5839 imm
= (int16_t)ctx
->opcode
;
5842 op1
= MASK_SPECIAL(ctx
->opcode
);
5844 case OPC_SLL
: /* Arithmetic with immediate */
5845 case OPC_SRL
... OPC_SRA
:
5846 gen_arith_imm(ctx
, op1
, rd
, rt
, sa
);
5848 case OPC_SLLV
: /* Arithmetic */
5849 case OPC_SRLV
... OPC_SRAV
:
5850 case OPC_MOVZ
... OPC_MOVN
:
5851 case OPC_ADD
... OPC_NOR
:
5852 case OPC_SLT
... OPC_SLTU
:
5853 gen_arith(ctx
, op1
, rd
, rs
, rt
);
5855 case OPC_MULT
... OPC_DIVU
:
5856 gen_muldiv(ctx
, op1
, rs
, rt
);
5858 case OPC_JR
... OPC_JALR
:
5859 gen_compute_branch(ctx
, op1
, rs
, rd
, sa
);
5861 case OPC_TGE
... OPC_TEQ
: /* Traps */
5863 gen_trap(ctx
, op1
, rs
, rt
, -1);
5865 case OPC_MFHI
: /* Move from HI/LO */
5867 gen_HILO(ctx
, op1
, rd
);
5870 case OPC_MTLO
: /* Move to HI/LO */
5871 gen_HILO(ctx
, op1
, rs
);
5873 case OPC_PMON
: /* Pmon entry point, also R4010 selsl */
5874 #ifdef MIPS_STRICT_STANDARD
5875 MIPS_INVAL("PMON / selsl");
5876 generate_exception(ctx
, EXCP_RI
);
5882 generate_exception(ctx
, EXCP_SYSCALL
);
5885 /* XXX: Hack to work around wrong handling of self-modifying code. */
5887 save_cpu_state(ctx
, 1);
5889 generate_exception(ctx
, EXCP_BREAK
);
5892 #ifdef MIPS_STRICT_STANDARD
5894 generate_exception(ctx
, EXCP_RI
);
5896 /* Implemented as RI exception for now. */
5897 MIPS_INVAL("spim (unofficial)");
5898 generate_exception(ctx
, EXCP_RI
);
5906 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
5907 save_cpu_state(ctx
, 1);
5908 check_cp1_enabled(ctx
);
5909 gen_movci(ctx
, rd
, rs
, (ctx
->opcode
>> 18) & 0x7,
5910 (ctx
->opcode
>> 16) & 1);
5912 generate_exception_err(ctx
, EXCP_CpU
, 1);
5916 #ifdef TARGET_MIPS64
5917 /* MIPS64 specific opcodes */
5919 case OPC_DSRL
... OPC_DSRA
:
5921 case OPC_DSRL32
... OPC_DSRA32
:
5922 if (!(ctx
->hflags
& MIPS_HFLAG_64
))
5923 generate_exception(ctx
, EXCP_RI
);
5924 gen_arith_imm(ctx
, op1
, rd
, rt
, sa
);
5927 case OPC_DSRLV
... OPC_DSRAV
:
5928 case OPC_DADD
... OPC_DSUBU
:
5929 if (!(ctx
->hflags
& MIPS_HFLAG_64
))
5930 generate_exception(ctx
, EXCP_RI
);
5931 gen_arith(ctx
, op1
, rd
, rs
, rt
);
5933 case OPC_DMULT
... OPC_DDIVU
:
5934 if (!(ctx
->hflags
& MIPS_HFLAG_64
))
5935 generate_exception(ctx
, EXCP_RI
);
5936 gen_muldiv(ctx
, op1
, rs
, rt
);
5939 default: /* Invalid */
5940 MIPS_INVAL("special");
5941 generate_exception(ctx
, EXCP_RI
);
5946 op1
= MASK_SPECIAL2(ctx
->opcode
);
5948 case OPC_MADD
... OPC_MADDU
: /* Multiply and add/sub */
5949 case OPC_MSUB
... OPC_MSUBU
:
5950 gen_muldiv(ctx
, op1
, rs
, rt
);
5953 gen_arith(ctx
, op1
, rd
, rs
, rt
);
5955 case OPC_CLZ
... OPC_CLO
:
5956 gen_cl(ctx
, op1
, rd
, rs
);
5959 /* XXX: not clear which exception should be raised
5960 * when in debug mode...
5962 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
5963 generate_exception(ctx
, EXCP_DBp
);
5965 generate_exception(ctx
, EXCP_DBp
);
5969 #ifdef TARGET_MIPS64
5970 case OPC_DCLZ
... OPC_DCLO
:
5971 if (!(ctx
->hflags
& MIPS_HFLAG_64
))
5972 generate_exception(ctx
, EXCP_RI
);
5973 gen_cl(ctx
, op1
, rd
, rs
);
5976 default: /* Invalid */
5977 MIPS_INVAL("special2");
5978 generate_exception(ctx
, EXCP_RI
);
5983 check_mips_r2(env
, ctx
);
5984 op1
= MASK_SPECIAL3(ctx
->opcode
);
5988 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
5991 op2
= MASK_BSHFL(ctx
->opcode
);
5994 GEN_LOAD_REG_TN(T1
, rt
);
5998 GEN_LOAD_REG_TN(T1
, rt
);
6002 GEN_LOAD_REG_TN(T1
, rt
);
6005 default: /* Invalid */
6006 MIPS_INVAL("bshfl");
6007 generate_exception(ctx
, EXCP_RI
);
6010 GEN_STORE_TN_REG(rd
, T0
);
6015 save_cpu_state(ctx
, 1);
6016 gen_op_rdhwr_cpunum();
6019 save_cpu_state(ctx
, 1);
6020 gen_op_rdhwr_synci_step();
6023 save_cpu_state(ctx
, 1);
6027 save_cpu_state(ctx
, 1);
6028 gen_op_rdhwr_ccres();
6031 #if defined (CONFIG_USER_ONLY)
6035 default: /* Invalid */
6036 MIPS_INVAL("rdhwr");
6037 generate_exception(ctx
, EXCP_RI
);
6040 GEN_STORE_TN_REG(rt
, T0
);
6043 check_mips_mt(env
, ctx
);
6044 GEN_LOAD_REG_TN(T0
, rt
);
6045 GEN_LOAD_REG_TN(T1
, rs
);
6049 check_mips_mt(env
, ctx
);
6050 GEN_LOAD_REG_TN(T0
, rs
);
6052 GEN_STORE_TN_REG(rd
, T0
);
6054 #ifdef TARGET_MIPS64
6055 case OPC_DEXTM
... OPC_DEXT
:
6056 case OPC_DINSM
... OPC_DINS
:
6057 if (!(ctx
->hflags
& MIPS_HFLAG_64
))
6058 generate_exception(ctx
, EXCP_RI
);
6059 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
6062 if (!(ctx
->hflags
& MIPS_HFLAG_64
))
6063 generate_exception(ctx
, EXCP_RI
);
6064 op2
= MASK_DBSHFL(ctx
->opcode
);
6067 GEN_LOAD_REG_TN(T1
, rt
);
6071 GEN_LOAD_REG_TN(T1
, rt
);
6074 default: /* Invalid */
6075 MIPS_INVAL("dbshfl");
6076 generate_exception(ctx
, EXCP_RI
);
6079 GEN_STORE_TN_REG(rd
, T0
);
6081 default: /* Invalid */
6082 MIPS_INVAL("special3");
6083 generate_exception(ctx
, EXCP_RI
);
6088 op1
= MASK_REGIMM(ctx
->opcode
);
6090 case OPC_BLTZ
... OPC_BGEZL
: /* REGIMM branches */
6091 case OPC_BLTZAL
... OPC_BGEZALL
:
6092 gen_compute_branch(ctx
, op1
, rs
, -1, imm
<< 2);
6094 case OPC_TGEI
... OPC_TEQI
: /* REGIMM traps */
6096 gen_trap(ctx
, op1
, rs
, -1, imm
);
6099 check_mips_r2(env
, ctx
);
6102 default: /* Invalid */
6103 MIPS_INVAL("regimm");
6104 generate_exception(ctx
, EXCP_RI
);
6109 save_cpu_state(ctx
, 1);
6110 gen_op_cp0_enabled();
6111 op1
= MASK_CP0(ctx
->opcode
);
6117 #ifdef TARGET_MIPS64
6121 gen_cp0(env
, ctx
, op1
, rt
, rd
);
6123 case OPC_C0_FIRST
... OPC_C0_LAST
:
6124 gen_cp0(env
, ctx
, MASK_C0(ctx
->opcode
), rt
, rd
);
6127 check_mips_r2(env
, ctx
);
6128 op2
= MASK_MFMC0(ctx
->opcode
);
6131 check_mips_mt(env
, ctx
);
6135 check_mips_mt(env
, ctx
);
6139 check_mips_mt(env
, ctx
);
6143 check_mips_mt(env
, ctx
);
6148 /* Stop translation as we may have switched the execution mode */
6149 ctx
->bstate
= BS_STOP
;
6153 /* Stop translation as we may have switched the execution mode */
6154 ctx
->bstate
= BS_STOP
;
6156 default: /* Invalid */
6157 MIPS_INVAL("mfmc0");
6158 generate_exception(ctx
, EXCP_RI
);
6161 GEN_STORE_TN_REG(rt
, T0
);
6164 check_mips_r2(env
, ctx
);
6165 GEN_LOAD_SRSREG_TN(T0
, rt
);
6166 GEN_STORE_TN_REG(rd
, T0
);
6169 check_mips_r2(env
, ctx
);
6170 GEN_LOAD_REG_TN(T0
, rt
);
6171 GEN_STORE_TN_SRSREG(rd
, T0
);
6175 generate_exception(ctx
, EXCP_RI
);
6179 case OPC_ADDI
... OPC_LUI
: /* Arithmetic with immediate opcode */
6180 gen_arith_imm(ctx
, op
, rt
, rs
, imm
);
6182 case OPC_J
... OPC_JAL
: /* Jump */
6183 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 2;
6184 gen_compute_branch(ctx
, op
, rs
, rt
, offset
);
6186 case OPC_BEQ
... OPC_BGTZ
: /* Branch */
6187 case OPC_BEQL
... OPC_BGTZL
:
6188 gen_compute_branch(ctx
, op
, rs
, rt
, imm
<< 2);
6190 case OPC_LB
... OPC_LWR
: /* Load and stores */
6191 case OPC_SB
... OPC_SW
:
6195 gen_ldst(ctx
, op
, rt
, rs
, imm
);
6204 /* Floating point (COP1). */
6209 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
6210 save_cpu_state(ctx
, 1);
6211 check_cp1_enabled(ctx
);
6212 gen_flt_ldst(ctx
, op
, rt
, rs
, imm
);
6214 generate_exception_err(ctx
, EXCP_CpU
, 1);
6219 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
6220 save_cpu_state(ctx
, 1);
6221 check_cp1_enabled(ctx
);
6222 op1
= MASK_CP1(ctx
->opcode
);
6226 check_mips_r2(env
, ctx
);
6231 #ifdef TARGET_MIPS64
6235 gen_cp1(ctx
, op1
, rt
, rd
);
6240 gen_compute_branch1(ctx
, MASK_BC1(ctx
->opcode
),
6241 (rt
>> 2) & 0x7, imm
<< 2);
6248 gen_farith(ctx
, MASK_CP1_FUNC(ctx
->opcode
), rt
, rd
, sa
,
6253 generate_exception (ctx
, EXCP_RI
);
6257 generate_exception_err(ctx
, EXCP_CpU
, 1);
6267 /* COP2: Not implemented. */
6268 generate_exception_err(ctx
, EXCP_CpU
, 2);
6272 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
6273 save_cpu_state(ctx
, 1);
6274 check_cp1_enabled(ctx
);
6275 op1
= MASK_CP3(ctx
->opcode
);
6283 gen_flt3_ldst(ctx
, op1
, sa
, rd
, rs
, rt
);
6301 gen_flt3_arith(ctx
, op1
, sa
, rs
, rd
, rt
);
6305 generate_exception (ctx
, EXCP_RI
);
6309 generate_exception_err(ctx
, EXCP_CpU
, 1);
6313 #ifdef TARGET_MIPS64
6314 /* MIPS64 opcodes */
6316 case OPC_LDL
... OPC_LDR
:
6317 case OPC_SDL
... OPC_SDR
:
6322 if (!(ctx
->hflags
& MIPS_HFLAG_64
))
6323 generate_exception(ctx
, EXCP_RI
);
6324 gen_ldst(ctx
, op
, rt
, rs
, imm
);
6326 case OPC_DADDI
... OPC_DADDIU
:
6327 if (!(ctx
->hflags
& MIPS_HFLAG_64
))
6328 generate_exception(ctx
, EXCP_RI
);
6329 gen_arith_imm(ctx
, op
, rt
, rs
, imm
);
6332 #ifdef MIPS_HAS_MIPS16
6334 /* MIPS16: Not implemented. */
6336 #ifdef MIPS_HAS_MDMX
6338 /* MDMX: Not implemented. */
6340 default: /* Invalid */
6341 MIPS_INVAL("major opcode");
6342 generate_exception(ctx
, EXCP_RI
);
6345 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
6346 int hflags
= ctx
->hflags
& MIPS_HFLAG_BMASK
;
6347 /* Branches completion */
6348 ctx
->hflags
&= ~MIPS_HFLAG_BMASK
;
6349 ctx
->bstate
= BS_BRANCH
;
6350 save_cpu_state(ctx
, 0);
6353 /* unconditional branch */
6354 MIPS_DEBUG("unconditional branch");
6355 gen_goto_tb(ctx
, 0, ctx
->btarget
);
6358 /* blikely taken case */
6359 MIPS_DEBUG("blikely branch taken");
6360 gen_goto_tb(ctx
, 0, ctx
->btarget
);
6363 /* Conditional branch */
6364 MIPS_DEBUG("conditional branch");
6367 l1
= gen_new_label();
6369 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
6371 gen_goto_tb(ctx
, 0, ctx
->btarget
);
6375 /* unconditional branch to register */
6376 MIPS_DEBUG("branch to register");
6382 MIPS_DEBUG("unknown branch");
6389 gen_intermediate_code_internal (CPUState
*env
, TranslationBlock
*tb
,
6393 target_ulong pc_start
;
6394 uint16_t *gen_opc_end
;
6397 if (search_pc
&& loglevel
)
6398 fprintf (logfile
, "search pc %d\n", search_pc
);
6401 gen_opc_ptr
= gen_opc_buf
;
6402 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
6403 gen_opparam_ptr
= gen_opparam_buf
;
6408 ctx
.bstate
= BS_NONE
;
6409 /* Restore delay slot state from the tb context. */
6410 ctx
.hflags
= tb
->flags
;
6411 restore_cpu_state(env
, &ctx
);
6412 #if defined(CONFIG_USER_ONLY)
6415 ctx
.mem_idx
= !((ctx
.hflags
& MIPS_HFLAG_MODE
) == MIPS_HFLAG_UM
);
6418 if (loglevel
& CPU_LOG_TB_CPU
) {
6419 fprintf(logfile
, "------------------------------------------------\n");
6420 /* FIXME: This may print out stale hflags from env... */
6421 cpu_dump_state(env
, logfile
, fprintf
, 0);
6424 #ifdef MIPS_DEBUG_DISAS
6425 if (loglevel
& CPU_LOG_TB_IN_ASM
)
6426 fprintf(logfile
, "\ntb %p super %d cond %04x\n",
6427 tb
, ctx
.mem_idx
, ctx
.hflags
);
6429 while (ctx
.bstate
== BS_NONE
&& gen_opc_ptr
< gen_opc_end
) {
6430 if (env
->nb_breakpoints
> 0) {
6431 for(j
= 0; j
< env
->nb_breakpoints
; j
++) {
6432 if (env
->breakpoints
[j
] == ctx
.pc
) {
6433 save_cpu_state(&ctx
, 1);
6434 ctx
.bstate
= BS_BRANCH
;
6436 goto done_generating
;
6442 j
= gen_opc_ptr
- gen_opc_buf
;
6446 gen_opc_instr_start
[lj
++] = 0;
6448 gen_opc_pc
[lj
] = ctx
.pc
;
6449 gen_opc_hflags
[lj
] = ctx
.hflags
& MIPS_HFLAG_BMASK
;
6450 gen_opc_instr_start
[lj
] = 1;
6452 ctx
.opcode
= ldl_code(ctx
.pc
);
6453 decode_opc(env
, &ctx
);
6456 if (env
->singlestep_enabled
)
6459 if ((ctx
.pc
& (TARGET_PAGE_SIZE
- 1)) == 0)
6462 #if defined (MIPS_SINGLE_STEP)
6466 if (env
->singlestep_enabled
) {
6467 save_cpu_state(&ctx
, ctx
.bstate
== BS_NONE
);
6470 switch (ctx
.bstate
) {
6472 gen_op_interrupt_restart();
6473 gen_goto_tb(&ctx
, 0, ctx
.pc
);
6476 save_cpu_state(&ctx
, 0);
6477 gen_goto_tb(&ctx
, 0, ctx
.pc
);
6480 gen_op_interrupt_restart();
6490 *gen_opc_ptr
= INDEX_op_end
;
6492 j
= gen_opc_ptr
- gen_opc_buf
;
6495 gen_opc_instr_start
[lj
++] = 0;
6498 tb
->size
= ctx
.pc
- pc_start
;
6501 #if defined MIPS_DEBUG_DISAS
6502 if (loglevel
& CPU_LOG_TB_IN_ASM
)
6503 fprintf(logfile
, "\n");
6505 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
6506 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
6507 target_disas(logfile
, pc_start
, ctx
.pc
- pc_start
, 0);
6508 fprintf(logfile
, "\n");
6510 if (loglevel
& CPU_LOG_TB_OP
) {
6511 fprintf(logfile
, "OP:\n");
6512 dump_ops(gen_opc_buf
, gen_opparam_buf
);
6513 fprintf(logfile
, "\n");
6515 if (loglevel
& CPU_LOG_TB_CPU
) {
6516 fprintf(logfile
, "---------------- %d %08x\n", ctx
.bstate
, ctx
.hflags
);
6523 int gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
6525 return gen_intermediate_code_internal(env
, tb
, 0);
6528 int gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
6530 return gen_intermediate_code_internal(env
, tb
, 1);
6533 void fpu_dump_state(CPUState
*env
, FILE *f
,
6534 int (*fpu_fprintf
)(FILE *f
, const char *fmt
, ...),
6538 int is_fpu64
= !!(env
->hflags
& MIPS_HFLAG_F64
);
6540 #define printfpr(fp) \
6543 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu: %13g\n", \
6544 (fp)->w[FP_ENDIAN_IDX], (fp)->d, (fp)->fd, \
6545 (fp)->fs[FP_ENDIAN_IDX], (fp)->fs[!FP_ENDIAN_IDX]); \
6548 tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \
6549 tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \
6550 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu:%13g\n", \
6551 tmp.w[FP_ENDIAN_IDX], tmp.d, tmp.fd, \
6552 tmp.fs[FP_ENDIAN_IDX], tmp.fs[!FP_ENDIAN_IDX]); \
6557 fpu_fprintf(f
, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n",
6558 env
->fpu
->fcr0
, env
->fpu
->fcr31
, is_fpu64
, env
->fpu
->fp_status
,
6559 get_float_exception_flags(&env
->fpu
->fp_status
));
6560 fpu_fprintf(f
, "FT0: "); printfpr(&env
->fpu
->ft0
);
6561 fpu_fprintf(f
, "FT1: "); printfpr(&env
->fpu
->ft1
);
6562 fpu_fprintf(f
, "FT2: "); printfpr(&env
->fpu
->ft2
);
6563 for (i
= 0; i
< 32; (is_fpu64
) ? i
++ : (i
+= 2)) {
6564 fpu_fprintf(f
, "%3s: ", fregnames
[i
]);
6565 printfpr(&env
->fpu
->fpr
[i
]);
6571 void dump_fpu (CPUState
*env
)
6574 fprintf(logfile
, "pc=0x" TARGET_FMT_lx
" HI=0x" TARGET_FMT_lx
" LO=0x" TARGET_FMT_lx
" ds %04x " TARGET_FMT_lx
" %d\n",
6575 env
->PC
[env
->current_tc
], env
->HI
[0][env
->current_tc
], env
->LO
[0][env
->current_tc
], env
->hflags
, env
->btarget
, env
->bcond
);
6576 fpu_dump_state(env
, logfile
, fprintf
, 0);
6580 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
6581 /* Debug help: The architecture requires 32bit code to maintain proper
6582 sign-extened values on 64bit machines. */
6584 #define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff))
6586 void cpu_mips_check_sign_extensions (CPUState
*env
, FILE *f
,
6587 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
6592 if (!SIGN_EXT_P(env
->PC
[env
->current_tc
]))
6593 cpu_fprintf(f
, "BROKEN: pc=0x" TARGET_FMT_lx
"\n", env
->PC
[env
->current_tc
]);
6594 if (!SIGN_EXT_P(env
->HI
[env
->current_tc
]))
6595 cpu_fprintf(f
, "BROKEN: HI=0x" TARGET_FMT_lx
"\n", env
->HI
[env
->current_tc
]);
6596 if (!SIGN_EXT_P(env
->LO
[env
->current_tc
]))
6597 cpu_fprintf(f
, "BROKEN: LO=0x" TARGET_FMT_lx
"\n", env
->LO
[env
->current_tc
]);
6598 if (!SIGN_EXT_P(env
->btarget
))
6599 cpu_fprintf(f
, "BROKEN: btarget=0x" TARGET_FMT_lx
"\n", env
->btarget
);
6601 for (i
= 0; i
< 32; i
++) {
6602 if (!SIGN_EXT_P(env
->gpr
[i
][env
->current_tc
]))
6603 cpu_fprintf(f
, "BROKEN: %s=0x" TARGET_FMT_lx
"\n", regnames
[i
], env
->gpr
[i
][env
->current_tc
]);
6606 if (!SIGN_EXT_P(env
->CP0_EPC
))
6607 cpu_fprintf(f
, "BROKEN: EPC=0x" TARGET_FMT_lx
"\n", env
->CP0_EPC
);
6608 if (!SIGN_EXT_P(env
->CP0_LLAddr
))
6609 cpu_fprintf(f
, "BROKEN: LLAddr=0x" TARGET_FMT_lx
"\n", env
->CP0_LLAddr
);
6613 void cpu_dump_state (CPUState
*env
, FILE *f
,
6614 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
6619 cpu_fprintf(f
, "pc=0x" TARGET_FMT_lx
" HI=0x" TARGET_FMT_lx
" LO=0x" TARGET_FMT_lx
" ds %04x " TARGET_FMT_lx
" %d\n",
6620 env
->PC
[env
->current_tc
], env
->HI
[env
->current_tc
], env
->LO
[env
->current_tc
], env
->hflags
, env
->btarget
, env
->bcond
);
6621 for (i
= 0; i
< 32; i
++) {
6623 cpu_fprintf(f
, "GPR%02d:", i
);
6624 cpu_fprintf(f
, " %s " TARGET_FMT_lx
, regnames
[i
], env
->gpr
[i
][env
->current_tc
]);
6626 cpu_fprintf(f
, "\n");
6629 cpu_fprintf(f
, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx
"\n",
6630 env
->CP0_Status
, env
->CP0_Cause
, env
->CP0_EPC
);
6631 cpu_fprintf(f
, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx
"\n",
6632 env
->CP0_Config0
, env
->CP0_Config1
, env
->CP0_LLAddr
);
6633 if (env
->hflags
& MIPS_HFLAG_FPU
)
6634 fpu_dump_state(env
, f
, cpu_fprintf
, flags
);
6635 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
6636 cpu_mips_check_sign_extensions(env
, f
, cpu_fprintf
, flags
);
6640 CPUMIPSState
*cpu_mips_init (void)
6644 env
= qemu_mallocz(sizeof(CPUMIPSState
));
6652 void cpu_reset (CPUMIPSState
*env
)
6654 memset(env
, 0, offsetof(CPUMIPSState
, breakpoints
));
6659 #if !defined(CONFIG_USER_ONLY)
6660 if (env
->hflags
& MIPS_HFLAG_BMASK
) {
6661 /* If the exception was raised from a delay slot,
6662 * come back to the jump. */
6663 env
->CP0_ErrorEPC
= env
->PC
[env
->current_tc
] - 4;
6665 env
->CP0_ErrorEPC
= env
->PC
[env
->current_tc
];
6668 env
->PC
[env
->current_tc
] = (int32_t)0xBFC00000;
6670 /* SMP not implemented */
6671 env
->CP0_EBase
= 0x80000000;
6672 env
->CP0_Status
= (1 << CP0St_BEV
) | (1 << CP0St_ERL
);
6673 /* vectored interrupts not implemented, timer on int 7,
6674 no performance counters. */
6675 env
->CP0_IntCtl
= 0xe0000000;
6679 for (i
= 0; i
< 7; i
++) {
6680 env
->CP0_WatchLo
[i
] = 0;
6681 env
->CP0_WatchHi
[i
] = 0x80000000;
6683 env
->CP0_WatchLo
[7] = 0;
6684 env
->CP0_WatchHi
[7] = 0;
6686 /* Count register increments in debug mode, EJTAG version 1 */
6687 env
->CP0_Debug
= (1 << CP0DB_CNT
) | (0x1 << CP0DB_VER
);
6689 env
->exception_index
= EXCP_NONE
;
6690 #if defined(CONFIG_USER_ONLY)
6691 env
->hflags
|= MIPS_HFLAG_UM
;
6692 env
->user_mode_only
= 1;
6696 #include "translate_init.c"