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PowerPC MMU and exception fixes:
[qemu.git] / target-ppc / exec.h
1 /*
2 * PowerPC emulation definitions for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #if !defined (__PPC_H__)
21 #define __PPC_H__
22
23 #include "config.h"
24
25 #include "dyngen-exec.h"
26
27 #include "cpu.h"
28 #include "exec-all.h"
29
30 /* For normal operations, precise emulation should not be needed */
31 //#define USE_PRECISE_EMULATION 1
32 #define USE_PRECISE_EMULATION 0
33
34 register struct CPUPPCState *env asm(AREG0);
35 #if TARGET_LONG_BITS > HOST_LONG_BITS
36 /* no registers can be used */
37 #define T0 (env->t0)
38 #define T1 (env->t1)
39 #define T2 (env->t2)
40 #else
41 register unsigned long T0 asm(AREG1);
42 register unsigned long T1 asm(AREG2);
43 register unsigned long T2 asm(AREG3);
44 #endif
45 /* We may, sometime, need 64 bits registers on 32 bits target */
46 #if TARGET_GPR_BITS > HOST_LONG_BITS
47 /* no registers can be used */
48 #define T0_64 (env->t0)
49 #define T1_64 (env->t1)
50 #define T2_64 (env->t2)
51 #else
52 #define T0_64 T0
53 #define T1_64 T1
54 #define T2_64 T2
55 #endif
56 /* Provision for Altivec */
57 #define AVR0 (env->avr0)
58 #define AVR1 (env->avr1)
59 #define AVR2 (env->avr2)
60
61 #define FT0 (env->ft0)
62 #define FT1 (env->ft1)
63 #define FT2 (env->ft2)
64
65 #if defined (DEBUG_OP)
66 # define RETURN() __asm__ __volatile__("nop" : : : "memory");
67 #else
68 # define RETURN() __asm__ __volatile__("" : : : "memory");
69 #endif
70
71 static always_inline target_ulong rotl8 (target_ulong i, int n)
72 {
73 return (((uint8_t)i << n) | ((uint8_t)i >> (8 - n)));
74 }
75
76 static always_inline target_ulong rotl16 (target_ulong i, int n)
77 {
78 return (((uint16_t)i << n) | ((uint16_t)i >> (16 - n)));
79 }
80
81 static always_inline target_ulong rotl32 (target_ulong i, int n)
82 {
83 return (((uint32_t)i << n) | ((uint32_t)i >> (32 - n)));
84 }
85
86 #if defined(TARGET_PPC64)
87 static always_inline target_ulong rotl64 (target_ulong i, int n)
88 {
89 return (((uint64_t)i << n) | ((uint64_t)i >> (64 - n)));
90 }
91 #endif
92
93 #if !defined(CONFIG_USER_ONLY)
94 #include "softmmu_exec.h"
95 #endif /* !defined(CONFIG_USER_ONLY) */
96
97 void do_raise_exception_err (uint32_t exception, int error_code);
98 void do_raise_exception (uint32_t exception);
99
100 int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong vaddr,
101 int rw, int access_type);
102
103 void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
104 target_ulong pte0, target_ulong pte1);
105
106 static always_inline void env_to_regs (void)
107 {
108 }
109
110 static always_inline void regs_to_env (void)
111 {
112 }
113
114 int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
115 int mmu_idx, int is_softmmu);
116
117 static always_inline int cpu_halted (CPUState *env)
118 {
119 if (!env->halted)
120 return 0;
121 if (msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD)) {
122 env->halted = 0;
123 return 0;
124 }
125 return EXCP_HALTED;
126 }
127
128 #endif /* !defined (__PPC_H__) */