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[qemu.git] / target-ppc / op_helper.c
1 /*
2 * PowerPC emulation helpers for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "exec.h"
21 #include "host-utils.h"
22
23 #include "helper_regs.h"
24 #include "op_helper.h"
25
26 #define MEMSUFFIX _raw
27 #include "op_helper.h"
28 #include "op_helper_mem.h"
29 #if !defined(CONFIG_USER_ONLY)
30 #define MEMSUFFIX _user
31 #include "op_helper.h"
32 #include "op_helper_mem.h"
33 #define MEMSUFFIX _kernel
34 #include "op_helper.h"
35 #include "op_helper_mem.h"
36 #define MEMSUFFIX _hypv
37 #include "op_helper.h"
38 #include "op_helper_mem.h"
39 #endif
40
41 //#define DEBUG_OP
42 //#define DEBUG_EXCEPTIONS
43 //#define DEBUG_SOFTWARE_TLB
44
45 /*****************************************************************************/
46 /* Exceptions processing helpers */
47
48 void do_raise_exception_err (uint32_t exception, int error_code)
49 {
50 #if 0
51 printf("Raise exception %3x code : %d\n", exception, error_code);
52 #endif
53 env->exception_index = exception;
54 env->error_code = error_code;
55 cpu_loop_exit();
56 }
57
58 void do_raise_exception (uint32_t exception)
59 {
60 do_raise_exception_err(exception, 0);
61 }
62
63 /*****************************************************************************/
64 /* Registers load and stores */
65 void do_load_cr (void)
66 {
67 T0 = (env->crf[0] << 28) |
68 (env->crf[1] << 24) |
69 (env->crf[2] << 20) |
70 (env->crf[3] << 16) |
71 (env->crf[4] << 12) |
72 (env->crf[5] << 8) |
73 (env->crf[6] << 4) |
74 (env->crf[7] << 0);
75 }
76
77 void do_store_cr (uint32_t mask)
78 {
79 int i, sh;
80
81 for (i = 0, sh = 7; i < 8; i++, sh--) {
82 if (mask & (1 << sh))
83 env->crf[i] = (T0 >> (sh * 4)) & 0xFUL;
84 }
85 }
86
87 #if defined(TARGET_PPC64)
88 void do_store_pri (int prio)
89 {
90 env->spr[SPR_PPR] &= ~0x001C000000000000ULL;
91 env->spr[SPR_PPR] |= ((uint64_t)prio & 0x7) << 50;
92 }
93 #endif
94
95 target_ulong ppc_load_dump_spr (int sprn)
96 {
97 if (loglevel != 0) {
98 fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
99 sprn, sprn, env->spr[sprn]);
100 }
101
102 return env->spr[sprn];
103 }
104
105 void ppc_store_dump_spr (int sprn, target_ulong val)
106 {
107 if (loglevel != 0) {
108 fprintf(logfile, "Write SPR %d %03x => " ADDRX " <= " ADDRX "\n",
109 sprn, sprn, env->spr[sprn], val);
110 }
111 env->spr[sprn] = val;
112 }
113
114 /*****************************************************************************/
115 /* Fixed point operations helpers */
116 void do_adde (void)
117 {
118 T2 = T0;
119 T0 += T1 + xer_ca;
120 if (likely(!((uint32_t)T0 < (uint32_t)T2 ||
121 (xer_ca == 1 && (uint32_t)T0 == (uint32_t)T2)))) {
122 env->xer &= ~(1 << XER_CA);
123 } else {
124 env->xer |= (1 << XER_CA);
125 }
126 }
127
128 #if defined(TARGET_PPC64)
129 void do_adde_64 (void)
130 {
131 T2 = T0;
132 T0 += T1 + xer_ca;
133 if (likely(!((uint64_t)T0 < (uint64_t)T2 ||
134 (xer_ca == 1 && (uint64_t)T0 == (uint64_t)T2)))) {
135 env->xer &= ~(1 << XER_CA);
136 } else {
137 env->xer |= (1 << XER_CA);
138 }
139 }
140 #endif
141
142 void do_addmeo (void)
143 {
144 int ov;
145 T1 = T0;
146 T0 += xer_ca + (-1);
147 ov = ((uint32_t)T1 & ((uint32_t)T1 ^ (uint32_t)T0)) >> 31;
148 if (ov) {
149 env->xer |= (1 << XER_OV) | (1 << XER_SO);
150 } else {
151 env->xer &= ~(1 << XER_OV);
152 }
153 if (likely((uint32_t)T1 != 0))
154 env->xer |= (1 << XER_CA);
155 }
156
157 #if defined(TARGET_PPC64)
158 void do_addmeo_64 (void)
159 {
160 int ov;
161 T1 = T0;
162 T0 += xer_ca + (-1);
163 ov = ((uint64_t)T1 & ((uint64_t)T1 ^ (uint64_t)T0)) >> 63;
164 if (ov) {
165 env->xer |= (1 << XER_OV) | (1 << XER_SO);
166 } else {
167 env->xer &= ~(1 << XER_OV);
168 }
169 if (likely((uint64_t)T1 != 0))
170 env->xer |= (1 << XER_CA);
171 }
172 #endif
173
174 void do_divwo (void)
175 {
176 if (likely(!(((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
177 (int32_t)T1 == 0))) {
178 env->xer &= ~(1 << XER_OV);
179 T0 = (int32_t)T0 / (int32_t)T1;
180 } else {
181 env->xer |= (1 << XER_OV) | (1 << XER_SO);
182 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
183 }
184 }
185
186 #if defined(TARGET_PPC64)
187 void do_divdo (void)
188 {
189 if (likely(!(((int64_t)T0 == INT64_MIN && (int64_t)T1 == (int64_t)-1LL) ||
190 (int64_t)T1 == 0))) {
191 env->xer &= ~(1 << XER_OV);
192 T0 = (int64_t)T0 / (int64_t)T1;
193 } else {
194 env->xer |= (1 << XER_OV) | (1 << XER_SO);
195 T0 = UINT64_MAX * ((uint64_t)T0 >> 63);
196 }
197 }
198 #endif
199
200 void do_divwuo (void)
201 {
202 if (likely((uint32_t)T1 != 0)) {
203 env->xer &= ~(1 << XER_OV);
204 T0 = (uint32_t)T0 / (uint32_t)T1;
205 } else {
206 env->xer |= (1 << XER_OV) | (1 << XER_SO);
207 T0 = 0;
208 }
209 }
210
211 #if defined(TARGET_PPC64)
212 void do_divduo (void)
213 {
214 if (likely((uint64_t)T1 != 0)) {
215 env->xer &= ~(1 << XER_OV);
216 T0 = (uint64_t)T0 / (uint64_t)T1;
217 } else {
218 env->xer |= (1 << XER_OV) | (1 << XER_SO);
219 T0 = 0;
220 }
221 }
222 #endif
223
224 void do_mullwo (void)
225 {
226 int64_t res = (int64_t)(int32_t)T0 * (int64_t)(int32_t)T1;
227
228 if (likely((int32_t)res == res)) {
229 env->xer &= ~(1 << XER_OV);
230 } else {
231 env->xer |= (1 << XER_OV) | (1 << XER_SO);
232 }
233 T0 = (int32_t)res;
234 }
235
236 #if defined(TARGET_PPC64)
237 void do_mulldo (void)
238 {
239 int64_t th;
240 uint64_t tl;
241
242 muls64(&tl, (uint64_t *)&th, T0, T1);
243 T0 = (int64_t)tl;
244 /* If th != 0 && th != -1, then we had an overflow */
245 if (likely((uint64_t)(th + 1) <= 1)) {
246 env->xer &= ~(1 << XER_OV);
247 } else {
248 env->xer |= (1 << XER_OV) | (1 << XER_SO);
249 }
250 }
251 #endif
252
253 void do_nego (void)
254 {
255 if (likely((int32_t)T0 != INT32_MIN)) {
256 env->xer &= ~(1 << XER_OV);
257 T0 = -(int32_t)T0;
258 } else {
259 env->xer |= (1 << XER_OV) | (1 << XER_SO);
260 }
261 }
262
263 #if defined(TARGET_PPC64)
264 void do_nego_64 (void)
265 {
266 if (likely((int64_t)T0 != INT64_MIN)) {
267 env->xer &= ~(1 << XER_OV);
268 T0 = -(int64_t)T0;
269 } else {
270 env->xer |= (1 << XER_OV) | (1 << XER_SO);
271 }
272 }
273 #endif
274
275 void do_subfe (void)
276 {
277 T0 = T1 + ~T0 + xer_ca;
278 if (likely((uint32_t)T0 >= (uint32_t)T1 &&
279 (xer_ca == 0 || (uint32_t)T0 != (uint32_t)T1))) {
280 env->xer &= ~(1 << XER_CA);
281 } else {
282 env->xer |= (1 << XER_CA);
283 }
284 }
285
286 #if defined(TARGET_PPC64)
287 void do_subfe_64 (void)
288 {
289 T0 = T1 + ~T0 + xer_ca;
290 if (likely((uint64_t)T0 >= (uint64_t)T1 &&
291 (xer_ca == 0 || (uint64_t)T0 != (uint64_t)T1))) {
292 env->xer &= ~(1 << XER_CA);
293 } else {
294 env->xer |= (1 << XER_CA);
295 }
296 }
297 #endif
298
299 void do_subfmeo (void)
300 {
301 int ov;
302 T1 = T0;
303 T0 = ~T0 + xer_ca - 1;
304 ov = ((uint32_t)~T1 & ((uint32_t)~T1 ^ (uint32_t)T0)) >> 31;
305 if (ov) {
306 env->xer |= (1 << XER_OV) | (1 << XER_SO);
307 } else {
308 env->xer &= ~(1 << XER_OV);
309 }
310 if (likely((uint32_t)T1 != UINT32_MAX))
311 env->xer |= (1 << XER_CA);
312 }
313
314 #if defined(TARGET_PPC64)
315 void do_subfmeo_64 (void)
316 {
317 int ov;
318 T1 = T0;
319 T0 = ~T0 + xer_ca - 1;
320 ov = ((uint64_t)~T1 & ((uint64_t)~T1 ^ (uint64_t)T0)) >> 63;
321 if (ov) {
322 env->xer |= (1 << XER_OV) | (1 << XER_SO);
323 } else {
324 env->xer &= ~(1 << XER_OV);
325 }
326 if (likely((uint64_t)T1 != UINT64_MAX))
327 env->xer |= (1 << XER_CA);
328 }
329 #endif
330
331 void do_subfzeo (void)
332 {
333 int ov;
334 T1 = T0;
335 T0 = ~T0 + xer_ca;
336 ov = (((uint32_t)~T1 ^ UINT32_MAX) &
337 ((uint32_t)(~T1) ^ (uint32_t)T0)) >> 31;
338 if (ov) {
339 env->xer |= (1 << XER_OV) | (1 << XER_SO);
340 } else {
341 env->xer &= ~(1 << XER_OV);
342 }
343 if (likely((uint32_t)T0 >= (uint32_t)~T1)) {
344 env->xer &= ~(1 << XER_CA);
345 } else {
346 env->xer |= (1 << XER_CA);
347 }
348 }
349
350 #if defined(TARGET_PPC64)
351 void do_subfzeo_64 (void)
352 {
353 int ov;
354 T1 = T0;
355 T0 = ~T0 + xer_ca;
356 ov = (((uint64_t)~T1 ^ UINT64_MAX) &
357 ((uint64_t)(~T1) ^ (uint64_t)T0)) >> 63;
358 if (ov) {
359 env->xer |= (1 << XER_OV) | (1 << XER_SO);
360 } else {
361 env->xer &= ~(1 << XER_OV);
362 }
363 if (likely((uint64_t)T0 >= (uint64_t)~T1)) {
364 env->xer &= ~(1 << XER_CA);
365 } else {
366 env->xer |= (1 << XER_CA);
367 }
368 }
369 #endif
370
371 void do_cntlzw (void)
372 {
373 T0 = clz32(T0);
374 }
375
376 #if defined(TARGET_PPC64)
377 void do_cntlzd (void)
378 {
379 T0 = clz64(T0);
380 }
381 #endif
382
383 /* shift right arithmetic helper */
384 void do_sraw (void)
385 {
386 int32_t ret;
387
388 if (likely(!(T1 & 0x20UL))) {
389 if (likely((uint32_t)T1 != 0)) {
390 ret = (int32_t)T0 >> (T1 & 0x1fUL);
391 if (likely(ret >= 0 || ((int32_t)T0 & ((1 << T1) - 1)) == 0)) {
392 env->xer &= ~(1 << XER_CA);
393 } else {
394 env->xer |= (1 << XER_CA);
395 }
396 } else {
397 ret = T0;
398 env->xer &= ~(1 << XER_CA);
399 }
400 } else {
401 ret = UINT32_MAX * ((uint32_t)T0 >> 31);
402 if (likely(ret >= 0 || ((uint32_t)T0 & ~0x80000000UL) == 0)) {
403 env->xer &= ~(1 << XER_CA);
404 } else {
405 env->xer |= (1 << XER_CA);
406 }
407 }
408 T0 = ret;
409 }
410
411 #if defined(TARGET_PPC64)
412 void do_srad (void)
413 {
414 int64_t ret;
415
416 if (likely(!(T1 & 0x40UL))) {
417 if (likely((uint64_t)T1 != 0)) {
418 ret = (int64_t)T0 >> (T1 & 0x3FUL);
419 if (likely(ret >= 0 || ((int64_t)T0 & ((1 << T1) - 1)) == 0)) {
420 env->xer &= ~(1 << XER_CA);
421 } else {
422 env->xer |= (1 << XER_CA);
423 }
424 } else {
425 ret = T0;
426 env->xer &= ~(1 << XER_CA);
427 }
428 } else {
429 ret = UINT64_MAX * ((uint64_t)T0 >> 63);
430 if (likely(ret >= 0 || ((uint64_t)T0 & ~0x8000000000000000ULL) == 0)) {
431 env->xer &= ~(1 << XER_CA);
432 } else {
433 env->xer |= (1 << XER_CA);
434 }
435 }
436 T0 = ret;
437 }
438 #endif
439
440 void do_popcntb (void)
441 {
442 uint32_t ret;
443 int i;
444
445 ret = 0;
446 for (i = 0; i < 32; i += 8)
447 ret |= ctpop8((T0 >> i) & 0xFF) << i;
448 T0 = ret;
449 }
450
451 #if defined(TARGET_PPC64)
452 void do_popcntb_64 (void)
453 {
454 uint64_t ret;
455 int i;
456
457 ret = 0;
458 for (i = 0; i < 64; i += 8)
459 ret |= ctpop8((T0 >> i) & 0xFF) << i;
460 T0 = ret;
461 }
462 #endif
463
464 /*****************************************************************************/
465 /* Floating point operations helpers */
466 static always_inline int fpisneg (float64 d)
467 {
468 CPU_DoubleU u;
469
470 u.d = d;
471
472 return u.ll >> 63 != 0;
473 }
474
475 static always_inline int isden (float64 d)
476 {
477 CPU_DoubleU u;
478
479 u.d = d;
480
481 return ((u.ll >> 52) & 0x7FF) == 0;
482 }
483
484 static always_inline int iszero (float64 d)
485 {
486 CPU_DoubleU u;
487
488 u.d = d;
489
490 return (u.ll & ~0x8000000000000000ULL) == 0;
491 }
492
493 static always_inline int isinfinity (float64 d)
494 {
495 CPU_DoubleU u;
496
497 u.d = d;
498
499 return ((u.ll >> 52) & 0x7FF) == 0x7FF &&
500 (u.ll & 0x000FFFFFFFFFFFFFULL) == 0;
501 }
502
503 #ifdef CONFIG_SOFTFLOAT
504 static always_inline int isfinite (float64 d)
505 {
506 CPU_DoubleU u;
507
508 u.d = d;
509
510 return (((u.ll >> 52) & 0x7FF) != 0x7FF);
511 }
512
513 static always_inline int isnormal (float64 d)
514 {
515 CPU_DoubleU u;
516
517 u.d = d;
518
519 uint32_t exp = (u.ll >> 52) & 0x7FF;
520 return ((0 < exp) && (exp < 0x7FF));
521 }
522 #endif
523
524 void do_compute_fprf (int set_fprf)
525 {
526 int isneg;
527
528 isneg = fpisneg(FT0);
529 if (unlikely(float64_is_nan(FT0))) {
530 if (float64_is_signaling_nan(FT0)) {
531 /* Signaling NaN: flags are undefined */
532 T0 = 0x00;
533 } else {
534 /* Quiet NaN */
535 T0 = 0x11;
536 }
537 } else if (unlikely(isinfinity(FT0))) {
538 /* +/- infinity */
539 if (isneg)
540 T0 = 0x09;
541 else
542 T0 = 0x05;
543 } else {
544 if (iszero(FT0)) {
545 /* +/- zero */
546 if (isneg)
547 T0 = 0x12;
548 else
549 T0 = 0x02;
550 } else {
551 if (isden(FT0)) {
552 /* Denormalized numbers */
553 T0 = 0x10;
554 } else {
555 /* Normalized numbers */
556 T0 = 0x00;
557 }
558 if (isneg) {
559 T0 |= 0x08;
560 } else {
561 T0 |= 0x04;
562 }
563 }
564 }
565 if (set_fprf) {
566 /* We update FPSCR_FPRF */
567 env->fpscr &= ~(0x1F << FPSCR_FPRF);
568 env->fpscr |= T0 << FPSCR_FPRF;
569 }
570 /* We just need fpcc to update Rc1 */
571 T0 &= 0xF;
572 }
573
574 /* Floating-point invalid operations exception */
575 static always_inline void fload_invalid_op_excp (int op)
576 {
577 int ve;
578
579 ve = fpscr_ve;
580 if (op & POWERPC_EXCP_FP_VXSNAN) {
581 /* Operation on signaling NaN */
582 env->fpscr |= 1 << FPSCR_VXSNAN;
583 }
584 if (op & POWERPC_EXCP_FP_VXSOFT) {
585 /* Software-defined condition */
586 env->fpscr |= 1 << FPSCR_VXSOFT;
587 }
588 switch (op & ~(POWERPC_EXCP_FP_VXSOFT | POWERPC_EXCP_FP_VXSNAN)) {
589 case POWERPC_EXCP_FP_VXISI:
590 /* Magnitude subtraction of infinities */
591 env->fpscr |= 1 << FPSCR_VXISI;
592 goto update_arith;
593 case POWERPC_EXCP_FP_VXIDI:
594 /* Division of infinity by infinity */
595 env->fpscr |= 1 << FPSCR_VXIDI;
596 goto update_arith;
597 case POWERPC_EXCP_FP_VXZDZ:
598 /* Division of zero by zero */
599 env->fpscr |= 1 << FPSCR_VXZDZ;
600 goto update_arith;
601 case POWERPC_EXCP_FP_VXIMZ:
602 /* Multiplication of zero by infinity */
603 env->fpscr |= 1 << FPSCR_VXIMZ;
604 goto update_arith;
605 case POWERPC_EXCP_FP_VXVC:
606 /* Ordered comparison of NaN */
607 env->fpscr |= 1 << FPSCR_VXVC;
608 env->fpscr &= ~(0xF << FPSCR_FPCC);
609 env->fpscr |= 0x11 << FPSCR_FPCC;
610 /* We must update the target FPR before raising the exception */
611 if (ve != 0) {
612 env->exception_index = POWERPC_EXCP_PROGRAM;
613 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
614 /* Update the floating-point enabled exception summary */
615 env->fpscr |= 1 << FPSCR_FEX;
616 /* Exception is differed */
617 ve = 0;
618 }
619 break;
620 case POWERPC_EXCP_FP_VXSQRT:
621 /* Square root of a negative number */
622 env->fpscr |= 1 << FPSCR_VXSQRT;
623 update_arith:
624 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
625 if (ve == 0) {
626 /* Set the result to quiet NaN */
627 FT0 = UINT64_MAX;
628 env->fpscr &= ~(0xF << FPSCR_FPCC);
629 env->fpscr |= 0x11 << FPSCR_FPCC;
630 }
631 break;
632 case POWERPC_EXCP_FP_VXCVI:
633 /* Invalid conversion */
634 env->fpscr |= 1 << FPSCR_VXCVI;
635 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
636 if (ve == 0) {
637 /* Set the result to quiet NaN */
638 FT0 = UINT64_MAX;
639 env->fpscr &= ~(0xF << FPSCR_FPCC);
640 env->fpscr |= 0x11 << FPSCR_FPCC;
641 }
642 break;
643 }
644 /* Update the floating-point invalid operation summary */
645 env->fpscr |= 1 << FPSCR_VX;
646 /* Update the floating-point exception summary */
647 env->fpscr |= 1 << FPSCR_FX;
648 if (ve != 0) {
649 /* Update the floating-point enabled exception summary */
650 env->fpscr |= 1 << FPSCR_FEX;
651 if (msr_fe0 != 0 || msr_fe1 != 0)
652 do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
653 }
654 }
655
656 static always_inline void float_zero_divide_excp (void)
657 {
658 CPU_DoubleU u0, u1;
659
660 env->fpscr |= 1 << FPSCR_ZX;
661 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
662 /* Update the floating-point exception summary */
663 env->fpscr |= 1 << FPSCR_FX;
664 if (fpscr_ze != 0) {
665 /* Update the floating-point enabled exception summary */
666 env->fpscr |= 1 << FPSCR_FEX;
667 if (msr_fe0 != 0 || msr_fe1 != 0) {
668 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
669 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
670 }
671 } else {
672 /* Set the result to infinity */
673 u0.d = FT0;
674 u1.d = FT1;
675 u0.ll = ((u0.ll ^ u1.ll) & 0x8000000000000000ULL);
676 u0.ll |= 0x7FFULL << 52;
677 FT0 = u0.d;
678 }
679 }
680
681 static always_inline void float_overflow_excp (void)
682 {
683 env->fpscr |= 1 << FPSCR_OX;
684 /* Update the floating-point exception summary */
685 env->fpscr |= 1 << FPSCR_FX;
686 if (fpscr_oe != 0) {
687 /* XXX: should adjust the result */
688 /* Update the floating-point enabled exception summary */
689 env->fpscr |= 1 << FPSCR_FEX;
690 /* We must update the target FPR before raising the exception */
691 env->exception_index = POWERPC_EXCP_PROGRAM;
692 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
693 } else {
694 env->fpscr |= 1 << FPSCR_XX;
695 env->fpscr |= 1 << FPSCR_FI;
696 }
697 }
698
699 static always_inline void float_underflow_excp (void)
700 {
701 env->fpscr |= 1 << FPSCR_UX;
702 /* Update the floating-point exception summary */
703 env->fpscr |= 1 << FPSCR_FX;
704 if (fpscr_ue != 0) {
705 /* XXX: should adjust the result */
706 /* Update the floating-point enabled exception summary */
707 env->fpscr |= 1 << FPSCR_FEX;
708 /* We must update the target FPR before raising the exception */
709 env->exception_index = POWERPC_EXCP_PROGRAM;
710 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
711 }
712 }
713
714 static always_inline void float_inexact_excp (void)
715 {
716 env->fpscr |= 1 << FPSCR_XX;
717 /* Update the floating-point exception summary */
718 env->fpscr |= 1 << FPSCR_FX;
719 if (fpscr_xe != 0) {
720 /* Update the floating-point enabled exception summary */
721 env->fpscr |= 1 << FPSCR_FEX;
722 /* We must update the target FPR before raising the exception */
723 env->exception_index = POWERPC_EXCP_PROGRAM;
724 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
725 }
726 }
727
728 static always_inline void fpscr_set_rounding_mode (void)
729 {
730 int rnd_type;
731
732 /* Set rounding mode */
733 switch (fpscr_rn) {
734 case 0:
735 /* Best approximation (round to nearest) */
736 rnd_type = float_round_nearest_even;
737 break;
738 case 1:
739 /* Smaller magnitude (round toward zero) */
740 rnd_type = float_round_to_zero;
741 break;
742 case 2:
743 /* Round toward +infinite */
744 rnd_type = float_round_up;
745 break;
746 default:
747 case 3:
748 /* Round toward -infinite */
749 rnd_type = float_round_down;
750 break;
751 }
752 set_float_rounding_mode(rnd_type, &env->fp_status);
753 }
754
755 void do_fpscr_setbit (int bit)
756 {
757 int prev;
758
759 prev = (env->fpscr >> bit) & 1;
760 env->fpscr |= 1 << bit;
761 if (prev == 0) {
762 switch (bit) {
763 case FPSCR_VX:
764 env->fpscr |= 1 << FPSCR_FX;
765 if (fpscr_ve)
766 goto raise_ve;
767 case FPSCR_OX:
768 env->fpscr |= 1 << FPSCR_FX;
769 if (fpscr_oe)
770 goto raise_oe;
771 break;
772 case FPSCR_UX:
773 env->fpscr |= 1 << FPSCR_FX;
774 if (fpscr_ue)
775 goto raise_ue;
776 break;
777 case FPSCR_ZX:
778 env->fpscr |= 1 << FPSCR_FX;
779 if (fpscr_ze)
780 goto raise_ze;
781 break;
782 case FPSCR_XX:
783 env->fpscr |= 1 << FPSCR_FX;
784 if (fpscr_xe)
785 goto raise_xe;
786 break;
787 case FPSCR_VXSNAN:
788 case FPSCR_VXISI:
789 case FPSCR_VXIDI:
790 case FPSCR_VXZDZ:
791 case FPSCR_VXIMZ:
792 case FPSCR_VXVC:
793 case FPSCR_VXSOFT:
794 case FPSCR_VXSQRT:
795 case FPSCR_VXCVI:
796 env->fpscr |= 1 << FPSCR_VX;
797 env->fpscr |= 1 << FPSCR_FX;
798 if (fpscr_ve != 0)
799 goto raise_ve;
800 break;
801 case FPSCR_VE:
802 if (fpscr_vx != 0) {
803 raise_ve:
804 env->error_code = POWERPC_EXCP_FP;
805 if (fpscr_vxsnan)
806 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
807 if (fpscr_vxisi)
808 env->error_code |= POWERPC_EXCP_FP_VXISI;
809 if (fpscr_vxidi)
810 env->error_code |= POWERPC_EXCP_FP_VXIDI;
811 if (fpscr_vxzdz)
812 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
813 if (fpscr_vximz)
814 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
815 if (fpscr_vxvc)
816 env->error_code |= POWERPC_EXCP_FP_VXVC;
817 if (fpscr_vxsoft)
818 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
819 if (fpscr_vxsqrt)
820 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
821 if (fpscr_vxcvi)
822 env->error_code |= POWERPC_EXCP_FP_VXCVI;
823 goto raise_excp;
824 }
825 break;
826 case FPSCR_OE:
827 if (fpscr_ox != 0) {
828 raise_oe:
829 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
830 goto raise_excp;
831 }
832 break;
833 case FPSCR_UE:
834 if (fpscr_ux != 0) {
835 raise_ue:
836 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
837 goto raise_excp;
838 }
839 break;
840 case FPSCR_ZE:
841 if (fpscr_zx != 0) {
842 raise_ze:
843 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
844 goto raise_excp;
845 }
846 break;
847 case FPSCR_XE:
848 if (fpscr_xx != 0) {
849 raise_xe:
850 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
851 goto raise_excp;
852 }
853 break;
854 case FPSCR_RN1:
855 case FPSCR_RN:
856 fpscr_set_rounding_mode();
857 break;
858 default:
859 break;
860 raise_excp:
861 /* Update the floating-point enabled exception summary */
862 env->fpscr |= 1 << FPSCR_FEX;
863 /* We have to update Rc1 before raising the exception */
864 env->exception_index = POWERPC_EXCP_PROGRAM;
865 break;
866 }
867 }
868 }
869
870 #if defined(WORDS_BIGENDIAN)
871 #define WORD0 0
872 #define WORD1 1
873 #else
874 #define WORD0 1
875 #define WORD1 0
876 #endif
877 void do_store_fpscr (uint32_t mask)
878 {
879 /*
880 * We use only the 32 LSB of the incoming fpr
881 */
882 CPU_DoubleU u;
883 uint32_t prev, new;
884 int i;
885
886 u.d = FT0;
887 prev = env->fpscr;
888 new = u.l.lower;
889 new &= ~0x90000000;
890 new |= prev & 0x90000000;
891 for (i = 0; i < 7; i++) {
892 if (mask & (1 << i)) {
893 env->fpscr &= ~(0xF << (4 * i));
894 env->fpscr |= new & (0xF << (4 * i));
895 }
896 }
897 /* Update VX and FEX */
898 if (fpscr_ix != 0)
899 env->fpscr |= 1 << FPSCR_VX;
900 else
901 env->fpscr &= ~(1 << FPSCR_VX);
902 if ((fpscr_ex & fpscr_eex) != 0) {
903 env->fpscr |= 1 << FPSCR_FEX;
904 env->exception_index = POWERPC_EXCP_PROGRAM;
905 /* XXX: we should compute it properly */
906 env->error_code = POWERPC_EXCP_FP;
907 }
908 else
909 env->fpscr &= ~(1 << FPSCR_FEX);
910 fpscr_set_rounding_mode();
911 }
912 #undef WORD0
913 #undef WORD1
914
915 #ifdef CONFIG_SOFTFLOAT
916 void do_float_check_status (void)
917 {
918 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
919 (env->error_code & POWERPC_EXCP_FP)) {
920 /* Differred floating-point exception after target FPR update */
921 if (msr_fe0 != 0 || msr_fe1 != 0)
922 do_raise_exception_err(env->exception_index, env->error_code);
923 } else if (env->fp_status.float_exception_flags & float_flag_overflow) {
924 float_overflow_excp();
925 } else if (env->fp_status.float_exception_flags & float_flag_underflow) {
926 float_underflow_excp();
927 } else if (env->fp_status.float_exception_flags & float_flag_inexact) {
928 float_inexact_excp();
929 }
930 }
931 #endif
932
933 #if USE_PRECISE_EMULATION
934 void do_fadd (void)
935 {
936 if (unlikely(float64_is_signaling_nan(FT0) ||
937 float64_is_signaling_nan(FT1))) {
938 /* sNaN addition */
939 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
940 } else if (likely(isfinite(FT0) || isfinite(FT1) ||
941 fpisneg(FT0) == fpisneg(FT1))) {
942 FT0 = float64_add(FT0, FT1, &env->fp_status);
943 } else {
944 /* Magnitude subtraction of infinities */
945 fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
946 }
947 }
948
949 void do_fsub (void)
950 {
951 if (unlikely(float64_is_signaling_nan(FT0) ||
952 float64_is_signaling_nan(FT1))) {
953 /* sNaN subtraction */
954 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
955 } else if (likely(isfinite(FT0) || isfinite(FT1) ||
956 fpisneg(FT0) != fpisneg(FT1))) {
957 FT0 = float64_sub(FT0, FT1, &env->fp_status);
958 } else {
959 /* Magnitude subtraction of infinities */
960 fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
961 }
962 }
963
964 void do_fmul (void)
965 {
966 if (unlikely(float64_is_signaling_nan(FT0) ||
967 float64_is_signaling_nan(FT1))) {
968 /* sNaN multiplication */
969 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
970 } else if (unlikely((isinfinity(FT0) && iszero(FT1)) ||
971 (iszero(FT0) && isinfinity(FT1)))) {
972 /* Multiplication of zero by infinity */
973 fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
974 } else {
975 FT0 = float64_mul(FT0, FT1, &env->fp_status);
976 }
977 }
978
979 void do_fdiv (void)
980 {
981 if (unlikely(float64_is_signaling_nan(FT0) ||
982 float64_is_signaling_nan(FT1))) {
983 /* sNaN division */
984 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
985 } else if (unlikely(isinfinity(FT0) && isinfinity(FT1))) {
986 /* Division of infinity by infinity */
987 fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
988 } else if (unlikely(iszero(FT1))) {
989 if (iszero(FT0)) {
990 /* Division of zero by zero */
991 fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
992 } else {
993 /* Division by zero */
994 float_zero_divide_excp();
995 }
996 } else {
997 FT0 = float64_div(FT0, FT1, &env->fp_status);
998 }
999 }
1000 #endif /* USE_PRECISE_EMULATION */
1001
1002 void do_fctiw (void)
1003 {
1004 CPU_DoubleU p;
1005
1006 if (unlikely(float64_is_signaling_nan(FT0))) {
1007 /* sNaN conversion */
1008 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1009 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
1010 /* qNan / infinity conversion */
1011 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1012 } else {
1013 p.ll = float64_to_int32(FT0, &env->fp_status);
1014 #if USE_PRECISE_EMULATION
1015 /* XXX: higher bits are not supposed to be significant.
1016 * to make tests easier, return the same as a real PowerPC 750
1017 */
1018 p.ll |= 0xFFF80000ULL << 32;
1019 #endif
1020 FT0 = p.d;
1021 }
1022 }
1023
1024 void do_fctiwz (void)
1025 {
1026 CPU_DoubleU p;
1027
1028 if (unlikely(float64_is_signaling_nan(FT0))) {
1029 /* sNaN conversion */
1030 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1031 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
1032 /* qNan / infinity conversion */
1033 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1034 } else {
1035 p.ll = float64_to_int32_round_to_zero(FT0, &env->fp_status);
1036 #if USE_PRECISE_EMULATION
1037 /* XXX: higher bits are not supposed to be significant.
1038 * to make tests easier, return the same as a real PowerPC 750
1039 */
1040 p.ll |= 0xFFF80000ULL << 32;
1041 #endif
1042 FT0 = p.d;
1043 }
1044 }
1045
1046 #if defined(TARGET_PPC64)
1047 void do_fcfid (void)
1048 {
1049 CPU_DoubleU p;
1050
1051 p.d = FT0;
1052 FT0 = int64_to_float64(p.ll, &env->fp_status);
1053 }
1054
1055 void do_fctid (void)
1056 {
1057 CPU_DoubleU p;
1058
1059 if (unlikely(float64_is_signaling_nan(FT0))) {
1060 /* sNaN conversion */
1061 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1062 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
1063 /* qNan / infinity conversion */
1064 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1065 } else {
1066 p.ll = float64_to_int64(FT0, &env->fp_status);
1067 FT0 = p.d;
1068 }
1069 }
1070
1071 void do_fctidz (void)
1072 {
1073 CPU_DoubleU p;
1074
1075 if (unlikely(float64_is_signaling_nan(FT0))) {
1076 /* sNaN conversion */
1077 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1078 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
1079 /* qNan / infinity conversion */
1080 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1081 } else {
1082 p.ll = float64_to_int64_round_to_zero(FT0, &env->fp_status);
1083 FT0 = p.d;
1084 }
1085 }
1086
1087 #endif
1088
1089 static always_inline void do_fri (int rounding_mode)
1090 {
1091 if (unlikely(float64_is_signaling_nan(FT0))) {
1092 /* sNaN round */
1093 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1094 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
1095 /* qNan / infinity round */
1096 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1097 } else {
1098 set_float_rounding_mode(rounding_mode, &env->fp_status);
1099 FT0 = float64_round_to_int(FT0, &env->fp_status);
1100 /* Restore rounding mode from FPSCR */
1101 fpscr_set_rounding_mode();
1102 }
1103 }
1104
1105 void do_frin (void)
1106 {
1107 do_fri(float_round_nearest_even);
1108 }
1109
1110 void do_friz (void)
1111 {
1112 do_fri(float_round_to_zero);
1113 }
1114
1115 void do_frip (void)
1116 {
1117 do_fri(float_round_up);
1118 }
1119
1120 void do_frim (void)
1121 {
1122 do_fri(float_round_down);
1123 }
1124
1125 #if USE_PRECISE_EMULATION
1126 void do_fmadd (void)
1127 {
1128 if (unlikely(float64_is_signaling_nan(FT0) ||
1129 float64_is_signaling_nan(FT1) ||
1130 float64_is_signaling_nan(FT2))) {
1131 /* sNaN operation */
1132 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1133 } else {
1134 #ifdef FLOAT128
1135 /* This is the way the PowerPC specification defines it */
1136 float128 ft0_128, ft1_128;
1137
1138 ft0_128 = float64_to_float128(FT0, &env->fp_status);
1139 ft1_128 = float64_to_float128(FT1, &env->fp_status);
1140 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1141 ft1_128 = float64_to_float128(FT2, &env->fp_status);
1142 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1143 FT0 = float128_to_float64(ft0_128, &env->fp_status);
1144 #else
1145 /* This is OK on x86 hosts */
1146 FT0 = (FT0 * FT1) + FT2;
1147 #endif
1148 }
1149 }
1150
1151 void do_fmsub (void)
1152 {
1153 if (unlikely(float64_is_signaling_nan(FT0) ||
1154 float64_is_signaling_nan(FT1) ||
1155 float64_is_signaling_nan(FT2))) {
1156 /* sNaN operation */
1157 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1158 } else {
1159 #ifdef FLOAT128
1160 /* This is the way the PowerPC specification defines it */
1161 float128 ft0_128, ft1_128;
1162
1163 ft0_128 = float64_to_float128(FT0, &env->fp_status);
1164 ft1_128 = float64_to_float128(FT1, &env->fp_status);
1165 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1166 ft1_128 = float64_to_float128(FT2, &env->fp_status);
1167 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1168 FT0 = float128_to_float64(ft0_128, &env->fp_status);
1169 #else
1170 /* This is OK on x86 hosts */
1171 FT0 = (FT0 * FT1) - FT2;
1172 #endif
1173 }
1174 }
1175 #endif /* USE_PRECISE_EMULATION */
1176
1177 void do_fnmadd (void)
1178 {
1179 if (unlikely(float64_is_signaling_nan(FT0) ||
1180 float64_is_signaling_nan(FT1) ||
1181 float64_is_signaling_nan(FT2))) {
1182 /* sNaN operation */
1183 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1184 } else {
1185 #if USE_PRECISE_EMULATION
1186 #ifdef FLOAT128
1187 /* This is the way the PowerPC specification defines it */
1188 float128 ft0_128, ft1_128;
1189
1190 ft0_128 = float64_to_float128(FT0, &env->fp_status);
1191 ft1_128 = float64_to_float128(FT1, &env->fp_status);
1192 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1193 ft1_128 = float64_to_float128(FT2, &env->fp_status);
1194 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1195 FT0 = float128_to_float64(ft0_128, &env->fp_status);
1196 #else
1197 /* This is OK on x86 hosts */
1198 FT0 = (FT0 * FT1) + FT2;
1199 #endif
1200 #else
1201 FT0 = float64_mul(FT0, FT1, &env->fp_status);
1202 FT0 = float64_add(FT0, FT2, &env->fp_status);
1203 #endif
1204 if (likely(!isnan(FT0)))
1205 FT0 = float64_chs(FT0);
1206 }
1207 }
1208
1209 void do_fnmsub (void)
1210 {
1211 if (unlikely(float64_is_signaling_nan(FT0) ||
1212 float64_is_signaling_nan(FT1) ||
1213 float64_is_signaling_nan(FT2))) {
1214 /* sNaN operation */
1215 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1216 } else {
1217 #if USE_PRECISE_EMULATION
1218 #ifdef FLOAT128
1219 /* This is the way the PowerPC specification defines it */
1220 float128 ft0_128, ft1_128;
1221
1222 ft0_128 = float64_to_float128(FT0, &env->fp_status);
1223 ft1_128 = float64_to_float128(FT1, &env->fp_status);
1224 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1225 ft1_128 = float64_to_float128(FT2, &env->fp_status);
1226 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1227 FT0 = float128_to_float64(ft0_128, &env->fp_status);
1228 #else
1229 /* This is OK on x86 hosts */
1230 FT0 = (FT0 * FT1) - FT2;
1231 #endif
1232 #else
1233 FT0 = float64_mul(FT0, FT1, &env->fp_status);
1234 FT0 = float64_sub(FT0, FT2, &env->fp_status);
1235 #endif
1236 if (likely(!isnan(FT0)))
1237 FT0 = float64_chs(FT0);
1238 }
1239 }
1240
1241 #if USE_PRECISE_EMULATION
1242 void do_frsp (void)
1243 {
1244 if (unlikely(float64_is_signaling_nan(FT0))) {
1245 /* sNaN square root */
1246 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1247 } else {
1248 FT0 = float64_to_float32(FT0, &env->fp_status);
1249 }
1250 }
1251 #endif /* USE_PRECISE_EMULATION */
1252
1253 void do_fsqrt (void)
1254 {
1255 if (unlikely(float64_is_signaling_nan(FT0))) {
1256 /* sNaN square root */
1257 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1258 } else if (unlikely(fpisneg(FT0) && !iszero(FT0))) {
1259 /* Square root of a negative nonzero number */
1260 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1261 } else {
1262 FT0 = float64_sqrt(FT0, &env->fp_status);
1263 }
1264 }
1265
1266 void do_fre (void)
1267 {
1268 CPU_DoubleU p;
1269
1270 if (unlikely(float64_is_signaling_nan(FT0))) {
1271 /* sNaN reciprocal */
1272 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1273 } else if (unlikely(iszero(FT0))) {
1274 /* Zero reciprocal */
1275 float_zero_divide_excp();
1276 } else if (likely(isnormal(FT0))) {
1277 FT0 = float64_div(1.0, FT0, &env->fp_status);
1278 } else {
1279 p.d = FT0;
1280 if (p.ll == 0x8000000000000000ULL) {
1281 p.ll = 0xFFF0000000000000ULL;
1282 } else if (p.ll == 0x0000000000000000ULL) {
1283 p.ll = 0x7FF0000000000000ULL;
1284 } else if (isnan(FT0)) {
1285 p.ll = 0x7FF8000000000000ULL;
1286 } else if (fpisneg(FT0)) {
1287 p.ll = 0x8000000000000000ULL;
1288 } else {
1289 p.ll = 0x0000000000000000ULL;
1290 }
1291 FT0 = p.d;
1292 }
1293 }
1294
1295 void do_fres (void)
1296 {
1297 CPU_DoubleU p;
1298
1299 if (unlikely(float64_is_signaling_nan(FT0))) {
1300 /* sNaN reciprocal */
1301 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1302 } else if (unlikely(iszero(FT0))) {
1303 /* Zero reciprocal */
1304 float_zero_divide_excp();
1305 } else if (likely(isnormal(FT0))) {
1306 #if USE_PRECISE_EMULATION
1307 FT0 = float64_div(1.0, FT0, &env->fp_status);
1308 FT0 = float64_to_float32(FT0, &env->fp_status);
1309 #else
1310 FT0 = float32_div(1.0, FT0, &env->fp_status);
1311 #endif
1312 } else {
1313 p.d = FT0;
1314 if (p.ll == 0x8000000000000000ULL) {
1315 p.ll = 0xFFF0000000000000ULL;
1316 } else if (p.ll == 0x0000000000000000ULL) {
1317 p.ll = 0x7FF0000000000000ULL;
1318 } else if (isnan(FT0)) {
1319 p.ll = 0x7FF8000000000000ULL;
1320 } else if (fpisneg(FT0)) {
1321 p.ll = 0x8000000000000000ULL;
1322 } else {
1323 p.ll = 0x0000000000000000ULL;
1324 }
1325 FT0 = p.d;
1326 }
1327 }
1328
1329 void do_frsqrte (void)
1330 {
1331 CPU_DoubleU p;
1332
1333 if (unlikely(float64_is_signaling_nan(FT0))) {
1334 /* sNaN reciprocal square root */
1335 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1336 } else if (unlikely(fpisneg(FT0) && !iszero(FT0))) {
1337 /* Reciprocal square root of a negative nonzero number */
1338 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1339 } else if (likely(isnormal(FT0))) {
1340 FT0 = float64_sqrt(FT0, &env->fp_status);
1341 FT0 = float32_div(1.0, FT0, &env->fp_status);
1342 } else {
1343 p.d = FT0;
1344 if (p.ll == 0x8000000000000000ULL) {
1345 p.ll = 0xFFF0000000000000ULL;
1346 } else if (p.ll == 0x0000000000000000ULL) {
1347 p.ll = 0x7FF0000000000000ULL;
1348 } else if (isnan(FT0)) {
1349 p.ll |= 0x000FFFFFFFFFFFFFULL;
1350 } else if (fpisneg(FT0)) {
1351 p.ll = 0x7FF8000000000000ULL;
1352 } else {
1353 p.ll = 0x0000000000000000ULL;
1354 }
1355 FT0 = p.d;
1356 }
1357 }
1358
1359 void do_fsel (void)
1360 {
1361 if (!fpisneg(FT0) || iszero(FT0))
1362 FT0 = FT1;
1363 else
1364 FT0 = FT2;
1365 }
1366
1367 void do_fcmpu (void)
1368 {
1369 if (unlikely(float64_is_signaling_nan(FT0) ||
1370 float64_is_signaling_nan(FT1))) {
1371 /* sNaN comparison */
1372 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1373 } else {
1374 if (float64_lt(FT0, FT1, &env->fp_status)) {
1375 T0 = 0x08UL;
1376 } else if (!float64_le(FT0, FT1, &env->fp_status)) {
1377 T0 = 0x04UL;
1378 } else {
1379 T0 = 0x02UL;
1380 }
1381 }
1382 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1383 env->fpscr |= T0 << FPSCR_FPRF;
1384 }
1385
1386 void do_fcmpo (void)
1387 {
1388 if (unlikely(float64_is_nan(FT0) ||
1389 float64_is_nan(FT1))) {
1390 if (float64_is_signaling_nan(FT0) ||
1391 float64_is_signaling_nan(FT1)) {
1392 /* sNaN comparison */
1393 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
1394 POWERPC_EXCP_FP_VXVC);
1395 } else {
1396 /* qNaN comparison */
1397 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
1398 }
1399 } else {
1400 if (float64_lt(FT0, FT1, &env->fp_status)) {
1401 T0 = 0x08UL;
1402 } else if (!float64_le(FT0, FT1, &env->fp_status)) {
1403 T0 = 0x04UL;
1404 } else {
1405 T0 = 0x02UL;
1406 }
1407 }
1408 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1409 env->fpscr |= T0 << FPSCR_FPRF;
1410 }
1411
1412 #if !defined (CONFIG_USER_ONLY)
1413 void cpu_dump_rfi (target_ulong RA, target_ulong msr);
1414
1415 void do_store_msr (void)
1416 {
1417 T0 = hreg_store_msr(env, T0, 0);
1418 if (T0 != 0) {
1419 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1420 do_raise_exception(T0);
1421 }
1422 }
1423
1424 static always_inline void __do_rfi (target_ulong nip, target_ulong msr,
1425 target_ulong msrm, int keep_msrh)
1426 {
1427 #if defined(TARGET_PPC64)
1428 if (msr & (1ULL << MSR_SF)) {
1429 nip = (uint64_t)nip;
1430 msr &= (uint64_t)msrm;
1431 } else {
1432 nip = (uint32_t)nip;
1433 msr = (uint32_t)(msr & msrm);
1434 if (keep_msrh)
1435 msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
1436 }
1437 #else
1438 nip = (uint32_t)nip;
1439 msr &= (uint32_t)msrm;
1440 #endif
1441 /* XXX: beware: this is false if VLE is supported */
1442 env->nip = nip & ~((target_ulong)0x00000003);
1443 hreg_store_msr(env, msr, 1);
1444 #if defined (DEBUG_OP)
1445 cpu_dump_rfi(env->nip, env->msr);
1446 #endif
1447 /* No need to raise an exception here,
1448 * as rfi is always the last insn of a TB
1449 */
1450 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1451 }
1452
1453 void do_rfi (void)
1454 {
1455 __do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1456 ~((target_ulong)0xFFFF0000), 1);
1457 }
1458
1459 #if defined(TARGET_PPC64)
1460 void do_rfid (void)
1461 {
1462 __do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1463 ~((target_ulong)0xFFFF0000), 0);
1464 }
1465
1466 void do_hrfid (void)
1467 {
1468 __do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
1469 ~((target_ulong)0xFFFF0000), 0);
1470 }
1471 #endif
1472 #endif
1473
1474 void do_tw (int flags)
1475 {
1476 if (!likely(!(((int32_t)T0 < (int32_t)T1 && (flags & 0x10)) ||
1477 ((int32_t)T0 > (int32_t)T1 && (flags & 0x08)) ||
1478 ((int32_t)T0 == (int32_t)T1 && (flags & 0x04)) ||
1479 ((uint32_t)T0 < (uint32_t)T1 && (flags & 0x02)) ||
1480 ((uint32_t)T0 > (uint32_t)T1 && (flags & 0x01))))) {
1481 do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1482 }
1483 }
1484
1485 #if defined(TARGET_PPC64)
1486 void do_td (int flags)
1487 {
1488 if (!likely(!(((int64_t)T0 < (int64_t)T1 && (flags & 0x10)) ||
1489 ((int64_t)T0 > (int64_t)T1 && (flags & 0x08)) ||
1490 ((int64_t)T0 == (int64_t)T1 && (flags & 0x04)) ||
1491 ((uint64_t)T0 < (uint64_t)T1 && (flags & 0x02)) ||
1492 ((uint64_t)T0 > (uint64_t)T1 && (flags & 0x01)))))
1493 do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1494 }
1495 #endif
1496
1497 /*****************************************************************************/
1498 /* PowerPC 601 specific instructions (POWER bridge) */
1499 void do_POWER_abso (void)
1500 {
1501 if ((int32_t)T0 == INT32_MIN) {
1502 T0 = INT32_MAX;
1503 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1504 } else if ((int32_t)T0 < 0) {
1505 T0 = -T0;
1506 env->xer &= ~(1 << XER_OV);
1507 } else {
1508 env->xer &= ~(1 << XER_OV);
1509 }
1510 }
1511
1512 void do_POWER_clcs (void)
1513 {
1514 switch (T0) {
1515 case 0x0CUL:
1516 /* Instruction cache line size */
1517 T0 = env->icache_line_size;
1518 break;
1519 case 0x0DUL:
1520 /* Data cache line size */
1521 T0 = env->dcache_line_size;
1522 break;
1523 case 0x0EUL:
1524 /* Minimum cache line size */
1525 T0 = env->icache_line_size < env->dcache_line_size ?
1526 env->icache_line_size : env->dcache_line_size;
1527 break;
1528 case 0x0FUL:
1529 /* Maximum cache line size */
1530 T0 = env->icache_line_size > env->dcache_line_size ?
1531 env->icache_line_size : env->dcache_line_size;
1532 break;
1533 default:
1534 /* Undefined */
1535 break;
1536 }
1537 }
1538
1539 void do_POWER_div (void)
1540 {
1541 uint64_t tmp;
1542
1543 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1544 (int32_t)T1 == 0) {
1545 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1546 env->spr[SPR_MQ] = 0;
1547 } else {
1548 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1549 env->spr[SPR_MQ] = tmp % T1;
1550 T0 = tmp / (int32_t)T1;
1551 }
1552 }
1553
1554 void do_POWER_divo (void)
1555 {
1556 int64_t tmp;
1557
1558 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1559 (int32_t)T1 == 0) {
1560 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1561 env->spr[SPR_MQ] = 0;
1562 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1563 } else {
1564 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1565 env->spr[SPR_MQ] = tmp % T1;
1566 tmp /= (int32_t)T1;
1567 if (tmp > (int64_t)INT32_MAX || tmp < (int64_t)INT32_MIN) {
1568 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1569 } else {
1570 env->xer &= ~(1 << XER_OV);
1571 }
1572 T0 = tmp;
1573 }
1574 }
1575
1576 void do_POWER_divs (void)
1577 {
1578 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1579 (int32_t)T1 == 0) {
1580 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1581 env->spr[SPR_MQ] = 0;
1582 } else {
1583 env->spr[SPR_MQ] = T0 % T1;
1584 T0 = (int32_t)T0 / (int32_t)T1;
1585 }
1586 }
1587
1588 void do_POWER_divso (void)
1589 {
1590 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1591 (int32_t)T1 == 0) {
1592 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1593 env->spr[SPR_MQ] = 0;
1594 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1595 } else {
1596 T0 = (int32_t)T0 / (int32_t)T1;
1597 env->spr[SPR_MQ] = (int32_t)T0 % (int32_t)T1;
1598 env->xer &= ~(1 << XER_OV);
1599 }
1600 }
1601
1602 void do_POWER_dozo (void)
1603 {
1604 if ((int32_t)T1 > (int32_t)T0) {
1605 T2 = T0;
1606 T0 = T1 - T0;
1607 if (((uint32_t)(~T2) ^ (uint32_t)T1 ^ UINT32_MAX) &
1608 ((uint32_t)(~T2) ^ (uint32_t)T0) & (1UL << 31)) {
1609 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1610 } else {
1611 env->xer &= ~(1 << XER_OV);
1612 }
1613 } else {
1614 T0 = 0;
1615 env->xer &= ~(1 << XER_OV);
1616 }
1617 }
1618
1619 void do_POWER_maskg (void)
1620 {
1621 uint32_t ret;
1622
1623 if ((uint32_t)T0 == (uint32_t)(T1 + 1)) {
1624 ret = UINT32_MAX;
1625 } else {
1626 ret = (UINT32_MAX >> ((uint32_t)T0)) ^
1627 ((UINT32_MAX >> ((uint32_t)T1)) >> 1);
1628 if ((uint32_t)T0 > (uint32_t)T1)
1629 ret = ~ret;
1630 }
1631 T0 = ret;
1632 }
1633
1634 void do_POWER_mulo (void)
1635 {
1636 uint64_t tmp;
1637
1638 tmp = (uint64_t)T0 * (uint64_t)T1;
1639 env->spr[SPR_MQ] = tmp >> 32;
1640 T0 = tmp;
1641 if (tmp >> 32 != ((uint64_t)T0 >> 16) * ((uint64_t)T1 >> 16)) {
1642 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1643 } else {
1644 env->xer &= ~(1 << XER_OV);
1645 }
1646 }
1647
1648 #if !defined (CONFIG_USER_ONLY)
1649 void do_POWER_rac (void)
1650 {
1651 mmu_ctx_t ctx;
1652 int nb_BATs;
1653
1654 /* We don't have to generate many instances of this instruction,
1655 * as rac is supervisor only.
1656 */
1657 /* XXX: FIX THIS: Pretend we have no BAT */
1658 nb_BATs = env->nb_BATs;
1659 env->nb_BATs = 0;
1660 if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT) == 0)
1661 T0 = ctx.raddr;
1662 env->nb_BATs = nb_BATs;
1663 }
1664
1665 void do_POWER_rfsvc (void)
1666 {
1667 __do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
1668 }
1669
1670 void do_store_hid0_601 (void)
1671 {
1672 uint32_t hid0;
1673
1674 hid0 = env->spr[SPR_HID0];
1675 if ((T0 ^ hid0) & 0x00000008) {
1676 /* Change current endianness */
1677 env->hflags &= ~(1 << MSR_LE);
1678 env->hflags_nmsr &= ~(1 << MSR_LE);
1679 env->hflags_nmsr |= (1 << MSR_LE) & (((T0 >> 3) & 1) << MSR_LE);
1680 env->hflags |= env->hflags_nmsr;
1681 if (loglevel != 0) {
1682 fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n",
1683 __func__, T0 & 0x8 ? 'l' : 'b', env->hflags);
1684 }
1685 }
1686 env->spr[SPR_HID0] = T0;
1687 }
1688 #endif
1689
1690 /*****************************************************************************/
1691 /* 602 specific instructions */
1692 /* mfrom is the most crazy instruction ever seen, imho ! */
1693 /* Real implementation uses a ROM table. Do the same */
1694 #define USE_MFROM_ROM_TABLE
1695 void do_op_602_mfrom (void)
1696 {
1697 if (likely(T0 < 602)) {
1698 #if defined(USE_MFROM_ROM_TABLE)
1699 #include "mfrom_table.c"
1700 T0 = mfrom_ROM_table[T0];
1701 #else
1702 double d;
1703 /* Extremly decomposed:
1704 * -T0 / 256
1705 * T0 = 256 * log10(10 + 1.0) + 0.5
1706 */
1707 d = T0;
1708 d = float64_div(d, 256, &env->fp_status);
1709 d = float64_chs(d);
1710 d = exp10(d); // XXX: use float emulation function
1711 d = float64_add(d, 1.0, &env->fp_status);
1712 d = log10(d); // XXX: use float emulation function
1713 d = float64_mul(d, 256, &env->fp_status);
1714 d = float64_add(d, 0.5, &env->fp_status);
1715 T0 = float64_round_to_int(d, &env->fp_status);
1716 #endif
1717 } else {
1718 T0 = 0;
1719 }
1720 }
1721
1722 /*****************************************************************************/
1723 /* Embedded PowerPC specific helpers */
1724 void do_405_check_sat (void)
1725 {
1726 if (!likely((((uint32_t)T1 ^ (uint32_t)T2) >> 31) ||
1727 !(((uint32_t)T0 ^ (uint32_t)T2) >> 31))) {
1728 /* Saturate result */
1729 if (T2 >> 31) {
1730 T0 = INT32_MIN;
1731 } else {
1732 T0 = INT32_MAX;
1733 }
1734 }
1735 }
1736
1737 /* XXX: to be improved to check access rights when in user-mode */
1738 void do_load_dcr (void)
1739 {
1740 target_ulong val;
1741
1742 if (unlikely(env->dcr_env == NULL)) {
1743 if (loglevel != 0) {
1744 fprintf(logfile, "No DCR environment\n");
1745 }
1746 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1747 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1748 } else if (unlikely(ppc_dcr_read(env->dcr_env, T0, &val) != 0)) {
1749 if (loglevel != 0) {
1750 fprintf(logfile, "DCR read error %d %03x\n", (int)T0, (int)T0);
1751 }
1752 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1753 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1754 } else {
1755 T0 = val;
1756 }
1757 }
1758
1759 void do_store_dcr (void)
1760 {
1761 if (unlikely(env->dcr_env == NULL)) {
1762 if (loglevel != 0) {
1763 fprintf(logfile, "No DCR environment\n");
1764 }
1765 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1766 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1767 } else if (unlikely(ppc_dcr_write(env->dcr_env, T0, T1) != 0)) {
1768 if (loglevel != 0) {
1769 fprintf(logfile, "DCR write error %d %03x\n", (int)T0, (int)T0);
1770 }
1771 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1772 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1773 }
1774 }
1775
1776 #if !defined(CONFIG_USER_ONLY)
1777 void do_40x_rfci (void)
1778 {
1779 __do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
1780 ~((target_ulong)0xFFFF0000), 0);
1781 }
1782
1783 void do_rfci (void)
1784 {
1785 __do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
1786 ~((target_ulong)0x3FFF0000), 0);
1787 }
1788
1789 void do_rfdi (void)
1790 {
1791 __do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
1792 ~((target_ulong)0x3FFF0000), 0);
1793 }
1794
1795 void do_rfmci (void)
1796 {
1797 __do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
1798 ~((target_ulong)0x3FFF0000), 0);
1799 }
1800
1801 void do_load_403_pb (int num)
1802 {
1803 T0 = env->pb[num];
1804 }
1805
1806 void do_store_403_pb (int num)
1807 {
1808 if (likely(env->pb[num] != T0)) {
1809 env->pb[num] = T0;
1810 /* Should be optimized */
1811 tlb_flush(env, 1);
1812 }
1813 }
1814 #endif
1815
1816 /* 440 specific */
1817 void do_440_dlmzb (void)
1818 {
1819 target_ulong mask;
1820 int i;
1821
1822 i = 1;
1823 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1824 if ((T0 & mask) == 0)
1825 goto done;
1826 i++;
1827 }
1828 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1829 if ((T1 & mask) == 0)
1830 break;
1831 i++;
1832 }
1833 done:
1834 T0 = i;
1835 }
1836
1837 /* SPE extension helpers */
1838 /* Use a table to make this quicker */
1839 static uint8_t hbrev[16] = {
1840 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
1841 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
1842 };
1843
1844 static always_inline uint8_t byte_reverse (uint8_t val)
1845 {
1846 return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
1847 }
1848
1849 static always_inline uint32_t word_reverse (uint32_t val)
1850 {
1851 return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
1852 (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
1853 }
1854
1855 #define MASKBITS 16 // Random value - to be fixed (implementation dependant)
1856 void do_brinc (void)
1857 {
1858 uint32_t a, b, d, mask;
1859
1860 mask = UINT32_MAX >> (32 - MASKBITS);
1861 a = T0 & mask;
1862 b = T1 & mask;
1863 d = word_reverse(1 + word_reverse(a | ~b));
1864 T0 = (T0 & ~mask) | (d & b);
1865 }
1866
1867 #define DO_SPE_OP2(name) \
1868 void do_ev##name (void) \
1869 { \
1870 T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32, T1_64 >> 32) << 32) | \
1871 (uint64_t)_do_e##name(T0_64, T1_64); \
1872 }
1873
1874 #define DO_SPE_OP1(name) \
1875 void do_ev##name (void) \
1876 { \
1877 T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32) << 32) | \
1878 (uint64_t)_do_e##name(T0_64); \
1879 }
1880
1881 /* Fixed-point vector arithmetic */
1882 static always_inline uint32_t _do_eabs (uint32_t val)
1883 {
1884 if ((val & 0x80000000) && val != 0x80000000)
1885 val -= val;
1886
1887 return val;
1888 }
1889
1890 static always_inline uint32_t _do_eaddw (uint32_t op1, uint32_t op2)
1891 {
1892 return op1 + op2;
1893 }
1894
1895 static always_inline int _do_ecntlsw (uint32_t val)
1896 {
1897 if (val & 0x80000000)
1898 return clz32(~val);
1899 else
1900 return clz32(val);
1901 }
1902
1903 static always_inline int _do_ecntlzw (uint32_t val)
1904 {
1905 return clz32(val);
1906 }
1907
1908 static always_inline uint32_t _do_eneg (uint32_t val)
1909 {
1910 if (val != 0x80000000)
1911 val -= val;
1912
1913 return val;
1914 }
1915
1916 static always_inline uint32_t _do_erlw (uint32_t op1, uint32_t op2)
1917 {
1918 return rotl32(op1, op2);
1919 }
1920
1921 static always_inline uint32_t _do_erndw (uint32_t val)
1922 {
1923 return (val + 0x000080000000) & 0xFFFF0000;
1924 }
1925
1926 static always_inline uint32_t _do_eslw (uint32_t op1, uint32_t op2)
1927 {
1928 /* No error here: 6 bits are used */
1929 return op1 << (op2 & 0x3F);
1930 }
1931
1932 static always_inline int32_t _do_esrws (int32_t op1, uint32_t op2)
1933 {
1934 /* No error here: 6 bits are used */
1935 return op1 >> (op2 & 0x3F);
1936 }
1937
1938 static always_inline uint32_t _do_esrwu (uint32_t op1, uint32_t op2)
1939 {
1940 /* No error here: 6 bits are used */
1941 return op1 >> (op2 & 0x3F);
1942 }
1943
1944 static always_inline uint32_t _do_esubfw (uint32_t op1, uint32_t op2)
1945 {
1946 return op2 - op1;
1947 }
1948
1949 /* evabs */
1950 DO_SPE_OP1(abs);
1951 /* evaddw */
1952 DO_SPE_OP2(addw);
1953 /* evcntlsw */
1954 DO_SPE_OP1(cntlsw);
1955 /* evcntlzw */
1956 DO_SPE_OP1(cntlzw);
1957 /* evneg */
1958 DO_SPE_OP1(neg);
1959 /* evrlw */
1960 DO_SPE_OP2(rlw);
1961 /* evrnd */
1962 DO_SPE_OP1(rndw);
1963 /* evslw */
1964 DO_SPE_OP2(slw);
1965 /* evsrws */
1966 DO_SPE_OP2(srws);
1967 /* evsrwu */
1968 DO_SPE_OP2(srwu);
1969 /* evsubfw */
1970 DO_SPE_OP2(subfw);
1971
1972 /* evsel is a little bit more complicated... */
1973 static always_inline uint32_t _do_esel (uint32_t op1, uint32_t op2, int n)
1974 {
1975 if (n)
1976 return op1;
1977 else
1978 return op2;
1979 }
1980
1981 void do_evsel (void)
1982 {
1983 T0_64 = ((uint64_t)_do_esel(T0_64 >> 32, T1_64 >> 32, T0 >> 3) << 32) |
1984 (uint64_t)_do_esel(T0_64, T1_64, (T0 >> 2) & 1);
1985 }
1986
1987 /* Fixed-point vector comparisons */
1988 #define DO_SPE_CMP(name) \
1989 void do_ev##name (void) \
1990 { \
1991 T0 = _do_evcmp_merge((uint64_t)_do_e##name(T0_64 >> 32, \
1992 T1_64 >> 32) << 32, \
1993 _do_e##name(T0_64, T1_64)); \
1994 }
1995
1996 static always_inline uint32_t _do_evcmp_merge (int t0, int t1)
1997 {
1998 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
1999 }
2000 static always_inline int _do_ecmpeq (uint32_t op1, uint32_t op2)
2001 {
2002 return op1 == op2 ? 1 : 0;
2003 }
2004
2005 static always_inline int _do_ecmpgts (int32_t op1, int32_t op2)
2006 {
2007 return op1 > op2 ? 1 : 0;
2008 }
2009
2010 static always_inline int _do_ecmpgtu (uint32_t op1, uint32_t op2)
2011 {
2012 return op1 > op2 ? 1 : 0;
2013 }
2014
2015 static always_inline int _do_ecmplts (int32_t op1, int32_t op2)
2016 {
2017 return op1 < op2 ? 1 : 0;
2018 }
2019
2020 static always_inline int _do_ecmpltu (uint32_t op1, uint32_t op2)
2021 {
2022 return op1 < op2 ? 1 : 0;
2023 }
2024
2025 /* evcmpeq */
2026 DO_SPE_CMP(cmpeq);
2027 /* evcmpgts */
2028 DO_SPE_CMP(cmpgts);
2029 /* evcmpgtu */
2030 DO_SPE_CMP(cmpgtu);
2031 /* evcmplts */
2032 DO_SPE_CMP(cmplts);
2033 /* evcmpltu */
2034 DO_SPE_CMP(cmpltu);
2035
2036 /* Single precision floating-point conversions from/to integer */
2037 static always_inline uint32_t _do_efscfsi (int32_t val)
2038 {
2039 CPU_FloatU u;
2040
2041 u.f = int32_to_float32(val, &env->spe_status);
2042
2043 return u.l;
2044 }
2045
2046 static always_inline uint32_t _do_efscfui (uint32_t val)
2047 {
2048 CPU_FloatU u;
2049
2050 u.f = uint32_to_float32(val, &env->spe_status);
2051
2052 return u.l;
2053 }
2054
2055 static always_inline int32_t _do_efsctsi (uint32_t val)
2056 {
2057 CPU_FloatU u;
2058
2059 u.l = val;
2060 /* NaN are not treated the same way IEEE 754 does */
2061 if (unlikely(isnan(u.f)))
2062 return 0;
2063
2064 return float32_to_int32(u.f, &env->spe_status);
2065 }
2066
2067 static always_inline uint32_t _do_efsctui (uint32_t val)
2068 {
2069 CPU_FloatU u;
2070
2071 u.l = val;
2072 /* NaN are not treated the same way IEEE 754 does */
2073 if (unlikely(isnan(u.f)))
2074 return 0;
2075
2076 return float32_to_uint32(u.f, &env->spe_status);
2077 }
2078
2079 static always_inline int32_t _do_efsctsiz (uint32_t val)
2080 {
2081 CPU_FloatU u;
2082
2083 u.l = val;
2084 /* NaN are not treated the same way IEEE 754 does */
2085 if (unlikely(isnan(u.f)))
2086 return 0;
2087
2088 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
2089 }
2090
2091 static always_inline uint32_t _do_efsctuiz (uint32_t val)
2092 {
2093 CPU_FloatU u;
2094
2095 u.l = val;
2096 /* NaN are not treated the same way IEEE 754 does */
2097 if (unlikely(isnan(u.f)))
2098 return 0;
2099
2100 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
2101 }
2102
2103 void do_efscfsi (void)
2104 {
2105 T0_64 = _do_efscfsi(T0_64);
2106 }
2107
2108 void do_efscfui (void)
2109 {
2110 T0_64 = _do_efscfui(T0_64);
2111 }
2112
2113 void do_efsctsi (void)
2114 {
2115 T0_64 = _do_efsctsi(T0_64);
2116 }
2117
2118 void do_efsctui (void)
2119 {
2120 T0_64 = _do_efsctui(T0_64);
2121 }
2122
2123 void do_efsctsiz (void)
2124 {
2125 T0_64 = _do_efsctsiz(T0_64);
2126 }
2127
2128 void do_efsctuiz (void)
2129 {
2130 T0_64 = _do_efsctuiz(T0_64);
2131 }
2132
2133 /* Single precision floating-point conversion to/from fractional */
2134 static always_inline uint32_t _do_efscfsf (uint32_t val)
2135 {
2136 CPU_FloatU u;
2137 float32 tmp;
2138
2139 u.f = int32_to_float32(val, &env->spe_status);
2140 tmp = int64_to_float32(1ULL << 32, &env->spe_status);
2141 u.f = float32_div(u.f, tmp, &env->spe_status);
2142
2143 return u.l;
2144 }
2145
2146 static always_inline uint32_t _do_efscfuf (uint32_t val)
2147 {
2148 CPU_FloatU u;
2149 float32 tmp;
2150
2151 u.f = uint32_to_float32(val, &env->spe_status);
2152 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2153 u.f = float32_div(u.f, tmp, &env->spe_status);
2154
2155 return u.l;
2156 }
2157
2158 static always_inline int32_t _do_efsctsf (uint32_t val)
2159 {
2160 CPU_FloatU u;
2161 float32 tmp;
2162
2163 u.l = val;
2164 /* NaN are not treated the same way IEEE 754 does */
2165 if (unlikely(isnan(u.f)))
2166 return 0;
2167 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2168 u.f = float32_mul(u.f, tmp, &env->spe_status);
2169
2170 return float32_to_int32(u.f, &env->spe_status);
2171 }
2172
2173 static always_inline uint32_t _do_efsctuf (uint32_t val)
2174 {
2175 CPU_FloatU u;
2176 float32 tmp;
2177
2178 u.l = val;
2179 /* NaN are not treated the same way IEEE 754 does */
2180 if (unlikely(isnan(u.f)))
2181 return 0;
2182 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2183 u.f = float32_mul(u.f, tmp, &env->spe_status);
2184
2185 return float32_to_uint32(u.f, &env->spe_status);
2186 }
2187
2188 static always_inline int32_t _do_efsctsfz (uint32_t val)
2189 {
2190 CPU_FloatU u;
2191 float32 tmp;
2192
2193 u.l = val;
2194 /* NaN are not treated the same way IEEE 754 does */
2195 if (unlikely(isnan(u.f)))
2196 return 0;
2197 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2198 u.f = float32_mul(u.f, tmp, &env->spe_status);
2199
2200 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
2201 }
2202
2203 static always_inline uint32_t _do_efsctufz (uint32_t val)
2204 {
2205 CPU_FloatU u;
2206 float32 tmp;
2207
2208 u.l = val;
2209 /* NaN are not treated the same way IEEE 754 does */
2210 if (unlikely(isnan(u.f)))
2211 return 0;
2212 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2213 u.f = float32_mul(u.f, tmp, &env->spe_status);
2214
2215 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
2216 }
2217
2218 void do_efscfsf (void)
2219 {
2220 T0_64 = _do_efscfsf(T0_64);
2221 }
2222
2223 void do_efscfuf (void)
2224 {
2225 T0_64 = _do_efscfuf(T0_64);
2226 }
2227
2228 void do_efsctsf (void)
2229 {
2230 T0_64 = _do_efsctsf(T0_64);
2231 }
2232
2233 void do_efsctuf (void)
2234 {
2235 T0_64 = _do_efsctuf(T0_64);
2236 }
2237
2238 void do_efsctsfz (void)
2239 {
2240 T0_64 = _do_efsctsfz(T0_64);
2241 }
2242
2243 void do_efsctufz (void)
2244 {
2245 T0_64 = _do_efsctufz(T0_64);
2246 }
2247
2248 /* Double precision floating point helpers */
2249 static always_inline int _do_efdcmplt (uint64_t op1, uint64_t op2)
2250 {
2251 /* XXX: TODO: test special values (NaN, infinites, ...) */
2252 return _do_efdtstlt(op1, op2);
2253 }
2254
2255 static always_inline int _do_efdcmpgt (uint64_t op1, uint64_t op2)
2256 {
2257 /* XXX: TODO: test special values (NaN, infinites, ...) */
2258 return _do_efdtstgt(op1, op2);
2259 }
2260
2261 static always_inline int _do_efdcmpeq (uint64_t op1, uint64_t op2)
2262 {
2263 /* XXX: TODO: test special values (NaN, infinites, ...) */
2264 return _do_efdtsteq(op1, op2);
2265 }
2266
2267 void do_efdcmplt (void)
2268 {
2269 T0 = _do_efdcmplt(T0_64, T1_64);
2270 }
2271
2272 void do_efdcmpgt (void)
2273 {
2274 T0 = _do_efdcmpgt(T0_64, T1_64);
2275 }
2276
2277 void do_efdcmpeq (void)
2278 {
2279 T0 = _do_efdcmpeq(T0_64, T1_64);
2280 }
2281
2282 /* Double precision floating-point conversion to/from integer */
2283 static always_inline uint64_t _do_efdcfsi (int64_t val)
2284 {
2285 CPU_DoubleU u;
2286
2287 u.d = int64_to_float64(val, &env->spe_status);
2288
2289 return u.ll;
2290 }
2291
2292 static always_inline uint64_t _do_efdcfui (uint64_t val)
2293 {
2294 CPU_DoubleU u;
2295
2296 u.d = uint64_to_float64(val, &env->spe_status);
2297
2298 return u.ll;
2299 }
2300
2301 static always_inline int64_t _do_efdctsi (uint64_t val)
2302 {
2303 CPU_DoubleU u;
2304
2305 u.ll = val;
2306 /* NaN are not treated the same way IEEE 754 does */
2307 if (unlikely(isnan(u.d)))
2308 return 0;
2309
2310 return float64_to_int64(u.d, &env->spe_status);
2311 }
2312
2313 static always_inline uint64_t _do_efdctui (uint64_t val)
2314 {
2315 CPU_DoubleU u;
2316
2317 u.ll = val;
2318 /* NaN are not treated the same way IEEE 754 does */
2319 if (unlikely(isnan(u.d)))
2320 return 0;
2321
2322 return float64_to_uint64(u.d, &env->spe_status);
2323 }
2324
2325 static always_inline int64_t _do_efdctsiz (uint64_t val)
2326 {
2327 CPU_DoubleU u;
2328
2329 u.ll = val;
2330 /* NaN are not treated the same way IEEE 754 does */
2331 if (unlikely(isnan(u.d)))
2332 return 0;
2333
2334 return float64_to_int64_round_to_zero(u.d, &env->spe_status);
2335 }
2336
2337 static always_inline uint64_t _do_efdctuiz (uint64_t val)
2338 {
2339 CPU_DoubleU u;
2340
2341 u.ll = val;
2342 /* NaN are not treated the same way IEEE 754 does */
2343 if (unlikely(isnan(u.d)))
2344 return 0;
2345
2346 return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
2347 }
2348
2349 void do_efdcfsi (void)
2350 {
2351 T0_64 = _do_efdcfsi(T0_64);
2352 }
2353
2354 void do_efdcfui (void)
2355 {
2356 T0_64 = _do_efdcfui(T0_64);
2357 }
2358
2359 void do_efdctsi (void)
2360 {
2361 T0_64 = _do_efdctsi(T0_64);
2362 }
2363
2364 void do_efdctui (void)
2365 {
2366 T0_64 = _do_efdctui(T0_64);
2367 }
2368
2369 void do_efdctsiz (void)
2370 {
2371 T0_64 = _do_efdctsiz(T0_64);
2372 }
2373
2374 void do_efdctuiz (void)
2375 {
2376 T0_64 = _do_efdctuiz(T0_64);
2377 }
2378
2379 /* Double precision floating-point conversion to/from fractional */
2380 static always_inline uint64_t _do_efdcfsf (int64_t val)
2381 {
2382 CPU_DoubleU u;
2383 float64 tmp;
2384
2385 u.d = int32_to_float64(val, &env->spe_status);
2386 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2387 u.d = float64_div(u.d, tmp, &env->spe_status);
2388
2389 return u.ll;
2390 }
2391
2392 static always_inline uint64_t _do_efdcfuf (uint64_t val)
2393 {
2394 CPU_DoubleU u;
2395 float64 tmp;
2396
2397 u.d = uint32_to_float64(val, &env->spe_status);
2398 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2399 u.d = float64_div(u.d, tmp, &env->spe_status);
2400
2401 return u.ll;
2402 }
2403
2404 static always_inline int64_t _do_efdctsf (uint64_t val)
2405 {
2406 CPU_DoubleU u;
2407 float64 tmp;
2408
2409 u.ll = val;
2410 /* NaN are not treated the same way IEEE 754 does */
2411 if (unlikely(isnan(u.d)))
2412 return 0;
2413 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2414 u.d = float64_mul(u.d, tmp, &env->spe_status);
2415
2416 return float64_to_int32(u.d, &env->spe_status);
2417 }
2418
2419 static always_inline uint64_t _do_efdctuf (uint64_t val)
2420 {
2421 CPU_DoubleU u;
2422 float64 tmp;
2423
2424 u.ll = val;
2425 /* NaN are not treated the same way IEEE 754 does */
2426 if (unlikely(isnan(u.d)))
2427 return 0;
2428 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2429 u.d = float64_mul(u.d, tmp, &env->spe_status);
2430
2431 return float64_to_uint32(u.d, &env->spe_status);
2432 }
2433
2434 static always_inline int64_t _do_efdctsfz (uint64_t val)
2435 {
2436 CPU_DoubleU u;
2437 float64 tmp;
2438
2439 u.ll = val;
2440 /* NaN are not treated the same way IEEE 754 does */
2441 if (unlikely(isnan(u.d)))
2442 return 0;
2443 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2444 u.d = float64_mul(u.d, tmp, &env->spe_status);
2445
2446 return float64_to_int32_round_to_zero(u.d, &env->spe_status);
2447 }
2448
2449 static always_inline uint64_t _do_efdctufz (uint64_t val)
2450 {
2451 CPU_DoubleU u;
2452 float64 tmp;
2453
2454 u.ll = val;
2455 /* NaN are not treated the same way IEEE 754 does */
2456 if (unlikely(isnan(u.d)))
2457 return 0;
2458 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2459 u.d = float64_mul(u.d, tmp, &env->spe_status);
2460
2461 return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
2462 }
2463
2464 void do_efdcfsf (void)
2465 {
2466 T0_64 = _do_efdcfsf(T0_64);
2467 }
2468
2469 void do_efdcfuf (void)
2470 {
2471 T0_64 = _do_efdcfuf(T0_64);
2472 }
2473
2474 void do_efdctsf (void)
2475 {
2476 T0_64 = _do_efdctsf(T0_64);
2477 }
2478
2479 void do_efdctuf (void)
2480 {
2481 T0_64 = _do_efdctuf(T0_64);
2482 }
2483
2484 void do_efdctsfz (void)
2485 {
2486 T0_64 = _do_efdctsfz(T0_64);
2487 }
2488
2489 void do_efdctufz (void)
2490 {
2491 T0_64 = _do_efdctufz(T0_64);
2492 }
2493
2494 /* Floating point conversion between single and double precision */
2495 static always_inline uint32_t _do_efscfd (uint64_t val)
2496 {
2497 CPU_DoubleU u1;
2498 CPU_FloatU u2;
2499
2500 u1.ll = val;
2501 u2.f = float64_to_float32(u1.d, &env->spe_status);
2502
2503 return u2.l;
2504 }
2505
2506 static always_inline uint64_t _do_efdcfs (uint32_t val)
2507 {
2508 CPU_DoubleU u2;
2509 CPU_FloatU u1;
2510
2511 u1.l = val;
2512 u2.d = float32_to_float64(u1.f, &env->spe_status);
2513
2514 return u2.ll;
2515 }
2516
2517 void do_efscfd (void)
2518 {
2519 T0_64 = _do_efscfd(T0_64);
2520 }
2521
2522 void do_efdcfs (void)
2523 {
2524 T0_64 = _do_efdcfs(T0_64);
2525 }
2526
2527 /* Single precision fixed-point vector arithmetic */
2528 /* evfsabs */
2529 DO_SPE_OP1(fsabs);
2530 /* evfsnabs */
2531 DO_SPE_OP1(fsnabs);
2532 /* evfsneg */
2533 DO_SPE_OP1(fsneg);
2534 /* evfsadd */
2535 DO_SPE_OP2(fsadd);
2536 /* evfssub */
2537 DO_SPE_OP2(fssub);
2538 /* evfsmul */
2539 DO_SPE_OP2(fsmul);
2540 /* evfsdiv */
2541 DO_SPE_OP2(fsdiv);
2542
2543 /* Single-precision floating-point comparisons */
2544 static always_inline int _do_efscmplt (uint32_t op1, uint32_t op2)
2545 {
2546 /* XXX: TODO: test special values (NaN, infinites, ...) */
2547 return _do_efststlt(op1, op2);
2548 }
2549
2550 static always_inline int _do_efscmpgt (uint32_t op1, uint32_t op2)
2551 {
2552 /* XXX: TODO: test special values (NaN, infinites, ...) */
2553 return _do_efststgt(op1, op2);
2554 }
2555
2556 static always_inline int _do_efscmpeq (uint32_t op1, uint32_t op2)
2557 {
2558 /* XXX: TODO: test special values (NaN, infinites, ...) */
2559 return _do_efststeq(op1, op2);
2560 }
2561
2562 void do_efscmplt (void)
2563 {
2564 T0 = _do_efscmplt(T0_64, T1_64);
2565 }
2566
2567 void do_efscmpgt (void)
2568 {
2569 T0 = _do_efscmpgt(T0_64, T1_64);
2570 }
2571
2572 void do_efscmpeq (void)
2573 {
2574 T0 = _do_efscmpeq(T0_64, T1_64);
2575 }
2576
2577 /* Single-precision floating-point vector comparisons */
2578 /* evfscmplt */
2579 DO_SPE_CMP(fscmplt);
2580 /* evfscmpgt */
2581 DO_SPE_CMP(fscmpgt);
2582 /* evfscmpeq */
2583 DO_SPE_CMP(fscmpeq);
2584 /* evfststlt */
2585 DO_SPE_CMP(fststlt);
2586 /* evfststgt */
2587 DO_SPE_CMP(fststgt);
2588 /* evfststeq */
2589 DO_SPE_CMP(fststeq);
2590
2591 /* Single-precision floating-point vector conversions */
2592 /* evfscfsi */
2593 DO_SPE_OP1(fscfsi);
2594 /* evfscfui */
2595 DO_SPE_OP1(fscfui);
2596 /* evfscfuf */
2597 DO_SPE_OP1(fscfuf);
2598 /* evfscfsf */
2599 DO_SPE_OP1(fscfsf);
2600 /* evfsctsi */
2601 DO_SPE_OP1(fsctsi);
2602 /* evfsctui */
2603 DO_SPE_OP1(fsctui);
2604 /* evfsctsiz */
2605 DO_SPE_OP1(fsctsiz);
2606 /* evfsctuiz */
2607 DO_SPE_OP1(fsctuiz);
2608 /* evfsctsf */
2609 DO_SPE_OP1(fsctsf);
2610 /* evfsctuf */
2611 DO_SPE_OP1(fsctuf);
2612
2613 /*****************************************************************************/
2614 /* Softmmu support */
2615 #if !defined (CONFIG_USER_ONLY)
2616
2617 #define MMUSUFFIX _mmu
2618
2619 #define SHIFT 0
2620 #include "softmmu_template.h"
2621
2622 #define SHIFT 1
2623 #include "softmmu_template.h"
2624
2625 #define SHIFT 2
2626 #include "softmmu_template.h"
2627
2628 #define SHIFT 3
2629 #include "softmmu_template.h"
2630
2631 /* try to fill the TLB and return an exception if error. If retaddr is
2632 NULL, it means that the function was called in C code (i.e. not
2633 from generated code or from helper.c) */
2634 /* XXX: fix it to restore all registers */
2635 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
2636 {
2637 TranslationBlock *tb;
2638 CPUState *saved_env;
2639 unsigned long pc;
2640 int ret;
2641
2642 /* XXX: hack to restore env in all cases, even if not called from
2643 generated code */
2644 saved_env = env;
2645 env = cpu_single_env;
2646 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
2647 if (unlikely(ret != 0)) {
2648 if (likely(retaddr)) {
2649 /* now we have a real cpu fault */
2650 pc = (unsigned long)retaddr;
2651 tb = tb_find_pc(pc);
2652 if (likely(tb)) {
2653 /* the PC is inside the translated code. It means that we have
2654 a virtual CPU fault */
2655 cpu_restore_state(tb, env, pc, NULL);
2656 }
2657 }
2658 do_raise_exception_err(env->exception_index, env->error_code);
2659 }
2660 env = saved_env;
2661 }
2662
2663 /* Software driven TLBs management */
2664 /* PowerPC 602/603 software TLB load instructions helpers */
2665 void do_load_6xx_tlb (int is_code)
2666 {
2667 target_ulong RPN, CMP, EPN;
2668 int way;
2669
2670 RPN = env->spr[SPR_RPA];
2671 if (is_code) {
2672 CMP = env->spr[SPR_ICMP];
2673 EPN = env->spr[SPR_IMISS];
2674 } else {
2675 CMP = env->spr[SPR_DCMP];
2676 EPN = env->spr[SPR_DMISS];
2677 }
2678 way = (env->spr[SPR_SRR1] >> 17) & 1;
2679 #if defined (DEBUG_SOFTWARE_TLB)
2680 if (loglevel != 0) {
2681 fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX
2682 " PTE1 " ADDRX " way %d\n",
2683 __func__, T0, EPN, CMP, RPN, way);
2684 }
2685 #endif
2686 /* Store this TLB */
2687 ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
2688 way, is_code, CMP, RPN);
2689 }
2690
2691 void do_load_74xx_tlb (int is_code)
2692 {
2693 target_ulong RPN, CMP, EPN;
2694 int way;
2695
2696 RPN = env->spr[SPR_PTELO];
2697 CMP = env->spr[SPR_PTEHI];
2698 EPN = env->spr[SPR_TLBMISS] & ~0x3;
2699 way = env->spr[SPR_TLBMISS] & 0x3;
2700 #if defined (DEBUG_SOFTWARE_TLB)
2701 if (loglevel != 0) {
2702 fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX
2703 " PTE1 " ADDRX " way %d\n",
2704 __func__, T0, EPN, CMP, RPN, way);
2705 }
2706 #endif
2707 /* Store this TLB */
2708 ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
2709 way, is_code, CMP, RPN);
2710 }
2711
2712 static always_inline target_ulong booke_tlb_to_page_size (int size)
2713 {
2714 return 1024 << (2 * size);
2715 }
2716
2717 static always_inline int booke_page_size_to_tlb (target_ulong page_size)
2718 {
2719 int size;
2720
2721 switch (page_size) {
2722 case 0x00000400UL:
2723 size = 0x0;
2724 break;
2725 case 0x00001000UL:
2726 size = 0x1;
2727 break;
2728 case 0x00004000UL:
2729 size = 0x2;
2730 break;
2731 case 0x00010000UL:
2732 size = 0x3;
2733 break;
2734 case 0x00040000UL:
2735 size = 0x4;
2736 break;
2737 case 0x00100000UL:
2738 size = 0x5;
2739 break;
2740 case 0x00400000UL:
2741 size = 0x6;
2742 break;
2743 case 0x01000000UL:
2744 size = 0x7;
2745 break;
2746 case 0x04000000UL:
2747 size = 0x8;
2748 break;
2749 case 0x10000000UL:
2750 size = 0x9;
2751 break;
2752 case 0x40000000UL:
2753 size = 0xA;
2754 break;
2755 #if defined (TARGET_PPC64)
2756 case 0x000100000000ULL:
2757 size = 0xB;
2758 break;
2759 case 0x000400000000ULL:
2760 size = 0xC;
2761 break;
2762 case 0x001000000000ULL:
2763 size = 0xD;
2764 break;
2765 case 0x004000000000ULL:
2766 size = 0xE;
2767 break;
2768 case 0x010000000000ULL:
2769 size = 0xF;
2770 break;
2771 #endif
2772 default:
2773 size = -1;
2774 break;
2775 }
2776
2777 return size;
2778 }
2779
2780 /* Helpers for 4xx TLB management */
2781 void do_4xx_tlbre_lo (void)
2782 {
2783 ppcemb_tlb_t *tlb;
2784 int size;
2785
2786 T0 &= 0x3F;
2787 tlb = &env->tlb[T0].tlbe;
2788 T0 = tlb->EPN;
2789 if (tlb->prot & PAGE_VALID)
2790 T0 |= 0x400;
2791 size = booke_page_size_to_tlb(tlb->size);
2792 if (size < 0 || size > 0x7)
2793 size = 1;
2794 T0 |= size << 7;
2795 env->spr[SPR_40x_PID] = tlb->PID;
2796 }
2797
2798 void do_4xx_tlbre_hi (void)
2799 {
2800 ppcemb_tlb_t *tlb;
2801
2802 T0 &= 0x3F;
2803 tlb = &env->tlb[T0].tlbe;
2804 T0 = tlb->RPN;
2805 if (tlb->prot & PAGE_EXEC)
2806 T0 |= 0x200;
2807 if (tlb->prot & PAGE_WRITE)
2808 T0 |= 0x100;
2809 }
2810
2811 void do_4xx_tlbwe_hi (void)
2812 {
2813 ppcemb_tlb_t *tlb;
2814 target_ulong page, end;
2815
2816 #if defined (DEBUG_SOFTWARE_TLB)
2817 if (loglevel != 0) {
2818 fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1);
2819 }
2820 #endif
2821 T0 &= 0x3F;
2822 tlb = &env->tlb[T0].tlbe;
2823 /* Invalidate previous TLB (if it's valid) */
2824 if (tlb->prot & PAGE_VALID) {
2825 end = tlb->EPN + tlb->size;
2826 #if defined (DEBUG_SOFTWARE_TLB)
2827 if (loglevel != 0) {
2828 fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
2829 " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2830 }
2831 #endif
2832 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2833 tlb_flush_page(env, page);
2834 }
2835 tlb->size = booke_tlb_to_page_size((T1 >> 7) & 0x7);
2836 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2837 * If this ever occurs, one should use the ppcemb target instead
2838 * of the ppc or ppc64 one
2839 */
2840 if ((T1 & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
2841 cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
2842 "are not supported (%d)\n",
2843 tlb->size, TARGET_PAGE_SIZE, (int)((T1 >> 7) & 0x7));
2844 }
2845 tlb->EPN = T1 & ~(tlb->size - 1);
2846 if (T1 & 0x40)
2847 tlb->prot |= PAGE_VALID;
2848 else
2849 tlb->prot &= ~PAGE_VALID;
2850 if (T1 & 0x20) {
2851 /* XXX: TO BE FIXED */
2852 cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
2853 }
2854 tlb->PID = env->spr[SPR_40x_PID]; /* PID */
2855 tlb->attr = T1 & 0xFF;
2856 #if defined (DEBUG_SOFTWARE_TLB)
2857 if (loglevel != 0) {
2858 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2859 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2860 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
2861 tlb->prot & PAGE_READ ? 'r' : '-',
2862 tlb->prot & PAGE_WRITE ? 'w' : '-',
2863 tlb->prot & PAGE_EXEC ? 'x' : '-',
2864 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2865 }
2866 #endif
2867 /* Invalidate new TLB (if valid) */
2868 if (tlb->prot & PAGE_VALID) {
2869 end = tlb->EPN + tlb->size;
2870 #if defined (DEBUG_SOFTWARE_TLB)
2871 if (loglevel != 0) {
2872 fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
2873 " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2874 }
2875 #endif
2876 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2877 tlb_flush_page(env, page);
2878 }
2879 }
2880
2881 void do_4xx_tlbwe_lo (void)
2882 {
2883 ppcemb_tlb_t *tlb;
2884
2885 #if defined (DEBUG_SOFTWARE_TLB)
2886 if (loglevel != 0) {
2887 fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1);
2888 }
2889 #endif
2890 T0 &= 0x3F;
2891 tlb = &env->tlb[T0].tlbe;
2892 tlb->RPN = T1 & 0xFFFFFC00;
2893 tlb->prot = PAGE_READ;
2894 if (T1 & 0x200)
2895 tlb->prot |= PAGE_EXEC;
2896 if (T1 & 0x100)
2897 tlb->prot |= PAGE_WRITE;
2898 #if defined (DEBUG_SOFTWARE_TLB)
2899 if (loglevel != 0) {
2900 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2901 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2902 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
2903 tlb->prot & PAGE_READ ? 'r' : '-',
2904 tlb->prot & PAGE_WRITE ? 'w' : '-',
2905 tlb->prot & PAGE_EXEC ? 'x' : '-',
2906 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2907 }
2908 #endif
2909 }
2910
2911 /* PowerPC 440 TLB management */
2912 void do_440_tlbwe (int word)
2913 {
2914 ppcemb_tlb_t *tlb;
2915 target_ulong EPN, RPN, size;
2916 int do_flush_tlbs;
2917
2918 #if defined (DEBUG_SOFTWARE_TLB)
2919 if (loglevel != 0) {
2920 fprintf(logfile, "%s word %d T0 " TDX " T1 " TDX "\n",
2921 __func__, word, T0, T1);
2922 }
2923 #endif
2924 do_flush_tlbs = 0;
2925 T0 &= 0x3F;
2926 tlb = &env->tlb[T0].tlbe;
2927 switch (word) {
2928 default:
2929 /* Just here to please gcc */
2930 case 0:
2931 EPN = T1 & 0xFFFFFC00;
2932 if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
2933 do_flush_tlbs = 1;
2934 tlb->EPN = EPN;
2935 size = booke_tlb_to_page_size((T1 >> 4) & 0xF);
2936 if ((tlb->prot & PAGE_VALID) && tlb->size < size)
2937 do_flush_tlbs = 1;
2938 tlb->size = size;
2939 tlb->attr &= ~0x1;
2940 tlb->attr |= (T1 >> 8) & 1;
2941 if (T1 & 0x200) {
2942 tlb->prot |= PAGE_VALID;
2943 } else {
2944 if (tlb->prot & PAGE_VALID) {
2945 tlb->prot &= ~PAGE_VALID;
2946 do_flush_tlbs = 1;
2947 }
2948 }
2949 tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
2950 if (do_flush_tlbs)
2951 tlb_flush(env, 1);
2952 break;
2953 case 1:
2954 RPN = T1 & 0xFFFFFC0F;
2955 if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
2956 tlb_flush(env, 1);
2957 tlb->RPN = RPN;
2958 break;
2959 case 2:
2960 tlb->attr = (tlb->attr & 0x1) | (T1 & 0x0000FF00);
2961 tlb->prot = tlb->prot & PAGE_VALID;
2962 if (T1 & 0x1)
2963 tlb->prot |= PAGE_READ << 4;
2964 if (T1 & 0x2)
2965 tlb->prot |= PAGE_WRITE << 4;
2966 if (T1 & 0x4)
2967 tlb->prot |= PAGE_EXEC << 4;
2968 if (T1 & 0x8)
2969 tlb->prot |= PAGE_READ;
2970 if (T1 & 0x10)
2971 tlb->prot |= PAGE_WRITE;
2972 if (T1 & 0x20)
2973 tlb->prot |= PAGE_EXEC;
2974 break;
2975 }
2976 }
2977
2978 void do_440_tlbre (int word)
2979 {
2980 ppcemb_tlb_t *tlb;
2981 int size;
2982
2983 T0 &= 0x3F;
2984 tlb = &env->tlb[T0].tlbe;
2985 switch (word) {
2986 default:
2987 /* Just here to please gcc */
2988 case 0:
2989 T0 = tlb->EPN;
2990 size = booke_page_size_to_tlb(tlb->size);
2991 if (size < 0 || size > 0xF)
2992 size = 1;
2993 T0 |= size << 4;
2994 if (tlb->attr & 0x1)
2995 T0 |= 0x100;
2996 if (tlb->prot & PAGE_VALID)
2997 T0 |= 0x200;
2998 env->spr[SPR_440_MMUCR] &= ~0x000000FF;
2999 env->spr[SPR_440_MMUCR] |= tlb->PID;
3000 break;
3001 case 1:
3002 T0 = tlb->RPN;
3003 break;
3004 case 2:
3005 T0 = tlb->attr & ~0x1;
3006 if (tlb->prot & (PAGE_READ << 4))
3007 T0 |= 0x1;
3008 if (tlb->prot & (PAGE_WRITE << 4))
3009 T0 |= 0x2;
3010 if (tlb->prot & (PAGE_EXEC << 4))
3011 T0 |= 0x4;
3012 if (tlb->prot & PAGE_READ)
3013 T0 |= 0x8;
3014 if (tlb->prot & PAGE_WRITE)
3015 T0 |= 0x10;
3016 if (tlb->prot & PAGE_EXEC)
3017 T0 |= 0x20;
3018 break;
3019 }
3020 }
3021 #endif /* !CONFIG_USER_ONLY */
Qemu copy for testing