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1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25
26 #include "cpu.h"
27 #include "exec-all.h"
28 #include "disas.h"
29 #include "tcg-op.h"
30 #include "qemu-common.h"
31
32 #include "helper.h"
33 #define GEN_HELPER 1
34 #include "helper.h"
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define DO_SINGLE_STEP
42 //#define PPC_DEBUG_DISAS
43 //#define DO_PPC_STATISTICS
44
45 /*****************************************************************************/
46 /* Code translation helpers */
47
48 /* global register indexes */
49 static TCGv_ptr cpu_env;
50 static char cpu_reg_names[10*3 + 22*4 /* GPR */
51 #if !defined(TARGET_PPC64)
52 + 10*4 + 22*5 /* SPE GPRh */
53 #endif
54 + 10*4 + 22*5 /* FPR */
55 + 2*(10*6 + 22*7) /* AVRh, AVRl */
56 + 8*5 /* CRF */];
57 static TCGv cpu_gpr[32];
58 #if !defined(TARGET_PPC64)
59 static TCGv cpu_gprh[32];
60 #endif
61 static TCGv_i64 cpu_fpr[32];
62 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
63 static TCGv_i32 cpu_crf[8];
64 static TCGv cpu_nip;
65 static TCGv cpu_msr;
66 static TCGv cpu_ctr;
67 static TCGv cpu_lr;
68 static TCGv cpu_xer;
69 static TCGv cpu_reserve;
70 static TCGv_i32 cpu_fpscr;
71 static TCGv_i32 cpu_access_type;
72
73 #include "gen-icount.h"
74
75 void ppc_translate_init(void)
76 {
77 int i;
78 char* p;
79 static int done_init = 0;
80
81 if (done_init)
82 return;
83
84 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
85
86 p = cpu_reg_names;
87
88 for (i = 0; i < 8; i++) {
89 sprintf(p, "crf%d", i);
90 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
91 offsetof(CPUState, crf[i]), p);
92 p += 5;
93 }
94
95 for (i = 0; i < 32; i++) {
96 sprintf(p, "r%d", i);
97 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
98 offsetof(CPUState, gpr[i]), p);
99 p += (i < 10) ? 3 : 4;
100 #if !defined(TARGET_PPC64)
101 sprintf(p, "r%dH", i);
102 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
103 offsetof(CPUState, gprh[i]), p);
104 p += (i < 10) ? 4 : 5;
105 #endif
106
107 sprintf(p, "fp%d", i);
108 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
109 offsetof(CPUState, fpr[i]), p);
110 p += (i < 10) ? 4 : 5;
111
112 sprintf(p, "avr%dH", i);
113 #ifdef WORDS_BIGENDIAN
114 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUState, avr[i].u64[0]), p);
116 #else
117 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
118 offsetof(CPUState, avr[i].u64[1]), p);
119 #endif
120 p += (i < 10) ? 6 : 7;
121
122 sprintf(p, "avr%dL", i);
123 #ifdef WORDS_BIGENDIAN
124 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
125 offsetof(CPUState, avr[i].u64[1]), p);
126 #else
127 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
128 offsetof(CPUState, avr[i].u64[0]), p);
129 #endif
130 p += (i < 10) ? 6 : 7;
131 }
132
133 cpu_nip = tcg_global_mem_new(TCG_AREG0,
134 offsetof(CPUState, nip), "nip");
135
136 cpu_msr = tcg_global_mem_new(TCG_AREG0,
137 offsetof(CPUState, msr), "msr");
138
139 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
140 offsetof(CPUState, ctr), "ctr");
141
142 cpu_lr = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUState, lr), "lr");
144
145 cpu_xer = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUState, xer), "xer");
147
148 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUState, reserve), "reserve");
150
151 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
152 offsetof(CPUState, fpscr), "fpscr");
153
154 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
155 offsetof(CPUState, access_type), "access_type");
156
157 /* register helpers */
158 #define GEN_HELPER 2
159 #include "helper.h"
160
161 done_init = 1;
162 }
163
164 /* internal defines */
165 typedef struct DisasContext {
166 struct TranslationBlock *tb;
167 target_ulong nip;
168 uint32_t opcode;
169 uint32_t exception;
170 /* Routine used to access memory */
171 int mem_idx;
172 int access_type;
173 /* Translation flags */
174 int le_mode;
175 #if defined(TARGET_PPC64)
176 int sf_mode;
177 #endif
178 int fpu_enabled;
179 int altivec_enabled;
180 int spe_enabled;
181 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
182 int singlestep_enabled;
183 } DisasContext;
184
185 struct opc_handler_t {
186 /* invalid bits */
187 uint32_t inval;
188 /* instruction type */
189 uint64_t type;
190 /* handler */
191 void (*handler)(DisasContext *ctx);
192 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
193 const char *oname;
194 #endif
195 #if defined(DO_PPC_STATISTICS)
196 uint64_t count;
197 #endif
198 };
199
200 static always_inline void gen_reset_fpstatus (void)
201 {
202 #ifdef CONFIG_SOFTFLOAT
203 gen_helper_reset_fpstatus();
204 #endif
205 }
206
207 static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
208 {
209 TCGv_i32 t0 = tcg_temp_new_i32();
210
211 if (set_fprf != 0) {
212 /* This case might be optimized later */
213 tcg_gen_movi_i32(t0, 1);
214 gen_helper_compute_fprf(t0, arg, t0);
215 if (unlikely(set_rc)) {
216 tcg_gen_mov_i32(cpu_crf[1], t0);
217 }
218 gen_helper_float_check_status();
219 } else if (unlikely(set_rc)) {
220 /* We always need to compute fpcc */
221 tcg_gen_movi_i32(t0, 0);
222 gen_helper_compute_fprf(t0, arg, t0);
223 tcg_gen_mov_i32(cpu_crf[1], t0);
224 }
225
226 tcg_temp_free_i32(t0);
227 }
228
229 static always_inline void gen_set_access_type (DisasContext *ctx, int access_type)
230 {
231 if (ctx->access_type != access_type) {
232 tcg_gen_movi_i32(cpu_access_type, access_type);
233 ctx->access_type = access_type;
234 }
235 }
236
237 static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
238 {
239 #if defined(TARGET_PPC64)
240 if (ctx->sf_mode)
241 tcg_gen_movi_tl(cpu_nip, nip);
242 else
243 #endif
244 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
245 }
246
247 static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error)
248 {
249 TCGv_i32 t0, t1;
250 if (ctx->exception == POWERPC_EXCP_NONE) {
251 gen_update_nip(ctx, ctx->nip);
252 }
253 t0 = tcg_const_i32(excp);
254 t1 = tcg_const_i32(error);
255 gen_helper_raise_exception_err(t0, t1);
256 tcg_temp_free_i32(t0);
257 tcg_temp_free_i32(t1);
258 ctx->exception = (excp);
259 }
260
261 static always_inline void gen_exception (DisasContext *ctx, uint32_t excp)
262 {
263 TCGv_i32 t0;
264 if (ctx->exception == POWERPC_EXCP_NONE) {
265 gen_update_nip(ctx, ctx->nip);
266 }
267 t0 = tcg_const_i32(excp);
268 gen_helper_raise_exception(t0);
269 tcg_temp_free_i32(t0);
270 ctx->exception = (excp);
271 }
272
273 static always_inline void gen_debug_exception (DisasContext *ctx)
274 {
275 TCGv_i32 t0;
276 gen_update_nip(ctx, ctx->nip);
277 t0 = tcg_const_i32(EXCP_DEBUG);
278 gen_helper_raise_exception(t0);
279 tcg_temp_free_i32(t0);
280 }
281
282 static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error)
283 {
284 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
285 }
286
287 /* Stop translation */
288 static always_inline void gen_stop_exception (DisasContext *ctx)
289 {
290 gen_update_nip(ctx, ctx->nip);
291 ctx->exception = POWERPC_EXCP_STOP;
292 }
293
294 /* No need to update nip here, as execution flow will change */
295 static always_inline void gen_sync_exception (DisasContext *ctx)
296 {
297 ctx->exception = POWERPC_EXCP_SYNC;
298 }
299
300 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
301 static void gen_##name (DisasContext *ctx); \
302 GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
303 static void gen_##name (DisasContext *ctx)
304
305 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
306 static void gen_##name (DisasContext *ctx); \
307 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
308 static void gen_##name (DisasContext *ctx)
309
310 typedef struct opcode_t {
311 unsigned char opc1, opc2, opc3;
312 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
313 unsigned char pad[5];
314 #else
315 unsigned char pad[1];
316 #endif
317 opc_handler_t handler;
318 const char *oname;
319 } opcode_t;
320
321 /*****************************************************************************/
322 /*** Instruction decoding ***/
323 #define EXTRACT_HELPER(name, shift, nb) \
324 static always_inline uint32_t name (uint32_t opcode) \
325 { \
326 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
327 }
328
329 #define EXTRACT_SHELPER(name, shift, nb) \
330 static always_inline int32_t name (uint32_t opcode) \
331 { \
332 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
333 }
334
335 /* Opcode part 1 */
336 EXTRACT_HELPER(opc1, 26, 6);
337 /* Opcode part 2 */
338 EXTRACT_HELPER(opc2, 1, 5);
339 /* Opcode part 3 */
340 EXTRACT_HELPER(opc3, 6, 5);
341 /* Update Cr0 flags */
342 EXTRACT_HELPER(Rc, 0, 1);
343 /* Destination */
344 EXTRACT_HELPER(rD, 21, 5);
345 /* Source */
346 EXTRACT_HELPER(rS, 21, 5);
347 /* First operand */
348 EXTRACT_HELPER(rA, 16, 5);
349 /* Second operand */
350 EXTRACT_HELPER(rB, 11, 5);
351 /* Third operand */
352 EXTRACT_HELPER(rC, 6, 5);
353 /*** Get CRn ***/
354 EXTRACT_HELPER(crfD, 23, 3);
355 EXTRACT_HELPER(crfS, 18, 3);
356 EXTRACT_HELPER(crbD, 21, 5);
357 EXTRACT_HELPER(crbA, 16, 5);
358 EXTRACT_HELPER(crbB, 11, 5);
359 /* SPR / TBL */
360 EXTRACT_HELPER(_SPR, 11, 10);
361 static always_inline uint32_t SPR (uint32_t opcode)
362 {
363 uint32_t sprn = _SPR(opcode);
364
365 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
366 }
367 /*** Get constants ***/
368 EXTRACT_HELPER(IMM, 12, 8);
369 /* 16 bits signed immediate value */
370 EXTRACT_SHELPER(SIMM, 0, 16);
371 /* 16 bits unsigned immediate value */
372 EXTRACT_HELPER(UIMM, 0, 16);
373 /* 5 bits signed immediate value */
374 EXTRACT_HELPER(SIMM5, 16, 5);
375 /* 5 bits signed immediate value */
376 EXTRACT_HELPER(UIMM5, 16, 5);
377 /* Bit count */
378 EXTRACT_HELPER(NB, 11, 5);
379 /* Shift count */
380 EXTRACT_HELPER(SH, 11, 5);
381 /* Vector shift count */
382 EXTRACT_HELPER(VSH, 6, 4);
383 /* Mask start */
384 EXTRACT_HELPER(MB, 6, 5);
385 /* Mask end */
386 EXTRACT_HELPER(ME, 1, 5);
387 /* Trap operand */
388 EXTRACT_HELPER(TO, 21, 5);
389
390 EXTRACT_HELPER(CRM, 12, 8);
391 EXTRACT_HELPER(FM, 17, 8);
392 EXTRACT_HELPER(SR, 16, 4);
393 EXTRACT_HELPER(FPIMM, 12, 4);
394
395 /*** Jump target decoding ***/
396 /* Displacement */
397 EXTRACT_SHELPER(d, 0, 16);
398 /* Immediate address */
399 static always_inline target_ulong LI (uint32_t opcode)
400 {
401 return (opcode >> 0) & 0x03FFFFFC;
402 }
403
404 static always_inline uint32_t BD (uint32_t opcode)
405 {
406 return (opcode >> 0) & 0xFFFC;
407 }
408
409 EXTRACT_HELPER(BO, 21, 5);
410 EXTRACT_HELPER(BI, 16, 5);
411 /* Absolute/relative address */
412 EXTRACT_HELPER(AA, 1, 1);
413 /* Link */
414 EXTRACT_HELPER(LK, 0, 1);
415
416 /* Create a mask between <start> and <end> bits */
417 static always_inline target_ulong MASK (uint32_t start, uint32_t end)
418 {
419 target_ulong ret;
420
421 #if defined(TARGET_PPC64)
422 if (likely(start == 0)) {
423 ret = UINT64_MAX << (63 - end);
424 } else if (likely(end == 63)) {
425 ret = UINT64_MAX >> start;
426 }
427 #else
428 if (likely(start == 0)) {
429 ret = UINT32_MAX << (31 - end);
430 } else if (likely(end == 31)) {
431 ret = UINT32_MAX >> start;
432 }
433 #endif
434 else {
435 ret = (((target_ulong)(-1ULL)) >> (start)) ^
436 (((target_ulong)(-1ULL) >> (end)) >> 1);
437 if (unlikely(start > end))
438 return ~ret;
439 }
440
441 return ret;
442 }
443
444 /*****************************************************************************/
445 /* PowerPC Instructions types definitions */
446 enum {
447 PPC_NONE = 0x0000000000000000ULL,
448 /* PowerPC base instructions set */
449 PPC_INSNS_BASE = 0x0000000000000001ULL,
450 /* integer operations instructions */
451 #define PPC_INTEGER PPC_INSNS_BASE
452 /* flow control instructions */
453 #define PPC_FLOW PPC_INSNS_BASE
454 /* virtual memory instructions */
455 #define PPC_MEM PPC_INSNS_BASE
456 /* ld/st with reservation instructions */
457 #define PPC_RES PPC_INSNS_BASE
458 /* spr/msr access instructions */
459 #define PPC_MISC PPC_INSNS_BASE
460 /* Deprecated instruction sets */
461 /* Original POWER instruction set */
462 PPC_POWER = 0x0000000000000002ULL,
463 /* POWER2 instruction set extension */
464 PPC_POWER2 = 0x0000000000000004ULL,
465 /* Power RTC support */
466 PPC_POWER_RTC = 0x0000000000000008ULL,
467 /* Power-to-PowerPC bridge (601) */
468 PPC_POWER_BR = 0x0000000000000010ULL,
469 /* 64 bits PowerPC instruction set */
470 PPC_64B = 0x0000000000000020ULL,
471 /* New 64 bits extensions (PowerPC 2.0x) */
472 PPC_64BX = 0x0000000000000040ULL,
473 /* 64 bits hypervisor extensions */
474 PPC_64H = 0x0000000000000080ULL,
475 /* New wait instruction (PowerPC 2.0x) */
476 PPC_WAIT = 0x0000000000000100ULL,
477 /* Time base mftb instruction */
478 PPC_MFTB = 0x0000000000000200ULL,
479
480 /* Fixed-point unit extensions */
481 /* PowerPC 602 specific */
482 PPC_602_SPEC = 0x0000000000000400ULL,
483 /* isel instruction */
484 PPC_ISEL = 0x0000000000000800ULL,
485 /* popcntb instruction */
486 PPC_POPCNTB = 0x0000000000001000ULL,
487 /* string load / store */
488 PPC_STRING = 0x0000000000002000ULL,
489
490 /* Floating-point unit extensions */
491 /* Optional floating point instructions */
492 PPC_FLOAT = 0x0000000000010000ULL,
493 /* New floating-point extensions (PowerPC 2.0x) */
494 PPC_FLOAT_EXT = 0x0000000000020000ULL,
495 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
496 PPC_FLOAT_FRES = 0x0000000000080000ULL,
497 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
498 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
499 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
500 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
501
502 /* Vector/SIMD extensions */
503 /* Altivec support */
504 PPC_ALTIVEC = 0x0000000001000000ULL,
505 /* PowerPC 2.03 SPE extension */
506 PPC_SPE = 0x0000000002000000ULL,
507 /* PowerPC 2.03 SPE floating-point extension */
508 PPC_SPEFPU = 0x0000000004000000ULL,
509
510 /* Optional memory control instructions */
511 PPC_MEM_TLBIA = 0x0000000010000000ULL,
512 PPC_MEM_TLBIE = 0x0000000020000000ULL,
513 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
514 /* sync instruction */
515 PPC_MEM_SYNC = 0x0000000080000000ULL,
516 /* eieio instruction */
517 PPC_MEM_EIEIO = 0x0000000100000000ULL,
518
519 /* Cache control instructions */
520 PPC_CACHE = 0x0000000200000000ULL,
521 /* icbi instruction */
522 PPC_CACHE_ICBI = 0x0000000400000000ULL,
523 /* dcbz instruction with fixed cache line size */
524 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
525 /* dcbz instruction with tunable cache line size */
526 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
527 /* dcba instruction */
528 PPC_CACHE_DCBA = 0x0000002000000000ULL,
529 /* Freescale cache locking instructions */
530 PPC_CACHE_LOCK = 0x0000004000000000ULL,
531
532 /* MMU related extensions */
533 /* external control instructions */
534 PPC_EXTERN = 0x0000010000000000ULL,
535 /* segment register access instructions */
536 PPC_SEGMENT = 0x0000020000000000ULL,
537 /* PowerPC 6xx TLB management instructions */
538 PPC_6xx_TLB = 0x0000040000000000ULL,
539 /* PowerPC 74xx TLB management instructions */
540 PPC_74xx_TLB = 0x0000080000000000ULL,
541 /* PowerPC 40x TLB management instructions */
542 PPC_40x_TLB = 0x0000100000000000ULL,
543 /* segment register access instructions for PowerPC 64 "bridge" */
544 PPC_SEGMENT_64B = 0x0000200000000000ULL,
545 /* SLB management */
546 PPC_SLBI = 0x0000400000000000ULL,
547
548 /* Embedded PowerPC dedicated instructions */
549 PPC_WRTEE = 0x0001000000000000ULL,
550 /* PowerPC 40x exception model */
551 PPC_40x_EXCP = 0x0002000000000000ULL,
552 /* PowerPC 405 Mac instructions */
553 PPC_405_MAC = 0x0004000000000000ULL,
554 /* PowerPC 440 specific instructions */
555 PPC_440_SPEC = 0x0008000000000000ULL,
556 /* BookE (embedded) PowerPC specification */
557 PPC_BOOKE = 0x0010000000000000ULL,
558 /* mfapidi instruction */
559 PPC_MFAPIDI = 0x0020000000000000ULL,
560 /* tlbiva instruction */
561 PPC_TLBIVA = 0x0040000000000000ULL,
562 /* tlbivax instruction */
563 PPC_TLBIVAX = 0x0080000000000000ULL,
564 /* PowerPC 4xx dedicated instructions */
565 PPC_4xx_COMMON = 0x0100000000000000ULL,
566 /* PowerPC 40x ibct instructions */
567 PPC_40x_ICBT = 0x0200000000000000ULL,
568 /* rfmci is not implemented in all BookE PowerPC */
569 PPC_RFMCI = 0x0400000000000000ULL,
570 /* rfdi instruction */
571 PPC_RFDI = 0x0800000000000000ULL,
572 /* DCR accesses */
573 PPC_DCR = 0x1000000000000000ULL,
574 /* DCR extended accesse */
575 PPC_DCRX = 0x2000000000000000ULL,
576 /* user-mode DCR access, implemented in PowerPC 460 */
577 PPC_DCRUX = 0x4000000000000000ULL,
578 };
579
580 /*****************************************************************************/
581 /* PowerPC instructions table */
582 #if HOST_LONG_BITS == 64
583 #define OPC_ALIGN 8
584 #else
585 #define OPC_ALIGN 4
586 #endif
587 #if defined(__APPLE__)
588 #define OPCODES_SECTION \
589 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
590 #else
591 #define OPCODES_SECTION \
592 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
593 #endif
594
595 #if defined(DO_PPC_STATISTICS)
596 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
597 OPCODES_SECTION opcode_t opc_##name = { \
598 .opc1 = op1, \
599 .opc2 = op2, \
600 .opc3 = op3, \
601 .pad = { 0, }, \
602 .handler = { \
603 .inval = invl, \
604 .type = _typ, \
605 .handler = &gen_##name, \
606 .oname = stringify(name), \
607 }, \
608 .oname = stringify(name), \
609 }
610 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
611 OPCODES_SECTION opcode_t opc_##name = { \
612 .opc1 = op1, \
613 .opc2 = op2, \
614 .opc3 = op3, \
615 .pad = { 0, }, \
616 .handler = { \
617 .inval = invl, \
618 .type = _typ, \
619 .handler = &gen_##name, \
620 .oname = onam, \
621 }, \
622 .oname = onam, \
623 }
624 #else
625 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
626 OPCODES_SECTION opcode_t opc_##name = { \
627 .opc1 = op1, \
628 .opc2 = op2, \
629 .opc3 = op3, \
630 .pad = { 0, }, \
631 .handler = { \
632 .inval = invl, \
633 .type = _typ, \
634 .handler = &gen_##name, \
635 }, \
636 .oname = stringify(name), \
637 }
638 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
639 OPCODES_SECTION opcode_t opc_##name = { \
640 .opc1 = op1, \
641 .opc2 = op2, \
642 .opc3 = op3, \
643 .pad = { 0, }, \
644 .handler = { \
645 .inval = invl, \
646 .type = _typ, \
647 .handler = &gen_##name, \
648 }, \
649 .oname = onam, \
650 }
651 #endif
652
653 #define GEN_OPCODE_MARK(name) \
654 OPCODES_SECTION opcode_t opc_##name = { \
655 .opc1 = 0xFF, \
656 .opc2 = 0xFF, \
657 .opc3 = 0xFF, \
658 .pad = { 0, }, \
659 .handler = { \
660 .inval = 0x00000000, \
661 .type = 0x00, \
662 .handler = NULL, \
663 }, \
664 .oname = stringify(name), \
665 }
666
667 /* SPR load/store helpers */
668 static always_inline void gen_load_spr(TCGv t, int reg)
669 {
670 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
671 }
672
673 static always_inline void gen_store_spr(int reg, TCGv t)
674 {
675 tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
676 }
677
678 /* Start opcode list */
679 GEN_OPCODE_MARK(start);
680
681 /* Invalid instruction */
682 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
683 {
684 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
685 }
686
687 static opc_handler_t invalid_handler = {
688 .inval = 0xFFFFFFFF,
689 .type = PPC_NONE,
690 .handler = gen_invalid,
691 };
692
693 /*** Integer comparison ***/
694
695 static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
696 {
697 int l1, l2, l3;
698
699 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
700 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
701 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
702
703 l1 = gen_new_label();
704 l2 = gen_new_label();
705 l3 = gen_new_label();
706 if (s) {
707 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
708 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
709 } else {
710 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
711 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
712 }
713 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
714 tcg_gen_br(l3);
715 gen_set_label(l1);
716 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
717 tcg_gen_br(l3);
718 gen_set_label(l2);
719 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
720 gen_set_label(l3);
721 }
722
723 static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
724 {
725 TCGv t0 = tcg_const_local_tl(arg1);
726 gen_op_cmp(arg0, t0, s, crf);
727 tcg_temp_free(t0);
728 }
729
730 #if defined(TARGET_PPC64)
731 static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
732 {
733 TCGv t0, t1;
734 t0 = tcg_temp_local_new();
735 t1 = tcg_temp_local_new();
736 if (s) {
737 tcg_gen_ext32s_tl(t0, arg0);
738 tcg_gen_ext32s_tl(t1, arg1);
739 } else {
740 tcg_gen_ext32u_tl(t0, arg0);
741 tcg_gen_ext32u_tl(t1, arg1);
742 }
743 gen_op_cmp(t0, t1, s, crf);
744 tcg_temp_free(t1);
745 tcg_temp_free(t0);
746 }
747
748 static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
749 {
750 TCGv t0 = tcg_const_local_tl(arg1);
751 gen_op_cmp32(arg0, t0, s, crf);
752 tcg_temp_free(t0);
753 }
754 #endif
755
756 static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
757 {
758 #if defined(TARGET_PPC64)
759 if (!(ctx->sf_mode))
760 gen_op_cmpi32(reg, 0, 1, 0);
761 else
762 #endif
763 gen_op_cmpi(reg, 0, 1, 0);
764 }
765
766 /* cmp */
767 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
768 {
769 #if defined(TARGET_PPC64)
770 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
771 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
772 1, crfD(ctx->opcode));
773 else
774 #endif
775 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
776 1, crfD(ctx->opcode));
777 }
778
779 /* cmpi */
780 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
781 {
782 #if defined(TARGET_PPC64)
783 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
784 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
785 1, crfD(ctx->opcode));
786 else
787 #endif
788 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
789 1, crfD(ctx->opcode));
790 }
791
792 /* cmpl */
793 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
794 {
795 #if defined(TARGET_PPC64)
796 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
797 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
798 0, crfD(ctx->opcode));
799 else
800 #endif
801 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
802 0, crfD(ctx->opcode));
803 }
804
805 /* cmpli */
806 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
807 {
808 #if defined(TARGET_PPC64)
809 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
810 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
811 0, crfD(ctx->opcode));
812 else
813 #endif
814 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
815 0, crfD(ctx->opcode));
816 }
817
818 /* isel (PowerPC 2.03 specification) */
819 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
820 {
821 int l1, l2;
822 uint32_t bi = rC(ctx->opcode);
823 uint32_t mask;
824 TCGv_i32 t0;
825
826 l1 = gen_new_label();
827 l2 = gen_new_label();
828
829 mask = 1 << (3 - (bi & 0x03));
830 t0 = tcg_temp_new_i32();
831 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
832 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
833 if (rA(ctx->opcode) == 0)
834 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
835 else
836 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
837 tcg_gen_br(l2);
838 gen_set_label(l1);
839 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
840 gen_set_label(l2);
841 tcg_temp_free_i32(t0);
842 }
843
844 /*** Integer arithmetic ***/
845
846 static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
847 {
848 int l1;
849 TCGv t0;
850
851 l1 = gen_new_label();
852 /* Start with XER OV disabled, the most likely case */
853 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
854 t0 = tcg_temp_local_new();
855 tcg_gen_xor_tl(t0, arg0, arg1);
856 #if defined(TARGET_PPC64)
857 if (!ctx->sf_mode)
858 tcg_gen_ext32s_tl(t0, t0);
859 #endif
860 if (sub)
861 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
862 else
863 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
864 tcg_gen_xor_tl(t0, arg1, arg2);
865 #if defined(TARGET_PPC64)
866 if (!ctx->sf_mode)
867 tcg_gen_ext32s_tl(t0, t0);
868 #endif
869 if (sub)
870 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
871 else
872 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
873 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
874 gen_set_label(l1);
875 tcg_temp_free(t0);
876 }
877
878 static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
879 {
880 int l1 = gen_new_label();
881
882 #if defined(TARGET_PPC64)
883 if (!(ctx->sf_mode)) {
884 TCGv t0, t1;
885 t0 = tcg_temp_new();
886 t1 = tcg_temp_new();
887
888 tcg_gen_ext32u_tl(t0, arg1);
889 tcg_gen_ext32u_tl(t1, arg2);
890 if (sub) {
891 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
892 } else {
893 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
894 }
895 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
896 gen_set_label(l1);
897 tcg_temp_free(t0);
898 tcg_temp_free(t1);
899 } else
900 #endif
901 {
902 if (sub) {
903 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
904 } else {
905 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
906 }
907 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
908 gen_set_label(l1);
909 }
910 }
911
912 /* Common add function */
913 static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
914 int add_ca, int compute_ca, int compute_ov)
915 {
916 TCGv t0, t1;
917
918 if ((!compute_ca && !compute_ov) ||
919 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
920 t0 = ret;
921 } else {
922 t0 = tcg_temp_local_new();
923 }
924
925 if (add_ca) {
926 t1 = tcg_temp_local_new();
927 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
928 tcg_gen_shri_tl(t1, t1, XER_CA);
929 }
930
931 if (compute_ca && compute_ov) {
932 /* Start with XER CA and OV disabled, the most likely case */
933 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
934 } else if (compute_ca) {
935 /* Start with XER CA disabled, the most likely case */
936 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
937 } else if (compute_ov) {
938 /* Start with XER OV disabled, the most likely case */
939 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
940 }
941
942 tcg_gen_add_tl(t0, arg1, arg2);
943
944 if (compute_ca) {
945 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
946 }
947 if (add_ca) {
948 tcg_gen_add_tl(t0, t0, t1);
949 gen_op_arith_compute_ca(ctx, t0, t1, 0);
950 tcg_temp_free(t1);
951 }
952 if (compute_ov) {
953 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
954 }
955
956 if (unlikely(Rc(ctx->opcode) != 0))
957 gen_set_Rc0(ctx, t0);
958
959 if (!TCGV_EQUAL(t0, ret)) {
960 tcg_gen_mov_tl(ret, t0);
961 tcg_temp_free(t0);
962 }
963 }
964 /* Add functions with two operands */
965 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
966 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
967 { \
968 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
969 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
970 add_ca, compute_ca, compute_ov); \
971 }
972 /* Add functions with one operand and one immediate */
973 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
974 add_ca, compute_ca, compute_ov) \
975 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
976 { \
977 TCGv t0 = tcg_const_local_tl(const_val); \
978 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
979 cpu_gpr[rA(ctx->opcode)], t0, \
980 add_ca, compute_ca, compute_ov); \
981 tcg_temp_free(t0); \
982 }
983
984 /* add add. addo addo. */
985 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
986 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
987 /* addc addc. addco addco. */
988 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
989 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
990 /* adde adde. addeo addeo. */
991 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
992 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
993 /* addme addme. addmeo addmeo. */
994 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
995 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
996 /* addze addze. addzeo addzeo.*/
997 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
998 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
999 /* addi */
1000 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1001 {
1002 target_long simm = SIMM(ctx->opcode);
1003
1004 if (rA(ctx->opcode) == 0) {
1005 /* li case */
1006 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1007 } else {
1008 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1009 }
1010 }
1011 /* addic addic.*/
1012 static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1013 int compute_Rc0)
1014 {
1015 target_long simm = SIMM(ctx->opcode);
1016
1017 /* Start with XER CA and OV disabled, the most likely case */
1018 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1019
1020 if (likely(simm != 0)) {
1021 TCGv t0 = tcg_temp_local_new();
1022 tcg_gen_addi_tl(t0, arg1, simm);
1023 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1024 tcg_gen_mov_tl(ret, t0);
1025 tcg_temp_free(t0);
1026 } else {
1027 tcg_gen_mov_tl(ret, arg1);
1028 }
1029 if (compute_Rc0) {
1030 gen_set_Rc0(ctx, ret);
1031 }
1032 }
1033 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1034 {
1035 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1036 }
1037 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1038 {
1039 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1040 }
1041 /* addis */
1042 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1043 {
1044 target_long simm = SIMM(ctx->opcode);
1045
1046 if (rA(ctx->opcode) == 0) {
1047 /* lis case */
1048 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1049 } else {
1050 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1051 }
1052 }
1053
1054 static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1055 int sign, int compute_ov)
1056 {
1057 int l1 = gen_new_label();
1058 int l2 = gen_new_label();
1059 TCGv_i32 t0 = tcg_temp_local_new_i32();
1060 TCGv_i32 t1 = tcg_temp_local_new_i32();
1061
1062 tcg_gen_trunc_tl_i32(t0, arg1);
1063 tcg_gen_trunc_tl_i32(t1, arg2);
1064 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
1065 if (sign) {
1066 int l3 = gen_new_label();
1067 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1068 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
1069 gen_set_label(l3);
1070 tcg_gen_div_i32(t0, t0, t1);
1071 } else {
1072 tcg_gen_divu_i32(t0, t0, t1);
1073 }
1074 if (compute_ov) {
1075 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1076 }
1077 tcg_gen_br(l2);
1078 gen_set_label(l1);
1079 if (sign) {
1080 tcg_gen_sari_i32(t0, t0, 31);
1081 } else {
1082 tcg_gen_movi_i32(t0, 0);
1083 }
1084 if (compute_ov) {
1085 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1086 }
1087 gen_set_label(l2);
1088 tcg_gen_extu_i32_tl(ret, t0);
1089 tcg_temp_free_i32(t0);
1090 tcg_temp_free_i32(t1);
1091 if (unlikely(Rc(ctx->opcode) != 0))
1092 gen_set_Rc0(ctx, ret);
1093 }
1094 /* Div functions */
1095 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1096 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1097 { \
1098 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1099 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1100 sign, compute_ov); \
1101 }
1102 /* divwu divwu. divwuo divwuo. */
1103 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1104 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1105 /* divw divw. divwo divwo. */
1106 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1107 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1108 #if defined(TARGET_PPC64)
1109 static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1110 int sign, int compute_ov)
1111 {
1112 int l1 = gen_new_label();
1113 int l2 = gen_new_label();
1114
1115 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1116 if (sign) {
1117 int l3 = gen_new_label();
1118 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1119 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1120 gen_set_label(l3);
1121 tcg_gen_div_i64(ret, arg1, arg2);
1122 } else {
1123 tcg_gen_divu_i64(ret, arg1, arg2);
1124 }
1125 if (compute_ov) {
1126 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1127 }
1128 tcg_gen_br(l2);
1129 gen_set_label(l1);
1130 if (sign) {
1131 tcg_gen_sari_i64(ret, arg1, 63);
1132 } else {
1133 tcg_gen_movi_i64(ret, 0);
1134 }
1135 if (compute_ov) {
1136 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1137 }
1138 gen_set_label(l2);
1139 if (unlikely(Rc(ctx->opcode) != 0))
1140 gen_set_Rc0(ctx, ret);
1141 }
1142 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1143 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1144 { \
1145 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1146 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1147 sign, compute_ov); \
1148 }
1149 /* divwu divwu. divwuo divwuo. */
1150 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1151 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1152 /* divw divw. divwo divwo. */
1153 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1154 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1155 #endif
1156
1157 /* mulhw mulhw. */
1158 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
1159 {
1160 TCGv_i64 t0, t1;
1161
1162 t0 = tcg_temp_new_i64();
1163 t1 = tcg_temp_new_i64();
1164 #if defined(TARGET_PPC64)
1165 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1166 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1167 tcg_gen_mul_i64(t0, t0, t1);
1168 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1169 #else
1170 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1171 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1172 tcg_gen_mul_i64(t0, t0, t1);
1173 tcg_gen_shri_i64(t0, t0, 32);
1174 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1175 #endif
1176 tcg_temp_free_i64(t0);
1177 tcg_temp_free_i64(t1);
1178 if (unlikely(Rc(ctx->opcode) != 0))
1179 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1180 }
1181 /* mulhwu mulhwu. */
1182 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
1183 {
1184 TCGv_i64 t0, t1;
1185
1186 t0 = tcg_temp_new_i64();
1187 t1 = tcg_temp_new_i64();
1188 #if defined(TARGET_PPC64)
1189 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1190 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1191 tcg_gen_mul_i64(t0, t0, t1);
1192 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1193 #else
1194 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1195 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1196 tcg_gen_mul_i64(t0, t0, t1);
1197 tcg_gen_shri_i64(t0, t0, 32);
1198 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1199 #endif
1200 tcg_temp_free_i64(t0);
1201 tcg_temp_free_i64(t1);
1202 if (unlikely(Rc(ctx->opcode) != 0))
1203 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1204 }
1205 /* mullw mullw. */
1206 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
1207 {
1208 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1209 cpu_gpr[rB(ctx->opcode)]);
1210 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1211 if (unlikely(Rc(ctx->opcode) != 0))
1212 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1213 }
1214 /* mullwo mullwo. */
1215 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
1216 {
1217 int l1;
1218 TCGv_i64 t0, t1;
1219
1220 t0 = tcg_temp_new_i64();
1221 t1 = tcg_temp_new_i64();
1222 l1 = gen_new_label();
1223 /* Start with XER OV disabled, the most likely case */
1224 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1225 #if defined(TARGET_PPC64)
1226 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1227 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1228 #else
1229 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1230 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1231 #endif
1232 tcg_gen_mul_i64(t0, t0, t1);
1233 #if defined(TARGET_PPC64)
1234 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1235 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1236 #else
1237 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1238 tcg_gen_ext32s_i64(t1, t0);
1239 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1240 #endif
1241 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1242 gen_set_label(l1);
1243 tcg_temp_free_i64(t0);
1244 tcg_temp_free_i64(t1);
1245 if (unlikely(Rc(ctx->opcode) != 0))
1246 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1247 }
1248 /* mulli */
1249 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1250 {
1251 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1252 SIMM(ctx->opcode));
1253 }
1254 #if defined(TARGET_PPC64)
1255 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1256 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1257 { \
1258 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
1259 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1260 if (unlikely(Rc(ctx->opcode) != 0)) \
1261 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1262 }
1263 /* mulhd mulhd. */
1264 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1265 /* mulhdu mulhdu. */
1266 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1267 /* mulld mulld. */
1268 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
1269 {
1270 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1271 cpu_gpr[rB(ctx->opcode)]);
1272 if (unlikely(Rc(ctx->opcode) != 0))
1273 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1274 }
1275 /* mulldo mulldo. */
1276 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
1277 #endif
1278
1279 /* neg neg. nego nego. */
1280 static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
1281 {
1282 int l1 = gen_new_label();
1283 int l2 = gen_new_label();
1284 TCGv t0 = tcg_temp_local_new();
1285 #if defined(TARGET_PPC64)
1286 if (ctx->sf_mode) {
1287 tcg_gen_mov_tl(t0, arg1);
1288 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1289 } else
1290 #endif
1291 {
1292 tcg_gen_ext32s_tl(t0, arg1);
1293 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1294 }
1295 tcg_gen_neg_tl(ret, arg1);
1296 if (ov_check) {
1297 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1298 }
1299 tcg_gen_br(l2);
1300 gen_set_label(l1);
1301 tcg_gen_mov_tl(ret, t0);
1302 if (ov_check) {
1303 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1304 }
1305 gen_set_label(l2);
1306 tcg_temp_free(t0);
1307 if (unlikely(Rc(ctx->opcode) != 0))
1308 gen_set_Rc0(ctx, ret);
1309 }
1310 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
1311 {
1312 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1313 }
1314 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
1315 {
1316 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1317 }
1318
1319 /* Common subf function */
1320 static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1321 int add_ca, int compute_ca, int compute_ov)
1322 {
1323 TCGv t0, t1;
1324
1325 if ((!compute_ca && !compute_ov) ||
1326 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
1327 t0 = ret;
1328 } else {
1329 t0 = tcg_temp_local_new();
1330 }
1331
1332 if (add_ca) {
1333 t1 = tcg_temp_local_new();
1334 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1335 tcg_gen_shri_tl(t1, t1, XER_CA);
1336 }
1337
1338 if (compute_ca && compute_ov) {
1339 /* Start with XER CA and OV disabled, the most likely case */
1340 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1341 } else if (compute_ca) {
1342 /* Start with XER CA disabled, the most likely case */
1343 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1344 } else if (compute_ov) {
1345 /* Start with XER OV disabled, the most likely case */
1346 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1347 }
1348
1349 if (add_ca) {
1350 tcg_gen_not_tl(t0, arg1);
1351 tcg_gen_add_tl(t0, t0, arg2);
1352 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1353 tcg_gen_add_tl(t0, t0, t1);
1354 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1355 tcg_temp_free(t1);
1356 } else {
1357 tcg_gen_sub_tl(t0, arg2, arg1);
1358 if (compute_ca) {
1359 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1360 }
1361 }
1362 if (compute_ov) {
1363 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1364 }
1365
1366 if (unlikely(Rc(ctx->opcode) != 0))
1367 gen_set_Rc0(ctx, t0);
1368
1369 if (!TCGV_EQUAL(t0, ret)) {
1370 tcg_gen_mov_tl(ret, t0);
1371 tcg_temp_free(t0);
1372 }
1373 }
1374 /* Sub functions with Two operands functions */
1375 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1376 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1377 { \
1378 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1379 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1380 add_ca, compute_ca, compute_ov); \
1381 }
1382 /* Sub functions with one operand and one immediate */
1383 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1384 add_ca, compute_ca, compute_ov) \
1385 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1386 { \
1387 TCGv t0 = tcg_const_local_tl(const_val); \
1388 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1389 cpu_gpr[rA(ctx->opcode)], t0, \
1390 add_ca, compute_ca, compute_ov); \
1391 tcg_temp_free(t0); \
1392 }
1393 /* subf subf. subfo subfo. */
1394 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1395 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1396 /* subfc subfc. subfco subfco. */
1397 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1398 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1399 /* subfe subfe. subfeo subfo. */
1400 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1401 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1402 /* subfme subfme. subfmeo subfmeo. */
1403 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1404 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1405 /* subfze subfze. subfzeo subfzeo.*/
1406 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1407 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1408 /* subfic */
1409 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1410 {
1411 /* Start with XER CA and OV disabled, the most likely case */
1412 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1413 TCGv t0 = tcg_temp_local_new();
1414 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1415 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1416 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1417 tcg_temp_free(t1);
1418 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1419 tcg_temp_free(t0);
1420 }
1421
1422 /*** Integer logical ***/
1423 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1424 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
1425 { \
1426 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1427 cpu_gpr[rB(ctx->opcode)]); \
1428 if (unlikely(Rc(ctx->opcode) != 0)) \
1429 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1430 }
1431
1432 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1433 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
1434 { \
1435 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1436 if (unlikely(Rc(ctx->opcode) != 0)) \
1437 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1438 }
1439
1440 /* and & and. */
1441 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1442 /* andc & andc. */
1443 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1444 /* andi. */
1445 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1446 {
1447 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1448 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1449 }
1450 /* andis. */
1451 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1452 {
1453 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1454 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1455 }
1456 /* cntlzw */
1457 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1458 {
1459 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1460 if (unlikely(Rc(ctx->opcode) != 0))
1461 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1462 }
1463 /* eqv & eqv. */
1464 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1465 /* extsb & extsb. */
1466 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1467 /* extsh & extsh. */
1468 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1469 /* nand & nand. */
1470 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1471 /* nor & nor. */
1472 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1473 /* or & or. */
1474 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1475 {
1476 int rs, ra, rb;
1477
1478 rs = rS(ctx->opcode);
1479 ra = rA(ctx->opcode);
1480 rb = rB(ctx->opcode);
1481 /* Optimisation for mr. ri case */
1482 if (rs != ra || rs != rb) {
1483 if (rs != rb)
1484 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1485 else
1486 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1487 if (unlikely(Rc(ctx->opcode) != 0))
1488 gen_set_Rc0(ctx, cpu_gpr[ra]);
1489 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1490 gen_set_Rc0(ctx, cpu_gpr[rs]);
1491 #if defined(TARGET_PPC64)
1492 } else {
1493 int prio = 0;
1494
1495 switch (rs) {
1496 case 1:
1497 /* Set process priority to low */
1498 prio = 2;
1499 break;
1500 case 6:
1501 /* Set process priority to medium-low */
1502 prio = 3;
1503 break;
1504 case 2:
1505 /* Set process priority to normal */
1506 prio = 4;
1507 break;
1508 #if !defined(CONFIG_USER_ONLY)
1509 case 31:
1510 if (ctx->mem_idx > 0) {
1511 /* Set process priority to very low */
1512 prio = 1;
1513 }
1514 break;
1515 case 5:
1516 if (ctx->mem_idx > 0) {
1517 /* Set process priority to medium-hight */
1518 prio = 5;
1519 }
1520 break;
1521 case 3:
1522 if (ctx->mem_idx > 0) {
1523 /* Set process priority to high */
1524 prio = 6;
1525 }
1526 break;
1527 case 7:
1528 if (ctx->mem_idx > 1) {
1529 /* Set process priority to very high */
1530 prio = 7;
1531 }
1532 break;
1533 #endif
1534 default:
1535 /* nop */
1536 break;
1537 }
1538 if (prio) {
1539 TCGv t0 = tcg_temp_new();
1540 gen_load_spr(t0, SPR_PPR);
1541 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1542 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1543 gen_store_spr(SPR_PPR, t0);
1544 tcg_temp_free(t0);
1545 }
1546 #endif
1547 }
1548 }
1549 /* orc & orc. */
1550 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1551 /* xor & xor. */
1552 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1553 {
1554 /* Optimisation for "set to zero" case */
1555 if (rS(ctx->opcode) != rB(ctx->opcode))
1556 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1557 else
1558 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1559 if (unlikely(Rc(ctx->opcode) != 0))
1560 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1561 }
1562 /* ori */
1563 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1564 {
1565 target_ulong uimm = UIMM(ctx->opcode);
1566
1567 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1568 /* NOP */
1569 /* XXX: should handle special NOPs for POWER series */
1570 return;
1571 }
1572 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1573 }
1574 /* oris */
1575 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1576 {
1577 target_ulong uimm = UIMM(ctx->opcode);
1578
1579 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1580 /* NOP */
1581 return;
1582 }
1583 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1584 }
1585 /* xori */
1586 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1587 {
1588 target_ulong uimm = UIMM(ctx->opcode);
1589
1590 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1591 /* NOP */
1592 return;
1593 }
1594 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1595 }
1596 /* xoris */
1597 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1598 {
1599 target_ulong uimm = UIMM(ctx->opcode);
1600
1601 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1602 /* NOP */
1603 return;
1604 }
1605 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1606 }
1607 /* popcntb : PowerPC 2.03 specification */
1608 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
1609 {
1610 #if defined(TARGET_PPC64)
1611 if (ctx->sf_mode)
1612 gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1613 else
1614 #endif
1615 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1616 }
1617
1618 #if defined(TARGET_PPC64)
1619 /* extsw & extsw. */
1620 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1621 /* cntlzd */
1622 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1623 {
1624 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1625 if (unlikely(Rc(ctx->opcode) != 0))
1626 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1627 }
1628 #endif
1629
1630 /*** Integer rotate ***/
1631 /* rlwimi & rlwimi. */
1632 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1633 {
1634 uint32_t mb, me, sh;
1635
1636 mb = MB(ctx->opcode);
1637 me = ME(ctx->opcode);
1638 sh = SH(ctx->opcode);
1639 if (likely(sh == 0 && mb == 0 && me == 31)) {
1640 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1641 } else {
1642 target_ulong mask;
1643 TCGv t1;
1644 TCGv t0 = tcg_temp_new();
1645 #if defined(TARGET_PPC64)
1646 TCGv_i32 t2 = tcg_temp_new_i32();
1647 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1648 tcg_gen_rotli_i32(t2, t2, sh);
1649 tcg_gen_extu_i32_i64(t0, t2);
1650 tcg_temp_free_i32(t2);
1651 #else
1652 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1653 #endif
1654 #if defined(TARGET_PPC64)
1655 mb += 32;
1656 me += 32;
1657 #endif
1658 mask = MASK(mb, me);
1659 t1 = tcg_temp_new();
1660 tcg_gen_andi_tl(t0, t0, mask);
1661 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1662 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1663 tcg_temp_free(t0);
1664 tcg_temp_free(t1);
1665 }
1666 if (unlikely(Rc(ctx->opcode) != 0))
1667 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1668 }
1669 /* rlwinm & rlwinm. */
1670 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1671 {
1672 uint32_t mb, me, sh;
1673
1674 sh = SH(ctx->opcode);
1675 mb = MB(ctx->opcode);
1676 me = ME(ctx->opcode);
1677
1678 if (likely(mb == 0 && me == (31 - sh))) {
1679 if (likely(sh == 0)) {
1680 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1681 } else {
1682 TCGv t0 = tcg_temp_new();
1683 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1684 tcg_gen_shli_tl(t0, t0, sh);
1685 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1686 tcg_temp_free(t0);
1687 }
1688 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1689 TCGv t0 = tcg_temp_new();
1690 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1691 tcg_gen_shri_tl(t0, t0, mb);
1692 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1693 tcg_temp_free(t0);
1694 } else {
1695 TCGv t0 = tcg_temp_new();
1696 #if defined(TARGET_PPC64)
1697 TCGv_i32 t1 = tcg_temp_new_i32();
1698 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1699 tcg_gen_rotli_i32(t1, t1, sh);
1700 tcg_gen_extu_i32_i64(t0, t1);
1701 tcg_temp_free_i32(t1);
1702 #else
1703 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1704 #endif
1705 #if defined(TARGET_PPC64)
1706 mb += 32;
1707 me += 32;
1708 #endif
1709 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1710 tcg_temp_free(t0);
1711 }
1712 if (unlikely(Rc(ctx->opcode) != 0))
1713 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1714 }
1715 /* rlwnm & rlwnm. */
1716 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1717 {
1718 uint32_t mb, me;
1719 TCGv t0;
1720 #if defined(TARGET_PPC64)
1721 TCGv_i32 t1, t2;
1722 #endif
1723
1724 mb = MB(ctx->opcode);
1725 me = ME(ctx->opcode);
1726 t0 = tcg_temp_new();
1727 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1728 #if defined(TARGET_PPC64)
1729 t1 = tcg_temp_new_i32();
1730 t2 = tcg_temp_new_i32();
1731 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1732 tcg_gen_trunc_i64_i32(t2, t0);
1733 tcg_gen_rotl_i32(t1, t1, t2);
1734 tcg_gen_extu_i32_i64(t0, t1);
1735 tcg_temp_free_i32(t1);
1736 tcg_temp_free_i32(t2);
1737 #else
1738 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1739 #endif
1740 if (unlikely(mb != 0 || me != 31)) {
1741 #if defined(TARGET_PPC64)
1742 mb += 32;
1743 me += 32;
1744 #endif
1745 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1746 } else {
1747 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1748 }
1749 tcg_temp_free(t0);
1750 if (unlikely(Rc(ctx->opcode) != 0))
1751 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1752 }
1753
1754 #if defined(TARGET_PPC64)
1755 #define GEN_PPC64_R2(name, opc1, opc2) \
1756 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1757 { \
1758 gen_##name(ctx, 0); \
1759 } \
1760 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1761 PPC_64B) \
1762 { \
1763 gen_##name(ctx, 1); \
1764 }
1765 #define GEN_PPC64_R4(name, opc1, opc2) \
1766 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1767 { \
1768 gen_##name(ctx, 0, 0); \
1769 } \
1770 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1771 PPC_64B) \
1772 { \
1773 gen_##name(ctx, 0, 1); \
1774 } \
1775 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1776 PPC_64B) \
1777 { \
1778 gen_##name(ctx, 1, 0); \
1779 } \
1780 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1781 PPC_64B) \
1782 { \
1783 gen_##name(ctx, 1, 1); \
1784 }
1785
1786 static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1787 uint32_t me, uint32_t sh)
1788 {
1789 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1790 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1791 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1792 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1793 } else {
1794 TCGv t0 = tcg_temp_new();
1795 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1796 if (likely(mb == 0 && me == 63)) {
1797 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1798 } else {
1799 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1800 }
1801 tcg_temp_free(t0);
1802 }
1803 if (unlikely(Rc(ctx->opcode) != 0))
1804 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1805 }
1806 /* rldicl - rldicl. */
1807 static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1808 {
1809 uint32_t sh, mb;
1810
1811 sh = SH(ctx->opcode) | (shn << 5);
1812 mb = MB(ctx->opcode) | (mbn << 5);
1813 gen_rldinm(ctx, mb, 63, sh);
1814 }
1815 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1816 /* rldicr - rldicr. */
1817 static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1818 {
1819 uint32_t sh, me;
1820
1821 sh = SH(ctx->opcode) | (shn << 5);
1822 me = MB(ctx->opcode) | (men << 5);
1823 gen_rldinm(ctx, 0, me, sh);
1824 }
1825 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1826 /* rldic - rldic. */
1827 static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1828 {
1829 uint32_t sh, mb;
1830
1831 sh = SH(ctx->opcode) | (shn << 5);
1832 mb = MB(ctx->opcode) | (mbn << 5);
1833 gen_rldinm(ctx, mb, 63 - sh, sh);
1834 }
1835 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1836
1837 static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1838 uint32_t me)
1839 {
1840 TCGv t0;
1841
1842 mb = MB(ctx->opcode);
1843 me = ME(ctx->opcode);
1844 t0 = tcg_temp_new();
1845 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1846 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1847 if (unlikely(mb != 0 || me != 63)) {
1848 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1849 } else {
1850 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1851 }
1852 tcg_temp_free(t0);
1853 if (unlikely(Rc(ctx->opcode) != 0))
1854 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1855 }
1856
1857 /* rldcl - rldcl. */
1858 static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
1859 {
1860 uint32_t mb;
1861
1862 mb = MB(ctx->opcode) | (mbn << 5);
1863 gen_rldnm(ctx, mb, 63);
1864 }
1865 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1866 /* rldcr - rldcr. */
1867 static always_inline void gen_rldcr (DisasContext *ctx, int men)
1868 {
1869 uint32_t me;
1870
1871 me = MB(ctx->opcode) | (men << 5);
1872 gen_rldnm(ctx, 0, me);
1873 }
1874 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1875 /* rldimi - rldimi. */
1876 static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1877 {
1878 uint32_t sh, mb, me;
1879
1880 sh = SH(ctx->opcode) | (shn << 5);
1881 mb = MB(ctx->opcode) | (mbn << 5);
1882 me = 63 - sh;
1883 if (unlikely(sh == 0 && mb == 0)) {
1884 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1885 } else {
1886 TCGv t0, t1;
1887 target_ulong mask;
1888
1889 t0 = tcg_temp_new();
1890 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1891 t1 = tcg_temp_new();
1892 mask = MASK(mb, me);
1893 tcg_gen_andi_tl(t0, t0, mask);
1894 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1895 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1896 tcg_temp_free(t0);
1897 tcg_temp_free(t1);
1898 }
1899 if (unlikely(Rc(ctx->opcode) != 0))
1900 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1901 }
1902 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1903 #endif
1904
1905 /*** Integer shift ***/
1906 /* slw & slw. */
1907 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1908 {
1909 TCGv t0;
1910 int l1, l2;
1911 l1 = gen_new_label();
1912 l2 = gen_new_label();
1913
1914 t0 = tcg_temp_local_new();
1915 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1916 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1917 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1918 tcg_gen_br(l2);
1919 gen_set_label(l1);
1920 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
1921 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1922 gen_set_label(l2);
1923 tcg_temp_free(t0);
1924 if (unlikely(Rc(ctx->opcode) != 0))
1925 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1926 }
1927 /* sraw & sraw. */
1928 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1929 {
1930 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1931 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1932 if (unlikely(Rc(ctx->opcode) != 0))
1933 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1934 }
1935 /* srawi & srawi. */
1936 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1937 {
1938 int sh = SH(ctx->opcode);
1939 if (sh != 0) {
1940 int l1, l2;
1941 TCGv t0;
1942 l1 = gen_new_label();
1943 l2 = gen_new_label();
1944 t0 = tcg_temp_local_new();
1945 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1946 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1947 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1948 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1949 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1950 tcg_gen_br(l2);
1951 gen_set_label(l1);
1952 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1953 gen_set_label(l2);
1954 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1955 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1956 tcg_temp_free(t0);
1957 } else {
1958 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1959 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1960 }
1961 if (unlikely(Rc(ctx->opcode) != 0))
1962 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1963 }
1964 /* srw & srw. */
1965 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1966 {
1967 TCGv t0, t1;
1968 int l1, l2;
1969 l1 = gen_new_label();
1970 l2 = gen_new_label();
1971
1972 t0 = tcg_temp_local_new();
1973 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1974 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1975 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1976 tcg_gen_br(l2);
1977 gen_set_label(l1);
1978 t1 = tcg_temp_new();
1979 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1980 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
1981 tcg_temp_free(t1);
1982 gen_set_label(l2);
1983 tcg_temp_free(t0);
1984 if (unlikely(Rc(ctx->opcode) != 0))
1985 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1986 }
1987 #if defined(TARGET_PPC64)
1988 /* sld & sld. */
1989 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
1990 {
1991 TCGv t0;
1992 int l1, l2;
1993 l1 = gen_new_label();
1994 l2 = gen_new_label();
1995
1996 t0 = tcg_temp_local_new();
1997 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
1998 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
1999 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2000 tcg_gen_br(l2);
2001 gen_set_label(l1);
2002 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2003 gen_set_label(l2);
2004 tcg_temp_free(t0);
2005 if (unlikely(Rc(ctx->opcode) != 0))
2006 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2007 }
2008 /* srad & srad. */
2009 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2010 {
2011 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
2012 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2013 if (unlikely(Rc(ctx->opcode) != 0))
2014 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2015 }
2016 /* sradi & sradi. */
2017 static always_inline void gen_sradi (DisasContext *ctx, int n)
2018 {
2019 int sh = SH(ctx->opcode) + (n << 5);
2020 if (sh != 0) {
2021 int l1, l2;
2022 TCGv t0;
2023 l1 = gen_new_label();
2024 l2 = gen_new_label();
2025 t0 = tcg_temp_local_new();
2026 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
2027 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2028 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2029 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
2030 tcg_gen_br(l2);
2031 gen_set_label(l1);
2032 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2033 gen_set_label(l2);
2034 tcg_temp_free(t0);
2035 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2036 } else {
2037 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2038 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2039 }
2040 if (unlikely(Rc(ctx->opcode) != 0))
2041 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2042 }
2043 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
2044 {
2045 gen_sradi(ctx, 0);
2046 }
2047 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
2048 {
2049 gen_sradi(ctx, 1);
2050 }
2051 /* srd & srd. */
2052 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2053 {
2054 TCGv t0;
2055 int l1, l2;
2056 l1 = gen_new_label();
2057 l2 = gen_new_label();
2058
2059 t0 = tcg_temp_local_new();
2060 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2061 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
2062 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2063 tcg_gen_br(l2);
2064 gen_set_label(l1);
2065 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2066 gen_set_label(l2);
2067 tcg_temp_free(t0);
2068 if (unlikely(Rc(ctx->opcode) != 0))
2069 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2070 }
2071 #endif
2072
2073 /*** Floating-Point arithmetic ***/
2074 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2075 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
2076 { \
2077 if (unlikely(!ctx->fpu_enabled)) { \
2078 gen_exception(ctx, POWERPC_EXCP_FPU); \
2079 return; \
2080 } \
2081 /* NIP cannot be restored if the memory exception comes from an helper */ \
2082 gen_update_nip(ctx, ctx->nip - 4); \
2083 gen_reset_fpstatus(); \
2084 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2085 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2086 if (isfloat) { \
2087 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2088 } \
2089 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2090 Rc(ctx->opcode) != 0); \
2091 }
2092
2093 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2094 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2095 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2096
2097 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2098 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2099 { \
2100 if (unlikely(!ctx->fpu_enabled)) { \
2101 gen_exception(ctx, POWERPC_EXCP_FPU); \
2102 return; \
2103 } \
2104 /* NIP cannot be restored if the memory exception comes from an helper */ \
2105 gen_update_nip(ctx, ctx->nip - 4); \
2106 gen_reset_fpstatus(); \
2107 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2108 cpu_fpr[rB(ctx->opcode)]); \
2109 if (isfloat) { \
2110 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2111 } \
2112 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2113 set_fprf, Rc(ctx->opcode) != 0); \
2114 }
2115 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2116 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2117 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2118
2119 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2120 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2121 { \
2122 if (unlikely(!ctx->fpu_enabled)) { \
2123 gen_exception(ctx, POWERPC_EXCP_FPU); \
2124 return; \
2125 } \
2126 /* NIP cannot be restored if the memory exception comes from an helper */ \
2127 gen_update_nip(ctx, ctx->nip - 4); \
2128 gen_reset_fpstatus(); \
2129 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2130 cpu_fpr[rC(ctx->opcode)]); \
2131 if (isfloat) { \
2132 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2133 } \
2134 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2135 set_fprf, Rc(ctx->opcode) != 0); \
2136 }
2137 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2138 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2139 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2140
2141 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2142 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
2143 { \
2144 if (unlikely(!ctx->fpu_enabled)) { \
2145 gen_exception(ctx, POWERPC_EXCP_FPU); \
2146 return; \
2147 } \
2148 /* NIP cannot be restored if the memory exception comes from an helper */ \
2149 gen_update_nip(ctx, ctx->nip - 4); \
2150 gen_reset_fpstatus(); \
2151 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2152 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2153 set_fprf, Rc(ctx->opcode) != 0); \
2154 }
2155
2156 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2157 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
2158 { \
2159 if (unlikely(!ctx->fpu_enabled)) { \
2160 gen_exception(ctx, POWERPC_EXCP_FPU); \
2161 return; \
2162 } \
2163 /* NIP cannot be restored if the memory exception comes from an helper */ \
2164 gen_update_nip(ctx, ctx->nip - 4); \
2165 gen_reset_fpstatus(); \
2166 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2167 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2168 set_fprf, Rc(ctx->opcode) != 0); \
2169 }
2170
2171 /* fadd - fadds */
2172 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2173 /* fdiv - fdivs */
2174 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2175 /* fmul - fmuls */
2176 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2177
2178 /* fre */
2179 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2180
2181 /* fres */
2182 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2183
2184 /* frsqrte */
2185 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2186
2187 /* frsqrtes */
2188 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
2189 {
2190 if (unlikely(!ctx->fpu_enabled)) {
2191 gen_exception(ctx, POWERPC_EXCP_FPU);
2192 return;
2193 }
2194 /* NIP cannot be restored if the memory exception comes from an helper */
2195 gen_update_nip(ctx, ctx->nip - 4);
2196 gen_reset_fpstatus();
2197 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2198 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2199 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2200 }
2201
2202 /* fsel */
2203 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2204 /* fsub - fsubs */
2205 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2206 /* Optional: */
2207 /* fsqrt */
2208 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2209 {
2210 if (unlikely(!ctx->fpu_enabled)) {
2211 gen_exception(ctx, POWERPC_EXCP_FPU);
2212 return;
2213 }
2214 /* NIP cannot be restored if the memory exception comes from an helper */
2215 gen_update_nip(ctx, ctx->nip - 4);
2216 gen_reset_fpstatus();
2217 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2218 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2219 }
2220
2221 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2222 {
2223 if (unlikely(!ctx->fpu_enabled)) {
2224 gen_exception(ctx, POWERPC_EXCP_FPU);
2225 return;
2226 }
2227 /* NIP cannot be restored if the memory exception comes from an helper */
2228 gen_update_nip(ctx, ctx->nip - 4);
2229 gen_reset_fpstatus();
2230 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2231 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2232 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2233 }
2234
2235 /*** Floating-Point multiply-and-add ***/
2236 /* fmadd - fmadds */
2237 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2238 /* fmsub - fmsubs */
2239 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2240 /* fnmadd - fnmadds */
2241 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2242 /* fnmsub - fnmsubs */
2243 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2244
2245 /*** Floating-Point round & convert ***/
2246 /* fctiw */
2247 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2248 /* fctiwz */
2249 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2250 /* frsp */
2251 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2252 #if defined(TARGET_PPC64)
2253 /* fcfid */
2254 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2255 /* fctid */
2256 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2257 /* fctidz */
2258 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2259 #endif
2260
2261 /* frin */
2262 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2263 /* friz */
2264 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2265 /* frip */
2266 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2267 /* frim */
2268 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2269
2270 /*** Floating-Point compare ***/
2271 /* fcmpo */
2272 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
2273 {
2274 TCGv_i32 crf;
2275 if (unlikely(!ctx->fpu_enabled)) {
2276 gen_exception(ctx, POWERPC_EXCP_FPU);
2277 return;
2278 }
2279 /* NIP cannot be restored if the memory exception comes from an helper */
2280 gen_update_nip(ctx, ctx->nip - 4);
2281 gen_reset_fpstatus();
2282 crf = tcg_const_i32(crfD(ctx->opcode));
2283 gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2284 tcg_temp_free_i32(crf);
2285 gen_helper_float_check_status();
2286 }
2287
2288 /* fcmpu */
2289 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
2290 {
2291 TCGv_i32 crf;
2292 if (unlikely(!ctx->fpu_enabled)) {
2293 gen_exception(ctx, POWERPC_EXCP_FPU);
2294 return;
2295 }
2296 /* NIP cannot be restored if the memory exception comes from an helper */
2297 gen_update_nip(ctx, ctx->nip - 4);
2298 gen_reset_fpstatus();
2299 crf = tcg_const_i32(crfD(ctx->opcode));
2300 gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2301 tcg_temp_free_i32(crf);
2302 gen_helper_float_check_status();
2303 }
2304
2305 /*** Floating-point move ***/
2306 /* fabs */
2307 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2308 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2309
2310 /* fmr - fmr. */
2311 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2312 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2313 {
2314 if (unlikely(!ctx->fpu_enabled)) {
2315 gen_exception(ctx, POWERPC_EXCP_FPU);
2316 return;
2317 }
2318 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2319 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2320 }
2321
2322 /* fnabs */
2323 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2324 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2325 /* fneg */
2326 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2327 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2328
2329 /*** Floating-Point status & ctrl register ***/
2330 /* mcrfs */
2331 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2332 {
2333 int bfa;
2334
2335 if (unlikely(!ctx->fpu_enabled)) {
2336 gen_exception(ctx, POWERPC_EXCP_FPU);
2337 return;
2338 }
2339 bfa = 4 * (7 - crfS(ctx->opcode));
2340 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2341 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2342 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2343 }
2344
2345 /* mffs */
2346 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2347 {
2348 if (unlikely(!ctx->fpu_enabled)) {
2349 gen_exception(ctx, POWERPC_EXCP_FPU);
2350 return;
2351 }
2352 gen_reset_fpstatus();
2353 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2354 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2355 }
2356
2357 /* mtfsb0 */
2358 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2359 {
2360 uint8_t crb;
2361
2362 if (unlikely(!ctx->fpu_enabled)) {
2363 gen_exception(ctx, POWERPC_EXCP_FPU);
2364 return;
2365 }
2366 crb = 31 - crbD(ctx->opcode);
2367 gen_reset_fpstatus();
2368 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2369 TCGv_i32 t0;
2370 /* NIP cannot be restored if the memory exception comes from an helper */
2371 gen_update_nip(ctx, ctx->nip - 4);
2372 t0 = tcg_const_i32(crb);
2373 gen_helper_fpscr_clrbit(t0);
2374 tcg_temp_free_i32(t0);
2375 }
2376 if (unlikely(Rc(ctx->opcode) != 0)) {
2377 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2378 }
2379 }
2380
2381 /* mtfsb1 */
2382 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2383 {
2384 uint8_t crb;
2385
2386 if (unlikely(!ctx->fpu_enabled)) {
2387 gen_exception(ctx, POWERPC_EXCP_FPU);
2388 return;
2389 }
2390 crb = 31 - crbD(ctx->opcode);
2391 gen_reset_fpstatus();
2392 /* XXX: we pretend we can only do IEEE floating-point computations */
2393 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2394 TCGv_i32 t0;
2395 /* NIP cannot be restored if the memory exception comes from an helper */
2396 gen_update_nip(ctx, ctx->nip - 4);
2397 t0 = tcg_const_i32(crb);
2398 gen_helper_fpscr_setbit(t0);
2399 tcg_temp_free_i32(t0);
2400 }
2401 if (unlikely(Rc(ctx->opcode) != 0)) {
2402 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2403 }
2404 /* We can raise a differed exception */
2405 gen_helper_float_check_status();
2406 }
2407
2408 /* mtfsf */
2409 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2410 {
2411 TCGv_i32 t0;
2412
2413 if (unlikely(!ctx->fpu_enabled)) {
2414 gen_exception(ctx, POWERPC_EXCP_FPU);
2415 return;
2416 }
2417 /* NIP cannot be restored if the memory exception comes from an helper */
2418 gen_update_nip(ctx, ctx->nip - 4);
2419 gen_reset_fpstatus();
2420 t0 = tcg_const_i32(FM(ctx->opcode));
2421 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
2422 tcg_temp_free_i32(t0);
2423 if (unlikely(Rc(ctx->opcode) != 0)) {
2424 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2425 }
2426 /* We can raise a differed exception */
2427 gen_helper_float_check_status();
2428 }
2429
2430 /* mtfsfi */
2431 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2432 {
2433 int bf, sh;
2434 TCGv_i64 t0;
2435 TCGv_i32 t1;
2436
2437 if (unlikely(!ctx->fpu_enabled)) {
2438 gen_exception(ctx, POWERPC_EXCP_FPU);
2439 return;
2440 }
2441 bf = crbD(ctx->opcode) >> 2;
2442 sh = 7 - bf;
2443 /* NIP cannot be restored if the memory exception comes from an helper */
2444 gen_update_nip(ctx, ctx->nip - 4);
2445 gen_reset_fpstatus();
2446 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2447 t1 = tcg_const_i32(1 << sh);
2448 gen_helper_store_fpscr(t0, t1);
2449 tcg_temp_free_i64(t0);
2450 tcg_temp_free_i32(t1);
2451 if (unlikely(Rc(ctx->opcode) != 0)) {
2452 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2453 }
2454 /* We can raise a differed exception */
2455 gen_helper_float_check_status();
2456 }
2457
2458 /*** Addressing modes ***/
2459 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2460 static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target_long maskl)
2461 {
2462 target_long simm = SIMM(ctx->opcode);
2463
2464 simm &= ~maskl;
2465 if (rA(ctx->opcode) == 0) {
2466 #if defined(TARGET_PPC64)
2467 if (!ctx->sf_mode) {
2468 tcg_gen_movi_tl(EA, (uint32_t)simm);
2469 } else
2470 #endif
2471 tcg_gen_movi_tl(EA, simm);
2472 } else if (likely(simm != 0)) {
2473 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2474 #if defined(TARGET_PPC64)
2475 if (!ctx->sf_mode) {
2476 tcg_gen_ext32u_tl(EA, EA);
2477 }
2478 #endif
2479 } else {
2480 #if defined(TARGET_PPC64)
2481 if (!ctx->sf_mode) {
2482 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2483 } else
2484 #endif
2485 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2486 }
2487 }
2488
2489 static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA)
2490 {
2491 if (rA(ctx->opcode) == 0) {
2492 #if defined(TARGET_PPC64)
2493 if (!ctx->sf_mode) {
2494 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2495 } else
2496 #endif
2497 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2498 } else {
2499 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2500 #if defined(TARGET_PPC64)
2501 if (!ctx->sf_mode) {
2502 tcg_gen_ext32u_tl(EA, EA);
2503 }
2504 #endif
2505 }
2506 }
2507
2508 static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA)
2509 {
2510 if (rA(ctx->opcode) == 0) {
2511 tcg_gen_movi_tl(EA, 0);
2512 } else {
2513 #if defined(TARGET_PPC64)
2514 if (!ctx->sf_mode) {
2515 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2516 } else
2517 #endif
2518 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2519 }
2520 }
2521
2522 static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, target_long val)
2523 {
2524 tcg_gen_addi_tl(ret, arg1, val);
2525 #if defined(TARGET_PPC64)
2526 if (!ctx->sf_mode) {
2527 tcg_gen_ext32u_tl(ret, ret);
2528 }
2529 #endif
2530 }
2531
2532 static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
2533 {
2534 int l1 = gen_new_label();
2535 TCGv t0 = tcg_temp_new();
2536 TCGv_i32 t1, t2;
2537 /* NIP cannot be restored if the memory exception comes from an helper */
2538 gen_update_nip(ctx, ctx->nip - 4);
2539 tcg_gen_andi_tl(t0, EA, mask);
2540 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2541 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2542 t2 = tcg_const_i32(0);
2543 gen_helper_raise_exception_err(t1, t2);
2544 tcg_temp_free_i32(t1);
2545 tcg_temp_free_i32(t2);
2546 gen_set_label(l1);
2547 tcg_temp_free(t0);
2548 }
2549
2550 /*** Integer load ***/
2551 static always_inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2552 {
2553 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2554 }
2555
2556 static always_inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2557 {
2558 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2559 }
2560
2561 static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2562 {
2563 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2564 if (unlikely(ctx->le_mode)) {
2565 #if defined(TARGET_PPC64)
2566 TCGv_i32 t0 = tcg_temp_new_i32();
2567 tcg_gen_trunc_tl_i32(t0, arg1);
2568 tcg_gen_bswap16_i32(t0, t0);
2569 tcg_gen_extu_i32_tl(arg1, t0);
2570 tcg_temp_free_i32(t0);
2571 #else
2572 tcg_gen_bswap16_i32(arg1, arg1);
2573 #endif
2574 }
2575 }
2576
2577 static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2578 {
2579 if (unlikely(ctx->le_mode)) {
2580 #if defined(TARGET_PPC64)
2581 TCGv_i32 t0;
2582 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2583 t0 = tcg_temp_new_i32();
2584 tcg_gen_trunc_tl_i32(t0, arg1);
2585 tcg_gen_bswap16_i32(t0, t0);
2586 tcg_gen_extu_i32_tl(arg1, t0);
2587 tcg_gen_ext16s_tl(arg1, arg1);
2588 tcg_temp_free_i32(t0);
2589 #else
2590 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2591 tcg_gen_bswap16_i32(arg1, arg1);
2592 tcg_gen_ext16s_i32(arg1, arg1);
2593 #endif
2594 } else {
2595 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2596 }
2597 }
2598
2599 static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2600 {
2601 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2602 if (unlikely(ctx->le_mode)) {
2603 #if defined(TARGET_PPC64)
2604 TCGv_i32 t0 = tcg_temp_new_i32();
2605 tcg_gen_trunc_tl_i32(t0, arg1);
2606 tcg_gen_bswap_i32(t0, t0);
2607 tcg_gen_extu_i32_tl(arg1, t0);
2608 tcg_temp_free_i32(t0);
2609 #else
2610 tcg_gen_bswap_i32(arg1, arg1);
2611 #endif
2612 }
2613 }
2614
2615 #if defined(TARGET_PPC64)
2616 static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2617 {
2618 if (unlikely(ctx->mem_idx)) {
2619 TCGv_i32 t0;
2620 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2621 t0 = tcg_temp_new_i32();
2622 tcg_gen_trunc_tl_i32(t0, arg1);
2623 tcg_gen_bswap_i32(t0, t0);
2624 tcg_gen_ext_i32_tl(arg1, t0);
2625 tcg_temp_free_i32(t0);
2626 } else
2627 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2628 }
2629 #endif
2630
2631 static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2632 {
2633 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2634 if (unlikely(ctx->le_mode)) {
2635 tcg_gen_bswap_i64(arg1, arg1);
2636 }
2637 }
2638
2639 static always_inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2640 {
2641 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2642 }
2643
2644 static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2645 {
2646 if (unlikely(ctx->le_mode)) {
2647 #if defined(TARGET_PPC64)
2648 TCGv_i32 t0;
2649 TCGv t1;
2650 t0 = tcg_temp_new_i32();
2651 tcg_gen_trunc_tl_i32(t0, arg1);
2652 tcg_gen_ext16u_i32(t0, t0);
2653 tcg_gen_bswap16_i32(t0, t0);
2654 t1 = tcg_temp_new();
2655 tcg_gen_extu_i32_tl(t1, t0);
2656 tcg_temp_free_i32(t0);
2657 tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
2658 tcg_temp_free(t1);
2659 #else
2660 TCGv t0 = tcg_temp_new();
2661 tcg_gen_ext16u_tl(t0, arg1);
2662 tcg_gen_bswap16_i32(t0, t0);
2663 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2664 tcg_temp_free(t0);
2665 #endif
2666 } else {
2667 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2668 }
2669 }
2670
2671 static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2672 {
2673 if (unlikely(ctx->le_mode)) {
2674 #if defined(TARGET_PPC64)
2675 TCGv_i32 t0;
2676 TCGv t1;
2677 t0 = tcg_temp_new_i32();
2678 tcg_gen_trunc_tl_i32(t0, arg1);
2679 tcg_gen_bswap_i32(t0, t0);
2680 t1 = tcg_temp_new();
2681 tcg_gen_extu_i32_tl(t1, t0);
2682 tcg_temp_free_i32(t0);
2683 tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
2684 tcg_temp_free(t1);
2685 #else
2686 TCGv t0 = tcg_temp_new_i32();
2687 tcg_gen_bswap_i32(t0, arg1);
2688 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2689 tcg_temp_free(t0);
2690 #endif
2691 } else {
2692 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2693 }
2694 }
2695
2696 static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2697 {
2698 if (unlikely(ctx->le_mode)) {
2699 TCGv_i64 t0 = tcg_temp_new_i64();
2700 tcg_gen_bswap_i64(t0, arg1);
2701 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2702 tcg_temp_free_i64(t0);
2703 } else
2704 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2705 }
2706
2707 #define GEN_LD(name, ldop, opc, type) \
2708 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2709 { \
2710 TCGv EA; \
2711 gen_set_access_type(ctx, ACCESS_INT); \
2712 EA = tcg_temp_new(); \
2713 gen_addr_imm_index(ctx, EA, 0); \
2714 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2715 tcg_temp_free(EA); \
2716 }
2717
2718 #define GEN_LDU(name, ldop, opc, type) \
2719 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2720 { \
2721 TCGv EA; \
2722 if (unlikely(rA(ctx->opcode) == 0 || \
2723 rA(ctx->opcode) == rD(ctx->opcode))) { \
2724 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2725 return; \
2726 } \
2727 gen_set_access_type(ctx, ACCESS_INT); \
2728 EA = tcg_temp_new(); \
2729 if (type == PPC_64B) \
2730 gen_addr_imm_index(ctx, EA, 0x03); \
2731 else \
2732 gen_addr_imm_index(ctx, EA, 0); \
2733 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2734 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2735 tcg_temp_free(EA); \
2736 }
2737
2738 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2739 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2740 { \
2741 TCGv EA; \
2742 if (unlikely(rA(ctx->opcode) == 0 || \
2743 rA(ctx->opcode) == rD(ctx->opcode))) { \
2744 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2745 return; \
2746 } \
2747 gen_set_access_type(ctx, ACCESS_INT); \
2748 EA = tcg_temp_new(); \
2749 gen_addr_reg_index(ctx, EA); \
2750 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2751 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2752 tcg_temp_free(EA); \
2753 }
2754
2755 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2756 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2757 { \
2758 TCGv EA; \
2759 gen_set_access_type(ctx, ACCESS_INT); \
2760 EA = tcg_temp_new(); \
2761 gen_addr_reg_index(ctx, EA); \
2762 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2763 tcg_temp_free(EA); \
2764 }
2765
2766 #define GEN_LDS(name, ldop, op, type) \
2767 GEN_LD(name, ldop, op | 0x20, type); \
2768 GEN_LDU(name, ldop, op | 0x21, type); \
2769 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2770 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2771
2772 /* lbz lbzu lbzux lbzx */
2773 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2774 /* lha lhau lhaux lhax */
2775 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2776 /* lhz lhzu lhzux lhzx */
2777 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2778 /* lwz lwzu lwzux lwzx */
2779 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2780 #if defined(TARGET_PPC64)
2781 /* lwaux */
2782 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2783 /* lwax */
2784 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2785 /* ldux */
2786 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2787 /* ldx */
2788 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2789 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2790 {
2791 TCGv EA;
2792 if (Rc(ctx->opcode)) {
2793 if (unlikely(rA(ctx->opcode) == 0 ||
2794 rA(ctx->opcode) == rD(ctx->opcode))) {
2795 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2796 return;
2797 }
2798 }
2799 gen_set_access_type(ctx, ACCESS_INT);
2800 EA = tcg_temp_new();
2801 gen_addr_imm_index(ctx, EA, 0x03);
2802 if (ctx->opcode & 0x02) {
2803 /* lwa (lwau is undefined) */
2804 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2805 } else {
2806 /* ld - ldu */
2807 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2808 }
2809 if (Rc(ctx->opcode))
2810 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2811 tcg_temp_free(EA);
2812 }
2813 /* lq */
2814 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2815 {
2816 #if defined(CONFIG_USER_ONLY)
2817 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2818 #else
2819 int ra, rd;
2820 TCGv EA;
2821
2822 /* Restore CPU state */
2823 if (unlikely(ctx->mem_idx == 0)) {
2824 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2825 return;
2826 }
2827 ra = rA(ctx->opcode);
2828 rd = rD(ctx->opcode);
2829 if (unlikely((rd & 1) || rd == ra)) {
2830 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2831 return;
2832 }
2833 if (unlikely(ctx->le_mode)) {
2834 /* Little-endian mode is not handled */
2835 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2836 return;
2837 }
2838 gen_set_access_type(ctx, ACCESS_INT);
2839 EA = tcg_temp_new();
2840 gen_addr_imm_index(ctx, EA, 0x0F);
2841 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2842 gen_addr_add(ctx, EA, EA, 8);
2843 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2844 tcg_temp_free(EA);
2845 #endif
2846 }
2847 #endif
2848
2849 /*** Integer store ***/
2850 #define GEN_ST(name, stop, opc, type) \
2851 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2852 { \
2853 TCGv EA; \
2854 gen_set_access_type(ctx, ACCESS_INT); \
2855 EA = tcg_temp_new(); \
2856 gen_addr_imm_index(ctx, EA, 0); \
2857 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2858 tcg_temp_free(EA); \
2859 }
2860
2861 #define GEN_STU(name, stop, opc, type) \
2862 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2863 { \
2864 TCGv EA; \
2865 if (unlikely(rA(ctx->opcode) == 0)) { \
2866 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2867 return; \
2868 } \
2869 gen_set_access_type(ctx, ACCESS_INT); \
2870 EA = tcg_temp_new(); \
2871 if (type == PPC_64B) \
2872 gen_addr_imm_index(ctx, EA, 0x03); \
2873 else \
2874 gen_addr_imm_index(ctx, EA, 0); \
2875 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2876 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2877 tcg_temp_free(EA); \
2878 }
2879
2880 #define GEN_STUX(name, stop, opc2, opc3, type) \
2881 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2882 { \
2883 TCGv EA; \
2884 if (unlikely(rA(ctx->opcode) == 0)) { \
2885 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2886 return; \
2887 } \
2888 gen_set_access_type(ctx, ACCESS_INT); \
2889 EA = tcg_temp_new(); \
2890 gen_addr_reg_index(ctx, EA); \
2891 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2892 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2893 tcg_temp_free(EA); \
2894 }
2895
2896 #define GEN_STX(name, stop, opc2, opc3, type) \
2897 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2898 { \
2899 TCGv EA; \
2900 gen_set_access_type(ctx, ACCESS_INT); \
2901 EA = tcg_temp_new(); \
2902 gen_addr_reg_index(ctx, EA); \
2903 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2904 tcg_temp_free(EA); \
2905 }
2906
2907 #define GEN_STS(name, stop, op, type) \
2908 GEN_ST(name, stop, op | 0x20, type); \
2909 GEN_STU(name, stop, op | 0x21, type); \
2910 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2911 GEN_STX(name, stop, 0x17, op | 0x00, type)
2912
2913 /* stb stbu stbux stbx */
2914 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2915 /* sth sthu sthux sthx */
2916 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2917 /* stw stwu stwux stwx */
2918 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2919 #if defined(TARGET_PPC64)
2920 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2921 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2922 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2923 {
2924 int rs;
2925 TCGv EA;
2926
2927 rs = rS(ctx->opcode);
2928 if ((ctx->opcode & 0x3) == 0x2) {
2929 #if defined(CONFIG_USER_ONLY)
2930 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2931 #else
2932 /* stq */
2933 if (unlikely(ctx->mem_idx == 0)) {
2934 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2935 return;
2936 }
2937 if (unlikely(rs & 1)) {
2938 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2939 return;
2940 }
2941 if (unlikely(ctx->le_mode)) {
2942 /* Little-endian mode is not handled */
2943 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2944 return;
2945 }
2946 gen_set_access_type(ctx, ACCESS_INT);
2947 EA = tcg_temp_new();
2948 gen_addr_imm_index(ctx, EA, 0x03);
2949 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2950 gen_addr_add(ctx, EA, EA, 8);
2951 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2952 tcg_temp_free(EA);
2953 #endif
2954 } else {
2955 /* std / stdu */
2956 if (Rc(ctx->opcode)) {
2957 if (unlikely(rA(ctx->opcode) == 0)) {
2958 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2959 return;
2960 }
2961 }
2962 gen_set_access_type(ctx, ACCESS_INT);
2963 EA = tcg_temp_new();
2964 gen_addr_imm_index(ctx, EA, 0x03);
2965 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2966 if (Rc(ctx->opcode))
2967 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2968 tcg_temp_free(EA);
2969 }
2970 }
2971 #endif
2972 /*** Integer load and store with byte reverse ***/
2973 /* lhbrx */
2974 static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2975 {
2976 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2977 if (likely(!ctx->le_mode)) {
2978 #if defined(TARGET_PPC64)
2979 TCGv_i32 t0 = tcg_temp_new_i32();
2980 tcg_gen_trunc_tl_i32(t0, arg1);
2981 tcg_gen_bswap16_i32(t0, t0);
2982 tcg_gen_extu_i32_tl(arg1, t0);
2983 tcg_temp_free_i32(t0);
2984 #else
2985 tcg_gen_bswap16_i32(arg1, arg1);
2986 #endif
2987 }
2988 }
2989 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2990
2991 /* lwbrx */
2992 static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2993 {
2994 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2995 if (likely(!ctx->le_mode)) {
2996 #if defined(TARGET_PPC64)
2997 TCGv_i32 t0 = tcg_temp_new_i32();
2998 tcg_gen_trunc_tl_i32(t0, arg1);
2999 tcg_gen_bswap_i32(t0, t0);
3000 tcg_gen_extu_i32_tl(arg1, t0);
3001 tcg_temp_free_i32(t0);
3002 #else
3003 tcg_gen_bswap_i32(arg1, arg1);
3004 #endif
3005 }
3006 }
3007 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3008
3009 /* sthbrx */
3010 static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3011 {
3012 if (likely(!ctx->le_mode)) {
3013 #if defined(TARGET_PPC64)
3014 TCGv_i32 t0;
3015 TCGv t1;
3016 t0 = tcg_temp_new_i32();
3017 tcg_gen_trunc_tl_i32(t0, arg1);
3018 tcg_gen_ext16u_i32(t0, t0);
3019 tcg_gen_bswap16_i32(t0, t0);
3020 t1 = tcg_temp_new();
3021 tcg_gen_extu_i32_tl(t1, t0);
3022 tcg_temp_free_i32(t0);
3023 tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
3024 tcg_temp_free(t1);
3025 #else
3026 TCGv t0 = tcg_temp_new();
3027 tcg_gen_ext16u_tl(t0, arg1);
3028 tcg_gen_bswap16_i32(t0, t0);
3029 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
3030 tcg_temp_free(t0);
3031 #endif
3032 } else {
3033 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
3034 }
3035 }
3036 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3037
3038 /* stwbrx */
3039 static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3040 {
3041 if (likely(!ctx->le_mode)) {
3042 #if defined(TARGET_PPC64)
3043 TCGv_i32 t0;
3044 TCGv t1;
3045 t0 = tcg_temp_new_i32();
3046 tcg_gen_trunc_tl_i32(t0, arg1);
3047 tcg_gen_bswap_i32(t0, t0);
3048 t1 = tcg_temp_new();
3049 tcg_gen_extu_i32_tl(t1, t0);
3050 tcg_temp_free_i32(t0);
3051 tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
3052 tcg_temp_free(t1);
3053 #else
3054 TCGv t0 = tcg_temp_new_i32();
3055 tcg_gen_bswap_i32(t0, arg1);
3056 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
3057 tcg_temp_free(t0);
3058 #endif
3059 } else {
3060 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
3061 }
3062 }
3063 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3064
3065 /*** Integer load and store multiple ***/
3066 /* lmw */
3067 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3068 {
3069 TCGv t0;
3070 TCGv_i32 t1;
3071 gen_set_access_type(ctx, ACCESS_INT);
3072 /* NIP cannot be restored if the memory exception comes from an helper */
3073 gen_update_nip(ctx, ctx->nip - 4);
3074 t0 = tcg_temp_new();
3075 t1 = tcg_const_i32(rD(ctx->opcode));
3076 gen_addr_imm_index(ctx, t0, 0);
3077 gen_helper_lmw(t0, t1);
3078 tcg_temp_free(t0);
3079 tcg_temp_free_i32(t1);
3080 }
3081
3082 /* stmw */
3083 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3084 {
3085 TCGv t0;
3086 TCGv_i32 t1;
3087 gen_set_access_type(ctx, ACCESS_INT);
3088 /* NIP cannot be restored if the memory exception comes from an helper */
3089 gen_update_nip(ctx, ctx->nip - 4);
3090 t0 = tcg_temp_new();
3091 t1 = tcg_const_i32(rS(ctx->opcode));
3092 gen_addr_imm_index(ctx, t0, 0);
3093 gen_helper_stmw(t0, t1);
3094 tcg_temp_free(t0);
3095 tcg_temp_free_i32(t1);
3096 }
3097
3098 /*** Integer load and store strings ***/
3099 /* lswi */
3100 /* PowerPC32 specification says we must generate an exception if
3101 * rA is in the range of registers to be loaded.
3102 * In an other hand, IBM says this is valid, but rA won't be loaded.
3103 * For now, I'll follow the spec...
3104 */
3105 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
3106 {
3107 TCGv t0;
3108 TCGv_i32 t1, t2;
3109 int nb = NB(ctx->opcode);
3110 int start = rD(ctx->opcode);
3111 int ra = rA(ctx->opcode);
3112 int nr;
3113
3114 if (nb == 0)
3115 nb = 32;
3116 nr = nb / 4;
3117 if (unlikely(((start + nr) > 32 &&
3118 start <= ra && (start + nr - 32) > ra) ||
3119 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3120 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3121 return;
3122 }
3123 gen_set_access_type(ctx, ACCESS_INT);
3124 /* NIP cannot be restored if the memory exception comes from an helper */
3125 gen_update_nip(ctx, ctx->nip - 4);
3126 t0 = tcg_temp_new();
3127 gen_addr_register(ctx, t0);
3128 t1 = tcg_const_i32(nb);
3129 t2 = tcg_const_i32(start);
3130 gen_helper_lsw(t0, t1, t2);
3131 tcg_temp_free(t0);
3132 tcg_temp_free_i32(t1);
3133 tcg_temp_free_i32(t2);
3134 }
3135
3136 /* lswx */
3137 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
3138 {
3139 TCGv t0;
3140 TCGv_i32 t1, t2, t3;
3141 gen_set_access_type(ctx, ACCESS_INT);
3142 /* NIP cannot be restored if the memory exception comes from an helper */
3143 gen_update_nip(ctx, ctx->nip - 4);
3144 t0 = tcg_temp_new();
3145 gen_addr_reg_index(ctx, t0);
3146 t1 = tcg_const_i32(rD(ctx->opcode));
3147 t2 = tcg_const_i32(rA(ctx->opcode));
3148 t3 = tcg_const_i32(rB(ctx->opcode));
3149 gen_helper_lswx(t0, t1, t2, t3);
3150 tcg_temp_free(t0);
3151 tcg_temp_free_i32(t1);
3152 tcg_temp_free_i32(t2);
3153 tcg_temp_free_i32(t3);
3154 }
3155
3156 /* stswi */
3157 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
3158 {
3159 TCGv t0;
3160 TCGv_i32 t1, t2;
3161 int nb = NB(ctx->opcode);
3162 gen_set_access_type(ctx, ACCESS_INT);
3163 /* NIP cannot be restored if the memory exception comes from an helper */
3164 gen_update_nip(ctx, ctx->nip - 4);
3165 t0 = tcg_temp_new();
3166 gen_addr_register(ctx, t0);
3167 if (nb == 0)
3168 nb = 32;
3169 t1 = tcg_const_i32(nb);
3170 t2 = tcg_const_i32(rS(ctx->opcode));
3171 gen_helper_stsw(t0, t1, t2);
3172 tcg_temp_free(t0);
3173 tcg_temp_free_i32(t1);
3174 tcg_temp_free_i32(t2);
3175 }
3176
3177 /* stswx */
3178 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
3179 {
3180 TCGv t0;
3181 TCGv_i32 t1, t2;
3182 gen_set_access_type(ctx, ACCESS_INT);
3183 /* NIP cannot be restored if the memory exception comes from an helper */
3184 gen_update_nip(ctx, ctx->nip - 4);
3185 t0 = tcg_temp_new();
3186 gen_addr_reg_index(ctx, t0);
3187 t1 = tcg_temp_new_i32();
3188 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3189 tcg_gen_andi_i32(t1, t1, 0x7F);
3190 t2 = tcg_const_i32(rS(ctx->opcode));
3191 gen_helper_stsw(t0, t1, t2);
3192 tcg_temp_free(t0);
3193 tcg_temp_free_i32(t1);
3194 tcg_temp_free_i32(t2);
3195 }
3196
3197 /*** Memory synchronisation ***/
3198 /* eieio */
3199 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
3200 {
3201 }
3202
3203 /* isync */
3204 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
3205 {
3206 gen_stop_exception(ctx);
3207 }
3208
3209 /* lwarx */
3210 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
3211 {
3212 TCGv t0;
3213 gen_set_access_type(ctx, ACCESS_RES);
3214 t0 = tcg_temp_local_new();
3215 gen_addr_reg_index(ctx, t0);
3216 gen_check_align(ctx, t0, 0x03);
3217 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
3218 tcg_gen_mov_tl(cpu_reserve, t0);
3219 tcg_temp_free(t0);
3220 }
3221
3222 /* stwcx. */
3223 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
3224 {
3225 int l1;
3226 TCGv t0;
3227 gen_set_access_type(ctx, ACCESS_RES);
3228 t0 = tcg_temp_local_new();
3229 gen_addr_reg_index(ctx, t0);
3230 gen_check_align(ctx, t0, 0x03);
3231 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3232 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3233 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3234 l1 = gen_new_label();
3235 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3236 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3237 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3238 gen_set_label(l1);
3239 tcg_gen_movi_tl(cpu_reserve, -1);
3240 tcg_temp_free(t0);
3241 }
3242
3243 #if defined(TARGET_PPC64)
3244 /* ldarx */
3245 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
3246 {
3247 TCGv t0;
3248 gen_set_access_type(ctx, ACCESS_RES);
3249 t0 = tcg_temp_local_new();
3250 gen_addr_reg_index(ctx, t0);
3251 gen_check_align(ctx, t0, 0x07);
3252 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], t0);
3253 tcg_gen_mov_tl(cpu_reserve, t0);
3254 tcg_temp_free(t0);
3255 }
3256
3257 /* stdcx. */
3258 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
3259 {
3260 int l1;
3261 TCGv t0;
3262 gen_set_access_type(ctx, ACCESS_RES);
3263 t0 = tcg_temp_local_new();
3264 gen_addr_reg_index(ctx, t0);
3265 gen_check_align(ctx, t0, 0x07);
3266 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3267 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3268 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3269 l1 = gen_new_label();
3270 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3271 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3272 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3273 gen_set_label(l1);
3274 tcg_gen_movi_tl(cpu_reserve, -1);
3275 tcg_temp_free(t0);
3276 }
3277 #endif /* defined(TARGET_PPC64) */
3278
3279 /* sync */
3280 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
3281 {
3282 }
3283
3284 /* wait */
3285 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3286 {
3287 TCGv_i32 t0 = tcg_temp_new_i32();
3288 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3289 tcg_temp_free_i32(t0);
3290 /* Stop translation, as the CPU is supposed to sleep from now */
3291 gen_exception_err(ctx, EXCP_HLT, 1);
3292 }
3293
3294 /*** Floating-point load ***/
3295 #define GEN_LDF(name, ldop, opc, type) \
3296 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
3297 { \
3298 TCGv EA; \
3299 if (unlikely(!ctx->fpu_enabled)) { \
3300 gen_exception(ctx, POWERPC_EXCP_FPU); \
3301 return; \
3302 } \
3303 gen_set_access_type(ctx, ACCESS_FLOAT); \
3304 EA = tcg_temp_new(); \
3305 gen_addr_imm_index(ctx, EA, 0); \
3306 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3307 tcg_temp_free(EA); \
3308 }
3309
3310 #define GEN_LDUF(name, ldop, opc, type) \
3311 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3312 { \
3313 TCGv EA; \
3314 if (unlikely(!ctx->fpu_enabled)) { \
3315 gen_exception(ctx, POWERPC_EXCP_FPU); \
3316 return; \
3317 } \
3318 if (unlikely(rA(ctx->opcode) == 0)) { \
3319 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3320 return; \
3321 } \
3322 gen_set_access_type(ctx, ACCESS_FLOAT); \
3323 EA = tcg_temp_new(); \
3324 gen_addr_imm_index(ctx, EA, 0); \
3325 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3326 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3327 tcg_temp_free(EA); \
3328 }
3329
3330 #define GEN_LDUXF(name, ldop, opc, type) \
3331 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3332 { \
3333 TCGv EA; \
3334 if (unlikely(!ctx->fpu_enabled)) { \
3335 gen_exception(ctx, POWERPC_EXCP_FPU); \
3336 return; \
3337 } \
3338 if (unlikely(rA(ctx->opcode) == 0)) { \
3339 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3340 return; \
3341 } \
3342 gen_set_access_type(ctx, ACCESS_FLOAT); \
3343 EA = tcg_temp_new(); \
3344 gen_addr_reg_index(ctx, EA); \
3345 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3346 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3347 tcg_temp_free(EA); \
3348 }
3349
3350 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3351 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
3352 { \
3353 TCGv EA; \
3354 if (unlikely(!ctx->fpu_enabled)) { \
3355 gen_exception(ctx, POWERPC_EXCP_FPU); \
3356 return; \
3357 } \
3358 gen_set_access_type(ctx, ACCESS_FLOAT); \
3359 EA = tcg_temp_new(); \
3360 gen_addr_reg_index(ctx, EA); \
3361 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3362 tcg_temp_free(EA); \
3363 }
3364
3365 #define GEN_LDFS(name, ldop, op, type) \
3366 GEN_LDF(name, ldop, op | 0x20, type); \
3367 GEN_LDUF(name, ldop, op | 0x21, type); \
3368 GEN_LDUXF(name, ldop, op | 0x01, type); \
3369 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3370
3371 static always_inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3372 {
3373 TCGv t0 = tcg_temp_new();
3374 TCGv_i32 t1 = tcg_temp_new_i32();
3375 gen_qemu_ld32u(ctx, t0, arg2);
3376 tcg_gen_trunc_tl_i32(t1, t0);
3377 tcg_temp_free(t0);
3378 gen_helper_float32_to_float64(arg1, t1);
3379 tcg_temp_free_i32(t1);
3380 }
3381
3382 /* lfd lfdu lfdux lfdx */
3383 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3384 /* lfs lfsu lfsux lfsx */
3385 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3386
3387 /*** Floating-point store ***/
3388 #define GEN_STF(name, stop, opc, type) \
3389 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
3390 { \
3391 TCGv EA; \
3392 if (unlikely(!ctx->fpu_enabled)) { \
3393 gen_exception(ctx, POWERPC_EXCP_FPU); \
3394 return; \
3395 } \
3396 gen_set_access_type(ctx, ACCESS_FLOAT); \
3397 EA = tcg_temp_new(); \
3398 gen_addr_imm_index(ctx, EA, 0); \
3399 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3400 tcg_temp_free(EA); \
3401 }
3402
3403 #define GEN_STUF(name, stop, opc, type) \
3404 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3405 { \
3406 TCGv EA; \
3407 if (unlikely(!ctx->fpu_enabled)) { \
3408 gen_exception(ctx, POWERPC_EXCP_FPU); \
3409 return; \
3410 } \
3411 if (unlikely(rA(ctx->opcode) == 0)) { \
3412 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3413 return; \
3414 } \
3415 gen_set_access_type(ctx, ACCESS_FLOAT); \
3416 EA = tcg_temp_new(); \
3417 gen_addr_imm_index(ctx, EA, 0); \
3418 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3419 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3420 tcg_temp_free(EA); \
3421 }
3422
3423 #define GEN_STUXF(name, stop, opc, type) \
3424 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3425 { \
3426 TCGv EA; \
3427 if (unlikely(!ctx->fpu_enabled)) { \
3428 gen_exception(ctx, POWERPC_EXCP_FPU); \
3429 return; \
3430 } \
3431 if (unlikely(rA(ctx->opcode) == 0)) { \
3432 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3433 return; \
3434 } \
3435 gen_set_access_type(ctx, ACCESS_FLOAT); \
3436 EA = tcg_temp_new(); \
3437 gen_addr_reg_index(ctx, EA); \
3438 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3439 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3440 tcg_temp_free(EA); \
3441 }
3442
3443 #define GEN_STXF(name, stop, opc2, opc3, type) \
3444 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
3445 { \
3446 TCGv EA; \
3447 if (unlikely(!ctx->fpu_enabled)) { \
3448 gen_exception(ctx, POWERPC_EXCP_FPU); \
3449 return; \
3450 } \
3451 gen_set_access_type(ctx, ACCESS_FLOAT); \
3452 EA = tcg_temp_new(); \
3453 gen_addr_reg_index(ctx, EA); \
3454 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3455 tcg_temp_free(EA); \
3456 }
3457
3458 #define GEN_STFS(name, stop, op, type) \
3459 GEN_STF(name, stop, op | 0x20, type); \
3460 GEN_STUF(name, stop, op | 0x21, type); \
3461 GEN_STUXF(name, stop, op | 0x01, type); \
3462 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3463
3464 static always_inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3465 {
3466 TCGv_i32 t0 = tcg_temp_new_i32();
3467 TCGv t1 = tcg_temp_new();
3468 gen_helper_float64_to_float32(t0, arg1);
3469 tcg_gen_extu_i32_tl(t1, t0);
3470 tcg_temp_free_i32(t0);
3471 gen_qemu_st32(ctx, t1, arg2);
3472 tcg_temp_free(t1);
3473 }
3474
3475 /* stfd stfdu stfdux stfdx */
3476 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3477 /* stfs stfsu stfsux stfsx */
3478 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3479
3480 /* Optional: */
3481 static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3482 {
3483 TCGv t0 = tcg_temp_new();
3484 tcg_gen_trunc_i64_tl(t0, arg1),
3485 gen_qemu_st32(ctx, t0, arg2);
3486 tcg_temp_free(t0);
3487 }
3488 /* stfiwx */
3489 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3490
3491 /*** Branch ***/
3492 static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3493 target_ulong dest)
3494 {
3495 TranslationBlock *tb;
3496 tb = ctx->tb;
3497 #if defined(TARGET_PPC64)
3498 if (!ctx->sf_mode)
3499 dest = (uint32_t) dest;
3500 #endif
3501 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3502 likely(!ctx->singlestep_enabled)) {
3503 tcg_gen_goto_tb(n);
3504 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3505 tcg_gen_exit_tb((long)tb + n);
3506 } else {
3507 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3508 if (unlikely(ctx->singlestep_enabled)) {
3509 if ((ctx->singlestep_enabled &
3510 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3511 ctx->exception == POWERPC_EXCP_BRANCH) {
3512 target_ulong tmp = ctx->nip;
3513 ctx->nip = dest;
3514 gen_exception(ctx, POWERPC_EXCP_TRACE);
3515 ctx->nip = tmp;
3516 }
3517 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3518 gen_debug_exception(ctx);
3519 }
3520 }
3521 tcg_gen_exit_tb(0);
3522 }
3523 }
3524
3525 static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
3526 {
3527 #if defined(TARGET_PPC64)
3528 if (ctx->sf_mode == 0)
3529 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3530 else
3531 #endif
3532 tcg_gen_movi_tl(cpu_lr, nip);
3533 }
3534
3535 /* b ba bl bla */
3536 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3537 {
3538 target_ulong li, target;
3539
3540 ctx->exception = POWERPC_EXCP_BRANCH;
3541 /* sign extend LI */
3542 #if defined(TARGET_PPC64)
3543 if (ctx->sf_mode)
3544 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3545 else
3546 #endif
3547 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3548 if (likely(AA(ctx->opcode) == 0))
3549 target = ctx->nip + li - 4;
3550 else
3551 target = li;
3552 if (LK(ctx->opcode))
3553 gen_setlr(ctx, ctx->nip);
3554 gen_goto_tb(ctx, 0, target);
3555 }
3556
3557 #define BCOND_IM 0
3558 #define BCOND_LR 1
3559 #define BCOND_CTR 2
3560
3561 static always_inline void gen_bcond (DisasContext *ctx, int type)
3562 {
3563 uint32_t bo = BO(ctx->opcode);
3564 int l1 = gen_new_label();
3565 TCGv target;
3566
3567 ctx->exception = POWERPC_EXCP_BRANCH;
3568 if (type == BCOND_LR || type == BCOND_CTR) {
3569 target = tcg_temp_local_new();
3570 if (type == BCOND_CTR)
3571 tcg_gen_mov_tl(target, cpu_ctr);
3572 else
3573 tcg_gen_mov_tl(target, cpu_lr);
3574 }
3575 if (LK(ctx->opcode))
3576 gen_setlr(ctx, ctx->nip);
3577 l1 = gen_new_label();
3578 if ((bo & 0x4) == 0) {
3579 /* Decrement and test CTR */
3580 TCGv temp = tcg_temp_new();
3581 if (unlikely(type == BCOND_CTR)) {
3582 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3583 return;
3584 }
3585 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3586 #if defined(TARGET_PPC64)
3587 if (!ctx->sf_mode)
3588 tcg_gen_ext32u_tl(temp, cpu_ctr);
3589 else
3590 #endif
3591 tcg_gen_mov_tl(temp, cpu_ctr);
3592 if (bo & 0x2) {
3593 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3594 } else {
3595 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3596 }
3597 tcg_temp_free(temp);
3598 }
3599 if ((bo & 0x10) == 0) {
3600 /* Test CR */
3601 uint32_t bi = BI(ctx->opcode);
3602 uint32_t mask = 1 << (3 - (bi & 0x03));
3603 TCGv_i32 temp = tcg_temp_new_i32();
3604
3605 if (bo & 0x8) {
3606 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3607 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3608 } else {
3609 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3610 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3611 }
3612 tcg_temp_free_i32(temp);
3613 }
3614 if (type == BCOND_IM) {
3615 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3616 if (likely(AA(ctx->opcode) == 0)) {
3617 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3618 } else {
3619 gen_goto_tb(ctx, 0, li);
3620 }
3621 gen_set_label(l1);
3622 gen_goto_tb(ctx, 1, ctx->nip);
3623 } else {
3624 #if defined(TARGET_PPC64)
3625 if (!(ctx->sf_mode))
3626 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3627 else
3628 #endif
3629 tcg_gen_andi_tl(cpu_nip, target, ~3);
3630 tcg_gen_exit_tb(0);
3631 gen_set_label(l1);
3632 #if defined(TARGET_PPC64)
3633 if (!(ctx->sf_mode))
3634 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3635 else
3636 #endif
3637 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3638 tcg_gen_exit_tb(0);
3639 }
3640 }
3641
3642 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3643 {
3644 gen_bcond(ctx, BCOND_IM);
3645 }
3646
3647 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3648 {
3649 gen_bcond(ctx, BCOND_CTR);
3650 }
3651
3652 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3653 {
3654 gen_bcond(ctx, BCOND_LR);
3655 }
3656
3657 /*** Condition register logical ***/
3658 #define GEN_CRLOGIC(name, tcg_op, opc) \
3659 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3660 { \
3661 uint8_t bitmask; \
3662 int sh; \
3663 TCGv_i32 t0, t1; \
3664 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3665 t0 = tcg_temp_new_i32(); \
3666 if (sh > 0) \
3667 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3668 else if (sh < 0) \
3669 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3670 else \
3671 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3672 t1 = tcg_temp_new_i32(); \
3673 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3674 if (sh > 0) \
3675 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3676 else if (sh < 0) \
3677 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3678 else \
3679 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3680 tcg_op(t0, t0, t1); \
3681 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3682 tcg_gen_andi_i32(t0, t0, bitmask); \
3683 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3684 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3685 tcg_temp_free_i32(t0); \
3686 tcg_temp_free_i32(t1); \
3687 }
3688
3689 /* crand */
3690 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3691 /* crandc */
3692 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3693 /* creqv */
3694 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3695 /* crnand */
3696 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3697 /* crnor */
3698 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3699 /* cror */
3700 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3701 /* crorc */
3702 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3703 /* crxor */
3704 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3705 /* mcrf */
3706 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3707 {
3708 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3709 }
3710
3711 /*** System linkage ***/
3712 /* rfi (mem_idx only) */
3713 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
3714 {
3715 #if defined(CONFIG_USER_ONLY)
3716 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3717 #else
3718 /* Restore CPU state */
3719 if (unlikely(!ctx->mem_idx)) {
3720 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3721 return;
3722 }
3723 gen_helper_rfi();
3724 gen_sync_exception(ctx);
3725 #endif
3726 }
3727
3728 #if defined(TARGET_PPC64)
3729 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
3730 {
3731 #if defined(CONFIG_USER_ONLY)
3732 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3733 #else
3734 /* Restore CPU state */
3735 if (unlikely(!ctx->mem_idx)) {
3736 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3737 return;
3738 }
3739 gen_helper_rfid();
3740 gen_sync_exception(ctx);
3741 #endif
3742 }
3743
3744 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
3745 {
3746 #if defined(CONFIG_USER_ONLY)
3747 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3748 #else
3749 /* Restore CPU state */
3750 if (unlikely(ctx->mem_idx <= 1)) {
3751 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3752 return;
3753 }
3754 gen_helper_hrfid();
3755 gen_sync_exception(ctx);
3756 #endif
3757 }
3758 #endif
3759
3760 /* sc */
3761 #if defined(CONFIG_USER_ONLY)
3762 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3763 #else
3764 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3765 #endif
3766 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
3767 {
3768 uint32_t lev;
3769
3770 lev = (ctx->opcode >> 5) & 0x7F;
3771 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3772 }
3773
3774 /*** Trap ***/
3775 /* tw */
3776 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
3777 {
3778 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3779 /* Update the nip since this might generate a trap exception */
3780 gen_update_nip(ctx, ctx->nip);
3781 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3782 tcg_temp_free_i32(t0);
3783 }
3784
3785 /* twi */
3786 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3787 {
3788 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3789 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3790 /* Update the nip since this might generate a trap exception */
3791 gen_update_nip(ctx, ctx->nip);
3792 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3793 tcg_temp_free(t0);
3794 tcg_temp_free_i32(t1);
3795 }
3796
3797 #if defined(TARGET_PPC64)
3798 /* td */
3799 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3800 {
3801 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3802 /* Update the nip since this might generate a trap exception */
3803 gen_update_nip(ctx, ctx->nip);
3804 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3805 tcg_temp_free_i32(t0);
3806 }
3807
3808 /* tdi */
3809 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3810 {
3811 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3812 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3813 /* Update the nip since this might generate a trap exception */
3814 gen_update_nip(ctx, ctx->nip);
3815 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3816 tcg_temp_free(t0);
3817 tcg_temp_free_i32(t1);
3818 }
3819 #endif
3820
3821 /*** Processor control ***/
3822 /* mcrxr */
3823 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3824 {
3825 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3826 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3827 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
3828 }
3829
3830 /* mfcr */
3831 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3832 {
3833 uint32_t crm, crn;
3834
3835 if (likely(ctx->opcode & 0x00100000)) {
3836 crm = CRM(ctx->opcode);
3837 if (likely((crm ^ (crm - 1)) == 0)) {
3838 crn = ffs(crm);
3839 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3840 }
3841 } else {
3842 gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]);
3843 }
3844 }
3845
3846 /* mfmsr */
3847 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3848 {
3849 #if defined(CONFIG_USER_ONLY)
3850 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3851 #else
3852 if (unlikely(!ctx->mem_idx)) {
3853 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3854 return;
3855 }
3856 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3857 #endif
3858 }
3859
3860 #if 1
3861 #define SPR_NOACCESS ((void *)(-1UL))
3862 #else
3863 static void spr_noaccess (void *opaque, int sprn)
3864 {
3865 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3866 printf("ERROR: try to access SPR %d !\n", sprn);
3867 }
3868 #define SPR_NOACCESS (&spr_noaccess)
3869 #endif
3870
3871 /* mfspr */
3872 static always_inline void gen_op_mfspr (DisasContext *ctx)
3873 {
3874 void (*read_cb)(void *opaque, int gprn, int sprn);
3875 uint32_t sprn = SPR(ctx->opcode);
3876
3877 #if !defined(CONFIG_USER_ONLY)
3878 if (ctx->mem_idx == 2)
3879 read_cb = ctx->spr_cb[sprn].hea_read;
3880 else if (ctx->mem_idx)
3881 read_cb = ctx->spr_cb[sprn].oea_read;
3882 else
3883 #endif
3884 read_cb = ctx->spr_cb[sprn].uea_read;
3885 if (likely(read_cb != NULL)) {
3886 if (likely(read_cb != SPR_NOACCESS)) {
3887 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3888 } else {
3889 /* Privilege exception */
3890 /* This is a hack to avoid warnings when running Linux:
3891 * this OS breaks the PowerPC virtualisation model,
3892 * allowing userland application to read the PVR
3893 */
3894 if (sprn != SPR_PVR) {
3895 if (loglevel != 0) {
3896 fprintf(logfile, "Trying to read privileged spr %d %03x at "
3897 ADDRX "\n", sprn, sprn, ctx->nip);
3898 }
3899 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3900 sprn, sprn, ctx->nip);
3901 }
3902 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3903 }
3904 } else {
3905 /* Not defined */
3906 if (loglevel != 0) {
3907 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3908 ADDRX "\n", sprn, sprn, ctx->nip);
3909 }
3910 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3911 sprn, sprn, ctx->nip);
3912 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3913 }
3914 }
3915
3916 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
3917 {
3918 gen_op_mfspr(ctx);
3919 }
3920
3921 /* mftb */
3922 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3923 {
3924 gen_op_mfspr(ctx);
3925 }
3926
3927 /* mtcrf */
3928 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3929 {
3930 uint32_t crm, crn;
3931
3932 crm = CRM(ctx->opcode);
3933 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3934 TCGv_i32 temp = tcg_temp_new_i32();
3935 crn = ffs(crm);
3936 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3937 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3938 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3939 tcg_temp_free_i32(temp);
3940 } else {
3941 TCGv_i32 temp = tcg_const_i32(crm);
3942 gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp);
3943 tcg_temp_free_i32(temp);
3944 }
3945 }
3946
3947 /* mtmsr */
3948 #if defined(TARGET_PPC64)
3949 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3950 {
3951 #if defined(CONFIG_USER_ONLY)
3952 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3953 #else
3954 if (unlikely(!ctx->mem_idx)) {
3955 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3956 return;
3957 }
3958 if (ctx->opcode & 0x00010000) {
3959 /* Special form that does not need any synchronisation */
3960 TCGv t0 = tcg_temp_new();
3961 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3962 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3963 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3964 tcg_temp_free(t0);
3965 } else {
3966 /* XXX: we need to update nip before the store
3967 * if we enter power saving mode, we will exit the loop
3968 * directly from ppc_store_msr
3969 */
3970 gen_update_nip(ctx, ctx->nip);
3971 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
3972 /* Must stop the translation as machine state (may have) changed */
3973 /* Note that mtmsr is not always defined as context-synchronizing */
3974 gen_stop_exception(ctx);
3975 }
3976 #endif
3977 }
3978 #endif
3979
3980 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3981 {
3982 #if defined(CONFIG_USER_ONLY)
3983 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3984 #else
3985 if (unlikely(!ctx->mem_idx)) {
3986 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3987 return;
3988 }
3989 if (ctx->opcode & 0x00010000) {
3990 /* Special form that does not need any synchronisation */
3991 TCGv t0 = tcg_temp_new();
3992 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3993 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3994 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3995 tcg_temp_free(t0);
3996 } else {
3997 /* XXX: we need to update nip before the store
3998 * if we enter power saving mode, we will exit the loop
3999 * directly from ppc_store_msr
4000 */
4001 gen_update_nip(ctx, ctx->nip);
4002 #if defined(TARGET_PPC64)
4003 if (!ctx->sf_mode) {
4004 TCGv t0 = tcg_temp_new();
4005 TCGv t1 = tcg_temp_new();
4006 tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
4007 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
4008 tcg_gen_or_tl(t0, t0, t1);
4009 tcg_temp_free(t1);
4010 gen_helper_store_msr(t0);
4011 tcg_temp_free(t0);
4012 } else
4013 #endif
4014 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
4015 /* Must stop the translation as machine state (may have) changed */
4016 /* Note that mtmsr is not always defined as context-synchronizing */
4017 gen_stop_exception(ctx);
4018 }
4019 #endif
4020 }
4021
4022 /* mtspr */
4023 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
4024 {
4025 void (*write_cb)(void *opaque, int sprn, int gprn);
4026 uint32_t sprn = SPR(ctx->opcode);
4027
4028 #if !defined(CONFIG_USER_ONLY)
4029 if (ctx->mem_idx == 2)
4030 write_cb = ctx->spr_cb[sprn].hea_write;
4031 else if (ctx->mem_idx)
4032 write_cb = ctx->spr_cb[sprn].oea_write;
4033 else
4034 #endif
4035 write_cb = ctx->spr_cb[sprn].uea_write;
4036 if (likely(write_cb != NULL)) {
4037 if (likely(write_cb != SPR_NOACCESS)) {
4038 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4039 } else {
4040 /* Privilege exception */
4041 if (loglevel != 0) {
4042 fprintf(logfile, "Trying to write privileged spr %d %03x at "
4043 ADDRX "\n", sprn, sprn, ctx->nip);
4044 }
4045 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
4046 sprn, sprn, ctx->nip);
4047 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4048 }
4049 } else {
4050 /* Not defined */
4051 if (loglevel != 0) {
4052 fprintf(logfile, "Trying to write invalid spr %d %03x at "
4053 ADDRX "\n", sprn, sprn, ctx->nip);
4054 }
4055 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4056 sprn, sprn, ctx->nip);
4057 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4058 }
4059 }
4060
4061 /*** Cache management ***/
4062 /* dcbf */
4063 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
4064 {
4065 /* XXX: specification says this is treated as a load by the MMU */
4066 TCGv t0;
4067 gen_set_access_type(ctx, ACCESS_CACHE);
4068 t0 = tcg_temp_new();
4069 gen_addr_reg_index(ctx, t0);
4070 gen_qemu_ld8u(ctx, t0, t0);
4071 tcg_temp_free(t0);
4072 }
4073
4074 /* dcbi (Supervisor only) */
4075 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
4076 {
4077 #if defined(CONFIG_USER_ONLY)
4078 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4079 #else
4080 TCGv EA, val;
4081 if (unlikely(!ctx->mem_idx)) {
4082 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4083 return;
4084 }
4085 EA = tcg_temp_new();
4086 gen_set_access_type(ctx, ACCESS_CACHE);
4087 gen_addr_reg_index(ctx, EA);
4088 val = tcg_temp_new();
4089 /* XXX: specification says this should be treated as a store by the MMU */
4090 gen_qemu_ld8u(ctx, val, EA);
4091 gen_qemu_st8(ctx, val, EA);
4092 tcg_temp_free(val);
4093 tcg_temp_free(EA);
4094 #endif
4095 }
4096
4097 /* dcdst */
4098 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
4099 {
4100 /* XXX: specification say this is treated as a load by the MMU */
4101 TCGv t0;
4102 gen_set_access_type(ctx, ACCESS_CACHE);
4103 t0 = tcg_temp_new();
4104 gen_addr_reg_index(ctx, t0);
4105 gen_qemu_ld8u(ctx, t0, t0);
4106 tcg_temp_free(t0);
4107 }
4108
4109 /* dcbt */
4110 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
4111 {
4112 /* interpreted as no-op */
4113 /* XXX: specification say this is treated as a load by the MMU
4114 * but does not generate any exception
4115 */
4116 }
4117
4118 /* dcbtst */
4119 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
4120 {
4121 /* interpreted as no-op */
4122 /* XXX: specification say this is treated as a load by the MMU
4123 * but does not generate any exception
4124 */
4125 }
4126
4127 /* dcbz */
4128 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
4129 {
4130 TCGv t0;
4131 gen_set_access_type(ctx, ACCESS_CACHE);
4132 /* NIP cannot be restored if the memory exception comes from an helper */
4133 gen_update_nip(ctx, ctx->nip - 4);
4134 t0 = tcg_temp_new();
4135 gen_addr_reg_index(ctx, t0);
4136 gen_helper_dcbz(t0);
4137 tcg_temp_free(t0);
4138 }
4139
4140 GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
4141 {
4142 TCGv t0;
4143 gen_set_access_type(ctx, ACCESS_CACHE);
4144 /* NIP cannot be restored if the memory exception comes from an helper */
4145 gen_update_nip(ctx, ctx->nip - 4);
4146 t0 = tcg_temp_new();
4147 gen_addr_reg_index(ctx, t0);
4148 if (ctx->opcode & 0x00200000)
4149 gen_helper_dcbz(t0);
4150 else
4151 gen_helper_dcbz_970(t0);
4152 tcg_temp_free(t0);
4153 }
4154
4155 /* icbi */
4156 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
4157 {
4158 TCGv t0;
4159 gen_set_access_type(ctx, ACCESS_CACHE);
4160 /* NIP cannot be restored if the memory exception comes from an helper */
4161 gen_update_nip(ctx, ctx->nip - 4);
4162 t0 = tcg_temp_new();
4163 gen_addr_reg_index(ctx, t0);
4164 gen_helper_icbi(t0);
4165 tcg_temp_free(t0);
4166 }
4167
4168 /* Optional: */
4169 /* dcba */
4170 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
4171 {
4172 /* interpreted as no-op */
4173 /* XXX: specification say this is treated as a store by the MMU
4174 * but does not generate any exception
4175 */
4176 }
4177
4178 /*** Segment register manipulation ***/
4179 /* Supervisor only: */
4180 /* mfsr */
4181 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4182 {
4183 #if defined(CONFIG_USER_ONLY)
4184 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4185 #else
4186 TCGv t0;
4187 if (unlikely(!ctx->mem_idx)) {
4188 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4189 return;
4190 }
4191 t0 = tcg_const_tl(SR(ctx->opcode));
4192 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4193 tcg_temp_free(t0);
4194 #endif
4195 }
4196
4197 /* mfsrin */
4198 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
4199 {
4200 #if defined(CONFIG_USER_ONLY)
4201 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4202 #else
4203 TCGv t0;
4204 if (unlikely(!ctx->mem_idx)) {
4205 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4206 return;
4207 }
4208 t0 = tcg_temp_new();
4209 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4210 tcg_gen_andi_tl(t0, t0, 0xF);
4211 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4212 tcg_temp_free(t0);
4213 #endif
4214 }
4215
4216 /* mtsr */
4217 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
4218 {
4219 #if defined(CONFIG_USER_ONLY)
4220 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4221 #else
4222 TCGv t0;
4223 if (unlikely(!ctx->mem_idx)) {
4224 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4225 return;
4226 }
4227 t0 = tcg_const_tl(SR(ctx->opcode));
4228 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4229 tcg_temp_free(t0);
4230 #endif
4231 }
4232
4233 /* mtsrin */
4234 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
4235 {
4236 #if defined(CONFIG_USER_ONLY)
4237 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4238 #else
4239 TCGv t0;
4240 if (unlikely(!ctx->mem_idx)) {
4241 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4242 return;
4243 }
4244 t0 = tcg_temp_new();
4245 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4246 tcg_gen_andi_tl(t0, t0, 0xF);
4247 gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4248 tcg_temp_free(t0);
4249 #endif
4250 }
4251
4252 #if defined(TARGET_PPC64)
4253 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4254 /* mfsr */
4255 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
4256 {
4257 #if defined(CONFIG_USER_ONLY)
4258 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4259 #else
4260 TCGv t0;
4261 if (unlikely(!ctx->mem_idx)) {
4262 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4263 return;
4264 }
4265 t0 = tcg_const_tl(SR(ctx->opcode));
4266 gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4267 tcg_temp_free(t0);
4268 #endif
4269 }
4270
4271 /* mfsrin */
4272 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4273 PPC_SEGMENT_64B)
4274 {
4275 #if defined(CONFIG_USER_ONLY)
4276 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4277 #else
4278 TCGv t0;
4279 if (unlikely(!ctx->mem_idx)) {
4280 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4281 return;
4282 }
4283 t0 = tcg_temp_new();
4284 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4285 tcg_gen_andi_tl(t0, t0, 0xF);
4286 gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4287 tcg_temp_free(t0);
4288 #endif
4289 }
4290
4291 /* mtsr */
4292 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
4293 {
4294 #if defined(CONFIG_USER_ONLY)
4295 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4296 #else
4297 TCGv t0;
4298 if (unlikely(!ctx->mem_idx)) {
4299 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4300 return;
4301 }
4302 t0 = tcg_const_tl(SR(ctx->opcode));
4303 gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4304 tcg_temp_free(t0);
4305 #endif
4306 }
4307
4308 /* mtsrin */
4309 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4310 PPC_SEGMENT_64B)
4311 {
4312 #if defined(CONFIG_USER_ONLY)
4313 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4314 #else
4315 TCGv t0;
4316 if (unlikely(!ctx->mem_idx)) {
4317 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4318 return;
4319 }
4320 t0 = tcg_temp_new();
4321 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4322 tcg_gen_andi_tl(t0, t0, 0xF);
4323 gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4324 tcg_temp_free(t0);
4325 #endif
4326 }
4327 #endif /* defined(TARGET_PPC64) */
4328
4329 /*** Lookaside buffer management ***/
4330 /* Optional & mem_idx only: */
4331 /* tlbia */
4332 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
4333 {
4334 #if defined(CONFIG_USER_ONLY)
4335 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4336 #else
4337 if (unlikely(!ctx->mem_idx)) {
4338 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4339 return;
4340 }
4341 gen_helper_tlbia();
4342 #endif
4343 }
4344
4345 /* tlbie */
4346 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
4347 {
4348 #if defined(CONFIG_USER_ONLY)
4349 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4350 #else
4351 if (unlikely(!ctx->mem_idx)) {
4352 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4353 return;
4354 }
4355 #if defined(TARGET_PPC64)
4356 if (!ctx->sf_mode) {
4357 TCGv t0 = tcg_temp_new();
4358 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4359 gen_helper_tlbie(t0);
4360 tcg_temp_free(t0);
4361 } else
4362 #endif
4363 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4364 #endif
4365 }
4366
4367 /* tlbsync */
4368 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
4369 {
4370 #if defined(CONFIG_USER_ONLY)
4371 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4372 #else
4373 if (unlikely(!ctx->mem_idx)) {
4374 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4375 return;
4376 }
4377 /* This has no effect: it should ensure that all previous
4378 * tlbie have completed
4379 */
4380 gen_stop_exception(ctx);
4381 #endif
4382 }
4383
4384 #if defined(TARGET_PPC64)
4385 /* slbia */
4386 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4387 {
4388 #if defined(CONFIG_USER_ONLY)
4389 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4390 #else
4391 if (unlikely(!ctx->mem_idx)) {
4392 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4393 return;
4394 }
4395 gen_helper_slbia();
4396 #endif
4397 }
4398
4399 /* slbie */
4400 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4401 {
4402 #if defined(CONFIG_USER_ONLY)
4403 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4404 #else
4405 if (unlikely(!ctx->mem_idx)) {
4406 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4407 return;
4408 }
4409 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
4410 #endif
4411 }
4412 #endif
4413
4414 /*** External control ***/
4415 /* Optional: */
4416 /* eciwx */
4417 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4418 {
4419 TCGv t0;
4420 /* Should check EAR[E] ! */
4421 gen_set_access_type(ctx, ACCESS_EXT);
4422 t0 = tcg_temp_new();
4423 gen_addr_reg_index(ctx, t0);
4424 gen_check_align(ctx, t0, 0x03);
4425 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4426 tcg_temp_free(t0);
4427 }
4428
4429 /* ecowx */
4430 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4431 {
4432 TCGv t0;
4433 /* Should check EAR[E] ! */
4434 gen_set_access_type(ctx, ACCESS_EXT);
4435 t0 = tcg_temp_new();
4436 gen_addr_reg_index(ctx, t0);
4437 gen_check_align(ctx, t0, 0x03);
4438 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4439 tcg_temp_free(t0);
4440 }
4441
4442 /* PowerPC 601 specific instructions */
4443 /* abs - abs. */
4444 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4445 {
4446 int l1 = gen_new_label();
4447 int l2 = gen_new_label();
4448 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4449 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4450 tcg_gen_br(l2);
4451 gen_set_label(l1);
4452 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4453 gen_set_label(l2);
4454 if (unlikely(Rc(ctx->opcode) != 0))
4455 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4456 }
4457
4458 /* abso - abso. */
4459 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4460 {
4461 int l1 = gen_new_label();
4462 int l2 = gen_new_label();
4463 int l3 = gen_new_label();
4464 /* Start with XER OV disabled, the most likely case */
4465 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4466 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4467 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4468 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4469 tcg_gen_br(l2);
4470 gen_set_label(l1);
4471 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4472 tcg_gen_br(l3);
4473 gen_set_label(l2);
4474 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4475 gen_set_label(l3);
4476 if (unlikely(Rc(ctx->opcode) != 0))
4477 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4478 }
4479
4480 /* clcs */
4481 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
4482 {
4483 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4484 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4485 tcg_temp_free_i32(t0);
4486 /* Rc=1 sets CR0 to an undefined state */
4487 }
4488
4489 /* div - div. */
4490 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4491 {
4492 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4493 if (unlikely(Rc(ctx->opcode) != 0))
4494 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4495 }
4496
4497 /* divo - divo. */
4498 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4499 {
4500 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4501 if (unlikely(Rc(ctx->opcode) != 0))
4502 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4503 }
4504
4505 /* divs - divs. */
4506 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4507 {
4508 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4509 if (unlikely(Rc(ctx->opcode) != 0))
4510 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4511 }
4512
4513 /* divso - divso. */
4514 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4515 {
4516 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4517 if (unlikely(Rc(ctx->opcode) != 0))
4518 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4519 }
4520
4521 /* doz - doz. */
4522 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4523 {
4524 int l1 = gen_new_label();
4525 int l2 = gen_new_label();
4526 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4527 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4528 tcg_gen_br(l2);
4529 gen_set_label(l1);
4530 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4531 gen_set_label(l2);
4532 if (unlikely(Rc(ctx->opcode) != 0))
4533 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4534 }
4535
4536 /* dozo - dozo. */
4537 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4538 {
4539 int l1 = gen_new_label();
4540 int l2 = gen_new_label();
4541 TCGv t0 = tcg_temp_new();
4542 TCGv t1 = tcg_temp_new();
4543 TCGv t2 = tcg_temp_new();
4544 /* Start with XER OV disabled, the most likely case */
4545 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4546 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4547 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4548 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4549 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4550 tcg_gen_andc_tl(t1, t1, t2);
4551 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4552 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4553 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4554 tcg_gen_br(l2);
4555 gen_set_label(l1);
4556 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4557 gen_set_label(l2);
4558 tcg_temp_free(t0);
4559 tcg_temp_free(t1);
4560 tcg_temp_free(t2);
4561 if (unlikely(Rc(ctx->opcode) != 0))
4562 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4563 }
4564
4565 /* dozi */
4566 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4567 {
4568 target_long simm = SIMM(ctx->opcode);
4569 int l1 = gen_new_label();
4570 int l2 = gen_new_label();
4571 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4572 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4573 tcg_gen_br(l2);
4574 gen_set_label(l1);
4575 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4576 gen_set_label(l2);
4577 if (unlikely(Rc(ctx->opcode) != 0))
4578 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4579 }
4580
4581 /* lscbx - lscbx. */
4582 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4583 {
4584 TCGv t0 = tcg_temp_new();
4585 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4586 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4587 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4588
4589 gen_addr_reg_index(ctx, t0);
4590 /* NIP cannot be restored if the memory exception comes from an helper */
4591 gen_update_nip(ctx, ctx->nip - 4);
4592 gen_helper_lscbx(t0, t0, t1, t2, t3);
4593 tcg_temp_free_i32(t1);
4594 tcg_temp_free_i32(t2);
4595 tcg_temp_free_i32(t3);
4596 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4597 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4598 if (unlikely(Rc(ctx->opcode) != 0))
4599 gen_set_Rc0(ctx, t0);
4600 tcg_temp_free(t0);
4601 }
4602
4603 /* maskg - maskg. */
4604 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4605 {
4606 int l1 = gen_new_label();
4607 TCGv t0 = tcg_temp_new();
4608 TCGv t1 = tcg_temp_new();
4609 TCGv t2 = tcg_temp_new();
4610 TCGv t3 = tcg_temp_new();
4611 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4612 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4613 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4614 tcg_gen_addi_tl(t2, t0, 1);
4615 tcg_gen_shr_tl(t2, t3, t2);
4616 tcg_gen_shr_tl(t3, t3, t1);
4617 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4618 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4619 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4620 gen_set_label(l1);
4621 tcg_temp_free(t0);
4622 tcg_temp_free(t1);
4623 tcg_temp_free(t2);
4624 tcg_temp_free(t3);
4625 if (unlikely(Rc(ctx->opcode) != 0))
4626 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4627 }
4628
4629 /* maskir - maskir. */
4630 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4631 {
4632 TCGv t0 = tcg_temp_new();
4633 TCGv t1 = tcg_temp_new();
4634 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4635 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4636 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4637 tcg_temp_free(t0);
4638 tcg_temp_free(t1);
4639 if (unlikely(Rc(ctx->opcode) != 0))
4640 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4641 }
4642
4643 /* mul - mul. */
4644 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4645 {
4646 TCGv_i64 t0 = tcg_temp_new_i64();
4647 TCGv_i64 t1 = tcg_temp_new_i64();
4648 TCGv t2 = tcg_temp_new();
4649 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4650 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4651 tcg_gen_mul_i64(t0, t0, t1);
4652 tcg_gen_trunc_i64_tl(t2, t0);
4653 gen_store_spr(SPR_MQ, t2);
4654 tcg_gen_shri_i64(t1, t0, 32);
4655 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4656 tcg_temp_free_i64(t0);
4657 tcg_temp_free_i64(t1);
4658 tcg_temp_free(t2);
4659 if (unlikely(Rc(ctx->opcode) != 0))
4660 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4661 }
4662
4663 /* mulo - mulo. */
4664 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4665 {
4666 int l1 = gen_new_label();
4667 TCGv_i64 t0 = tcg_temp_new_i64();
4668 TCGv_i64 t1 = tcg_temp_new_i64();
4669 TCGv t2 = tcg_temp_new();
4670 /* Start with XER OV disabled, the most likely case */
4671 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4672 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4673 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4674 tcg_gen_mul_i64(t0, t0, t1);
4675 tcg_gen_trunc_i64_tl(t2, t0);
4676 gen_store_spr(SPR_MQ, t2);
4677 tcg_gen_shri_i64(t1, t0, 32);
4678 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4679 tcg_gen_ext32s_i64(t1, t0);
4680 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4681 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4682 gen_set_label(l1);
4683 tcg_temp_free_i64(t0);
4684 tcg_temp_free_i64(t1);
4685 tcg_temp_free(t2);
4686 if (unlikely(Rc(ctx->opcode) != 0))
4687 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4688 }
4689
4690 /* nabs - nabs. */
4691 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4692 {
4693 int l1 = gen_new_label();
4694 int l2 = gen_new_label();
4695 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4696 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4697 tcg_gen_br(l2);
4698 gen_set_label(l1);
4699 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4700 gen_set_label(l2);
4701 if (unlikely(Rc(ctx->opcode) != 0))
4702 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4703 }
4704
4705 /* nabso - nabso. */
4706 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4707 {
4708 int l1 = gen_new_label();
4709 int l2 = gen_new_label();
4710 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4711 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4712 tcg_gen_br(l2);
4713 gen_set_label(l1);
4714 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4715 gen_set_label(l2);
4716 /* nabs never overflows */
4717 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4718 if (unlikely(Rc(ctx->opcode) != 0))
4719 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4720 }
4721
4722 /* rlmi - rlmi. */
4723 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4724 {
4725 uint32_t mb = MB(ctx->opcode);
4726 uint32_t me = ME(ctx->opcode);
4727 TCGv t0 = tcg_temp_new();
4728 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4729 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4730 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4731 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4732 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4733 tcg_temp_free(t0);
4734 if (unlikely(Rc(ctx->opcode) != 0))
4735 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4736 }
4737
4738 /* rrib - rrib. */
4739 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4740 {
4741 TCGv t0 = tcg_temp_new();
4742 TCGv t1 = tcg_temp_new();
4743 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4744 tcg_gen_movi_tl(t1, 0x80000000);
4745 tcg_gen_shr_tl(t1, t1, t0);
4746 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4747 tcg_gen_and_tl(t0, t0, t1);
4748 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4749 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4750 tcg_temp_free(t0);
4751 tcg_temp_free(t1);
4752 if (unlikely(Rc(ctx->opcode) != 0))
4753 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4754 }
4755
4756 /* sle - sle. */
4757 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4758 {
4759 TCGv t0 = tcg_temp_new();
4760 TCGv t1 = tcg_temp_new();
4761 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4762 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4763 tcg_gen_subfi_tl(t1, 32, t1);
4764 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4765 tcg_gen_or_tl(t1, t0, t1);
4766 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4767 gen_store_spr(SPR_MQ, t1);
4768 tcg_temp_free(t0);
4769 tcg_temp_free(t1);
4770 if (unlikely(Rc(ctx->opcode) != 0))
4771 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4772 }
4773
4774 /* sleq - sleq. */
4775 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4776 {
4777 TCGv t0 = tcg_temp_new();
4778 TCGv t1 = tcg_temp_new();
4779 TCGv t2 = tcg_temp_new();
4780 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4781 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4782 tcg_gen_shl_tl(t2, t2, t0);
4783 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4784 gen_load_spr(t1, SPR_MQ);
4785 gen_store_spr(SPR_MQ, t0);
4786 tcg_gen_and_tl(t0, t0, t2);
4787 tcg_gen_andc_tl(t1, t1, t2);
4788 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4789 tcg_temp_free(t0);
4790 tcg_temp_free(t1);
4791 tcg_temp_free(t2);
4792 if (unlikely(Rc(ctx->opcode) != 0))
4793 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4794 }
4795
4796 /* sliq - sliq. */
4797 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4798 {
4799 int sh = SH(ctx->opcode);
4800 TCGv t0 = tcg_temp_new();
4801 TCGv t1 = tcg_temp_new();
4802 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4803 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4804 tcg_gen_or_tl(t1, t0, t1);
4805 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4806 gen_store_spr(SPR_MQ, t1);
4807 tcg_temp_free(t0);
4808 tcg_temp_free(t1);
4809 if (unlikely(Rc(ctx->opcode) != 0))
4810 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4811 }
4812
4813 /* slliq - slliq. */
4814 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4815 {
4816 int sh = SH(ctx->opcode);
4817 TCGv t0 = tcg_temp_new();
4818 TCGv t1 = tcg_temp_new();
4819 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4820 gen_load_spr(t1, SPR_MQ);
4821 gen_store_spr(SPR_MQ, t0);
4822 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4823 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4824 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4825 tcg_temp_free(t0);
4826 tcg_temp_free(t1);
4827 if (unlikely(Rc(ctx->opcode) != 0))
4828 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4829 }
4830
4831 /* sllq - sllq. */
4832 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4833 {
4834 int l1 = gen_new_label();
4835 int l2 = gen_new_label();
4836 TCGv t0 = tcg_temp_local_new();
4837 TCGv t1 = tcg_temp_local_new();
4838 TCGv t2 = tcg_temp_local_new();
4839 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4840 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4841 tcg_gen_shl_tl(t1, t1, t2);
4842 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4843 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4844 gen_load_spr(t0, SPR_MQ);
4845 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4846 tcg_gen_br(l2);
4847 gen_set_label(l1);
4848 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4849 gen_load_spr(t2, SPR_MQ);
4850 tcg_gen_andc_tl(t1, t2, t1);
4851 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4852 gen_set_label(l2);
4853 tcg_temp_free(t0);
4854 tcg_temp_free(t1);
4855 tcg_temp_free(t2);
4856 if (unlikely(Rc(ctx->opcode) != 0))
4857 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4858 }
4859
4860 /* slq - slq. */
4861 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4862 {
4863 int l1 = gen_new_label();
4864 TCGv t0 = tcg_temp_new();
4865 TCGv t1 = tcg_temp_new();
4866 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4867 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4868 tcg_gen_subfi_tl(t1, 32, t1);
4869 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4870 tcg_gen_or_tl(t1, t0, t1);
4871 gen_store_spr(SPR_MQ, t1);
4872 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4873 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4874 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4875 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4876 gen_set_label(l1);
4877 tcg_temp_free(t0);
4878 tcg_temp_free(t1);
4879 if (unlikely(Rc(ctx->opcode) != 0))
4880 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4881 }
4882
4883 /* sraiq - sraiq. */
4884 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4885 {
4886 int sh = SH(ctx->opcode);
4887 int l1 = gen_new_label();
4888 TCGv t0 = tcg_temp_new();
4889 TCGv t1 = tcg_temp_new();
4890 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4891 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4892 tcg_gen_or_tl(t0, t0, t1);
4893 gen_store_spr(SPR_MQ, t0);
4894 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4895 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4896 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4897 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4898 gen_set_label(l1);
4899 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4900 tcg_temp_free(t0);
4901 tcg_temp_free(t1);
4902 if (unlikely(Rc(ctx->opcode) != 0))
4903 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4904 }
4905
4906 /* sraq - sraq. */
4907 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4908 {
4909 int l1 = gen_new_label();
4910 int l2 = gen_new_label();
4911 TCGv t0 = tcg_temp_new();
4912 TCGv t1 = tcg_temp_local_new();
4913 TCGv t2 = tcg_temp_local_new();
4914 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4915 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4916 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4917 tcg_gen_subfi_tl(t2, 32, t2);
4918 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4919 tcg_gen_or_tl(t0, t0, t2);
4920 gen_store_spr(SPR_MQ, t0);
4921 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4922 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4923 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4924 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4925 gen_set_label(l1);
4926 tcg_temp_free(t0);
4927 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4928 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4929 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4930 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4931 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4932 gen_set_label(l2);
4933 tcg_temp_free(t1);
4934 tcg_temp_free(t2);
4935 if (unlikely(Rc(ctx->opcode) != 0))
4936 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4937 }
4938
4939 /* sre - sre. */
4940 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4941 {
4942 TCGv t0 = tcg_temp_new();
4943 TCGv t1 = tcg_temp_new();
4944 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4945 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4946 tcg_gen_subfi_tl(t1, 32, t1);
4947 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4948 tcg_gen_or_tl(t1, t0, t1);
4949 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4950 gen_store_spr(SPR_MQ, t1);
4951 tcg_temp_free(t0);
4952 tcg_temp_free(t1);
4953 if (unlikely(Rc(ctx->opcode) != 0))
4954 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4955 }
4956
4957 /* srea - srea. */
4958 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4959 {
4960 TCGv t0 = tcg_temp_new();
4961 TCGv t1 = tcg_temp_new();
4962 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4963 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4964 gen_store_spr(SPR_MQ, t0);
4965 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4966 tcg_temp_free(t0);
4967 tcg_temp_free(t1);
4968 if (unlikely(Rc(ctx->opcode) != 0))
4969 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4970 }
4971
4972 /* sreq */
4973 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4974 {
4975 TCGv t0 = tcg_temp_new();
4976 TCGv t1 = tcg_temp_new();
4977 TCGv t2 = tcg_temp_new();
4978 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4979 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4980 tcg_gen_shr_tl(t1, t1, t0);
4981 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4982 gen_load_spr(t2, SPR_MQ);
4983 gen_store_spr(SPR_MQ, t0);
4984 tcg_gen_and_tl(t0, t0, t1);
4985 tcg_gen_andc_tl(t2, t2, t1);
4986 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4987 tcg_temp_free(t0);
4988 tcg_temp_free(t1);
4989 tcg_temp_free(t2);
4990 if (unlikely(Rc(ctx->opcode) != 0))
4991 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4992 }
4993
4994 /* sriq */
4995 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4996 {
4997 int sh = SH(ctx->opcode);
4998 TCGv t0 = tcg_temp_new();
4999 TCGv t1 = tcg_temp_new();
5000 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5001 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5002 tcg_gen_or_tl(t1, t0, t1);
5003 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5004 gen_store_spr(SPR_MQ, t1);
5005 tcg_temp_free(t0);
5006 tcg_temp_free(t1);
5007 if (unlikely(Rc(ctx->opcode) != 0))
5008 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5009 }
5010
5011 /* srliq */
5012 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
5013 {
5014 int sh = SH(ctx->opcode);
5015 TCGv t0 = tcg_temp_new();
5016 TCGv t1 = tcg_temp_new();
5017 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5018 gen_load_spr(t1, SPR_MQ);
5019 gen_store_spr(SPR_MQ, t0);
5020 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5021 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5022 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5023 tcg_temp_free(t0);
5024 tcg_temp_free(t1);
5025 if (unlikely(Rc(ctx->opcode) != 0))
5026 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5027 }
5028
5029 /* srlq */
5030 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
5031 {
5032 int l1 = gen_new_label();
5033 int l2 = gen_new_label();
5034 TCGv t0 = tcg_temp_local_new();
5035 TCGv t1 = tcg_temp_local_new();
5036 TCGv t2 = tcg_temp_local_new();
5037 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5038 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5039 tcg_gen_shr_tl(t2, t1, t2);
5040 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5041 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5042 gen_load_spr(t0, SPR_MQ);
5043 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5044 tcg_gen_br(l2);
5045 gen_set_label(l1);
5046 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5047 tcg_gen_and_tl(t0, t0, t2);
5048 gen_load_spr(t1, SPR_MQ);
5049 tcg_gen_andc_tl(t1, t1, t2);
5050 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5051 gen_set_label(l2);
5052 tcg_temp_free(t0);
5053 tcg_temp_free(t1);
5054 tcg_temp_free(t2);
5055 if (unlikely(Rc(ctx->opcode) != 0))
5056 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5057 }
5058
5059 /* srq */
5060 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
5061 {
5062 int l1 = gen_new_label();
5063 TCGv t0 = tcg_temp_new();
5064 TCGv t1 = tcg_temp_new();
5065 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5066 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5067 tcg_gen_subfi_tl(t1, 32, t1);
5068 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5069 tcg_gen_or_tl(t1, t0, t1);
5070 gen_store_spr(SPR_MQ, t1);
5071 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5072 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5073 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5074 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5075 gen_set_label(l1);
5076 tcg_temp_free(t0);
5077 tcg_temp_free(t1);
5078 if (unlikely(Rc(ctx->opcode) != 0))
5079 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5080 }
5081
5082 /* PowerPC 602 specific instructions */
5083 /* dsa */
5084 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
5085 {
5086 /* XXX: TODO */
5087 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5088 }
5089
5090 /* esa */
5091 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
5092 {
5093 /* XXX: TODO */
5094 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5095 }
5096
5097 /* mfrom */
5098 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
5099 {
5100 #if defined(CONFIG_USER_ONLY)
5101 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5102 #else
5103 if (unlikely(!ctx->mem_idx)) {
5104 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5105 return;
5106 }
5107 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5108 #endif
5109 }
5110
5111 /* 602 - 603 - G2 TLB management */
5112 /* tlbld */
5113 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
5114 {
5115 #if defined(CONFIG_USER_ONLY)
5116 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5117 #else
5118 if (unlikely(!ctx->mem_idx)) {
5119 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5120 return;
5121 }
5122 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5123 #endif
5124 }
5125
5126 /* tlbli */
5127 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
5128 {
5129 #if defined(CONFIG_USER_ONLY)
5130 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5131 #else
5132 if (unlikely(!ctx->mem_idx)) {
5133 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5134 return;
5135 }
5136 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5137 #endif
5138 }
5139
5140 /* 74xx TLB management */
5141 /* tlbld */
5142 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
5143 {
5144 #if defined(CONFIG_USER_ONLY)
5145 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5146 #else
5147 if (unlikely(!ctx->mem_idx)) {
5148 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5149 return;
5150 }
5151 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5152 #endif
5153 }
5154
5155 /* tlbli */
5156 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
5157 {
5158 #if defined(CONFIG_USER_ONLY)
5159 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5160 #else
5161 if (unlikely(!ctx->mem_idx)) {
5162 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5163 return;
5164 }
5165 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5166 #endif
5167 }
5168
5169 /* POWER instructions not in PowerPC 601 */
5170 /* clf */
5171 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
5172 {
5173 /* Cache line flush: implemented as no-op */
5174 }
5175
5176 /* cli */
5177 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
5178 {
5179 /* Cache line invalidate: privileged and treated as no-op */
5180 #if defined(CONFIG_USER_ONLY)
5181 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5182 #else
5183 if (unlikely(!ctx->mem_idx)) {
5184 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5185 return;
5186 }
5187 #endif
5188 }
5189
5190 /* dclst */
5191 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
5192 {
5193 /* Data cache line store: treated as no-op */
5194 }
5195
5196 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
5197 {
5198 #if defined(CONFIG_USER_ONLY)
5199 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5200 #else
5201 int ra = rA(ctx->opcode);
5202 int rd = rD(ctx->opcode);
5203 TCGv t0;
5204 if (unlikely(!ctx->mem_idx)) {
5205 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5206 return;
5207 }
5208 t0 = tcg_temp_new();
5209 gen_addr_reg_index(ctx, t0);
5210 tcg_gen_shri_tl(t0, t0, 28);
5211 tcg_gen_andi_tl(t0, t0, 0xF);
5212 gen_helper_load_sr(cpu_gpr[rd], t0);
5213 tcg_temp_free(t0);
5214 if (ra != 0 && ra != rd)
5215 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5216 #endif
5217 }
5218
5219 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
5220 {
5221 #if defined(CONFIG_USER_ONLY)
5222 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5223 #else
5224 TCGv t0;
5225 if (unlikely(!ctx->mem_idx)) {
5226 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5227 return;
5228 }
5229 t0 = tcg_temp_new();
5230 gen_addr_reg_index(ctx, t0);
5231 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
5232 tcg_temp_free(t0);
5233 #endif
5234 }
5235
5236 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5237 {
5238 #if defined(CONFIG_USER_ONLY)
5239 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5240 #else
5241 if (unlikely(!ctx->mem_idx)) {
5242 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5243 return;
5244 }
5245 gen_helper_rfsvc();
5246 gen_sync_exception(ctx);
5247 #endif
5248 }
5249
5250 /* svc is not implemented for now */
5251
5252 /* POWER2 specific instructions */
5253 /* Quad manipulation (load/store two floats at a time) */
5254
5255 /* lfq */
5256 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5257 {
5258 int rd = rD(ctx->opcode);
5259 TCGv t0;
5260 gen_set_access_type(ctx, ACCESS_FLOAT);
5261 t0 = tcg_temp_new();
5262 gen_addr_imm_index(ctx, t0, 0);
5263 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5264 gen_addr_add(ctx, t0, t0, 8);
5265 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5266 tcg_temp_free(t0);
5267 }
5268
5269 /* lfqu */
5270 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5271 {
5272 int ra = rA(ctx->opcode);
5273 int rd = rD(ctx->opcode);
5274 TCGv t0, t1;
5275 gen_set_access_type(ctx, ACCESS_FLOAT);
5276 t0 = tcg_temp_new();
5277 t1 = tcg_temp_new();
5278 gen_addr_imm_index(ctx, t0, 0);
5279 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5280 gen_addr_add(ctx, t1, t0, 8);
5281 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5282 if (ra != 0)
5283 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5284 tcg_temp_free(t0);
5285 tcg_temp_free(t1);
5286 }
5287
5288 /* lfqux */
5289 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5290 {
5291 int ra = rA(ctx->opcode);
5292 int rd = rD(ctx->opcode);
5293 gen_set_access_type(ctx, ACCESS_FLOAT);
5294 TCGv t0, t1;
5295 t0 = tcg_temp_new();
5296 gen_addr_reg_index(ctx, t0);
5297 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5298 t1 = tcg_temp_new();
5299 gen_addr_add(ctx, t1, t0, 8);
5300 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5301 tcg_temp_free(t1);
5302 if (ra != 0)
5303 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5304 tcg_temp_free(t0);
5305 }
5306
5307 /* lfqx */
5308 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5309 {
5310 int rd = rD(ctx->opcode);
5311 TCGv t0;
5312 gen_set_access_type(ctx, ACCESS_FLOAT);
5313 t0 = tcg_temp_new();
5314 gen_addr_reg_index(ctx, t0);
5315 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5316 gen_addr_add(ctx, t0, t0, 8);
5317 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5318 tcg_temp_free(t0);
5319 }
5320
5321 /* stfq */
5322 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5323 {
5324 int rd = rD(ctx->opcode);
5325 TCGv t0;
5326 gen_set_access_type(ctx, ACCESS_FLOAT);
5327 t0 = tcg_temp_new();
5328 gen_addr_imm_index(ctx, t0, 0);
5329 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5330 gen_addr_add(ctx, t0, t0, 8);
5331 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5332 tcg_temp_free(t0);
5333 }
5334
5335 /* stfqu */
5336 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5337 {
5338 int ra = rA(ctx->opcode);
5339 int rd = rD(ctx->opcode);
5340 TCGv t0, t1;
5341 gen_set_access_type(ctx, ACCESS_FLOAT);
5342 t0 = tcg_temp_new();
5343 gen_addr_imm_index(ctx, t0, 0);
5344 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5345 t1 = tcg_temp_new();
5346 gen_addr_add(ctx, t1, t0, 8);
5347 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5348 tcg_temp_free(t1);
5349 if (ra != 0)
5350 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5351 tcg_temp_free(t0);
5352 }
5353
5354 /* stfqux */
5355 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5356 {
5357 int ra = rA(ctx->opcode);
5358 int rd = rD(ctx->opcode);
5359 TCGv t0, t1;
5360 gen_set_access_type(ctx, ACCESS_FLOAT);
5361 t0 = tcg_temp_new();
5362 gen_addr_reg_index(ctx, t0);
5363 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5364 t1 = tcg_temp_new();
5365 gen_addr_add(ctx, t1, t0, 8);
5366 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5367 tcg_temp_free(t1);
5368 if (ra != 0)
5369 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5370 tcg_temp_free(t0);
5371 }
5372
5373 /* stfqx */
5374 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5375 {
5376 int rd = rD(ctx->opcode);
5377 TCGv t0;
5378 gen_set_access_type(ctx, ACCESS_FLOAT);
5379 t0 = tcg_temp_new();
5380 gen_addr_reg_index(ctx, t0);
5381 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5382 gen_addr_add(ctx, t0, t0, 8);
5383 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5384 tcg_temp_free(t0);
5385 }
5386
5387 /* BookE specific instructions */
5388 /* XXX: not implemented on 440 ? */
5389 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
5390 {
5391 /* XXX: TODO */
5392 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5393 }
5394
5395 /* XXX: not implemented on 440 ? */
5396 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
5397 {
5398 #if defined(CONFIG_USER_ONLY)
5399 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5400 #else
5401 TCGv t0;
5402 if (unlikely(!ctx->mem_idx)) {
5403 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5404 return;
5405 }
5406 t0 = tcg_temp_new();
5407 gen_addr_reg_index(ctx, t0);
5408 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
5409 tcg_temp_free(t0);
5410 #endif
5411 }
5412
5413 /* All 405 MAC instructions are translated here */
5414 static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5415 int opc2, int opc3,
5416 int ra, int rb, int rt, int Rc)
5417 {
5418 TCGv t0, t1;
5419
5420 t0 = tcg_temp_local_new();
5421 t1 = tcg_temp_local_new();
5422
5423 switch (opc3 & 0x0D) {
5424 case 0x05:
5425 /* macchw - macchw. - macchwo - macchwo. */
5426 /* macchws - macchws. - macchwso - macchwso. */
5427 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5428 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5429 /* mulchw - mulchw. */
5430 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5431 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5432 tcg_gen_ext16s_tl(t1, t1);
5433 break;
5434 case 0x04:
5435 /* macchwu - macchwu. - macchwuo - macchwuo. */
5436 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5437 /* mulchwu - mulchwu. */
5438 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5439 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5440 tcg_gen_ext16u_tl(t1, t1);
5441 break;
5442 case 0x01:
5443 /* machhw - machhw. - machhwo - machhwo. */
5444 /* machhws - machhws. - machhwso - machhwso. */
5445 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5446 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5447 /* mulhhw - mulhhw. */
5448 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5449 tcg_gen_ext16s_tl(t0, t0);
5450 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5451 tcg_gen_ext16s_tl(t1, t1);
5452 break;
5453 case 0x00:
5454 /* machhwu - machhwu. - machhwuo - machhwuo. */
5455 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5456 /* mulhhwu - mulhhwu. */
5457 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5458 tcg_gen_ext16u_tl(t0, t0);
5459 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5460 tcg_gen_ext16u_tl(t1, t1);
5461 break;
5462 case 0x0D:
5463 /* maclhw - maclhw. - maclhwo - maclhwo. */
5464 /* maclhws - maclhws. - maclhwso - maclhwso. */
5465 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5466 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5467 /* mullhw - mullhw. */
5468 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5469 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5470 break;
5471 case 0x0C:
5472 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5473 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5474 /* mullhwu - mullhwu. */
5475 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5476 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5477 break;
5478 }
5479 if (opc2 & 0x04) {
5480 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5481 tcg_gen_mul_tl(t1, t0, t1);
5482 if (opc2 & 0x02) {
5483 /* nmultiply-and-accumulate (0x0E) */
5484 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5485 } else {
5486 /* multiply-and-accumulate (0x0C) */
5487 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5488 }
5489
5490 if (opc3 & 0x12) {
5491 /* Check overflow and/or saturate */
5492 int l1 = gen_new_label();
5493
5494 if (opc3 & 0x10) {
5495 /* Start with XER OV disabled, the most likely case */
5496 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5497 }
5498 if (opc3 & 0x01) {
5499 /* Signed */
5500 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5501 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5502 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5503 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5504 if (opc3 & 0x02) {
5505 /* Saturate */
5506 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5507 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5508 }
5509 } else {
5510 /* Unsigned */
5511 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5512 if (opc3 & 0x02) {
5513 /* Saturate */
5514 tcg_gen_movi_tl(t0, UINT32_MAX);
5515 }
5516 }
5517 if (opc3 & 0x10) {
5518 /* Check overflow */
5519 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5520 }
5521 gen_set_label(l1);
5522 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5523 }
5524 } else {
5525 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5526 }
5527 tcg_temp_free(t0);
5528 tcg_temp_free(t1);
5529 if (unlikely(Rc) != 0) {
5530 /* Update Rc0 */
5531 gen_set_Rc0(ctx, cpu_gpr[rt]);
5532 }
5533 }
5534
5535 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5536 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
5537 { \
5538 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5539 rD(ctx->opcode), Rc(ctx->opcode)); \
5540 }
5541
5542 /* macchw - macchw. */
5543 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5544 /* macchwo - macchwo. */
5545 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5546 /* macchws - macchws. */
5547 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5548 /* macchwso - macchwso. */
5549 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5550 /* macchwsu - macchwsu. */
5551 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5552 /* macchwsuo - macchwsuo. */
5553 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5554 /* macchwu - macchwu. */
5555 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5556 /* macchwuo - macchwuo. */
5557 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5558 /* machhw - machhw. */
5559 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5560 /* machhwo - machhwo. */
5561 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5562 /* machhws - machhws. */
5563 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5564 /* machhwso - machhwso. */
5565 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5566 /* machhwsu - machhwsu. */
5567 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5568 /* machhwsuo - machhwsuo. */
5569 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5570 /* machhwu - machhwu. */
5571 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5572 /* machhwuo - machhwuo. */
5573 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5574 /* maclhw - maclhw. */
5575 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5576 /* maclhwo - maclhwo. */
5577 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5578 /* maclhws - maclhws. */
5579 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5580 /* maclhwso - maclhwso. */
5581 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5582 /* maclhwu - maclhwu. */
5583 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5584 /* maclhwuo - maclhwuo. */
5585 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5586 /* maclhwsu - maclhwsu. */
5587 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5588 /* maclhwsuo - maclhwsuo. */
5589 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5590 /* nmacchw - nmacchw. */
5591 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5592 /* nmacchwo - nmacchwo. */
5593 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5594 /* nmacchws - nmacchws. */
5595 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5596 /* nmacchwso - nmacchwso. */
5597 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5598 /* nmachhw - nmachhw. */
5599 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5600 /* nmachhwo - nmachhwo. */
5601 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5602 /* nmachhws - nmachhws. */
5603 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5604 /* nmachhwso - nmachhwso. */
5605 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5606 /* nmaclhw - nmaclhw. */
5607 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5608 /* nmaclhwo - nmaclhwo. */
5609 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5610 /* nmaclhws - nmaclhws. */
5611 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5612 /* nmaclhwso - nmaclhwso. */
5613 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5614
5615 /* mulchw - mulchw. */
5616 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5617 /* mulchwu - mulchwu. */
5618 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5619 /* mulhhw - mulhhw. */
5620 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5621 /* mulhhwu - mulhhwu. */
5622 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5623 /* mullhw - mullhw. */
5624 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5625 /* mullhwu - mullhwu. */
5626 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5627
5628 /* mfdcr */
5629 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
5630 {
5631 #if defined(CONFIG_USER_ONLY)
5632 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5633 #else
5634 TCGv dcrn;
5635 if (unlikely(!ctx->mem_idx)) {
5636 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5637 return;
5638 }
5639 /* NIP cannot be restored if the memory exception comes from an helper */
5640 gen_update_nip(ctx, ctx->nip - 4);
5641 dcrn = tcg_const_tl(SPR(ctx->opcode));
5642 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn);
5643 tcg_temp_free(dcrn);
5644 #endif
5645 }
5646
5647 /* mtdcr */
5648 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
5649 {
5650 #if defined(CONFIG_USER_ONLY)
5651 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5652 #else
5653 TCGv dcrn;
5654 if (unlikely(!ctx->mem_idx)) {
5655 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5656 return;
5657 }
5658 /* NIP cannot be restored if the memory exception comes from an helper */
5659 gen_update_nip(ctx, ctx->nip - 4);
5660 dcrn = tcg_const_tl(SPR(ctx->opcode));
5661 gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]);
5662 tcg_temp_free(dcrn);
5663 #endif
5664 }
5665
5666 /* mfdcrx */
5667 /* XXX: not implemented on 440 ? */
5668 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
5669 {
5670 #if defined(CONFIG_USER_ONLY)
5671 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5672 #else
5673 if (unlikely(!ctx->mem_idx)) {
5674 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5675 return;
5676 }
5677 /* NIP cannot be restored if the memory exception comes from an helper */
5678 gen_update_nip(ctx, ctx->nip - 4);
5679 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5680 /* Note: Rc update flag set leads to undefined state of Rc0 */
5681 #endif
5682 }
5683
5684 /* mtdcrx */
5685 /* XXX: not implemented on 440 ? */
5686 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
5687 {
5688 #if defined(CONFIG_USER_ONLY)
5689 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5690 #else
5691 if (unlikely(!ctx->mem_idx)) {
5692 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5693 return;
5694 }
5695 /* NIP cannot be restored if the memory exception comes from an helper */
5696 gen_update_nip(ctx, ctx->nip - 4);
5697 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5698 /* Note: Rc update flag set leads to undefined state of Rc0 */
5699 #endif
5700 }
5701
5702 /* mfdcrux (PPC 460) : user-mode access to DCR */
5703 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5704 {
5705 /* NIP cannot be restored if the memory exception comes from an helper */
5706 gen_update_nip(ctx, ctx->nip - 4);
5707 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5708 /* Note: Rc update flag set leads to undefined state of Rc0 */
5709 }
5710
5711 /* mtdcrux (PPC 460) : user-mode access to DCR */
5712 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5713 {
5714 /* NIP cannot be restored if the memory exception comes from an helper */
5715 gen_update_nip(ctx, ctx->nip - 4);
5716 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5717 /* Note: Rc update flag set leads to undefined state of Rc0 */
5718 }
5719
5720 /* dccci */
5721 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5722 {
5723 #if defined(CONFIG_USER_ONLY)
5724 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5725 #else
5726 if (unlikely(!ctx->mem_idx)) {
5727 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5728 return;
5729 }
5730 /* interpreted as no-op */
5731 #endif
5732 }
5733
5734 /* dcread */
5735 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5736 {
5737 #if defined(CONFIG_USER_ONLY)
5738 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5739 #else
5740 TCGv EA, val;
5741 if (unlikely(!ctx->mem_idx)) {
5742 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5743 return;
5744 }
5745 gen_set_access_type(ctx, ACCESS_CACHE);
5746 EA = tcg_temp_new();
5747 gen_addr_reg_index(ctx, EA);
5748 val = tcg_temp_new();
5749 gen_qemu_ld32u(ctx, val, EA);
5750 tcg_temp_free(val);
5751 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5752 tcg_temp_free(EA);
5753 #endif
5754 }
5755
5756 /* icbt */
5757 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
5758 {
5759 /* interpreted as no-op */
5760 /* XXX: specification say this is treated as a load by the MMU
5761 * but does not generate any exception
5762 */
5763 }
5764
5765 /* iccci */
5766 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5767 {
5768 #if defined(CONFIG_USER_ONLY)
5769 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5770 #else
5771 if (unlikely(!ctx->mem_idx)) {
5772 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5773 return;
5774 }
5775 /* interpreted as no-op */
5776 #endif
5777 }
5778
5779 /* icread */
5780 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5781 {
5782 #if defined(CONFIG_USER_ONLY)
5783 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5784 #else
5785 if (unlikely(!ctx->mem_idx)) {
5786 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5787 return;
5788 }
5789 /* interpreted as no-op */
5790 #endif
5791 }
5792
5793 /* rfci (mem_idx only) */
5794 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
5795 {
5796 #if defined(CONFIG_USER_ONLY)
5797 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5798 #else
5799 if (unlikely(!ctx->mem_idx)) {
5800 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5801 return;
5802 }
5803 /* Restore CPU state */
5804 gen_helper_40x_rfci();
5805 gen_sync_exception(ctx);
5806 #endif
5807 }
5808
5809 GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5810 {
5811 #if defined(CONFIG_USER_ONLY)
5812 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5813 #else
5814 if (unlikely(!ctx->mem_idx)) {
5815 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5816 return;
5817 }
5818 /* Restore CPU state */
5819 gen_helper_rfci();
5820 gen_sync_exception(ctx);
5821 #endif
5822 }
5823
5824 /* BookE specific */
5825 /* XXX: not implemented on 440 ? */
5826 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
5827 {
5828 #if defined(CONFIG_USER_ONLY)
5829 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5830 #else
5831 if (unlikely(!ctx->mem_idx)) {
5832 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5833 return;
5834 }
5835 /* Restore CPU state */
5836 gen_helper_rfdi();
5837 gen_sync_exception(ctx);
5838 #endif
5839 }
5840
5841 /* XXX: not implemented on 440 ? */
5842 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
5843 {
5844 #if defined(CONFIG_USER_ONLY)
5845 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5846 #else
5847 if (unlikely(!ctx->mem_idx)) {
5848 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5849 return;
5850 }
5851 /* Restore CPU state */
5852 gen_helper_rfmci();
5853 gen_sync_exception(ctx);
5854 #endif
5855 }
5856
5857 /* TLB management - PowerPC 405 implementation */
5858 /* tlbre */
5859 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
5860 {
5861 #if defined(CONFIG_USER_ONLY)
5862 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5863 #else
5864 if (unlikely(!ctx->mem_idx)) {
5865 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5866 return;
5867 }
5868 switch (rB(ctx->opcode)) {
5869 case 0:
5870 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5871 break;
5872 case 1:
5873 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5874 break;
5875 default:
5876 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5877 break;
5878 }
5879 #endif
5880 }
5881
5882 /* tlbsx - tlbsx. */
5883 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
5884 {
5885 #if defined(CONFIG_USER_ONLY)
5886 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5887 #else
5888 TCGv t0;
5889 if (unlikely(!ctx->mem_idx)) {
5890 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5891 return;
5892 }
5893 t0 = tcg_temp_new();
5894 gen_addr_reg_index(ctx, t0);
5895 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5896 tcg_temp_free(t0);
5897 if (Rc(ctx->opcode)) {
5898 int l1 = gen_new_label();
5899 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5900 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5901 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5902 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5903 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5904 gen_set_label(l1);
5905 }
5906 #endif
5907 }
5908
5909 /* tlbwe */
5910 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
5911 {
5912 #if defined(CONFIG_USER_ONLY)
5913 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5914 #else
5915 if (unlikely(!ctx->mem_idx)) {
5916 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5917 return;
5918 }
5919 switch (rB(ctx->opcode)) {
5920 case 0:
5921 gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5922 break;
5923 case 1:
5924 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5925 break;
5926 default:
5927 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5928 break;
5929 }
5930 #endif
5931 }
5932
5933 /* TLB management - PowerPC 440 implementation */
5934 /* tlbre */
5935 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5936 {
5937 #if defined(CONFIG_USER_ONLY)
5938 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5939 #else
5940 if (unlikely(!ctx->mem_idx)) {
5941 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5942 return;
5943 }
5944 switch (rB(ctx->opcode)) {
5945 case 0:
5946 case 1:
5947 case 2:
5948 {
5949 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5950 gen_helper_440_tlbwe(t0, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5951 tcg_temp_free_i32(t0);
5952 }
5953 break;
5954 default:
5955 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5956 break;
5957 }
5958 #endif
5959 }
5960
5961 /* tlbsx - tlbsx. */
5962 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5963 {
5964 #if defined(CONFIG_USER_ONLY)
5965 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5966 #else
5967 TCGv t0;
5968 if (unlikely(!ctx->mem_idx)) {
5969 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5970 return;
5971 }
5972 t0 = tcg_temp_new();
5973 gen_addr_reg_index(ctx, t0);
5974 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5975 tcg_temp_free(t0);
5976 if (Rc(ctx->opcode)) {
5977 int l1 = gen_new_label();
5978 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5979 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5980 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5981 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5982 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5983 gen_set_label(l1);
5984 }
5985 #endif
5986 }
5987
5988 /* tlbwe */
5989 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5990 {
5991 #if defined(CONFIG_USER_ONLY)
5992 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5993 #else
5994 if (unlikely(!ctx->mem_idx)) {
5995 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5996 return;
5997 }
5998 switch (rB(ctx->opcode)) {
5999 case 0:
6000 case 1:
6001 case 2:
6002 {
6003 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6004 gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
6005 tcg_temp_free_i32(t0);
6006 }
6007 break;
6008 default:
6009 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6010 break;
6011 }
6012 #endif
6013 }
6014
6015 /* wrtee */
6016 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
6017 {
6018 #if defined(CONFIG_USER_ONLY)
6019 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6020 #else
6021 TCGv t0;
6022 if (unlikely(!ctx->mem_idx)) {
6023 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6024 return;
6025 }
6026 t0 = tcg_temp_new();
6027 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6028 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6029 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6030 tcg_temp_free(t0);
6031 /* Stop translation to have a chance to raise an exception
6032 * if we just set msr_ee to 1
6033 */
6034 gen_stop_exception(ctx);
6035 #endif
6036 }
6037
6038 /* wrteei */
6039 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
6040 {
6041 #if defined(CONFIG_USER_ONLY)
6042 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6043 #else
6044 if (unlikely(!ctx->mem_idx)) {
6045 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6046 return;
6047 }
6048 if (ctx->opcode & 0x00010000) {
6049 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6050 /* Stop translation to have a chance to raise an exception */
6051 gen_stop_exception(ctx);
6052 } else {
6053 tcg_gen_andi_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6054 }
6055 #endif
6056 }
6057
6058 /* PowerPC 440 specific instructions */
6059 /* dlmzb */
6060 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
6061 {
6062 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6063 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
6064 cpu_gpr[rB(ctx->opcode)], t0);
6065 tcg_temp_free_i32(t0);
6066 }
6067
6068 /* mbar replaces eieio on 440 */
6069 GEN_HANDLER(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE)
6070 {
6071 /* interpreted as no-op */
6072 }
6073
6074 /* msync replaces sync on 440 */
6075 GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
6076 {
6077 /* interpreted as no-op */
6078 }
6079
6080 /* icbt */
6081 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
6082 {
6083 /* interpreted as no-op */
6084 /* XXX: specification say this is treated as a load by the MMU
6085 * but does not generate any exception
6086 */
6087 }
6088
6089 /*** Altivec vector extension ***/
6090 /* Altivec registers moves */
6091
6092 static always_inline TCGv_ptr gen_avr_ptr(int reg)
6093 {
6094 TCGv_ptr r = tcg_temp_new_ptr();
6095 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6096 return r;
6097 }
6098
6099 #define GEN_VR_LDX(name, opc2, opc3) \
6100 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6101 { \
6102 TCGv EA; \
6103 if (unlikely(!ctx->altivec_enabled)) { \
6104 gen_exception(ctx, POWERPC_EXCP_VPU); \
6105 return; \
6106 } \
6107 gen_set_access_type(ctx, ACCESS_INT); \
6108 EA = tcg_temp_new(); \
6109 gen_addr_reg_index(ctx, EA); \
6110 tcg_gen_andi_tl(EA, EA, ~0xf); \
6111 if (ctx->le_mode) { \
6112 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6113 tcg_gen_addi_tl(EA, EA, 8); \
6114 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6115 } else { \
6116 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6117 tcg_gen_addi_tl(EA, EA, 8); \
6118 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6119 } \
6120 tcg_temp_free(EA); \
6121 }
6122
6123 #define GEN_VR_STX(name, opc2, opc3) \
6124 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6125 { \
6126 TCGv EA; \
6127 if (unlikely(!ctx->altivec_enabled)) { \
6128 gen_exception(ctx, POWERPC_EXCP_VPU); \
6129 return; \
6130 } \
6131 gen_set_access_type(ctx, ACCESS_INT); \
6132 EA = tcg_temp_new(); \
6133 gen_addr_reg_index(ctx, EA); \
6134 tcg_gen_andi_tl(EA, EA, ~0xf); \
6135 if (ctx->le_mode) { \
6136 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6137 tcg_gen_addi_tl(EA, EA, 8); \
6138 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6139 } else { \
6140 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6141 tcg_gen_addi_tl(EA, EA, 8); \
6142 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6143 } \
6144 tcg_temp_free(EA); \
6145 }
6146
6147 #define GEN_VR_LVE(name, opc2, opc3) \
6148 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6149 { \
6150 TCGv EA; \
6151 TCGv_ptr rs; \
6152 if (unlikely(!ctx->altivec_enabled)) { \
6153 gen_exception(ctx, POWERPC_EXCP_VPU); \
6154 return; \
6155 } \
6156 gen_set_access_type(ctx, ACCESS_INT); \
6157 EA = tcg_temp_new(); \
6158 gen_addr_reg_index(ctx, EA); \
6159 rs = gen_avr_ptr(rS(ctx->opcode)); \
6160 gen_helper_lve##name (rs, EA); \
6161 tcg_temp_free(EA); \
6162 tcg_temp_free_ptr(rs); \
6163 }
6164
6165 #define GEN_VR_STVE(name, opc2, opc3) \
6166 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6167 { \
6168 TCGv EA; \
6169 TCGv_ptr rs; \
6170 if (unlikely(!ctx->altivec_enabled)) { \
6171 gen_exception(ctx, POWERPC_EXCP_VPU); \
6172 return; \
6173 } \
6174 gen_set_access_type(ctx, ACCESS_INT); \
6175 EA = tcg_temp_new(); \
6176 gen_addr_reg_index(ctx, EA); \
6177 rs = gen_avr_ptr(rS(ctx->opcode)); \
6178 gen_helper_stve##name (rs, EA); \
6179 tcg_temp_free(EA); \
6180 tcg_temp_free_ptr(rs); \
6181 }
6182
6183 GEN_VR_LDX(lvx, 0x07, 0x03);
6184 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6185 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6186
6187 GEN_VR_LVE(bx, 0x07, 0x00);
6188 GEN_VR_LVE(hx, 0x07, 0x01);
6189 GEN_VR_LVE(wx, 0x07, 0x02);
6190
6191 GEN_VR_STX(svx, 0x07, 0x07);
6192 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6193 GEN_VR_STX(svxl, 0x07, 0x0F);
6194
6195 GEN_VR_STVE(bx, 0x07, 0x04);
6196 GEN_VR_STVE(hx, 0x07, 0x05);
6197 GEN_VR_STVE(wx, 0x07, 0x06);
6198
6199 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC)
6200 {
6201 TCGv_ptr rd;
6202 TCGv EA;
6203 if (unlikely(!ctx->altivec_enabled)) {
6204 gen_exception(ctx, POWERPC_EXCP_VPU);
6205 return;
6206 }
6207 EA = tcg_temp_new();
6208 gen_addr_reg_index(ctx, EA);
6209 rd = gen_avr_ptr(rD(ctx->opcode));
6210 gen_helper_lvsl(rd, EA);
6211 tcg_temp_free(EA);
6212 tcg_temp_free_ptr(rd);
6213 }
6214
6215 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC)
6216 {
6217 TCGv_ptr rd;
6218 TCGv EA;
6219 if (unlikely(!ctx->altivec_enabled)) {
6220 gen_exception(ctx, POWERPC_EXCP_VPU);
6221 return;
6222 }
6223 EA = tcg_temp_new();
6224 gen_addr_reg_index(ctx, EA);
6225 rd = gen_avr_ptr(rD(ctx->opcode));
6226 gen_helper_lvsr(rd, EA);
6227 tcg_temp_free(EA);
6228 tcg_temp_free_ptr(rd);
6229 }
6230
6231 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC)
6232 {
6233 TCGv_i32 t;
6234 if (unlikely(!ctx->altivec_enabled)) {
6235 gen_exception(ctx, POWERPC_EXCP_VPU);
6236 return;
6237 }
6238 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6239 t = tcg_temp_new_i32();
6240 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr));
6241 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6242 tcg_temp_free(t);
6243 }
6244
6245 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC)
6246 {
6247 TCGv_i32 t;
6248 if (unlikely(!ctx->altivec_enabled)) {
6249 gen_exception(ctx, POWERPC_EXCP_VPU);
6250 return;
6251 }
6252 t = tcg_temp_new_i32();
6253 tcg_gen_trunc_i64_i32(t, cpu_avrl[rD(ctx->opcode)]);
6254 tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, vscr));
6255 tcg_temp_free_i32(t);
6256 }
6257
6258 /* Logical operations */
6259 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6260 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6261 { \
6262 if (unlikely(!ctx->altivec_enabled)) { \
6263 gen_exception(ctx, POWERPC_EXCP_VPU); \
6264 return; \
6265 } \
6266 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6267 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6268 }
6269
6270 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6271 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6272 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6273 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6274 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6275
6276 #define GEN_VXFORM(name, opc2, opc3) \
6277 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6278 { \
6279 TCGv_ptr ra, rb, rd; \
6280 if (unlikely(!ctx->altivec_enabled)) { \
6281 gen_exception(ctx, POWERPC_EXCP_VPU); \
6282 return; \
6283 } \
6284 ra = gen_avr_ptr(rA(ctx->opcode)); \
6285 rb = gen_avr_ptr(rB(ctx->opcode)); \
6286 rd = gen_avr_ptr(rD(ctx->opcode)); \
6287 gen_helper_##name (rd, ra, rb); \
6288 tcg_temp_free_ptr(ra); \
6289 tcg_temp_free_ptr(rb); \
6290 tcg_temp_free_ptr(rd); \
6291 }
6292
6293 GEN_VXFORM(vaddubm, 0, 0);
6294 GEN_VXFORM(vadduhm, 0, 1);
6295 GEN_VXFORM(vadduwm, 0, 2);
6296 GEN_VXFORM(vsububm, 0, 16);
6297 GEN_VXFORM(vsubuhm, 0, 17);
6298 GEN_VXFORM(vsubuwm, 0, 18);
6299 GEN_VXFORM(vmaxub, 1, 0);
6300 GEN_VXFORM(vmaxuh, 1, 1);
6301 GEN_VXFORM(vmaxuw, 1, 2);
6302 GEN_VXFORM(vmaxsb, 1, 4);
6303 GEN_VXFORM(vmaxsh, 1, 5);
6304 GEN_VXFORM(vmaxsw, 1, 6);
6305 GEN_VXFORM(vminub, 1, 8);
6306 GEN_VXFORM(vminuh, 1, 9);
6307 GEN_VXFORM(vminuw, 1, 10);
6308 GEN_VXFORM(vminsb, 1, 12);
6309 GEN_VXFORM(vminsh, 1, 13);
6310 GEN_VXFORM(vminsw, 1, 14);
6311 GEN_VXFORM(vavgub, 1, 16);
6312 GEN_VXFORM(vavguh, 1, 17);
6313 GEN_VXFORM(vavguw, 1, 18);
6314 GEN_VXFORM(vavgsb, 1, 20);
6315 GEN_VXFORM(vavgsh, 1, 21);
6316 GEN_VXFORM(vavgsw, 1, 22);
6317 GEN_VXFORM(vmrghb, 6, 0);
6318 GEN_VXFORM(vmrghh, 6, 1);
6319 GEN_VXFORM(vmrghw, 6, 2);
6320 GEN_VXFORM(vmrglb, 6, 4);
6321 GEN_VXFORM(vmrglh, 6, 5);
6322 GEN_VXFORM(vmrglw, 6, 6);
6323 GEN_VXFORM(vmuloub, 4, 0);
6324 GEN_VXFORM(vmulouh, 4, 1);
6325 GEN_VXFORM(vmulosb, 4, 4);
6326 GEN_VXFORM(vmulosh, 4, 5);
6327 GEN_VXFORM(vmuleub, 4, 8);
6328 GEN_VXFORM(vmuleuh, 4, 9);
6329 GEN_VXFORM(vmulesb, 4, 12);
6330 GEN_VXFORM(vmulesh, 4, 13);
6331 GEN_VXFORM(vslb, 2, 4);
6332 GEN_VXFORM(vslh, 2, 5);
6333 GEN_VXFORM(vslw, 2, 6);
6334 GEN_VXFORM(vsrb, 2, 8);
6335 GEN_VXFORM(vsrh, 2, 9);
6336 GEN_VXFORM(vsrw, 2, 10);
6337 GEN_VXFORM(vsrab, 2, 12);
6338 GEN_VXFORM(vsrah, 2, 13);
6339 GEN_VXFORM(vsraw, 2, 14);
6340 GEN_VXFORM(vslo, 6, 16);
6341 GEN_VXFORM(vsro, 6, 17);
6342 GEN_VXFORM(vaddcuw, 0, 6);
6343 GEN_VXFORM(vsubcuw, 0, 22);
6344 GEN_VXFORM(vrlb, 2, 0);
6345 GEN_VXFORM(vrlh, 2, 1);
6346 GEN_VXFORM(vrlw, 2, 2);
6347 GEN_VXFORM(vsl, 2, 7);
6348 GEN_VXFORM(vsr, 2, 11);
6349 GEN_VXFORM(vpkuhum, 7, 0);
6350 GEN_VXFORM(vpkuwum, 7, 1);
6351 GEN_VXFORM(vpkuhus, 7, 2);
6352 GEN_VXFORM(vpkuwus, 7, 3);
6353 GEN_VXFORM(vpkshus, 7, 4);
6354 GEN_VXFORM(vpkswus, 7, 5);
6355 GEN_VXFORM(vpkshss, 7, 6);
6356 GEN_VXFORM(vpkswss, 7, 7);
6357 GEN_VXFORM(vpkpx, 7, 12);
6358 GEN_VXFORM(vsum4ubs, 4, 24);
6359 GEN_VXFORM(vsum4sbs, 4, 28);
6360 GEN_VXFORM(vsum4shs, 4, 25);
6361 GEN_VXFORM(vsum2sws, 4, 26);
6362 GEN_VXFORM(vsumsws, 4, 30);
6363
6364 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6365 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6366 { \
6367 TCGv_ptr ra, rb, rd; \
6368 if (unlikely(!ctx->altivec_enabled)) { \
6369 gen_exception(ctx, POWERPC_EXCP_VPU); \
6370 return; \
6371 } \
6372 ra = gen_avr_ptr(rA(ctx->opcode)); \
6373 rb = gen_avr_ptr(rB(ctx->opcode)); \
6374 rd = gen_avr_ptr(rD(ctx->opcode)); \
6375 gen_helper_##opname (rd, ra, rb); \
6376 tcg_temp_free_ptr(ra); \
6377 tcg_temp_free_ptr(rb); \
6378 tcg_temp_free_ptr(rd); \
6379 }
6380
6381 #define GEN_VXRFORM(name, opc2, opc3) \
6382 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6383 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6384
6385 GEN_VXRFORM(vcmpequb, 3, 0)
6386 GEN_VXRFORM(vcmpequh, 3, 1)
6387 GEN_VXRFORM(vcmpequw, 3, 2)
6388 GEN_VXRFORM(vcmpgtsb, 3, 12)
6389 GEN_VXRFORM(vcmpgtsh, 3, 13)
6390 GEN_VXRFORM(vcmpgtsw, 3, 14)
6391 GEN_VXRFORM(vcmpgtub, 3, 8)
6392 GEN_VXRFORM(vcmpgtuh, 3, 9)
6393 GEN_VXRFORM(vcmpgtuw, 3, 10)
6394
6395 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6396 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) \
6397 { \
6398 TCGv_ptr rb, rd; \
6399 if (unlikely(!ctx->altivec_enabled)) { \
6400 gen_exception(ctx, POWERPC_EXCP_VPU); \
6401 return; \
6402 } \
6403 rb = gen_avr_ptr(rB(ctx->opcode)); \
6404 rd = gen_avr_ptr(rD(ctx->opcode)); \
6405 gen_helper_##name (rd, rb); \
6406 tcg_temp_free_ptr(rb); \
6407 tcg_temp_free_ptr(rd); \
6408 }
6409
6410 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6411 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6412 GEN_VXFORM_NOA(vupklsb, 7, 10);
6413 GEN_VXFORM_NOA(vupklsh, 7, 11);
6414 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6415 GEN_VXFORM_NOA(vupklpx, 7, 15);
6416
6417 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6418 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6419 { \
6420 TCGv_ptr rd; \
6421 TCGv_i32 simm; \
6422 if (unlikely(!ctx->altivec_enabled)) { \
6423 gen_exception(ctx, POWERPC_EXCP_VPU); \
6424 return; \
6425 } \
6426 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6427 rd = gen_avr_ptr(rD(ctx->opcode)); \
6428 gen_helper_##name (rd, simm); \
6429 tcg_temp_free_i32(simm); \
6430 tcg_temp_free_ptr(rd); \
6431 }
6432
6433 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6434 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6435 { \
6436 TCGv_ptr rb, rd; \
6437 TCGv_i32 uimm; \
6438 if (unlikely(!ctx->altivec_enabled)) { \
6439 gen_exception(ctx, POWERPC_EXCP_VPU); \
6440 return; \
6441 } \
6442 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6443 rb = gen_avr_ptr(rB(ctx->opcode)); \
6444 rd = gen_avr_ptr(rD(ctx->opcode)); \
6445 gen_helper_##name (rd, rb, uimm); \
6446 tcg_temp_free_i32(uimm); \
6447 tcg_temp_free_ptr(rb); \
6448 tcg_temp_free_ptr(rd); \
6449 }
6450
6451 GEN_VXFORM_UIMM(vspltb, 6, 8);
6452 GEN_VXFORM_UIMM(vsplth, 6, 9);
6453 GEN_VXFORM_UIMM(vspltw, 6, 10);
6454
6455 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
6456 {
6457 TCGv_ptr ra, rb, rd;
6458 TCGv sh;
6459 if (unlikely(!ctx->altivec_enabled)) {
6460 gen_exception(ctx, POWERPC_EXCP_VPU);
6461 return;
6462 }
6463 ra = gen_avr_ptr(rA(ctx->opcode));
6464 rb = gen_avr_ptr(rB(ctx->opcode));
6465 rd = gen_avr_ptr(rD(ctx->opcode));
6466 sh = tcg_const_i32(VSH(ctx->opcode));
6467 gen_helper_vsldoi (rd, ra, rb, sh);
6468 tcg_temp_free_ptr(ra);
6469 tcg_temp_free_ptr(rb);
6470 tcg_temp_free_ptr(rd);
6471 tcg_temp_free(sh);
6472 }
6473
6474 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6475 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) \
6476 { \
6477 TCGv_ptr ra, rb, rc, rd; \
6478 if (unlikely(!ctx->altivec_enabled)) { \
6479 gen_exception(ctx, POWERPC_EXCP_VPU); \
6480 return; \
6481 } \
6482 ra = gen_avr_ptr(rA(ctx->opcode)); \
6483 rb = gen_avr_ptr(rB(ctx->opcode)); \
6484 rc = gen_avr_ptr(rC(ctx->opcode)); \
6485 rd = gen_avr_ptr(rD(ctx->opcode)); \
6486 if (Rc(ctx->opcode)) { \
6487 gen_helper_##name1 (rd, ra, rb, rc); \
6488 } else { \
6489 gen_helper_##name0 (rd, ra, rb, rc); \
6490 } \
6491 tcg_temp_free_ptr(ra); \
6492 tcg_temp_free_ptr(rb); \
6493 tcg_temp_free_ptr(rc); \
6494 tcg_temp_free_ptr(rd); \
6495 }
6496
6497 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6498
6499 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC)
6500 {
6501 TCGv_ptr ra, rb, rc, rd;
6502 if (unlikely(!ctx->altivec_enabled)) {
6503 gen_exception(ctx, POWERPC_EXCP_VPU);
6504 return;
6505 }
6506 ra = gen_avr_ptr(rA(ctx->opcode));
6507 rb = gen_avr_ptr(rB(ctx->opcode));
6508 rc = gen_avr_ptr(rC(ctx->opcode));
6509 rd = gen_avr_ptr(rD(ctx->opcode));
6510 gen_helper_vmladduhm(rd, ra, rb, rc);
6511 tcg_temp_free_ptr(ra);
6512 tcg_temp_free_ptr(rb);
6513 tcg_temp_free_ptr(rc);
6514 tcg_temp_free_ptr(rd);
6515 }
6516
6517 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6518 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6519 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6520 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6521
6522 /*** SPE extension ***/
6523 /* Register moves */
6524
6525 static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
6526 #if defined(TARGET_PPC64)
6527 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6528 #else
6529 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6530 #endif
6531 }
6532
6533 static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
6534 #if defined(TARGET_PPC64)
6535 tcg_gen_mov_i64(cpu_gpr[reg], t);
6536 #else
6537 TCGv_i64 tmp = tcg_temp_new_i64();
6538 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6539 tcg_gen_shri_i64(tmp, t, 32);
6540 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6541 tcg_temp_free_i64(tmp);
6542 #endif
6543 }
6544
6545 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
6546 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
6547 { \
6548 if (Rc(ctx->opcode)) \
6549 gen_##name1(ctx); \
6550 else \
6551 gen_##name0(ctx); \
6552 }
6553
6554 /* Handler for undefined SPE opcodes */
6555 static always_inline void gen_speundef (DisasContext *ctx)
6556 {
6557 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6558 }
6559
6560 /* SPE logic */
6561 #if defined(TARGET_PPC64)
6562 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6563 static always_inline void gen_##name (DisasContext *ctx) \
6564 { \
6565 if (unlikely(!ctx->spe_enabled)) { \
6566 gen_exception(ctx, POWERPC_EXCP_APU); \
6567 return; \
6568 } \
6569 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6570 cpu_gpr[rB(ctx->opcode)]); \
6571 }
6572 #else
6573 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6574 static always_inline void gen_##name (DisasContext *ctx) \
6575 { \
6576 if (unlikely(!ctx->spe_enabled)) { \
6577 gen_exception(ctx, POWERPC_EXCP_APU); \
6578 return; \
6579 } \
6580 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6581 cpu_gpr[rB(ctx->opcode)]); \
6582 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6583 cpu_gprh[rB(ctx->opcode)]); \
6584 }
6585 #endif
6586
6587 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6588 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6589 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6590 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6591 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6592 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6593 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6594 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6595
6596 /* SPE logic immediate */
6597 #if defined(TARGET_PPC64)
6598 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6599 static always_inline void gen_##name (DisasContext *ctx) \
6600 { \
6601 if (unlikely(!ctx->spe_enabled)) { \
6602 gen_exception(ctx, POWERPC_EXCP_APU); \
6603 return; \
6604 } \
6605 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6606 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6607 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6608 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6609 tcg_opi(t0, t0, rB(ctx->opcode)); \
6610 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6611 tcg_gen_trunc_i64_i32(t1, t2); \
6612 tcg_temp_free_i64(t2); \
6613 tcg_opi(t1, t1, rB(ctx->opcode)); \
6614 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6615 tcg_temp_free_i32(t0); \
6616 tcg_temp_free_i32(t1); \
6617 }
6618 #else
6619 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6620 static always_inline void gen_##name (DisasContext *ctx) \
6621 { \
6622 if (unlikely(!ctx->spe_enabled)) { \
6623 gen_exception(ctx, POWERPC_EXCP_APU); \
6624 return; \
6625 } \
6626 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6627 rB(ctx->opcode)); \
6628 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6629 rB(ctx->opcode)); \
6630 }
6631 #endif
6632 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6633 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6634 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6635 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6636
6637 /* SPE arithmetic */
6638 #if defined(TARGET_PPC64)
6639 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6640 static always_inline void gen_##name (DisasContext *ctx) \
6641 { \
6642 if (unlikely(!ctx->spe_enabled)) { \
6643 gen_exception(ctx, POWERPC_EXCP_APU); \
6644 return; \
6645 } \
6646 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6647 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6648 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6649 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6650 tcg_op(t0, t0); \
6651 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6652 tcg_gen_trunc_i64_i32(t1, t2); \
6653 tcg_temp_free_i64(t2); \
6654 tcg_op(t1, t1); \
6655 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6656 tcg_temp_free_i32(t0); \
6657 tcg_temp_free_i32(t1); \
6658 }
6659 #else
6660 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6661 static always_inline void gen_##name (DisasContext *ctx) \
6662 { \
6663 if (unlikely(!ctx->spe_enabled)) { \
6664 gen_exception(ctx, POWERPC_EXCP_APU); \
6665 return; \
6666 } \
6667 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6668 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6669 }
6670 #endif
6671
6672 static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
6673 {
6674 int l1 = gen_new_label();
6675 int l2 = gen_new_label();
6676
6677 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6678 tcg_gen_neg_i32(ret, arg1);
6679 tcg_gen_br(l2);
6680 gen_set_label(l1);
6681 tcg_gen_mov_i32(ret, arg1);
6682 gen_set_label(l2);
6683 }
6684 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6685 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6686 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6687 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
6688 static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
6689 {
6690 tcg_gen_addi_i32(ret, arg1, 0x8000);
6691 tcg_gen_ext16u_i32(ret, ret);
6692 }
6693 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
6694 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6695 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
6696
6697 #if defined(TARGET_PPC64)
6698 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6699 static always_inline void gen_##name (DisasContext *ctx) \
6700 { \
6701 if (unlikely(!ctx->spe_enabled)) { \
6702 gen_exception(ctx, POWERPC_EXCP_APU); \
6703 return; \
6704 } \
6705 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6706 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6707 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6708 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
6709 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6710 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6711 tcg_op(t0, t0, t2); \
6712 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6713 tcg_gen_trunc_i64_i32(t1, t3); \
6714 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6715 tcg_gen_trunc_i64_i32(t2, t3); \
6716 tcg_temp_free_i64(t3); \
6717 tcg_op(t1, t1, t2); \
6718 tcg_temp_free_i32(t2); \
6719 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6720 tcg_temp_free_i32(t0); \
6721 tcg_temp_free_i32(t1); \
6722 }
6723 #else
6724 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6725 static always_inline void gen_##name (DisasContext *ctx) \
6726 { \
6727 if (unlikely(!ctx->spe_enabled)) { \
6728 gen_exception(ctx, POWERPC_EXCP_APU); \
6729 return; \
6730 } \
6731 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6732 cpu_gpr[rB(ctx->opcode)]); \
6733 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6734 cpu_gprh[rB(ctx->opcode)]); \
6735 }
6736 #endif
6737
6738 static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6739 {
6740 TCGv_i32 t0;
6741 int l1, l2;
6742
6743 l1 = gen_new_label();
6744 l2 = gen_new_label();
6745 t0 = tcg_temp_local_new_i32();
6746 /* No error here: 6 bits are used */
6747 tcg_gen_andi_i32(t0, arg2, 0x3F);
6748 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6749 tcg_gen_shr_i32(ret, arg1, t0);
6750 tcg_gen_br(l2);
6751 gen_set_label(l1);
6752 tcg_gen_movi_i32(ret, 0);
6753 tcg_gen_br(l2);
6754 tcg_temp_free_i32(t0);
6755 }
6756 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
6757 static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6758 {
6759 TCGv_i32 t0;
6760 int l1, l2;
6761
6762 l1 = gen_new_label();
6763 l2 = gen_new_label();
6764 t0 = tcg_temp_local_new_i32();
6765 /* No error here: 6 bits are used */
6766 tcg_gen_andi_i32(t0, arg2, 0x3F);
6767 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6768 tcg_gen_sar_i32(ret, arg1, t0);
6769 tcg_gen_br(l2);
6770 gen_set_label(l1);
6771 tcg_gen_movi_i32(ret, 0);
6772 tcg_gen_br(l2);
6773 tcg_temp_free_i32(t0);
6774 }
6775 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
6776 static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6777 {
6778 TCGv_i32 t0;
6779 int l1, l2;
6780
6781 l1 = gen_new_label();
6782 l2 = gen_new_label();
6783 t0 = tcg_temp_local_new_i32();
6784 /* No error here: 6 bits are used */
6785 tcg_gen_andi_i32(t0, arg2, 0x3F);
6786 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6787 tcg_gen_shl_i32(ret, arg1, t0);
6788 tcg_gen_br(l2);
6789 gen_set_label(l1);
6790 tcg_gen_movi_i32(ret, 0);
6791 tcg_gen_br(l2);
6792 tcg_temp_free_i32(t0);
6793 }
6794 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
6795 static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6796 {
6797 TCGv_i32 t0 = tcg_temp_new_i32();
6798 tcg_gen_andi_i32(t0, arg2, 0x1F);
6799 tcg_gen_rotl_i32(ret, arg1, t0);
6800 tcg_temp_free_i32(t0);
6801 }
6802 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6803 static always_inline void gen_evmergehi (DisasContext *ctx)
6804 {
6805 if (unlikely(!ctx->spe_enabled)) {
6806 gen_exception(ctx, POWERPC_EXCP_APU);
6807 return;
6808 }
6809 #if defined(TARGET_PPC64)
6810 TCGv t0 = tcg_temp_new();
6811 TCGv t1 = tcg_temp_new();
6812 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6813 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6814 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6815 tcg_temp_free(t0);
6816 tcg_temp_free(t1);
6817 #else
6818 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6819 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6820 #endif
6821 }
6822 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
6823 static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6824 {
6825 tcg_gen_sub_i32(ret, arg2, arg1);
6826 }
6827 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
6828
6829 /* SPE arithmetic immediate */
6830 #if defined(TARGET_PPC64)
6831 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6832 static always_inline void gen_##name (DisasContext *ctx) \
6833 { \
6834 if (unlikely(!ctx->spe_enabled)) { \
6835 gen_exception(ctx, POWERPC_EXCP_APU); \
6836 return; \
6837 } \
6838 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6839 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6840 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6841 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6842 tcg_op(t0, t0, rA(ctx->opcode)); \
6843 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6844 tcg_gen_trunc_i64_i32(t1, t2); \
6845 tcg_temp_free_i64(t2); \
6846 tcg_op(t1, t1, rA(ctx->opcode)); \
6847 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6848 tcg_temp_free_i32(t0); \
6849 tcg_temp_free_i32(t1); \
6850 }
6851 #else
6852 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6853 static always_inline void gen_##name (DisasContext *ctx) \
6854 { \
6855 if (unlikely(!ctx->spe_enabled)) { \
6856 gen_exception(ctx, POWERPC_EXCP_APU); \
6857 return; \
6858 } \
6859 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6860 rA(ctx->opcode)); \
6861 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6862 rA(ctx->opcode)); \
6863 }
6864 #endif
6865 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
6866 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
6867
6868 /* SPE comparison */
6869 #if defined(TARGET_PPC64)
6870 #define GEN_SPEOP_COMP(name, tcg_cond) \
6871 static always_inline void gen_##name (DisasContext *ctx) \
6872 { \
6873 if (unlikely(!ctx->spe_enabled)) { \
6874 gen_exception(ctx, POWERPC_EXCP_APU); \
6875 return; \
6876 } \
6877 int l1 = gen_new_label(); \
6878 int l2 = gen_new_label(); \
6879 int l3 = gen_new_label(); \
6880 int l4 = gen_new_label(); \
6881 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6882 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6883 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6884 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6885 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6886 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
6887 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
6888 tcg_gen_br(l2); \
6889 gen_set_label(l1); \
6890 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6891 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6892 gen_set_label(l2); \
6893 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6894 tcg_gen_trunc_i64_i32(t0, t2); \
6895 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6896 tcg_gen_trunc_i64_i32(t1, t2); \
6897 tcg_temp_free_i64(t2); \
6898 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
6899 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6900 ~(CRF_CH | CRF_CH_AND_CL)); \
6901 tcg_gen_br(l4); \
6902 gen_set_label(l3); \
6903 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6904 CRF_CH | CRF_CH_OR_CL); \
6905 gen_set_label(l4); \
6906 tcg_temp_free_i32(t0); \
6907 tcg_temp_free_i32(t1); \
6908 }
6909 #else
6910 #define GEN_SPEOP_COMP(name, tcg_cond) \
6911 static always_inline void gen_##name (DisasContext *ctx) \
6912 { \
6913 if (unlikely(!ctx->spe_enabled)) { \
6914 gen_exception(ctx, POWERPC_EXCP_APU); \
6915 return; \
6916 } \
6917 int l1 = gen_new_label(); \
6918 int l2 = gen_new_label(); \
6919 int l3 = gen_new_label(); \
6920 int l4 = gen_new_label(); \
6921 \
6922 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
6923 cpu_gpr[rB(ctx->opcode)], l1); \
6924 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
6925 tcg_gen_br(l2); \
6926 gen_set_label(l1); \
6927 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6928 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6929 gen_set_label(l2); \
6930 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
6931 cpu_gprh[rB(ctx->opcode)], l3); \
6932 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6933 ~(CRF_CH | CRF_CH_AND_CL)); \
6934 tcg_gen_br(l4); \
6935 gen_set_label(l3); \
6936 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6937 CRF_CH | CRF_CH_OR_CL); \
6938 gen_set_label(l4); \
6939 }
6940 #endif
6941 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
6942 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
6943 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
6944 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
6945 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
6946
6947 /* SPE misc */
6948 static always_inline void gen_brinc (DisasContext *ctx)
6949 {
6950 /* Note: brinc is usable even if SPE is disabled */
6951 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
6952 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6953 }
6954 static always_inline void gen_evmergelo (DisasContext *ctx)
6955 {
6956 if (unlikely(!ctx->spe_enabled)) {
6957 gen_exception(ctx, POWERPC_EXCP_APU);
6958 return;
6959 }
6960 #if defined(TARGET_PPC64)
6961 TCGv t0 = tcg_temp_new();
6962 TCGv t1 = tcg_temp_new();
6963 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6964 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6965 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6966 tcg_temp_free(t0);
6967 tcg_temp_free(t1);
6968 #else
6969 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6970 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6971 #endif
6972 }
6973 static always_inline void gen_evmergehilo (DisasContext *ctx)
6974 {
6975 if (unlikely(!ctx->spe_enabled)) {
6976 gen_exception(ctx, POWERPC_EXCP_APU);
6977 return;
6978 }
6979 #if defined(TARGET_PPC64)
6980 TCGv t0 = tcg_temp_new();
6981 TCGv t1 = tcg_temp_new();
6982 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6983 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6984 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6985 tcg_temp_free(t0);
6986 tcg_temp_free(t1);
6987 #else
6988 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6989 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6990 #endif
6991 }
6992 static always_inline void gen_evmergelohi (DisasContext *ctx)
6993 {
6994 if (unlikely(!ctx->spe_enabled)) {
6995 gen_exception(ctx, POWERPC_EXCP_APU);
6996 return;
6997 }
6998 #if defined(TARGET_PPC64)
6999 TCGv t0 = tcg_temp_new();
7000 TCGv t1 = tcg_temp_new();
7001 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7002 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7003 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7004 tcg_temp_free(t0);
7005 tcg_temp_free(t1);
7006 #else
7007 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7008 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7009 #endif
7010 }
7011 static always_inline void gen_evsplati (DisasContext *ctx)
7012 {
7013 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
7014
7015 #if defined(TARGET_PPC64)
7016 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7017 #else
7018 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7019 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7020 #endif
7021 }
7022 static always_inline void gen_evsplatfi (DisasContext *ctx)
7023 {
7024 uint64_t imm = rA(ctx->opcode) << 11;
7025
7026 #if defined(TARGET_PPC64)
7027 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7028 #else
7029 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7030 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7031 #endif
7032 }
7033
7034 static always_inline void gen_evsel (DisasContext *ctx)
7035 {
7036 int l1 = gen_new_label();
7037 int l2 = gen_new_label();
7038 int l3 = gen_new_label();
7039 int l4 = gen_new_label();
7040 TCGv_i32 t0 = tcg_temp_local_new_i32();
7041 #if defined(TARGET_PPC64)
7042 TCGv t1 = tcg_temp_local_new();
7043 TCGv t2 = tcg_temp_local_new();
7044 #endif
7045 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7046 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7047 #if defined(TARGET_PPC64)
7048 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7049 #else
7050 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7051 #endif
7052 tcg_gen_br(l2);
7053 gen_set_label(l1);
7054 #if defined(TARGET_PPC64)
7055 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7056 #else
7057 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7058 #endif
7059 gen_set_label(l2);
7060 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7061 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7062 #if defined(TARGET_PPC64)
7063 tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
7064 #else
7065 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7066 #endif
7067 tcg_gen_br(l4);
7068 gen_set_label(l3);
7069 #if defined(TARGET_PPC64)
7070 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
7071 #else
7072 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7073 #endif
7074 gen_set_label(l4);
7075 tcg_temp_free_i32(t0);
7076 #if defined(TARGET_PPC64)
7077 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7078 tcg_temp_free(t1);
7079 tcg_temp_free(t2);
7080 #endif
7081 }
7082 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
7083 {
7084 gen_evsel(ctx);
7085 }
7086 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
7087 {
7088 gen_evsel(ctx);
7089 }
7090 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
7091 {
7092 gen_evsel(ctx);
7093 }
7094 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
7095 {
7096 gen_evsel(ctx);
7097 }
7098
7099 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
7100 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
7101 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
7102 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
7103 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
7104 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
7105 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
7106 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
7107 GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
7108 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
7109 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
7110 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
7111 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
7112 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
7113 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
7114 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
7115 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
7116 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
7117 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
7118 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
7119 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
7120 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
7121 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
7122 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
7123 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
7124
7125 /* SPE load and stores */
7126 static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, TCGv EA, int sh)
7127 {
7128 target_ulong uimm = rB(ctx->opcode);
7129
7130 if (rA(ctx->opcode) == 0) {
7131 tcg_gen_movi_tl(EA, uimm << sh);
7132 } else {
7133 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7134 #if defined(TARGET_PPC64)
7135 if (!ctx->sf_mode) {
7136 tcg_gen_ext32u_tl(EA, EA);
7137 }
7138 #endif
7139 }
7140 }
7141
7142 static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7143 {
7144 #if defined(TARGET_PPC64)
7145 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7146 #else
7147 TCGv_i64 t0 = tcg_temp_new_i64();
7148 gen_qemu_ld64(ctx, t0, addr);
7149 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7150 tcg_gen_shri_i64(t0, t0, 32);
7151 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7152 tcg_temp_free_i64(t0);
7153 #endif
7154 }
7155
7156 static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7157 {
7158 #if defined(TARGET_PPC64)
7159 TCGv t0 = tcg_temp_new();
7160 gen_qemu_ld32u(ctx, t0, addr);
7161 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7162 gen_addr_add(ctx, addr, addr, 4);
7163 gen_qemu_ld32u(ctx, t0, addr);
7164 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7165 tcg_temp_free(t0);
7166 #else
7167 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7168 gen_addr_add(ctx, addr, addr, 4);
7169 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7170 #endif
7171 }
7172
7173 static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7174 {
7175 TCGv t0 = tcg_temp_new();
7176 #if defined(TARGET_PPC64)
7177 gen_qemu_ld16u(ctx, t0, addr);
7178 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7179 gen_addr_add(ctx, addr, addr, 2);
7180 gen_qemu_ld16u(ctx, t0, addr);
7181 tcg_gen_shli_tl(t0, t0, 32);
7182 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7183 gen_addr_add(ctx, addr, addr, 2);
7184 gen_qemu_ld16u(ctx, t0, addr);
7185 tcg_gen_shli_tl(t0, t0, 16);
7186 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7187 gen_addr_add(ctx, addr, addr, 2);
7188 gen_qemu_ld16u(ctx, t0, addr);
7189 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7190 #else
7191 gen_qemu_ld16u(ctx, t0, addr);
7192 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7193 gen_addr_add(ctx, addr, addr, 2);
7194 gen_qemu_ld16u(ctx, t0, addr);
7195 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7196 gen_addr_add(ctx, addr, addr, 2);
7197 gen_qemu_ld16u(ctx, t0, addr);
7198 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7199 gen_addr_add(ctx, addr, addr, 2);
7200 gen_qemu_ld16u(ctx, t0, addr);
7201 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7202 #endif
7203 tcg_temp_free(t0);
7204 }
7205
7206 static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7207 {
7208 TCGv t0 = tcg_temp_new();
7209 gen_qemu_ld16u(ctx, t0, addr);
7210 #if defined(TARGET_PPC64)
7211 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7212 tcg_gen_shli_tl(t0, t0, 16);
7213 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7214 #else
7215 tcg_gen_shli_tl(t0, t0, 16);
7216 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7217 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7218 #endif
7219 tcg_temp_free(t0);
7220 }
7221
7222 static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7223 {
7224 TCGv t0 = tcg_temp_new();
7225 gen_qemu_ld16u(ctx, t0, addr);
7226 #if defined(TARGET_PPC64)
7227 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7228 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7229 #else
7230 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7231 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7232 #endif
7233 tcg_temp_free(t0);
7234 }
7235
7236 static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7237 {
7238 TCGv t0 = tcg_temp_new();
7239 gen_qemu_ld16s(ctx, t0, addr);
7240 #if defined(TARGET_PPC64)
7241 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7242 tcg_gen_ext32u_tl(t0, t0);
7243 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7244 #else
7245 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7246 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7247 #endif
7248 tcg_temp_free(t0);
7249 }
7250
7251 static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7252 {
7253 TCGv t0 = tcg_temp_new();
7254 #if defined(TARGET_PPC64)
7255 gen_qemu_ld16u(ctx, t0, addr);
7256 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7257 gen_addr_add(ctx, addr, addr, 2);
7258 gen_qemu_ld16u(ctx, t0, addr);
7259 tcg_gen_shli_tl(t0, t0, 16);
7260 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7261 #else
7262 gen_qemu_ld16u(ctx, t0, addr);
7263 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7264 gen_addr_add(ctx, addr, addr, 2);
7265 gen_qemu_ld16u(ctx, t0, addr);
7266 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7267 #endif
7268 tcg_temp_free(t0);
7269 }
7270
7271 static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7272 {
7273 #if defined(TARGET_PPC64)
7274 TCGv t0 = tcg_temp_new();
7275 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7276 gen_addr_add(ctx, addr, addr, 2);
7277 gen_qemu_ld16u(ctx, t0, addr);
7278 tcg_gen_shli_tl(t0, t0, 32);
7279 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7280 tcg_temp_free(t0);
7281 #else
7282 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7283 gen_addr_add(ctx, addr, addr, 2);
7284 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7285 #endif
7286 }
7287
7288 static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7289 {
7290 #if defined(TARGET_PPC64)
7291 TCGv t0 = tcg_temp_new();
7292 gen_qemu_ld16s(ctx, t0, addr);
7293 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7294 gen_addr_add(ctx, addr, addr, 2);
7295 gen_qemu_ld16s(ctx, t0, addr);
7296 tcg_gen_shli_tl(t0, t0, 32);
7297 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7298 tcg_temp_free(t0);
7299 #else
7300 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7301 gen_addr_add(ctx, addr, addr, 2);
7302 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7303 #endif
7304 }
7305
7306 static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7307 {
7308 TCGv t0 = tcg_temp_new();
7309 gen_qemu_ld32u(ctx, t0, addr);
7310 #if defined(TARGET_PPC64)
7311 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7312 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7313 #else
7314 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7315 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7316 #endif
7317 tcg_temp_free(t0);
7318 }
7319
7320 static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7321 {
7322 TCGv t0 = tcg_temp_new();
7323 #if defined(TARGET_PPC64)
7324 gen_qemu_ld16u(ctx, t0, addr);
7325 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7326 tcg_gen_shli_tl(t0, t0, 32);
7327 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7328 gen_addr_add(ctx, addr, addr, 2);
7329 gen_qemu_ld16u(ctx, t0, addr);
7330 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7331 tcg_gen_shli_tl(t0, t0, 16);
7332 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7333 #else
7334 gen_qemu_ld16u(ctx, t0, addr);
7335 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7336 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7337 gen_addr_add(ctx, addr, addr, 2);
7338 gen_qemu_ld16u(ctx, t0, addr);
7339 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7340 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7341 #endif
7342 tcg_temp_free(t0);
7343 }
7344
7345 static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7346 {
7347 #if defined(TARGET_PPC64)
7348 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7349 #else
7350 TCGv_i64 t0 = tcg_temp_new_i64();
7351 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7352 gen_qemu_st64(ctx, t0, addr);
7353 tcg_temp_free_i64(t0);
7354 #endif
7355 }
7356
7357 static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7358 {
7359 #if defined(TARGET_PPC64)
7360 TCGv t0 = tcg_temp_new();
7361 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7362 gen_qemu_st32(ctx, t0, addr);
7363 tcg_temp_free(t0);
7364 #else
7365 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7366 #endif
7367 gen_addr_add(ctx, addr, addr, 4);
7368 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7369 }
7370
7371 static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7372 {
7373 TCGv t0 = tcg_temp_new();
7374 #if defined(TARGET_PPC64)
7375 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7376 #else
7377 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7378 #endif
7379 gen_qemu_st16(ctx, t0, addr);
7380 gen_addr_add(ctx, addr, addr, 2);
7381 #if defined(TARGET_PPC64)
7382 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7383 gen_qemu_st16(ctx, t0, addr);
7384 #else
7385 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7386 #endif
7387 gen_addr_add(ctx, addr, addr, 2);
7388 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7389 gen_qemu_st16(ctx, t0, addr);
7390 tcg_temp_free(t0);
7391 gen_addr_add(ctx, addr, addr, 2);
7392 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7393 }
7394
7395 static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7396 {
7397 TCGv t0 = tcg_temp_new();
7398 #if defined(TARGET_PPC64)
7399 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7400 #else
7401 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7402 #endif
7403 gen_qemu_st16(ctx, t0, addr);
7404 gen_addr_add(ctx, addr, addr, 2);
7405 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7406 gen_qemu_st16(ctx, t0, addr);
7407 tcg_temp_free(t0);
7408 }
7409
7410 static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7411 {
7412 #if defined(TARGET_PPC64)
7413 TCGv t0 = tcg_temp_new();
7414 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7415 gen_qemu_st16(ctx, t0, addr);
7416 tcg_temp_free(t0);
7417 #else
7418 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7419 #endif
7420 gen_addr_add(ctx, addr, addr, 2);
7421 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7422 }
7423
7424 static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7425 {
7426 #if defined(TARGET_PPC64)
7427 TCGv t0 = tcg_temp_new();
7428 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7429 gen_qemu_st32(ctx, t0, addr);
7430 tcg_temp_free(t0);
7431 #else
7432 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7433 #endif
7434 }
7435
7436 static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7437 {
7438 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7439 }
7440
7441 #define GEN_SPEOP_LDST(name, opc2, sh) \
7442 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \
7443 { \
7444 TCGv t0; \
7445 if (unlikely(!ctx->spe_enabled)) { \
7446 gen_exception(ctx, POWERPC_EXCP_APU); \
7447 return; \
7448 } \
7449 gen_set_access_type(ctx, ACCESS_INT); \
7450 t0 = tcg_temp_new(); \
7451 if (Rc(ctx->opcode)) { \
7452 gen_addr_spe_imm_index(ctx, t0, sh); \
7453 } else { \
7454 gen_addr_reg_index(ctx, t0); \
7455 } \
7456 gen_op_##name(ctx, t0); \
7457 tcg_temp_free(t0); \
7458 }
7459
7460 GEN_SPEOP_LDST(evldd, 0x00, 3);
7461 GEN_SPEOP_LDST(evldw, 0x01, 3);
7462 GEN_SPEOP_LDST(evldh, 0x02, 3);
7463 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7464 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7465 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7466 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7467 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7468 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7469 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7470 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7471
7472 GEN_SPEOP_LDST(evstdd, 0x10, 3);
7473 GEN_SPEOP_LDST(evstdw, 0x11, 3);
7474 GEN_SPEOP_LDST(evstdh, 0x12, 3);
7475 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7476 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7477 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7478 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
7479
7480 /* Multiply and add - TODO */
7481 #if 0
7482 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
7483 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
7484 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
7485 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
7486 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
7487 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
7488 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
7489 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
7490 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
7491 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
7492 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
7493 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
7494
7495 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
7496 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
7497 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
7498 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
7499 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
7500 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
7501 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
7502 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
7503 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
7504 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
7505 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
7506 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
7507 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
7508 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
7509
7510 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
7511 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
7512 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
7513 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
7514 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
7515 GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
7516
7517 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
7518 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
7519 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
7520 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
7521 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
7522 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
7523 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
7524 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
7525 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
7526 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
7527 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
7528 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
7529
7530 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
7531 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
7532 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
7533 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
7534 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
7535
7536 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
7537 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
7538 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
7539 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
7540 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
7541 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
7542 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
7543 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
7544 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
7545 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
7546 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
7547 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
7548
7549 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
7550 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
7551 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
7552 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
7553 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
7554 #endif
7555
7556 /*** SPE floating-point extension ***/
7557 #if defined(TARGET_PPC64)
7558 #define GEN_SPEFPUOP_CONV_32_32(name) \
7559 static always_inline void gen_##name (DisasContext *ctx) \
7560 { \
7561 TCGv_i32 t0; \
7562 TCGv t1; \
7563 t0 = tcg_temp_new_i32(); \
7564 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7565 gen_helper_##name(t0, t0); \
7566 t1 = tcg_temp_new(); \
7567 tcg_gen_extu_i32_tl(t1, t0); \
7568 tcg_temp_free_i32(t0); \
7569 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7570 0xFFFFFFFF00000000ULL); \
7571 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7572 tcg_temp_free(t1); \
7573 }
7574 #define GEN_SPEFPUOP_CONV_32_64(name) \
7575 static always_inline void gen_##name (DisasContext *ctx) \
7576 { \
7577 TCGv_i32 t0; \
7578 TCGv t1; \
7579 t0 = tcg_temp_new_i32(); \
7580 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7581 t1 = tcg_temp_new(); \
7582 tcg_gen_extu_i32_tl(t1, t0); \
7583 tcg_temp_free_i32(t0); \
7584 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7585 0xFFFFFFFF00000000ULL); \
7586 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7587 tcg_temp_free(t1); \
7588 }
7589 #define GEN_SPEFPUOP_CONV_64_32(name) \
7590 static always_inline void gen_##name (DisasContext *ctx) \
7591 { \
7592 TCGv_i32 t0 = tcg_temp_new_i32(); \
7593 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7594 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7595 tcg_temp_free_i32(t0); \
7596 }
7597 #define GEN_SPEFPUOP_CONV_64_64(name) \
7598 static always_inline void gen_##name (DisasContext *ctx) \
7599 { \
7600 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7601 }
7602 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7603 static always_inline void gen_##name (DisasContext *ctx) \
7604 { \
7605 TCGv_i32 t0, t1; \
7606 TCGv_i64 t2; \
7607 if (unlikely(!ctx->spe_enabled)) { \
7608 gen_exception(ctx, POWERPC_EXCP_APU); \
7609 return; \
7610 } \
7611 t0 = tcg_temp_new_i32(); \
7612 t1 = tcg_temp_new_i32(); \
7613 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7614 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7615 gen_helper_##name(t0, t0, t1); \
7616 tcg_temp_free_i32(t1); \
7617 t2 = tcg_temp_new(); \
7618 tcg_gen_extu_i32_tl(t2, t0); \
7619 tcg_temp_free_i32(t0); \
7620 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7621 0xFFFFFFFF00000000ULL); \
7622 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
7623 tcg_temp_free(t2); \
7624 }
7625 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7626 static always_inline void gen_##name (DisasContext *ctx) \
7627 { \
7628 if (unlikely(!ctx->spe_enabled)) { \
7629 gen_exception(ctx, POWERPC_EXCP_APU); \
7630 return; \
7631 } \
7632 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7633 cpu_gpr[rB(ctx->opcode)]); \
7634 }
7635 #define GEN_SPEFPUOP_COMP_32(name) \
7636 static always_inline void gen_##name (DisasContext *ctx) \
7637 { \
7638 TCGv_i32 t0, t1; \
7639 if (unlikely(!ctx->spe_enabled)) { \
7640 gen_exception(ctx, POWERPC_EXCP_APU); \
7641 return; \
7642 } \
7643 t0 = tcg_temp_new_i32(); \
7644 t1 = tcg_temp_new_i32(); \
7645 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7646 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7647 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7648 tcg_temp_free_i32(t0); \
7649 tcg_temp_free_i32(t1); \
7650 }
7651 #define GEN_SPEFPUOP_COMP_64(name) \
7652 static always_inline void gen_##name (DisasContext *ctx) \
7653 { \
7654 if (unlikely(!ctx->spe_enabled)) { \
7655 gen_exception(ctx, POWERPC_EXCP_APU); \
7656 return; \
7657 } \
7658 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7659 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7660 }
7661 #else
7662 #define GEN_SPEFPUOP_CONV_32_32(name) \
7663 static always_inline void gen_##name (DisasContext *ctx) \
7664 { \
7665 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7666 }
7667 #define GEN_SPEFPUOP_CONV_32_64(name) \
7668 static always_inline void gen_##name (DisasContext *ctx) \
7669 { \
7670 TCGv_i64 t0 = tcg_temp_new_i64(); \
7671 gen_load_gpr64(t0, rB(ctx->opcode)); \
7672 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7673 tcg_temp_free_i64(t0); \
7674 }
7675 #define GEN_SPEFPUOP_CONV_64_32(name) \
7676 static always_inline void gen_##name (DisasContext *ctx) \
7677 { \
7678 TCGv_i64 t0 = tcg_temp_new_i64(); \
7679 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7680 gen_store_gpr64(rD(ctx->opcode), t0); \
7681 tcg_temp_free_i64(t0); \
7682 }
7683 #define GEN_SPEFPUOP_CONV_64_64(name) \
7684 static always_inline void gen_##name (DisasContext *ctx) \
7685 { \
7686 TCGv_i64 t0 = tcg_temp_new_i64(); \
7687 gen_load_gpr64(t0, rB(ctx->opcode)); \
7688 gen_helper_##name(t0, t0); \
7689 gen_store_gpr64(rD(ctx->opcode), t0); \
7690 tcg_temp_free_i64(t0); \
7691 }
7692 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7693 static always_inline void gen_##name (DisasContext *ctx) \
7694 { \
7695 if (unlikely(!ctx->spe_enabled)) { \
7696 gen_exception(ctx, POWERPC_EXCP_APU); \
7697 return; \
7698 } \
7699 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7700 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7701 }
7702 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7703 static always_inline void gen_##name (DisasContext *ctx) \
7704 { \
7705 TCGv_i64 t0, t1; \
7706 if (unlikely(!ctx->spe_enabled)) { \
7707 gen_exception(ctx, POWERPC_EXCP_APU); \
7708 return; \
7709 } \
7710 t0 = tcg_temp_new_i64(); \
7711 t1 = tcg_temp_new_i64(); \
7712 gen_load_gpr64(t0, rA(ctx->opcode)); \
7713 gen_load_gpr64(t1, rB(ctx->opcode)); \
7714 gen_helper_##name(t0, t0, t1); \
7715 gen_store_gpr64(rD(ctx->opcode), t0); \
7716 tcg_temp_free_i64(t0); \
7717 tcg_temp_free_i64(t1); \
7718 }
7719 #define GEN_SPEFPUOP_COMP_32(name) \
7720 static always_inline void gen_##name (DisasContext *ctx) \
7721 { \
7722 if (unlikely(!ctx->spe_enabled)) { \
7723 gen_exception(ctx, POWERPC_EXCP_APU); \
7724 return; \
7725 } \
7726 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7727 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7728 }
7729 #define GEN_SPEFPUOP_COMP_64(name) \
7730 static always_inline void gen_##name (DisasContext *ctx) \
7731 { \
7732 TCGv_i64 t0, t1; \
7733 if (unlikely(!ctx->spe_enabled)) { \
7734 gen_exception(ctx, POWERPC_EXCP_APU); \
7735 return; \
7736 } \
7737 t0 = tcg_temp_new_i64(); \
7738 t1 = tcg_temp_new_i64(); \
7739 gen_load_gpr64(t0, rA(ctx->opcode)); \
7740 gen_load_gpr64(t1, rB(ctx->opcode)); \
7741 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7742 tcg_temp_free_i64(t0); \
7743 tcg_temp_free_i64(t1); \
7744 }
7745 #endif
7746
7747 /* Single precision floating-point vectors operations */
7748 /* Arithmetic */
7749 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
7750 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
7751 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
7752 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7753 static always_inline void gen_evfsabs (DisasContext *ctx)
7754 {
7755 if (unlikely(!ctx->spe_enabled)) {
7756 gen_exception(ctx, POWERPC_EXCP_APU);
7757 return;
7758 }
7759 #if defined(TARGET_PPC64)
7760 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
7761 #else
7762 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
7763 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7764 #endif
7765 }
7766 static always_inline void gen_evfsnabs (DisasContext *ctx)
7767 {
7768 if (unlikely(!ctx->spe_enabled)) {
7769 gen_exception(ctx, POWERPC_EXCP_APU);
7770 return;
7771 }
7772 #if defined(TARGET_PPC64)
7773 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7774 #else
7775 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7776 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7777 #endif
7778 }
7779 static always_inline void gen_evfsneg (DisasContext *ctx)
7780 {
7781 if (unlikely(!ctx->spe_enabled)) {
7782 gen_exception(ctx, POWERPC_EXCP_APU);
7783 return;
7784 }
7785 #if defined(TARGET_PPC64)
7786 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7787 #else
7788 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7789 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7790 #endif
7791 }
7792
7793 /* Conversion */
7794 GEN_SPEFPUOP_CONV_64_64(evfscfui);
7795 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
7796 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
7797 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
7798 GEN_SPEFPUOP_CONV_64_64(evfsctui);
7799 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
7800 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
7801 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
7802 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
7803 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
7804
7805 /* Comparison */
7806 GEN_SPEFPUOP_COMP_64(evfscmpgt);
7807 GEN_SPEFPUOP_COMP_64(evfscmplt);
7808 GEN_SPEFPUOP_COMP_64(evfscmpeq);
7809 GEN_SPEFPUOP_COMP_64(evfststgt);
7810 GEN_SPEFPUOP_COMP_64(evfststlt);
7811 GEN_SPEFPUOP_COMP_64(evfststeq);
7812
7813 /* Opcodes definitions */
7814 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
7815 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
7816 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
7817 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
7818 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
7819 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
7820 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
7821 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
7822 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
7823 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
7824 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
7825 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
7826 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
7827 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
7828
7829 /* Single precision floating-point operations */
7830 /* Arithmetic */
7831 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
7832 GEN_SPEFPUOP_ARITH2_32_32(efssub);
7833 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
7834 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7835 static always_inline void gen_efsabs (DisasContext *ctx)
7836 {
7837 if (unlikely(!ctx->spe_enabled)) {
7838 gen_exception(ctx, POWERPC_EXCP_APU);
7839 return;
7840 }
7841 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
7842 }
7843 static always_inline void gen_efsnabs (DisasContext *ctx)
7844 {
7845 if (unlikely(!ctx->spe_enabled)) {
7846 gen_exception(ctx, POWERPC_EXCP_APU);
7847 return;
7848 }
7849 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7850 }
7851 static always_inline void gen_efsneg (DisasContext *ctx)
7852 {
7853 if (unlikely(!ctx->spe_enabled)) {
7854 gen_exception(ctx, POWERPC_EXCP_APU);
7855 return;
7856 }
7857 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7858 }
7859
7860 /* Conversion */
7861 GEN_SPEFPUOP_CONV_32_32(efscfui);
7862 GEN_SPEFPUOP_CONV_32_32(efscfsi);
7863 GEN_SPEFPUOP_CONV_32_32(efscfuf);
7864 GEN_SPEFPUOP_CONV_32_32(efscfsf);
7865 GEN_SPEFPUOP_CONV_32_32(efsctui);
7866 GEN_SPEFPUOP_CONV_32_32(efsctsi);
7867 GEN_SPEFPUOP_CONV_32_32(efsctuf);
7868 GEN_SPEFPUOP_CONV_32_32(efsctsf);
7869 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
7870 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
7871 GEN_SPEFPUOP_CONV_32_64(efscfd);
7872
7873 /* Comparison */
7874 GEN_SPEFPUOP_COMP_32(efscmpgt);
7875 GEN_SPEFPUOP_COMP_32(efscmplt);
7876 GEN_SPEFPUOP_COMP_32(efscmpeq);
7877 GEN_SPEFPUOP_COMP_32(efststgt);
7878 GEN_SPEFPUOP_COMP_32(efststlt);
7879 GEN_SPEFPUOP_COMP_32(efststeq);
7880
7881 /* Opcodes definitions */
7882 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
7883 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
7884 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
7885 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
7886 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
7887 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
7888 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
7889 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
7890 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
7891 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
7892 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
7893 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
7894 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
7895 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
7896
7897 /* Double precision floating-point operations */
7898 /* Arithmetic */
7899 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
7900 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
7901 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
7902 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
7903 static always_inline void gen_efdabs (DisasContext *ctx)
7904 {
7905 if (unlikely(!ctx->spe_enabled)) {
7906 gen_exception(ctx, POWERPC_EXCP_APU);
7907 return;
7908 }
7909 #if defined(TARGET_PPC64)
7910 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
7911 #else
7912 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7913 #endif
7914 }
7915 static always_inline void gen_efdnabs (DisasContext *ctx)
7916 {
7917 if (unlikely(!ctx->spe_enabled)) {
7918 gen_exception(ctx, POWERPC_EXCP_APU);
7919 return;
7920 }
7921 #if defined(TARGET_PPC64)
7922 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7923 #else
7924 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7925 #endif
7926 }
7927 static always_inline void gen_efdneg (DisasContext *ctx)
7928 {
7929 if (unlikely(!ctx->spe_enabled)) {
7930 gen_exception(ctx, POWERPC_EXCP_APU);
7931 return;
7932 }
7933 #if defined(TARGET_PPC64)
7934 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7935 #else
7936 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7937 #endif
7938 }
7939
7940 /* Conversion */
7941 GEN_SPEFPUOP_CONV_64_32(efdcfui);
7942 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
7943 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
7944 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
7945 GEN_SPEFPUOP_CONV_32_64(efdctui);
7946 GEN_SPEFPUOP_CONV_32_64(efdctsi);
7947 GEN_SPEFPUOP_CONV_32_64(efdctuf);
7948 GEN_SPEFPUOP_CONV_32_64(efdctsf);
7949 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
7950 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
7951 GEN_SPEFPUOP_CONV_64_32(efdcfs);
7952 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
7953 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
7954 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
7955 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
7956
7957 /* Comparison */
7958 GEN_SPEFPUOP_COMP_64(efdcmpgt);
7959 GEN_SPEFPUOP_COMP_64(efdcmplt);
7960 GEN_SPEFPUOP_COMP_64(efdcmpeq);
7961 GEN_SPEFPUOP_COMP_64(efdtstgt);
7962 GEN_SPEFPUOP_COMP_64(efdtstlt);
7963 GEN_SPEFPUOP_COMP_64(efdtsteq);
7964
7965 /* Opcodes definitions */
7966 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
7967 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
7968 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
7969 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
7970 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
7971 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
7972 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
7973 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
7974 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
7975 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
7976 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
7977 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
7978 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
7979 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
7980 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
7981 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
7982
7983 /* End opcode list */
7984 GEN_OPCODE_MARK(end);
7985
7986 #include "translate_init.c"
7987 #include "helper_regs.h"
7988
7989 /*****************************************************************************/
7990 /* Misc PowerPC helpers */
7991 void cpu_dump_state (CPUState *env, FILE *f,
7992 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
7993 int flags)
7994 {
7995 #define RGPL 4
7996 #define RFPL 4
7997
7998 int i;
7999
8000 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
8001 env->nip, env->lr, env->ctr, env->xer);
8002 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
8003 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
8004 #if !defined(NO_TIMER_DUMP)
8005 cpu_fprintf(f, "TB %08x %08x "
8006 #if !defined(CONFIG_USER_ONLY)
8007 "DECR %08x"
8008 #endif
8009 "\n",
8010 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
8011 #if !defined(CONFIG_USER_ONLY)
8012 , cpu_ppc_load_decr(env)
8013 #endif
8014 );
8015 #endif
8016 for (i = 0; i < 32; i++) {
8017 if ((i & (RGPL - 1)) == 0)
8018 cpu_fprintf(f, "GPR%02d", i);
8019 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
8020 if ((i & (RGPL - 1)) == (RGPL - 1))
8021 cpu_fprintf(f, "\n");
8022 }
8023 cpu_fprintf(f, "CR ");
8024 for (i = 0; i < 8; i++)
8025 cpu_fprintf(f, "%01x", env->crf[i]);
8026 cpu_fprintf(f, " [");
8027 for (i = 0; i < 8; i++) {
8028 char a = '-';
8029 if (env->crf[i] & 0x08)
8030 a = 'L';
8031 else if (env->crf[i] & 0x04)
8032 a = 'G';
8033 else if (env->crf[i] & 0x02)
8034 a = 'E';
8035 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
8036 }
8037 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
8038 for (i = 0; i < 32; i++) {
8039 if ((i & (RFPL - 1)) == 0)
8040 cpu_fprintf(f, "FPR%02d", i);
8041 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
8042 if ((i & (RFPL - 1)) == (RFPL - 1))
8043 cpu_fprintf(f, "\n");
8044 }
8045 cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
8046 #if !defined(CONFIG_USER_ONLY)
8047 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
8048 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
8049 #endif
8050
8051 #undef RGPL
8052 #undef RFPL
8053 }
8054
8055 void cpu_dump_statistics (CPUState *env, FILE*f,
8056 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8057 int flags)
8058 {
8059 #if defined(DO_PPC_STATISTICS)
8060 opc_handler_t **t1, **t2, **t3, *handler;
8061 int op1, op2, op3;
8062
8063 t1 = env->opcodes;
8064 for (op1 = 0; op1 < 64; op1++) {
8065 handler = t1[op1];
8066 if (is_indirect_opcode(handler)) {
8067 t2 = ind_table(handler);
8068 for (op2 = 0; op2 < 32; op2++) {
8069 handler = t2[op2];
8070 if (is_indirect_opcode(handler)) {
8071 t3 = ind_table(handler);
8072 for (op3 = 0; op3 < 32; op3++) {
8073 handler = t3[op3];
8074 if (handler->count == 0)
8075 continue;
8076 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
8077 "%016llx %lld\n",
8078 op1, op2, op3, op1, (op3 << 5) | op2,
8079 handler->oname,
8080 handler->count, handler->count);
8081 }
8082 } else {
8083 if (handler->count == 0)
8084 continue;
8085 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
8086 "%016llx %lld\n",
8087 op1, op2, op1, op2, handler->oname,
8088 handler->count, handler->count);
8089 }
8090 }
8091 } else {
8092 if (handler->count == 0)
8093 continue;
8094 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
8095 op1, op1, handler->oname,
8096 handler->count, handler->count);
8097 }
8098 }
8099 #endif
8100 }
8101
8102 /*****************************************************************************/
8103 static always_inline void gen_intermediate_code_internal (CPUState *env,
8104 TranslationBlock *tb,
8105 int search_pc)
8106 {
8107 DisasContext ctx, *ctxp = &ctx;
8108 opc_handler_t **table, *handler;
8109 target_ulong pc_start;
8110 uint16_t *gen_opc_end;
8111 CPUBreakpoint *bp;
8112 int j, lj = -1;
8113 int num_insns;
8114 int max_insns;
8115
8116 pc_start = tb->pc;
8117 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
8118 ctx.nip = pc_start;
8119 ctx.tb = tb;
8120 ctx.exception = POWERPC_EXCP_NONE;
8121 ctx.spr_cb = env->spr_cb;
8122 ctx.mem_idx = env->mmu_idx;
8123 ctx.access_type = -1;
8124 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
8125 #if defined(TARGET_PPC64)
8126 ctx.sf_mode = msr_sf;
8127 #endif
8128 ctx.fpu_enabled = msr_fp;
8129 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
8130 ctx.spe_enabled = msr_spe;
8131 else
8132 ctx.spe_enabled = 0;
8133 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
8134 ctx.altivec_enabled = msr_vr;
8135 else
8136 ctx.altivec_enabled = 0;
8137 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8138 ctx.singlestep_enabled = CPU_SINGLE_STEP;
8139 else
8140 ctx.singlestep_enabled = 0;
8141 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8142 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
8143 if (unlikely(env->singlestep_enabled))
8144 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
8145 #if defined (DO_SINGLE_STEP) && 0
8146 /* Single step trace mode */
8147 msr_se = 1;
8148 #endif
8149 num_insns = 0;
8150 max_insns = tb->cflags & CF_COUNT_MASK;
8151 if (max_insns == 0)
8152 max_insns = CF_COUNT_MASK;
8153
8154 gen_icount_start();
8155 /* Set env in case of segfault during code fetch */
8156 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
8157 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
8158 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
8159 if (bp->pc == ctx.nip) {
8160 gen_debug_exception(ctxp);
8161 break;
8162 }
8163 }
8164 }
8165 if (unlikely(search_pc)) {
8166 j = gen_opc_ptr - gen_opc_buf;
8167 if (lj < j) {
8168 lj++;
8169 while (lj < j)
8170 gen_opc_instr_start[lj++] = 0;
8171 gen_opc_pc[lj] = ctx.nip;
8172 gen_opc_instr_start[lj] = 1;
8173 gen_opc_icount[lj] = num_insns;
8174 }
8175 }
8176 #if defined PPC_DEBUG_DISAS
8177 if (loglevel & CPU_LOG_TB_IN_ASM) {
8178 fprintf(logfile, "----------------\n");
8179 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
8180 ctx.nip, ctx.mem_idx, (int)msr_ir);
8181 }
8182 #endif
8183 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
8184 gen_io_start();
8185 if (unlikely(ctx.le_mode)) {
8186 ctx.opcode = bswap32(ldl_code(ctx.nip));
8187 } else {
8188 ctx.opcode = ldl_code(ctx.nip);
8189 }
8190 #if defined PPC_DEBUG_DISAS
8191 if (loglevel & CPU_LOG_TB_IN_ASM) {
8192 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
8193 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
8194 opc3(ctx.opcode), little_endian ? "little" : "big");
8195 }
8196 #endif
8197 ctx.nip += 4;
8198 table = env->opcodes;
8199 num_insns++;
8200 handler = table[opc1(ctx.opcode)];
8201 if (is_indirect_opcode(handler)) {
8202 table = ind_table(handler);
8203 handler = table[opc2(ctx.opcode)];
8204 if (is_indirect_opcode(handler)) {
8205 table = ind_table(handler);
8206 handler = table[opc3(ctx.opcode)];
8207 }
8208 }
8209 /* Is opcode *REALLY* valid ? */
8210 if (unlikely(handler->handler == &gen_invalid)) {
8211 if (loglevel != 0) {
8212 fprintf(logfile, "invalid/unsupported opcode: "
8213 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
8214 opc1(ctx.opcode), opc2(ctx.opcode),
8215 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
8216 } else {
8217 printf("invalid/unsupported opcode: "
8218 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
8219 opc1(ctx.opcode), opc2(ctx.opcode),
8220 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
8221 }
8222 } else {
8223 if (unlikely((ctx.opcode & handler->inval) != 0)) {
8224 if (loglevel != 0) {
8225 fprintf(logfile, "invalid bits: %08x for opcode: "
8226 "%02x - %02x - %02x (%08x) " ADDRX "\n",
8227 ctx.opcode & handler->inval, opc1(ctx.opcode),
8228 opc2(ctx.opcode), opc3(ctx.opcode),
8229 ctx.opcode, ctx.nip - 4);
8230 } else {
8231 printf("invalid bits: %08x for opcode: "
8232 "%02x - %02x - %02x (%08x) " ADDRX "\n",
8233 ctx.opcode & handler->inval, opc1(ctx.opcode),
8234 opc2(ctx.opcode), opc3(ctx.opcode),
8235 ctx.opcode, ctx.nip - 4);
8236 }
8237 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
8238 break;
8239 }
8240 }
8241 (*(handler->handler))(&ctx);
8242 #if defined(DO_PPC_STATISTICS)
8243 handler->count++;
8244 #endif
8245 /* Check trace mode exceptions */
8246 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
8247 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
8248 ctx.exception != POWERPC_SYSCALL &&
8249 ctx.exception != POWERPC_EXCP_TRAP &&
8250 ctx.exception != POWERPC_EXCP_BRANCH)) {
8251 gen_exception(ctxp, POWERPC_EXCP_TRACE);
8252 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
8253 (env->singlestep_enabled) ||
8254 num_insns >= max_insns)) {
8255 /* if we reach a page boundary or are single stepping, stop
8256 * generation
8257 */
8258 break;
8259 }
8260 #if defined (DO_SINGLE_STEP)
8261 break;
8262 #endif
8263 }
8264 if (tb->cflags & CF_LAST_IO)
8265 gen_io_end();
8266 if (ctx.exception == POWERPC_EXCP_NONE) {
8267 gen_goto_tb(&ctx, 0, ctx.nip);
8268 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8269 if (unlikely(env->singlestep_enabled)) {
8270 gen_debug_exception(ctxp);
8271 }
8272 /* Generate the return instruction */
8273 tcg_gen_exit_tb(0);
8274 }
8275 gen_icount_end(tb, num_insns);
8276 *gen_opc_ptr = INDEX_op_end;
8277 if (unlikely(search_pc)) {
8278 j = gen_opc_ptr - gen_opc_buf;
8279 lj++;
8280 while (lj <= j)
8281 gen_opc_instr_start[lj++] = 0;
8282 } else {
8283 tb->size = ctx.nip - pc_start;
8284 tb->icount = num_insns;
8285 }
8286 #if defined(DEBUG_DISAS)
8287 if (loglevel & CPU_LOG_TB_CPU) {
8288 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
8289 cpu_dump_state(env, logfile, fprintf, 0);
8290 }
8291 if (loglevel & CPU_LOG_TB_IN_ASM) {
8292 int flags;
8293 flags = env->bfd_mach;
8294 flags |= ctx.le_mode << 16;
8295 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
8296 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
8297 fprintf(logfile, "\n");
8298 }
8299 #endif
8300 }
8301
8302 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
8303 {
8304 gen_intermediate_code_internal(env, tb, 0);
8305 }
8306
8307 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
8308 {
8309 gen_intermediate_code_internal(env, tb, 1);
8310 }
8311
8312 void gen_pc_load(CPUState *env, TranslationBlock *tb,
8313 unsigned long searched_pc, int pc_pos, void *puc)
8314 {
8315 env->nip = gen_opc_pc[pc_pos];
8316 }
Qemu copy for testing