2 * PowerPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 /* Include definitions for instructions classes and implementations flags */
31 //#define DO_SINGLE_STEP
32 //#define PPC_DEBUG_DISAS
33 //#define DEBUG_MEMORY_ACCESSES
34 //#define DO_PPC_STATISTICS
36 /*****************************************************************************/
37 /* Code translation helpers */
38 #if defined(USE_DIRECT_JUMP)
41 #define TBPARAM(x) (long)(x)
45 #define DEF(s, n, copy_size) INDEX_op_ ## s,
51 static uint16_t *gen_opc_ptr
;
52 static uint32_t *gen_opparam_ptr
;
56 static inline void gen_set_T0 (target_ulong val
)
58 #if defined(TARGET_PPC64)
60 gen_op_set_T0_64(val
>> 32, val
);
66 static inline void gen_set_T1 (target_ulong val
)
68 #if defined(TARGET_PPC64)
70 gen_op_set_T1_64(val
>> 32, val
);
76 #define GEN8(func, NAME) \
77 static GenOpFunc *NAME ## _table [8] = { \
78 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
79 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
81 static inline void func(int n) \
83 NAME ## _table[n](); \
86 #define GEN16(func, NAME) \
87 static GenOpFunc *NAME ## _table [16] = { \
88 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
89 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
90 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
91 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
93 static inline void func(int n) \
95 NAME ## _table[n](); \
98 #define GEN32(func, NAME) \
99 static GenOpFunc *NAME ## _table [32] = { \
100 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
101 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
102 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
103 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
104 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
105 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
106 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
107 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
109 static inline void func(int n) \
111 NAME ## _table[n](); \
114 /* Condition register moves */
115 GEN8(gen_op_load_crf_T0
, gen_op_load_crf_T0_crf
);
116 GEN8(gen_op_load_crf_T1
, gen_op_load_crf_T1_crf
);
117 GEN8(gen_op_store_T0_crf
, gen_op_store_T0_crf_crf
);
118 GEN8(gen_op_store_T1_crf
, gen_op_store_T1_crf_crf
);
120 /* Floating point condition and status register moves */
121 GEN8(gen_op_load_fpscr_T0
, gen_op_load_fpscr_T0_fpscr
);
122 GEN8(gen_op_store_T0_fpscr
, gen_op_store_T0_fpscr_fpscr
);
123 GEN8(gen_op_clear_fpscr
, gen_op_clear_fpscr_fpscr
);
124 static inline void gen_op_store_T0_fpscri (int n
, uint8_t param
)
126 gen_op_set_T0(param
);
127 gen_op_store_T0_fpscr(n
);
130 /* General purpose registers moves */
131 GEN32(gen_op_load_gpr_T0
, gen_op_load_gpr_T0_gpr
);
132 GEN32(gen_op_load_gpr_T1
, gen_op_load_gpr_T1_gpr
);
133 GEN32(gen_op_load_gpr_T2
, gen_op_load_gpr_T2_gpr
);
135 GEN32(gen_op_store_T0_gpr
, gen_op_store_T0_gpr_gpr
);
136 GEN32(gen_op_store_T1_gpr
, gen_op_store_T1_gpr_gpr
);
138 GEN32(gen_op_store_T2_gpr
, gen_op_store_T2_gpr_gpr
);
141 /* floating point registers moves */
142 GEN32(gen_op_load_fpr_FT0
, gen_op_load_fpr_FT0_fpr
);
143 GEN32(gen_op_load_fpr_FT1
, gen_op_load_fpr_FT1_fpr
);
144 GEN32(gen_op_load_fpr_FT2
, gen_op_load_fpr_FT2_fpr
);
145 GEN32(gen_op_store_FT0_fpr
, gen_op_store_FT0_fpr_fpr
);
146 GEN32(gen_op_store_FT1_fpr
, gen_op_store_FT1_fpr_fpr
);
148 GEN32(gen_op_store_FT2_fpr
, gen_op_store_FT2_fpr_fpr
);
151 /* internal defines */
152 typedef struct DisasContext
{
153 struct TranslationBlock
*tb
;
157 /* Routine used to access memory */
159 /* Translation flags */
160 #if !defined(CONFIG_USER_ONLY)
163 #if defined(TARGET_PPC64)
167 #if defined(TARGET_PPCEMB)
170 ppc_spr_t
*spr_cb
; /* Needed to check rights for mfspr/mtspr */
171 int singlestep_enabled
;
174 struct opc_handler_t
{
177 /* instruction type */
180 void (*handler
)(DisasContext
*ctx
);
181 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
182 const unsigned char *oname
;
184 #if defined(DO_PPC_STATISTICS)
189 static inline void gen_set_Rc0 (DisasContext
*ctx
)
191 #if defined(TARGET_PPC64)
200 static inline void gen_update_nip (DisasContext
*ctx
, target_ulong nip
)
202 #if defined(TARGET_PPC64)
204 gen_op_update_nip_64(nip
>> 32, nip
);
207 gen_op_update_nip(nip
);
210 #define GEN_EXCP(ctx, excp, error) \
212 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
213 gen_update_nip(ctx, (ctx)->nip); \
215 gen_op_raise_exception_err((excp), (error)); \
216 ctx->exception = (excp); \
219 #define GEN_EXCP_INVAL(ctx) \
220 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
221 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
223 #define GEN_EXCP_PRIVOPC(ctx) \
224 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
225 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
227 #define GEN_EXCP_PRIVREG(ctx) \
228 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
229 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
231 #define GEN_EXCP_NO_FP(ctx) \
232 GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
234 #define GEN_EXCP_NO_AP(ctx) \
235 GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
237 /* Stop translation */
238 static inline void GEN_STOP (DisasContext
*ctx
)
240 gen_update_nip(ctx
, ctx
->nip
);
241 ctx
->exception
= POWERPC_EXCP_STOP
;
244 /* No need to update nip here, as execution flow will change */
245 static inline void GEN_SYNC (DisasContext
*ctx
)
247 ctx
->exception
= POWERPC_EXCP_SYNC
;
250 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
251 static void gen_##name (DisasContext *ctx); \
252 GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
253 static void gen_##name (DisasContext *ctx)
255 typedef struct opcode_t
{
256 unsigned char opc1
, opc2
, opc3
;
257 #if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */
258 unsigned char pad
[5];
260 unsigned char pad
[1];
262 opc_handler_t handler
;
263 const unsigned char *oname
;
266 /*****************************************************************************/
267 /*** Instruction decoding ***/
268 #define EXTRACT_HELPER(name, shift, nb) \
269 static inline uint32_t name (uint32_t opcode) \
271 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
274 #define EXTRACT_SHELPER(name, shift, nb) \
275 static inline int32_t name (uint32_t opcode) \
277 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
281 EXTRACT_HELPER(opc1
, 26, 6);
283 EXTRACT_HELPER(opc2
, 1, 5);
285 EXTRACT_HELPER(opc3
, 6, 5);
286 /* Update Cr0 flags */
287 EXTRACT_HELPER(Rc
, 0, 1);
289 EXTRACT_HELPER(rD
, 21, 5);
291 EXTRACT_HELPER(rS
, 21, 5);
293 EXTRACT_HELPER(rA
, 16, 5);
295 EXTRACT_HELPER(rB
, 11, 5);
297 EXTRACT_HELPER(rC
, 6, 5);
299 EXTRACT_HELPER(crfD
, 23, 3);
300 EXTRACT_HELPER(crfS
, 18, 3);
301 EXTRACT_HELPER(crbD
, 21, 5);
302 EXTRACT_HELPER(crbA
, 16, 5);
303 EXTRACT_HELPER(crbB
, 11, 5);
305 EXTRACT_HELPER(_SPR
, 11, 10);
306 static inline uint32_t SPR (uint32_t opcode
)
308 uint32_t sprn
= _SPR(opcode
);
310 return ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
312 /*** Get constants ***/
313 EXTRACT_HELPER(IMM
, 12, 8);
314 /* 16 bits signed immediate value */
315 EXTRACT_SHELPER(SIMM
, 0, 16);
316 /* 16 bits unsigned immediate value */
317 EXTRACT_HELPER(UIMM
, 0, 16);
319 EXTRACT_HELPER(NB
, 11, 5);
321 EXTRACT_HELPER(SH
, 11, 5);
323 EXTRACT_HELPER(MB
, 6, 5);
325 EXTRACT_HELPER(ME
, 1, 5);
327 EXTRACT_HELPER(TO
, 21, 5);
329 EXTRACT_HELPER(CRM
, 12, 8);
330 EXTRACT_HELPER(FM
, 17, 8);
331 EXTRACT_HELPER(SR
, 16, 4);
332 EXTRACT_HELPER(FPIMM
, 20, 4);
334 /*** Jump target decoding ***/
336 EXTRACT_SHELPER(d
, 0, 16);
337 /* Immediate address */
338 static inline target_ulong
LI (uint32_t opcode
)
340 return (opcode
>> 0) & 0x03FFFFFC;
343 static inline uint32_t BD (uint32_t opcode
)
345 return (opcode
>> 0) & 0xFFFC;
348 EXTRACT_HELPER(BO
, 21, 5);
349 EXTRACT_HELPER(BI
, 16, 5);
350 /* Absolute/relative address */
351 EXTRACT_HELPER(AA
, 1, 1);
353 EXTRACT_HELPER(LK
, 0, 1);
355 /* Create a mask between <start> and <end> bits */
356 static inline target_ulong
MASK (uint32_t start
, uint32_t end
)
360 #if defined(TARGET_PPC64)
361 if (likely(start
== 0)) {
362 ret
= (uint64_t)(-1ULL) << (63 - end
);
363 } else if (likely(end
== 63)) {
364 ret
= (uint64_t)(-1ULL) >> start
;
367 if (likely(start
== 0)) {
368 ret
= (uint32_t)(-1ULL) << (31 - end
);
369 } else if (likely(end
== 31)) {
370 ret
= (uint32_t)(-1ULL) >> start
;
374 ret
= (((target_ulong
)(-1ULL)) >> (start
)) ^
375 (((target_ulong
)(-1ULL) >> (end
)) >> 1);
376 if (unlikely(start
> end
))
383 /*****************************************************************************/
384 /* PowerPC Instructions types definitions */
386 PPC_NONE
= 0x0000000000000000ULL
,
387 /* integer operations instructions */
388 /* flow control instructions */
389 /* virtual memory instructions */
390 /* ld/st with reservation instructions */
391 /* cache control instructions */
392 /* spr/msr access instructions */
393 PPC_INSNS_BASE
= 0x0000000000000001ULL
,
394 #define PPC_INTEGER PPC_INSNS_BASE
395 #define PPC_FLOW PPC_INSNS_BASE
396 #define PPC_MEM PPC_INSNS_BASE
397 #define PPC_RES PPC_INSNS_BASE
398 #define PPC_CACHE PPC_INSNS_BASE
399 #define PPC_MISC PPC_INSNS_BASE
400 /* Optional floating point instructions */
401 PPC_FLOAT
= 0x0000000000000002ULL
,
402 PPC_FLOAT_FSQRT
= 0x0000000000000004ULL
,
403 PPC_FLOAT_FRES
= 0x0000000000000008ULL
,
404 PPC_FLOAT_FRSQRTE
= 0x0000000000000010ULL
,
405 PPC_FLOAT_FSEL
= 0x0000000000000020ULL
,
406 PPC_FLOAT_STFIWX
= 0x0000000000000040ULL
,
407 /* external control instructions */
408 PPC_EXTERN
= 0x0000000000000080ULL
,
409 /* segment register access instructions */
410 PPC_SEGMENT
= 0x0000000000000100ULL
,
411 /* Optional cache control instruction */
412 PPC_CACHE_DCBA
= 0x0000000000000200ULL
,
413 /* Optional memory control instructions */
414 PPC_MEM_TLBIA
= 0x0000000000000400ULL
,
415 PPC_MEM_TLBIE
= 0x0000000000000800ULL
,
416 PPC_MEM_TLBSYNC
= 0x0000000000001000ULL
,
418 PPC_MEM_SYNC
= 0x0000000000002000ULL
,
419 /* PowerPC 6xx TLB management instructions */
420 PPC_6xx_TLB
= 0x0000000000004000ULL
,
421 /* Altivec support */
422 PPC_ALTIVEC
= 0x0000000000008000ULL
,
423 /* Time base mftb instruction */
424 PPC_MFTB
= 0x0000000000010000ULL
,
425 /* Embedded PowerPC dedicated instructions */
426 PPC_EMB_COMMON
= 0x0000000000020000ULL
,
427 /* PowerPC 40x exception model */
428 PPC_40x_EXCP
= 0x0000000000040000ULL
,
429 /* PowerPC 40x TLB management instructions */
430 PPC_40x_TLB
= 0x0000000000080000ULL
,
431 /* PowerPC 405 Mac instructions */
432 PPC_405_MAC
= 0x0000000000100000ULL
,
433 /* PowerPC 440 specific instructions */
434 PPC_440_SPEC
= 0x0000000000200000ULL
,
435 /* Power-to-PowerPC bridge (601) */
436 PPC_POWER_BR
= 0x0000000000400000ULL
,
437 /* PowerPC 602 specific */
438 PPC_602_SPEC
= 0x0000000000800000ULL
,
439 /* Deprecated instructions */
440 /* Original POWER instruction set */
441 PPC_POWER
= 0x0000000001000000ULL
,
442 /* POWER2 instruction set extension */
443 PPC_POWER2
= 0x0000000002000000ULL
,
444 /* Power RTC support */
445 PPC_POWER_RTC
= 0x0000000004000000ULL
,
446 /* 64 bits PowerPC instructions */
447 /* 64 bits PowerPC instruction set */
448 PPC_64B
= 0x0000000008000000ULL
,
449 /* 64 bits hypervisor extensions */
450 PPC_64H
= 0x0000000010000000ULL
,
451 /* 64 bits PowerPC "bridge" features */
452 PPC_64_BRIDGE
= 0x0000000020000000ULL
,
453 /* BookE (embedded) PowerPC specification */
454 PPC_BOOKE
= 0x0000000040000000ULL
,
456 PPC_MEM_EIEIO
= 0x0000000080000000ULL
,
457 /* e500 vector instructions */
458 PPC_E500_VECTOR
= 0x0000000100000000ULL
,
459 /* PowerPC 4xx dedicated instructions */
460 PPC_4xx_COMMON
= 0x0000000200000000ULL
,
461 /* PowerPC 2.03 specification extensions */
462 PPC_203
= 0x0000000400000000ULL
,
463 /* PowerPC 2.03 SPE extension */
464 PPC_SPE
= 0x0000000800000000ULL
,
465 /* PowerPC 2.03 SPE floating-point extension */
466 PPC_SPEFPU
= 0x0000001000000000ULL
,
468 PPC_SLBI
= 0x0000002000000000ULL
,
469 /* PowerPC 40x ibct instructions */
470 PPC_40x_ICBT
= 0x0000004000000000ULL
,
471 /* PowerPC 74xx TLB management instructions */
472 PPC_74xx_TLB
= 0x0000008000000000ULL
,
473 /* More BookE (embedded) instructions... */
474 PPC_BOOKE_EXT
= 0x0000010000000000ULL
,
475 /* rfmci is not implemented in all BookE PowerPC */
476 PPC_RFMCI
= 0x0000020000000000ULL
,
477 /* user-mode DCR access, implemented in PowerPC 460 */
478 PPC_DCRUX
= 0x0000040000000000ULL
,
479 /* New floating-point extensions (PowerPC 2.0x) */
480 PPC_FLOAT_EXT
= 0x0000080000000000ULL
,
481 /* New wait instruction (PowerPC 2.0x) */
482 PPC_WAIT
= 0x0000100000000000ULL
,
483 /* New 64 bits extensions (PowerPC 2.0x) */
484 PPC_64BX
= 0x0000200000000000ULL
,
487 /*****************************************************************************/
488 /* PowerPC instructions table */
489 #if HOST_LONG_BITS == 64
494 #if defined(__APPLE__)
495 #define OPCODES_SECTION \
496 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
498 #define OPCODES_SECTION \
499 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
502 #if defined(DO_PPC_STATISTICS)
503 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
504 OPCODES_SECTION opcode_t opc_##name = { \
512 .handler = &gen_##name, \
513 .oname = stringify(name), \
515 .oname = stringify(name), \
518 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
519 OPCODES_SECTION opcode_t opc_##name = { \
527 .handler = &gen_##name, \
529 .oname = stringify(name), \
533 #define GEN_OPCODE_MARK(name) \
534 OPCODES_SECTION opcode_t opc_##name = { \
540 .inval = 0x00000000, \
544 .oname = stringify(name), \
547 /* Start opcode list */
548 GEN_OPCODE_MARK(start
);
550 /* Invalid instruction */
551 GEN_HANDLER(invalid
, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE
)
556 static opc_handler_t invalid_handler
= {
559 .handler
= gen_invalid
,
562 /*** Integer arithmetic ***/
563 #define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) \
564 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
566 gen_op_load_gpr_T0(rA(ctx->opcode)); \
567 gen_op_load_gpr_T1(rB(ctx->opcode)); \
569 gen_op_store_T0_gpr(rD(ctx->opcode)); \
570 if (unlikely(Rc(ctx->opcode) != 0)) \
574 #define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) \
575 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
577 gen_op_load_gpr_T0(rA(ctx->opcode)); \
578 gen_op_load_gpr_T1(rB(ctx->opcode)); \
580 gen_op_store_T0_gpr(rD(ctx->opcode)); \
581 if (unlikely(Rc(ctx->opcode) != 0)) \
585 #define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
586 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
588 gen_op_load_gpr_T0(rA(ctx->opcode)); \
590 gen_op_store_T0_gpr(rD(ctx->opcode)); \
591 if (unlikely(Rc(ctx->opcode) != 0)) \
594 #define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) \
595 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
597 gen_op_load_gpr_T0(rA(ctx->opcode)); \
599 gen_op_store_T0_gpr(rD(ctx->opcode)); \
600 if (unlikely(Rc(ctx->opcode) != 0)) \
604 /* Two operands arithmetic functions */
605 #define GEN_INT_ARITH2(name, opc1, opc2, opc3, type) \
606 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type) \
607 __GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
609 /* Two operands arithmetic functions with no overflow allowed */
610 #define GEN_INT_ARITHN(name, opc1, opc2, opc3, type) \
611 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)
613 /* One operand arithmetic functions */
614 #define GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
615 __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
616 __GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)
618 #if defined(TARGET_PPC64)
619 #define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) \
620 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
622 gen_op_load_gpr_T0(rA(ctx->opcode)); \
623 gen_op_load_gpr_T1(rB(ctx->opcode)); \
625 gen_op_##name##_64(); \
628 gen_op_store_T0_gpr(rD(ctx->opcode)); \
629 if (unlikely(Rc(ctx->opcode) != 0)) \
633 #define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) \
634 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
636 gen_op_load_gpr_T0(rA(ctx->opcode)); \
637 gen_op_load_gpr_T1(rB(ctx->opcode)); \
639 gen_op_##name##_64(); \
642 gen_op_store_T0_gpr(rD(ctx->opcode)); \
643 if (unlikely(Rc(ctx->opcode) != 0)) \
647 #define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
648 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
650 gen_op_load_gpr_T0(rA(ctx->opcode)); \
652 gen_op_##name##_64(); \
655 gen_op_store_T0_gpr(rD(ctx->opcode)); \
656 if (unlikely(Rc(ctx->opcode) != 0)) \
659 #define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) \
660 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
662 gen_op_load_gpr_T0(rA(ctx->opcode)); \
664 gen_op_##name##_64(); \
667 gen_op_store_T0_gpr(rD(ctx->opcode)); \
668 if (unlikely(Rc(ctx->opcode) != 0)) \
672 /* Two operands arithmetic functions */
673 #define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type) \
674 __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type) \
675 __GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
677 /* Two operands arithmetic functions with no overflow allowed */
678 #define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type) \
679 __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)
681 /* One operand arithmetic functions */
682 #define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
683 __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
684 __GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)
686 #define GEN_INT_ARITH2_64 GEN_INT_ARITH2
687 #define GEN_INT_ARITHN_64 GEN_INT_ARITHN
688 #define GEN_INT_ARITH1_64 GEN_INT_ARITH1
691 /* add add. addo addo. */
692 static inline void gen_op_addo (void)
698 #if defined(TARGET_PPC64)
699 #define gen_op_add_64 gen_op_add
700 static inline void gen_op_addo_64 (void)
704 gen_op_check_addo_64();
707 GEN_INT_ARITH2_64 (add
, 0x1F, 0x0A, 0x08, PPC_INTEGER
);
708 /* addc addc. addco addco. */
709 static inline void gen_op_addc (void)
715 static inline void gen_op_addco (void)
722 #if defined(TARGET_PPC64)
723 static inline void gen_op_addc_64 (void)
727 gen_op_check_addc_64();
729 static inline void gen_op_addco_64 (void)
733 gen_op_check_addc_64();
734 gen_op_check_addo_64();
737 GEN_INT_ARITH2_64 (addc
, 0x1F, 0x0A, 0x00, PPC_INTEGER
);
738 /* adde adde. addeo addeo. */
739 static inline void gen_op_addeo (void)
745 #if defined(TARGET_PPC64)
746 static inline void gen_op_addeo_64 (void)
750 gen_op_check_addo_64();
753 GEN_INT_ARITH2_64 (adde
, 0x1F, 0x0A, 0x04, PPC_INTEGER
);
754 /* addme addme. addmeo addmeo. */
755 static inline void gen_op_addme (void)
760 #if defined(TARGET_PPC64)
761 static inline void gen_op_addme_64 (void)
767 GEN_INT_ARITH1_64 (addme
, 0x1F, 0x0A, 0x07, PPC_INTEGER
);
768 /* addze addze. addzeo addzeo. */
769 static inline void gen_op_addze (void)
775 static inline void gen_op_addzeo (void)
782 #if defined(TARGET_PPC64)
783 static inline void gen_op_addze_64 (void)
787 gen_op_check_addc_64();
789 static inline void gen_op_addzeo_64 (void)
793 gen_op_check_addc_64();
794 gen_op_check_addo_64();
797 GEN_INT_ARITH1_64 (addze
, 0x1F, 0x0A, 0x06, PPC_INTEGER
);
798 /* divw divw. divwo divwo. */
799 GEN_INT_ARITH2 (divw
, 0x1F, 0x0B, 0x0F, PPC_INTEGER
);
800 /* divwu divwu. divwuo divwuo. */
801 GEN_INT_ARITH2 (divwu
, 0x1F, 0x0B, 0x0E, PPC_INTEGER
);
803 GEN_INT_ARITHN (mulhw
, 0x1F, 0x0B, 0x02, PPC_INTEGER
);
805 GEN_INT_ARITHN (mulhwu
, 0x1F, 0x0B, 0x00, PPC_INTEGER
);
806 /* mullw mullw. mullwo mullwo. */
807 GEN_INT_ARITH2 (mullw
, 0x1F, 0x0B, 0x07, PPC_INTEGER
);
808 /* neg neg. nego nego. */
809 GEN_INT_ARITH1_64 (neg
, 0x1F, 0x08, 0x03, PPC_INTEGER
);
810 /* subf subf. subfo subfo. */
811 static inline void gen_op_subfo (void)
815 gen_op_check_subfo();
817 #if defined(TARGET_PPC64)
818 #define gen_op_subf_64 gen_op_subf
819 static inline void gen_op_subfo_64 (void)
823 gen_op_check_subfo_64();
826 GEN_INT_ARITH2_64 (subf
, 0x1F, 0x08, 0x01, PPC_INTEGER
);
827 /* subfc subfc. subfco subfco. */
828 static inline void gen_op_subfc (void)
831 gen_op_check_subfc();
833 static inline void gen_op_subfco (void)
837 gen_op_check_subfc();
838 gen_op_check_subfo();
840 #if defined(TARGET_PPC64)
841 static inline void gen_op_subfc_64 (void)
844 gen_op_check_subfc_64();
846 static inline void gen_op_subfco_64 (void)
850 gen_op_check_subfc_64();
851 gen_op_check_subfo_64();
854 GEN_INT_ARITH2_64 (subfc
, 0x1F, 0x08, 0x00, PPC_INTEGER
);
855 /* subfe subfe. subfeo subfeo. */
856 static inline void gen_op_subfeo (void)
860 gen_op_check_subfo();
862 #if defined(TARGET_PPC64)
863 #define gen_op_subfe_64 gen_op_subfe
864 static inline void gen_op_subfeo_64 (void)
868 gen_op_check_subfo_64();
871 GEN_INT_ARITH2_64 (subfe
, 0x1F, 0x08, 0x04, PPC_INTEGER
);
872 /* subfme subfme. subfmeo subfmeo. */
873 GEN_INT_ARITH1_64 (subfme
, 0x1F, 0x08, 0x07, PPC_INTEGER
);
874 /* subfze subfze. subfzeo subfzeo. */
875 GEN_INT_ARITH1_64 (subfze
, 0x1F, 0x08, 0x06, PPC_INTEGER
);
877 GEN_HANDLER(addi
, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
879 target_long simm
= SIMM(ctx
->opcode
);
881 if (rA(ctx
->opcode
) == 0) {
885 gen_op_load_gpr_T0(rA(ctx
->opcode
));
886 if (likely(simm
!= 0))
889 gen_op_store_T0_gpr(rD(ctx
->opcode
));
892 GEN_HANDLER(addic
, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
894 target_long simm
= SIMM(ctx
->opcode
);
896 gen_op_load_gpr_T0(rA(ctx
->opcode
));
897 if (likely(simm
!= 0)) {
900 #if defined(TARGET_PPC64)
902 gen_op_check_addc_64();
907 gen_op_clear_xer_ca();
909 gen_op_store_T0_gpr(rD(ctx
->opcode
));
912 GEN_HANDLER(addic_
, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
914 target_long simm
= SIMM(ctx
->opcode
);
916 gen_op_load_gpr_T0(rA(ctx
->opcode
));
917 if (likely(simm
!= 0)) {
920 #if defined(TARGET_PPC64)
922 gen_op_check_addc_64();
927 gen_op_clear_xer_ca();
929 gen_op_store_T0_gpr(rD(ctx
->opcode
));
933 GEN_HANDLER(addis
, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
935 target_long simm
= SIMM(ctx
->opcode
);
937 if (rA(ctx
->opcode
) == 0) {
939 gen_set_T0(simm
<< 16);
941 gen_op_load_gpr_T0(rA(ctx
->opcode
));
942 if (likely(simm
!= 0))
943 gen_op_addi(simm
<< 16);
945 gen_op_store_T0_gpr(rD(ctx
->opcode
));
948 GEN_HANDLER(mulli
, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
950 gen_op_load_gpr_T0(rA(ctx
->opcode
));
951 gen_op_mulli(SIMM(ctx
->opcode
));
952 gen_op_store_T0_gpr(rD(ctx
->opcode
));
955 GEN_HANDLER(subfic
, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
957 gen_op_load_gpr_T0(rA(ctx
->opcode
));
958 #if defined(TARGET_PPC64)
960 gen_op_subfic_64(SIMM(ctx
->opcode
));
963 gen_op_subfic(SIMM(ctx
->opcode
));
964 gen_op_store_T0_gpr(rD(ctx
->opcode
));
967 #if defined(TARGET_PPC64)
969 GEN_INT_ARITHN (mulhd
, 0x1F, 0x09, 0x02, PPC_64B
);
971 GEN_INT_ARITHN (mulhdu
, 0x1F, 0x09, 0x00, PPC_64B
);
972 /* mulld mulld. mulldo mulldo. */
973 GEN_INT_ARITH2 (mulld
, 0x1F, 0x09, 0x07, PPC_64B
);
974 /* divd divd. divdo divdo. */
975 GEN_INT_ARITH2 (divd
, 0x1F, 0x09, 0x0F, PPC_64B
);
976 /* divdu divdu. divduo divduo. */
977 GEN_INT_ARITH2 (divdu
, 0x1F, 0x09, 0x0E, PPC_64B
);
980 /*** Integer comparison ***/
981 #if defined(TARGET_PPC64)
982 #define GEN_CMP(name, opc, type) \
983 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
985 gen_op_load_gpr_T0(rA(ctx->opcode)); \
986 gen_op_load_gpr_T1(rB(ctx->opcode)); \
987 if (ctx->sf_mode && (ctx->opcode & 0x00200000)) \
988 gen_op_##name##_64(); \
991 gen_op_store_T0_crf(crfD(ctx->opcode)); \
994 #define GEN_CMP(name, opc, type) \
995 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
997 gen_op_load_gpr_T0(rA(ctx->opcode)); \
998 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1000 gen_op_store_T0_crf(crfD(ctx->opcode)); \
1005 GEN_CMP(cmp
, 0x00, PPC_INTEGER
);
1007 GEN_HANDLER(cmpi
, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
)
1009 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1010 #if defined(TARGET_PPC64)
1011 if (ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000))
1012 gen_op_cmpi_64(SIMM(ctx
->opcode
));
1015 gen_op_cmpi(SIMM(ctx
->opcode
));
1016 gen_op_store_T0_crf(crfD(ctx
->opcode
));
1019 GEN_CMP(cmpl
, 0x01, PPC_INTEGER
);
1021 GEN_HANDLER(cmpli
, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
)
1023 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1024 #if defined(TARGET_PPC64)
1025 if (ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000))
1026 gen_op_cmpli_64(UIMM(ctx
->opcode
));
1029 gen_op_cmpli(UIMM(ctx
->opcode
));
1030 gen_op_store_T0_crf(crfD(ctx
->opcode
));
1033 /* isel (PowerPC 2.03 specification) */
1034 GEN_HANDLER(isel
, 0x1F, 0x0F, 0x00, 0x00000001, PPC_203
)
1036 uint32_t bi
= rC(ctx
->opcode
);
1039 if (rA(ctx
->opcode
) == 0) {
1042 gen_op_load_gpr_T1(rA(ctx
->opcode
));
1044 gen_op_load_gpr_T2(rB(ctx
->opcode
));
1045 mask
= 1 << (3 - (bi
& 0x03));
1046 gen_op_load_crf_T0(bi
>> 2);
1047 gen_op_test_true(mask
);
1049 gen_op_store_T0_gpr(rD(ctx
->opcode
));
1052 /*** Integer logical ***/
1053 #define __GEN_LOGICAL2(name, opc2, opc3, type) \
1054 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type) \
1056 gen_op_load_gpr_T0(rS(ctx->opcode)); \
1057 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1059 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1060 if (unlikely(Rc(ctx->opcode) != 0)) \
1063 #define GEN_LOGICAL2(name, opc, type) \
1064 __GEN_LOGICAL2(name, 0x1C, opc, type)
1066 #define GEN_LOGICAL1(name, opc, type) \
1067 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
1069 gen_op_load_gpr_T0(rS(ctx->opcode)); \
1071 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1072 if (unlikely(Rc(ctx->opcode) != 0)) \
1077 GEN_LOGICAL2(and, 0x00, PPC_INTEGER
);
1079 GEN_LOGICAL2(andc
, 0x01, PPC_INTEGER
);
1081 GEN_HANDLER(andi_
, 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1083 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1084 gen_op_andi_T0(UIMM(ctx
->opcode
));
1085 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1089 GEN_HANDLER(andis_
, 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1091 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1092 gen_op_andi_T0(UIMM(ctx
->opcode
) << 16);
1093 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1098 GEN_LOGICAL1(cntlzw
, 0x00, PPC_INTEGER
);
1100 GEN_LOGICAL2(eqv
, 0x08, PPC_INTEGER
);
1101 /* extsb & extsb. */
1102 GEN_LOGICAL1(extsb
, 0x1D, PPC_INTEGER
);
1103 /* extsh & extsh. */
1104 GEN_LOGICAL1(extsh
, 0x1C, PPC_INTEGER
);
1106 GEN_LOGICAL2(nand
, 0x0E, PPC_INTEGER
);
1108 GEN_LOGICAL2(nor
, 0x03, PPC_INTEGER
);
1111 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER
)
1115 rs
= rS(ctx
->opcode
);
1116 ra
= rA(ctx
->opcode
);
1117 rb
= rB(ctx
->opcode
);
1118 /* Optimisation for mr. ri case */
1119 if (rs
!= ra
|| rs
!= rb
) {
1120 gen_op_load_gpr_T0(rs
);
1122 gen_op_load_gpr_T1(rb
);
1125 gen_op_store_T0_gpr(ra
);
1126 if (unlikely(Rc(ctx
->opcode
) != 0))
1128 } else if (unlikely(Rc(ctx
->opcode
) != 0)) {
1129 gen_op_load_gpr_T0(rs
);
1131 #if defined(TARGET_PPC64)
1135 /* Set process priority to low */
1136 gen_op_store_pri(2);
1139 /* Set process priority to medium-low */
1140 gen_op_store_pri(3);
1143 /* Set process priority to normal */
1144 gen_op_store_pri(4);
1146 #if !defined(CONFIG_USER_ONLY)
1148 if (ctx
->supervisor
> 0) {
1149 /* Set process priority to very low */
1150 gen_op_store_pri(1);
1154 if (ctx
->supervisor
> 0) {
1155 /* Set process priority to medium-hight */
1156 gen_op_store_pri(5);
1160 if (ctx
->supervisor
> 0) {
1161 /* Set process priority to high */
1162 gen_op_store_pri(6);
1165 #if defined(TARGET_PPC64H)
1167 if (ctx
->supervisor
> 1) {
1168 /* Set process priority to very high */
1169 gen_op_store_pri(7);
1183 GEN_LOGICAL2(orc
, 0x0C, PPC_INTEGER
);
1185 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER
)
1187 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1188 /* Optimisation for "set to zero" case */
1189 if (rS(ctx
->opcode
) != rB(ctx
->opcode
)) {
1190 gen_op_load_gpr_T1(rB(ctx
->opcode
));
1195 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1196 if (unlikely(Rc(ctx
->opcode
) != 0))
1200 GEN_HANDLER(ori
, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1202 target_ulong uimm
= UIMM(ctx
->opcode
);
1204 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1206 /* XXX: should handle special NOPs for POWER series */
1209 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1210 if (likely(uimm
!= 0))
1212 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1215 GEN_HANDLER(oris
, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1217 target_ulong uimm
= UIMM(ctx
->opcode
);
1219 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1223 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1224 if (likely(uimm
!= 0))
1225 gen_op_ori(uimm
<< 16);
1226 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1229 GEN_HANDLER(xori
, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1231 target_ulong uimm
= UIMM(ctx
->opcode
);
1233 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1237 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1238 if (likely(uimm
!= 0))
1240 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1244 GEN_HANDLER(xoris
, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1246 target_ulong uimm
= UIMM(ctx
->opcode
);
1248 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1252 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1253 if (likely(uimm
!= 0))
1254 gen_op_xori(uimm
<< 16);
1255 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1258 /* popcntb : PowerPC 2.03 specification */
1259 GEN_HANDLER(popcntb
, 0x1F, 0x03, 0x03, 0x0000F801, PPC_203
)
1261 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1262 #if defined(TARGET_PPC64)
1264 gen_op_popcntb_64();
1268 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1271 #if defined(TARGET_PPC64)
1272 /* extsw & extsw. */
1273 GEN_LOGICAL1(extsw
, 0x1E, PPC_64B
);
1275 GEN_LOGICAL1(cntlzd
, 0x01, PPC_64B
);
1278 /*** Integer rotate ***/
1279 /* rlwimi & rlwimi. */
1280 GEN_HANDLER(rlwimi
, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1283 uint32_t mb
, me
, sh
;
1285 mb
= MB(ctx
->opcode
);
1286 me
= ME(ctx
->opcode
);
1287 sh
= SH(ctx
->opcode
);
1288 if (likely(sh
== 0)) {
1289 if (likely(mb
== 0 && me
== 31)) {
1290 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1292 } else if (likely(mb
== 31 && me
== 0)) {
1293 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1296 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1297 gen_op_load_gpr_T1(rA(ctx
->opcode
));
1300 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1301 gen_op_load_gpr_T1(rA(ctx
->opcode
));
1302 gen_op_rotli32_T0(SH(ctx
->opcode
));
1304 #if defined(TARGET_PPC64)
1308 mask
= MASK(mb
, me
);
1309 gen_op_andi_T0(mask
);
1310 gen_op_andi_T1(~mask
);
1313 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1314 if (unlikely(Rc(ctx
->opcode
) != 0))
1317 /* rlwinm & rlwinm. */
1318 GEN_HANDLER(rlwinm
, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1320 uint32_t mb
, me
, sh
;
1322 sh
= SH(ctx
->opcode
);
1323 mb
= MB(ctx
->opcode
);
1324 me
= ME(ctx
->opcode
);
1325 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1326 if (likely(sh
== 0)) {
1329 if (likely(mb
== 0)) {
1330 if (likely(me
== 31)) {
1331 gen_op_rotli32_T0(sh
);
1333 } else if (likely(me
== (31 - sh
))) {
1337 } else if (likely(me
== 31)) {
1338 if (likely(sh
== (32 - mb
))) {
1343 gen_op_rotli32_T0(sh
);
1345 #if defined(TARGET_PPC64)
1349 gen_op_andi_T0(MASK(mb
, me
));
1351 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1352 if (unlikely(Rc(ctx
->opcode
) != 0))
1355 /* rlwnm & rlwnm. */
1356 GEN_HANDLER(rlwnm
, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1360 mb
= MB(ctx
->opcode
);
1361 me
= ME(ctx
->opcode
);
1362 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1363 gen_op_load_gpr_T1(rB(ctx
->opcode
));
1364 gen_op_rotl32_T0_T1();
1365 if (unlikely(mb
!= 0 || me
!= 31)) {
1366 #if defined(TARGET_PPC64)
1370 gen_op_andi_T0(MASK(mb
, me
));
1372 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1373 if (unlikely(Rc(ctx
->opcode
) != 0))
1377 #if defined(TARGET_PPC64)
1378 #define GEN_PPC64_R2(name, opc1, opc2) \
1379 GEN_HANDLER(name##0, opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1381 gen_##name(ctx, 0); \
1383 GEN_HANDLER(name##1, opc1, opc2 | 0x10, 0xFF, 0x00000000, PPC_64B) \
1385 gen_##name(ctx, 1); \
1387 #define GEN_PPC64_R4(name, opc1, opc2) \
1388 GEN_HANDLER(name##0, opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1390 gen_##name(ctx, 0, 0); \
1392 GEN_HANDLER(name##1, opc1, opc2 | 0x01, 0xFF, 0x00000000, PPC_64B) \
1394 gen_##name(ctx, 0, 1); \
1396 GEN_HANDLER(name##2, opc1, opc2 | 0x10, 0xFF, 0x00000000, PPC_64B) \
1398 gen_##name(ctx, 1, 0); \
1400 GEN_HANDLER(name##3, opc1, opc2 | 0x11, 0xFF, 0x00000000, PPC_64B) \
1402 gen_##name(ctx, 1, 1); \
1405 static inline void gen_andi_T0_64 (DisasContext
*ctx
, uint64_t mask
)
1408 gen_op_andi_T0_64(mask
>> 32, mask
& 0xFFFFFFFF);
1410 gen_op_andi_T0(mask
);
1413 static inline void gen_andi_T1_64 (DisasContext
*ctx
, uint64_t mask
)
1416 gen_op_andi_T1_64(mask
>> 32, mask
& 0xFFFFFFFF);
1418 gen_op_andi_T1(mask
);
1421 static inline void gen_rldinm (DisasContext
*ctx
, uint32_t mb
, uint32_t me
,
1424 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1425 if (likely(sh
== 0)) {
1428 if (likely(mb
== 0)) {
1429 if (likely(me
== 63)) {
1430 gen_op_rotli64_T0(sh
);
1432 } else if (likely(me
== (63 - sh
))) {
1436 } else if (likely(me
== 63)) {
1437 if (likely(sh
== (64 - mb
))) {
1438 gen_op_srli_T0_64(mb
);
1442 gen_op_rotli64_T0(sh
);
1444 gen_andi_T0_64(ctx
, MASK(mb
, me
));
1446 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1447 if (unlikely(Rc(ctx
->opcode
) != 0))
1450 /* rldicl - rldicl. */
1451 static inline void gen_rldicl (DisasContext
*ctx
, int mbn
, int shn
)
1455 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1456 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1457 gen_rldinm(ctx
, mb
, 63, sh
);
1459 GEN_PPC64_R4(rldicl
, 0x1E, 0x00);
1460 /* rldicr - rldicr. */
1461 static inline void gen_rldicr (DisasContext
*ctx
, int men
, int shn
)
1465 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1466 me
= MB(ctx
->opcode
) | (men
<< 5);
1467 gen_rldinm(ctx
, 0, me
, sh
);
1469 GEN_PPC64_R4(rldicr
, 0x1E, 0x02);
1470 /* rldic - rldic. */
1471 static inline void gen_rldic (DisasContext
*ctx
, int mbn
, int shn
)
1475 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1476 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1477 gen_rldinm(ctx
, mb
, 63 - sh
, sh
);
1479 GEN_PPC64_R4(rldic
, 0x1E, 0x04);
1481 static inline void gen_rldnm (DisasContext
*ctx
, uint32_t mb
, uint32_t me
)
1483 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1484 gen_op_load_gpr_T1(rB(ctx
->opcode
));
1485 gen_op_rotl64_T0_T1();
1486 if (unlikely(mb
!= 0 || me
!= 63)) {
1487 gen_andi_T0_64(ctx
, MASK(mb
, me
));
1489 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1490 if (unlikely(Rc(ctx
->opcode
) != 0))
1494 /* rldcl - rldcl. */
1495 static inline void gen_rldcl (DisasContext
*ctx
, int mbn
)
1499 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1500 gen_rldnm(ctx
, mb
, 63);
1502 GEN_PPC64_R2(rldcl
, 0x1E, 0x08);
1503 /* rldcr - rldcr. */
1504 static inline void gen_rldcr (DisasContext
*ctx
, int men
)
1508 me
= MB(ctx
->opcode
) | (men
<< 5);
1509 gen_rldnm(ctx
, 0, me
);
1511 GEN_PPC64_R2(rldcr
, 0x1E, 0x09);
1512 /* rldimi - rldimi. */
1513 static inline void gen_rldimi (DisasContext
*ctx
, int mbn
, int shn
)
1518 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1519 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1520 if (likely(sh
== 0)) {
1521 if (likely(mb
== 0)) {
1522 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1524 } else if (likely(mb
== 63)) {
1525 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1528 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1529 gen_op_load_gpr_T1(rA(ctx
->opcode
));
1532 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1533 gen_op_load_gpr_T1(rA(ctx
->opcode
));
1534 gen_op_rotli64_T0(sh
);
1536 mask
= MASK(mb
, 63 - sh
);
1537 gen_andi_T0_64(ctx
, mask
);
1538 gen_andi_T1_64(ctx
, ~mask
);
1541 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1542 if (unlikely(Rc(ctx
->opcode
) != 0))
1545 GEN_PPC64_R4(rldimi
, 0x1E, 0x06);
1548 /*** Integer shift ***/
1550 __GEN_LOGICAL2(slw
, 0x18, 0x00, PPC_INTEGER
);
1552 __GEN_LOGICAL2(sraw
, 0x18, 0x18, PPC_INTEGER
);
1553 /* srawi & srawi. */
1554 GEN_HANDLER(srawi
, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER
)
1557 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1558 if (SH(ctx
->opcode
) != 0) {
1559 gen_op_move_T1_T0();
1560 mb
= 32 - SH(ctx
->opcode
);
1562 #if defined(TARGET_PPC64)
1566 gen_op_srawi(SH(ctx
->opcode
), MASK(mb
, me
));
1568 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1569 if (unlikely(Rc(ctx
->opcode
) != 0))
1573 __GEN_LOGICAL2(srw
, 0x18, 0x10, PPC_INTEGER
);
1575 #if defined(TARGET_PPC64)
1577 __GEN_LOGICAL2(sld
, 0x1B, 0x00, PPC_64B
);
1579 __GEN_LOGICAL2(srad
, 0x1A, 0x18, PPC_64B
);
1580 /* sradi & sradi. */
1581 static inline void gen_sradi (DisasContext
*ctx
, int n
)
1586 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1587 sh
= SH(ctx
->opcode
) + (n
<< 5);
1589 gen_op_move_T1_T0();
1590 mb
= 64 - SH(ctx
->opcode
);
1592 mask
= MASK(mb
, me
);
1593 gen_op_sradi(sh
, mask
>> 32, mask
);
1595 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1596 if (unlikely(Rc(ctx
->opcode
) != 0))
1599 GEN_HANDLER(sradi0
, 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B
)
1603 GEN_HANDLER(sradi1
, 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B
)
1608 __GEN_LOGICAL2(srd
, 0x1B, 0x10, PPC_64B
);
1611 /*** Floating-Point arithmetic ***/
1612 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, type) \
1613 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
1615 if (unlikely(!ctx->fpu_enabled)) { \
1616 GEN_EXCP_NO_FP(ctx); \
1619 gen_op_reset_scrfx(); \
1620 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1621 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
1622 gen_op_load_fpr_FT2(rB(ctx->opcode)); \
1627 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1628 if (unlikely(Rc(ctx->opcode) != 0)) \
1632 #define GEN_FLOAT_ACB(name, op2, type) \
1633 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, type); \
1634 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, type);
1636 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat) \
1637 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
1639 if (unlikely(!ctx->fpu_enabled)) { \
1640 GEN_EXCP_NO_FP(ctx); \
1643 gen_op_reset_scrfx(); \
1644 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1645 gen_op_load_fpr_FT1(rB(ctx->opcode)); \
1650 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1651 if (unlikely(Rc(ctx->opcode) != 0)) \
1654 #define GEN_FLOAT_AB(name, op2, inval) \
1655 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0); \
1656 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1);
1658 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat) \
1659 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
1661 if (unlikely(!ctx->fpu_enabled)) { \
1662 GEN_EXCP_NO_FP(ctx); \
1665 gen_op_reset_scrfx(); \
1666 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1667 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
1672 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1673 if (unlikely(Rc(ctx->opcode) != 0)) \
1676 #define GEN_FLOAT_AC(name, op2, inval) \
1677 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0); \
1678 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1);
1680 #define GEN_FLOAT_B(name, op2, op3, type) \
1681 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
1683 if (unlikely(!ctx->fpu_enabled)) { \
1684 GEN_EXCP_NO_FP(ctx); \
1687 gen_op_reset_scrfx(); \
1688 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
1690 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1691 if (unlikely(Rc(ctx->opcode) != 0)) \
1695 #define GEN_FLOAT_BS(name, op1, op2, type) \
1696 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
1698 if (unlikely(!ctx->fpu_enabled)) { \
1699 GEN_EXCP_NO_FP(ctx); \
1702 gen_op_reset_scrfx(); \
1703 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
1705 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1706 if (unlikely(Rc(ctx->opcode) != 0)) \
1711 GEN_FLOAT_AB(add
, 0x15, 0x000007C0);
1713 GEN_FLOAT_AB(div
, 0x12, 0x000007C0);
1715 GEN_FLOAT_AC(mul
, 0x19, 0x0000F800);
1718 GEN_FLOAT_BS(re
, 0x3F, 0x18, PPC_FLOAT_EXT
);
1721 GEN_FLOAT_BS(res
, 0x3B, 0x18, PPC_FLOAT_FRES
);
1724 GEN_FLOAT_BS(rsqrte
, 0x3F, 0x1A, PPC_FLOAT_FRSQRTE
);
1727 _GEN_FLOAT_ACB(sel
, sel
, 0x3F, 0x17, 0, PPC_FLOAT_FSEL
);
1729 GEN_FLOAT_AB(sub
, 0x14, 0x000007C0);
1732 GEN_HANDLER(fsqrt
, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
)
1734 if (unlikely(!ctx
->fpu_enabled
)) {
1735 GEN_EXCP_NO_FP(ctx
);
1738 gen_op_reset_scrfx();
1739 gen_op_load_fpr_FT0(rB(ctx
->opcode
));
1741 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
1742 if (unlikely(Rc(ctx
->opcode
) != 0))
1746 GEN_HANDLER(fsqrts
, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
)
1748 if (unlikely(!ctx
->fpu_enabled
)) {
1749 GEN_EXCP_NO_FP(ctx
);
1752 gen_op_reset_scrfx();
1753 gen_op_load_fpr_FT0(rB(ctx
->opcode
));
1756 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
1757 if (unlikely(Rc(ctx
->opcode
) != 0))
1761 /*** Floating-Point multiply-and-add ***/
1762 /* fmadd - fmadds */
1763 GEN_FLOAT_ACB(madd
, 0x1D, PPC_FLOAT
);
1764 /* fmsub - fmsubs */
1765 GEN_FLOAT_ACB(msub
, 0x1C, PPC_FLOAT
);
1766 /* fnmadd - fnmadds */
1767 GEN_FLOAT_ACB(nmadd
, 0x1F, PPC_FLOAT
);
1768 /* fnmsub - fnmsubs */
1769 GEN_FLOAT_ACB(nmsub
, 0x1E, PPC_FLOAT
);
1771 /*** Floating-Point round & convert ***/
1773 GEN_FLOAT_B(ctiw
, 0x0E, 0x00, PPC_FLOAT
);
1775 GEN_FLOAT_B(ctiwz
, 0x0F, 0x00, PPC_FLOAT
);
1777 GEN_FLOAT_B(rsp
, 0x0C, 0x00, PPC_FLOAT
);
1778 #if defined(TARGET_PPC64)
1780 GEN_FLOAT_B(cfid
, 0x0E, 0x1A, PPC_64B
);
1782 GEN_FLOAT_B(ctid
, 0x0E, 0x19, PPC_64B
);
1784 GEN_FLOAT_B(ctidz
, 0x0F, 0x19, PPC_64B
);
1788 GEN_FLOAT_B(rin
, 0x08, 0x0C, PPC_FLOAT_EXT
);
1790 GEN_FLOAT_B(riz
, 0x08, 0x0D, PPC_FLOAT_EXT
);
1792 GEN_FLOAT_B(rip
, 0x08, 0x0E, PPC_FLOAT_EXT
);
1794 GEN_FLOAT_B(rim
, 0x08, 0x0F, PPC_FLOAT_EXT
);
1796 /*** Floating-Point compare ***/
1798 GEN_HANDLER(fcmpo
, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT
)
1800 if (unlikely(!ctx
->fpu_enabled
)) {
1801 GEN_EXCP_NO_FP(ctx
);
1804 gen_op_reset_scrfx();
1805 gen_op_load_fpr_FT0(rA(ctx
->opcode
));
1806 gen_op_load_fpr_FT1(rB(ctx
->opcode
));
1808 gen_op_store_T0_crf(crfD(ctx
->opcode
));
1812 GEN_HANDLER(fcmpu
, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT
)
1814 if (unlikely(!ctx
->fpu_enabled
)) {
1815 GEN_EXCP_NO_FP(ctx
);
1818 gen_op_reset_scrfx();
1819 gen_op_load_fpr_FT0(rA(ctx
->opcode
));
1820 gen_op_load_fpr_FT1(rB(ctx
->opcode
));
1822 gen_op_store_T0_crf(crfD(ctx
->opcode
));
1825 /*** Floating-point move ***/
1827 GEN_FLOAT_B(abs
, 0x08, 0x08, PPC_FLOAT
);
1830 GEN_HANDLER(fmr
, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT
)
1832 if (unlikely(!ctx
->fpu_enabled
)) {
1833 GEN_EXCP_NO_FP(ctx
);
1836 gen_op_reset_scrfx();
1837 gen_op_load_fpr_FT0(rB(ctx
->opcode
));
1838 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
1839 if (unlikely(Rc(ctx
->opcode
) != 0))
1844 GEN_FLOAT_B(nabs
, 0x08, 0x04, PPC_FLOAT
);
1846 GEN_FLOAT_B(neg
, 0x08, 0x01, PPC_FLOAT
);
1848 /*** Floating-Point status & ctrl register ***/
1850 GEN_HANDLER(mcrfs
, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT
)
1852 if (unlikely(!ctx
->fpu_enabled
)) {
1853 GEN_EXCP_NO_FP(ctx
);
1856 gen_op_load_fpscr_T0(crfS(ctx
->opcode
));
1857 gen_op_store_T0_crf(crfD(ctx
->opcode
));
1858 gen_op_clear_fpscr(crfS(ctx
->opcode
));
1862 GEN_HANDLER(mffs
, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT
)
1864 if (unlikely(!ctx
->fpu_enabled
)) {
1865 GEN_EXCP_NO_FP(ctx
);
1868 gen_op_load_fpscr();
1869 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
1870 if (unlikely(Rc(ctx
->opcode
) != 0))
1875 GEN_HANDLER(mtfsb0
, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT
)
1879 if (unlikely(!ctx
->fpu_enabled
)) {
1880 GEN_EXCP_NO_FP(ctx
);
1883 crb
= crbD(ctx
->opcode
) >> 2;
1884 gen_op_load_fpscr_T0(crb
);
1885 gen_op_andi_T0(~(1 << (crbD(ctx
->opcode
) & 0x03)));
1886 gen_op_store_T0_fpscr(crb
);
1887 if (unlikely(Rc(ctx
->opcode
) != 0))
1892 GEN_HANDLER(mtfsb1
, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT
)
1896 if (unlikely(!ctx
->fpu_enabled
)) {
1897 GEN_EXCP_NO_FP(ctx
);
1900 crb
= crbD(ctx
->opcode
) >> 2;
1901 gen_op_load_fpscr_T0(crb
);
1902 gen_op_ori(1 << (crbD(ctx
->opcode
) & 0x03));
1903 gen_op_store_T0_fpscr(crb
);
1904 if (unlikely(Rc(ctx
->opcode
) != 0))
1909 GEN_HANDLER(mtfsf
, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT
)
1911 if (unlikely(!ctx
->fpu_enabled
)) {
1912 GEN_EXCP_NO_FP(ctx
);
1915 gen_op_load_fpr_FT0(rB(ctx
->opcode
));
1916 gen_op_store_fpscr(FM(ctx
->opcode
));
1917 if (unlikely(Rc(ctx
->opcode
) != 0))
1922 GEN_HANDLER(mtfsfi
, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT
)
1924 if (unlikely(!ctx
->fpu_enabled
)) {
1925 GEN_EXCP_NO_FP(ctx
);
1928 gen_op_store_T0_fpscri(crbD(ctx
->opcode
) >> 2, FPIMM(ctx
->opcode
));
1929 if (unlikely(Rc(ctx
->opcode
) != 0))
1933 /*** Addressing modes ***/
1934 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
1935 static inline void gen_addr_imm_index (DisasContext
*ctx
, target_long maskl
)
1937 target_long simm
= SIMM(ctx
->opcode
);
1940 if (rA(ctx
->opcode
) == 0) {
1943 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1944 if (likely(simm
!= 0))
1947 #ifdef DEBUG_MEMORY_ACCESSES
1948 gen_op_print_mem_EA();
1952 static inline void gen_addr_reg_index (DisasContext
*ctx
)
1954 if (rA(ctx
->opcode
) == 0) {
1955 gen_op_load_gpr_T0(rB(ctx
->opcode
));
1957 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1958 gen_op_load_gpr_T1(rB(ctx
->opcode
));
1961 #ifdef DEBUG_MEMORY_ACCESSES
1962 gen_op_print_mem_EA();
1966 static inline void gen_addr_register (DisasContext
*ctx
)
1968 if (rA(ctx
->opcode
) == 0) {
1971 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1973 #ifdef DEBUG_MEMORY_ACCESSES
1974 gen_op_print_mem_EA();
1978 /*** Integer load ***/
1979 #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
1980 #if defined(CONFIG_USER_ONLY)
1981 #if defined(TARGET_PPC64)
1982 #define OP_LD_TABLE(width) \
1983 static GenOpFunc *gen_op_l##width[] = { \
1984 &gen_op_l##width##_raw, \
1985 &gen_op_l##width##_le_raw, \
1986 &gen_op_l##width##_64_raw, \
1987 &gen_op_l##width##_le_64_raw, \
1989 #define OP_ST_TABLE(width) \
1990 static GenOpFunc *gen_op_st##width[] = { \
1991 &gen_op_st##width##_raw, \
1992 &gen_op_st##width##_le_raw, \
1993 &gen_op_st##width##_64_raw, \
1994 &gen_op_st##width##_le_64_raw, \
1996 /* Byte access routine are endian safe */
1997 #define gen_op_stb_le_64_raw gen_op_stb_64_raw
1998 #define gen_op_lbz_le_64_raw gen_op_lbz_64_raw
2000 #define OP_LD_TABLE(width) \
2001 static GenOpFunc *gen_op_l##width[] = { \
2002 &gen_op_l##width##_raw, \
2003 &gen_op_l##width##_le_raw, \
2005 #define OP_ST_TABLE(width) \
2006 static GenOpFunc *gen_op_st##width[] = { \
2007 &gen_op_st##width##_raw, \
2008 &gen_op_st##width##_le_raw, \
2011 /* Byte access routine are endian safe */
2012 #define gen_op_stb_le_raw gen_op_stb_raw
2013 #define gen_op_lbz_le_raw gen_op_lbz_raw
2015 #if defined(TARGET_PPC64)
2016 #define OP_LD_TABLE(width) \
2017 static GenOpFunc *gen_op_l##width[] = { \
2018 &gen_op_l##width##_user, \
2019 &gen_op_l##width##_le_user, \
2020 &gen_op_l##width##_kernel, \
2021 &gen_op_l##width##_le_kernel, \
2022 &gen_op_l##width##_64_user, \
2023 &gen_op_l##width##_le_64_user, \
2024 &gen_op_l##width##_64_kernel, \
2025 &gen_op_l##width##_le_64_kernel, \
2027 #define OP_ST_TABLE(width) \
2028 static GenOpFunc *gen_op_st##width[] = { \
2029 &gen_op_st##width##_user, \
2030 &gen_op_st##width##_le_user, \
2031 &gen_op_st##width##_kernel, \
2032 &gen_op_st##width##_le_kernel, \
2033 &gen_op_st##width##_64_user, \
2034 &gen_op_st##width##_le_64_user, \
2035 &gen_op_st##width##_64_kernel, \
2036 &gen_op_st##width##_le_64_kernel, \
2038 /* Byte access routine are endian safe */
2039 #define gen_op_stb_le_64_user gen_op_stb_64_user
2040 #define gen_op_lbz_le_64_user gen_op_lbz_64_user
2041 #define gen_op_stb_le_64_kernel gen_op_stb_64_kernel
2042 #define gen_op_lbz_le_64_kernel gen_op_lbz_64_kernel
2044 #define OP_LD_TABLE(width) \
2045 static GenOpFunc *gen_op_l##width[] = { \
2046 &gen_op_l##width##_user, \
2047 &gen_op_l##width##_le_user, \
2048 &gen_op_l##width##_kernel, \
2049 &gen_op_l##width##_le_kernel, \
2051 #define OP_ST_TABLE(width) \
2052 static GenOpFunc *gen_op_st##width[] = { \
2053 &gen_op_st##width##_user, \
2054 &gen_op_st##width##_le_user, \
2055 &gen_op_st##width##_kernel, \
2056 &gen_op_st##width##_le_kernel, \
2059 /* Byte access routine are endian safe */
2060 #define gen_op_stb_le_user gen_op_stb_user
2061 #define gen_op_lbz_le_user gen_op_lbz_user
2062 #define gen_op_stb_le_kernel gen_op_stb_kernel
2063 #define gen_op_lbz_le_kernel gen_op_lbz_kernel
2066 #define GEN_LD(width, opc, type) \
2067 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2069 gen_addr_imm_index(ctx, 0); \
2070 op_ldst(l##width); \
2071 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2074 #define GEN_LDU(width, opc, type) \
2075 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2077 if (unlikely(rA(ctx->opcode) == 0 || \
2078 rA(ctx->opcode) == rD(ctx->opcode))) { \
2079 GEN_EXCP_INVAL(ctx); \
2082 if (type == PPC_64B) \
2083 gen_addr_imm_index(ctx, 0x03); \
2085 gen_addr_imm_index(ctx, 0); \
2086 op_ldst(l##width); \
2087 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2088 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2091 #define GEN_LDUX(width, opc2, opc3, type) \
2092 GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2094 if (unlikely(rA(ctx->opcode) == 0 || \
2095 rA(ctx->opcode) == rD(ctx->opcode))) { \
2096 GEN_EXCP_INVAL(ctx); \
2099 gen_addr_reg_index(ctx); \
2100 op_ldst(l##width); \
2101 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2102 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2105 #define GEN_LDX(width, opc2, opc3, type) \
2106 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2108 gen_addr_reg_index(ctx); \
2109 op_ldst(l##width); \
2110 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2113 #define GEN_LDS(width, op, type) \
2114 OP_LD_TABLE(width); \
2115 GEN_LD(width, op | 0x20, type); \
2116 GEN_LDU(width, op | 0x21, type); \
2117 GEN_LDUX(width, 0x17, op | 0x01, type); \
2118 GEN_LDX(width, 0x17, op | 0x00, type)
2120 /* lbz lbzu lbzux lbzx */
2121 GEN_LDS(bz
, 0x02, PPC_INTEGER
);
2122 /* lha lhau lhaux lhax */
2123 GEN_LDS(ha
, 0x0A, PPC_INTEGER
);
2124 /* lhz lhzu lhzux lhzx */
2125 GEN_LDS(hz
, 0x08, PPC_INTEGER
);
2126 /* lwz lwzu lwzux lwzx */
2127 GEN_LDS(wz
, 0x00, PPC_INTEGER
);
2128 #if defined(TARGET_PPC64)
2132 GEN_LDUX(wa
, 0x15, 0x0B, PPC_64B
);
2134 GEN_LDX(wa
, 0x15, 0x0A, PPC_64B
);
2136 GEN_LDUX(d
, 0x15, 0x01, PPC_64B
);
2138 GEN_LDX(d
, 0x15, 0x00, PPC_64B
);
2139 GEN_HANDLER(ld
, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B
)
2141 if (Rc(ctx
->opcode
)) {
2142 if (unlikely(rA(ctx
->opcode
) == 0 ||
2143 rA(ctx
->opcode
) == rD(ctx
->opcode
))) {
2144 GEN_EXCP_INVAL(ctx
);
2148 gen_addr_imm_index(ctx
, 0x03);
2149 if (ctx
->opcode
& 0x02) {
2150 /* lwa (lwau is undefined) */
2156 gen_op_store_T1_gpr(rD(ctx
->opcode
));
2157 if (Rc(ctx
->opcode
))
2158 gen_op_store_T0_gpr(rA(ctx
->opcode
));
2161 GEN_HANDLER(lq
, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX
)
2163 #if defined(CONFIG_USER_ONLY)
2164 GEN_EXCP_PRIVOPC(ctx
);
2168 /* Restore CPU state */
2169 if (unlikely(ctx
->supervisor
== 0)) {
2170 GEN_EXCP_PRIVOPC(ctx
);
2173 ra
= rA(ctx
->opcode
);
2174 rd
= rD(ctx
->opcode
);
2175 if (unlikely((rd
& 1) || rd
== ra
)) {
2176 GEN_EXCP_INVAL(ctx
);
2179 if (unlikely(ctx
->mem_idx
& 1)) {
2180 /* Little-endian mode is not handled */
2181 GEN_EXCP(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
2184 gen_addr_imm_index(ctx
, 0x0F);
2186 gen_op_store_T1_gpr(rd
);
2189 gen_op_store_T1_gpr(rd
+ 1);
2194 /*** Integer store ***/
2195 #define GEN_ST(width, opc, type) \
2196 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2198 gen_addr_imm_index(ctx, 0); \
2199 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2200 op_ldst(st##width); \
2203 #define GEN_STU(width, opc, type) \
2204 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2206 if (unlikely(rA(ctx->opcode) == 0)) { \
2207 GEN_EXCP_INVAL(ctx); \
2210 if (type == PPC_64B) \
2211 gen_addr_imm_index(ctx, 0x03); \
2213 gen_addr_imm_index(ctx, 0); \
2214 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2215 op_ldst(st##width); \
2216 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2219 #define GEN_STUX(width, opc2, opc3, type) \
2220 GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2222 if (unlikely(rA(ctx->opcode) == 0)) { \
2223 GEN_EXCP_INVAL(ctx); \
2226 gen_addr_reg_index(ctx); \
2227 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2228 op_ldst(st##width); \
2229 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2232 #define GEN_STX(width, opc2, opc3, type) \
2233 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2235 gen_addr_reg_index(ctx); \
2236 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2237 op_ldst(st##width); \
2240 #define GEN_STS(width, op, type) \
2241 OP_ST_TABLE(width); \
2242 GEN_ST(width, op | 0x20, type); \
2243 GEN_STU(width, op | 0x21, type); \
2244 GEN_STUX(width, 0x17, op | 0x01, type); \
2245 GEN_STX(width, 0x17, op | 0x00, type)
2247 /* stb stbu stbux stbx */
2248 GEN_STS(b
, 0x06, PPC_INTEGER
);
2249 /* sth sthu sthux sthx */
2250 GEN_STS(h
, 0x0C, PPC_INTEGER
);
2251 /* stw stwu stwux stwx */
2252 GEN_STS(w
, 0x04, PPC_INTEGER
);
2253 #if defined(TARGET_PPC64)
2255 GEN_STUX(d
, 0x15, 0x05, PPC_64B
);
2256 GEN_STX(d
, 0x15, 0x04, PPC_64B
);
2257 GEN_HANDLER(std
, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B
)
2261 rs
= rS(ctx
->opcode
);
2262 if ((ctx
->opcode
& 0x3) == 0x2) {
2263 #if defined(CONFIG_USER_ONLY)
2264 GEN_EXCP_PRIVOPC(ctx
);
2267 if (unlikely(ctx
->supervisor
== 0)) {
2268 GEN_EXCP_PRIVOPC(ctx
);
2271 if (unlikely(rs
& 1)) {
2272 GEN_EXCP_INVAL(ctx
);
2275 if (unlikely(ctx
->mem_idx
& 1)) {
2276 /* Little-endian mode is not handled */
2277 GEN_EXCP(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
2280 gen_addr_imm_index(ctx
, 0x03);
2281 gen_op_load_gpr_T1(rs
);
2284 gen_op_load_gpr_T1(rs
+ 1);
2289 if (Rc(ctx
->opcode
)) {
2290 if (unlikely(rA(ctx
->opcode
) == 0)) {
2291 GEN_EXCP_INVAL(ctx
);
2295 gen_addr_imm_index(ctx
, 0x03);
2296 gen_op_load_gpr_T1(rs
);
2298 if (Rc(ctx
->opcode
))
2299 gen_op_store_T0_gpr(rA(ctx
->opcode
));
2303 /*** Integer load and store with byte reverse ***/
2306 GEN_LDX(hbr
, 0x16, 0x18, PPC_INTEGER
);
2309 GEN_LDX(wbr
, 0x16, 0x10, PPC_INTEGER
);
2312 GEN_STX(hbr
, 0x16, 0x1C, PPC_INTEGER
);
2315 GEN_STX(wbr
, 0x16, 0x14, PPC_INTEGER
);
2317 /*** Integer load and store multiple ***/
2318 #define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
2319 #if defined(TARGET_PPC64)
2320 #if defined(CONFIG_USER_ONLY)
2321 static GenOpFunc1
*gen_op_lmw
[] = {
2325 &gen_op_lmw_le_64_raw
,
2327 static GenOpFunc1
*gen_op_stmw
[] = {
2328 &gen_op_stmw_64_raw
,
2329 &gen_op_stmw_le_64_raw
,
2332 static GenOpFunc1
*gen_op_lmw
[] = {
2334 &gen_op_lmw_le_user
,
2336 &gen_op_lmw_le_kernel
,
2337 &gen_op_lmw_64_user
,
2338 &gen_op_lmw_le_64_user
,
2339 &gen_op_lmw_64_kernel
,
2340 &gen_op_lmw_le_64_kernel
,
2342 static GenOpFunc1
*gen_op_stmw
[] = {
2344 &gen_op_stmw_le_user
,
2345 &gen_op_stmw_kernel
,
2346 &gen_op_stmw_le_kernel
,
2347 &gen_op_stmw_64_user
,
2348 &gen_op_stmw_le_64_user
,
2349 &gen_op_stmw_64_kernel
,
2350 &gen_op_stmw_le_64_kernel
,
2354 #if defined(CONFIG_USER_ONLY)
2355 static GenOpFunc1
*gen_op_lmw
[] = {
2359 static GenOpFunc1
*gen_op_stmw
[] = {
2361 &gen_op_stmw_le_raw
,
2364 static GenOpFunc1
*gen_op_lmw
[] = {
2366 &gen_op_lmw_le_user
,
2368 &gen_op_lmw_le_kernel
,
2370 static GenOpFunc1
*gen_op_stmw
[] = {
2372 &gen_op_stmw_le_user
,
2373 &gen_op_stmw_kernel
,
2374 &gen_op_stmw_le_kernel
,
2380 GEN_HANDLER(lmw
, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
2382 /* NIP cannot be restored if the memory exception comes from an helper */
2383 gen_update_nip(ctx
, ctx
->nip
- 4);
2384 gen_addr_imm_index(ctx
, 0);
2385 op_ldstm(lmw
, rD(ctx
->opcode
));
2389 GEN_HANDLER(stmw
, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
2391 /* NIP cannot be restored if the memory exception comes from an helper */
2392 gen_update_nip(ctx
, ctx
->nip
- 4);
2393 gen_addr_imm_index(ctx
, 0);
2394 op_ldstm(stmw
, rS(ctx
->opcode
));
2397 /*** Integer load and store strings ***/
2398 #define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
2399 #define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
2400 #if defined(TARGET_PPC64)
2401 #if defined(CONFIG_USER_ONLY)
2402 static GenOpFunc1
*gen_op_lswi
[] = {
2404 &gen_op_lswi_le_raw
,
2405 &gen_op_lswi_64_raw
,
2406 &gen_op_lswi_le_64_raw
,
2408 static GenOpFunc3
*gen_op_lswx
[] = {
2410 &gen_op_lswx_le_raw
,
2411 &gen_op_lswx_64_raw
,
2412 &gen_op_lswx_le_64_raw
,
2414 static GenOpFunc1
*gen_op_stsw
[] = {
2416 &gen_op_stsw_le_raw
,
2417 &gen_op_stsw_64_raw
,
2418 &gen_op_stsw_le_64_raw
,
2421 static GenOpFunc1
*gen_op_lswi
[] = {
2423 &gen_op_lswi_le_user
,
2424 &gen_op_lswi_kernel
,
2425 &gen_op_lswi_le_kernel
,
2426 &gen_op_lswi_64_user
,
2427 &gen_op_lswi_le_64_user
,
2428 &gen_op_lswi_64_kernel
,
2429 &gen_op_lswi_le_64_kernel
,
2431 static GenOpFunc3
*gen_op_lswx
[] = {
2433 &gen_op_lswx_le_user
,
2434 &gen_op_lswx_kernel
,
2435 &gen_op_lswx_le_kernel
,
2436 &gen_op_lswx_64_user
,
2437 &gen_op_lswx_le_64_user
,
2438 &gen_op_lswx_64_kernel
,
2439 &gen_op_lswx_le_64_kernel
,
2441 static GenOpFunc1
*gen_op_stsw
[] = {
2443 &gen_op_stsw_le_user
,
2444 &gen_op_stsw_kernel
,
2445 &gen_op_stsw_le_kernel
,
2446 &gen_op_stsw_64_user
,
2447 &gen_op_stsw_le_64_user
,
2448 &gen_op_stsw_64_kernel
,
2449 &gen_op_stsw_le_64_kernel
,
2453 #if defined(CONFIG_USER_ONLY)
2454 static GenOpFunc1
*gen_op_lswi
[] = {
2456 &gen_op_lswi_le_raw
,
2458 static GenOpFunc3
*gen_op_lswx
[] = {
2460 &gen_op_lswx_le_raw
,
2462 static GenOpFunc1
*gen_op_stsw
[] = {
2464 &gen_op_stsw_le_raw
,
2467 static GenOpFunc1
*gen_op_lswi
[] = {
2469 &gen_op_lswi_le_user
,
2470 &gen_op_lswi_kernel
,
2471 &gen_op_lswi_le_kernel
,
2473 static GenOpFunc3
*gen_op_lswx
[] = {
2475 &gen_op_lswx_le_user
,
2476 &gen_op_lswx_kernel
,
2477 &gen_op_lswx_le_kernel
,
2479 static GenOpFunc1
*gen_op_stsw
[] = {
2481 &gen_op_stsw_le_user
,
2482 &gen_op_stsw_kernel
,
2483 &gen_op_stsw_le_kernel
,
2489 /* PowerPC32 specification says we must generate an exception if
2490 * rA is in the range of registers to be loaded.
2491 * In an other hand, IBM says this is valid, but rA won't be loaded.
2492 * For now, I'll follow the spec...
2494 GEN_HANDLER(lswi
, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER
)
2496 int nb
= NB(ctx
->opcode
);
2497 int start
= rD(ctx
->opcode
);
2498 int ra
= rA(ctx
->opcode
);
2504 if (unlikely(((start
+ nr
) > 32 &&
2505 start
<= ra
&& (start
+ nr
- 32) > ra
) ||
2506 ((start
+ nr
) <= 32 && start
<= ra
&& (start
+ nr
) > ra
))) {
2507 GEN_EXCP(ctx
, POWERPC_EXCP_PROGRAM
,
2508 POWERPC_EXCP_INVAL
| POWERPC_EXCP_INVAL_LSWX
);
2511 /* NIP cannot be restored if the memory exception comes from an helper */
2512 gen_update_nip(ctx
, ctx
->nip
- 4);
2513 gen_addr_register(ctx
);
2515 op_ldsts(lswi
, start
);
2519 GEN_HANDLER(lswx
, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER
)
2521 int ra
= rA(ctx
->opcode
);
2522 int rb
= rB(ctx
->opcode
);
2524 /* NIP cannot be restored if the memory exception comes from an helper */
2525 gen_update_nip(ctx
, ctx
->nip
- 4);
2526 gen_addr_reg_index(ctx
);
2530 gen_op_load_xer_bc();
2531 op_ldstsx(lswx
, rD(ctx
->opcode
), ra
, rb
);
2535 GEN_HANDLER(stswi
, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER
)
2537 int nb
= NB(ctx
->opcode
);
2539 /* NIP cannot be restored if the memory exception comes from an helper */
2540 gen_update_nip(ctx
, ctx
->nip
- 4);
2541 gen_addr_register(ctx
);
2545 op_ldsts(stsw
, rS(ctx
->opcode
));
2549 GEN_HANDLER(stswx
, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER
)
2551 /* NIP cannot be restored if the memory exception comes from an helper */
2552 gen_update_nip(ctx
, ctx
->nip
- 4);
2553 gen_addr_reg_index(ctx
);
2554 gen_op_load_xer_bc();
2555 op_ldsts(stsw
, rS(ctx
->opcode
));
2558 /*** Memory synchronisation ***/
2560 GEN_HANDLER(eieio
, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO
)
2565 GEN_HANDLER(isync
, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM
)
2570 #define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
2571 #define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
2572 #if defined(TARGET_PPC64)
2573 #if defined(CONFIG_USER_ONLY)
2574 static GenOpFunc
*gen_op_lwarx
[] = {
2576 &gen_op_lwarx_le_raw
,
2577 &gen_op_lwarx_64_raw
,
2578 &gen_op_lwarx_le_64_raw
,
2580 static GenOpFunc
*gen_op_stwcx
[] = {
2582 &gen_op_stwcx_le_raw
,
2583 &gen_op_stwcx_64_raw
,
2584 &gen_op_stwcx_le_64_raw
,
2587 static GenOpFunc
*gen_op_lwarx
[] = {
2589 &gen_op_lwarx_le_user
,
2590 &gen_op_lwarx_kernel
,
2591 &gen_op_lwarx_le_kernel
,
2592 &gen_op_lwarx_64_user
,
2593 &gen_op_lwarx_le_64_user
,
2594 &gen_op_lwarx_64_kernel
,
2595 &gen_op_lwarx_le_64_kernel
,
2597 static GenOpFunc
*gen_op_stwcx
[] = {
2599 &gen_op_stwcx_le_user
,
2600 &gen_op_stwcx_kernel
,
2601 &gen_op_stwcx_le_kernel
,
2602 &gen_op_stwcx_64_user
,
2603 &gen_op_stwcx_le_64_user
,
2604 &gen_op_stwcx_64_kernel
,
2605 &gen_op_stwcx_le_64_kernel
,
2609 #if defined(CONFIG_USER_ONLY)
2610 static GenOpFunc
*gen_op_lwarx
[] = {
2612 &gen_op_lwarx_le_raw
,
2614 static GenOpFunc
*gen_op_stwcx
[] = {
2616 &gen_op_stwcx_le_raw
,
2619 static GenOpFunc
*gen_op_lwarx
[] = {
2621 &gen_op_lwarx_le_user
,
2622 &gen_op_lwarx_kernel
,
2623 &gen_op_lwarx_le_kernel
,
2625 static GenOpFunc
*gen_op_stwcx
[] = {
2627 &gen_op_stwcx_le_user
,
2628 &gen_op_stwcx_kernel
,
2629 &gen_op_stwcx_le_kernel
,
2635 GEN_HANDLER(lwarx
, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES
)
2637 gen_addr_reg_index(ctx
);
2639 gen_op_store_T1_gpr(rD(ctx
->opcode
));
2643 GEN_HANDLER(stwcx_
, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES
)
2645 gen_addr_reg_index(ctx
);
2646 gen_op_load_gpr_T1(rS(ctx
->opcode
));
2650 #if defined(TARGET_PPC64)
2651 #define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
2652 #define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
2653 #if defined(CONFIG_USER_ONLY)
2654 static GenOpFunc
*gen_op_ldarx
[] = {
2656 &gen_op_ldarx_le_raw
,
2657 &gen_op_ldarx_64_raw
,
2658 &gen_op_ldarx_le_64_raw
,
2660 static GenOpFunc
*gen_op_stdcx
[] = {
2662 &gen_op_stdcx_le_raw
,
2663 &gen_op_stdcx_64_raw
,
2664 &gen_op_stdcx_le_64_raw
,
2667 static GenOpFunc
*gen_op_ldarx
[] = {
2669 &gen_op_ldarx_le_user
,
2670 &gen_op_ldarx_kernel
,
2671 &gen_op_ldarx_le_kernel
,
2672 &gen_op_ldarx_64_user
,
2673 &gen_op_ldarx_le_64_user
,
2674 &gen_op_ldarx_64_kernel
,
2675 &gen_op_ldarx_le_64_kernel
,
2677 static GenOpFunc
*gen_op_stdcx
[] = {
2679 &gen_op_stdcx_le_user
,
2680 &gen_op_stdcx_kernel
,
2681 &gen_op_stdcx_le_kernel
,
2682 &gen_op_stdcx_64_user
,
2683 &gen_op_stdcx_le_64_user
,
2684 &gen_op_stdcx_64_kernel
,
2685 &gen_op_stdcx_le_64_kernel
,
2690 GEN_HANDLER(ldarx
, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B
)
2692 gen_addr_reg_index(ctx
);
2694 gen_op_store_T1_gpr(rD(ctx
->opcode
));
2698 GEN_HANDLER(stdcx_
, 0x1F, 0x16, 0x06, 0x00000000, PPC_64B
)
2700 gen_addr_reg_index(ctx
);
2701 gen_op_load_gpr_T1(rS(ctx
->opcode
));
2704 #endif /* defined(TARGET_PPC64) */
2707 GEN_HANDLER(sync
, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC
)
2712 GEN_HANDLER(wait
, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT
)
2714 /* Stop translation, as the CPU is supposed to sleep from now */
2716 GEN_EXCP(ctx
, EXCP_HLT
, 1);
2719 /*** Floating-point load ***/
2720 #define GEN_LDF(width, opc, type) \
2721 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2723 if (unlikely(!ctx->fpu_enabled)) { \
2724 GEN_EXCP_NO_FP(ctx); \
2727 gen_addr_imm_index(ctx, 0); \
2728 op_ldst(l##width); \
2729 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2732 #define GEN_LDUF(width, opc, type) \
2733 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2735 if (unlikely(!ctx->fpu_enabled)) { \
2736 GEN_EXCP_NO_FP(ctx); \
2739 if (unlikely(rA(ctx->opcode) == 0)) { \
2740 GEN_EXCP_INVAL(ctx); \
2743 gen_addr_imm_index(ctx, 0); \
2744 op_ldst(l##width); \
2745 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2746 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2749 #define GEN_LDUXF(width, opc, type) \
2750 GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
2752 if (unlikely(!ctx->fpu_enabled)) { \
2753 GEN_EXCP_NO_FP(ctx); \
2756 if (unlikely(rA(ctx->opcode) == 0)) { \
2757 GEN_EXCP_INVAL(ctx); \
2760 gen_addr_reg_index(ctx); \
2761 op_ldst(l##width); \
2762 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2763 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2766 #define GEN_LDXF(width, opc2, opc3, type) \
2767 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2769 if (unlikely(!ctx->fpu_enabled)) { \
2770 GEN_EXCP_NO_FP(ctx); \
2773 gen_addr_reg_index(ctx); \
2774 op_ldst(l##width); \
2775 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2778 #define GEN_LDFS(width, op, type) \
2779 OP_LD_TABLE(width); \
2780 GEN_LDF(width, op | 0x20, type); \
2781 GEN_LDUF(width, op | 0x21, type); \
2782 GEN_LDUXF(width, op | 0x01, type); \
2783 GEN_LDXF(width, 0x17, op | 0x00, type)
2785 /* lfd lfdu lfdux lfdx */
2786 GEN_LDFS(fd
, 0x12, PPC_FLOAT
);
2787 /* lfs lfsu lfsux lfsx */
2788 GEN_LDFS(fs
, 0x10, PPC_FLOAT
);
2790 /*** Floating-point store ***/
2791 #define GEN_STF(width, opc, type) \
2792 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2794 if (unlikely(!ctx->fpu_enabled)) { \
2795 GEN_EXCP_NO_FP(ctx); \
2798 gen_addr_imm_index(ctx, 0); \
2799 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2800 op_ldst(st##width); \
2803 #define GEN_STUF(width, opc, type) \
2804 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2806 if (unlikely(!ctx->fpu_enabled)) { \
2807 GEN_EXCP_NO_FP(ctx); \
2810 if (unlikely(rA(ctx->opcode) == 0)) { \
2811 GEN_EXCP_INVAL(ctx); \
2814 gen_addr_imm_index(ctx, 0); \
2815 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2816 op_ldst(st##width); \
2817 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2820 #define GEN_STUXF(width, opc, type) \
2821 GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
2823 if (unlikely(!ctx->fpu_enabled)) { \
2824 GEN_EXCP_NO_FP(ctx); \
2827 if (unlikely(rA(ctx->opcode) == 0)) { \
2828 GEN_EXCP_INVAL(ctx); \
2831 gen_addr_reg_index(ctx); \
2832 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2833 op_ldst(st##width); \
2834 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2837 #define GEN_STXF(width, opc2, opc3, type) \
2838 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2840 if (unlikely(!ctx->fpu_enabled)) { \
2841 GEN_EXCP_NO_FP(ctx); \
2844 gen_addr_reg_index(ctx); \
2845 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2846 op_ldst(st##width); \
2849 #define GEN_STFS(width, op, type) \
2850 OP_ST_TABLE(width); \
2851 GEN_STF(width, op | 0x20, type); \
2852 GEN_STUF(width, op | 0x21, type); \
2853 GEN_STUXF(width, op | 0x01, type); \
2854 GEN_STXF(width, 0x17, op | 0x00, type)
2856 /* stfd stfdu stfdux stfdx */
2857 GEN_STFS(fd
, 0x16, PPC_FLOAT
);
2858 /* stfs stfsu stfsux stfsx */
2859 GEN_STFS(fs
, 0x14, PPC_FLOAT
);
2864 GEN_STXF(fiwx
, 0x17, 0x1E, PPC_FLOAT_STFIWX
);
2867 static inline void gen_goto_tb (DisasContext
*ctx
, int n
, target_ulong dest
)
2869 TranslationBlock
*tb
;
2871 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
2873 gen_op_goto_tb0(TBPARAM(tb
));
2875 gen_op_goto_tb1(TBPARAM(tb
));
2877 #if defined(TARGET_PPC64)
2883 gen_op_set_T0((long)tb
+ n
);
2884 if (ctx
->singlestep_enabled
)
2889 #if defined(TARGET_PPC64)
2896 if (ctx
->singlestep_enabled
)
2902 static inline void gen_setlr (DisasContext
*ctx
, target_ulong nip
)
2904 #if defined(TARGET_PPC64)
2905 if (ctx
->sf_mode
!= 0 && (nip
>> 32))
2906 gen_op_setlr_64(ctx
->nip
>> 32, ctx
->nip
);
2909 gen_op_setlr(ctx
->nip
);
2913 GEN_HANDLER(b
, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW
)
2915 target_ulong li
, target
;
2917 /* sign extend LI */
2918 #if defined(TARGET_PPC64)
2920 li
= ((int64_t)LI(ctx
->opcode
) << 38) >> 38;
2923 li
= ((int32_t)LI(ctx
->opcode
) << 6) >> 6;
2924 if (likely(AA(ctx
->opcode
) == 0))
2925 target
= ctx
->nip
+ li
- 4;
2928 #if defined(TARGET_PPC64)
2930 target
= (uint32_t)target
;
2932 if (LK(ctx
->opcode
))
2933 gen_setlr(ctx
, ctx
->nip
);
2934 gen_goto_tb(ctx
, 0, target
);
2935 ctx
->exception
= POWERPC_EXCP_BRANCH
;
2942 static inline void gen_bcond (DisasContext
*ctx
, int type
)
2944 target_ulong target
= 0;
2946 uint32_t bo
= BO(ctx
->opcode
);
2947 uint32_t bi
= BI(ctx
->opcode
);
2950 if ((bo
& 0x4) == 0)
2954 li
= (target_long
)((int16_t)(BD(ctx
->opcode
)));
2955 if (likely(AA(ctx
->opcode
) == 0)) {
2956 target
= ctx
->nip
+ li
- 4;
2960 #if defined(TARGET_PPC64)
2962 target
= (uint32_t)target
;
2966 gen_op_movl_T1_ctr();
2970 gen_op_movl_T1_lr();
2973 if (LK(ctx
->opcode
))
2974 gen_setlr(ctx
, ctx
->nip
);
2976 /* No CR condition */
2979 #if defined(TARGET_PPC64)
2981 gen_op_test_ctr_64();
2987 #if defined(TARGET_PPC64)
2989 gen_op_test_ctrz_64();
2997 if (type
== BCOND_IM
) {
2998 gen_goto_tb(ctx
, 0, target
);
3001 #if defined(TARGET_PPC64)
3013 mask
= 1 << (3 - (bi
& 0x03));
3014 gen_op_load_crf_T0(bi
>> 2);
3018 #if defined(TARGET_PPC64)
3020 gen_op_test_ctr_true_64(mask
);
3023 gen_op_test_ctr_true(mask
);
3026 #if defined(TARGET_PPC64)
3028 gen_op_test_ctrz_true_64(mask
);
3031 gen_op_test_ctrz_true(mask
);
3036 gen_op_test_true(mask
);
3042 #if defined(TARGET_PPC64)
3044 gen_op_test_ctr_false_64(mask
);
3047 gen_op_test_ctr_false(mask
);
3050 #if defined(TARGET_PPC64)
3052 gen_op_test_ctrz_false_64(mask
);
3055 gen_op_test_ctrz_false(mask
);
3060 gen_op_test_false(mask
);
3065 if (type
== BCOND_IM
) {
3066 int l1
= gen_new_label();
3068 gen_goto_tb(ctx
, 0, target
);
3070 gen_goto_tb(ctx
, 1, ctx
->nip
);
3072 #if defined(TARGET_PPC64)
3074 gen_op_btest_T1_64(ctx
->nip
>> 32, ctx
->nip
);
3077 gen_op_btest_T1(ctx
->nip
);
3080 if (ctx
->singlestep_enabled
)
3085 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3088 GEN_HANDLER(bc
, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW
)
3090 gen_bcond(ctx
, BCOND_IM
);
3093 GEN_HANDLER(bcctr
, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW
)
3095 gen_bcond(ctx
, BCOND_CTR
);
3098 GEN_HANDLER(bclr
, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW
)
3100 gen_bcond(ctx
, BCOND_LR
);
3103 /*** Condition register logical ***/
3104 #define GEN_CRLOGIC(op, opc) \
3105 GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3107 gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
3108 gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03)); \
3109 gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
3110 gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03)); \
3112 gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
3113 gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))), \
3114 3 - (crbD(ctx->opcode) & 0x03)); \
3115 gen_op_store_T1_crf(crbD(ctx->opcode) >> 2); \
3119 GEN_CRLOGIC(and, 0x08);
3121 GEN_CRLOGIC(andc
, 0x04);
3123 GEN_CRLOGIC(eqv
, 0x09);
3125 GEN_CRLOGIC(nand
, 0x07);
3127 GEN_CRLOGIC(nor
, 0x01);
3129 GEN_CRLOGIC(or, 0x0E);
3131 GEN_CRLOGIC(orc
, 0x0D);
3133 GEN_CRLOGIC(xor, 0x06);
3135 GEN_HANDLER(mcrf
, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER
)
3137 gen_op_load_crf_T0(crfS(ctx
->opcode
));
3138 gen_op_store_T0_crf(crfD(ctx
->opcode
));
3141 /*** System linkage ***/
3142 /* rfi (supervisor only) */
3143 GEN_HANDLER(rfi
, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW
)
3145 #if defined(CONFIG_USER_ONLY)
3146 GEN_EXCP_PRIVOPC(ctx
);
3148 /* Restore CPU state */
3149 if (unlikely(!ctx
->supervisor
)) {
3150 GEN_EXCP_PRIVOPC(ctx
);
3158 #if defined(TARGET_PPC64)
3159 GEN_HANDLER(rfid
, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B
)
3161 #if defined(CONFIG_USER_ONLY)
3162 GEN_EXCP_PRIVOPC(ctx
);
3164 /* Restore CPU state */
3165 if (unlikely(!ctx
->supervisor
)) {
3166 GEN_EXCP_PRIVOPC(ctx
);
3175 #if defined(TARGET_PPC64H)
3176 GEN_HANDLER(hrfid
, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64B
)
3178 #if defined(CONFIG_USER_ONLY)
3179 GEN_EXCP_PRIVOPC(ctx
);
3181 /* Restore CPU state */
3182 if (unlikely(ctx
->supervisor
<= 1)) {
3183 GEN_EXCP_PRIVOPC(ctx
);
3193 GEN_HANDLER(sc
, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW
)
3197 lev
= (ctx
->opcode
>> 5) & 0x7F;
3198 #if defined(CONFIG_USER_ONLY)
3199 GEN_EXCP(ctx
, POWERPC_EXCP_SYSCALL_USER
, lev
);
3201 GEN_EXCP(ctx
, POWERPC_EXCP_SYSCALL
, lev
);
3207 GEN_HANDLER(tw
, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW
)
3209 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3210 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3211 /* Update the nip since this might generate a trap exception */
3212 gen_update_nip(ctx
, ctx
->nip
);
3213 gen_op_tw(TO(ctx
->opcode
));
3217 GEN_HANDLER(twi
, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW
)
3219 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3220 gen_set_T1(SIMM(ctx
->opcode
));
3221 /* Update the nip since this might generate a trap exception */
3222 gen_update_nip(ctx
, ctx
->nip
);
3223 gen_op_tw(TO(ctx
->opcode
));
3226 #if defined(TARGET_PPC64)
3228 GEN_HANDLER(td
, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B
)
3230 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3231 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3232 /* Update the nip since this might generate a trap exception */
3233 gen_update_nip(ctx
, ctx
->nip
);
3234 gen_op_td(TO(ctx
->opcode
));
3238 GEN_HANDLER(tdi
, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B
)
3240 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3241 gen_set_T1(SIMM(ctx
->opcode
));
3242 /* Update the nip since this might generate a trap exception */
3243 gen_update_nip(ctx
, ctx
->nip
);
3244 gen_op_td(TO(ctx
->opcode
));
3248 /*** Processor control ***/
3250 GEN_HANDLER(mcrxr
, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC
)
3252 gen_op_load_xer_cr();
3253 gen_op_store_T0_crf(crfD(ctx
->opcode
));
3254 gen_op_clear_xer_ov();
3255 gen_op_clear_xer_ca();
3259 GEN_HANDLER(mfcr
, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC
)
3263 if (likely(ctx
->opcode
& 0x00100000)) {
3264 crm
= CRM(ctx
->opcode
);
3265 if (likely((crm
^ (crm
- 1)) == 0)) {
3267 gen_op_load_cro(7 - crn
);
3272 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3276 GEN_HANDLER(mfmsr
, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC
)
3278 #if defined(CONFIG_USER_ONLY)
3279 GEN_EXCP_PRIVREG(ctx
);
3281 if (unlikely(!ctx
->supervisor
)) {
3282 GEN_EXCP_PRIVREG(ctx
);
3286 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3291 #define SPR_NOACCESS ((void *)(-1))
3293 static void spr_noaccess (void *opaque
, int sprn
)
3295 sprn
= ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
3296 printf("ERROR: try to access SPR %d !\n", sprn
);
3298 #define SPR_NOACCESS (&spr_noaccess)
3302 static inline void gen_op_mfspr (DisasContext
*ctx
)
3304 void (*read_cb
)(void *opaque
, int sprn
);
3305 uint32_t sprn
= SPR(ctx
->opcode
);
3307 #if !defined(CONFIG_USER_ONLY)
3308 #if defined(TARGET_PPC64H)
3309 if (ctx
->supervisor
== 2)
3310 read_cb
= ctx
->spr_cb
[sprn
].hea_read
;
3313 if (ctx
->supervisor
)
3314 read_cb
= ctx
->spr_cb
[sprn
].oea_read
;
3317 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
3318 if (likely(read_cb
!= NULL
)) {
3319 if (likely(read_cb
!= SPR_NOACCESS
)) {
3320 (*read_cb
)(ctx
, sprn
);
3321 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3323 /* Privilege exception */
3324 if (loglevel
!= 0) {
3325 fprintf(logfile
, "Trying to read privileged spr %d %03x\n",
3328 printf("Trying to read privileged spr %d %03x\n", sprn
, sprn
);
3329 GEN_EXCP_PRIVREG(ctx
);
3333 if (loglevel
!= 0) {
3334 fprintf(logfile
, "Trying to read invalid spr %d %03x\n",
3337 printf("Trying to read invalid spr %d %03x\n", sprn
, sprn
);
3338 GEN_EXCP(ctx
, POWERPC_EXCP_PROGRAM
,
3339 POWERPC_EXCP_INVAL
| POWERPC_EXCP_INVAL_SPR
);
3343 GEN_HANDLER(mfspr
, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC
)
3349 GEN_HANDLER(mftb
, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB
)
3355 GEN_HANDLER(mtcrf
, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC
)
3359 gen_op_load_gpr_T0(rS(ctx
->opcode
));
3360 crm
= CRM(ctx
->opcode
);
3361 if (likely((ctx
->opcode
& 0x00100000) || (crm
^ (crm
- 1)) == 0)) {
3363 gen_op_srli_T0(crn
* 4);
3364 gen_op_andi_T0(0xF);
3365 gen_op_store_cro(7 - crn
);
3367 gen_op_store_cr(crm
);
3372 #if defined(TARGET_PPC64)
3373 GEN_HANDLER(mtmsrd
, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B
)
3375 #if defined(CONFIG_USER_ONLY)
3376 GEN_EXCP_PRIVREG(ctx
);
3378 if (unlikely(!ctx
->supervisor
)) {
3379 GEN_EXCP_PRIVREG(ctx
);
3382 gen_op_load_gpr_T0(rS(ctx
->opcode
));
3383 if (ctx
->opcode
& 0x00010000) {
3384 /* Special form that does not need any synchronisation */
3385 gen_op_update_riee();
3387 /* XXX: we need to update nip before the store
3388 * if we enter power saving mode, we will exit the loop
3389 * directly from ppc_store_msr
3391 gen_update_nip(ctx
, ctx
->nip
);
3393 /* Must stop the translation as machine state (may have) changed */
3394 /* Note that mtmsr is not always defined as context-synchronizing */
3395 ctx
->exception
= POWERPC_EXCP_STOP
;
3401 GEN_HANDLER(mtmsr
, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC
)
3403 #if defined(CONFIG_USER_ONLY)
3404 GEN_EXCP_PRIVREG(ctx
);
3406 if (unlikely(!ctx
->supervisor
)) {
3407 GEN_EXCP_PRIVREG(ctx
);
3410 gen_op_load_gpr_T0(rS(ctx
->opcode
));
3411 if (ctx
->opcode
& 0x00010000) {
3412 /* Special form that does not need any synchronisation */
3413 gen_op_update_riee();
3415 /* XXX: we need to update nip before the store
3416 * if we enter power saving mode, we will exit the loop
3417 * directly from ppc_store_msr
3419 gen_update_nip(ctx
, ctx
->nip
);
3420 #if defined(TARGET_PPC64)
3422 gen_op_store_msr_32();
3426 /* Must stop the translation as machine state (may have) changed */
3427 /* Note that mtmsrd is not always defined as context-synchronizing */
3428 ctx
->exception
= POWERPC_EXCP_STOP
;
3434 GEN_HANDLER(mtspr
, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC
)
3436 void (*write_cb
)(void *opaque
, int sprn
);
3437 uint32_t sprn
= SPR(ctx
->opcode
);
3439 #if !defined(CONFIG_USER_ONLY)
3440 #if defined(TARGET_PPC64H)
3441 if (ctx
->supervisor
== 2)
3442 write_cb
= ctx
->spr_cb
[sprn
].hea_write
;
3445 if (ctx
->supervisor
)
3446 write_cb
= ctx
->spr_cb
[sprn
].oea_write
;
3449 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
3450 if (likely(write_cb
!= NULL
)) {
3451 if (likely(write_cb
!= SPR_NOACCESS
)) {
3452 gen_op_load_gpr_T0(rS(ctx
->opcode
));
3453 (*write_cb
)(ctx
, sprn
);
3455 /* Privilege exception */
3456 if (loglevel
!= 0) {
3457 fprintf(logfile
, "Trying to write privileged spr %d %03x\n",
3460 printf("Trying to write privileged spr %d %03x\n", sprn
, sprn
);
3461 GEN_EXCP_PRIVREG(ctx
);
3465 if (loglevel
!= 0) {
3466 fprintf(logfile
, "Trying to write invalid spr %d %03x\n",
3469 printf("Trying to write invalid spr %d %03x\n", sprn
, sprn
);
3470 GEN_EXCP(ctx
, POWERPC_EXCP_PROGRAM
,
3471 POWERPC_EXCP_INVAL
| POWERPC_EXCP_INVAL_SPR
);
3475 /*** Cache management ***/
3476 /* For now, all those will be implemented as nop:
3477 * this is valid, regarding the PowerPC specs...
3478 * We just have to flush tb while invalidating instruction cache lines...
3481 GEN_HANDLER(dcbf
, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE
)
3483 gen_addr_reg_index(ctx
);
3487 /* dcbi (Supervisor only) */
3488 GEN_HANDLER(dcbi
, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE
)
3490 #if defined(CONFIG_USER_ONLY)
3491 GEN_EXCP_PRIVOPC(ctx
);
3493 if (unlikely(!ctx
->supervisor
)) {
3494 GEN_EXCP_PRIVOPC(ctx
);
3497 gen_addr_reg_index(ctx
);
3498 /* XXX: specification says this should be treated as a store by the MMU */
3505 GEN_HANDLER(dcbst
, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE
)
3507 /* XXX: specification say this is treated as a load by the MMU */
3508 gen_addr_reg_index(ctx
);
3513 GEN_HANDLER(dcbt
, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE
)
3515 /* interpreted as no-op */
3516 /* XXX: specification say this is treated as a load by the MMU
3517 * but does not generate any exception
3522 GEN_HANDLER(dcbtst
, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE
)
3524 /* interpreted as no-op */
3525 /* XXX: specification say this is treated as a load by the MMU
3526 * but does not generate any exception
3531 #define op_dcbz() (*gen_op_dcbz[ctx->mem_idx])()
3532 #if defined(TARGET_PPC64)
3533 #if defined(CONFIG_USER_ONLY)
3534 static GenOpFunc
*gen_op_dcbz
[] = {
3537 &gen_op_dcbz_64_raw
,
3538 &gen_op_dcbz_64_raw
,
3541 static GenOpFunc
*gen_op_dcbz
[] = {
3544 &gen_op_dcbz_kernel
,
3545 &gen_op_dcbz_kernel
,
3546 &gen_op_dcbz_64_user
,
3547 &gen_op_dcbz_64_user
,
3548 &gen_op_dcbz_64_kernel
,
3549 &gen_op_dcbz_64_kernel
,
3553 #if defined(CONFIG_USER_ONLY)
3554 static GenOpFunc
*gen_op_dcbz
[] = {
3559 static GenOpFunc
*gen_op_dcbz
[] = {
3562 &gen_op_dcbz_kernel
,
3563 &gen_op_dcbz_kernel
,
3568 GEN_HANDLER(dcbz
, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE
)
3570 gen_addr_reg_index(ctx
);
3572 gen_op_check_reservation();
3576 #define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
3577 #if defined(TARGET_PPC64)
3578 #if defined(CONFIG_USER_ONLY)
3579 static GenOpFunc
*gen_op_icbi
[] = {
3582 &gen_op_icbi_64_raw
,
3583 &gen_op_icbi_64_raw
,
3586 static GenOpFunc
*gen_op_icbi
[] = {
3589 &gen_op_icbi_kernel
,
3590 &gen_op_icbi_kernel
,
3591 &gen_op_icbi_64_user
,
3592 &gen_op_icbi_64_user
,
3593 &gen_op_icbi_64_kernel
,
3594 &gen_op_icbi_64_kernel
,
3598 #if defined(CONFIG_USER_ONLY)
3599 static GenOpFunc
*gen_op_icbi
[] = {
3604 static GenOpFunc
*gen_op_icbi
[] = {
3607 &gen_op_icbi_kernel
,
3608 &gen_op_icbi_kernel
,
3613 GEN_HANDLER(icbi
, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE
)
3615 gen_addr_reg_index(ctx
);
3621 GEN_HANDLER(dcba
, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA
)
3623 /* interpreted as no-op */
3624 /* XXX: specification say this is treated as a store by the MMU
3625 * but does not generate any exception
3629 /*** Segment register manipulation ***/
3630 /* Supervisor only: */
3632 GEN_HANDLER(mfsr
, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT
)
3634 #if defined(CONFIG_USER_ONLY)
3635 GEN_EXCP_PRIVREG(ctx
);
3637 if (unlikely(!ctx
->supervisor
)) {
3638 GEN_EXCP_PRIVREG(ctx
);
3641 gen_op_set_T1(SR(ctx
->opcode
));
3643 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3648 GEN_HANDLER(mfsrin
, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT
)
3650 #if defined(CONFIG_USER_ONLY)
3651 GEN_EXCP_PRIVREG(ctx
);
3653 if (unlikely(!ctx
->supervisor
)) {
3654 GEN_EXCP_PRIVREG(ctx
);
3657 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3660 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3665 GEN_HANDLER(mtsr
, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT
)
3667 #if defined(CONFIG_USER_ONLY)
3668 GEN_EXCP_PRIVREG(ctx
);
3670 if (unlikely(!ctx
->supervisor
)) {
3671 GEN_EXCP_PRIVREG(ctx
);
3674 gen_op_load_gpr_T0(rS(ctx
->opcode
));
3675 gen_op_set_T1(SR(ctx
->opcode
));
3681 GEN_HANDLER(mtsrin
, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT
)
3683 #if defined(CONFIG_USER_ONLY)
3684 GEN_EXCP_PRIVREG(ctx
);
3686 if (unlikely(!ctx
->supervisor
)) {
3687 GEN_EXCP_PRIVREG(ctx
);
3690 gen_op_load_gpr_T0(rS(ctx
->opcode
));
3691 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3697 /*** Lookaside buffer management ***/
3698 /* Optional & supervisor only: */
3700 GEN_HANDLER(tlbia
, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA
)
3702 #if defined(CONFIG_USER_ONLY)
3703 GEN_EXCP_PRIVOPC(ctx
);
3705 if (unlikely(!ctx
->supervisor
)) {
3707 fprintf(logfile
, "%s: ! supervisor\n", __func__
);
3708 GEN_EXCP_PRIVOPC(ctx
);
3716 GEN_HANDLER(tlbie
, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE
)
3718 #if defined(CONFIG_USER_ONLY)
3719 GEN_EXCP_PRIVOPC(ctx
);
3721 if (unlikely(!ctx
->supervisor
)) {
3722 GEN_EXCP_PRIVOPC(ctx
);
3725 gen_op_load_gpr_T0(rB(ctx
->opcode
));
3726 #if defined(TARGET_PPC64)
3736 GEN_HANDLER(tlbsync
, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC
)
3738 #if defined(CONFIG_USER_ONLY)
3739 GEN_EXCP_PRIVOPC(ctx
);
3741 if (unlikely(!ctx
->supervisor
)) {
3742 GEN_EXCP_PRIVOPC(ctx
);
3745 /* This has no effect: it should ensure that all previous
3746 * tlbie have completed
3752 #if defined(TARGET_PPC64)
3754 GEN_HANDLER(slbia
, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI
)
3756 #if defined(CONFIG_USER_ONLY)
3757 GEN_EXCP_PRIVOPC(ctx
);
3759 if (unlikely(!ctx
->supervisor
)) {
3761 fprintf(logfile
, "%s: ! supervisor\n", __func__
);
3762 GEN_EXCP_PRIVOPC(ctx
);
3770 GEN_HANDLER(slbie
, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI
)
3772 #if defined(CONFIG_USER_ONLY)
3773 GEN_EXCP_PRIVOPC(ctx
);
3775 if (unlikely(!ctx
->supervisor
)) {
3776 GEN_EXCP_PRIVOPC(ctx
);
3779 gen_op_load_gpr_T0(rB(ctx
->opcode
));
3785 /*** External control ***/
3787 #define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
3788 #define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
3789 #if defined(TARGET_PPC64)
3790 #if defined(CONFIG_USER_ONLY)
3791 static GenOpFunc
*gen_op_eciwx
[] = {
3793 &gen_op_eciwx_le_raw
,
3794 &gen_op_eciwx_64_raw
,
3795 &gen_op_eciwx_le_64_raw
,
3797 static GenOpFunc
*gen_op_ecowx
[] = {
3799 &gen_op_ecowx_le_raw
,
3800 &gen_op_ecowx_64_raw
,
3801 &gen_op_ecowx_le_64_raw
,
3804 static GenOpFunc
*gen_op_eciwx
[] = {
3806 &gen_op_eciwx_le_user
,
3807 &gen_op_eciwx_kernel
,
3808 &gen_op_eciwx_le_kernel
,
3809 &gen_op_eciwx_64_user
,
3810 &gen_op_eciwx_le_64_user
,
3811 &gen_op_eciwx_64_kernel
,
3812 &gen_op_eciwx_le_64_kernel
,
3814 static GenOpFunc
*gen_op_ecowx
[] = {
3816 &gen_op_ecowx_le_user
,
3817 &gen_op_ecowx_kernel
,
3818 &gen_op_ecowx_le_kernel
,
3819 &gen_op_ecowx_64_user
,
3820 &gen_op_ecowx_le_64_user
,
3821 &gen_op_ecowx_64_kernel
,
3822 &gen_op_ecowx_le_64_kernel
,
3826 #if defined(CONFIG_USER_ONLY)
3827 static GenOpFunc
*gen_op_eciwx
[] = {
3829 &gen_op_eciwx_le_raw
,
3831 static GenOpFunc
*gen_op_ecowx
[] = {
3833 &gen_op_ecowx_le_raw
,
3836 static GenOpFunc
*gen_op_eciwx
[] = {
3838 &gen_op_eciwx_le_user
,
3839 &gen_op_eciwx_kernel
,
3840 &gen_op_eciwx_le_kernel
,
3842 static GenOpFunc
*gen_op_ecowx
[] = {
3844 &gen_op_ecowx_le_user
,
3845 &gen_op_ecowx_kernel
,
3846 &gen_op_ecowx_le_kernel
,
3852 GEN_HANDLER(eciwx
, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN
)
3854 /* Should check EAR[E] & alignment ! */
3855 gen_addr_reg_index(ctx
);
3857 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3861 GEN_HANDLER(ecowx
, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN
)
3863 /* Should check EAR[E] & alignment ! */
3864 gen_addr_reg_index(ctx
);
3865 gen_op_load_gpr_T1(rS(ctx
->opcode
));
3869 /* PowerPC 601 specific instructions */
3871 GEN_HANDLER(abs
, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR
)
3873 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3875 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3876 if (unlikely(Rc(ctx
->opcode
) != 0))
3881 GEN_HANDLER(abso
, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR
)
3883 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3884 gen_op_POWER_abso();
3885 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3886 if (unlikely(Rc(ctx
->opcode
) != 0))
3891 GEN_HANDLER(clcs
, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR
)
3893 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3894 gen_op_POWER_clcs();
3895 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3899 GEN_HANDLER(div
, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR
)
3901 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3902 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3904 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3905 if (unlikely(Rc(ctx
->opcode
) != 0))
3910 GEN_HANDLER(divo
, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR
)
3912 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3913 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3914 gen_op_POWER_divo();
3915 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3916 if (unlikely(Rc(ctx
->opcode
) != 0))
3921 GEN_HANDLER(divs
, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR
)
3923 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3924 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3925 gen_op_POWER_divs();
3926 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3927 if (unlikely(Rc(ctx
->opcode
) != 0))
3931 /* divso - divso. */
3932 GEN_HANDLER(divso
, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR
)
3934 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3935 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3936 gen_op_POWER_divso();
3937 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3938 if (unlikely(Rc(ctx
->opcode
) != 0))
3943 GEN_HANDLER(doz
, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR
)
3945 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3946 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3948 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3949 if (unlikely(Rc(ctx
->opcode
) != 0))
3954 GEN_HANDLER(dozo
, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR
)
3956 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3957 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3958 gen_op_POWER_dozo();
3959 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3960 if (unlikely(Rc(ctx
->opcode
) != 0))
3965 GEN_HANDLER(dozi
, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
)
3967 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3968 gen_op_set_T1(SIMM(ctx
->opcode
));
3970 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3973 /* As lscbx load from memory byte after byte, it's always endian safe */
3974 #define op_POWER_lscbx(start, ra, rb) \
3975 (*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
3976 #if defined(CONFIG_USER_ONLY)
3977 static GenOpFunc3
*gen_op_POWER_lscbx
[] = {
3978 &gen_op_POWER_lscbx_raw
,
3979 &gen_op_POWER_lscbx_raw
,
3982 static GenOpFunc3
*gen_op_POWER_lscbx
[] = {
3983 &gen_op_POWER_lscbx_user
,
3984 &gen_op_POWER_lscbx_user
,
3985 &gen_op_POWER_lscbx_kernel
,
3986 &gen_op_POWER_lscbx_kernel
,
3990 /* lscbx - lscbx. */
3991 GEN_HANDLER(lscbx
, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR
)
3993 int ra
= rA(ctx
->opcode
);
3994 int rb
= rB(ctx
->opcode
);
3996 gen_addr_reg_index(ctx
);
4000 /* NIP cannot be restored if the memory exception comes from an helper */
4001 gen_update_nip(ctx
, ctx
->nip
- 4);
4002 gen_op_load_xer_bc();
4003 gen_op_load_xer_cmp();
4004 op_POWER_lscbx(rD(ctx
->opcode
), ra
, rb
);
4005 gen_op_store_xer_bc();
4006 if (unlikely(Rc(ctx
->opcode
) != 0))
4010 /* maskg - maskg. */
4011 GEN_HANDLER(maskg
, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR
)
4013 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4014 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4015 gen_op_POWER_maskg();
4016 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4017 if (unlikely(Rc(ctx
->opcode
) != 0))
4021 /* maskir - maskir. */
4022 GEN_HANDLER(maskir
, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR
)
4024 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4025 gen_op_load_gpr_T1(rS(ctx
->opcode
));
4026 gen_op_load_gpr_T2(rB(ctx
->opcode
));
4027 gen_op_POWER_maskir();
4028 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4029 if (unlikely(Rc(ctx
->opcode
) != 0))
4034 GEN_HANDLER(mul
, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR
)
4036 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4037 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4039 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4040 if (unlikely(Rc(ctx
->opcode
) != 0))
4045 GEN_HANDLER(mulo
, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR
)
4047 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4048 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4049 gen_op_POWER_mulo();
4050 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4051 if (unlikely(Rc(ctx
->opcode
) != 0))
4056 GEN_HANDLER(nabs
, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR
)
4058 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4059 gen_op_POWER_nabs();
4060 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4061 if (unlikely(Rc(ctx
->opcode
) != 0))
4065 /* nabso - nabso. */
4066 GEN_HANDLER(nabso
, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR
)
4068 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4069 gen_op_POWER_nabso();
4070 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4071 if (unlikely(Rc(ctx
->opcode
) != 0))
4076 GEN_HANDLER(rlmi
, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
)
4080 mb
= MB(ctx
->opcode
);
4081 me
= ME(ctx
->opcode
);
4082 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4083 gen_op_load_gpr_T1(rA(ctx
->opcode
));
4084 gen_op_load_gpr_T2(rB(ctx
->opcode
));
4085 gen_op_POWER_rlmi(MASK(mb
, me
), ~MASK(mb
, me
));
4086 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4087 if (unlikely(Rc(ctx
->opcode
) != 0))
4092 GEN_HANDLER(rrib
, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR
)
4094 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4095 gen_op_load_gpr_T1(rA(ctx
->opcode
));
4096 gen_op_load_gpr_T2(rB(ctx
->opcode
));
4097 gen_op_POWER_rrib();
4098 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4099 if (unlikely(Rc(ctx
->opcode
) != 0))
4104 GEN_HANDLER(sle
, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR
)
4106 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4107 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4109 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4110 if (unlikely(Rc(ctx
->opcode
) != 0))
4115 GEN_HANDLER(sleq
, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR
)
4117 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4118 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4119 gen_op_POWER_sleq();
4120 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4121 if (unlikely(Rc(ctx
->opcode
) != 0))
4126 GEN_HANDLER(sliq
, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR
)
4128 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4129 gen_op_set_T1(SH(ctx
->opcode
));
4131 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4132 if (unlikely(Rc(ctx
->opcode
) != 0))
4136 /* slliq - slliq. */
4137 GEN_HANDLER(slliq
, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR
)
4139 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4140 gen_op_set_T1(SH(ctx
->opcode
));
4141 gen_op_POWER_sleq();
4142 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4143 if (unlikely(Rc(ctx
->opcode
) != 0))
4148 GEN_HANDLER(sllq
, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR
)
4150 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4151 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4152 gen_op_POWER_sllq();
4153 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4154 if (unlikely(Rc(ctx
->opcode
) != 0))
4159 GEN_HANDLER(slq
, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR
)
4161 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4162 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4164 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4165 if (unlikely(Rc(ctx
->opcode
) != 0))
4169 /* sraiq - sraiq. */
4170 GEN_HANDLER(sraiq
, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR
)
4172 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4173 gen_op_set_T1(SH(ctx
->opcode
));
4174 gen_op_POWER_sraq();
4175 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4176 if (unlikely(Rc(ctx
->opcode
) != 0))
4181 GEN_HANDLER(sraq
, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR
)
4183 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4184 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4185 gen_op_POWER_sraq();
4186 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4187 if (unlikely(Rc(ctx
->opcode
) != 0))
4192 GEN_HANDLER(sre
, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR
)
4194 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4195 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4197 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4198 if (unlikely(Rc(ctx
->opcode
) != 0))
4203 GEN_HANDLER(srea
, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR
)
4205 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4206 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4207 gen_op_POWER_srea();
4208 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4209 if (unlikely(Rc(ctx
->opcode
) != 0))
4214 GEN_HANDLER(sreq
, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR
)
4216 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4217 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4218 gen_op_POWER_sreq();
4219 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4220 if (unlikely(Rc(ctx
->opcode
) != 0))
4225 GEN_HANDLER(sriq
, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR
)
4227 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4228 gen_op_set_T1(SH(ctx
->opcode
));
4230 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4231 if (unlikely(Rc(ctx
->opcode
) != 0))
4236 GEN_HANDLER(srliq
, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR
)
4238 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4239 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4240 gen_op_set_T1(SH(ctx
->opcode
));
4241 gen_op_POWER_srlq();
4242 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4243 if (unlikely(Rc(ctx
->opcode
) != 0))
4248 GEN_HANDLER(srlq
, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR
)
4250 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4251 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4252 gen_op_POWER_srlq();
4253 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4254 if (unlikely(Rc(ctx
->opcode
) != 0))
4259 GEN_HANDLER(srq
, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR
)
4261 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4262 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4264 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4265 if (unlikely(Rc(ctx
->opcode
) != 0))
4269 /* PowerPC 602 specific instructions */
4271 GEN_HANDLER(dsa
, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC
)
4274 GEN_EXCP_INVAL(ctx
);
4278 GEN_HANDLER(esa
, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC
)
4281 GEN_EXCP_INVAL(ctx
);
4285 GEN_HANDLER(mfrom
, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC
)
4287 #if defined(CONFIG_USER_ONLY)
4288 GEN_EXCP_PRIVOPC(ctx
);
4290 if (unlikely(!ctx
->supervisor
)) {
4291 GEN_EXCP_PRIVOPC(ctx
);
4294 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4296 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4300 /* 602 - 603 - G2 TLB management */
4302 GEN_HANDLER(tlbld_6xx
, 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB
)
4304 #if defined(CONFIG_USER_ONLY)
4305 GEN_EXCP_PRIVOPC(ctx
);
4307 if (unlikely(!ctx
->supervisor
)) {
4308 GEN_EXCP_PRIVOPC(ctx
);
4311 gen_op_load_gpr_T0(rB(ctx
->opcode
));
4317 GEN_HANDLER(tlbli_6xx
, 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB
)
4319 #if defined(CONFIG_USER_ONLY)
4320 GEN_EXCP_PRIVOPC(ctx
);
4322 if (unlikely(!ctx
->supervisor
)) {
4323 GEN_EXCP_PRIVOPC(ctx
);
4326 gen_op_load_gpr_T0(rB(ctx
->opcode
));
4331 /* 74xx TLB management */
4333 GEN_HANDLER(tlbld_74xx
, 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB
)
4335 #if defined(CONFIG_USER_ONLY)
4336 GEN_EXCP_PRIVOPC(ctx
);
4338 if (unlikely(!ctx
->supervisor
)) {
4339 GEN_EXCP_PRIVOPC(ctx
);
4342 gen_op_load_gpr_T0(rB(ctx
->opcode
));
4343 gen_op_74xx_tlbld();
4348 GEN_HANDLER(tlbli_74xx
, 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB
)
4350 #if defined(CONFIG_USER_ONLY)
4351 GEN_EXCP_PRIVOPC(ctx
);
4353 if (unlikely(!ctx
->supervisor
)) {
4354 GEN_EXCP_PRIVOPC(ctx
);
4357 gen_op_load_gpr_T0(rB(ctx
->opcode
));
4358 gen_op_74xx_tlbli();
4362 /* POWER instructions not in PowerPC 601 */
4364 GEN_HANDLER(clf
, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER
)
4366 /* Cache line flush: implemented as no-op */
4370 GEN_HANDLER(cli
, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER
)
4372 /* Cache line invalidate: privileged and treated as no-op */
4373 #if defined(CONFIG_USER_ONLY)
4374 GEN_EXCP_PRIVOPC(ctx
);
4376 if (unlikely(!ctx
->supervisor
)) {
4377 GEN_EXCP_PRIVOPC(ctx
);
4384 GEN_HANDLER(dclst
, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER
)
4386 /* Data cache line store: treated as no-op */
4389 GEN_HANDLER(mfsri
, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER
)
4391 #if defined(CONFIG_USER_ONLY)
4392 GEN_EXCP_PRIVOPC(ctx
);
4394 if (unlikely(!ctx
->supervisor
)) {
4395 GEN_EXCP_PRIVOPC(ctx
);
4398 int ra
= rA(ctx
->opcode
);
4399 int rd
= rD(ctx
->opcode
);
4401 gen_addr_reg_index(ctx
);
4402 gen_op_POWER_mfsri();
4403 gen_op_store_T0_gpr(rd
);
4404 if (ra
!= 0 && ra
!= rd
)
4405 gen_op_store_T1_gpr(ra
);
4409 GEN_HANDLER(rac
, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER
)
4411 #if defined(CONFIG_USER_ONLY)
4412 GEN_EXCP_PRIVOPC(ctx
);
4414 if (unlikely(!ctx
->supervisor
)) {
4415 GEN_EXCP_PRIVOPC(ctx
);
4418 gen_addr_reg_index(ctx
);
4420 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4424 GEN_HANDLER(rfsvc
, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER
)
4426 #if defined(CONFIG_USER_ONLY)
4427 GEN_EXCP_PRIVOPC(ctx
);
4429 if (unlikely(!ctx
->supervisor
)) {
4430 GEN_EXCP_PRIVOPC(ctx
);
4433 gen_op_POWER_rfsvc();
4438 /* svc is not implemented for now */
4440 /* POWER2 specific instructions */
4441 /* Quad manipulation (load/store two floats at a time) */
4442 #define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
4443 #define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
4444 #if defined(CONFIG_USER_ONLY)
4445 static GenOpFunc
*gen_op_POWER2_lfq
[] = {
4446 &gen_op_POWER2_lfq_le_raw
,
4447 &gen_op_POWER2_lfq_raw
,
4449 static GenOpFunc
*gen_op_POWER2_stfq
[] = {
4450 &gen_op_POWER2_stfq_le_raw
,
4451 &gen_op_POWER2_stfq_raw
,
4454 static GenOpFunc
*gen_op_POWER2_lfq
[] = {
4455 &gen_op_POWER2_lfq_le_user
,
4456 &gen_op_POWER2_lfq_user
,
4457 &gen_op_POWER2_lfq_le_kernel
,
4458 &gen_op_POWER2_lfq_kernel
,
4460 static GenOpFunc
*gen_op_POWER2_stfq
[] = {
4461 &gen_op_POWER2_stfq_le_user
,
4462 &gen_op_POWER2_stfq_user
,
4463 &gen_op_POWER2_stfq_le_kernel
,
4464 &gen_op_POWER2_stfq_kernel
,
4469 GEN_HANDLER(lfq
, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2
)
4471 /* NIP cannot be restored if the memory exception comes from an helper */
4472 gen_update_nip(ctx
, ctx
->nip
- 4);
4473 gen_addr_imm_index(ctx
, 0);
4475 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
4476 gen_op_store_FT1_fpr(rD(ctx
->opcode
) + 1);
4480 GEN_HANDLER(lfqu
, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2
)
4482 int ra
= rA(ctx
->opcode
);
4484 /* NIP cannot be restored if the memory exception comes from an helper */
4485 gen_update_nip(ctx
, ctx
->nip
- 4);
4486 gen_addr_imm_index(ctx
, 0);
4488 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
4489 gen_op_store_FT1_fpr(rD(ctx
->opcode
) + 1);
4491 gen_op_store_T0_gpr(ra
);
4495 GEN_HANDLER(lfqux
, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2
)
4497 int ra
= rA(ctx
->opcode
);
4499 /* NIP cannot be restored if the memory exception comes from an helper */
4500 gen_update_nip(ctx
, ctx
->nip
- 4);
4501 gen_addr_reg_index(ctx
);
4503 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
4504 gen_op_store_FT1_fpr(rD(ctx
->opcode
) + 1);
4506 gen_op_store_T0_gpr(ra
);
4510 GEN_HANDLER(lfqx
, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2
)
4512 /* NIP cannot be restored if the memory exception comes from an helper */
4513 gen_update_nip(ctx
, ctx
->nip
- 4);
4514 gen_addr_reg_index(ctx
);
4516 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
4517 gen_op_store_FT1_fpr(rD(ctx
->opcode
) + 1);
4521 GEN_HANDLER(stfq
, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2
)
4523 /* NIP cannot be restored if the memory exception comes from an helper */
4524 gen_update_nip(ctx
, ctx
->nip
- 4);
4525 gen_addr_imm_index(ctx
, 0);
4526 gen_op_load_fpr_FT0(rS(ctx
->opcode
));
4527 gen_op_load_fpr_FT1(rS(ctx
->opcode
) + 1);
4532 GEN_HANDLER(stfqu
, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2
)
4534 int ra
= rA(ctx
->opcode
);
4536 /* NIP cannot be restored if the memory exception comes from an helper */
4537 gen_update_nip(ctx
, ctx
->nip
- 4);
4538 gen_addr_imm_index(ctx
, 0);
4539 gen_op_load_fpr_FT0(rS(ctx
->opcode
));
4540 gen_op_load_fpr_FT1(rS(ctx
->opcode
) + 1);
4543 gen_op_store_T0_gpr(ra
);
4547 GEN_HANDLER(stfqux
, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2
)
4549 int ra
= rA(ctx
->opcode
);
4551 /* NIP cannot be restored if the memory exception comes from an helper */
4552 gen_update_nip(ctx
, ctx
->nip
- 4);
4553 gen_addr_reg_index(ctx
);
4554 gen_op_load_fpr_FT0(rS(ctx
->opcode
));
4555 gen_op_load_fpr_FT1(rS(ctx
->opcode
) + 1);
4558 gen_op_store_T0_gpr(ra
);
4562 GEN_HANDLER(stfqx
, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2
)
4564 /* NIP cannot be restored if the memory exception comes from an helper */
4565 gen_update_nip(ctx
, ctx
->nip
- 4);
4566 gen_addr_reg_index(ctx
);
4567 gen_op_load_fpr_FT0(rS(ctx
->opcode
));
4568 gen_op_load_fpr_FT1(rS(ctx
->opcode
) + 1);
4572 /* BookE specific instructions */
4573 /* XXX: not implemented on 440 ? */
4574 GEN_HANDLER(mfapidi
, 0x1F, 0x13, 0x08, 0x0000F801, PPC_BOOKE_EXT
)
4577 GEN_EXCP_INVAL(ctx
);
4580 /* XXX: not implemented on 440 ? */
4581 GEN_HANDLER(tlbiva
, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_BOOKE_EXT
)
4583 #if defined(CONFIG_USER_ONLY)
4584 GEN_EXCP_PRIVOPC(ctx
);
4586 if (unlikely(!ctx
->supervisor
)) {
4587 GEN_EXCP_PRIVOPC(ctx
);
4590 gen_addr_reg_index(ctx
);
4591 /* Use the same micro-ops as for tlbie */
4592 #if defined(TARGET_PPC64)
4601 /* All 405 MAC instructions are translated here */
4602 static inline void gen_405_mulladd_insn (DisasContext
*ctx
, int opc2
, int opc3
,
4603 int ra
, int rb
, int rt
, int Rc
)
4605 gen_op_load_gpr_T0(ra
);
4606 gen_op_load_gpr_T1(rb
);
4607 switch (opc3
& 0x0D) {
4609 /* macchw - macchw. - macchwo - macchwo. */
4610 /* macchws - macchws. - macchwso - macchwso. */
4611 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
4612 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
4613 /* mulchw - mulchw. */
4614 gen_op_405_mulchw();
4617 /* macchwu - macchwu. - macchwuo - macchwuo. */
4618 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
4619 /* mulchwu - mulchwu. */
4620 gen_op_405_mulchwu();
4623 /* machhw - machhw. - machhwo - machhwo. */
4624 /* machhws - machhws. - machhwso - machhwso. */
4625 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
4626 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
4627 /* mulhhw - mulhhw. */
4628 gen_op_405_mulhhw();
4631 /* machhwu - machhwu. - machhwuo - machhwuo. */
4632 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
4633 /* mulhhwu - mulhhwu. */
4634 gen_op_405_mulhhwu();
4637 /* maclhw - maclhw. - maclhwo - maclhwo. */
4638 /* maclhws - maclhws. - maclhwso - maclhwso. */
4639 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
4640 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
4641 /* mullhw - mullhw. */
4642 gen_op_405_mullhw();
4645 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
4646 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
4647 /* mullhwu - mullhwu. */
4648 gen_op_405_mullhwu();
4652 /* nmultiply-and-accumulate (0x0E) */
4656 /* (n)multiply-and-accumulate (0x0C - 0x0E) */
4657 gen_op_load_gpr_T2(rt
);
4658 gen_op_move_T1_T0();
4659 gen_op_405_add_T0_T2();
4662 /* Check overflow */
4664 gen_op_405_check_ov();
4666 gen_op_405_check_ovu();
4671 gen_op_405_check_sat();
4673 gen_op_405_check_satu();
4675 gen_op_store_T0_gpr(rt
);
4676 if (unlikely(Rc
) != 0) {
4682 #define GEN_MAC_HANDLER(name, opc2, opc3) \
4683 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
4685 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
4686 rD(ctx->opcode), Rc(ctx->opcode)); \
4689 /* macchw - macchw. */
4690 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05);
4691 /* macchwo - macchwo. */
4692 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15);
4693 /* macchws - macchws. */
4694 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07);
4695 /* macchwso - macchwso. */
4696 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17);
4697 /* macchwsu - macchwsu. */
4698 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06);
4699 /* macchwsuo - macchwsuo. */
4700 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16);
4701 /* macchwu - macchwu. */
4702 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04);
4703 /* macchwuo - macchwuo. */
4704 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14);
4705 /* machhw - machhw. */
4706 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01);
4707 /* machhwo - machhwo. */
4708 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11);
4709 /* machhws - machhws. */
4710 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03);
4711 /* machhwso - machhwso. */
4712 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13);
4713 /* machhwsu - machhwsu. */
4714 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02);
4715 /* machhwsuo - machhwsuo. */
4716 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12);
4717 /* machhwu - machhwu. */
4718 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00);
4719 /* machhwuo - machhwuo. */
4720 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10);
4721 /* maclhw - maclhw. */
4722 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D);
4723 /* maclhwo - maclhwo. */
4724 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D);
4725 /* maclhws - maclhws. */
4726 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F);
4727 /* maclhwso - maclhwso. */
4728 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F);
4729 /* maclhwu - maclhwu. */
4730 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C);
4731 /* maclhwuo - maclhwuo. */
4732 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C);
4733 /* maclhwsu - maclhwsu. */
4734 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E);
4735 /* maclhwsuo - maclhwsuo. */
4736 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E);
4737 /* nmacchw - nmacchw. */
4738 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05);
4739 /* nmacchwo - nmacchwo. */
4740 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15);
4741 /* nmacchws - nmacchws. */
4742 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07);
4743 /* nmacchwso - nmacchwso. */
4744 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17);
4745 /* nmachhw - nmachhw. */
4746 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01);
4747 /* nmachhwo - nmachhwo. */
4748 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11);
4749 /* nmachhws - nmachhws. */
4750 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03);
4751 /* nmachhwso - nmachhwso. */
4752 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13);
4753 /* nmaclhw - nmaclhw. */
4754 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D);
4755 /* nmaclhwo - nmaclhwo. */
4756 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D);
4757 /* nmaclhws - nmaclhws. */
4758 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F);
4759 /* nmaclhwso - nmaclhwso. */
4760 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F);
4762 /* mulchw - mulchw. */
4763 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05);
4764 /* mulchwu - mulchwu. */
4765 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04);
4766 /* mulhhw - mulhhw. */
4767 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01);
4768 /* mulhhwu - mulhhwu. */
4769 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00);
4770 /* mullhw - mullhw. */
4771 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D);
4772 /* mullhwu - mullhwu. */
4773 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C);
4776 GEN_HANDLER(mfdcr
, 0x1F, 0x03, 0x0A, 0x00000001, PPC_EMB_COMMON
)
4778 #if defined(CONFIG_USER_ONLY)
4779 GEN_EXCP_PRIVREG(ctx
);
4781 uint32_t dcrn
= SPR(ctx
->opcode
);
4783 if (unlikely(!ctx
->supervisor
)) {
4784 GEN_EXCP_PRIVREG(ctx
);
4787 gen_op_set_T0(dcrn
);
4789 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4794 GEN_HANDLER(mtdcr
, 0x1F, 0x03, 0x0E, 0x00000001, PPC_EMB_COMMON
)
4796 #if defined(CONFIG_USER_ONLY)
4797 GEN_EXCP_PRIVREG(ctx
);
4799 uint32_t dcrn
= SPR(ctx
->opcode
);
4801 if (unlikely(!ctx
->supervisor
)) {
4802 GEN_EXCP_PRIVREG(ctx
);
4805 gen_op_set_T0(dcrn
);
4806 gen_op_load_gpr_T1(rS(ctx
->opcode
));
4812 /* XXX: not implemented on 440 ? */
4813 GEN_HANDLER(mfdcrx
, 0x1F, 0x03, 0x08, 0x00000000, PPC_BOOKE_EXT
)
4815 #if defined(CONFIG_USER_ONLY)
4816 GEN_EXCP_PRIVREG(ctx
);
4818 if (unlikely(!ctx
->supervisor
)) {
4819 GEN_EXCP_PRIVREG(ctx
);
4822 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4824 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4825 /* Note: Rc update flag set leads to undefined state of Rc0 */
4830 /* XXX: not implemented on 440 ? */
4831 GEN_HANDLER(mtdcrx
, 0x1F, 0x03, 0x0C, 0x00000000, PPC_BOOKE_EXT
)
4833 #if defined(CONFIG_USER_ONLY)
4834 GEN_EXCP_PRIVREG(ctx
);
4836 if (unlikely(!ctx
->supervisor
)) {
4837 GEN_EXCP_PRIVREG(ctx
);
4840 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4841 gen_op_load_gpr_T1(rS(ctx
->opcode
));
4843 /* Note: Rc update flag set leads to undefined state of Rc0 */
4847 /* mfdcrux (PPC 460) : user-mode access to DCR */
4848 GEN_HANDLER(mfdcrux
, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX
)
4850 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4852 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4853 /* Note: Rc update flag set leads to undefined state of Rc0 */
4856 /* mtdcrux (PPC 460) : user-mode access to DCR */
4857 GEN_HANDLER(mtdcrux
, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX
)
4859 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4860 gen_op_load_gpr_T1(rS(ctx
->opcode
));
4862 /* Note: Rc update flag set leads to undefined state of Rc0 */
4866 GEN_HANDLER(dccci
, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON
)
4868 #if defined(CONFIG_USER_ONLY)
4869 GEN_EXCP_PRIVOPC(ctx
);
4871 if (unlikely(!ctx
->supervisor
)) {
4872 GEN_EXCP_PRIVOPC(ctx
);
4875 /* interpreted as no-op */
4880 GEN_HANDLER(dcread
, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON
)
4882 #if defined(CONFIG_USER_ONLY)
4883 GEN_EXCP_PRIVOPC(ctx
);
4885 if (unlikely(!ctx
->supervisor
)) {
4886 GEN_EXCP_PRIVOPC(ctx
);
4889 gen_addr_reg_index(ctx
);
4891 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4896 GEN_HANDLER(icbt_40x
, 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT
)
4898 /* interpreted as no-op */
4899 /* XXX: specification say this is treated as a load by the MMU
4900 * but does not generate any exception
4905 GEN_HANDLER(iccci
, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON
)
4907 #if defined(CONFIG_USER_ONLY)
4908 GEN_EXCP_PRIVOPC(ctx
);
4910 if (unlikely(!ctx
->supervisor
)) {
4911 GEN_EXCP_PRIVOPC(ctx
);
4914 /* interpreted as no-op */
4919 GEN_HANDLER(icread
, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON
)
4921 #if defined(CONFIG_USER_ONLY)
4922 GEN_EXCP_PRIVOPC(ctx
);
4924 if (unlikely(!ctx
->supervisor
)) {
4925 GEN_EXCP_PRIVOPC(ctx
);
4928 /* interpreted as no-op */
4932 /* rfci (supervisor only) */
4933 GEN_HANDLER(rfci_40x
, 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP
)
4935 #if defined(CONFIG_USER_ONLY)
4936 GEN_EXCP_PRIVOPC(ctx
);
4938 if (unlikely(!ctx
->supervisor
)) {
4939 GEN_EXCP_PRIVOPC(ctx
);
4942 /* Restore CPU state */
4948 GEN_HANDLER(rfci
, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE
)
4950 #if defined(CONFIG_USER_ONLY)
4951 GEN_EXCP_PRIVOPC(ctx
);
4953 if (unlikely(!ctx
->supervisor
)) {
4954 GEN_EXCP_PRIVOPC(ctx
);
4957 /* Restore CPU state */
4963 /* BookE specific */
4964 /* XXX: not implemented on 440 ? */
4965 GEN_HANDLER(rfdi
, 0x13, 0x07, 0x01, 0x03FF8001, PPC_BOOKE_EXT
)
4967 #if defined(CONFIG_USER_ONLY)
4968 GEN_EXCP_PRIVOPC(ctx
);
4970 if (unlikely(!ctx
->supervisor
)) {
4971 GEN_EXCP_PRIVOPC(ctx
);
4974 /* Restore CPU state */
4980 /* XXX: not implemented on 440 ? */
4981 GEN_HANDLER(rfmci
, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI
)
4983 #if defined(CONFIG_USER_ONLY)
4984 GEN_EXCP_PRIVOPC(ctx
);
4986 if (unlikely(!ctx
->supervisor
)) {
4987 GEN_EXCP_PRIVOPC(ctx
);
4990 /* Restore CPU state */
4996 /* TLB management - PowerPC 405 implementation */
4998 GEN_HANDLER(tlbre_40x
, 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB
)
5000 #if defined(CONFIG_USER_ONLY)
5001 GEN_EXCP_PRIVOPC(ctx
);
5003 if (unlikely(!ctx
->supervisor
)) {
5004 GEN_EXCP_PRIVOPC(ctx
);
5007 switch (rB(ctx
->opcode
)) {
5009 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5010 gen_op_4xx_tlbre_hi();
5011 gen_op_store_T0_gpr(rD(ctx
->opcode
));
5014 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5015 gen_op_4xx_tlbre_lo();
5016 gen_op_store_T0_gpr(rD(ctx
->opcode
));
5019 GEN_EXCP_INVAL(ctx
);
5025 /* tlbsx - tlbsx. */
5026 GEN_HANDLER(tlbsx_40x
, 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB
)
5028 #if defined(CONFIG_USER_ONLY)
5029 GEN_EXCP_PRIVOPC(ctx
);
5031 if (unlikely(!ctx
->supervisor
)) {
5032 GEN_EXCP_PRIVOPC(ctx
);
5035 gen_addr_reg_index(ctx
);
5037 if (Rc(ctx
->opcode
))
5038 gen_op_4xx_tlbsx_check();
5039 gen_op_store_T0_gpr(rD(ctx
->opcode
));
5044 GEN_HANDLER(tlbwe_40x
, 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB
)
5046 #if defined(CONFIG_USER_ONLY)
5047 GEN_EXCP_PRIVOPC(ctx
);
5049 if (unlikely(!ctx
->supervisor
)) {
5050 GEN_EXCP_PRIVOPC(ctx
);
5053 switch (rB(ctx
->opcode
)) {
5055 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5056 gen_op_load_gpr_T1(rS(ctx
->opcode
));
5057 gen_op_4xx_tlbwe_hi();
5060 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5061 gen_op_load_gpr_T1(rS(ctx
->opcode
));
5062 gen_op_4xx_tlbwe_lo();
5065 GEN_EXCP_INVAL(ctx
);
5071 /* TLB management - PowerPC 440 implementation */
5073 GEN_HANDLER(tlbre_440
, 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE
)
5075 #if defined(CONFIG_USER_ONLY)
5076 GEN_EXCP_PRIVOPC(ctx
);
5078 if (unlikely(!ctx
->supervisor
)) {
5079 GEN_EXCP_PRIVOPC(ctx
);
5082 switch (rB(ctx
->opcode
)) {
5086 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5087 gen_op_440_tlbre(rB(ctx
->opcode
));
5088 gen_op_store_T0_gpr(rD(ctx
->opcode
));
5091 GEN_EXCP_INVAL(ctx
);
5097 /* tlbsx - tlbsx. */
5098 GEN_HANDLER(tlbsx_440
, 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE
)
5100 #if defined(CONFIG_USER_ONLY)
5101 GEN_EXCP_PRIVOPC(ctx
);
5103 if (unlikely(!ctx
->supervisor
)) {
5104 GEN_EXCP_PRIVOPC(ctx
);
5107 gen_addr_reg_index(ctx
);
5109 if (Rc(ctx
->opcode
))
5110 gen_op_4xx_tlbsx_check();
5111 gen_op_store_T0_gpr(rD(ctx
->opcode
));
5116 GEN_HANDLER(tlbwe_440
, 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE
)
5118 #if defined(CONFIG_USER_ONLY)
5119 GEN_EXCP_PRIVOPC(ctx
);
5121 if (unlikely(!ctx
->supervisor
)) {
5122 GEN_EXCP_PRIVOPC(ctx
);
5125 switch (rB(ctx
->opcode
)) {
5129 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5130 gen_op_load_gpr_T1(rS(ctx
->opcode
));
5131 gen_op_440_tlbwe(rB(ctx
->opcode
));
5134 GEN_EXCP_INVAL(ctx
);
5141 GEN_HANDLER(wrtee
, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_EMB_COMMON
)
5143 #if defined(CONFIG_USER_ONLY)
5144 GEN_EXCP_PRIVOPC(ctx
);
5146 if (unlikely(!ctx
->supervisor
)) {
5147 GEN_EXCP_PRIVOPC(ctx
);
5150 gen_op_load_gpr_T0(rD(ctx
->opcode
));
5152 /* Stop translation to have a chance to raise an exception
5153 * if we just set msr_ee to 1
5160 GEN_HANDLER(wrteei
, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_EMB_COMMON
)
5162 #if defined(CONFIG_USER_ONLY)
5163 GEN_EXCP_PRIVOPC(ctx
);
5165 if (unlikely(!ctx
->supervisor
)) {
5166 GEN_EXCP_PRIVOPC(ctx
);
5169 gen_op_set_T0(ctx
->opcode
& 0x00010000);
5171 /* Stop translation to have a chance to raise an exception
5172 * if we just set msr_ee to 1
5178 /* PowerPC 440 specific instructions */
5180 GEN_HANDLER(dlmzb
, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC
)
5182 gen_op_load_gpr_T0(rS(ctx
->opcode
));
5183 gen_op_load_gpr_T1(rB(ctx
->opcode
));
5185 gen_op_store_T0_gpr(rA(ctx
->opcode
));
5186 gen_op_store_xer_bc();
5187 if (Rc(ctx
->opcode
)) {
5188 gen_op_440_dlmzb_update_Rc();
5189 gen_op_store_T0_crf(0);
5193 /* mbar replaces eieio on 440 */
5194 GEN_HANDLER(mbar
, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE
)
5196 /* interpreted as no-op */
5199 /* msync replaces sync on 440 */
5200 GEN_HANDLER(msync
, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE
)
5202 /* interpreted as no-op */
5206 GEN_HANDLER(icbt_440
, 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE
)
5208 /* interpreted as no-op */
5209 /* XXX: specification say this is treated as a load by the MMU
5210 * but does not generate any exception
5214 #if defined(TARGET_PPCEMB)
5215 /*** SPE extension ***/
5217 /* Register moves */
5218 GEN32(gen_op_load_gpr64_T0
, gen_op_load_gpr64_T0_gpr
);
5219 GEN32(gen_op_load_gpr64_T1
, gen_op_load_gpr64_T1_gpr
);
5221 GEN32(gen_op_load_gpr64_T2
, gen_op_load_gpr64_T2_gpr
);
5224 GEN32(gen_op_store_T0_gpr64
, gen_op_store_T0_gpr64_gpr
);
5225 GEN32(gen_op_store_T1_gpr64
, gen_op_store_T1_gpr64_gpr
);
5227 GEN32(gen_op_store_T2_gpr64
, gen_op_store_T2_gpr64_gpr
);
5230 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5231 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5233 if (Rc(ctx->opcode)) \
5239 /* Handler for undefined SPE opcodes */
5240 static inline void gen_speundef (DisasContext
*ctx
)
5242 GEN_EXCP_INVAL(ctx
);
5245 /* SPE load and stores */
5246 static inline void gen_addr_spe_imm_index (DisasContext
*ctx
, int sh
)
5248 target_long simm
= rB(ctx
->opcode
);
5250 if (rA(ctx
->opcode
) == 0) {
5251 gen_set_T0(simm
<< sh
);
5253 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5254 if (likely(simm
!= 0))
5255 gen_op_addi(simm
<< sh
);
5259 #define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
5260 #if defined(CONFIG_USER_ONLY)
5261 #if defined(TARGET_PPC64)
5262 #define OP_SPE_LD_TABLE(name) \
5263 static GenOpFunc *gen_op_spe_l##name[] = { \
5264 &gen_op_spe_l##name##_raw, \
5265 &gen_op_spe_l##name##_le_raw, \
5266 &gen_op_spe_l##name##_64_raw, \
5267 &gen_op_spe_l##name##_le_64_raw, \
5269 #define OP_SPE_ST_TABLE(name) \
5270 static GenOpFunc *gen_op_spe_st##name[] = { \
5271 &gen_op_spe_st##name##_raw, \
5272 &gen_op_spe_st##name##_le_raw, \
5273 &gen_op_spe_st##name##_64_raw, \
5274 &gen_op_spe_st##name##_le_64_raw, \
5276 #else /* defined(TARGET_PPC64) */
5277 #define OP_SPE_LD_TABLE(name) \
5278 static GenOpFunc *gen_op_spe_l##name[] = { \
5279 &gen_op_spe_l##name##_raw, \
5280 &gen_op_spe_l##name##_le_raw, \
5282 #define OP_SPE_ST_TABLE(name) \
5283 static GenOpFunc *gen_op_spe_st##name[] = { \
5284 &gen_op_spe_st##name##_raw, \
5285 &gen_op_spe_st##name##_le_raw, \
5287 #endif /* defined(TARGET_PPC64) */
5288 #else /* defined(CONFIG_USER_ONLY) */
5289 #if defined(TARGET_PPC64)
5290 #define OP_SPE_LD_TABLE(name) \
5291 static GenOpFunc *gen_op_spe_l##name[] = { \
5292 &gen_op_spe_l##name##_user, \
5293 &gen_op_spe_l##name##_le_user, \
5294 &gen_op_spe_l##name##_kernel, \
5295 &gen_op_spe_l##name##_le_kernel, \
5296 &gen_op_spe_l##name##_64_user, \
5297 &gen_op_spe_l##name##_le_64_user, \
5298 &gen_op_spe_l##name##_64_kernel, \
5299 &gen_op_spe_l##name##_le_64_kernel, \
5301 #define OP_SPE_ST_TABLE(name) \
5302 static GenOpFunc *gen_op_spe_st##name[] = { \
5303 &gen_op_spe_st##name##_user, \
5304 &gen_op_spe_st##name##_le_user, \
5305 &gen_op_spe_st##name##_kernel, \
5306 &gen_op_spe_st##name##_le_kernel, \
5307 &gen_op_spe_st##name##_64_user, \
5308 &gen_op_spe_st##name##_le_64_user, \
5309 &gen_op_spe_st##name##_64_kernel, \
5310 &gen_op_spe_st##name##_le_64_kernel, \
5312 #else /* defined(TARGET_PPC64) */
5313 #define OP_SPE_LD_TABLE(name) \
5314 static GenOpFunc *gen_op_spe_l##name[] = { \
5315 &gen_op_spe_l##name##_user, \
5316 &gen_op_spe_l##name##_le_user, \
5317 &gen_op_spe_l##name##_kernel, \
5318 &gen_op_spe_l##name##_le_kernel, \
5320 #define OP_SPE_ST_TABLE(name) \
5321 static GenOpFunc *gen_op_spe_st##name[] = { \
5322 &gen_op_spe_st##name##_user, \
5323 &gen_op_spe_st##name##_le_user, \
5324 &gen_op_spe_st##name##_kernel, \
5325 &gen_op_spe_st##name##_le_kernel, \
5327 #endif /* defined(TARGET_PPC64) */
5328 #endif /* defined(CONFIG_USER_ONLY) */
5330 #define GEN_SPE_LD(name, sh) \
5331 static inline void gen_evl##name (DisasContext *ctx) \
5333 if (unlikely(!ctx->spe_enabled)) { \
5334 GEN_EXCP_NO_AP(ctx); \
5337 gen_addr_spe_imm_index(ctx, sh); \
5338 op_spe_ldst(spe_l##name); \
5339 gen_op_store_T1_gpr64(rD(ctx->opcode)); \
5342 #define GEN_SPE_LDX(name) \
5343 static inline void gen_evl##name##x (DisasContext *ctx) \
5345 if (unlikely(!ctx->spe_enabled)) { \
5346 GEN_EXCP_NO_AP(ctx); \
5349 gen_addr_reg_index(ctx); \
5350 op_spe_ldst(spe_l##name); \
5351 gen_op_store_T1_gpr64(rD(ctx->opcode)); \
5354 #define GEN_SPEOP_LD(name, sh) \
5355 OP_SPE_LD_TABLE(name); \
5356 GEN_SPE_LD(name, sh); \
5359 #define GEN_SPE_ST(name, sh) \
5360 static inline void gen_evst##name (DisasContext *ctx) \
5362 if (unlikely(!ctx->spe_enabled)) { \
5363 GEN_EXCP_NO_AP(ctx); \
5366 gen_addr_spe_imm_index(ctx, sh); \
5367 gen_op_load_gpr64_T1(rS(ctx->opcode)); \
5368 op_spe_ldst(spe_st##name); \
5371 #define GEN_SPE_STX(name) \
5372 static inline void gen_evst##name##x (DisasContext *ctx) \
5374 if (unlikely(!ctx->spe_enabled)) { \
5375 GEN_EXCP_NO_AP(ctx); \
5378 gen_addr_reg_index(ctx); \
5379 gen_op_load_gpr64_T1(rS(ctx->opcode)); \
5380 op_spe_ldst(spe_st##name); \
5383 #define GEN_SPEOP_ST(name, sh) \
5384 OP_SPE_ST_TABLE(name); \
5385 GEN_SPE_ST(name, sh); \
5388 #define GEN_SPEOP_LDST(name, sh) \
5389 GEN_SPEOP_LD(name, sh); \
5390 GEN_SPEOP_ST(name, sh)
5392 /* SPE arithmetic and logic */
5393 #define GEN_SPEOP_ARITH2(name) \
5394 static inline void gen_##name (DisasContext *ctx) \
5396 if (unlikely(!ctx->spe_enabled)) { \
5397 GEN_EXCP_NO_AP(ctx); \
5400 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5401 gen_op_load_gpr64_T1(rB(ctx->opcode)); \
5403 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5406 #define GEN_SPEOP_ARITH1(name) \
5407 static inline void gen_##name (DisasContext *ctx) \
5409 if (unlikely(!ctx->spe_enabled)) { \
5410 GEN_EXCP_NO_AP(ctx); \
5413 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5415 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5418 #define GEN_SPEOP_COMP(name) \
5419 static inline void gen_##name (DisasContext *ctx) \
5421 if (unlikely(!ctx->spe_enabled)) { \
5422 GEN_EXCP_NO_AP(ctx); \
5425 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5426 gen_op_load_gpr64_T1(rB(ctx->opcode)); \
5428 gen_op_store_T0_crf(crfD(ctx->opcode)); \
5432 GEN_SPEOP_ARITH2(evand
);
5433 GEN_SPEOP_ARITH2(evandc
);
5434 GEN_SPEOP_ARITH2(evxor
);
5435 GEN_SPEOP_ARITH2(evor
);
5436 GEN_SPEOP_ARITH2(evnor
);
5437 GEN_SPEOP_ARITH2(eveqv
);
5438 GEN_SPEOP_ARITH2(evorc
);
5439 GEN_SPEOP_ARITH2(evnand
);
5440 GEN_SPEOP_ARITH2(evsrwu
);
5441 GEN_SPEOP_ARITH2(evsrws
);
5442 GEN_SPEOP_ARITH2(evslw
);
5443 GEN_SPEOP_ARITH2(evrlw
);
5444 GEN_SPEOP_ARITH2(evmergehi
);
5445 GEN_SPEOP_ARITH2(evmergelo
);
5446 GEN_SPEOP_ARITH2(evmergehilo
);
5447 GEN_SPEOP_ARITH2(evmergelohi
);
5450 GEN_SPEOP_ARITH2(evaddw
);
5451 GEN_SPEOP_ARITH2(evsubfw
);
5452 GEN_SPEOP_ARITH1(evabs
);
5453 GEN_SPEOP_ARITH1(evneg
);
5454 GEN_SPEOP_ARITH1(evextsb
);
5455 GEN_SPEOP_ARITH1(evextsh
);
5456 GEN_SPEOP_ARITH1(evrndw
);
5457 GEN_SPEOP_ARITH1(evcntlzw
);
5458 GEN_SPEOP_ARITH1(evcntlsw
);
5459 static inline void gen_brinc (DisasContext
*ctx
)
5461 /* Note: brinc is usable even if SPE is disabled */
5462 gen_op_load_gpr64_T0(rA(ctx
->opcode
));
5463 gen_op_load_gpr64_T1(rB(ctx
->opcode
));
5465 gen_op_store_T0_gpr64(rD(ctx
->opcode
));
5468 #define GEN_SPEOP_ARITH_IMM2(name) \
5469 static inline void gen_##name##i (DisasContext *ctx) \
5471 if (unlikely(!ctx->spe_enabled)) { \
5472 GEN_EXCP_NO_AP(ctx); \
5475 gen_op_load_gpr64_T0(rB(ctx->opcode)); \
5476 gen_op_splatwi_T1_64(rA(ctx->opcode)); \
5478 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5481 #define GEN_SPEOP_LOGIC_IMM2(name) \
5482 static inline void gen_##name##i (DisasContext *ctx) \
5484 if (unlikely(!ctx->spe_enabled)) { \
5485 GEN_EXCP_NO_AP(ctx); \
5488 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5489 gen_op_splatwi_T1_64(rB(ctx->opcode)); \
5491 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5494 GEN_SPEOP_ARITH_IMM2(evaddw
);
5495 #define gen_evaddiw gen_evaddwi
5496 GEN_SPEOP_ARITH_IMM2(evsubfw
);
5497 #define gen_evsubifw gen_evsubfwi
5498 GEN_SPEOP_LOGIC_IMM2(evslw
);
5499 GEN_SPEOP_LOGIC_IMM2(evsrwu
);
5500 #define gen_evsrwis gen_evsrwsi
5501 GEN_SPEOP_LOGIC_IMM2(evsrws
);
5502 #define gen_evsrwiu gen_evsrwui
5503 GEN_SPEOP_LOGIC_IMM2(evrlw
);
5505 static inline void gen_evsplati (DisasContext
*ctx
)
5507 int32_t imm
= (int32_t)(rA(ctx
->opcode
) << 27) >> 27;
5509 gen_op_splatwi_T0_64(imm
);
5510 gen_op_store_T0_gpr64(rD(ctx
->opcode
));
5513 static inline void gen_evsplatfi (DisasContext
*ctx
)
5515 uint32_t imm
= rA(ctx
->opcode
) << 27;
5517 gen_op_splatwi_T0_64(imm
);
5518 gen_op_store_T0_gpr64(rD(ctx
->opcode
));
5522 GEN_SPEOP_COMP(evcmpgtu
);
5523 GEN_SPEOP_COMP(evcmpgts
);
5524 GEN_SPEOP_COMP(evcmpltu
);
5525 GEN_SPEOP_COMP(evcmplts
);
5526 GEN_SPEOP_COMP(evcmpeq
);
5528 GEN_SPE(evaddw
, speundef
, 0x00, 0x08, 0x00000000, PPC_SPE
); ////
5529 GEN_SPE(evaddiw
, speundef
, 0x01, 0x08, 0x00000000, PPC_SPE
);
5530 GEN_SPE(evsubfw
, speundef
, 0x02, 0x08, 0x00000000, PPC_SPE
); ////
5531 GEN_SPE(evsubifw
, speundef
, 0x03, 0x08, 0x00000000, PPC_SPE
);
5532 GEN_SPE(evabs
, evneg
, 0x04, 0x08, 0x0000F800, PPC_SPE
); ////
5533 GEN_SPE(evextsb
, evextsh
, 0x05, 0x08, 0x0000F800, PPC_SPE
); ////
5534 GEN_SPE(evrndw
, evcntlzw
, 0x06, 0x08, 0x0000F800, PPC_SPE
); ////
5535 GEN_SPE(evcntlsw
, brinc
, 0x07, 0x08, 0x00000000, PPC_SPE
); //
5536 GEN_SPE(speundef
, evand
, 0x08, 0x08, 0x00000000, PPC_SPE
); ////
5537 GEN_SPE(evandc
, speundef
, 0x09, 0x08, 0x00000000, PPC_SPE
); ////
5538 GEN_SPE(evxor
, evor
, 0x0B, 0x08, 0x00000000, PPC_SPE
); ////
5539 GEN_SPE(evnor
, eveqv
, 0x0C, 0x08, 0x00000000, PPC_SPE
); ////
5540 GEN_SPE(speundef
, evorc
, 0x0D, 0x08, 0x00000000, PPC_SPE
); ////
5541 GEN_SPE(evnand
, speundef
, 0x0F, 0x08, 0x00000000, PPC_SPE
); ////
5542 GEN_SPE(evsrwu
, evsrws
, 0x10, 0x08, 0x00000000, PPC_SPE
); ////
5543 GEN_SPE(evsrwiu
, evsrwis
, 0x11, 0x08, 0x00000000, PPC_SPE
);
5544 GEN_SPE(evslw
, speundef
, 0x12, 0x08, 0x00000000, PPC_SPE
); ////
5545 GEN_SPE(evslwi
, speundef
, 0x13, 0x08, 0x00000000, PPC_SPE
);
5546 GEN_SPE(evrlw
, evsplati
, 0x14, 0x08, 0x00000000, PPC_SPE
); //
5547 GEN_SPE(evrlwi
, evsplatfi
, 0x15, 0x08, 0x00000000, PPC_SPE
);
5548 GEN_SPE(evmergehi
, evmergelo
, 0x16, 0x08, 0x00000000, PPC_SPE
); ////
5549 GEN_SPE(evmergehilo
, evmergelohi
, 0x17, 0x08, 0x00000000, PPC_SPE
); ////
5550 GEN_SPE(evcmpgtu
, evcmpgts
, 0x18, 0x08, 0x00600000, PPC_SPE
); ////
5551 GEN_SPE(evcmpltu
, evcmplts
, 0x19, 0x08, 0x00600000, PPC_SPE
); ////
5552 GEN_SPE(evcmpeq
, speundef
, 0x1A, 0x08, 0x00600000, PPC_SPE
); ////
5554 static inline void gen_evsel (DisasContext
*ctx
)
5556 if (unlikely(!ctx
->spe_enabled
)) {
5557 GEN_EXCP_NO_AP(ctx
);
5560 gen_op_load_crf_T0(ctx
->opcode
& 0x7);
5561 gen_op_load_gpr64_T0(rA(ctx
->opcode
));
5562 gen_op_load_gpr64_T1(rB(ctx
->opcode
));
5564 gen_op_store_T0_gpr64(rD(ctx
->opcode
));
5567 GEN_HANDLER(evsel0
, 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE
)
5571 GEN_HANDLER(evsel1
, 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE
)
5575 GEN_HANDLER(evsel2
, 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE
)
5579 GEN_HANDLER(evsel3
, 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE
)
5584 /* Load and stores */
5585 #if defined(TARGET_PPC64)
5586 /* In that case, we already have 64 bits load & stores
5587 * so, spe_ldd is equivalent to ld and spe_std is equivalent to std
5589 #if defined(CONFIG_USER_ONLY)
5590 #define gen_op_spe_ldd_raw gen_op_ld_raw
5591 #define gen_op_spe_ldd_64_raw gen_op_ld_64_raw
5592 #define gen_op_spe_ldd_le_raw gen_op_ld_le_raw
5593 #define gen_op_spe_ldd_le_64_raw gen_op_ld_le_64_raw
5594 #define gen_op_spe_stdd_raw gen_op_ld_raw
5595 #define gen_op_spe_stdd_64_raw gen_op_std_64_raw
5596 #define gen_op_spe_stdd_le_raw gen_op_std_le_raw
5597 #define gen_op_spe_stdd_le_64_raw gen_op_std_le_64_raw
5598 #else /* defined(CONFIG_USER_ONLY) */
5599 #define gen_op_spe_ldd_kernel gen_op_ld_kernel
5600 #define gen_op_spe_ldd_64_kernel gen_op_ld_64_kernel
5601 #define gen_op_spe_ldd_le_kernel gen_op_ld_kernel
5602 #define gen_op_spe_ldd_le_64_kernel gen_op_ld_64_kernel
5603 #define gen_op_spe_ldd_user gen_op_ld_user
5604 #define gen_op_spe_ldd_64_user gen_op_ld_64_user
5605 #define gen_op_spe_ldd_le_user gen_op_ld_le_user
5606 #define gen_op_spe_ldd_le_64_user gen_op_ld_le_64_user
5607 #define gen_op_spe_stdd_kernel gen_op_std_kernel
5608 #define gen_op_spe_stdd_64_kernel gen_op_std_64_kernel
5609 #define gen_op_spe_stdd_le_kernel gen_op_std_kernel
5610 #define gen_op_spe_stdd_le_64_kernel gen_op_std_64_kernel
5611 #define gen_op_spe_stdd_user gen_op_std_user
5612 #define gen_op_spe_stdd_64_user gen_op_std_64_user
5613 #define gen_op_spe_stdd_le_user gen_op_std_le_user
5614 #define gen_op_spe_stdd_le_64_user gen_op_std_le_64_user
5615 #endif /* defined(CONFIG_USER_ONLY) */
5616 #endif /* defined(TARGET_PPC64) */
5617 GEN_SPEOP_LDST(dd
, 3);
5618 GEN_SPEOP_LDST(dw
, 3);
5619 GEN_SPEOP_LDST(dh
, 3);
5620 GEN_SPEOP_LDST(whe
, 2);
5621 GEN_SPEOP_LD(whou
, 2);
5622 GEN_SPEOP_LD(whos
, 2);
5623 GEN_SPEOP_ST(who
, 2);
5625 #if defined(TARGET_PPC64)
5626 /* In that case, spe_stwwo is equivalent to stw */
5627 #if defined(CONFIG_USER_ONLY)
5628 #define gen_op_spe_stwwo_raw gen_op_stw_raw
5629 #define gen_op_spe_stwwo_le_raw gen_op_stw_le_raw
5630 #define gen_op_spe_stwwo_64_raw gen_op_stw_64_raw
5631 #define gen_op_spe_stwwo_le_64_raw gen_op_stw_le_64_raw
5633 #define gen_op_spe_stwwo_user gen_op_stw_user
5634 #define gen_op_spe_stwwo_le_user gen_op_stw_le_user
5635 #define gen_op_spe_stwwo_64_user gen_op_stw_64_user
5636 #define gen_op_spe_stwwo_le_64_user gen_op_stw_le_64_user
5637 #define gen_op_spe_stwwo_kernel gen_op_stw_kernel
5638 #define gen_op_spe_stwwo_le_kernel gen_op_stw_le_kernel
5639 #define gen_op_spe_stwwo_64_kernel gen_op_stw_64_kernel
5640 #define gen_op_spe_stwwo_le_64_kernel gen_op_stw_le_64_kernel
5643 #define _GEN_OP_SPE_STWWE(suffix) \
5644 static inline void gen_op_spe_stwwe_##suffix (void) \
5646 gen_op_srli32_T1_64(); \
5647 gen_op_spe_stwwo_##suffix(); \
5649 #define _GEN_OP_SPE_STWWE_LE(suffix) \
5650 static inline void gen_op_spe_stwwe_le_##suffix (void) \
5652 gen_op_srli32_T1_64(); \
5653 gen_op_spe_stwwo_le_##suffix(); \
5655 #if defined(TARGET_PPC64)
5656 #define GEN_OP_SPE_STWWE(suffix) \
5657 _GEN_OP_SPE_STWWE(suffix); \
5658 _GEN_OP_SPE_STWWE_LE(suffix); \
5659 static inline void gen_op_spe_stwwe_64_##suffix (void) \
5661 gen_op_srli32_T1_64(); \
5662 gen_op_spe_stwwo_64_##suffix(); \
5664 static inline void gen_op_spe_stwwe_le_64_##suffix (void) \
5666 gen_op_srli32_T1_64(); \
5667 gen_op_spe_stwwo_le_64_##suffix(); \
5670 #define GEN_OP_SPE_STWWE(suffix) \
5671 _GEN_OP_SPE_STWWE(suffix); \
5672 _GEN_OP_SPE_STWWE_LE(suffix)
5674 #if defined(CONFIG_USER_ONLY)
5675 GEN_OP_SPE_STWWE(raw
);
5676 #else /* defined(CONFIG_USER_ONLY) */
5677 GEN_OP_SPE_STWWE(kernel
);
5678 GEN_OP_SPE_STWWE(user
);
5679 #endif /* defined(CONFIG_USER_ONLY) */
5680 GEN_SPEOP_ST(wwe
, 2);
5681 GEN_SPEOP_ST(wwo
, 2);
5683 #define GEN_SPE_LDSPLAT(name, op, suffix) \
5684 static inline void gen_op_spe_l##name##_##suffix (void) \
5686 gen_op_##op##_##suffix(); \
5687 gen_op_splatw_T1_64(); \
5690 #define GEN_OP_SPE_LHE(suffix) \
5691 static inline void gen_op_spe_lhe_##suffix (void) \
5693 gen_op_spe_lh_##suffix(); \
5694 gen_op_sli16_T1_64(); \
5697 #define GEN_OP_SPE_LHX(suffix) \
5698 static inline void gen_op_spe_lhx_##suffix (void) \
5700 gen_op_spe_lh_##suffix(); \
5701 gen_op_extsh_T1_64(); \
5704 #if defined(CONFIG_USER_ONLY)
5705 GEN_OP_SPE_LHE(raw
);
5706 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, raw
);
5707 GEN_OP_SPE_LHE(le_raw
);
5708 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, le_raw
);
5709 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, raw
);
5710 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, le_raw
);
5711 GEN_OP_SPE_LHX(raw
);
5712 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, raw
);
5713 GEN_OP_SPE_LHX(le_raw
);
5714 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, le_raw
);
5715 #if defined(TARGET_PPC64)
5716 GEN_OP_SPE_LHE(64_raw
);
5717 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, 64_raw
);
5718 GEN_OP_SPE_LHE(le_64_raw
);
5719 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, le_64_raw
);
5720 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, 64_raw
);
5721 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, le_64_raw
);
5722 GEN_OP_SPE_LHX(64_raw
);
5723 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, 64_raw
);
5724 GEN_OP_SPE_LHX(le_64_raw
);
5725 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, le_64_raw
);
5728 GEN_OP_SPE_LHE(kernel
);
5729 GEN_OP_SPE_LHE(user
);
5730 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, kernel
);
5731 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, user
);
5732 GEN_OP_SPE_LHE(le_kernel
);
5733 GEN_OP_SPE_LHE(le_user
);
5734 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, le_kernel
);
5735 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, le_user
);
5736 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, kernel
);
5737 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, user
);
5738 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, le_kernel
);
5739 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, le_user
);
5740 GEN_OP_SPE_LHX(kernel
);
5741 GEN_OP_SPE_LHX(user
);
5742 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, kernel
);
5743 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, user
);
5744 GEN_OP_SPE_LHX(le_kernel
);
5745 GEN_OP_SPE_LHX(le_user
);
5746 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, le_kernel
);
5747 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, le_user
);
5748 #if defined(TARGET_PPC64)
5749 GEN_OP_SPE_LHE(64_kernel
);
5750 GEN_OP_SPE_LHE(64_user
);
5751 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, 64_kernel
);
5752 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, 64_user
);
5753 GEN_OP_SPE_LHE(le_64_kernel
);
5754 GEN_OP_SPE_LHE(le_64_user
);
5755 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, le_64_kernel
);
5756 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, le_64_user
);
5757 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, 64_kernel
);
5758 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, 64_user
);
5759 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, le_64_kernel
);
5760 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, le_64_user
);
5761 GEN_OP_SPE_LHX(64_kernel
);
5762 GEN_OP_SPE_LHX(64_user
);
5763 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, 64_kernel
);
5764 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, 64_user
);
5765 GEN_OP_SPE_LHX(le_64_kernel
);
5766 GEN_OP_SPE_LHX(le_64_user
);
5767 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, le_64_kernel
);
5768 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, le_64_user
);
5771 GEN_SPEOP_LD(hhesplat
, 1);
5772 GEN_SPEOP_LD(hhousplat
, 1);
5773 GEN_SPEOP_LD(hhossplat
, 1);
5774 GEN_SPEOP_LD(wwsplat
, 2);
5775 GEN_SPEOP_LD(whsplat
, 2);
5777 GEN_SPE(evlddx
, evldd
, 0x00, 0x0C, 0x00000000, PPC_SPE
); //
5778 GEN_SPE(evldwx
, evldw
, 0x01, 0x0C, 0x00000000, PPC_SPE
); //
5779 GEN_SPE(evldhx
, evldh
, 0x02, 0x0C, 0x00000000, PPC_SPE
); //
5780 GEN_SPE(evlhhesplatx
, evlhhesplat
, 0x04, 0x0C, 0x00000000, PPC_SPE
); //
5781 GEN_SPE(evlhhousplatx
, evlhhousplat
, 0x06, 0x0C, 0x00000000, PPC_SPE
); //
5782 GEN_SPE(evlhhossplatx
, evlhhossplat
, 0x07, 0x0C, 0x00000000, PPC_SPE
); //
5783 GEN_SPE(evlwhex
, evlwhe
, 0x08, 0x0C, 0x00000000, PPC_SPE
); //
5784 GEN_SPE(evlwhoux
, evlwhou
, 0x0A, 0x0C, 0x00000000, PPC_SPE
); //
5785 GEN_SPE(evlwhosx
, evlwhos
, 0x0B, 0x0C, 0x00000000, PPC_SPE
); //
5786 GEN_SPE(evlwwsplatx
, evlwwsplat
, 0x0C, 0x0C, 0x00000000, PPC_SPE
); //
5787 GEN_SPE(evlwhsplatx
, evlwhsplat
, 0x0E, 0x0C, 0x00000000, PPC_SPE
); //
5788 GEN_SPE(evstddx
, evstdd
, 0x10, 0x0C, 0x00000000, PPC_SPE
); //
5789 GEN_SPE(evstdwx
, evstdw
, 0x11, 0x0C, 0x00000000, PPC_SPE
); //
5790 GEN_SPE(evstdhx
, evstdh
, 0x12, 0x0C, 0x00000000, PPC_SPE
); //
5791 GEN_SPE(evstwhex
, evstwhe
, 0x18, 0x0C, 0x00000000, PPC_SPE
); //
5792 GEN_SPE(evstwhox
, evstwho
, 0x1A, 0x0C, 0x00000000, PPC_SPE
); //
5793 GEN_SPE(evstwwex
, evstwwe
, 0x1C, 0x0C, 0x00000000, PPC_SPE
); //
5794 GEN_SPE(evstwwox
, evstwwo
, 0x1E, 0x0C, 0x00000000, PPC_SPE
); //
5796 /* Multiply and add - TODO */
5798 GEN_SPE(speundef
, evmhessf
, 0x01, 0x10, 0x00000000, PPC_SPE
);
5799 GEN_SPE(speundef
, evmhossf
, 0x03, 0x10, 0x00000000, PPC_SPE
);
5800 GEN_SPE(evmheumi
, evmhesmi
, 0x04, 0x10, 0x00000000, PPC_SPE
);
5801 GEN_SPE(speundef
, evmhesmf
, 0x05, 0x10, 0x00000000, PPC_SPE
);
5802 GEN_SPE(evmhoumi
, evmhosmi
, 0x06, 0x10, 0x00000000, PPC_SPE
);
5803 GEN_SPE(speundef
, evmhosmf
, 0x07, 0x10, 0x00000000, PPC_SPE
);
5804 GEN_SPE(speundef
, evmhessfa
, 0x11, 0x10, 0x00000000, PPC_SPE
);
5805 GEN_SPE(speundef
, evmhossfa
, 0x13, 0x10, 0x00000000, PPC_SPE
);
5806 GEN_SPE(evmheumia
, evmhesmia
, 0x14, 0x10, 0x00000000, PPC_SPE
);
5807 GEN_SPE(speundef
, evmhesmfa
, 0x15, 0x10, 0x00000000, PPC_SPE
);
5808 GEN_SPE(evmhoumia
, evmhosmia
, 0x16, 0x10, 0x00000000, PPC_SPE
);
5809 GEN_SPE(speundef
, evmhosmfa
, 0x17, 0x10, 0x00000000, PPC_SPE
);
5811 GEN_SPE(speundef
, evmwhssf
, 0x03, 0x11, 0x00000000, PPC_SPE
);
5812 GEN_SPE(evmwlumi
, speundef
, 0x04, 0x11, 0x00000000, PPC_SPE
);
5813 GEN_SPE(evmwhumi
, evmwhsmi
, 0x06, 0x11, 0x00000000, PPC_SPE
);
5814 GEN_SPE(speundef
, evmwhsmf
, 0x07, 0x11, 0x00000000, PPC_SPE
);
5815 GEN_SPE(speundef
, evmwssf
, 0x09, 0x11, 0x00000000, PPC_SPE
);
5816 GEN_SPE(evmwumi
, evmwsmi
, 0x0C, 0x11, 0x00000000, PPC_SPE
);
5817 GEN_SPE(speundef
, evmwsmf
, 0x0D, 0x11, 0x00000000, PPC_SPE
);
5818 GEN_SPE(speundef
, evmwhssfa
, 0x13, 0x11, 0x00000000, PPC_SPE
);
5819 GEN_SPE(evmwlumia
, speundef
, 0x14, 0x11, 0x00000000, PPC_SPE
);
5820 GEN_SPE(evmwhumia
, evmwhsmia
, 0x16, 0x11, 0x00000000, PPC_SPE
);
5821 GEN_SPE(speundef
, evmwhsmfa
, 0x17, 0x11, 0x00000000, PPC_SPE
);
5822 GEN_SPE(speundef
, evmwssfa
, 0x19, 0x11, 0x00000000, PPC_SPE
);
5823 GEN_SPE(evmwumia
, evmwsmia
, 0x1C, 0x11, 0x00000000, PPC_SPE
);
5824 GEN_SPE(speundef
, evmwsmfa
, 0x1D, 0x11, 0x00000000, PPC_SPE
);
5826 GEN_SPE(evadduiaaw
, evaddsiaaw
, 0x00, 0x13, 0x0000F800, PPC_SPE
);
5827 GEN_SPE(evsubfusiaaw
, evsubfssiaaw
, 0x01, 0x13, 0x0000F800, PPC_SPE
);
5828 GEN_SPE(evaddumiaaw
, evaddsmiaaw
, 0x04, 0x13, 0x0000F800, PPC_SPE
);
5829 GEN_SPE(evsubfumiaaw
, evsubfsmiaaw
, 0x05, 0x13, 0x0000F800, PPC_SPE
);
5830 GEN_SPE(evdivws
, evdivwu
, 0x06, 0x13, 0x00000000, PPC_SPE
);
5831 GEN_SPE(evmra
, speundef
, 0x07, 0x13, 0x0000F800, PPC_SPE
);
5833 GEN_SPE(evmheusiaaw
, evmhessiaaw
, 0x00, 0x14, 0x00000000, PPC_SPE
);
5834 GEN_SPE(speundef
, evmhessfaaw
, 0x01, 0x14, 0x00000000, PPC_SPE
);
5835 GEN_SPE(evmhousiaaw
, evmhossiaaw
, 0x02, 0x14, 0x00000000, PPC_SPE
);
5836 GEN_SPE(speundef
, evmhossfaaw
, 0x03, 0x14, 0x00000000, PPC_SPE
);
5837 GEN_SPE(evmheumiaaw
, evmhesmiaaw
, 0x04, 0x14, 0x00000000, PPC_SPE
);
5838 GEN_SPE(speundef
, evmhesmfaaw
, 0x05, 0x14, 0x00000000, PPC_SPE
);
5839 GEN_SPE(evmhoumiaaw
, evmhosmiaaw
, 0x06, 0x14, 0x00000000, PPC_SPE
);
5840 GEN_SPE(speundef
, evmhosmfaaw
, 0x07, 0x14, 0x00000000, PPC_SPE
);
5841 GEN_SPE(evmhegumiaa
, evmhegsmiaa
, 0x14, 0x14, 0x00000000, PPC_SPE
);
5842 GEN_SPE(speundef
, evmhegsmfaa
, 0x15, 0x14, 0x00000000, PPC_SPE
);
5843 GEN_SPE(evmhogumiaa
, evmhogsmiaa
, 0x16, 0x14, 0x00000000, PPC_SPE
);
5844 GEN_SPE(speundef
, evmhogsmfaa
, 0x17, 0x14, 0x00000000, PPC_SPE
);
5846 GEN_SPE(evmwlusiaaw
, evmwlssiaaw
, 0x00, 0x15, 0x00000000, PPC_SPE
);
5847 GEN_SPE(evmwlumiaaw
, evmwlsmiaaw
, 0x04, 0x15, 0x00000000, PPC_SPE
);
5848 GEN_SPE(speundef
, evmwssfaa
, 0x09, 0x15, 0x00000000, PPC_SPE
);
5849 GEN_SPE(evmwumiaa
, evmwsmiaa
, 0x0C, 0x15, 0x00000000, PPC_SPE
);
5850 GEN_SPE(speundef
, evmwsmfaa
, 0x0D, 0x15, 0x00000000, PPC_SPE
);
5852 GEN_SPE(evmheusianw
, evmhessianw
, 0x00, 0x16, 0x00000000, PPC_SPE
);
5853 GEN_SPE(speundef
, evmhessfanw
, 0x01, 0x16, 0x00000000, PPC_SPE
);
5854 GEN_SPE(evmhousianw
, evmhossianw
, 0x02, 0x16, 0x00000000, PPC_SPE
);
5855 GEN_SPE(speundef
, evmhossfanw
, 0x03, 0x16, 0x00000000, PPC_SPE
);
5856 GEN_SPE(evmheumianw
, evmhesmianw
, 0x04, 0x16, 0x00000000, PPC_SPE
);
5857 GEN_SPE(speundef
, evmhesmfanw
, 0x05, 0x16, 0x00000000, PPC_SPE
);
5858 GEN_SPE(evmhoumianw
, evmhosmianw
, 0x06, 0x16, 0x00000000, PPC_SPE
);
5859 GEN_SPE(speundef
, evmhosmfanw
, 0x07, 0x16, 0x00000000, PPC_SPE
);
5860 GEN_SPE(evmhegumian
, evmhegsmian
, 0x14, 0x16, 0x00000000, PPC_SPE
);
5861 GEN_SPE(speundef
, evmhegsmfan
, 0x15, 0x16, 0x00000000, PPC_SPE
);
5862 GEN_SPE(evmhigumian
, evmhigsmian
, 0x16, 0x16, 0x00000000, PPC_SPE
);
5863 GEN_SPE(speundef
, evmhogsmfan
, 0x17, 0x16, 0x00000000, PPC_SPE
);
5865 GEN_SPE(evmwlusianw
, evmwlssianw
, 0x00, 0x17, 0x00000000, PPC_SPE
);
5866 GEN_SPE(evmwlumianw
, evmwlsmianw
, 0x04, 0x17, 0x00000000, PPC_SPE
);
5867 GEN_SPE(speundef
, evmwssfan
, 0x09, 0x17, 0x00000000, PPC_SPE
);
5868 GEN_SPE(evmwumian
, evmwsmian
, 0x0C, 0x17, 0x00000000, PPC_SPE
);
5869 GEN_SPE(speundef
, evmwsmfan
, 0x0D, 0x17, 0x00000000, PPC_SPE
);
5872 /*** SPE floating-point extension ***/
5873 #define GEN_SPEFPUOP_CONV(name) \
5874 static inline void gen_##name (DisasContext *ctx) \
5876 gen_op_load_gpr64_T0(rB(ctx->opcode)); \
5878 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5881 /* Single precision floating-point vectors operations */
5883 GEN_SPEOP_ARITH2(evfsadd
);
5884 GEN_SPEOP_ARITH2(evfssub
);
5885 GEN_SPEOP_ARITH2(evfsmul
);
5886 GEN_SPEOP_ARITH2(evfsdiv
);
5887 GEN_SPEOP_ARITH1(evfsabs
);
5888 GEN_SPEOP_ARITH1(evfsnabs
);
5889 GEN_SPEOP_ARITH1(evfsneg
);
5891 GEN_SPEFPUOP_CONV(evfscfui
);
5892 GEN_SPEFPUOP_CONV(evfscfsi
);
5893 GEN_SPEFPUOP_CONV(evfscfuf
);
5894 GEN_SPEFPUOP_CONV(evfscfsf
);
5895 GEN_SPEFPUOP_CONV(evfsctui
);
5896 GEN_SPEFPUOP_CONV(evfsctsi
);
5897 GEN_SPEFPUOP_CONV(evfsctuf
);
5898 GEN_SPEFPUOP_CONV(evfsctsf
);
5899 GEN_SPEFPUOP_CONV(evfsctuiz
);
5900 GEN_SPEFPUOP_CONV(evfsctsiz
);
5902 GEN_SPEOP_COMP(evfscmpgt
);
5903 GEN_SPEOP_COMP(evfscmplt
);
5904 GEN_SPEOP_COMP(evfscmpeq
);
5905 GEN_SPEOP_COMP(evfststgt
);
5906 GEN_SPEOP_COMP(evfststlt
);
5907 GEN_SPEOP_COMP(evfststeq
);
5909 /* Opcodes definitions */
5910 GEN_SPE(evfsadd
, evfssub
, 0x00, 0x0A, 0x00000000, PPC_SPEFPU
); //
5911 GEN_SPE(evfsabs
, evfsnabs
, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU
); //
5912 GEN_SPE(evfsneg
, speundef
, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU
); //
5913 GEN_SPE(evfsmul
, evfsdiv
, 0x04, 0x0A, 0x00000000, PPC_SPEFPU
); //
5914 GEN_SPE(evfscmpgt
, evfscmplt
, 0x06, 0x0A, 0x00600000, PPC_SPEFPU
); //
5915 GEN_SPE(evfscmpeq
, speundef
, 0x07, 0x0A, 0x00600000, PPC_SPEFPU
); //
5916 GEN_SPE(evfscfui
, evfscfsi
, 0x08, 0x0A, 0x00180000, PPC_SPEFPU
); //
5917 GEN_SPE(evfscfuf
, evfscfsf
, 0x09, 0x0A, 0x00180000, PPC_SPEFPU
); //
5918 GEN_SPE(evfsctui
, evfsctsi
, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU
); //
5919 GEN_SPE(evfsctuf
, evfsctsf
, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU
); //
5920 GEN_SPE(evfsctuiz
, speundef
, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU
); //
5921 GEN_SPE(evfsctsiz
, speundef
, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU
); //
5922 GEN_SPE(evfststgt
, evfststlt
, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU
); //
5923 GEN_SPE(evfststeq
, speundef
, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU
); //
5925 /* Single precision floating-point operations */
5927 GEN_SPEOP_ARITH2(efsadd
);
5928 GEN_SPEOP_ARITH2(efssub
);
5929 GEN_SPEOP_ARITH2(efsmul
);
5930 GEN_SPEOP_ARITH2(efsdiv
);
5931 GEN_SPEOP_ARITH1(efsabs
);
5932 GEN_SPEOP_ARITH1(efsnabs
);
5933 GEN_SPEOP_ARITH1(efsneg
);
5935 GEN_SPEFPUOP_CONV(efscfui
);
5936 GEN_SPEFPUOP_CONV(efscfsi
);
5937 GEN_SPEFPUOP_CONV(efscfuf
);
5938 GEN_SPEFPUOP_CONV(efscfsf
);
5939 GEN_SPEFPUOP_CONV(efsctui
);
5940 GEN_SPEFPUOP_CONV(efsctsi
);
5941 GEN_SPEFPUOP_CONV(efsctuf
);
5942 GEN_SPEFPUOP_CONV(efsctsf
);
5943 GEN_SPEFPUOP_CONV(efsctuiz
);
5944 GEN_SPEFPUOP_CONV(efsctsiz
);
5945 GEN_SPEFPUOP_CONV(efscfd
);
5947 GEN_SPEOP_COMP(efscmpgt
);
5948 GEN_SPEOP_COMP(efscmplt
);
5949 GEN_SPEOP_COMP(efscmpeq
);
5950 GEN_SPEOP_COMP(efststgt
);
5951 GEN_SPEOP_COMP(efststlt
);
5952 GEN_SPEOP_COMP(efststeq
);
5954 /* Opcodes definitions */
5955 GEN_SPE(efsadd
, efssub
, 0x00, 0x0A, 0x00000000, PPC_SPEFPU
); //
5956 GEN_SPE(efsabs
, efsnabs
, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU
); //
5957 GEN_SPE(efsneg
, speundef
, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU
); //
5958 GEN_SPE(efsmul
, efsdiv
, 0x04, 0x0B, 0x00000000, PPC_SPEFPU
); //
5959 GEN_SPE(efscmpgt
, efscmplt
, 0x06, 0x0B, 0x00600000, PPC_SPEFPU
); //
5960 GEN_SPE(efscmpeq
, efscfd
, 0x07, 0x0B, 0x00600000, PPC_SPEFPU
); //
5961 GEN_SPE(efscfui
, efscfsi
, 0x08, 0x0B, 0x00180000, PPC_SPEFPU
); //
5962 GEN_SPE(efscfuf
, efscfsf
, 0x09, 0x0B, 0x00180000, PPC_SPEFPU
); //
5963 GEN_SPE(efsctui
, efsctsi
, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU
); //
5964 GEN_SPE(efsctuf
, efsctsf
, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU
); //
5965 GEN_SPE(efsctuiz
, efsctsiz
, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU
); //
5966 GEN_SPE(efststgt
, efststlt
, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU
); //
5967 GEN_SPE(efststeq
, speundef
, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU
); //
5969 /* Double precision floating-point operations */
5971 GEN_SPEOP_ARITH2(efdadd
);
5972 GEN_SPEOP_ARITH2(efdsub
);
5973 GEN_SPEOP_ARITH2(efdmul
);
5974 GEN_SPEOP_ARITH2(efddiv
);
5975 GEN_SPEOP_ARITH1(efdabs
);
5976 GEN_SPEOP_ARITH1(efdnabs
);
5977 GEN_SPEOP_ARITH1(efdneg
);
5980 GEN_SPEFPUOP_CONV(efdcfui
);
5981 GEN_SPEFPUOP_CONV(efdcfsi
);
5982 GEN_SPEFPUOP_CONV(efdcfuf
);
5983 GEN_SPEFPUOP_CONV(efdcfsf
);
5984 GEN_SPEFPUOP_CONV(efdctui
);
5985 GEN_SPEFPUOP_CONV(efdctsi
);
5986 GEN_SPEFPUOP_CONV(efdctuf
);
5987 GEN_SPEFPUOP_CONV(efdctsf
);
5988 GEN_SPEFPUOP_CONV(efdctuiz
);
5989 GEN_SPEFPUOP_CONV(efdctsiz
);
5990 GEN_SPEFPUOP_CONV(efdcfs
);
5991 GEN_SPEFPUOP_CONV(efdcfuid
);
5992 GEN_SPEFPUOP_CONV(efdcfsid
);
5993 GEN_SPEFPUOP_CONV(efdctuidz
);
5994 GEN_SPEFPUOP_CONV(efdctsidz
);
5996 GEN_SPEOP_COMP(efdcmpgt
);
5997 GEN_SPEOP_COMP(efdcmplt
);
5998 GEN_SPEOP_COMP(efdcmpeq
);
5999 GEN_SPEOP_COMP(efdtstgt
);
6000 GEN_SPEOP_COMP(efdtstlt
);
6001 GEN_SPEOP_COMP(efdtsteq
);
6003 /* Opcodes definitions */
6004 GEN_SPE(efdadd
, efdsub
, 0x10, 0x0B, 0x00000000, PPC_SPEFPU
); //
6005 GEN_SPE(efdcfuid
, efdcfsid
, 0x11, 0x0B, 0x00180000, PPC_SPEFPU
); //
6006 GEN_SPE(efdabs
, efdnabs
, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU
); //
6007 GEN_SPE(efdneg
, speundef
, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU
); //
6008 GEN_SPE(efdmul
, efddiv
, 0x14, 0x0B, 0x00000000, PPC_SPEFPU
); //
6009 GEN_SPE(efdctuidz
, efdctsidz
, 0x15, 0x0B, 0x00180000, PPC_SPEFPU
); //
6010 GEN_SPE(efdcmpgt
, efdcmplt
, 0x16, 0x0B, 0x00600000, PPC_SPEFPU
); //
6011 GEN_SPE(efdcmpeq
, efdcfs
, 0x17, 0x0B, 0x00600000, PPC_SPEFPU
); //
6012 GEN_SPE(efdcfui
, efdcfsi
, 0x18, 0x0B, 0x00180000, PPC_SPEFPU
); //
6013 GEN_SPE(efdcfuf
, efdcfsf
, 0x19, 0x0B, 0x00180000, PPC_SPEFPU
); //
6014 GEN_SPE(efdctui
, efdctsi
, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU
); //
6015 GEN_SPE(efdctuf
, efdctsf
, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU
); //
6016 GEN_SPE(efdctuiz
, speundef
, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU
); //
6017 GEN_SPE(efdctsiz
, speundef
, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU
); //
6018 GEN_SPE(efdtstgt
, efdtstlt
, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU
); //
6019 GEN_SPE(efdtsteq
, speundef
, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU
); //
6022 /* End opcode list */
6023 GEN_OPCODE_MARK(end
);
6025 #include "translate_init.c"
6027 /*****************************************************************************/
6028 /* Misc PowerPC helpers */
6029 static inline uint32_t load_xer (CPUState
*env
)
6031 return (xer_so
<< XER_SO
) |
6032 (xer_ov
<< XER_OV
) |
6033 (xer_ca
<< XER_CA
) |
6034 (xer_bc
<< XER_BC
) |
6035 (xer_cmp
<< XER_CMP
);
6038 void cpu_dump_state (CPUState
*env
, FILE *f
,
6039 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
6042 #if defined(TARGET_PPC64) || 1
6054 cpu_fprintf(f
, "NIP " ADDRX
" LR " ADDRX
" CTR " ADDRX
"\n",
6055 env
->nip
, env
->lr
, env
->ctr
);
6056 cpu_fprintf(f
, "MSR " REGX FILL
" XER %08x "
6057 #if !defined(NO_TIMER_DUMP)
6059 #if !defined(CONFIG_USER_ONLY)
6064 do_load_msr(env
), load_xer(env
)
6065 #if !defined(NO_TIMER_DUMP)
6066 , cpu_ppc_load_tbu(env
), cpu_ppc_load_tbl(env
)
6067 #if !defined(CONFIG_USER_ONLY)
6068 , cpu_ppc_load_decr(env
)
6072 for (i
= 0; i
< 32; i
++) {
6073 if ((i
& (RGPL
- 1)) == 0)
6074 cpu_fprintf(f
, "GPR%02d", i
);
6075 cpu_fprintf(f
, " " REGX
, (target_ulong
)env
->gpr
[i
]);
6076 if ((i
& (RGPL
- 1)) == (RGPL
- 1))
6077 cpu_fprintf(f
, "\n");
6079 cpu_fprintf(f
, "CR ");
6080 for (i
= 0; i
< 8; i
++)
6081 cpu_fprintf(f
, "%01x", env
->crf
[i
]);
6082 cpu_fprintf(f
, " [");
6083 for (i
= 0; i
< 8; i
++) {
6085 if (env
->crf
[i
] & 0x08)
6087 else if (env
->crf
[i
] & 0x04)
6089 else if (env
->crf
[i
] & 0x02)
6091 cpu_fprintf(f
, " %c%c", a
, env
->crf
[i
] & 0x01 ? 'O' : ' ');
6093 cpu_fprintf(f
, " ] " FILL
"RES " REGX
"\n", env
->reserve
);
6094 for (i
= 0; i
< 32; i
++) {
6095 if ((i
& (RFPL
- 1)) == 0)
6096 cpu_fprintf(f
, "FPR%02d", i
);
6097 cpu_fprintf(f
, " %016" PRIx64
, *((uint64_t *)&env
->fpr
[i
]));
6098 if ((i
& (RFPL
- 1)) == (RFPL
- 1))
6099 cpu_fprintf(f
, "\n");
6101 cpu_fprintf(f
, "SRR0 " REGX
" SRR1 " REGX
" " FILL FILL FILL
6103 env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
], env
->sdr1
);
6110 void cpu_dump_statistics (CPUState
*env
, FILE*f
,
6111 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
6114 #if defined(DO_PPC_STATISTICS)
6115 opc_handler_t
**t1
, **t2
, **t3
, *handler
;
6119 for (op1
= 0; op1
< 64; op1
++) {
6121 if (is_indirect_opcode(handler
)) {
6122 t2
= ind_table(handler
);
6123 for (op2
= 0; op2
< 32; op2
++) {
6125 if (is_indirect_opcode(handler
)) {
6126 t3
= ind_table(handler
);
6127 for (op3
= 0; op3
< 32; op3
++) {
6129 if (handler
->count
== 0)
6131 cpu_fprintf(f
, "%02x %02x %02x (%02x %04d) %16s: "
6133 op1
, op2
, op3
, op1
, (op3
<< 5) | op2
,
6135 handler
->count
, handler
->count
);
6138 if (handler
->count
== 0)
6140 cpu_fprintf(f
, "%02x %02x (%02x %04d) %16s: "
6142 op1
, op2
, op1
, op2
, handler
->oname
,
6143 handler
->count
, handler
->count
);
6147 if (handler
->count
== 0)
6149 cpu_fprintf(f
, "%02x (%02x ) %16s: %016llx %lld\n",
6150 op1
, op1
, handler
->oname
,
6151 handler
->count
, handler
->count
);
6157 /*****************************************************************************/
6158 static inline int gen_intermediate_code_internal (CPUState
*env
,
6159 TranslationBlock
*tb
,
6162 DisasContext ctx
, *ctxp
= &ctx
;
6163 opc_handler_t
**table
, *handler
;
6164 target_ulong pc_start
;
6165 uint16_t *gen_opc_end
;
6169 gen_opc_ptr
= gen_opc_buf
;
6170 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
6171 gen_opparam_ptr
= gen_opparam_buf
;
6175 ctx
.exception
= POWERPC_EXCP_NONE
;
6176 ctx
.spr_cb
= env
->spr_cb
;
6177 #if defined(CONFIG_USER_ONLY)
6178 ctx
.mem_idx
= msr_le
;
6179 #if defined(TARGET_PPC64)
6180 ctx
.mem_idx
|= msr_sf
<< 1;
6183 #if defined(TARGET_PPC64H)
6184 if (msr_pr
== 0 && msr_hv
== 1)
6188 ctx
.supervisor
= 1 - msr_pr
;
6189 ctx
.mem_idx
= ((1 - msr_pr
) << 1) | msr_le
;
6190 #if defined(TARGET_PPC64)
6191 ctx
.mem_idx
|= msr_sf
<< 2;
6194 #if defined(TARGET_PPC64)
6195 ctx
.sf_mode
= msr_sf
;
6197 ctx
.fpu_enabled
= msr_fp
;
6198 #if defined(TARGET_PPCEMB)
6199 ctx
.spe_enabled
= msr_spe
;
6201 ctx
.singlestep_enabled
= env
->singlestep_enabled
;
6202 #if defined (DO_SINGLE_STEP) && 0
6203 /* Single step trace mode */
6206 /* Set env in case of segfault during code fetch */
6207 while (ctx
.exception
== POWERPC_EXCP_NONE
&& gen_opc_ptr
< gen_opc_end
) {
6208 if (unlikely(env
->nb_breakpoints
> 0)) {
6209 for (j
= 0; j
< env
->nb_breakpoints
; j
++) {
6210 if (env
->breakpoints
[j
] == ctx
.nip
) {
6211 gen_update_nip(&ctx
, ctx
.nip
);
6217 if (unlikely(search_pc
)) {
6218 j
= gen_opc_ptr
- gen_opc_buf
;
6222 gen_opc_instr_start
[lj
++] = 0;
6223 gen_opc_pc
[lj
] = ctx
.nip
;
6224 gen_opc_instr_start
[lj
] = 1;
6227 #if defined PPC_DEBUG_DISAS
6228 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
6229 fprintf(logfile
, "----------------\n");
6230 fprintf(logfile
, "nip=" ADDRX
" super=%d ir=%d\n",
6231 ctx
.nip
, 1 - msr_pr
, msr_ir
);
6234 ctx
.opcode
= ldl_code(ctx
.nip
);
6236 ctx
.opcode
= ((ctx
.opcode
& 0xFF000000) >> 24) |
6237 ((ctx
.opcode
& 0x00FF0000) >> 8) |
6238 ((ctx
.opcode
& 0x0000FF00) << 8) |
6239 ((ctx
.opcode
& 0x000000FF) << 24);
6241 #if defined PPC_DEBUG_DISAS
6242 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
6243 fprintf(logfile
, "translate opcode %08x (%02x %02x %02x) (%s)\n",
6244 ctx
.opcode
, opc1(ctx
.opcode
), opc2(ctx
.opcode
),
6245 opc3(ctx
.opcode
), msr_le
? "little" : "big");
6249 table
= env
->opcodes
;
6250 handler
= table
[opc1(ctx
.opcode
)];
6251 if (is_indirect_opcode(handler
)) {
6252 table
= ind_table(handler
);
6253 handler
= table
[opc2(ctx
.opcode
)];
6254 if (is_indirect_opcode(handler
)) {
6255 table
= ind_table(handler
);
6256 handler
= table
[opc3(ctx
.opcode
)];
6259 /* Is opcode *REALLY* valid ? */
6260 if (unlikely(handler
->handler
== &gen_invalid
)) {
6261 if (loglevel
!= 0) {
6262 fprintf(logfile
, "invalid/unsupported opcode: "
6263 "%02x - %02x - %02x (%08x) 0x" ADDRX
" %d\n",
6264 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
6265 opc3(ctx
.opcode
), ctx
.opcode
, ctx
.nip
- 4, msr_ir
);
6267 printf("invalid/unsupported opcode: "
6268 "%02x - %02x - %02x (%08x) 0x" ADDRX
" %d\n",
6269 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
6270 opc3(ctx
.opcode
), ctx
.opcode
, ctx
.nip
- 4, msr_ir
);
6273 if (unlikely((ctx
.opcode
& handler
->inval
) != 0)) {
6274 if (loglevel
!= 0) {
6275 fprintf(logfile
, "invalid bits: %08x for opcode: "
6276 "%02x - %02x - %02x (%08x) 0x" ADDRX
"\n",
6277 ctx
.opcode
& handler
->inval
, opc1(ctx
.opcode
),
6278 opc2(ctx
.opcode
), opc3(ctx
.opcode
),
6279 ctx
.opcode
, ctx
.nip
- 4);
6281 printf("invalid bits: %08x for opcode: "
6282 "%02x - %02x - %02x (%08x) 0x" ADDRX
"\n",
6283 ctx
.opcode
& handler
->inval
, opc1(ctx
.opcode
),
6284 opc2(ctx
.opcode
), opc3(ctx
.opcode
),
6285 ctx
.opcode
, ctx
.nip
- 4);
6287 GEN_EXCP_INVAL(ctxp
);
6291 (*(handler
->handler
))(&ctx
);
6292 #if defined(DO_PPC_STATISTICS)
6295 /* Check trace mode exceptions */
6296 #if 0 // XXX: buggy on embedded PowerPC
6297 if (unlikely((msr_be
&& ctx
.exception
== POWERPC_EXCP_BRANCH
) ||
6298 /* Check in single step trace mode
6299 * we need to stop except if:
6300 * - rfi, trap or syscall
6301 * - first instruction of an exception handler
6303 (msr_se
&& (ctx
.nip
< 0x100 ||
6305 (ctx
.nip
& 0xFC) != 0x04) &&
6306 #if defined(CONFIG_USER_ONLY)
6307 ctx
.exception
!= POWERPC_EXCP_SYSCALL_USER
&&
6309 ctx
.exception
!= POWERPC_EXCP_SYSCALL
&&
6311 ctx
.exception
!= POWERPC_EXCP_TRAP
))) {
6312 GEN_EXCP(ctxp
, POWERPC_EXCP_TRACE
, 0);
6315 /* if we reach a page boundary or are single stepping, stop
6318 if (unlikely(((ctx
.nip
& (TARGET_PAGE_SIZE
- 1)) == 0) ||
6319 (env
->singlestep_enabled
))) {
6322 #if defined (DO_SINGLE_STEP)
6326 if (ctx
.exception
== POWERPC_EXCP_NONE
) {
6327 gen_goto_tb(&ctx
, 0, ctx
.nip
);
6328 } else if (ctx
.exception
!= POWERPC_EXCP_BRANCH
) {
6330 /* Generate the return instruction */
6333 *gen_opc_ptr
= INDEX_op_end
;
6334 if (unlikely(search_pc
)) {
6335 j
= gen_opc_ptr
- gen_opc_buf
;
6338 gen_opc_instr_start
[lj
++] = 0;
6340 tb
->size
= ctx
.nip
- pc_start
;
6342 #if defined(DEBUG_DISAS)
6343 if (loglevel
& CPU_LOG_TB_CPU
) {
6344 fprintf(logfile
, "---------------- excp: %04x\n", ctx
.exception
);
6345 cpu_dump_state(env
, logfile
, fprintf
, 0);
6347 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
6349 flags
= env
->bfd_mach
;
6350 flags
|= msr_le
<< 16;
6351 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
6352 target_disas(logfile
, pc_start
, ctx
.nip
- pc_start
, flags
);
6353 fprintf(logfile
, "\n");
6355 if (loglevel
& CPU_LOG_TB_OP
) {
6356 fprintf(logfile
, "OP:\n");
6357 dump_ops(gen_opc_buf
, gen_opparam_buf
);
6358 fprintf(logfile
, "\n");
6364 int gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
6366 return gen_intermediate_code_internal(env
, tb
, 0);
6369 int gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
6371 return gen_intermediate_code_internal(env
, tb
, 1);