2 * PowerPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
30 #include "qemu-common.h"
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
40 /* Include definitions for instructions classes and implementations flags */
41 //#define DO_SINGLE_STEP
42 //#define PPC_DEBUG_DISAS
43 //#define DO_PPC_STATISTICS
45 #ifdef PPC_DEBUG_DISAS
46 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
48 # define LOG_DISAS(...) do { } while (0)
50 /*****************************************************************************/
51 /* Code translation helpers */
53 /* global register indexes */
54 static TCGv_ptr cpu_env
;
55 static char cpu_reg_names
[10*3 + 22*4 /* GPR */
56 #if !defined(TARGET_PPC64)
57 + 10*4 + 22*5 /* SPE GPRh */
59 + 10*4 + 22*5 /* FPR */
60 + 2*(10*6 + 22*7) /* AVRh, AVRl */
62 static TCGv cpu_gpr
[32];
63 #if !defined(TARGET_PPC64)
64 static TCGv cpu_gprh
[32];
66 static TCGv_i64 cpu_fpr
[32];
67 static TCGv_i64 cpu_avrh
[32], cpu_avrl
[32];
68 static TCGv_i32 cpu_crf
[8];
74 static TCGv cpu_reserve
;
75 static TCGv_i32 cpu_fpscr
;
76 static TCGv_i32 cpu_access_type
;
78 #include "gen-icount.h"
80 void ppc_translate_init(void)
84 static int done_init
= 0;
89 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
93 for (i
= 0; i
< 8; i
++) {
94 sprintf(p
, "crf%d", i
);
95 cpu_crf
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
96 offsetof(CPUState
, crf
[i
]), p
);
100 for (i
= 0; i
< 32; i
++) {
101 sprintf(p
, "r%d", i
);
102 cpu_gpr
[i
] = tcg_global_mem_new(TCG_AREG0
,
103 offsetof(CPUState
, gpr
[i
]), p
);
104 p
+= (i
< 10) ? 3 : 4;
105 #if !defined(TARGET_PPC64)
106 sprintf(p
, "r%dH", i
);
107 cpu_gprh
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
108 offsetof(CPUState
, gprh
[i
]), p
);
109 p
+= (i
< 10) ? 4 : 5;
112 sprintf(p
, "fp%d", i
);
113 cpu_fpr
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
114 offsetof(CPUState
, fpr
[i
]), p
);
115 p
+= (i
< 10) ? 4 : 5;
117 sprintf(p
, "avr%dH", i
);
118 #ifdef WORDS_BIGENDIAN
119 cpu_avrh
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
120 offsetof(CPUState
, avr
[i
].u64
[0]), p
);
122 cpu_avrh
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
123 offsetof(CPUState
, avr
[i
].u64
[1]), p
);
125 p
+= (i
< 10) ? 6 : 7;
127 sprintf(p
, "avr%dL", i
);
128 #ifdef WORDS_BIGENDIAN
129 cpu_avrl
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
130 offsetof(CPUState
, avr
[i
].u64
[1]), p
);
132 cpu_avrl
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
133 offsetof(CPUState
, avr
[i
].u64
[0]), p
);
135 p
+= (i
< 10) ? 6 : 7;
138 cpu_nip
= tcg_global_mem_new(TCG_AREG0
,
139 offsetof(CPUState
, nip
), "nip");
141 cpu_msr
= tcg_global_mem_new(TCG_AREG0
,
142 offsetof(CPUState
, msr
), "msr");
144 cpu_ctr
= tcg_global_mem_new(TCG_AREG0
,
145 offsetof(CPUState
, ctr
), "ctr");
147 cpu_lr
= tcg_global_mem_new(TCG_AREG0
,
148 offsetof(CPUState
, lr
), "lr");
150 cpu_xer
= tcg_global_mem_new(TCG_AREG0
,
151 offsetof(CPUState
, xer
), "xer");
153 cpu_reserve
= tcg_global_mem_new(TCG_AREG0
,
154 offsetof(CPUState
, reserve
), "reserve");
156 cpu_fpscr
= tcg_global_mem_new_i32(TCG_AREG0
,
157 offsetof(CPUState
, fpscr
), "fpscr");
159 cpu_access_type
= tcg_global_mem_new_i32(TCG_AREG0
,
160 offsetof(CPUState
, access_type
), "access_type");
162 /* register helpers */
169 /* internal defines */
170 typedef struct DisasContext
{
171 struct TranslationBlock
*tb
;
175 /* Routine used to access memory */
178 /* Translation flags */
180 #if defined(TARGET_PPC64)
186 ppc_spr_t
*spr_cb
; /* Needed to check rights for mfspr/mtspr */
187 int singlestep_enabled
;
190 struct opc_handler_t
{
193 /* instruction type */
196 void (*handler
)(DisasContext
*ctx
);
197 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
200 #if defined(DO_PPC_STATISTICS)
205 static always_inline
void gen_reset_fpstatus (void)
207 #ifdef CONFIG_SOFTFLOAT
208 gen_helper_reset_fpstatus();
212 static always_inline
void gen_compute_fprf (TCGv_i64 arg
, int set_fprf
, int set_rc
)
214 TCGv_i32 t0
= tcg_temp_new_i32();
217 /* This case might be optimized later */
218 tcg_gen_movi_i32(t0
, 1);
219 gen_helper_compute_fprf(t0
, arg
, t0
);
220 if (unlikely(set_rc
)) {
221 tcg_gen_mov_i32(cpu_crf
[1], t0
);
223 gen_helper_float_check_status();
224 } else if (unlikely(set_rc
)) {
225 /* We always need to compute fpcc */
226 tcg_gen_movi_i32(t0
, 0);
227 gen_helper_compute_fprf(t0
, arg
, t0
);
228 tcg_gen_mov_i32(cpu_crf
[1], t0
);
231 tcg_temp_free_i32(t0
);
234 static always_inline
void gen_set_access_type (DisasContext
*ctx
, int access_type
)
236 if (ctx
->access_type
!= access_type
) {
237 tcg_gen_movi_i32(cpu_access_type
, access_type
);
238 ctx
->access_type
= access_type
;
242 static always_inline
void gen_update_nip (DisasContext
*ctx
, target_ulong nip
)
244 #if defined(TARGET_PPC64)
246 tcg_gen_movi_tl(cpu_nip
, nip
);
249 tcg_gen_movi_tl(cpu_nip
, (uint32_t)nip
);
252 static always_inline
void gen_exception_err (DisasContext
*ctx
, uint32_t excp
, uint32_t error
)
255 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
256 gen_update_nip(ctx
, ctx
->nip
);
258 t0
= tcg_const_i32(excp
);
259 t1
= tcg_const_i32(error
);
260 gen_helper_raise_exception_err(t0
, t1
);
261 tcg_temp_free_i32(t0
);
262 tcg_temp_free_i32(t1
);
263 ctx
->exception
= (excp
);
266 static always_inline
void gen_exception (DisasContext
*ctx
, uint32_t excp
)
269 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
270 gen_update_nip(ctx
, ctx
->nip
);
272 t0
= tcg_const_i32(excp
);
273 gen_helper_raise_exception(t0
);
274 tcg_temp_free_i32(t0
);
275 ctx
->exception
= (excp
);
278 static always_inline
void gen_debug_exception (DisasContext
*ctx
)
282 if (ctx
->exception
!= POWERPC_EXCP_BRANCH
)
283 gen_update_nip(ctx
, ctx
->nip
);
284 t0
= tcg_const_i32(EXCP_DEBUG
);
285 gen_helper_raise_exception(t0
);
286 tcg_temp_free_i32(t0
);
289 static always_inline
void gen_inval_exception (DisasContext
*ctx
, uint32_t error
)
291 gen_exception_err(ctx
, POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_INVAL
| error
);
294 /* Stop translation */
295 static always_inline
void gen_stop_exception (DisasContext
*ctx
)
297 gen_update_nip(ctx
, ctx
->nip
);
298 ctx
->exception
= POWERPC_EXCP_STOP
;
301 /* No need to update nip here, as execution flow will change */
302 static always_inline
void gen_sync_exception (DisasContext
*ctx
)
304 ctx
->exception
= POWERPC_EXCP_SYNC
;
307 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
308 static void gen_##name (DisasContext *ctx); \
309 GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
310 static void gen_##name (DisasContext *ctx)
312 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
313 static void gen_##name (DisasContext *ctx); \
314 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
315 static void gen_##name (DisasContext *ctx)
317 typedef struct opcode_t
{
318 unsigned char opc1
, opc2
, opc3
;
319 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
320 unsigned char pad
[5];
322 unsigned char pad
[1];
324 opc_handler_t handler
;
328 /*****************************************************************************/
329 /*** Instruction decoding ***/
330 #define EXTRACT_HELPER(name, shift, nb) \
331 static always_inline uint32_t name (uint32_t opcode) \
333 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
336 #define EXTRACT_SHELPER(name, shift, nb) \
337 static always_inline int32_t name (uint32_t opcode) \
339 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
343 EXTRACT_HELPER(opc1
, 26, 6);
345 EXTRACT_HELPER(opc2
, 1, 5);
347 EXTRACT_HELPER(opc3
, 6, 5);
348 /* Update Cr0 flags */
349 EXTRACT_HELPER(Rc
, 0, 1);
351 EXTRACT_HELPER(rD
, 21, 5);
353 EXTRACT_HELPER(rS
, 21, 5);
355 EXTRACT_HELPER(rA
, 16, 5);
357 EXTRACT_HELPER(rB
, 11, 5);
359 EXTRACT_HELPER(rC
, 6, 5);
361 EXTRACT_HELPER(crfD
, 23, 3);
362 EXTRACT_HELPER(crfS
, 18, 3);
363 EXTRACT_HELPER(crbD
, 21, 5);
364 EXTRACT_HELPER(crbA
, 16, 5);
365 EXTRACT_HELPER(crbB
, 11, 5);
367 EXTRACT_HELPER(_SPR
, 11, 10);
368 static always_inline
uint32_t SPR (uint32_t opcode
)
370 uint32_t sprn
= _SPR(opcode
);
372 return ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
374 /*** Get constants ***/
375 EXTRACT_HELPER(IMM
, 12, 8);
376 /* 16 bits signed immediate value */
377 EXTRACT_SHELPER(SIMM
, 0, 16);
378 /* 16 bits unsigned immediate value */
379 EXTRACT_HELPER(UIMM
, 0, 16);
380 /* 5 bits signed immediate value */
381 EXTRACT_HELPER(SIMM5
, 16, 5);
382 /* 5 bits signed immediate value */
383 EXTRACT_HELPER(UIMM5
, 16, 5);
385 EXTRACT_HELPER(NB
, 11, 5);
387 EXTRACT_HELPER(SH
, 11, 5);
388 /* Vector shift count */
389 EXTRACT_HELPER(VSH
, 6, 4);
391 EXTRACT_HELPER(MB
, 6, 5);
393 EXTRACT_HELPER(ME
, 1, 5);
395 EXTRACT_HELPER(TO
, 21, 5);
397 EXTRACT_HELPER(CRM
, 12, 8);
398 EXTRACT_HELPER(FM
, 17, 8);
399 EXTRACT_HELPER(SR
, 16, 4);
400 EXTRACT_HELPER(FPIMM
, 12, 4);
402 /*** Jump target decoding ***/
404 EXTRACT_SHELPER(d
, 0, 16);
405 /* Immediate address */
406 static always_inline target_ulong
LI (uint32_t opcode
)
408 return (opcode
>> 0) & 0x03FFFFFC;
411 static always_inline
uint32_t BD (uint32_t opcode
)
413 return (opcode
>> 0) & 0xFFFC;
416 EXTRACT_HELPER(BO
, 21, 5);
417 EXTRACT_HELPER(BI
, 16, 5);
418 /* Absolute/relative address */
419 EXTRACT_HELPER(AA
, 1, 1);
421 EXTRACT_HELPER(LK
, 0, 1);
423 /* Create a mask between <start> and <end> bits */
424 static always_inline target_ulong
MASK (uint32_t start
, uint32_t end
)
428 #if defined(TARGET_PPC64)
429 if (likely(start
== 0)) {
430 ret
= UINT64_MAX
<< (63 - end
);
431 } else if (likely(end
== 63)) {
432 ret
= UINT64_MAX
>> start
;
435 if (likely(start
== 0)) {
436 ret
= UINT32_MAX
<< (31 - end
);
437 } else if (likely(end
== 31)) {
438 ret
= UINT32_MAX
>> start
;
442 ret
= (((target_ulong
)(-1ULL)) >> (start
)) ^
443 (((target_ulong
)(-1ULL) >> (end
)) >> 1);
444 if (unlikely(start
> end
))
451 /*****************************************************************************/
452 /* PowerPC Instructions types definitions */
454 PPC_NONE
= 0x0000000000000000ULL
,
455 /* PowerPC base instructions set */
456 PPC_INSNS_BASE
= 0x0000000000000001ULL
,
457 /* integer operations instructions */
458 #define PPC_INTEGER PPC_INSNS_BASE
459 /* flow control instructions */
460 #define PPC_FLOW PPC_INSNS_BASE
461 /* virtual memory instructions */
462 #define PPC_MEM PPC_INSNS_BASE
463 /* ld/st with reservation instructions */
464 #define PPC_RES PPC_INSNS_BASE
465 /* spr/msr access instructions */
466 #define PPC_MISC PPC_INSNS_BASE
467 /* Deprecated instruction sets */
468 /* Original POWER instruction set */
469 PPC_POWER
= 0x0000000000000002ULL
,
470 /* POWER2 instruction set extension */
471 PPC_POWER2
= 0x0000000000000004ULL
,
472 /* Power RTC support */
473 PPC_POWER_RTC
= 0x0000000000000008ULL
,
474 /* Power-to-PowerPC bridge (601) */
475 PPC_POWER_BR
= 0x0000000000000010ULL
,
476 /* 64 bits PowerPC instruction set */
477 PPC_64B
= 0x0000000000000020ULL
,
478 /* New 64 bits extensions (PowerPC 2.0x) */
479 PPC_64BX
= 0x0000000000000040ULL
,
480 /* 64 bits hypervisor extensions */
481 PPC_64H
= 0x0000000000000080ULL
,
482 /* New wait instruction (PowerPC 2.0x) */
483 PPC_WAIT
= 0x0000000000000100ULL
,
484 /* Time base mftb instruction */
485 PPC_MFTB
= 0x0000000000000200ULL
,
487 /* Fixed-point unit extensions */
488 /* PowerPC 602 specific */
489 PPC_602_SPEC
= 0x0000000000000400ULL
,
490 /* isel instruction */
491 PPC_ISEL
= 0x0000000000000800ULL
,
492 /* popcntb instruction */
493 PPC_POPCNTB
= 0x0000000000001000ULL
,
494 /* string load / store */
495 PPC_STRING
= 0x0000000000002000ULL
,
497 /* Floating-point unit extensions */
498 /* Optional floating point instructions */
499 PPC_FLOAT
= 0x0000000000010000ULL
,
500 /* New floating-point extensions (PowerPC 2.0x) */
501 PPC_FLOAT_EXT
= 0x0000000000020000ULL
,
502 PPC_FLOAT_FSQRT
= 0x0000000000040000ULL
,
503 PPC_FLOAT_FRES
= 0x0000000000080000ULL
,
504 PPC_FLOAT_FRSQRTE
= 0x0000000000100000ULL
,
505 PPC_FLOAT_FRSQRTES
= 0x0000000000200000ULL
,
506 PPC_FLOAT_FSEL
= 0x0000000000400000ULL
,
507 PPC_FLOAT_STFIWX
= 0x0000000000800000ULL
,
509 /* Vector/SIMD extensions */
510 /* Altivec support */
511 PPC_ALTIVEC
= 0x0000000001000000ULL
,
512 /* PowerPC 2.03 SPE extension */
513 PPC_SPE
= 0x0000000002000000ULL
,
514 /* PowerPC 2.03 SPE single-precision floating-point extension */
515 PPC_SPE_SINGLE
= 0x0000000004000000ULL
,
516 /* PowerPC 2.03 SPE double-precision floating-point extension */
517 PPC_SPE_DOUBLE
= 0x0000000008000000ULL
,
519 /* Optional memory control instructions */
520 PPC_MEM_TLBIA
= 0x0000000010000000ULL
,
521 PPC_MEM_TLBIE
= 0x0000000020000000ULL
,
522 PPC_MEM_TLBSYNC
= 0x0000000040000000ULL
,
523 /* sync instruction */
524 PPC_MEM_SYNC
= 0x0000000080000000ULL
,
525 /* eieio instruction */
526 PPC_MEM_EIEIO
= 0x0000000100000000ULL
,
528 /* Cache control instructions */
529 PPC_CACHE
= 0x0000000200000000ULL
,
530 /* icbi instruction */
531 PPC_CACHE_ICBI
= 0x0000000400000000ULL
,
532 /* dcbz instruction with fixed cache line size */
533 PPC_CACHE_DCBZ
= 0x0000000800000000ULL
,
534 /* dcbz instruction with tunable cache line size */
535 PPC_CACHE_DCBZT
= 0x0000001000000000ULL
,
536 /* dcba instruction */
537 PPC_CACHE_DCBA
= 0x0000002000000000ULL
,
538 /* Freescale cache locking instructions */
539 PPC_CACHE_LOCK
= 0x0000004000000000ULL
,
541 /* MMU related extensions */
542 /* external control instructions */
543 PPC_EXTERN
= 0x0000010000000000ULL
,
544 /* segment register access instructions */
545 PPC_SEGMENT
= 0x0000020000000000ULL
,
546 /* PowerPC 6xx TLB management instructions */
547 PPC_6xx_TLB
= 0x0000040000000000ULL
,
548 /* PowerPC 74xx TLB management instructions */
549 PPC_74xx_TLB
= 0x0000080000000000ULL
,
550 /* PowerPC 40x TLB management instructions */
551 PPC_40x_TLB
= 0x0000100000000000ULL
,
552 /* segment register access instructions for PowerPC 64 "bridge" */
553 PPC_SEGMENT_64B
= 0x0000200000000000ULL
,
555 PPC_SLBI
= 0x0000400000000000ULL
,
557 /* Embedded PowerPC dedicated instructions */
558 PPC_WRTEE
= 0x0001000000000000ULL
,
559 /* PowerPC 40x exception model */
560 PPC_40x_EXCP
= 0x0002000000000000ULL
,
561 /* PowerPC 405 Mac instructions */
562 PPC_405_MAC
= 0x0004000000000000ULL
,
563 /* PowerPC 440 specific instructions */
564 PPC_440_SPEC
= 0x0008000000000000ULL
,
565 /* BookE (embedded) PowerPC specification */
566 PPC_BOOKE
= 0x0010000000000000ULL
,
567 /* mfapidi instruction */
568 PPC_MFAPIDI
= 0x0020000000000000ULL
,
569 /* tlbiva instruction */
570 PPC_TLBIVA
= 0x0040000000000000ULL
,
571 /* tlbivax instruction */
572 PPC_TLBIVAX
= 0x0080000000000000ULL
,
573 /* PowerPC 4xx dedicated instructions */
574 PPC_4xx_COMMON
= 0x0100000000000000ULL
,
575 /* PowerPC 40x ibct instructions */
576 PPC_40x_ICBT
= 0x0200000000000000ULL
,
577 /* rfmci is not implemented in all BookE PowerPC */
578 PPC_RFMCI
= 0x0400000000000000ULL
,
579 /* rfdi instruction */
580 PPC_RFDI
= 0x0800000000000000ULL
,
582 PPC_DCR
= 0x1000000000000000ULL
,
583 /* DCR extended accesse */
584 PPC_DCRX
= 0x2000000000000000ULL
,
585 /* user-mode DCR access, implemented in PowerPC 460 */
586 PPC_DCRUX
= 0x4000000000000000ULL
,
589 /*****************************************************************************/
590 /* PowerPC instructions table */
591 #if HOST_LONG_BITS == 64
596 #if defined(__APPLE__)
597 #define OPCODES_SECTION \
598 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
600 #define OPCODES_SECTION \
601 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
604 #if defined(DO_PPC_STATISTICS)
605 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
606 OPCODES_SECTION opcode_t opc_##name = { \
614 .handler = &gen_##name, \
615 .oname = stringify(name), \
617 .oname = stringify(name), \
619 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
620 OPCODES_SECTION opcode_t opc_##name = { \
628 .handler = &gen_##name, \
634 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
635 OPCODES_SECTION opcode_t opc_##name = { \
643 .handler = &gen_##name, \
645 .oname = stringify(name), \
647 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
648 OPCODES_SECTION opcode_t opc_##name = { \
656 .handler = &gen_##name, \
662 #define GEN_OPCODE_MARK(name) \
663 OPCODES_SECTION opcode_t opc_##name = { \
669 .inval = 0x00000000, \
673 .oname = stringify(name), \
676 /* SPR load/store helpers */
677 static always_inline
void gen_load_spr(TCGv t
, int reg
)
679 tcg_gen_ld_tl(t
, cpu_env
, offsetof(CPUState
, spr
[reg
]));
682 static always_inline
void gen_store_spr(int reg
, TCGv t
)
684 tcg_gen_st_tl(t
, cpu_env
, offsetof(CPUState
, spr
[reg
]));
687 /* Start opcode list */
688 GEN_OPCODE_MARK(start
);
690 /* Invalid instruction */
691 GEN_HANDLER(invalid
, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE
)
693 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
696 static opc_handler_t invalid_handler
= {
699 .handler
= gen_invalid
,
702 /*** Integer comparison ***/
704 static always_inline
void gen_op_cmp(TCGv arg0
, TCGv arg1
, int s
, int crf
)
708 tcg_gen_trunc_tl_i32(cpu_crf
[crf
], cpu_xer
);
709 tcg_gen_shri_i32(cpu_crf
[crf
], cpu_crf
[crf
], XER_SO
);
710 tcg_gen_andi_i32(cpu_crf
[crf
], cpu_crf
[crf
], 1);
712 l1
= gen_new_label();
713 l2
= gen_new_label();
714 l3
= gen_new_label();
716 tcg_gen_brcond_tl(TCG_COND_LT
, arg0
, arg1
, l1
);
717 tcg_gen_brcond_tl(TCG_COND_GT
, arg0
, arg1
, l2
);
719 tcg_gen_brcond_tl(TCG_COND_LTU
, arg0
, arg1
, l1
);
720 tcg_gen_brcond_tl(TCG_COND_GTU
, arg0
, arg1
, l2
);
722 tcg_gen_ori_i32(cpu_crf
[crf
], cpu_crf
[crf
], 1 << CRF_EQ
);
725 tcg_gen_ori_i32(cpu_crf
[crf
], cpu_crf
[crf
], 1 << CRF_LT
);
728 tcg_gen_ori_i32(cpu_crf
[crf
], cpu_crf
[crf
], 1 << CRF_GT
);
732 static always_inline
void gen_op_cmpi(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
734 TCGv t0
= tcg_const_local_tl(arg1
);
735 gen_op_cmp(arg0
, t0
, s
, crf
);
739 #if defined(TARGET_PPC64)
740 static always_inline
void gen_op_cmp32(TCGv arg0
, TCGv arg1
, int s
, int crf
)
743 t0
= tcg_temp_local_new();
744 t1
= tcg_temp_local_new();
746 tcg_gen_ext32s_tl(t0
, arg0
);
747 tcg_gen_ext32s_tl(t1
, arg1
);
749 tcg_gen_ext32u_tl(t0
, arg0
);
750 tcg_gen_ext32u_tl(t1
, arg1
);
752 gen_op_cmp(t0
, t1
, s
, crf
);
757 static always_inline
void gen_op_cmpi32(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
759 TCGv t0
= tcg_const_local_tl(arg1
);
760 gen_op_cmp32(arg0
, t0
, s
, crf
);
765 static always_inline
void gen_set_Rc0 (DisasContext
*ctx
, TCGv reg
)
767 #if defined(TARGET_PPC64)
769 gen_op_cmpi32(reg
, 0, 1, 0);
772 gen_op_cmpi(reg
, 0, 1, 0);
776 GEN_HANDLER(cmp
, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER
)
778 #if defined(TARGET_PPC64)
779 if (!(ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000)))
780 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
781 1, crfD(ctx
->opcode
));
784 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
785 1, crfD(ctx
->opcode
));
789 GEN_HANDLER(cmpi
, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
)
791 #if defined(TARGET_PPC64)
792 if (!(ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000)))
793 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
794 1, crfD(ctx
->opcode
));
797 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
798 1, crfD(ctx
->opcode
));
802 GEN_HANDLER(cmpl
, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER
)
804 #if defined(TARGET_PPC64)
805 if (!(ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000)))
806 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
807 0, crfD(ctx
->opcode
));
810 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
811 0, crfD(ctx
->opcode
));
815 GEN_HANDLER(cmpli
, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
)
817 #if defined(TARGET_PPC64)
818 if (!(ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000)))
819 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
820 0, crfD(ctx
->opcode
));
823 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
824 0, crfD(ctx
->opcode
));
827 /* isel (PowerPC 2.03 specification) */
828 GEN_HANDLER(isel
, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL
)
831 uint32_t bi
= rC(ctx
->opcode
);
835 l1
= gen_new_label();
836 l2
= gen_new_label();
838 mask
= 1 << (3 - (bi
& 0x03));
839 t0
= tcg_temp_new_i32();
840 tcg_gen_andi_i32(t0
, cpu_crf
[bi
>> 2], mask
);
841 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l1
);
842 if (rA(ctx
->opcode
) == 0)
843 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
845 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
848 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
850 tcg_temp_free_i32(t0
);
853 /*** Integer arithmetic ***/
855 static always_inline
void gen_op_arith_compute_ov(DisasContext
*ctx
, TCGv arg0
, TCGv arg1
, TCGv arg2
, int sub
)
860 l1
= gen_new_label();
861 /* Start with XER OV disabled, the most likely case */
862 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
863 t0
= tcg_temp_local_new();
864 tcg_gen_xor_tl(t0
, arg0
, arg1
);
865 #if defined(TARGET_PPC64)
867 tcg_gen_ext32s_tl(t0
, t0
);
870 tcg_gen_brcondi_tl(TCG_COND_LT
, t0
, 0, l1
);
872 tcg_gen_brcondi_tl(TCG_COND_GE
, t0
, 0, l1
);
873 tcg_gen_xor_tl(t0
, arg1
, arg2
);
874 #if defined(TARGET_PPC64)
876 tcg_gen_ext32s_tl(t0
, t0
);
879 tcg_gen_brcondi_tl(TCG_COND_GE
, t0
, 0, l1
);
881 tcg_gen_brcondi_tl(TCG_COND_LT
, t0
, 0, l1
);
882 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
887 static always_inline
void gen_op_arith_compute_ca(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
, int sub
)
889 int l1
= gen_new_label();
891 #if defined(TARGET_PPC64)
892 if (!(ctx
->sf_mode
)) {
897 tcg_gen_ext32u_tl(t0
, arg1
);
898 tcg_gen_ext32u_tl(t1
, arg2
);
900 tcg_gen_brcond_tl(TCG_COND_GTU
, t0
, t1
, l1
);
902 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
904 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, 1 << XER_CA
);
912 tcg_gen_brcond_tl(TCG_COND_GTU
, arg1
, arg2
, l1
);
914 tcg_gen_brcond_tl(TCG_COND_GEU
, arg1
, arg2
, l1
);
916 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, 1 << XER_CA
);
921 /* Common add function */
922 static always_inline
void gen_op_arith_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
, TCGv arg2
,
923 int add_ca
, int compute_ca
, int compute_ov
)
927 if ((!compute_ca
&& !compute_ov
) ||
928 (!TCGV_EQUAL(ret
,arg1
) && !TCGV_EQUAL(ret
, arg2
))) {
931 t0
= tcg_temp_local_new();
935 t1
= tcg_temp_local_new();
936 tcg_gen_andi_tl(t1
, cpu_xer
, (1 << XER_CA
));
937 tcg_gen_shri_tl(t1
, t1
, XER_CA
);
940 if (compute_ca
&& compute_ov
) {
941 /* Start with XER CA and OV disabled, the most likely case */
942 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~((1 << XER_CA
) | (1 << XER_OV
)));
943 } else if (compute_ca
) {
944 /* Start with XER CA disabled, the most likely case */
945 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
946 } else if (compute_ov
) {
947 /* Start with XER OV disabled, the most likely case */
948 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
951 tcg_gen_add_tl(t0
, arg1
, arg2
);
954 gen_op_arith_compute_ca(ctx
, t0
, arg1
, 0);
957 tcg_gen_add_tl(t0
, t0
, t1
);
958 gen_op_arith_compute_ca(ctx
, t0
, t1
, 0);
962 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 0);
965 if (unlikely(Rc(ctx
->opcode
) != 0))
966 gen_set_Rc0(ctx
, t0
);
968 if (!TCGV_EQUAL(t0
, ret
)) {
969 tcg_gen_mov_tl(ret
, t0
);
973 /* Add functions with two operands */
974 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
975 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
977 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
978 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
979 add_ca, compute_ca, compute_ov); \
981 /* Add functions with one operand and one immediate */
982 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
983 add_ca, compute_ca, compute_ov) \
984 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
986 TCGv t0 = tcg_const_local_tl(const_val); \
987 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
988 cpu_gpr[rA(ctx->opcode)], t0, \
989 add_ca, compute_ca, compute_ov); \
993 /* add add. addo addo. */
994 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
995 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
996 /* addc addc. addco addco. */
997 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
998 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
999 /* adde adde. addeo addeo. */
1000 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
1001 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
1002 /* addme addme. addmeo addmeo. */
1003 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
1004 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
1005 /* addze addze. addzeo addzeo.*/
1006 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
1007 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
1009 GEN_HANDLER(addi
, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1011 target_long simm
= SIMM(ctx
->opcode
);
1013 if (rA(ctx
->opcode
) == 0) {
1015 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
);
1017 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], simm
);
1021 static always_inline
void gen_op_addic (DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1024 target_long simm
= SIMM(ctx
->opcode
);
1026 /* Start with XER CA and OV disabled, the most likely case */
1027 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
1029 if (likely(simm
!= 0)) {
1030 TCGv t0
= tcg_temp_local_new();
1031 tcg_gen_addi_tl(t0
, arg1
, simm
);
1032 gen_op_arith_compute_ca(ctx
, t0
, arg1
, 0);
1033 tcg_gen_mov_tl(ret
, t0
);
1036 tcg_gen_mov_tl(ret
, arg1
);
1039 gen_set_Rc0(ctx
, ret
);
1042 GEN_HANDLER(addic
, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1044 gen_op_addic(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0);
1046 GEN_HANDLER2(addic_
, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1048 gen_op_addic(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 1);
1051 GEN_HANDLER(addis
, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1053 target_long simm
= SIMM(ctx
->opcode
);
1055 if (rA(ctx
->opcode
) == 0) {
1057 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
<< 16);
1059 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], simm
<< 16);
1063 static always_inline
void gen_op_arith_divw (DisasContext
*ctx
, TCGv ret
, TCGv arg1
, TCGv arg2
,
1064 int sign
, int compute_ov
)
1066 int l1
= gen_new_label();
1067 int l2
= gen_new_label();
1068 TCGv_i32 t0
= tcg_temp_local_new_i32();
1069 TCGv_i32 t1
= tcg_temp_local_new_i32();
1071 tcg_gen_trunc_tl_i32(t0
, arg1
);
1072 tcg_gen_trunc_tl_i32(t1
, arg2
);
1073 tcg_gen_brcondi_i32(TCG_COND_EQ
, t1
, 0, l1
);
1075 int l3
= gen_new_label();
1076 tcg_gen_brcondi_i32(TCG_COND_NE
, t1
, -1, l3
);
1077 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, INT32_MIN
, l1
);
1079 tcg_gen_div_i32(t0
, t0
, t1
);
1081 tcg_gen_divu_i32(t0
, t0
, t1
);
1084 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
1089 tcg_gen_sari_i32(t0
, t0
, 31);
1091 tcg_gen_movi_i32(t0
, 0);
1094 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
1097 tcg_gen_extu_i32_tl(ret
, t0
);
1098 tcg_temp_free_i32(t0
);
1099 tcg_temp_free_i32(t1
);
1100 if (unlikely(Rc(ctx
->opcode
) != 0))
1101 gen_set_Rc0(ctx
, ret
);
1104 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1105 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1107 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1108 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1109 sign, compute_ov); \
1111 /* divwu divwu. divwuo divwuo. */
1112 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0);
1113 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1);
1114 /* divw divw. divwo divwo. */
1115 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0);
1116 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1);
1117 #if defined(TARGET_PPC64)
1118 static always_inline
void gen_op_arith_divd (DisasContext
*ctx
, TCGv ret
, TCGv arg1
, TCGv arg2
,
1119 int sign
, int compute_ov
)
1121 int l1
= gen_new_label();
1122 int l2
= gen_new_label();
1124 tcg_gen_brcondi_i64(TCG_COND_EQ
, arg2
, 0, l1
);
1126 int l3
= gen_new_label();
1127 tcg_gen_brcondi_i64(TCG_COND_NE
, arg2
, -1, l3
);
1128 tcg_gen_brcondi_i64(TCG_COND_EQ
, arg1
, INT64_MIN
, l1
);
1130 tcg_gen_div_i64(ret
, arg1
, arg2
);
1132 tcg_gen_divu_i64(ret
, arg1
, arg2
);
1135 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
1140 tcg_gen_sari_i64(ret
, arg1
, 63);
1142 tcg_gen_movi_i64(ret
, 0);
1145 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
1148 if (unlikely(Rc(ctx
->opcode
) != 0))
1149 gen_set_Rc0(ctx
, ret
);
1151 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1152 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1154 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1155 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1156 sign, compute_ov); \
1158 /* divwu divwu. divwuo divwuo. */
1159 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0);
1160 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1);
1161 /* divw divw. divwo divwo. */
1162 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0);
1163 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1);
1167 GEN_HANDLER(mulhw
, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER
)
1171 t0
= tcg_temp_new_i64();
1172 t1
= tcg_temp_new_i64();
1173 #if defined(TARGET_PPC64)
1174 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1175 tcg_gen_ext32s_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1176 tcg_gen_mul_i64(t0
, t0
, t1
);
1177 tcg_gen_shri_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
1179 tcg_gen_ext_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1180 tcg_gen_ext_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1181 tcg_gen_mul_i64(t0
, t0
, t1
);
1182 tcg_gen_shri_i64(t0
, t0
, 32);
1183 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1185 tcg_temp_free_i64(t0
);
1186 tcg_temp_free_i64(t1
);
1187 if (unlikely(Rc(ctx
->opcode
) != 0))
1188 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1190 /* mulhwu mulhwu. */
1191 GEN_HANDLER(mulhwu
, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER
)
1195 t0
= tcg_temp_new_i64();
1196 t1
= tcg_temp_new_i64();
1197 #if defined(TARGET_PPC64)
1198 tcg_gen_ext32u_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1199 tcg_gen_ext32u_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1200 tcg_gen_mul_i64(t0
, t0
, t1
);
1201 tcg_gen_shri_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
1203 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1204 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1205 tcg_gen_mul_i64(t0
, t0
, t1
);
1206 tcg_gen_shri_i64(t0
, t0
, 32);
1207 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1209 tcg_temp_free_i64(t0
);
1210 tcg_temp_free_i64(t1
);
1211 if (unlikely(Rc(ctx
->opcode
) != 0))
1212 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1215 GEN_HANDLER(mullw
, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER
)
1217 tcg_gen_mul_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1218 cpu_gpr
[rB(ctx
->opcode
)]);
1219 tcg_gen_ext32s_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)]);
1220 if (unlikely(Rc(ctx
->opcode
) != 0))
1221 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1223 /* mullwo mullwo. */
1224 GEN_HANDLER(mullwo
, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER
)
1229 t0
= tcg_temp_new_i64();
1230 t1
= tcg_temp_new_i64();
1231 l1
= gen_new_label();
1232 /* Start with XER OV disabled, the most likely case */
1233 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
1234 #if defined(TARGET_PPC64)
1235 tcg_gen_ext32s_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1236 tcg_gen_ext32s_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1238 tcg_gen_ext_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1239 tcg_gen_ext_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1241 tcg_gen_mul_i64(t0
, t0
, t1
);
1242 #if defined(TARGET_PPC64)
1243 tcg_gen_ext32s_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1244 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, cpu_gpr
[rD(ctx
->opcode
)], l1
);
1246 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1247 tcg_gen_ext32s_i64(t1
, t0
);
1248 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, t1
, l1
);
1250 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
1252 tcg_temp_free_i64(t0
);
1253 tcg_temp_free_i64(t1
);
1254 if (unlikely(Rc(ctx
->opcode
) != 0))
1255 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1258 GEN_HANDLER(mulli
, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1260 tcg_gen_muli_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1263 #if defined(TARGET_PPC64)
1264 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1265 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1267 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
1268 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1269 if (unlikely(Rc(ctx->opcode) != 0)) \
1270 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1273 GEN_INT_ARITH_MUL_HELPER(mulhdu
, 0x00);
1274 /* mulhdu mulhdu. */
1275 GEN_INT_ARITH_MUL_HELPER(mulhd
, 0x02);
1277 GEN_HANDLER(mulld
, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B
)
1279 tcg_gen_mul_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1280 cpu_gpr
[rB(ctx
->opcode
)]);
1281 if (unlikely(Rc(ctx
->opcode
) != 0))
1282 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1284 /* mulldo mulldo. */
1285 GEN_INT_ARITH_MUL_HELPER(mulldo
, 0x17);
1288 /* neg neg. nego nego. */
1289 static always_inline
void gen_op_arith_neg (DisasContext
*ctx
, TCGv ret
, TCGv arg1
, int ov_check
)
1291 int l1
= gen_new_label();
1292 int l2
= gen_new_label();
1293 TCGv t0
= tcg_temp_local_new();
1294 #if defined(TARGET_PPC64)
1296 tcg_gen_mov_tl(t0
, arg1
);
1297 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, INT64_MIN
, l1
);
1301 tcg_gen_ext32s_tl(t0
, arg1
);
1302 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, INT32_MIN
, l1
);
1304 tcg_gen_neg_tl(ret
, arg1
);
1306 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
1310 tcg_gen_mov_tl(ret
, t0
);
1312 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
1316 if (unlikely(Rc(ctx
->opcode
) != 0))
1317 gen_set_Rc0(ctx
, ret
);
1319 GEN_HANDLER(neg
, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER
)
1321 gen_op_arith_neg(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0);
1323 GEN_HANDLER(nego
, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER
)
1325 gen_op_arith_neg(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 1);
1328 /* Common subf function */
1329 static always_inline
void gen_op_arith_subf(DisasContext
*ctx
, TCGv ret
, TCGv arg1
, TCGv arg2
,
1330 int add_ca
, int compute_ca
, int compute_ov
)
1334 if ((!compute_ca
&& !compute_ov
) ||
1335 (!TCGV_EQUAL(ret
, arg1
) && !TCGV_EQUAL(ret
, arg2
))) {
1338 t0
= tcg_temp_local_new();
1342 t1
= tcg_temp_local_new();
1343 tcg_gen_andi_tl(t1
, cpu_xer
, (1 << XER_CA
));
1344 tcg_gen_shri_tl(t1
, t1
, XER_CA
);
1347 if (compute_ca
&& compute_ov
) {
1348 /* Start with XER CA and OV disabled, the most likely case */
1349 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~((1 << XER_CA
) | (1 << XER_OV
)));
1350 } else if (compute_ca
) {
1351 /* Start with XER CA disabled, the most likely case */
1352 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
1353 } else if (compute_ov
) {
1354 /* Start with XER OV disabled, the most likely case */
1355 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
1359 tcg_gen_not_tl(t0
, arg1
);
1360 tcg_gen_add_tl(t0
, t0
, arg2
);
1361 gen_op_arith_compute_ca(ctx
, t0
, arg2
, 0);
1362 tcg_gen_add_tl(t0
, t0
, t1
);
1363 gen_op_arith_compute_ca(ctx
, t0
, t1
, 0);
1366 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1368 gen_op_arith_compute_ca(ctx
, t0
, arg2
, 1);
1372 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 1);
1375 if (unlikely(Rc(ctx
->opcode
) != 0))
1376 gen_set_Rc0(ctx
, t0
);
1378 if (!TCGV_EQUAL(t0
, ret
)) {
1379 tcg_gen_mov_tl(ret
, t0
);
1383 /* Sub functions with Two operands functions */
1384 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1385 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1387 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1388 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1389 add_ca, compute_ca, compute_ov); \
1391 /* Sub functions with one operand and one immediate */
1392 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1393 add_ca, compute_ca, compute_ov) \
1394 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1396 TCGv t0 = tcg_const_local_tl(const_val); \
1397 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1398 cpu_gpr[rA(ctx->opcode)], t0, \
1399 add_ca, compute_ca, compute_ov); \
1400 tcg_temp_free(t0); \
1402 /* subf subf. subfo subfo. */
1403 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
1404 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
1405 /* subfc subfc. subfco subfco. */
1406 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
1407 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
1408 /* subfe subfe. subfeo subfo. */
1409 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
1410 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
1411 /* subfme subfme. subfmeo subfmeo. */
1412 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
1413 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
1414 /* subfze subfze. subfzeo subfzeo.*/
1415 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
1416 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
1418 GEN_HANDLER(subfic
, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1420 /* Start with XER CA and OV disabled, the most likely case */
1421 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
1422 TCGv t0
= tcg_temp_local_new();
1423 TCGv t1
= tcg_const_local_tl(SIMM(ctx
->opcode
));
1424 tcg_gen_sub_tl(t0
, t1
, cpu_gpr
[rA(ctx
->opcode
)]);
1425 gen_op_arith_compute_ca(ctx
, t0
, t1
, 1);
1427 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1431 /*** Integer logical ***/
1432 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1433 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
1435 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1436 cpu_gpr[rB(ctx->opcode)]); \
1437 if (unlikely(Rc(ctx->opcode) != 0)) \
1438 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1441 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1442 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
1444 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1445 if (unlikely(Rc(ctx->opcode) != 0)) \
1446 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1450 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
);
1452 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
);
1454 GEN_HANDLER2(andi_
, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1456 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
));
1457 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1460 GEN_HANDLER2(andis_
, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1462 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
) << 16);
1463 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1466 GEN_HANDLER(cntlzw
, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER
)
1468 gen_helper_cntlzw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1469 if (unlikely(Rc(ctx
->opcode
) != 0))
1470 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1473 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
);
1474 /* extsb & extsb. */
1475 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
);
1476 /* extsh & extsh. */
1477 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
);
1479 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
);
1481 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
);
1483 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER
)
1487 rs
= rS(ctx
->opcode
);
1488 ra
= rA(ctx
->opcode
);
1489 rb
= rB(ctx
->opcode
);
1490 /* Optimisation for mr. ri case */
1491 if (rs
!= ra
|| rs
!= rb
) {
1493 tcg_gen_or_tl(cpu_gpr
[ra
], cpu_gpr
[rs
], cpu_gpr
[rb
]);
1495 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rs
]);
1496 if (unlikely(Rc(ctx
->opcode
) != 0))
1497 gen_set_Rc0(ctx
, cpu_gpr
[ra
]);
1498 } else if (unlikely(Rc(ctx
->opcode
) != 0)) {
1499 gen_set_Rc0(ctx
, cpu_gpr
[rs
]);
1500 #if defined(TARGET_PPC64)
1506 /* Set process priority to low */
1510 /* Set process priority to medium-low */
1514 /* Set process priority to normal */
1517 #if !defined(CONFIG_USER_ONLY)
1519 if (ctx
->mem_idx
> 0) {
1520 /* Set process priority to very low */
1525 if (ctx
->mem_idx
> 0) {
1526 /* Set process priority to medium-hight */
1531 if (ctx
->mem_idx
> 0) {
1532 /* Set process priority to high */
1537 if (ctx
->mem_idx
> 1) {
1538 /* Set process priority to very high */
1548 TCGv t0
= tcg_temp_new();
1549 gen_load_spr(t0
, SPR_PPR
);
1550 tcg_gen_andi_tl(t0
, t0
, ~0x001C000000000000ULL
);
1551 tcg_gen_ori_tl(t0
, t0
, ((uint64_t)prio
) << 50);
1552 gen_store_spr(SPR_PPR
, t0
);
1559 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
);
1561 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER
)
1563 /* Optimisation for "set to zero" case */
1564 if (rS(ctx
->opcode
) != rB(ctx
->opcode
))
1565 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1567 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
1568 if (unlikely(Rc(ctx
->opcode
) != 0))
1569 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1572 GEN_HANDLER(ori
, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1574 target_ulong uimm
= UIMM(ctx
->opcode
);
1576 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1578 /* XXX: should handle special NOPs for POWER series */
1581 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1584 GEN_HANDLER(oris
, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1586 target_ulong uimm
= UIMM(ctx
->opcode
);
1588 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1592 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1595 GEN_HANDLER(xori
, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1597 target_ulong uimm
= UIMM(ctx
->opcode
);
1599 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1603 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1606 GEN_HANDLER(xoris
, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1608 target_ulong uimm
= UIMM(ctx
->opcode
);
1610 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1614 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1616 /* popcntb : PowerPC 2.03 specification */
1617 GEN_HANDLER(popcntb
, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB
)
1619 #if defined(TARGET_PPC64)
1621 gen_helper_popcntb_64(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1624 gen_helper_popcntb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1627 #if defined(TARGET_PPC64)
1628 /* extsw & extsw. */
1629 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
);
1631 GEN_HANDLER(cntlzd
, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B
)
1633 gen_helper_cntlzd(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1634 if (unlikely(Rc(ctx
->opcode
) != 0))
1635 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1639 /*** Integer rotate ***/
1640 /* rlwimi & rlwimi. */
1641 GEN_HANDLER(rlwimi
, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1643 uint32_t mb
, me
, sh
;
1645 mb
= MB(ctx
->opcode
);
1646 me
= ME(ctx
->opcode
);
1647 sh
= SH(ctx
->opcode
);
1648 if (likely(sh
== 0 && mb
== 0 && me
== 31)) {
1649 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1653 TCGv t0
= tcg_temp_new();
1654 #if defined(TARGET_PPC64)
1655 TCGv_i32 t2
= tcg_temp_new_i32();
1656 tcg_gen_trunc_i64_i32(t2
, cpu_gpr
[rS(ctx
->opcode
)]);
1657 tcg_gen_rotli_i32(t2
, t2
, sh
);
1658 tcg_gen_extu_i32_i64(t0
, t2
);
1659 tcg_temp_free_i32(t2
);
1661 tcg_gen_rotli_i32(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1663 #if defined(TARGET_PPC64)
1667 mask
= MASK(mb
, me
);
1668 t1
= tcg_temp_new();
1669 tcg_gen_andi_tl(t0
, t0
, mask
);
1670 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], ~mask
);
1671 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1675 if (unlikely(Rc(ctx
->opcode
) != 0))
1676 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1678 /* rlwinm & rlwinm. */
1679 GEN_HANDLER(rlwinm
, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1681 uint32_t mb
, me
, sh
;
1683 sh
= SH(ctx
->opcode
);
1684 mb
= MB(ctx
->opcode
);
1685 me
= ME(ctx
->opcode
);
1687 if (likely(mb
== 0 && me
== (31 - sh
))) {
1688 if (likely(sh
== 0)) {
1689 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1691 TCGv t0
= tcg_temp_new();
1692 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1693 tcg_gen_shli_tl(t0
, t0
, sh
);
1694 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1697 } else if (likely(sh
!= 0 && me
== 31 && sh
== (32 - mb
))) {
1698 TCGv t0
= tcg_temp_new();
1699 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1700 tcg_gen_shri_tl(t0
, t0
, mb
);
1701 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1704 TCGv t0
= tcg_temp_new();
1705 #if defined(TARGET_PPC64)
1706 TCGv_i32 t1
= tcg_temp_new_i32();
1707 tcg_gen_trunc_i64_i32(t1
, cpu_gpr
[rS(ctx
->opcode
)]);
1708 tcg_gen_rotli_i32(t1
, t1
, sh
);
1709 tcg_gen_extu_i32_i64(t0
, t1
);
1710 tcg_temp_free_i32(t1
);
1712 tcg_gen_rotli_i32(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1714 #if defined(TARGET_PPC64)
1718 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1721 if (unlikely(Rc(ctx
->opcode
) != 0))
1722 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1724 /* rlwnm & rlwnm. */
1725 GEN_HANDLER(rlwnm
, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1729 #if defined(TARGET_PPC64)
1733 mb
= MB(ctx
->opcode
);
1734 me
= ME(ctx
->opcode
);
1735 t0
= tcg_temp_new();
1736 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
1737 #if defined(TARGET_PPC64)
1738 t1
= tcg_temp_new_i32();
1739 t2
= tcg_temp_new_i32();
1740 tcg_gen_trunc_i64_i32(t1
, cpu_gpr
[rS(ctx
->opcode
)]);
1741 tcg_gen_trunc_i64_i32(t2
, t0
);
1742 tcg_gen_rotl_i32(t1
, t1
, t2
);
1743 tcg_gen_extu_i32_i64(t0
, t1
);
1744 tcg_temp_free_i32(t1
);
1745 tcg_temp_free_i32(t2
);
1747 tcg_gen_rotl_i32(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1749 if (unlikely(mb
!= 0 || me
!= 31)) {
1750 #if defined(TARGET_PPC64)
1754 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1756 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1759 if (unlikely(Rc(ctx
->opcode
) != 0))
1760 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1763 #if defined(TARGET_PPC64)
1764 #define GEN_PPC64_R2(name, opc1, opc2) \
1765 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1767 gen_##name(ctx, 0); \
1769 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1772 gen_##name(ctx, 1); \
1774 #define GEN_PPC64_R4(name, opc1, opc2) \
1775 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1777 gen_##name(ctx, 0, 0); \
1779 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1782 gen_##name(ctx, 0, 1); \
1784 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1787 gen_##name(ctx, 1, 0); \
1789 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1792 gen_##name(ctx, 1, 1); \
1795 static always_inline
void gen_rldinm (DisasContext
*ctx
, uint32_t mb
,
1796 uint32_t me
, uint32_t sh
)
1798 if (likely(sh
!= 0 && mb
== 0 && me
== (63 - sh
))) {
1799 tcg_gen_shli_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
1800 } else if (likely(sh
!= 0 && me
== 63 && sh
== (64 - mb
))) {
1801 tcg_gen_shri_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], mb
);
1803 TCGv t0
= tcg_temp_new();
1804 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1805 if (likely(mb
== 0 && me
== 63)) {
1806 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1808 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1812 if (unlikely(Rc(ctx
->opcode
) != 0))
1813 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1815 /* rldicl - rldicl. */
1816 static always_inline
void gen_rldicl (DisasContext
*ctx
, int mbn
, int shn
)
1820 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1821 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1822 gen_rldinm(ctx
, mb
, 63, sh
);
1824 GEN_PPC64_R4(rldicl
, 0x1E, 0x00);
1825 /* rldicr - rldicr. */
1826 static always_inline
void gen_rldicr (DisasContext
*ctx
, int men
, int shn
)
1830 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1831 me
= MB(ctx
->opcode
) | (men
<< 5);
1832 gen_rldinm(ctx
, 0, me
, sh
);
1834 GEN_PPC64_R4(rldicr
, 0x1E, 0x02);
1835 /* rldic - rldic. */
1836 static always_inline
void gen_rldic (DisasContext
*ctx
, int mbn
, int shn
)
1840 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1841 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1842 gen_rldinm(ctx
, mb
, 63 - sh
, sh
);
1844 GEN_PPC64_R4(rldic
, 0x1E, 0x04);
1846 static always_inline
void gen_rldnm (DisasContext
*ctx
, uint32_t mb
,
1851 mb
= MB(ctx
->opcode
);
1852 me
= ME(ctx
->opcode
);
1853 t0
= tcg_temp_new();
1854 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
1855 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1856 if (unlikely(mb
!= 0 || me
!= 63)) {
1857 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1859 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1862 if (unlikely(Rc(ctx
->opcode
) != 0))
1863 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1866 /* rldcl - rldcl. */
1867 static always_inline
void gen_rldcl (DisasContext
*ctx
, int mbn
)
1871 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1872 gen_rldnm(ctx
, mb
, 63);
1874 GEN_PPC64_R2(rldcl
, 0x1E, 0x08);
1875 /* rldcr - rldcr. */
1876 static always_inline
void gen_rldcr (DisasContext
*ctx
, int men
)
1880 me
= MB(ctx
->opcode
) | (men
<< 5);
1881 gen_rldnm(ctx
, 0, me
);
1883 GEN_PPC64_R2(rldcr
, 0x1E, 0x09);
1884 /* rldimi - rldimi. */
1885 static always_inline
void gen_rldimi (DisasContext
*ctx
, int mbn
, int shn
)
1887 uint32_t sh
, mb
, me
;
1889 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1890 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1892 if (unlikely(sh
== 0 && mb
== 0)) {
1893 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1898 t0
= tcg_temp_new();
1899 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1900 t1
= tcg_temp_new();
1901 mask
= MASK(mb
, me
);
1902 tcg_gen_andi_tl(t0
, t0
, mask
);
1903 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], ~mask
);
1904 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1908 if (unlikely(Rc(ctx
->opcode
) != 0))
1909 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1911 GEN_PPC64_R4(rldimi
, 0x1E, 0x06);
1914 /*** Integer shift ***/
1916 GEN_HANDLER(slw
, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER
)
1920 l1
= gen_new_label();
1921 l2
= gen_new_label();
1923 t0
= tcg_temp_local_new();
1924 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
1925 tcg_gen_brcondi_tl(TCG_COND_LT
, t0
, 0x20, l1
);
1926 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
1929 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], t0
);
1930 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
1933 if (unlikely(Rc(ctx
->opcode
) != 0))
1934 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1937 GEN_HANDLER(sraw
, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER
)
1939 gen_helper_sraw(cpu_gpr
[rA(ctx
->opcode
)],
1940 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1941 if (unlikely(Rc(ctx
->opcode
) != 0))
1942 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1944 /* srawi & srawi. */
1945 GEN_HANDLER(srawi
, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER
)
1947 int sh
= SH(ctx
->opcode
);
1951 l1
= gen_new_label();
1952 l2
= gen_new_label();
1953 t0
= tcg_temp_local_new();
1954 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1955 tcg_gen_brcondi_tl(TCG_COND_GE
, t0
, 0, l1
);
1956 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1ULL << sh
) - 1);
1957 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
1958 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, 1 << XER_CA
);
1961 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
1963 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1964 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, sh
);
1967 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1968 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
1970 if (unlikely(Rc(ctx
->opcode
) != 0))
1971 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1974 GEN_HANDLER(srw
, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER
)
1978 l1
= gen_new_label();
1979 l2
= gen_new_label();
1981 t0
= tcg_temp_local_new();
1982 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
1983 tcg_gen_brcondi_tl(TCG_COND_LT
, t0
, 0x20, l1
);
1984 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
1987 t1
= tcg_temp_new();
1988 tcg_gen_ext32u_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)]);
1989 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t1
, t0
);
1993 if (unlikely(Rc(ctx
->opcode
) != 0))
1994 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1996 #if defined(TARGET_PPC64)
1998 GEN_HANDLER(sld
, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B
)
2002 l1
= gen_new_label();
2003 l2
= gen_new_label();
2005 t0
= tcg_temp_local_new();
2006 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x7f);
2007 tcg_gen_brcondi_tl(TCG_COND_LT
, t0
, 0x40, l1
);
2008 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
2011 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], t0
);
2014 if (unlikely(Rc(ctx
->opcode
) != 0))
2015 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2018 GEN_HANDLER(srad
, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B
)
2020 gen_helper_srad(cpu_gpr
[rA(ctx
->opcode
)],
2021 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2022 if (unlikely(Rc(ctx
->opcode
) != 0))
2023 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2025 /* sradi & sradi. */
2026 static always_inline
void gen_sradi (DisasContext
*ctx
, int n
)
2028 int sh
= SH(ctx
->opcode
) + (n
<< 5);
2032 l1
= gen_new_label();
2033 l2
= gen_new_label();
2034 t0
= tcg_temp_local_new();
2035 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rS(ctx
->opcode
)], 0, l1
);
2036 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1ULL << sh
) - 1);
2037 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
2038 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, 1 << XER_CA
);
2041 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
2044 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
2046 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
2047 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
2049 if (unlikely(Rc(ctx
->opcode
) != 0))
2050 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2052 GEN_HANDLER2(sradi0
, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B
)
2056 GEN_HANDLER2(sradi1
, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B
)
2061 GEN_HANDLER(srd
, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B
)
2065 l1
= gen_new_label();
2066 l2
= gen_new_label();
2068 t0
= tcg_temp_local_new();
2069 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x7f);
2070 tcg_gen_brcondi_tl(TCG_COND_LT
, t0
, 0x40, l1
);
2071 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
2074 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], t0
);
2077 if (unlikely(Rc(ctx
->opcode
) != 0))
2078 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2082 /*** Floating-Point arithmetic ***/
2083 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2084 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
2086 if (unlikely(!ctx->fpu_enabled)) { \
2087 gen_exception(ctx, POWERPC_EXCP_FPU); \
2090 /* NIP cannot be restored if the memory exception comes from an helper */ \
2091 gen_update_nip(ctx, ctx->nip - 4); \
2092 gen_reset_fpstatus(); \
2093 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2094 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2096 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2098 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2099 Rc(ctx->opcode) != 0); \
2102 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2103 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2104 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2106 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2107 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2109 if (unlikely(!ctx->fpu_enabled)) { \
2110 gen_exception(ctx, POWERPC_EXCP_FPU); \
2113 /* NIP cannot be restored if the memory exception comes from an helper */ \
2114 gen_update_nip(ctx, ctx->nip - 4); \
2115 gen_reset_fpstatus(); \
2116 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2117 cpu_fpr[rB(ctx->opcode)]); \
2119 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2121 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2122 set_fprf, Rc(ctx->opcode) != 0); \
2124 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2125 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2126 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2128 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2129 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2131 if (unlikely(!ctx->fpu_enabled)) { \
2132 gen_exception(ctx, POWERPC_EXCP_FPU); \
2135 /* NIP cannot be restored if the memory exception comes from an helper */ \
2136 gen_update_nip(ctx, ctx->nip - 4); \
2137 gen_reset_fpstatus(); \
2138 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2139 cpu_fpr[rC(ctx->opcode)]); \
2141 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2143 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2144 set_fprf, Rc(ctx->opcode) != 0); \
2146 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2147 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2148 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2150 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2151 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
2153 if (unlikely(!ctx->fpu_enabled)) { \
2154 gen_exception(ctx, POWERPC_EXCP_FPU); \
2157 /* NIP cannot be restored if the memory exception comes from an helper */ \
2158 gen_update_nip(ctx, ctx->nip - 4); \
2159 gen_reset_fpstatus(); \
2160 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2161 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2162 set_fprf, Rc(ctx->opcode) != 0); \
2165 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2166 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
2168 if (unlikely(!ctx->fpu_enabled)) { \
2169 gen_exception(ctx, POWERPC_EXCP_FPU); \
2172 /* NIP cannot be restored if the memory exception comes from an helper */ \
2173 gen_update_nip(ctx, ctx->nip - 4); \
2174 gen_reset_fpstatus(); \
2175 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2176 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2177 set_fprf, Rc(ctx->opcode) != 0); \
2181 GEN_FLOAT_AB(add
, 0x15, 0x000007C0, 1, PPC_FLOAT
);
2183 GEN_FLOAT_AB(div
, 0x12, 0x000007C0, 1, PPC_FLOAT
);
2185 GEN_FLOAT_AC(mul
, 0x19, 0x0000F800, 1, PPC_FLOAT
);
2188 GEN_FLOAT_BS(re
, 0x3F, 0x18, 1, PPC_FLOAT_EXT
);
2191 GEN_FLOAT_BS(res
, 0x3B, 0x18, 1, PPC_FLOAT_FRES
);
2194 GEN_FLOAT_BS(rsqrte
, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE
);
2197 GEN_HANDLER(frsqrtes
, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES
)
2199 if (unlikely(!ctx
->fpu_enabled
)) {
2200 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2203 /* NIP cannot be restored if the memory exception comes from an helper */
2204 gen_update_nip(ctx
, ctx
->nip
- 4);
2205 gen_reset_fpstatus();
2206 gen_helper_frsqrte(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)]);
2207 gen_helper_frsp(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rD(ctx
->opcode
)]);
2208 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 1, Rc(ctx
->opcode
) != 0);
2212 _GEN_FLOAT_ACB(sel
, sel
, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL
);
2214 GEN_FLOAT_AB(sub
, 0x14, 0x000007C0, 1, PPC_FLOAT
);
2217 GEN_HANDLER(fsqrt
, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
)
2219 if (unlikely(!ctx
->fpu_enabled
)) {
2220 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2223 /* NIP cannot be restored if the memory exception comes from an helper */
2224 gen_update_nip(ctx
, ctx
->nip
- 4);
2225 gen_reset_fpstatus();
2226 gen_helper_fsqrt(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)]);
2227 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 1, Rc(ctx
->opcode
) != 0);
2230 GEN_HANDLER(fsqrts
, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
)
2232 if (unlikely(!ctx
->fpu_enabled
)) {
2233 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2236 /* NIP cannot be restored if the memory exception comes from an helper */
2237 gen_update_nip(ctx
, ctx
->nip
- 4);
2238 gen_reset_fpstatus();
2239 gen_helper_fsqrt(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)]);
2240 gen_helper_frsp(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rD(ctx
->opcode
)]);
2241 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 1, Rc(ctx
->opcode
) != 0);
2244 /*** Floating-Point multiply-and-add ***/
2245 /* fmadd - fmadds */
2246 GEN_FLOAT_ACB(madd
, 0x1D, 1, PPC_FLOAT
);
2247 /* fmsub - fmsubs */
2248 GEN_FLOAT_ACB(msub
, 0x1C, 1, PPC_FLOAT
);
2249 /* fnmadd - fnmadds */
2250 GEN_FLOAT_ACB(nmadd
, 0x1F, 1, PPC_FLOAT
);
2251 /* fnmsub - fnmsubs */
2252 GEN_FLOAT_ACB(nmsub
, 0x1E, 1, PPC_FLOAT
);
2254 /*** Floating-Point round & convert ***/
2256 GEN_FLOAT_B(ctiw
, 0x0E, 0x00, 0, PPC_FLOAT
);
2258 GEN_FLOAT_B(ctiwz
, 0x0F, 0x00, 0, PPC_FLOAT
);
2260 GEN_FLOAT_B(rsp
, 0x0C, 0x00, 1, PPC_FLOAT
);
2261 #if defined(TARGET_PPC64)
2263 GEN_FLOAT_B(cfid
, 0x0E, 0x1A, 1, PPC_64B
);
2265 GEN_FLOAT_B(ctid
, 0x0E, 0x19, 0, PPC_64B
);
2267 GEN_FLOAT_B(ctidz
, 0x0F, 0x19, 0, PPC_64B
);
2271 GEN_FLOAT_B(rin
, 0x08, 0x0C, 1, PPC_FLOAT_EXT
);
2273 GEN_FLOAT_B(riz
, 0x08, 0x0D, 1, PPC_FLOAT_EXT
);
2275 GEN_FLOAT_B(rip
, 0x08, 0x0E, 1, PPC_FLOAT_EXT
);
2277 GEN_FLOAT_B(rim
, 0x08, 0x0F, 1, PPC_FLOAT_EXT
);
2279 /*** Floating-Point compare ***/
2281 GEN_HANDLER(fcmpo
, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT
)
2284 if (unlikely(!ctx
->fpu_enabled
)) {
2285 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2288 /* NIP cannot be restored if the memory exception comes from an helper */
2289 gen_update_nip(ctx
, ctx
->nip
- 4);
2290 gen_reset_fpstatus();
2291 crf
= tcg_const_i32(crfD(ctx
->opcode
));
2292 gen_helper_fcmpo(cpu_fpr
[rA(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)], crf
);
2293 tcg_temp_free_i32(crf
);
2294 gen_helper_float_check_status();
2298 GEN_HANDLER(fcmpu
, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT
)
2301 if (unlikely(!ctx
->fpu_enabled
)) {
2302 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2305 /* NIP cannot be restored if the memory exception comes from an helper */
2306 gen_update_nip(ctx
, ctx
->nip
- 4);
2307 gen_reset_fpstatus();
2308 crf
= tcg_const_i32(crfD(ctx
->opcode
));
2309 gen_helper_fcmpu(cpu_fpr
[rA(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)], crf
);
2310 tcg_temp_free_i32(crf
);
2311 gen_helper_float_check_status();
2314 /*** Floating-point move ***/
2316 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2317 GEN_FLOAT_B(abs
, 0x08, 0x08, 0, PPC_FLOAT
);
2320 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2321 GEN_HANDLER(fmr
, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT
)
2323 if (unlikely(!ctx
->fpu_enabled
)) {
2324 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2327 tcg_gen_mov_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)]);
2328 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 0, Rc(ctx
->opcode
) != 0);
2332 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2333 GEN_FLOAT_B(nabs
, 0x08, 0x04, 0, PPC_FLOAT
);
2335 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2336 GEN_FLOAT_B(neg
, 0x08, 0x01, 0, PPC_FLOAT
);
2338 /*** Floating-Point status & ctrl register ***/
2340 GEN_HANDLER(mcrfs
, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT
)
2344 if (unlikely(!ctx
->fpu_enabled
)) {
2345 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2348 bfa
= 4 * (7 - crfS(ctx
->opcode
));
2349 tcg_gen_shri_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_fpscr
, bfa
);
2350 tcg_gen_andi_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfD(ctx
->opcode
)], 0xf);
2351 tcg_gen_andi_i32(cpu_fpscr
, cpu_fpscr
, ~(0xF << bfa
));
2355 GEN_HANDLER(mffs
, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT
)
2357 if (unlikely(!ctx
->fpu_enabled
)) {
2358 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2361 gen_reset_fpstatus();
2362 tcg_gen_extu_i32_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpscr
);
2363 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 0, Rc(ctx
->opcode
) != 0);
2367 GEN_HANDLER(mtfsb0
, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT
)
2371 if (unlikely(!ctx
->fpu_enabled
)) {
2372 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2375 crb
= 31 - crbD(ctx
->opcode
);
2376 gen_reset_fpstatus();
2377 if (likely(crb
!= FPSCR_FEX
&& crb
!= FPSCR_VX
)) {
2379 /* NIP cannot be restored if the memory exception comes from an helper */
2380 gen_update_nip(ctx
, ctx
->nip
- 4);
2381 t0
= tcg_const_i32(crb
);
2382 gen_helper_fpscr_clrbit(t0
);
2383 tcg_temp_free_i32(t0
);
2385 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2386 tcg_gen_shri_i32(cpu_crf
[1], cpu_fpscr
, FPSCR_OX
);
2391 GEN_HANDLER(mtfsb1
, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT
)
2395 if (unlikely(!ctx
->fpu_enabled
)) {
2396 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2399 crb
= 31 - crbD(ctx
->opcode
);
2400 gen_reset_fpstatus();
2401 /* XXX: we pretend we can only do IEEE floating-point computations */
2402 if (likely(crb
!= FPSCR_FEX
&& crb
!= FPSCR_VX
&& crb
!= FPSCR_NI
)) {
2404 /* NIP cannot be restored if the memory exception comes from an helper */
2405 gen_update_nip(ctx
, ctx
->nip
- 4);
2406 t0
= tcg_const_i32(crb
);
2407 gen_helper_fpscr_setbit(t0
);
2408 tcg_temp_free_i32(t0
);
2410 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2411 tcg_gen_shri_i32(cpu_crf
[1], cpu_fpscr
, FPSCR_OX
);
2413 /* We can raise a differed exception */
2414 gen_helper_float_check_status();
2418 GEN_HANDLER(mtfsf
, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT
)
2422 if (unlikely(!ctx
->fpu_enabled
)) {
2423 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2426 /* NIP cannot be restored if the memory exception comes from an helper */
2427 gen_update_nip(ctx
, ctx
->nip
- 4);
2428 gen_reset_fpstatus();
2429 t0
= tcg_const_i32(FM(ctx
->opcode
));
2430 gen_helper_store_fpscr(cpu_fpr
[rB(ctx
->opcode
)], t0
);
2431 tcg_temp_free_i32(t0
);
2432 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2433 tcg_gen_shri_i32(cpu_crf
[1], cpu_fpscr
, FPSCR_OX
);
2435 /* We can raise a differed exception */
2436 gen_helper_float_check_status();
2440 GEN_HANDLER(mtfsfi
, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT
)
2446 if (unlikely(!ctx
->fpu_enabled
)) {
2447 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2450 bf
= crbD(ctx
->opcode
) >> 2;
2452 /* NIP cannot be restored if the memory exception comes from an helper */
2453 gen_update_nip(ctx
, ctx
->nip
- 4);
2454 gen_reset_fpstatus();
2455 t0
= tcg_const_i64(FPIMM(ctx
->opcode
) << (4 * sh
));
2456 t1
= tcg_const_i32(1 << sh
);
2457 gen_helper_store_fpscr(t0
, t1
);
2458 tcg_temp_free_i64(t0
);
2459 tcg_temp_free_i32(t1
);
2460 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2461 tcg_gen_shri_i32(cpu_crf
[1], cpu_fpscr
, FPSCR_OX
);
2463 /* We can raise a differed exception */
2464 gen_helper_float_check_status();
2467 /*** Addressing modes ***/
2468 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2469 static always_inline
void gen_addr_imm_index (DisasContext
*ctx
, TCGv EA
, target_long maskl
)
2471 target_long simm
= SIMM(ctx
->opcode
);
2474 if (rA(ctx
->opcode
) == 0) {
2475 #if defined(TARGET_PPC64)
2476 if (!ctx
->sf_mode
) {
2477 tcg_gen_movi_tl(EA
, (uint32_t)simm
);
2480 tcg_gen_movi_tl(EA
, simm
);
2481 } else if (likely(simm
!= 0)) {
2482 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], simm
);
2483 #if defined(TARGET_PPC64)
2484 if (!ctx
->sf_mode
) {
2485 tcg_gen_ext32u_tl(EA
, EA
);
2489 #if defined(TARGET_PPC64)
2490 if (!ctx
->sf_mode
) {
2491 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2494 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2498 static always_inline
void gen_addr_reg_index (DisasContext
*ctx
, TCGv EA
)
2500 if (rA(ctx
->opcode
) == 0) {
2501 #if defined(TARGET_PPC64)
2502 if (!ctx
->sf_mode
) {
2503 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2506 tcg_gen_mov_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2508 tcg_gen_add_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2509 #if defined(TARGET_PPC64)
2510 if (!ctx
->sf_mode
) {
2511 tcg_gen_ext32u_tl(EA
, EA
);
2517 static always_inline
void gen_addr_register (DisasContext
*ctx
, TCGv EA
)
2519 if (rA(ctx
->opcode
) == 0) {
2520 tcg_gen_movi_tl(EA
, 0);
2522 #if defined(TARGET_PPC64)
2523 if (!ctx
->sf_mode
) {
2524 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2527 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2531 static always_inline
void gen_addr_add (DisasContext
*ctx
, TCGv ret
, TCGv arg1
, target_long val
)
2533 tcg_gen_addi_tl(ret
, arg1
, val
);
2534 #if defined(TARGET_PPC64)
2535 if (!ctx
->sf_mode
) {
2536 tcg_gen_ext32u_tl(ret
, ret
);
2541 static always_inline
void gen_check_align (DisasContext
*ctx
, TCGv EA
, int mask
)
2543 int l1
= gen_new_label();
2544 TCGv t0
= tcg_temp_new();
2546 /* NIP cannot be restored if the memory exception comes from an helper */
2547 gen_update_nip(ctx
, ctx
->nip
- 4);
2548 tcg_gen_andi_tl(t0
, EA
, mask
);
2549 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
2550 t1
= tcg_const_i32(POWERPC_EXCP_ALIGN
);
2551 t2
= tcg_const_i32(0);
2552 gen_helper_raise_exception_err(t1
, t2
);
2553 tcg_temp_free_i32(t1
);
2554 tcg_temp_free_i32(t2
);
2559 /*** Integer load ***/
2560 static always_inline
void gen_qemu_ld8u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2562 tcg_gen_qemu_ld8u(arg1
, arg2
, ctx
->mem_idx
);
2565 static always_inline
void gen_qemu_ld8s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2567 tcg_gen_qemu_ld8s(arg1
, arg2
, ctx
->mem_idx
);
2570 static always_inline
void gen_qemu_ld16u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2572 tcg_gen_qemu_ld16u(arg1
, arg2
, ctx
->mem_idx
);
2573 if (unlikely(ctx
->le_mode
)) {
2574 #if defined(TARGET_PPC64)
2575 TCGv_i32 t0
= tcg_temp_new_i32();
2576 tcg_gen_trunc_tl_i32(t0
, arg1
);
2577 tcg_gen_bswap16_i32(t0
, t0
);
2578 tcg_gen_extu_i32_tl(arg1
, t0
);
2579 tcg_temp_free_i32(t0
);
2581 tcg_gen_bswap16_i32(arg1
, arg1
);
2586 static always_inline
void gen_qemu_ld16s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2588 if (unlikely(ctx
->le_mode
)) {
2589 #if defined(TARGET_PPC64)
2591 tcg_gen_qemu_ld16u(arg1
, arg2
, ctx
->mem_idx
);
2592 t0
= tcg_temp_new_i32();
2593 tcg_gen_trunc_tl_i32(t0
, arg1
);
2594 tcg_gen_bswap16_i32(t0
, t0
);
2595 tcg_gen_extu_i32_tl(arg1
, t0
);
2596 tcg_gen_ext16s_tl(arg1
, arg1
);
2597 tcg_temp_free_i32(t0
);
2599 tcg_gen_qemu_ld16u(arg1
, arg2
, ctx
->mem_idx
);
2600 tcg_gen_bswap16_i32(arg1
, arg1
);
2601 tcg_gen_ext16s_i32(arg1
, arg1
);
2604 tcg_gen_qemu_ld16s(arg1
, arg2
, ctx
->mem_idx
);
2608 static always_inline
void gen_qemu_ld32u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2610 tcg_gen_qemu_ld32u(arg1
, arg2
, ctx
->mem_idx
);
2611 if (unlikely(ctx
->le_mode
)) {
2612 #if defined(TARGET_PPC64)
2613 TCGv_i32 t0
= tcg_temp_new_i32();
2614 tcg_gen_trunc_tl_i32(t0
, arg1
);
2615 tcg_gen_bswap_i32(t0
, t0
);
2616 tcg_gen_extu_i32_tl(arg1
, t0
);
2617 tcg_temp_free_i32(t0
);
2619 tcg_gen_bswap_i32(arg1
, arg1
);
2624 #if defined(TARGET_PPC64)
2625 static always_inline
void gen_qemu_ld32s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2627 if (unlikely(ctx
->mem_idx
)) {
2629 tcg_gen_qemu_ld32u(arg1
, arg2
, ctx
->mem_idx
);
2630 t0
= tcg_temp_new_i32();
2631 tcg_gen_trunc_tl_i32(t0
, arg1
);
2632 tcg_gen_bswap_i32(t0
, t0
);
2633 tcg_gen_ext_i32_tl(arg1
, t0
);
2634 tcg_temp_free_i32(t0
);
2636 tcg_gen_qemu_ld32s(arg1
, arg2
, ctx
->mem_idx
);
2640 static always_inline
void gen_qemu_ld64(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
2642 tcg_gen_qemu_ld64(arg1
, arg2
, ctx
->mem_idx
);
2643 if (unlikely(ctx
->le_mode
)) {
2644 tcg_gen_bswap_i64(arg1
, arg1
);
2648 static always_inline
void gen_qemu_st8(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2650 tcg_gen_qemu_st8(arg1
, arg2
, ctx
->mem_idx
);
2653 static always_inline
void gen_qemu_st16(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2655 if (unlikely(ctx
->le_mode
)) {
2656 #if defined(TARGET_PPC64)
2659 t0
= tcg_temp_new_i32();
2660 tcg_gen_trunc_tl_i32(t0
, arg1
);
2661 tcg_gen_ext16u_i32(t0
, t0
);
2662 tcg_gen_bswap16_i32(t0
, t0
);
2663 t1
= tcg_temp_new();
2664 tcg_gen_extu_i32_tl(t1
, t0
);
2665 tcg_temp_free_i32(t0
);
2666 tcg_gen_qemu_st16(t1
, arg2
, ctx
->mem_idx
);
2669 TCGv t0
= tcg_temp_new();
2670 tcg_gen_ext16u_tl(t0
, arg1
);
2671 tcg_gen_bswap16_i32(t0
, t0
);
2672 tcg_gen_qemu_st16(t0
, arg2
, ctx
->mem_idx
);
2676 tcg_gen_qemu_st16(arg1
, arg2
, ctx
->mem_idx
);
2680 static always_inline
void gen_qemu_st32(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2682 if (unlikely(ctx
->le_mode
)) {
2683 #if defined(TARGET_PPC64)
2686 t0
= tcg_temp_new_i32();
2687 tcg_gen_trunc_tl_i32(t0
, arg1
);
2688 tcg_gen_bswap_i32(t0
, t0
);
2689 t1
= tcg_temp_new();
2690 tcg_gen_extu_i32_tl(t1
, t0
);
2691 tcg_temp_free_i32(t0
);
2692 tcg_gen_qemu_st32(t1
, arg2
, ctx
->mem_idx
);
2695 TCGv t0
= tcg_temp_new_i32();
2696 tcg_gen_bswap_i32(t0
, arg1
);
2697 tcg_gen_qemu_st32(t0
, arg2
, ctx
->mem_idx
);
2701 tcg_gen_qemu_st32(arg1
, arg2
, ctx
->mem_idx
);
2705 static always_inline
void gen_qemu_st64(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
2707 if (unlikely(ctx
->le_mode
)) {
2708 TCGv_i64 t0
= tcg_temp_new_i64();
2709 tcg_gen_bswap_i64(t0
, arg1
);
2710 tcg_gen_qemu_st64(t0
, arg2
, ctx
->mem_idx
);
2711 tcg_temp_free_i64(t0
);
2713 tcg_gen_qemu_st64(arg1
, arg2
, ctx
->mem_idx
);
2716 #define GEN_LD(name, ldop, opc, type) \
2717 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2720 gen_set_access_type(ctx, ACCESS_INT); \
2721 EA = tcg_temp_new(); \
2722 gen_addr_imm_index(ctx, EA, 0); \
2723 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2724 tcg_temp_free(EA); \
2727 #define GEN_LDU(name, ldop, opc, type) \
2728 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2731 if (unlikely(rA(ctx->opcode) == 0 || \
2732 rA(ctx->opcode) == rD(ctx->opcode))) { \
2733 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2736 gen_set_access_type(ctx, ACCESS_INT); \
2737 EA = tcg_temp_new(); \
2738 if (type == PPC_64B) \
2739 gen_addr_imm_index(ctx, EA, 0x03); \
2741 gen_addr_imm_index(ctx, EA, 0); \
2742 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2743 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2744 tcg_temp_free(EA); \
2747 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2748 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2751 if (unlikely(rA(ctx->opcode) == 0 || \
2752 rA(ctx->opcode) == rD(ctx->opcode))) { \
2753 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2756 gen_set_access_type(ctx, ACCESS_INT); \
2757 EA = tcg_temp_new(); \
2758 gen_addr_reg_index(ctx, EA); \
2759 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2760 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2761 tcg_temp_free(EA); \
2764 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2765 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2768 gen_set_access_type(ctx, ACCESS_INT); \
2769 EA = tcg_temp_new(); \
2770 gen_addr_reg_index(ctx, EA); \
2771 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2772 tcg_temp_free(EA); \
2775 #define GEN_LDS(name, ldop, op, type) \
2776 GEN_LD(name, ldop, op | 0x20, type); \
2777 GEN_LDU(name, ldop, op | 0x21, type); \
2778 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2779 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2781 /* lbz lbzu lbzux lbzx */
2782 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
);
2783 /* lha lhau lhaux lhax */
2784 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
);
2785 /* lhz lhzu lhzux lhzx */
2786 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
);
2787 /* lwz lwzu lwzux lwzx */
2788 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
);
2789 #if defined(TARGET_PPC64)
2791 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
);
2793 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
);
2795 GEN_LDUX(ld
, ld64
, 0x15, 0x01, PPC_64B
);
2797 GEN_LDX(ld
, ld64
, 0x15, 0x00, PPC_64B
);
2798 GEN_HANDLER(ld
, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B
)
2801 if (Rc(ctx
->opcode
)) {
2802 if (unlikely(rA(ctx
->opcode
) == 0 ||
2803 rA(ctx
->opcode
) == rD(ctx
->opcode
))) {
2804 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2808 gen_set_access_type(ctx
, ACCESS_INT
);
2809 EA
= tcg_temp_new();
2810 gen_addr_imm_index(ctx
, EA
, 0x03);
2811 if (ctx
->opcode
& 0x02) {
2812 /* lwa (lwau is undefined) */
2813 gen_qemu_ld32s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2816 gen_qemu_ld64(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2818 if (Rc(ctx
->opcode
))
2819 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2823 GEN_HANDLER(lq
, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX
)
2825 #if defined(CONFIG_USER_ONLY)
2826 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2831 /* Restore CPU state */
2832 if (unlikely(ctx
->mem_idx
== 0)) {
2833 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2836 ra
= rA(ctx
->opcode
);
2837 rd
= rD(ctx
->opcode
);
2838 if (unlikely((rd
& 1) || rd
== ra
)) {
2839 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2842 if (unlikely(ctx
->le_mode
)) {
2843 /* Little-endian mode is not handled */
2844 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
2847 gen_set_access_type(ctx
, ACCESS_INT
);
2848 EA
= tcg_temp_new();
2849 gen_addr_imm_index(ctx
, EA
, 0x0F);
2850 gen_qemu_ld64(ctx
, cpu_gpr
[rd
], EA
);
2851 gen_addr_add(ctx
, EA
, EA
, 8);
2852 gen_qemu_ld64(ctx
, cpu_gpr
[rd
+1], EA
);
2858 /*** Integer store ***/
2859 #define GEN_ST(name, stop, opc, type) \
2860 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2863 gen_set_access_type(ctx, ACCESS_INT); \
2864 EA = tcg_temp_new(); \
2865 gen_addr_imm_index(ctx, EA, 0); \
2866 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2867 tcg_temp_free(EA); \
2870 #define GEN_STU(name, stop, opc, type) \
2871 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2874 if (unlikely(rA(ctx->opcode) == 0)) { \
2875 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2878 gen_set_access_type(ctx, ACCESS_INT); \
2879 EA = tcg_temp_new(); \
2880 if (type == PPC_64B) \
2881 gen_addr_imm_index(ctx, EA, 0x03); \
2883 gen_addr_imm_index(ctx, EA, 0); \
2884 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2885 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2886 tcg_temp_free(EA); \
2889 #define GEN_STUX(name, stop, opc2, opc3, type) \
2890 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2893 if (unlikely(rA(ctx->opcode) == 0)) { \
2894 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2897 gen_set_access_type(ctx, ACCESS_INT); \
2898 EA = tcg_temp_new(); \
2899 gen_addr_reg_index(ctx, EA); \
2900 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2901 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2902 tcg_temp_free(EA); \
2905 #define GEN_STX(name, stop, opc2, opc3, type) \
2906 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2909 gen_set_access_type(ctx, ACCESS_INT); \
2910 EA = tcg_temp_new(); \
2911 gen_addr_reg_index(ctx, EA); \
2912 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2913 tcg_temp_free(EA); \
2916 #define GEN_STS(name, stop, op, type) \
2917 GEN_ST(name, stop, op | 0x20, type); \
2918 GEN_STU(name, stop, op | 0x21, type); \
2919 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2920 GEN_STX(name, stop, 0x17, op | 0x00, type)
2922 /* stb stbu stbux stbx */
2923 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
);
2924 /* sth sthu sthux sthx */
2925 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
);
2926 /* stw stwu stwux stwx */
2927 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
);
2928 #if defined(TARGET_PPC64)
2929 GEN_STUX(std
, st64
, 0x15, 0x05, PPC_64B
);
2930 GEN_STX(std
, st64
, 0x15, 0x04, PPC_64B
);
2931 GEN_HANDLER(std
, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B
)
2936 rs
= rS(ctx
->opcode
);
2937 if ((ctx
->opcode
& 0x3) == 0x2) {
2938 #if defined(CONFIG_USER_ONLY)
2939 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2942 if (unlikely(ctx
->mem_idx
== 0)) {
2943 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2946 if (unlikely(rs
& 1)) {
2947 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2950 if (unlikely(ctx
->le_mode
)) {
2951 /* Little-endian mode is not handled */
2952 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
2955 gen_set_access_type(ctx
, ACCESS_INT
);
2956 EA
= tcg_temp_new();
2957 gen_addr_imm_index(ctx
, EA
, 0x03);
2958 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
2959 gen_addr_add(ctx
, EA
, EA
, 8);
2960 gen_qemu_st64(ctx
, cpu_gpr
[rs
+1], EA
);
2965 if (Rc(ctx
->opcode
)) {
2966 if (unlikely(rA(ctx
->opcode
) == 0)) {
2967 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2971 gen_set_access_type(ctx
, ACCESS_INT
);
2972 EA
= tcg_temp_new();
2973 gen_addr_imm_index(ctx
, EA
, 0x03);
2974 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
2975 if (Rc(ctx
->opcode
))
2976 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2981 /*** Integer load and store with byte reverse ***/
2983 static void always_inline
gen_qemu_ld16ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2985 tcg_gen_qemu_ld16u(arg1
, arg2
, ctx
->mem_idx
);
2986 if (likely(!ctx
->le_mode
)) {
2987 #if defined(TARGET_PPC64)
2988 TCGv_i32 t0
= tcg_temp_new_i32();
2989 tcg_gen_trunc_tl_i32(t0
, arg1
);
2990 tcg_gen_bswap16_i32(t0
, t0
);
2991 tcg_gen_extu_i32_tl(arg1
, t0
);
2992 tcg_temp_free_i32(t0
);
2994 tcg_gen_bswap16_i32(arg1
, arg1
);
2998 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
);
3001 static void always_inline
gen_qemu_ld32ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
3003 tcg_gen_qemu_ld32u(arg1
, arg2
, ctx
->mem_idx
);
3004 if (likely(!ctx
->le_mode
)) {
3005 #if defined(TARGET_PPC64)
3006 TCGv_i32 t0
= tcg_temp_new_i32();
3007 tcg_gen_trunc_tl_i32(t0
, arg1
);
3008 tcg_gen_bswap_i32(t0
, t0
);
3009 tcg_gen_extu_i32_tl(arg1
, t0
);
3010 tcg_temp_free_i32(t0
);
3012 tcg_gen_bswap_i32(arg1
, arg1
);
3016 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
);
3019 static void always_inline
gen_qemu_st16r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
3021 if (likely(!ctx
->le_mode
)) {
3022 #if defined(TARGET_PPC64)
3025 t0
= tcg_temp_new_i32();
3026 tcg_gen_trunc_tl_i32(t0
, arg1
);
3027 tcg_gen_ext16u_i32(t0
, t0
);
3028 tcg_gen_bswap16_i32(t0
, t0
);
3029 t1
= tcg_temp_new();
3030 tcg_gen_extu_i32_tl(t1
, t0
);
3031 tcg_temp_free_i32(t0
);
3032 tcg_gen_qemu_st16(t1
, arg2
, ctx
->mem_idx
);
3035 TCGv t0
= tcg_temp_new();
3036 tcg_gen_ext16u_tl(t0
, arg1
);
3037 tcg_gen_bswap16_i32(t0
, t0
);
3038 tcg_gen_qemu_st16(t0
, arg2
, ctx
->mem_idx
);
3042 tcg_gen_qemu_st16(arg1
, arg2
, ctx
->mem_idx
);
3045 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
);
3048 static void always_inline
gen_qemu_st32r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
3050 if (likely(!ctx
->le_mode
)) {
3051 #if defined(TARGET_PPC64)
3054 t0
= tcg_temp_new_i32();
3055 tcg_gen_trunc_tl_i32(t0
, arg1
);
3056 tcg_gen_bswap_i32(t0
, t0
);
3057 t1
= tcg_temp_new();
3058 tcg_gen_extu_i32_tl(t1
, t0
);
3059 tcg_temp_free_i32(t0
);
3060 tcg_gen_qemu_st32(t1
, arg2
, ctx
->mem_idx
);
3063 TCGv t0
= tcg_temp_new_i32();
3064 tcg_gen_bswap_i32(t0
, arg1
);
3065 tcg_gen_qemu_st32(t0
, arg2
, ctx
->mem_idx
);
3069 tcg_gen_qemu_st32(arg1
, arg2
, ctx
->mem_idx
);
3072 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
);
3074 /*** Integer load and store multiple ***/
3076 GEN_HANDLER(lmw
, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
3080 gen_set_access_type(ctx
, ACCESS_INT
);
3081 /* NIP cannot be restored if the memory exception comes from an helper */
3082 gen_update_nip(ctx
, ctx
->nip
- 4);
3083 t0
= tcg_temp_new();
3084 t1
= tcg_const_i32(rD(ctx
->opcode
));
3085 gen_addr_imm_index(ctx
, t0
, 0);
3086 gen_helper_lmw(t0
, t1
);
3088 tcg_temp_free_i32(t1
);
3092 GEN_HANDLER(stmw
, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
3096 gen_set_access_type(ctx
, ACCESS_INT
);
3097 /* NIP cannot be restored if the memory exception comes from an helper */
3098 gen_update_nip(ctx
, ctx
->nip
- 4);
3099 t0
= tcg_temp_new();
3100 t1
= tcg_const_i32(rS(ctx
->opcode
));
3101 gen_addr_imm_index(ctx
, t0
, 0);
3102 gen_helper_stmw(t0
, t1
);
3104 tcg_temp_free_i32(t1
);
3107 /*** Integer load and store strings ***/
3109 /* PowerPC32 specification says we must generate an exception if
3110 * rA is in the range of registers to be loaded.
3111 * In an other hand, IBM says this is valid, but rA won't be loaded.
3112 * For now, I'll follow the spec...
3114 GEN_HANDLER(lswi
, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING
)
3118 int nb
= NB(ctx
->opcode
);
3119 int start
= rD(ctx
->opcode
);
3120 int ra
= rA(ctx
->opcode
);
3126 if (unlikely(((start
+ nr
) > 32 &&
3127 start
<= ra
&& (start
+ nr
- 32) > ra
) ||
3128 ((start
+ nr
) <= 32 && start
<= ra
&& (start
+ nr
) > ra
))) {
3129 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
3132 gen_set_access_type(ctx
, ACCESS_INT
);
3133 /* NIP cannot be restored if the memory exception comes from an helper */
3134 gen_update_nip(ctx
, ctx
->nip
- 4);
3135 t0
= tcg_temp_new();
3136 gen_addr_register(ctx
, t0
);
3137 t1
= tcg_const_i32(nb
);
3138 t2
= tcg_const_i32(start
);
3139 gen_helper_lsw(t0
, t1
, t2
);
3141 tcg_temp_free_i32(t1
);
3142 tcg_temp_free_i32(t2
);
3146 GEN_HANDLER(lswx
, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING
)
3149 TCGv_i32 t1
, t2
, t3
;
3150 gen_set_access_type(ctx
, ACCESS_INT
);
3151 /* NIP cannot be restored if the memory exception comes from an helper */
3152 gen_update_nip(ctx
, ctx
->nip
- 4);
3153 t0
= tcg_temp_new();
3154 gen_addr_reg_index(ctx
, t0
);
3155 t1
= tcg_const_i32(rD(ctx
->opcode
));
3156 t2
= tcg_const_i32(rA(ctx
->opcode
));
3157 t3
= tcg_const_i32(rB(ctx
->opcode
));
3158 gen_helper_lswx(t0
, t1
, t2
, t3
);
3160 tcg_temp_free_i32(t1
);
3161 tcg_temp_free_i32(t2
);
3162 tcg_temp_free_i32(t3
);
3166 GEN_HANDLER(stswi
, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING
)
3170 int nb
= NB(ctx
->opcode
);
3171 gen_set_access_type(ctx
, ACCESS_INT
);
3172 /* NIP cannot be restored if the memory exception comes from an helper */
3173 gen_update_nip(ctx
, ctx
->nip
- 4);
3174 t0
= tcg_temp_new();
3175 gen_addr_register(ctx
, t0
);
3178 t1
= tcg_const_i32(nb
);
3179 t2
= tcg_const_i32(rS(ctx
->opcode
));
3180 gen_helper_stsw(t0
, t1
, t2
);
3182 tcg_temp_free_i32(t1
);
3183 tcg_temp_free_i32(t2
);
3187 GEN_HANDLER(stswx
, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING
)
3191 gen_set_access_type(ctx
, ACCESS_INT
);
3192 /* NIP cannot be restored if the memory exception comes from an helper */
3193 gen_update_nip(ctx
, ctx
->nip
- 4);
3194 t0
= tcg_temp_new();
3195 gen_addr_reg_index(ctx
, t0
);
3196 t1
= tcg_temp_new_i32();
3197 tcg_gen_trunc_tl_i32(t1
, cpu_xer
);
3198 tcg_gen_andi_i32(t1
, t1
, 0x7F);
3199 t2
= tcg_const_i32(rS(ctx
->opcode
));
3200 gen_helper_stsw(t0
, t1
, t2
);
3202 tcg_temp_free_i32(t1
);
3203 tcg_temp_free_i32(t2
);
3206 /*** Memory synchronisation ***/
3208 GEN_HANDLER(eieio
, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO
)
3213 GEN_HANDLER(isync
, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM
)
3215 gen_stop_exception(ctx
);
3219 GEN_HANDLER(lwarx
, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES
)
3222 gen_set_access_type(ctx
, ACCESS_RES
);
3223 t0
= tcg_temp_local_new();
3224 gen_addr_reg_index(ctx
, t0
);
3225 gen_check_align(ctx
, t0
, 0x03);
3226 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
3227 tcg_gen_mov_tl(cpu_reserve
, t0
);
3232 GEN_HANDLER2(stwcx_
, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES
)
3236 gen_set_access_type(ctx
, ACCESS_RES
);
3237 t0
= tcg_temp_local_new();
3238 gen_addr_reg_index(ctx
, t0
);
3239 gen_check_align(ctx
, t0
, 0x03);
3240 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_xer
);
3241 tcg_gen_shri_i32(cpu_crf
[0], cpu_crf
[0], XER_SO
);
3242 tcg_gen_andi_i32(cpu_crf
[0], cpu_crf
[0], 1);
3243 l1
= gen_new_label();
3244 tcg_gen_brcond_tl(TCG_COND_NE
, t0
, cpu_reserve
, l1
);
3245 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 1 << CRF_EQ
);
3246 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
3248 tcg_gen_movi_tl(cpu_reserve
, -1);
3252 #if defined(TARGET_PPC64)
3254 GEN_HANDLER(ldarx
, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B
)
3257 gen_set_access_type(ctx
, ACCESS_RES
);
3258 t0
= tcg_temp_local_new();
3259 gen_addr_reg_index(ctx
, t0
);
3260 gen_check_align(ctx
, t0
, 0x07);
3261 gen_qemu_ld64(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
3262 tcg_gen_mov_tl(cpu_reserve
, t0
);
3267 GEN_HANDLER2(stdcx_
, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B
)
3271 gen_set_access_type(ctx
, ACCESS_RES
);
3272 t0
= tcg_temp_local_new();
3273 gen_addr_reg_index(ctx
, t0
);
3274 gen_check_align(ctx
, t0
, 0x07);
3275 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_xer
);
3276 tcg_gen_shri_i32(cpu_crf
[0], cpu_crf
[0], XER_SO
);
3277 tcg_gen_andi_i32(cpu_crf
[0], cpu_crf
[0], 1);
3278 l1
= gen_new_label();
3279 tcg_gen_brcond_tl(TCG_COND_NE
, t0
, cpu_reserve
, l1
);
3280 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 1 << CRF_EQ
);
3281 gen_qemu_st64(ctx
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
3283 tcg_gen_movi_tl(cpu_reserve
, -1);
3286 #endif /* defined(TARGET_PPC64) */
3289 GEN_HANDLER(sync
, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC
)
3294 GEN_HANDLER(wait
, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT
)
3296 TCGv_i32 t0
= tcg_temp_new_i32();
3297 tcg_gen_st_i32(t0
, cpu_env
, offsetof(CPUState
, halted
));
3298 tcg_temp_free_i32(t0
);
3299 /* Stop translation, as the CPU is supposed to sleep from now */
3300 gen_exception_err(ctx
, EXCP_HLT
, 1);
3303 /*** Floating-point load ***/
3304 #define GEN_LDF(name, ldop, opc, type) \
3305 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
3308 if (unlikely(!ctx->fpu_enabled)) { \
3309 gen_exception(ctx, POWERPC_EXCP_FPU); \
3312 gen_set_access_type(ctx, ACCESS_FLOAT); \
3313 EA = tcg_temp_new(); \
3314 gen_addr_imm_index(ctx, EA, 0); \
3315 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3316 tcg_temp_free(EA); \
3319 #define GEN_LDUF(name, ldop, opc, type) \
3320 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3323 if (unlikely(!ctx->fpu_enabled)) { \
3324 gen_exception(ctx, POWERPC_EXCP_FPU); \
3327 if (unlikely(rA(ctx->opcode) == 0)) { \
3328 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3331 gen_set_access_type(ctx, ACCESS_FLOAT); \
3332 EA = tcg_temp_new(); \
3333 gen_addr_imm_index(ctx, EA, 0); \
3334 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3335 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3336 tcg_temp_free(EA); \
3339 #define GEN_LDUXF(name, ldop, opc, type) \
3340 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3343 if (unlikely(!ctx->fpu_enabled)) { \
3344 gen_exception(ctx, POWERPC_EXCP_FPU); \
3347 if (unlikely(rA(ctx->opcode) == 0)) { \
3348 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3351 gen_set_access_type(ctx, ACCESS_FLOAT); \
3352 EA = tcg_temp_new(); \
3353 gen_addr_reg_index(ctx, EA); \
3354 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3355 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3356 tcg_temp_free(EA); \
3359 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3360 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
3363 if (unlikely(!ctx->fpu_enabled)) { \
3364 gen_exception(ctx, POWERPC_EXCP_FPU); \
3367 gen_set_access_type(ctx, ACCESS_FLOAT); \
3368 EA = tcg_temp_new(); \
3369 gen_addr_reg_index(ctx, EA); \
3370 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3371 tcg_temp_free(EA); \
3374 #define GEN_LDFS(name, ldop, op, type) \
3375 GEN_LDF(name, ldop, op | 0x20, type); \
3376 GEN_LDUF(name, ldop, op | 0x21, type); \
3377 GEN_LDUXF(name, ldop, op | 0x01, type); \
3378 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3380 static always_inline
void gen_qemu_ld32fs(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3382 TCGv t0
= tcg_temp_new();
3383 TCGv_i32 t1
= tcg_temp_new_i32();
3384 gen_qemu_ld32u(ctx
, t0
, arg2
);
3385 tcg_gen_trunc_tl_i32(t1
, t0
);
3387 gen_helper_float32_to_float64(arg1
, t1
);
3388 tcg_temp_free_i32(t1
);
3391 /* lfd lfdu lfdux lfdx */
3392 GEN_LDFS(lfd
, ld64
, 0x12, PPC_FLOAT
);
3393 /* lfs lfsu lfsux lfsx */
3394 GEN_LDFS(lfs
, ld32fs
, 0x10, PPC_FLOAT
);
3396 /*** Floating-point store ***/
3397 #define GEN_STF(name, stop, opc, type) \
3398 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
3401 if (unlikely(!ctx->fpu_enabled)) { \
3402 gen_exception(ctx, POWERPC_EXCP_FPU); \
3405 gen_set_access_type(ctx, ACCESS_FLOAT); \
3406 EA = tcg_temp_new(); \
3407 gen_addr_imm_index(ctx, EA, 0); \
3408 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3409 tcg_temp_free(EA); \
3412 #define GEN_STUF(name, stop, opc, type) \
3413 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3416 if (unlikely(!ctx->fpu_enabled)) { \
3417 gen_exception(ctx, POWERPC_EXCP_FPU); \
3420 if (unlikely(rA(ctx->opcode) == 0)) { \
3421 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3424 gen_set_access_type(ctx, ACCESS_FLOAT); \
3425 EA = tcg_temp_new(); \
3426 gen_addr_imm_index(ctx, EA, 0); \
3427 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3428 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3429 tcg_temp_free(EA); \
3432 #define GEN_STUXF(name, stop, opc, type) \
3433 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3436 if (unlikely(!ctx->fpu_enabled)) { \
3437 gen_exception(ctx, POWERPC_EXCP_FPU); \
3440 if (unlikely(rA(ctx->opcode) == 0)) { \
3441 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3444 gen_set_access_type(ctx, ACCESS_FLOAT); \
3445 EA = tcg_temp_new(); \
3446 gen_addr_reg_index(ctx, EA); \
3447 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3448 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3449 tcg_temp_free(EA); \
3452 #define GEN_STXF(name, stop, opc2, opc3, type) \
3453 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
3456 if (unlikely(!ctx->fpu_enabled)) { \
3457 gen_exception(ctx, POWERPC_EXCP_FPU); \
3460 gen_set_access_type(ctx, ACCESS_FLOAT); \
3461 EA = tcg_temp_new(); \
3462 gen_addr_reg_index(ctx, EA); \
3463 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3464 tcg_temp_free(EA); \
3467 #define GEN_STFS(name, stop, op, type) \
3468 GEN_STF(name, stop, op | 0x20, type); \
3469 GEN_STUF(name, stop, op | 0x21, type); \
3470 GEN_STUXF(name, stop, op | 0x01, type); \
3471 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3473 static always_inline
void gen_qemu_st32fs(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3475 TCGv_i32 t0
= tcg_temp_new_i32();
3476 TCGv t1
= tcg_temp_new();
3477 gen_helper_float64_to_float32(t0
, arg1
);
3478 tcg_gen_extu_i32_tl(t1
, t0
);
3479 tcg_temp_free_i32(t0
);
3480 gen_qemu_st32(ctx
, t1
, arg2
);
3484 /* stfd stfdu stfdux stfdx */
3485 GEN_STFS(stfd
, st64
, 0x16, PPC_FLOAT
);
3486 /* stfs stfsu stfsux stfsx */
3487 GEN_STFS(stfs
, st32fs
, 0x14, PPC_FLOAT
);
3490 static always_inline
void gen_qemu_st32fiw(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3492 TCGv t0
= tcg_temp_new();
3493 tcg_gen_trunc_i64_tl(t0
, arg1
),
3494 gen_qemu_st32(ctx
, t0
, arg2
);
3498 GEN_STXF(stfiw
, st32fiw
, 0x17, 0x1E, PPC_FLOAT_STFIWX
);
3501 static always_inline
void gen_goto_tb (DisasContext
*ctx
, int n
,
3504 TranslationBlock
*tb
;
3506 #if defined(TARGET_PPC64)
3508 dest
= (uint32_t) dest
;
3510 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) &&
3511 likely(!ctx
->singlestep_enabled
)) {
3513 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3514 tcg_gen_exit_tb((long)tb
+ n
);
3516 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3517 if (unlikely(ctx
->singlestep_enabled
)) {
3518 if ((ctx
->singlestep_enabled
&
3519 (CPU_BRANCH_STEP
| CPU_SINGLE_STEP
)) &&
3520 ctx
->exception
== POWERPC_EXCP_BRANCH
) {
3521 target_ulong tmp
= ctx
->nip
;
3523 gen_exception(ctx
, POWERPC_EXCP_TRACE
);
3526 if (ctx
->singlestep_enabled
& GDBSTUB_SINGLE_STEP
) {
3527 gen_debug_exception(ctx
);
3534 static always_inline
void gen_setlr (DisasContext
*ctx
, target_ulong nip
)
3536 #if defined(TARGET_PPC64)
3537 if (ctx
->sf_mode
== 0)
3538 tcg_gen_movi_tl(cpu_lr
, (uint32_t)nip
);
3541 tcg_gen_movi_tl(cpu_lr
, nip
);
3545 GEN_HANDLER(b
, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW
)
3547 target_ulong li
, target
;
3549 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3550 /* sign extend LI */
3551 #if defined(TARGET_PPC64)
3553 li
= ((int64_t)LI(ctx
->opcode
) << 38) >> 38;
3556 li
= ((int32_t)LI(ctx
->opcode
) << 6) >> 6;
3557 if (likely(AA(ctx
->opcode
) == 0))
3558 target
= ctx
->nip
+ li
- 4;
3561 if (LK(ctx
->opcode
))
3562 gen_setlr(ctx
, ctx
->nip
);
3563 gen_goto_tb(ctx
, 0, target
);
3570 static always_inline
void gen_bcond (DisasContext
*ctx
, int type
)
3572 uint32_t bo
= BO(ctx
->opcode
);
3573 int l1
= gen_new_label();
3576 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3577 if (type
== BCOND_LR
|| type
== BCOND_CTR
) {
3578 target
= tcg_temp_local_new();
3579 if (type
== BCOND_CTR
)
3580 tcg_gen_mov_tl(target
, cpu_ctr
);
3582 tcg_gen_mov_tl(target
, cpu_lr
);
3584 if (LK(ctx
->opcode
))
3585 gen_setlr(ctx
, ctx
->nip
);
3586 l1
= gen_new_label();
3587 if ((bo
& 0x4) == 0) {
3588 /* Decrement and test CTR */
3589 TCGv temp
= tcg_temp_new();
3590 if (unlikely(type
== BCOND_CTR
)) {
3591 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3594 tcg_gen_subi_tl(cpu_ctr
, cpu_ctr
, 1);
3595 #if defined(TARGET_PPC64)
3597 tcg_gen_ext32u_tl(temp
, cpu_ctr
);
3600 tcg_gen_mov_tl(temp
, cpu_ctr
);
3602 tcg_gen_brcondi_tl(TCG_COND_NE
, temp
, 0, l1
);
3604 tcg_gen_brcondi_tl(TCG_COND_EQ
, temp
, 0, l1
);
3606 tcg_temp_free(temp
);
3608 if ((bo
& 0x10) == 0) {
3610 uint32_t bi
= BI(ctx
->opcode
);
3611 uint32_t mask
= 1 << (3 - (bi
& 0x03));
3612 TCGv_i32 temp
= tcg_temp_new_i32();
3615 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3616 tcg_gen_brcondi_i32(TCG_COND_EQ
, temp
, 0, l1
);
3618 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3619 tcg_gen_brcondi_i32(TCG_COND_NE
, temp
, 0, l1
);
3621 tcg_temp_free_i32(temp
);
3623 if (type
== BCOND_IM
) {
3624 target_ulong li
= (target_long
)((int16_t)(BD(ctx
->opcode
)));
3625 if (likely(AA(ctx
->opcode
) == 0)) {
3626 gen_goto_tb(ctx
, 0, ctx
->nip
+ li
- 4);
3628 gen_goto_tb(ctx
, 0, li
);
3631 gen_goto_tb(ctx
, 1, ctx
->nip
);
3633 #if defined(TARGET_PPC64)
3634 if (!(ctx
->sf_mode
))
3635 tcg_gen_andi_tl(cpu_nip
, target
, (uint32_t)~3);
3638 tcg_gen_andi_tl(cpu_nip
, target
, ~3);
3641 #if defined(TARGET_PPC64)
3642 if (!(ctx
->sf_mode
))
3643 tcg_gen_movi_tl(cpu_nip
, (uint32_t)ctx
->nip
);
3646 tcg_gen_movi_tl(cpu_nip
, ctx
->nip
);
3651 GEN_HANDLER(bc
, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW
)
3653 gen_bcond(ctx
, BCOND_IM
);
3656 GEN_HANDLER(bcctr
, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW
)
3658 gen_bcond(ctx
, BCOND_CTR
);
3661 GEN_HANDLER(bclr
, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW
)
3663 gen_bcond(ctx
, BCOND_LR
);
3666 /*** Condition register logical ***/
3667 #define GEN_CRLOGIC(name, tcg_op, opc) \
3668 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3673 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3674 t0 = tcg_temp_new_i32(); \
3676 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3678 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3680 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3681 t1 = tcg_temp_new_i32(); \
3682 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3684 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3686 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3688 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3689 tcg_op(t0, t0, t1); \
3690 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3691 tcg_gen_andi_i32(t0, t0, bitmask); \
3692 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3693 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3694 tcg_temp_free_i32(t0); \
3695 tcg_temp_free_i32(t1); \
3699 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08);
3701 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04);
3703 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09);
3705 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07);
3707 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01);
3709 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E);
3711 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D);
3713 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06);
3715 GEN_HANDLER(mcrf
, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER
)
3717 tcg_gen_mov_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfS(ctx
->opcode
)]);
3720 /*** System linkage ***/
3721 /* rfi (mem_idx only) */
3722 GEN_HANDLER(rfi
, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW
)
3724 #if defined(CONFIG_USER_ONLY)
3725 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3727 /* Restore CPU state */
3728 if (unlikely(!ctx
->mem_idx
)) {
3729 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3733 gen_sync_exception(ctx
);
3737 #if defined(TARGET_PPC64)
3738 GEN_HANDLER(rfid
, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B
)
3740 #if defined(CONFIG_USER_ONLY)
3741 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3743 /* Restore CPU state */
3744 if (unlikely(!ctx
->mem_idx
)) {
3745 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3749 gen_sync_exception(ctx
);
3753 GEN_HANDLER(hrfid
, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H
)
3755 #if defined(CONFIG_USER_ONLY)
3756 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3758 /* Restore CPU state */
3759 if (unlikely(ctx
->mem_idx
<= 1)) {
3760 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3764 gen_sync_exception(ctx
);
3770 #if defined(CONFIG_USER_ONLY)
3771 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3773 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3775 GEN_HANDLER(sc
, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW
)
3779 lev
= (ctx
->opcode
>> 5) & 0x7F;
3780 gen_exception_err(ctx
, POWERPC_SYSCALL
, lev
);
3785 GEN_HANDLER(tw
, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW
)
3787 TCGv_i32 t0
= tcg_const_i32(TO(ctx
->opcode
));
3788 /* Update the nip since this might generate a trap exception */
3789 gen_update_nip(ctx
, ctx
->nip
);
3790 gen_helper_tw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], t0
);
3791 tcg_temp_free_i32(t0
);
3795 GEN_HANDLER(twi
, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW
)
3797 TCGv t0
= tcg_const_tl(SIMM(ctx
->opcode
));
3798 TCGv_i32 t1
= tcg_const_i32(TO(ctx
->opcode
));
3799 /* Update the nip since this might generate a trap exception */
3800 gen_update_nip(ctx
, ctx
->nip
);
3801 gen_helper_tw(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
3803 tcg_temp_free_i32(t1
);
3806 #if defined(TARGET_PPC64)
3808 GEN_HANDLER(td
, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B
)
3810 TCGv_i32 t0
= tcg_const_i32(TO(ctx
->opcode
));
3811 /* Update the nip since this might generate a trap exception */
3812 gen_update_nip(ctx
, ctx
->nip
);
3813 gen_helper_td(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], t0
);
3814 tcg_temp_free_i32(t0
);
3818 GEN_HANDLER(tdi
, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B
)
3820 TCGv t0
= tcg_const_tl(SIMM(ctx
->opcode
));
3821 TCGv_i32 t1
= tcg_const_i32(TO(ctx
->opcode
));
3822 /* Update the nip since this might generate a trap exception */
3823 gen_update_nip(ctx
, ctx
->nip
);
3824 gen_helper_td(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
3826 tcg_temp_free_i32(t1
);
3830 /*** Processor control ***/
3832 GEN_HANDLER(mcrxr
, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC
)
3834 tcg_gen_trunc_tl_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_xer
);
3835 tcg_gen_shri_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfD(ctx
->opcode
)], XER_CA
);
3836 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_SO
| 1 << XER_OV
| 1 << XER_CA
));
3840 GEN_HANDLER(mfcr
, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC
)
3844 if (likely(ctx
->opcode
& 0x00100000)) {
3845 crm
= CRM(ctx
->opcode
);
3846 if (likely((crm
^ (crm
- 1)) == 0)) {
3848 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_crf
[7 - crn
]);
3851 gen_helper_load_cr(cpu_gpr
[rD(ctx
->opcode
)]);
3856 GEN_HANDLER(mfmsr
, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC
)
3858 #if defined(CONFIG_USER_ONLY)
3859 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3861 if (unlikely(!ctx
->mem_idx
)) {
3862 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3865 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_msr
);
3870 #define SPR_NOACCESS ((void *)(-1UL))
3872 static void spr_noaccess (void *opaque
, int sprn
)
3874 sprn
= ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
3875 printf("ERROR: try to access SPR %d !\n", sprn
);
3877 #define SPR_NOACCESS (&spr_noaccess)
3881 static always_inline
void gen_op_mfspr (DisasContext
*ctx
)
3883 void (*read_cb
)(void *opaque
, int gprn
, int sprn
);
3884 uint32_t sprn
= SPR(ctx
->opcode
);
3886 #if !defined(CONFIG_USER_ONLY)
3887 if (ctx
->mem_idx
== 2)
3888 read_cb
= ctx
->spr_cb
[sprn
].hea_read
;
3889 else if (ctx
->mem_idx
)
3890 read_cb
= ctx
->spr_cb
[sprn
].oea_read
;
3893 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
3894 if (likely(read_cb
!= NULL
)) {
3895 if (likely(read_cb
!= SPR_NOACCESS
)) {
3896 (*read_cb
)(ctx
, rD(ctx
->opcode
), sprn
);
3898 /* Privilege exception */
3899 /* This is a hack to avoid warnings when running Linux:
3900 * this OS breaks the PowerPC virtualisation model,
3901 * allowing userland application to read the PVR
3903 if (sprn
!= SPR_PVR
) {
3904 qemu_log("Trying to read privileged spr %d %03x at "
3905 ADDRX
"\n", sprn
, sprn
, ctx
->nip
);
3906 printf("Trying to read privileged spr %d %03x at " ADDRX
"\n",
3907 sprn
, sprn
, ctx
->nip
);
3909 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3913 qemu_log("Trying to read invalid spr %d %03x at "
3914 ADDRX
"\n", sprn
, sprn
, ctx
->nip
);
3915 printf("Trying to read invalid spr %d %03x at " ADDRX
"\n",
3916 sprn
, sprn
, ctx
->nip
);
3917 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
3921 GEN_HANDLER(mfspr
, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC
)
3927 GEN_HANDLER(mftb
, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB
)
3933 GEN_HANDLER(mtcrf
, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC
)
3937 crm
= CRM(ctx
->opcode
);
3938 if (likely((ctx
->opcode
& 0x00100000) || (crm
^ (crm
- 1)) == 0)) {
3939 TCGv_i32 temp
= tcg_temp_new_i32();
3941 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
3942 tcg_gen_shri_i32(cpu_crf
[7 - crn
], temp
, crn
* 4);
3943 tcg_gen_andi_i32(cpu_crf
[7 - crn
], cpu_crf
[7 - crn
], 0xf);
3944 tcg_temp_free_i32(temp
);
3946 TCGv_i32 temp
= tcg_const_i32(crm
);
3947 gen_helper_store_cr(cpu_gpr
[rS(ctx
->opcode
)], temp
);
3948 tcg_temp_free_i32(temp
);
3953 #if defined(TARGET_PPC64)
3954 GEN_HANDLER(mtmsrd
, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B
)
3956 #if defined(CONFIG_USER_ONLY)
3957 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3959 if (unlikely(!ctx
->mem_idx
)) {
3960 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3963 if (ctx
->opcode
& 0x00010000) {
3964 /* Special form that does not need any synchronisation */
3965 TCGv t0
= tcg_temp_new();
3966 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
3967 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~((1 << MSR_RI
) | (1 << MSR_EE
)));
3968 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
3971 /* XXX: we need to update nip before the store
3972 * if we enter power saving mode, we will exit the loop
3973 * directly from ppc_store_msr
3975 gen_update_nip(ctx
, ctx
->nip
);
3976 gen_helper_store_msr(cpu_gpr
[rS(ctx
->opcode
)]);
3977 /* Must stop the translation as machine state (may have) changed */
3978 /* Note that mtmsr is not always defined as context-synchronizing */
3979 gen_stop_exception(ctx
);
3985 GEN_HANDLER(mtmsr
, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC
)
3987 #if defined(CONFIG_USER_ONLY)
3988 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3990 if (unlikely(!ctx
->mem_idx
)) {
3991 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3994 if (ctx
->opcode
& 0x00010000) {
3995 /* Special form that does not need any synchronisation */
3996 TCGv t0
= tcg_temp_new();
3997 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
3998 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~((1 << MSR_RI
) | (1 << MSR_EE
)));
3999 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
4002 /* XXX: we need to update nip before the store
4003 * if we enter power saving mode, we will exit the loop
4004 * directly from ppc_store_msr
4006 gen_update_nip(ctx
, ctx
->nip
);
4007 #if defined(TARGET_PPC64)
4008 if (!ctx
->sf_mode
) {
4009 TCGv t0
= tcg_temp_new();
4010 TCGv t1
= tcg_temp_new();
4011 tcg_gen_andi_tl(t0
, cpu_msr
, 0xFFFFFFFF00000000ULL
);
4012 tcg_gen_ext32u_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)]);
4013 tcg_gen_or_tl(t0
, t0
, t1
);
4015 gen_helper_store_msr(t0
);
4019 gen_helper_store_msr(cpu_gpr
[rS(ctx
->opcode
)]);
4020 /* Must stop the translation as machine state (may have) changed */
4021 /* Note that mtmsr is not always defined as context-synchronizing */
4022 gen_stop_exception(ctx
);
4028 GEN_HANDLER(mtspr
, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC
)
4030 void (*write_cb
)(void *opaque
, int sprn
, int gprn
);
4031 uint32_t sprn
= SPR(ctx
->opcode
);
4033 #if !defined(CONFIG_USER_ONLY)
4034 if (ctx
->mem_idx
== 2)
4035 write_cb
= ctx
->spr_cb
[sprn
].hea_write
;
4036 else if (ctx
->mem_idx
)
4037 write_cb
= ctx
->spr_cb
[sprn
].oea_write
;
4040 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
4041 if (likely(write_cb
!= NULL
)) {
4042 if (likely(write_cb
!= SPR_NOACCESS
)) {
4043 (*write_cb
)(ctx
, sprn
, rS(ctx
->opcode
));
4045 /* Privilege exception */
4046 qemu_log("Trying to write privileged spr %d %03x at "
4047 ADDRX
"\n", sprn
, sprn
, ctx
->nip
);
4048 printf("Trying to write privileged spr %d %03x at " ADDRX
"\n",
4049 sprn
, sprn
, ctx
->nip
);
4050 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4054 qemu_log("Trying to write invalid spr %d %03x at "
4055 ADDRX
"\n", sprn
, sprn
, ctx
->nip
);
4056 printf("Trying to write invalid spr %d %03x at " ADDRX
"\n",
4057 sprn
, sprn
, ctx
->nip
);
4058 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4062 /*** Cache management ***/
4064 GEN_HANDLER(dcbf
, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE
)
4066 /* XXX: specification says this is treated as a load by the MMU */
4068 gen_set_access_type(ctx
, ACCESS_CACHE
);
4069 t0
= tcg_temp_new();
4070 gen_addr_reg_index(ctx
, t0
);
4071 gen_qemu_ld8u(ctx
, t0
, t0
);
4075 /* dcbi (Supervisor only) */
4076 GEN_HANDLER(dcbi
, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE
)
4078 #if defined(CONFIG_USER_ONLY)
4079 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4082 if (unlikely(!ctx
->mem_idx
)) {
4083 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4086 EA
= tcg_temp_new();
4087 gen_set_access_type(ctx
, ACCESS_CACHE
);
4088 gen_addr_reg_index(ctx
, EA
);
4089 val
= tcg_temp_new();
4090 /* XXX: specification says this should be treated as a store by the MMU */
4091 gen_qemu_ld8u(ctx
, val
, EA
);
4092 gen_qemu_st8(ctx
, val
, EA
);
4099 GEN_HANDLER(dcbst
, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE
)
4101 /* XXX: specification say this is treated as a load by the MMU */
4103 gen_set_access_type(ctx
, ACCESS_CACHE
);
4104 t0
= tcg_temp_new();
4105 gen_addr_reg_index(ctx
, t0
);
4106 gen_qemu_ld8u(ctx
, t0
, t0
);
4111 GEN_HANDLER(dcbt
, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE
)
4113 /* interpreted as no-op */
4114 /* XXX: specification say this is treated as a load by the MMU
4115 * but does not generate any exception
4120 GEN_HANDLER(dcbtst
, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE
)
4122 /* interpreted as no-op */
4123 /* XXX: specification say this is treated as a load by the MMU
4124 * but does not generate any exception
4129 GEN_HANDLER(dcbz
, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ
)
4132 gen_set_access_type(ctx
, ACCESS_CACHE
);
4133 /* NIP cannot be restored if the memory exception comes from an helper */
4134 gen_update_nip(ctx
, ctx
->nip
- 4);
4135 t0
= tcg_temp_new();
4136 gen_addr_reg_index(ctx
, t0
);
4137 gen_helper_dcbz(t0
);
4141 GEN_HANDLER2(dcbz_970
, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT
)
4144 gen_set_access_type(ctx
, ACCESS_CACHE
);
4145 /* NIP cannot be restored if the memory exception comes from an helper */
4146 gen_update_nip(ctx
, ctx
->nip
- 4);
4147 t0
= tcg_temp_new();
4148 gen_addr_reg_index(ctx
, t0
);
4149 if (ctx
->opcode
& 0x00200000)
4150 gen_helper_dcbz(t0
);
4152 gen_helper_dcbz_970(t0
);
4157 GEN_HANDLER(dst
, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC
)
4159 if (rA(ctx
->opcode
) == 0) {
4160 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
4162 /* interpreted as no-op */
4167 GEN_HANDLER(dstst
, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC
)
4169 if (rA(ctx
->opcode
) == 0) {
4170 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
4172 /* interpreted as no-op */
4178 GEN_HANDLER(dss
, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC
)
4180 /* interpreted as no-op */
4184 GEN_HANDLER(icbi
, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI
)
4187 gen_set_access_type(ctx
, ACCESS_CACHE
);
4188 /* NIP cannot be restored if the memory exception comes from an helper */
4189 gen_update_nip(ctx
, ctx
->nip
- 4);
4190 t0
= tcg_temp_new();
4191 gen_addr_reg_index(ctx
, t0
);
4192 gen_helper_icbi(t0
);
4198 GEN_HANDLER(dcba
, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA
)
4200 /* interpreted as no-op */
4201 /* XXX: specification say this is treated as a store by the MMU
4202 * but does not generate any exception
4206 /*** Segment register manipulation ***/
4207 /* Supervisor only: */
4209 GEN_HANDLER(mfsr
, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT
)
4211 #if defined(CONFIG_USER_ONLY)
4212 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4215 if (unlikely(!ctx
->mem_idx
)) {
4216 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4219 t0
= tcg_const_tl(SR(ctx
->opcode
));
4220 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4226 GEN_HANDLER(mfsrin
, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT
)
4228 #if defined(CONFIG_USER_ONLY)
4229 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4232 if (unlikely(!ctx
->mem_idx
)) {
4233 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4236 t0
= tcg_temp_new();
4237 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4238 tcg_gen_andi_tl(t0
, t0
, 0xF);
4239 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4245 GEN_HANDLER(mtsr
, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT
)
4247 #if defined(CONFIG_USER_ONLY)
4248 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4251 if (unlikely(!ctx
->mem_idx
)) {
4252 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4255 t0
= tcg_const_tl(SR(ctx
->opcode
));
4256 gen_helper_store_sr(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4262 GEN_HANDLER(mtsrin
, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT
)
4264 #if defined(CONFIG_USER_ONLY)
4265 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4268 if (unlikely(!ctx
->mem_idx
)) {
4269 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4272 t0
= tcg_temp_new();
4273 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4274 tcg_gen_andi_tl(t0
, t0
, 0xF);
4275 gen_helper_store_sr(t0
, cpu_gpr
[rD(ctx
->opcode
)]);
4280 #if defined(TARGET_PPC64)
4281 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4283 GEN_HANDLER2(mfsr_64b
, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B
)
4285 #if defined(CONFIG_USER_ONLY)
4286 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4289 if (unlikely(!ctx
->mem_idx
)) {
4290 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4293 t0
= tcg_const_tl(SR(ctx
->opcode
));
4294 gen_helper_load_slb(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4300 GEN_HANDLER2(mfsrin_64b
, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4303 #if defined(CONFIG_USER_ONLY)
4304 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4307 if (unlikely(!ctx
->mem_idx
)) {
4308 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4311 t0
= tcg_temp_new();
4312 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4313 tcg_gen_andi_tl(t0
, t0
, 0xF);
4314 gen_helper_load_slb(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4320 GEN_HANDLER2(mtsr_64b
, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B
)
4322 #if defined(CONFIG_USER_ONLY)
4323 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4326 if (unlikely(!ctx
->mem_idx
)) {
4327 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4330 t0
= tcg_const_tl(SR(ctx
->opcode
));
4331 gen_helper_store_slb(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4337 GEN_HANDLER2(mtsrin_64b
, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4340 #if defined(CONFIG_USER_ONLY)
4341 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4344 if (unlikely(!ctx
->mem_idx
)) {
4345 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4348 t0
= tcg_temp_new();
4349 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4350 tcg_gen_andi_tl(t0
, t0
, 0xF);
4351 gen_helper_store_slb(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4355 #endif /* defined(TARGET_PPC64) */
4357 /*** Lookaside buffer management ***/
4358 /* Optional & mem_idx only: */
4360 GEN_HANDLER(tlbia
, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA
)
4362 #if defined(CONFIG_USER_ONLY)
4363 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4365 if (unlikely(!ctx
->mem_idx
)) {
4366 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4374 GEN_HANDLER(tlbie
, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE
)
4376 #if defined(CONFIG_USER_ONLY)
4377 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4379 if (unlikely(!ctx
->mem_idx
)) {
4380 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4383 #if defined(TARGET_PPC64)
4384 if (!ctx
->sf_mode
) {
4385 TCGv t0
= tcg_temp_new();
4386 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
4387 gen_helper_tlbie(t0
);
4391 gen_helper_tlbie(cpu_gpr
[rB(ctx
->opcode
)]);
4396 GEN_HANDLER(tlbsync
, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC
)
4398 #if defined(CONFIG_USER_ONLY)
4399 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4401 if (unlikely(!ctx
->mem_idx
)) {
4402 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4405 /* This has no effect: it should ensure that all previous
4406 * tlbie have completed
4408 gen_stop_exception(ctx
);
4412 #if defined(TARGET_PPC64)
4414 GEN_HANDLER(slbia
, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI
)
4416 #if defined(CONFIG_USER_ONLY)
4417 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4419 if (unlikely(!ctx
->mem_idx
)) {
4420 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4428 GEN_HANDLER(slbie
, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI
)
4430 #if defined(CONFIG_USER_ONLY)
4431 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4433 if (unlikely(!ctx
->mem_idx
)) {
4434 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4437 gen_helper_slbie(cpu_gpr
[rB(ctx
->opcode
)]);
4442 /*** External control ***/
4445 GEN_HANDLER(eciwx
, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN
)
4448 /* Should check EAR[E] ! */
4449 gen_set_access_type(ctx
, ACCESS_EXT
);
4450 t0
= tcg_temp_new();
4451 gen_addr_reg_index(ctx
, t0
);
4452 gen_check_align(ctx
, t0
, 0x03);
4453 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
4458 GEN_HANDLER(ecowx
, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN
)
4461 /* Should check EAR[E] ! */
4462 gen_set_access_type(ctx
, ACCESS_EXT
);
4463 t0
= tcg_temp_new();
4464 gen_addr_reg_index(ctx
, t0
);
4465 gen_check_align(ctx
, t0
, 0x03);
4466 gen_qemu_st32(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
4470 /* PowerPC 601 specific instructions */
4472 GEN_HANDLER(abs
, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR
)
4474 int l1
= gen_new_label();
4475 int l2
= gen_new_label();
4476 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4477 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4480 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4482 if (unlikely(Rc(ctx
->opcode
) != 0))
4483 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4487 GEN_HANDLER(abso
, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR
)
4489 int l1
= gen_new_label();
4490 int l2
= gen_new_label();
4491 int l3
= gen_new_label();
4492 /* Start with XER OV disabled, the most likely case */
4493 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
4494 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l2
);
4495 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[rA(ctx
->opcode
)], 0x80000000, l1
);
4496 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
4499 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4502 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4504 if (unlikely(Rc(ctx
->opcode
) != 0))
4505 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4509 GEN_HANDLER(clcs
, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR
)
4511 TCGv_i32 t0
= tcg_const_i32(rA(ctx
->opcode
));
4512 gen_helper_clcs(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4513 tcg_temp_free_i32(t0
);
4514 /* Rc=1 sets CR0 to an undefined state */
4518 GEN_HANDLER(div
, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR
)
4520 gen_helper_div(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4521 if (unlikely(Rc(ctx
->opcode
) != 0))
4522 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4526 GEN_HANDLER(divo
, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR
)
4528 gen_helper_divo(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4529 if (unlikely(Rc(ctx
->opcode
) != 0))
4530 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4534 GEN_HANDLER(divs
, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR
)
4536 gen_helper_divs(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4537 if (unlikely(Rc(ctx
->opcode
) != 0))
4538 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4541 /* divso - divso. */
4542 GEN_HANDLER(divso
, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR
)
4544 gen_helper_divso(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4545 if (unlikely(Rc(ctx
->opcode
) != 0))
4546 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4550 GEN_HANDLER(doz
, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR
)
4552 int l1
= gen_new_label();
4553 int l2
= gen_new_label();
4554 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
4555 tcg_gen_sub_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4558 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4560 if (unlikely(Rc(ctx
->opcode
) != 0))
4561 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4565 GEN_HANDLER(dozo
, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR
)
4567 int l1
= gen_new_label();
4568 int l2
= gen_new_label();
4569 TCGv t0
= tcg_temp_new();
4570 TCGv t1
= tcg_temp_new();
4571 TCGv t2
= tcg_temp_new();
4572 /* Start with XER OV disabled, the most likely case */
4573 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
4574 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
4575 tcg_gen_sub_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4576 tcg_gen_xor_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4577 tcg_gen_xor_tl(t2
, cpu_gpr
[rA(ctx
->opcode
)], t0
);
4578 tcg_gen_andc_tl(t1
, t1
, t2
);
4579 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4580 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
4581 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
4584 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4589 if (unlikely(Rc(ctx
->opcode
) != 0))
4590 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4594 GEN_HANDLER(dozi
, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
)
4596 target_long simm
= SIMM(ctx
->opcode
);
4597 int l1
= gen_new_label();
4598 int l2
= gen_new_label();
4599 tcg_gen_brcondi_tl(TCG_COND_LT
, cpu_gpr
[rA(ctx
->opcode
)], simm
, l1
);
4600 tcg_gen_subfi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
, cpu_gpr
[rA(ctx
->opcode
)]);
4603 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4605 if (unlikely(Rc(ctx
->opcode
) != 0))
4606 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4609 /* lscbx - lscbx. */
4610 GEN_HANDLER(lscbx
, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR
)
4612 TCGv t0
= tcg_temp_new();
4613 TCGv_i32 t1
= tcg_const_i32(rD(ctx
->opcode
));
4614 TCGv_i32 t2
= tcg_const_i32(rA(ctx
->opcode
));
4615 TCGv_i32 t3
= tcg_const_i32(rB(ctx
->opcode
));
4617 gen_addr_reg_index(ctx
, t0
);
4618 /* NIP cannot be restored if the memory exception comes from an helper */
4619 gen_update_nip(ctx
, ctx
->nip
- 4);
4620 gen_helper_lscbx(t0
, t0
, t1
, t2
, t3
);
4621 tcg_temp_free_i32(t1
);
4622 tcg_temp_free_i32(t2
);
4623 tcg_temp_free_i32(t3
);
4624 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~0x7F);
4625 tcg_gen_or_tl(cpu_xer
, cpu_xer
, t0
);
4626 if (unlikely(Rc(ctx
->opcode
) != 0))
4627 gen_set_Rc0(ctx
, t0
);
4631 /* maskg - maskg. */
4632 GEN_HANDLER(maskg
, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR
)
4634 int l1
= gen_new_label();
4635 TCGv t0
= tcg_temp_new();
4636 TCGv t1
= tcg_temp_new();
4637 TCGv t2
= tcg_temp_new();
4638 TCGv t3
= tcg_temp_new();
4639 tcg_gen_movi_tl(t3
, 0xFFFFFFFF);
4640 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4641 tcg_gen_andi_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 0x1F);
4642 tcg_gen_addi_tl(t2
, t0
, 1);
4643 tcg_gen_shr_tl(t2
, t3
, t2
);
4644 tcg_gen_shr_tl(t3
, t3
, t1
);
4645 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], t2
, t3
);
4646 tcg_gen_brcond_tl(TCG_COND_GE
, t0
, t1
, l1
);
4647 tcg_gen_neg_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4653 if (unlikely(Rc(ctx
->opcode
) != 0))
4654 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4657 /* maskir - maskir. */
4658 GEN_HANDLER(maskir
, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR
)
4660 TCGv t0
= tcg_temp_new();
4661 TCGv t1
= tcg_temp_new();
4662 tcg_gen_and_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4663 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4664 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4667 if (unlikely(Rc(ctx
->opcode
) != 0))
4668 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4672 GEN_HANDLER(mul
, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR
)
4674 TCGv_i64 t0
= tcg_temp_new_i64();
4675 TCGv_i64 t1
= tcg_temp_new_i64();
4676 TCGv t2
= tcg_temp_new();
4677 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
4678 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
4679 tcg_gen_mul_i64(t0
, t0
, t1
);
4680 tcg_gen_trunc_i64_tl(t2
, t0
);
4681 gen_store_spr(SPR_MQ
, t2
);
4682 tcg_gen_shri_i64(t1
, t0
, 32);
4683 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
4684 tcg_temp_free_i64(t0
);
4685 tcg_temp_free_i64(t1
);
4687 if (unlikely(Rc(ctx
->opcode
) != 0))
4688 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4692 GEN_HANDLER(mulo
, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR
)
4694 int l1
= gen_new_label();
4695 TCGv_i64 t0
= tcg_temp_new_i64();
4696 TCGv_i64 t1
= tcg_temp_new_i64();
4697 TCGv t2
= tcg_temp_new();
4698 /* Start with XER OV disabled, the most likely case */
4699 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
4700 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
4701 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
4702 tcg_gen_mul_i64(t0
, t0
, t1
);
4703 tcg_gen_trunc_i64_tl(t2
, t0
);
4704 gen_store_spr(SPR_MQ
, t2
);
4705 tcg_gen_shri_i64(t1
, t0
, 32);
4706 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
4707 tcg_gen_ext32s_i64(t1
, t0
);
4708 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, t1
, l1
);
4709 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
4711 tcg_temp_free_i64(t0
);
4712 tcg_temp_free_i64(t1
);
4714 if (unlikely(Rc(ctx
->opcode
) != 0))
4715 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4719 GEN_HANDLER(nabs
, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR
)
4721 int l1
= gen_new_label();
4722 int l2
= gen_new_label();
4723 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4724 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4727 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4729 if (unlikely(Rc(ctx
->opcode
) != 0))
4730 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4733 /* nabso - nabso. */
4734 GEN_HANDLER(nabso
, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR
)
4736 int l1
= gen_new_label();
4737 int l2
= gen_new_label();
4738 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4739 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4742 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4744 /* nabs never overflows */
4745 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
4746 if (unlikely(Rc(ctx
->opcode
) != 0))
4747 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4751 GEN_HANDLER(rlmi
, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
)
4753 uint32_t mb
= MB(ctx
->opcode
);
4754 uint32_t me
= ME(ctx
->opcode
);
4755 TCGv t0
= tcg_temp_new();
4756 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4757 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4758 tcg_gen_andi_tl(t0
, t0
, MASK(mb
, me
));
4759 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~MASK(mb
, me
));
4760 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], t0
);
4762 if (unlikely(Rc(ctx
->opcode
) != 0))
4763 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4767 GEN_HANDLER(rrib
, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR
)
4769 TCGv t0
= tcg_temp_new();
4770 TCGv t1
= tcg_temp_new();
4771 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4772 tcg_gen_movi_tl(t1
, 0x80000000);
4773 tcg_gen_shr_tl(t1
, t1
, t0
);
4774 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4775 tcg_gen_and_tl(t0
, t0
, t1
);
4776 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], t1
);
4777 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4780 if (unlikely(Rc(ctx
->opcode
) != 0))
4781 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4785 GEN_HANDLER(sle
, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR
)
4787 TCGv t0
= tcg_temp_new();
4788 TCGv t1
= tcg_temp_new();
4789 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4790 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4791 tcg_gen_subfi_tl(t1
, 32, t1
);
4792 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4793 tcg_gen_or_tl(t1
, t0
, t1
);
4794 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4795 gen_store_spr(SPR_MQ
, t1
);
4798 if (unlikely(Rc(ctx
->opcode
) != 0))
4799 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4803 GEN_HANDLER(sleq
, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR
)
4805 TCGv t0
= tcg_temp_new();
4806 TCGv t1
= tcg_temp_new();
4807 TCGv t2
= tcg_temp_new();
4808 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4809 tcg_gen_movi_tl(t2
, 0xFFFFFFFF);
4810 tcg_gen_shl_tl(t2
, t2
, t0
);
4811 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4812 gen_load_spr(t1
, SPR_MQ
);
4813 gen_store_spr(SPR_MQ
, t0
);
4814 tcg_gen_and_tl(t0
, t0
, t2
);
4815 tcg_gen_andc_tl(t1
, t1
, t2
);
4816 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4820 if (unlikely(Rc(ctx
->opcode
) != 0))
4821 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4825 GEN_HANDLER(sliq
, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR
)
4827 int sh
= SH(ctx
->opcode
);
4828 TCGv t0
= tcg_temp_new();
4829 TCGv t1
= tcg_temp_new();
4830 tcg_gen_shli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
4831 tcg_gen_shri_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
4832 tcg_gen_or_tl(t1
, t0
, t1
);
4833 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4834 gen_store_spr(SPR_MQ
, t1
);
4837 if (unlikely(Rc(ctx
->opcode
) != 0))
4838 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4841 /* slliq - slliq. */
4842 GEN_HANDLER(slliq
, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR
)
4844 int sh
= SH(ctx
->opcode
);
4845 TCGv t0
= tcg_temp_new();
4846 TCGv t1
= tcg_temp_new();
4847 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
4848 gen_load_spr(t1
, SPR_MQ
);
4849 gen_store_spr(SPR_MQ
, t0
);
4850 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
<< sh
));
4851 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
<< sh
));
4852 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4855 if (unlikely(Rc(ctx
->opcode
) != 0))
4856 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4860 GEN_HANDLER(sllq
, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR
)
4862 int l1
= gen_new_label();
4863 int l2
= gen_new_label();
4864 TCGv t0
= tcg_temp_local_new();
4865 TCGv t1
= tcg_temp_local_new();
4866 TCGv t2
= tcg_temp_local_new();
4867 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4868 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
4869 tcg_gen_shl_tl(t1
, t1
, t2
);
4870 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
4871 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
4872 gen_load_spr(t0
, SPR_MQ
);
4873 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4876 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
4877 gen_load_spr(t2
, SPR_MQ
);
4878 tcg_gen_andc_tl(t1
, t2
, t1
);
4879 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4884 if (unlikely(Rc(ctx
->opcode
) != 0))
4885 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4889 GEN_HANDLER(slq
, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR
)
4891 int l1
= gen_new_label();
4892 TCGv t0
= tcg_temp_new();
4893 TCGv t1
= tcg_temp_new();
4894 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4895 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4896 tcg_gen_subfi_tl(t1
, 32, t1
);
4897 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4898 tcg_gen_or_tl(t1
, t0
, t1
);
4899 gen_store_spr(SPR_MQ
, t1
);
4900 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
4901 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4902 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
4903 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
4907 if (unlikely(Rc(ctx
->opcode
) != 0))
4908 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4911 /* sraiq - sraiq. */
4912 GEN_HANDLER(sraiq
, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR
)
4914 int sh
= SH(ctx
->opcode
);
4915 int l1
= gen_new_label();
4916 TCGv t0
= tcg_temp_new();
4917 TCGv t1
= tcg_temp_new();
4918 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
4919 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
4920 tcg_gen_or_tl(t0
, t0
, t1
);
4921 gen_store_spr(SPR_MQ
, t0
);
4922 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
4923 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
4924 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rS(ctx
->opcode
)], 0, l1
);
4925 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_CA
));
4927 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
4930 if (unlikely(Rc(ctx
->opcode
) != 0))
4931 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4935 GEN_HANDLER(sraq
, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR
)
4937 int l1
= gen_new_label();
4938 int l2
= gen_new_label();
4939 TCGv t0
= tcg_temp_new();
4940 TCGv t1
= tcg_temp_local_new();
4941 TCGv t2
= tcg_temp_local_new();
4942 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4943 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
4944 tcg_gen_sar_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
4945 tcg_gen_subfi_tl(t2
, 32, t2
);
4946 tcg_gen_shl_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
4947 tcg_gen_or_tl(t0
, t0
, t2
);
4948 gen_store_spr(SPR_MQ
, t0
);
4949 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
4950 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l1
);
4951 tcg_gen_mov_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)]);
4952 tcg_gen_sari_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 31);
4955 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t1
);
4956 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
4957 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
4958 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l2
);
4959 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_CA
));
4963 if (unlikely(Rc(ctx
->opcode
) != 0))
4964 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4968 GEN_HANDLER(sre
, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR
)
4970 TCGv t0
= tcg_temp_new();
4971 TCGv t1
= tcg_temp_new();
4972 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4973 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4974 tcg_gen_subfi_tl(t1
, 32, t1
);
4975 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4976 tcg_gen_or_tl(t1
, t0
, t1
);
4977 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4978 gen_store_spr(SPR_MQ
, t1
);
4981 if (unlikely(Rc(ctx
->opcode
) != 0))
4982 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4986 GEN_HANDLER(srea
, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR
)
4988 TCGv t0
= tcg_temp_new();
4989 TCGv t1
= tcg_temp_new();
4990 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4991 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4992 gen_store_spr(SPR_MQ
, t0
);
4993 tcg_gen_sar_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], t1
);
4996 if (unlikely(Rc(ctx
->opcode
) != 0))
4997 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5001 GEN_HANDLER(sreq
, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR
)
5003 TCGv t0
= tcg_temp_new();
5004 TCGv t1
= tcg_temp_new();
5005 TCGv t2
= tcg_temp_new();
5006 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5007 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5008 tcg_gen_shr_tl(t1
, t1
, t0
);
5009 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5010 gen_load_spr(t2
, SPR_MQ
);
5011 gen_store_spr(SPR_MQ
, t0
);
5012 tcg_gen_and_tl(t0
, t0
, t1
);
5013 tcg_gen_andc_tl(t2
, t2
, t1
);
5014 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5018 if (unlikely(Rc(ctx
->opcode
) != 0))
5019 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5023 GEN_HANDLER(sriq
, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR
)
5025 int sh
= SH(ctx
->opcode
);
5026 TCGv t0
= tcg_temp_new();
5027 TCGv t1
= tcg_temp_new();
5028 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5029 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5030 tcg_gen_or_tl(t1
, t0
, t1
);
5031 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5032 gen_store_spr(SPR_MQ
, t1
);
5035 if (unlikely(Rc(ctx
->opcode
) != 0))
5036 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5040 GEN_HANDLER(srliq
, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR
)
5042 int sh
= SH(ctx
->opcode
);
5043 TCGv t0
= tcg_temp_new();
5044 TCGv t1
= tcg_temp_new();
5045 tcg_gen_rotri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5046 gen_load_spr(t1
, SPR_MQ
);
5047 gen_store_spr(SPR_MQ
, t0
);
5048 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
>> sh
));
5049 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
>> sh
));
5050 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5053 if (unlikely(Rc(ctx
->opcode
) != 0))
5054 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5058 GEN_HANDLER(srlq
, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR
)
5060 int l1
= gen_new_label();
5061 int l2
= gen_new_label();
5062 TCGv t0
= tcg_temp_local_new();
5063 TCGv t1
= tcg_temp_local_new();
5064 TCGv t2
= tcg_temp_local_new();
5065 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5066 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5067 tcg_gen_shr_tl(t2
, t1
, t2
);
5068 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5069 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5070 gen_load_spr(t0
, SPR_MQ
);
5071 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5074 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5075 tcg_gen_and_tl(t0
, t0
, t2
);
5076 gen_load_spr(t1
, SPR_MQ
);
5077 tcg_gen_andc_tl(t1
, t1
, t2
);
5078 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5083 if (unlikely(Rc(ctx
->opcode
) != 0))
5084 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5088 GEN_HANDLER(srq
, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR
)
5090 int l1
= gen_new_label();
5091 TCGv t0
= tcg_temp_new();
5092 TCGv t1
= tcg_temp_new();
5093 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5094 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5095 tcg_gen_subfi_tl(t1
, 32, t1
);
5096 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5097 tcg_gen_or_tl(t1
, t0
, t1
);
5098 gen_store_spr(SPR_MQ
, t1
);
5099 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5100 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5101 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5102 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5106 if (unlikely(Rc(ctx
->opcode
) != 0))
5107 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5110 /* PowerPC 602 specific instructions */
5112 GEN_HANDLER(dsa
, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC
)
5115 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5119 GEN_HANDLER(esa
, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC
)
5122 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5126 GEN_HANDLER(mfrom
, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC
)
5128 #if defined(CONFIG_USER_ONLY)
5129 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5131 if (unlikely(!ctx
->mem_idx
)) {
5132 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5135 gen_helper_602_mfrom(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5139 /* 602 - 603 - G2 TLB management */
5141 GEN_HANDLER2(tlbld_6xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB
)
5143 #if defined(CONFIG_USER_ONLY)
5144 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5146 if (unlikely(!ctx
->mem_idx
)) {
5147 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5150 gen_helper_6xx_tlbd(cpu_gpr
[rB(ctx
->opcode
)]);
5155 GEN_HANDLER2(tlbli_6xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB
)
5157 #if defined(CONFIG_USER_ONLY)
5158 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5160 if (unlikely(!ctx
->mem_idx
)) {
5161 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5164 gen_helper_6xx_tlbi(cpu_gpr
[rB(ctx
->opcode
)]);
5168 /* 74xx TLB management */
5170 GEN_HANDLER2(tlbld_74xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB
)
5172 #if defined(CONFIG_USER_ONLY)
5173 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5175 if (unlikely(!ctx
->mem_idx
)) {
5176 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5179 gen_helper_74xx_tlbd(cpu_gpr
[rB(ctx
->opcode
)]);
5184 GEN_HANDLER2(tlbli_74xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB
)
5186 #if defined(CONFIG_USER_ONLY)
5187 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5189 if (unlikely(!ctx
->mem_idx
)) {
5190 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5193 gen_helper_74xx_tlbi(cpu_gpr
[rB(ctx
->opcode
)]);
5197 /* POWER instructions not in PowerPC 601 */
5199 GEN_HANDLER(clf
, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER
)
5201 /* Cache line flush: implemented as no-op */
5205 GEN_HANDLER(cli
, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER
)
5207 /* Cache line invalidate: privileged and treated as no-op */
5208 #if defined(CONFIG_USER_ONLY)
5209 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5211 if (unlikely(!ctx
->mem_idx
)) {
5212 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5219 GEN_HANDLER(dclst
, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER
)
5221 /* Data cache line store: treated as no-op */
5224 GEN_HANDLER(mfsri
, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER
)
5226 #if defined(CONFIG_USER_ONLY)
5227 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5229 int ra
= rA(ctx
->opcode
);
5230 int rd
= rD(ctx
->opcode
);
5232 if (unlikely(!ctx
->mem_idx
)) {
5233 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5236 t0
= tcg_temp_new();
5237 gen_addr_reg_index(ctx
, t0
);
5238 tcg_gen_shri_tl(t0
, t0
, 28);
5239 tcg_gen_andi_tl(t0
, t0
, 0xF);
5240 gen_helper_load_sr(cpu_gpr
[rd
], t0
);
5242 if (ra
!= 0 && ra
!= rd
)
5243 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rd
]);
5247 GEN_HANDLER(rac
, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER
)
5249 #if defined(CONFIG_USER_ONLY)
5250 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5253 if (unlikely(!ctx
->mem_idx
)) {
5254 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5257 t0
= tcg_temp_new();
5258 gen_addr_reg_index(ctx
, t0
);
5259 gen_helper_rac(cpu_gpr
[rD(ctx
->opcode
)], t0
);
5264 GEN_HANDLER(rfsvc
, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER
)
5266 #if defined(CONFIG_USER_ONLY)
5267 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5269 if (unlikely(!ctx
->mem_idx
)) {
5270 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5274 gen_sync_exception(ctx
);
5278 /* svc is not implemented for now */
5280 /* POWER2 specific instructions */
5281 /* Quad manipulation (load/store two floats at a time) */
5284 GEN_HANDLER(lfq
, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2
)
5286 int rd
= rD(ctx
->opcode
);
5288 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5289 t0
= tcg_temp_new();
5290 gen_addr_imm_index(ctx
, t0
, 0);
5291 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5292 gen_addr_add(ctx
, t0
, t0
, 8);
5293 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5298 GEN_HANDLER(lfqu
, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2
)
5300 int ra
= rA(ctx
->opcode
);
5301 int rd
= rD(ctx
->opcode
);
5303 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5304 t0
= tcg_temp_new();
5305 t1
= tcg_temp_new();
5306 gen_addr_imm_index(ctx
, t0
, 0);
5307 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5308 gen_addr_add(ctx
, t1
, t0
, 8);
5309 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5311 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5317 GEN_HANDLER(lfqux
, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2
)
5319 int ra
= rA(ctx
->opcode
);
5320 int rd
= rD(ctx
->opcode
);
5321 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5323 t0
= tcg_temp_new();
5324 gen_addr_reg_index(ctx
, t0
);
5325 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5326 t1
= tcg_temp_new();
5327 gen_addr_add(ctx
, t1
, t0
, 8);
5328 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5331 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5336 GEN_HANDLER(lfqx
, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2
)
5338 int rd
= rD(ctx
->opcode
);
5340 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5341 t0
= tcg_temp_new();
5342 gen_addr_reg_index(ctx
, t0
);
5343 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5344 gen_addr_add(ctx
, t0
, t0
, 8);
5345 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5350 GEN_HANDLER(stfq
, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2
)
5352 int rd
= rD(ctx
->opcode
);
5354 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5355 t0
= tcg_temp_new();
5356 gen_addr_imm_index(ctx
, t0
, 0);
5357 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5358 gen_addr_add(ctx
, t0
, t0
, 8);
5359 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5364 GEN_HANDLER(stfqu
, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2
)
5366 int ra
= rA(ctx
->opcode
);
5367 int rd
= rD(ctx
->opcode
);
5369 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5370 t0
= tcg_temp_new();
5371 gen_addr_imm_index(ctx
, t0
, 0);
5372 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5373 t1
= tcg_temp_new();
5374 gen_addr_add(ctx
, t1
, t0
, 8);
5375 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5378 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5383 GEN_HANDLER(stfqux
, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2
)
5385 int ra
= rA(ctx
->opcode
);
5386 int rd
= rD(ctx
->opcode
);
5388 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5389 t0
= tcg_temp_new();
5390 gen_addr_reg_index(ctx
, t0
);
5391 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5392 t1
= tcg_temp_new();
5393 gen_addr_add(ctx
, t1
, t0
, 8);
5394 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5397 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5402 GEN_HANDLER(stfqx
, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2
)
5404 int rd
= rD(ctx
->opcode
);
5406 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5407 t0
= tcg_temp_new();
5408 gen_addr_reg_index(ctx
, t0
);
5409 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5410 gen_addr_add(ctx
, t0
, t0
, 8);
5411 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5415 /* BookE specific instructions */
5416 /* XXX: not implemented on 440 ? */
5417 GEN_HANDLER(mfapidi
, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI
)
5420 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5423 /* XXX: not implemented on 440 ? */
5424 GEN_HANDLER(tlbiva
, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA
)
5426 #if defined(CONFIG_USER_ONLY)
5427 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5430 if (unlikely(!ctx
->mem_idx
)) {
5431 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5434 t0
= tcg_temp_new();
5435 gen_addr_reg_index(ctx
, t0
);
5436 gen_helper_tlbie(cpu_gpr
[rB(ctx
->opcode
)]);
5441 /* All 405 MAC instructions are translated here */
5442 static always_inline
void gen_405_mulladd_insn (DisasContext
*ctx
,
5444 int ra
, int rb
, int rt
, int Rc
)
5448 t0
= tcg_temp_local_new();
5449 t1
= tcg_temp_local_new();
5451 switch (opc3
& 0x0D) {
5453 /* macchw - macchw. - macchwo - macchwo. */
5454 /* macchws - macchws. - macchwso - macchwso. */
5455 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5456 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5457 /* mulchw - mulchw. */
5458 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5459 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5460 tcg_gen_ext16s_tl(t1
, t1
);
5463 /* macchwu - macchwu. - macchwuo - macchwuo. */
5464 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5465 /* mulchwu - mulchwu. */
5466 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5467 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5468 tcg_gen_ext16u_tl(t1
, t1
);
5471 /* machhw - machhw. - machhwo - machhwo. */
5472 /* machhws - machhws. - machhwso - machhwso. */
5473 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5474 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5475 /* mulhhw - mulhhw. */
5476 tcg_gen_sari_tl(t0
, cpu_gpr
[ra
], 16);
5477 tcg_gen_ext16s_tl(t0
, t0
);
5478 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5479 tcg_gen_ext16s_tl(t1
, t1
);
5482 /* machhwu - machhwu. - machhwuo - machhwuo. */
5483 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5484 /* mulhhwu - mulhhwu. */
5485 tcg_gen_shri_tl(t0
, cpu_gpr
[ra
], 16);
5486 tcg_gen_ext16u_tl(t0
, t0
);
5487 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5488 tcg_gen_ext16u_tl(t1
, t1
);
5491 /* maclhw - maclhw. - maclhwo - maclhwo. */
5492 /* maclhws - maclhws. - maclhwso - maclhwso. */
5493 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5494 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5495 /* mullhw - mullhw. */
5496 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5497 tcg_gen_ext16s_tl(t1
, cpu_gpr
[rb
]);
5500 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5501 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5502 /* mullhwu - mullhwu. */
5503 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5504 tcg_gen_ext16u_tl(t1
, cpu_gpr
[rb
]);
5508 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5509 tcg_gen_mul_tl(t1
, t0
, t1
);
5511 /* nmultiply-and-accumulate (0x0E) */
5512 tcg_gen_sub_tl(t0
, cpu_gpr
[rt
], t1
);
5514 /* multiply-and-accumulate (0x0C) */
5515 tcg_gen_add_tl(t0
, cpu_gpr
[rt
], t1
);
5519 /* Check overflow and/or saturate */
5520 int l1
= gen_new_label();
5523 /* Start with XER OV disabled, the most likely case */
5524 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
5528 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t1
);
5529 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
5530 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t0
);
5531 tcg_gen_brcondi_tl(TCG_COND_LT
, t1
, 0, l1
);
5534 tcg_gen_sari_tl(t0
, cpu_gpr
[rt
], 31);
5535 tcg_gen_xori_tl(t0
, t0
, 0x7fffffff);
5539 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
5542 tcg_gen_movi_tl(t0
, UINT32_MAX
);
5546 /* Check overflow */
5547 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
5550 tcg_gen_mov_tl(cpu_gpr
[rt
], t0
);
5553 tcg_gen_mul_tl(cpu_gpr
[rt
], t0
, t1
);
5557 if (unlikely(Rc
) != 0) {
5559 gen_set_Rc0(ctx
, cpu_gpr
[rt
]);
5563 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5564 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
5566 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5567 rD(ctx->opcode), Rc(ctx->opcode)); \
5570 /* macchw - macchw. */
5571 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05);
5572 /* macchwo - macchwo. */
5573 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15);
5574 /* macchws - macchws. */
5575 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07);
5576 /* macchwso - macchwso. */
5577 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17);
5578 /* macchwsu - macchwsu. */
5579 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06);
5580 /* macchwsuo - macchwsuo. */
5581 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16);
5582 /* macchwu - macchwu. */
5583 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04);
5584 /* macchwuo - macchwuo. */
5585 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14);
5586 /* machhw - machhw. */
5587 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01);
5588 /* machhwo - machhwo. */
5589 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11);
5590 /* machhws - machhws. */
5591 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03);
5592 /* machhwso - machhwso. */
5593 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13);
5594 /* machhwsu - machhwsu. */
5595 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02);
5596 /* machhwsuo - machhwsuo. */
5597 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12);
5598 /* machhwu - machhwu. */
5599 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00);
5600 /* machhwuo - machhwuo. */
5601 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10);
5602 /* maclhw - maclhw. */
5603 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D);
5604 /* maclhwo - maclhwo. */
5605 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D);
5606 /* maclhws - maclhws. */
5607 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F);
5608 /* maclhwso - maclhwso. */
5609 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F);
5610 /* maclhwu - maclhwu. */
5611 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C);
5612 /* maclhwuo - maclhwuo. */
5613 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C);
5614 /* maclhwsu - maclhwsu. */
5615 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E);
5616 /* maclhwsuo - maclhwsuo. */
5617 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E);
5618 /* nmacchw - nmacchw. */
5619 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05);
5620 /* nmacchwo - nmacchwo. */
5621 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15);
5622 /* nmacchws - nmacchws. */
5623 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07);
5624 /* nmacchwso - nmacchwso. */
5625 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17);
5626 /* nmachhw - nmachhw. */
5627 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01);
5628 /* nmachhwo - nmachhwo. */
5629 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11);
5630 /* nmachhws - nmachhws. */
5631 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03);
5632 /* nmachhwso - nmachhwso. */
5633 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13);
5634 /* nmaclhw - nmaclhw. */
5635 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D);
5636 /* nmaclhwo - nmaclhwo. */
5637 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D);
5638 /* nmaclhws - nmaclhws. */
5639 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F);
5640 /* nmaclhwso - nmaclhwso. */
5641 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F);
5643 /* mulchw - mulchw. */
5644 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05);
5645 /* mulchwu - mulchwu. */
5646 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04);
5647 /* mulhhw - mulhhw. */
5648 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01);
5649 /* mulhhwu - mulhhwu. */
5650 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00);
5651 /* mullhw - mullhw. */
5652 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D);
5653 /* mullhwu - mullhwu. */
5654 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C);
5657 GEN_HANDLER(mfdcr
, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR
)
5659 #if defined(CONFIG_USER_ONLY)
5660 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5663 if (unlikely(!ctx
->mem_idx
)) {
5664 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5667 /* NIP cannot be restored if the memory exception comes from an helper */
5668 gen_update_nip(ctx
, ctx
->nip
- 4);
5669 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
5670 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], dcrn
);
5671 tcg_temp_free(dcrn
);
5676 GEN_HANDLER(mtdcr
, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR
)
5678 #if defined(CONFIG_USER_ONLY)
5679 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5682 if (unlikely(!ctx
->mem_idx
)) {
5683 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5686 /* NIP cannot be restored if the memory exception comes from an helper */
5687 gen_update_nip(ctx
, ctx
->nip
- 4);
5688 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
5689 gen_helper_store_dcr(dcrn
, cpu_gpr
[rS(ctx
->opcode
)]);
5690 tcg_temp_free(dcrn
);
5695 /* XXX: not implemented on 440 ? */
5696 GEN_HANDLER(mfdcrx
, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX
)
5698 #if defined(CONFIG_USER_ONLY)
5699 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5701 if (unlikely(!ctx
->mem_idx
)) {
5702 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5705 /* NIP cannot be restored if the memory exception comes from an helper */
5706 gen_update_nip(ctx
, ctx
->nip
- 4);
5707 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5708 /* Note: Rc update flag set leads to undefined state of Rc0 */
5713 /* XXX: not implemented on 440 ? */
5714 GEN_HANDLER(mtdcrx
, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX
)
5716 #if defined(CONFIG_USER_ONLY)
5717 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5719 if (unlikely(!ctx
->mem_idx
)) {
5720 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5723 /* NIP cannot be restored if the memory exception comes from an helper */
5724 gen_update_nip(ctx
, ctx
->nip
- 4);
5725 gen_helper_store_dcr(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
5726 /* Note: Rc update flag set leads to undefined state of Rc0 */
5730 /* mfdcrux (PPC 460) : user-mode access to DCR */
5731 GEN_HANDLER(mfdcrux
, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX
)
5733 /* NIP cannot be restored if the memory exception comes from an helper */
5734 gen_update_nip(ctx
, ctx
->nip
- 4);
5735 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5736 /* Note: Rc update flag set leads to undefined state of Rc0 */
5739 /* mtdcrux (PPC 460) : user-mode access to DCR */
5740 GEN_HANDLER(mtdcrux
, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX
)
5742 /* NIP cannot be restored if the memory exception comes from an helper */
5743 gen_update_nip(ctx
, ctx
->nip
- 4);
5744 gen_helper_store_dcr(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
5745 /* Note: Rc update flag set leads to undefined state of Rc0 */
5749 GEN_HANDLER(dccci
, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON
)
5751 #if defined(CONFIG_USER_ONLY)
5752 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5754 if (unlikely(!ctx
->mem_idx
)) {
5755 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5758 /* interpreted as no-op */
5763 GEN_HANDLER(dcread
, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON
)
5765 #if defined(CONFIG_USER_ONLY)
5766 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5769 if (unlikely(!ctx
->mem_idx
)) {
5770 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5773 gen_set_access_type(ctx
, ACCESS_CACHE
);
5774 EA
= tcg_temp_new();
5775 gen_addr_reg_index(ctx
, EA
);
5776 val
= tcg_temp_new();
5777 gen_qemu_ld32u(ctx
, val
, EA
);
5779 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], EA
);
5785 GEN_HANDLER2(icbt_40x
, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT
)
5787 /* interpreted as no-op */
5788 /* XXX: specification say this is treated as a load by the MMU
5789 * but does not generate any exception
5794 GEN_HANDLER(iccci
, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON
)
5796 #if defined(CONFIG_USER_ONLY)
5797 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5799 if (unlikely(!ctx
->mem_idx
)) {
5800 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5803 /* interpreted as no-op */
5808 GEN_HANDLER(icread
, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON
)
5810 #if defined(CONFIG_USER_ONLY)
5811 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5813 if (unlikely(!ctx
->mem_idx
)) {
5814 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5817 /* interpreted as no-op */
5821 /* rfci (mem_idx only) */
5822 GEN_HANDLER2(rfci_40x
, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP
)
5824 #if defined(CONFIG_USER_ONLY)
5825 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5827 if (unlikely(!ctx
->mem_idx
)) {
5828 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5831 /* Restore CPU state */
5832 gen_helper_40x_rfci();
5833 gen_sync_exception(ctx
);
5837 GEN_HANDLER(rfci
, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE
)
5839 #if defined(CONFIG_USER_ONLY)
5840 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5842 if (unlikely(!ctx
->mem_idx
)) {
5843 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5846 /* Restore CPU state */
5848 gen_sync_exception(ctx
);
5852 /* BookE specific */
5853 /* XXX: not implemented on 440 ? */
5854 GEN_HANDLER(rfdi
, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI
)
5856 #if defined(CONFIG_USER_ONLY)
5857 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5859 if (unlikely(!ctx
->mem_idx
)) {
5860 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5863 /* Restore CPU state */
5865 gen_sync_exception(ctx
);
5869 /* XXX: not implemented on 440 ? */
5870 GEN_HANDLER(rfmci
, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI
)
5872 #if defined(CONFIG_USER_ONLY)
5873 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5875 if (unlikely(!ctx
->mem_idx
)) {
5876 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5879 /* Restore CPU state */
5881 gen_sync_exception(ctx
);
5885 /* TLB management - PowerPC 405 implementation */
5887 GEN_HANDLER2(tlbre_40x
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB
)
5889 #if defined(CONFIG_USER_ONLY)
5890 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5892 if (unlikely(!ctx
->mem_idx
)) {
5893 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5896 switch (rB(ctx
->opcode
)) {
5898 gen_helper_4xx_tlbre_hi(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5901 gen_helper_4xx_tlbre_lo(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5904 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5910 /* tlbsx - tlbsx. */
5911 GEN_HANDLER2(tlbsx_40x
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB
)
5913 #if defined(CONFIG_USER_ONLY)
5914 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5917 if (unlikely(!ctx
->mem_idx
)) {
5918 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5921 t0
= tcg_temp_new();
5922 gen_addr_reg_index(ctx
, t0
);
5923 gen_helper_4xx_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], t0
);
5925 if (Rc(ctx
->opcode
)) {
5926 int l1
= gen_new_label();
5927 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_xer
);
5928 tcg_gen_shri_i32(cpu_crf
[0], cpu_crf
[0], XER_SO
);
5929 tcg_gen_andi_i32(cpu_crf
[0], cpu_crf
[0], 1);
5930 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
5931 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
5938 GEN_HANDLER2(tlbwe_40x
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB
)
5940 #if defined(CONFIG_USER_ONLY)
5941 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5943 if (unlikely(!ctx
->mem_idx
)) {
5944 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5947 switch (rB(ctx
->opcode
)) {
5949 gen_helper_4xx_tlbwe_hi(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
5952 gen_helper_4xx_tlbwe_lo(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
5955 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5961 /* TLB management - PowerPC 440 implementation */
5963 GEN_HANDLER2(tlbre_440
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE
)
5965 #if defined(CONFIG_USER_ONLY)
5966 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5968 if (unlikely(!ctx
->mem_idx
)) {
5969 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5972 switch (rB(ctx
->opcode
)) {
5977 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
5978 gen_helper_440_tlbwe(t0
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5979 tcg_temp_free_i32(t0
);
5983 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5989 /* tlbsx - tlbsx. */
5990 GEN_HANDLER2(tlbsx_440
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE
)
5992 #if defined(CONFIG_USER_ONLY)
5993 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5996 if (unlikely(!ctx
->mem_idx
)) {
5997 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6000 t0
= tcg_temp_new();
6001 gen_addr_reg_index(ctx
, t0
);
6002 gen_helper_440_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], t0
);
6004 if (Rc(ctx
->opcode
)) {
6005 int l1
= gen_new_label();
6006 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_xer
);
6007 tcg_gen_shri_i32(cpu_crf
[0], cpu_crf
[0], XER_SO
);
6008 tcg_gen_andi_i32(cpu_crf
[0], cpu_crf
[0], 1);
6009 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
6010 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
6017 GEN_HANDLER2(tlbwe_440
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE
)
6019 #if defined(CONFIG_USER_ONLY)
6020 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6022 if (unlikely(!ctx
->mem_idx
)) {
6023 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6026 switch (rB(ctx
->opcode
)) {
6031 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
6032 gen_helper_440_tlbwe(t0
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
6033 tcg_temp_free_i32(t0
);
6037 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6044 GEN_HANDLER(wrtee
, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE
)
6046 #if defined(CONFIG_USER_ONLY)
6047 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6050 if (unlikely(!ctx
->mem_idx
)) {
6051 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6054 t0
= tcg_temp_new();
6055 tcg_gen_andi_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)], (1 << MSR_EE
));
6056 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6057 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
6059 /* Stop translation to have a chance to raise an exception
6060 * if we just set msr_ee to 1
6062 gen_stop_exception(ctx
);
6067 GEN_HANDLER(wrteei
, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE
)
6069 #if defined(CONFIG_USER_ONLY)
6070 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6072 if (unlikely(!ctx
->mem_idx
)) {
6073 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6076 if (ctx
->opcode
& 0x00010000) {
6077 tcg_gen_ori_tl(cpu_msr
, cpu_msr
, (1 << MSR_EE
));
6078 /* Stop translation to have a chance to raise an exception */
6079 gen_stop_exception(ctx
);
6081 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6086 /* PowerPC 440 specific instructions */
6088 GEN_HANDLER(dlmzb
, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC
)
6090 TCGv_i32 t0
= tcg_const_i32(Rc(ctx
->opcode
));
6091 gen_helper_dlmzb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
6092 cpu_gpr
[rB(ctx
->opcode
)], t0
);
6093 tcg_temp_free_i32(t0
);
6096 /* mbar replaces eieio on 440 */
6097 GEN_HANDLER(mbar
, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE
)
6099 /* interpreted as no-op */
6102 /* msync replaces sync on 440 */
6103 GEN_HANDLER(msync
, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE
)
6105 /* interpreted as no-op */
6109 GEN_HANDLER2(icbt_440
, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE
)
6111 /* interpreted as no-op */
6112 /* XXX: specification say this is treated as a load by the MMU
6113 * but does not generate any exception
6117 /*** Altivec vector extension ***/
6118 /* Altivec registers moves */
6120 static always_inline TCGv_ptr
gen_avr_ptr(int reg
)
6122 TCGv_ptr r
= tcg_temp_new_ptr();
6123 tcg_gen_addi_ptr(r
, cpu_env
, offsetof(CPUPPCState
, avr
[reg
]));
6127 #define GEN_VR_LDX(name, opc2, opc3) \
6128 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6131 if (unlikely(!ctx->altivec_enabled)) { \
6132 gen_exception(ctx, POWERPC_EXCP_VPU); \
6135 gen_set_access_type(ctx, ACCESS_INT); \
6136 EA = tcg_temp_new(); \
6137 gen_addr_reg_index(ctx, EA); \
6138 tcg_gen_andi_tl(EA, EA, ~0xf); \
6139 if (ctx->le_mode) { \
6140 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6141 tcg_gen_addi_tl(EA, EA, 8); \
6142 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6144 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6145 tcg_gen_addi_tl(EA, EA, 8); \
6146 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6148 tcg_temp_free(EA); \
6151 #define GEN_VR_STX(name, opc2, opc3) \
6152 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6155 if (unlikely(!ctx->altivec_enabled)) { \
6156 gen_exception(ctx, POWERPC_EXCP_VPU); \
6159 gen_set_access_type(ctx, ACCESS_INT); \
6160 EA = tcg_temp_new(); \
6161 gen_addr_reg_index(ctx, EA); \
6162 tcg_gen_andi_tl(EA, EA, ~0xf); \
6163 if (ctx->le_mode) { \
6164 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6165 tcg_gen_addi_tl(EA, EA, 8); \
6166 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6168 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6169 tcg_gen_addi_tl(EA, EA, 8); \
6170 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6172 tcg_temp_free(EA); \
6175 #define GEN_VR_LVE(name, opc2, opc3) \
6176 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6180 if (unlikely(!ctx->altivec_enabled)) { \
6181 gen_exception(ctx, POWERPC_EXCP_VPU); \
6184 gen_set_access_type(ctx, ACCESS_INT); \
6185 EA = tcg_temp_new(); \
6186 gen_addr_reg_index(ctx, EA); \
6187 rs = gen_avr_ptr(rS(ctx->opcode)); \
6188 gen_helper_lve##name (rs, EA); \
6189 tcg_temp_free(EA); \
6190 tcg_temp_free_ptr(rs); \
6193 #define GEN_VR_STVE(name, opc2, opc3) \
6194 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6198 if (unlikely(!ctx->altivec_enabled)) { \
6199 gen_exception(ctx, POWERPC_EXCP_VPU); \
6202 gen_set_access_type(ctx, ACCESS_INT); \
6203 EA = tcg_temp_new(); \
6204 gen_addr_reg_index(ctx, EA); \
6205 rs = gen_avr_ptr(rS(ctx->opcode)); \
6206 gen_helper_stve##name (rs, EA); \
6207 tcg_temp_free(EA); \
6208 tcg_temp_free_ptr(rs); \
6211 GEN_VR_LDX(lvx
, 0x07, 0x03);
6212 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6213 GEN_VR_LDX(lvxl
, 0x07, 0x0B);
6215 GEN_VR_LVE(bx
, 0x07, 0x00);
6216 GEN_VR_LVE(hx
, 0x07, 0x01);
6217 GEN_VR_LVE(wx
, 0x07, 0x02);
6219 GEN_VR_STX(svx
, 0x07, 0x07);
6220 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6221 GEN_VR_STX(svxl
, 0x07, 0x0F);
6223 GEN_VR_STVE(bx
, 0x07, 0x04);
6224 GEN_VR_STVE(hx
, 0x07, 0x05);
6225 GEN_VR_STVE(wx
, 0x07, 0x06);
6227 GEN_HANDLER(lvsl
, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC
)
6231 if (unlikely(!ctx
->altivec_enabled
)) {
6232 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6235 EA
= tcg_temp_new();
6236 gen_addr_reg_index(ctx
, EA
);
6237 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6238 gen_helper_lvsl(rd
, EA
);
6240 tcg_temp_free_ptr(rd
);
6243 GEN_HANDLER(lvsr
, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC
)
6247 if (unlikely(!ctx
->altivec_enabled
)) {
6248 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6251 EA
= tcg_temp_new();
6252 gen_addr_reg_index(ctx
, EA
);
6253 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6254 gen_helper_lvsr(rd
, EA
);
6256 tcg_temp_free_ptr(rd
);
6259 GEN_HANDLER(mfvscr
, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC
)
6262 if (unlikely(!ctx
->altivec_enabled
)) {
6263 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6266 tcg_gen_movi_i64(cpu_avrh
[rD(ctx
->opcode
)], 0);
6267 t
= tcg_temp_new_i32();
6268 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUState
, vscr
));
6269 tcg_gen_extu_i32_i64(cpu_avrl
[rD(ctx
->opcode
)], t
);
6270 tcg_temp_free_i32(t
);
6273 GEN_HANDLER(mtvscr
, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC
)
6276 if (unlikely(!ctx
->altivec_enabled
)) {
6277 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6280 p
= gen_avr_ptr(rD(ctx
->opcode
));
6281 gen_helper_mtvscr(p
);
6282 tcg_temp_free_ptr(p
);
6285 /* Logical operations */
6286 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6287 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6289 if (unlikely(!ctx->altivec_enabled)) { \
6290 gen_exception(ctx, POWERPC_EXCP_VPU); \
6293 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6294 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6297 GEN_VX_LOGICAL(vand
, tcg_gen_and_i64
, 2, 16);
6298 GEN_VX_LOGICAL(vandc
, tcg_gen_andc_i64
, 2, 17);
6299 GEN_VX_LOGICAL(vor
, tcg_gen_or_i64
, 2, 18);
6300 GEN_VX_LOGICAL(vxor
, tcg_gen_xor_i64
, 2, 19);
6301 GEN_VX_LOGICAL(vnor
, tcg_gen_nor_i64
, 2, 20);
6303 #define GEN_VXFORM(name, opc2, opc3) \
6304 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6306 TCGv_ptr ra, rb, rd; \
6307 if (unlikely(!ctx->altivec_enabled)) { \
6308 gen_exception(ctx, POWERPC_EXCP_VPU); \
6311 ra = gen_avr_ptr(rA(ctx->opcode)); \
6312 rb = gen_avr_ptr(rB(ctx->opcode)); \
6313 rd = gen_avr_ptr(rD(ctx->opcode)); \
6314 gen_helper_##name (rd, ra, rb); \
6315 tcg_temp_free_ptr(ra); \
6316 tcg_temp_free_ptr(rb); \
6317 tcg_temp_free_ptr(rd); \
6320 GEN_VXFORM(vaddubm
, 0, 0);
6321 GEN_VXFORM(vadduhm
, 0, 1);
6322 GEN_VXFORM(vadduwm
, 0, 2);
6323 GEN_VXFORM(vsububm
, 0, 16);
6324 GEN_VXFORM(vsubuhm
, 0, 17);
6325 GEN_VXFORM(vsubuwm
, 0, 18);
6326 GEN_VXFORM(vmaxub
, 1, 0);
6327 GEN_VXFORM(vmaxuh
, 1, 1);
6328 GEN_VXFORM(vmaxuw
, 1, 2);
6329 GEN_VXFORM(vmaxsb
, 1, 4);
6330 GEN_VXFORM(vmaxsh
, 1, 5);
6331 GEN_VXFORM(vmaxsw
, 1, 6);
6332 GEN_VXFORM(vminub
, 1, 8);
6333 GEN_VXFORM(vminuh
, 1, 9);
6334 GEN_VXFORM(vminuw
, 1, 10);
6335 GEN_VXFORM(vminsb
, 1, 12);
6336 GEN_VXFORM(vminsh
, 1, 13);
6337 GEN_VXFORM(vminsw
, 1, 14);
6338 GEN_VXFORM(vavgub
, 1, 16);
6339 GEN_VXFORM(vavguh
, 1, 17);
6340 GEN_VXFORM(vavguw
, 1, 18);
6341 GEN_VXFORM(vavgsb
, 1, 20);
6342 GEN_VXFORM(vavgsh
, 1, 21);
6343 GEN_VXFORM(vavgsw
, 1, 22);
6344 GEN_VXFORM(vmrghb
, 6, 0);
6345 GEN_VXFORM(vmrghh
, 6, 1);
6346 GEN_VXFORM(vmrghw
, 6, 2);
6347 GEN_VXFORM(vmrglb
, 6, 4);
6348 GEN_VXFORM(vmrglh
, 6, 5);
6349 GEN_VXFORM(vmrglw
, 6, 6);
6350 GEN_VXFORM(vmuloub
, 4, 0);
6351 GEN_VXFORM(vmulouh
, 4, 1);
6352 GEN_VXFORM(vmulosb
, 4, 4);
6353 GEN_VXFORM(vmulosh
, 4, 5);
6354 GEN_VXFORM(vmuleub
, 4, 8);
6355 GEN_VXFORM(vmuleuh
, 4, 9);
6356 GEN_VXFORM(vmulesb
, 4, 12);
6357 GEN_VXFORM(vmulesh
, 4, 13);
6358 GEN_VXFORM(vslb
, 2, 4);
6359 GEN_VXFORM(vslh
, 2, 5);
6360 GEN_VXFORM(vslw
, 2, 6);
6361 GEN_VXFORM(vsrb
, 2, 8);
6362 GEN_VXFORM(vsrh
, 2, 9);
6363 GEN_VXFORM(vsrw
, 2, 10);
6364 GEN_VXFORM(vsrab
, 2, 12);
6365 GEN_VXFORM(vsrah
, 2, 13);
6366 GEN_VXFORM(vsraw
, 2, 14);
6367 GEN_VXFORM(vslo
, 6, 16);
6368 GEN_VXFORM(vsro
, 6, 17);
6369 GEN_VXFORM(vaddcuw
, 0, 6);
6370 GEN_VXFORM(vsubcuw
, 0, 22);
6371 GEN_VXFORM(vaddubs
, 0, 8);
6372 GEN_VXFORM(vadduhs
, 0, 9);
6373 GEN_VXFORM(vadduws
, 0, 10);
6374 GEN_VXFORM(vaddsbs
, 0, 12);
6375 GEN_VXFORM(vaddshs
, 0, 13);
6376 GEN_VXFORM(vaddsws
, 0, 14);
6377 GEN_VXFORM(vsububs
, 0, 24);
6378 GEN_VXFORM(vsubuhs
, 0, 25);
6379 GEN_VXFORM(vsubuws
, 0, 26);
6380 GEN_VXFORM(vsubsbs
, 0, 28);
6381 GEN_VXFORM(vsubshs
, 0, 29);
6382 GEN_VXFORM(vsubsws
, 0, 30);
6383 GEN_VXFORM(vrlb
, 2, 0);
6384 GEN_VXFORM(vrlh
, 2, 1);
6385 GEN_VXFORM(vrlw
, 2, 2);
6386 GEN_VXFORM(vsl
, 2, 7);
6387 GEN_VXFORM(vsr
, 2, 11);
6388 GEN_VXFORM(vpkuhum
, 7, 0);
6389 GEN_VXFORM(vpkuwum
, 7, 1);
6390 GEN_VXFORM(vpkuhus
, 7, 2);
6391 GEN_VXFORM(vpkuwus
, 7, 3);
6392 GEN_VXFORM(vpkshus
, 7, 4);
6393 GEN_VXFORM(vpkswus
, 7, 5);
6394 GEN_VXFORM(vpkshss
, 7, 6);
6395 GEN_VXFORM(vpkswss
, 7, 7);
6396 GEN_VXFORM(vpkpx
, 7, 12);
6397 GEN_VXFORM(vsum4ubs
, 4, 24);
6398 GEN_VXFORM(vsum4sbs
, 4, 28);
6399 GEN_VXFORM(vsum4shs
, 4, 25);
6400 GEN_VXFORM(vsum2sws
, 4, 26);
6401 GEN_VXFORM(vsumsws
, 4, 30);
6402 GEN_VXFORM(vaddfp
, 5, 0);
6403 GEN_VXFORM(vsubfp
, 5, 1);
6404 GEN_VXFORM(vmaxfp
, 5, 16);
6405 GEN_VXFORM(vminfp
, 5, 17);
6407 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6408 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6410 TCGv_ptr ra, rb, rd; \
6411 if (unlikely(!ctx->altivec_enabled)) { \
6412 gen_exception(ctx, POWERPC_EXCP_VPU); \
6415 ra = gen_avr_ptr(rA(ctx->opcode)); \
6416 rb = gen_avr_ptr(rB(ctx->opcode)); \
6417 rd = gen_avr_ptr(rD(ctx->opcode)); \
6418 gen_helper_##opname (rd, ra, rb); \
6419 tcg_temp_free_ptr(ra); \
6420 tcg_temp_free_ptr(rb); \
6421 tcg_temp_free_ptr(rd); \
6424 #define GEN_VXRFORM(name, opc2, opc3) \
6425 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6426 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6428 GEN_VXRFORM(vcmpequb
, 3, 0)
6429 GEN_VXRFORM(vcmpequh
, 3, 1)
6430 GEN_VXRFORM(vcmpequw
, 3, 2)
6431 GEN_VXRFORM(vcmpgtsb
, 3, 12)
6432 GEN_VXRFORM(vcmpgtsh
, 3, 13)
6433 GEN_VXRFORM(vcmpgtsw
, 3, 14)
6434 GEN_VXRFORM(vcmpgtub
, 3, 8)
6435 GEN_VXRFORM(vcmpgtuh
, 3, 9)
6436 GEN_VXRFORM(vcmpgtuw
, 3, 10)
6437 GEN_VXRFORM(vcmpeqfp
, 3, 3)
6438 GEN_VXRFORM(vcmpgefp
, 3, 7)
6439 GEN_VXRFORM(vcmpgtfp
, 3, 11)
6440 GEN_VXRFORM(vcmpbfp
, 3, 15)
6442 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6443 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6447 if (unlikely(!ctx->altivec_enabled)) { \
6448 gen_exception(ctx, POWERPC_EXCP_VPU); \
6451 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6452 rd = gen_avr_ptr(rD(ctx->opcode)); \
6453 gen_helper_##name (rd, simm); \
6454 tcg_temp_free_i32(simm); \
6455 tcg_temp_free_ptr(rd); \
6458 GEN_VXFORM_SIMM(vspltisb
, 6, 12);
6459 GEN_VXFORM_SIMM(vspltish
, 6, 13);
6460 GEN_VXFORM_SIMM(vspltisw
, 6, 14);
6462 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6463 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) \
6466 if (unlikely(!ctx->altivec_enabled)) { \
6467 gen_exception(ctx, POWERPC_EXCP_VPU); \
6470 rb = gen_avr_ptr(rB(ctx->opcode)); \
6471 rd = gen_avr_ptr(rD(ctx->opcode)); \
6472 gen_helper_##name (rd, rb); \
6473 tcg_temp_free_ptr(rb); \
6474 tcg_temp_free_ptr(rd); \
6477 GEN_VXFORM_NOA(vupkhsb
, 7, 8);
6478 GEN_VXFORM_NOA(vupkhsh
, 7, 9);
6479 GEN_VXFORM_NOA(vupklsb
, 7, 10);
6480 GEN_VXFORM_NOA(vupklsh
, 7, 11);
6481 GEN_VXFORM_NOA(vupkhpx
, 7, 13);
6482 GEN_VXFORM_NOA(vupklpx
, 7, 15);
6483 GEN_VXFORM_NOA(vrefp
, 5, 4);
6484 GEN_VXFORM_NOA(vrsqrtefp
, 5, 5);
6485 GEN_VXFORM_NOA(vlogefp
, 5, 7);
6486 GEN_VXFORM_NOA(vrfim
, 5, 8);
6487 GEN_VXFORM_NOA(vrfin
, 5, 9);
6488 GEN_VXFORM_NOA(vrfip
, 5, 10);
6489 GEN_VXFORM_NOA(vrfiz
, 5, 11);
6491 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6492 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6496 if (unlikely(!ctx->altivec_enabled)) { \
6497 gen_exception(ctx, POWERPC_EXCP_VPU); \
6500 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6501 rd = gen_avr_ptr(rD(ctx->opcode)); \
6502 gen_helper_##name (rd, simm); \
6503 tcg_temp_free_i32(simm); \
6504 tcg_temp_free_ptr(rd); \
6507 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6508 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6512 if (unlikely(!ctx->altivec_enabled)) { \
6513 gen_exception(ctx, POWERPC_EXCP_VPU); \
6516 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6517 rb = gen_avr_ptr(rB(ctx->opcode)); \
6518 rd = gen_avr_ptr(rD(ctx->opcode)); \
6519 gen_helper_##name (rd, rb, uimm); \
6520 tcg_temp_free_i32(uimm); \
6521 tcg_temp_free_ptr(rb); \
6522 tcg_temp_free_ptr(rd); \
6525 GEN_VXFORM_UIMM(vspltb
, 6, 8);
6526 GEN_VXFORM_UIMM(vsplth
, 6, 9);
6527 GEN_VXFORM_UIMM(vspltw
, 6, 10);
6528 GEN_VXFORM_UIMM(vcfux
, 5, 12);
6529 GEN_VXFORM_UIMM(vcfsx
, 5, 13);
6530 GEN_VXFORM_UIMM(vctuxs
, 5, 14);
6531 GEN_VXFORM_UIMM(vctsxs
, 5, 15);
6533 GEN_HANDLER(vsldoi
, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC
)
6535 TCGv_ptr ra
, rb
, rd
;
6537 if (unlikely(!ctx
->altivec_enabled
)) {
6538 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6541 ra
= gen_avr_ptr(rA(ctx
->opcode
));
6542 rb
= gen_avr_ptr(rB(ctx
->opcode
));
6543 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6544 sh
= tcg_const_i32(VSH(ctx
->opcode
));
6545 gen_helper_vsldoi (rd
, ra
, rb
, sh
);
6546 tcg_temp_free_ptr(ra
);
6547 tcg_temp_free_ptr(rb
);
6548 tcg_temp_free_ptr(rd
);
6549 tcg_temp_free_i32(sh
);
6552 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6553 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) \
6555 TCGv_ptr ra, rb, rc, rd; \
6556 if (unlikely(!ctx->altivec_enabled)) { \
6557 gen_exception(ctx, POWERPC_EXCP_VPU); \
6560 ra = gen_avr_ptr(rA(ctx->opcode)); \
6561 rb = gen_avr_ptr(rB(ctx->opcode)); \
6562 rc = gen_avr_ptr(rC(ctx->opcode)); \
6563 rd = gen_avr_ptr(rD(ctx->opcode)); \
6564 if (Rc(ctx->opcode)) { \
6565 gen_helper_##name1 (rd, ra, rb, rc); \
6567 gen_helper_##name0 (rd, ra, rb, rc); \
6569 tcg_temp_free_ptr(ra); \
6570 tcg_temp_free_ptr(rb); \
6571 tcg_temp_free_ptr(rc); \
6572 tcg_temp_free_ptr(rd); \
6575 GEN_VAFORM_PAIRED(vmhaddshs
, vmhraddshs
, 16)
6577 GEN_HANDLER(vmladduhm
, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC
)
6579 TCGv_ptr ra
, rb
, rc
, rd
;
6580 if (unlikely(!ctx
->altivec_enabled
)) {
6581 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6584 ra
= gen_avr_ptr(rA(ctx
->opcode
));
6585 rb
= gen_avr_ptr(rB(ctx
->opcode
));
6586 rc
= gen_avr_ptr(rC(ctx
->opcode
));
6587 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6588 gen_helper_vmladduhm(rd
, ra
, rb
, rc
);
6589 tcg_temp_free_ptr(ra
);
6590 tcg_temp_free_ptr(rb
);
6591 tcg_temp_free_ptr(rc
);
6592 tcg_temp_free_ptr(rd
);
6595 GEN_VAFORM_PAIRED(vmsumubm
, vmsummbm
, 18)
6596 GEN_VAFORM_PAIRED(vmsumuhm
, vmsumuhs
, 19)
6597 GEN_VAFORM_PAIRED(vmsumshm
, vmsumshs
, 20)
6598 GEN_VAFORM_PAIRED(vsel
, vperm
, 21)
6599 GEN_VAFORM_PAIRED(vmaddfp
, vnmsubfp
, 23)
6601 /*** SPE extension ***/
6602 /* Register moves */
6604 static always_inline
void gen_load_gpr64(TCGv_i64 t
, int reg
) {
6605 #if defined(TARGET_PPC64)
6606 tcg_gen_mov_i64(t
, cpu_gpr
[reg
]);
6608 tcg_gen_concat_i32_i64(t
, cpu_gpr
[reg
], cpu_gprh
[reg
]);
6612 static always_inline
void gen_store_gpr64(int reg
, TCGv_i64 t
) {
6613 #if defined(TARGET_PPC64)
6614 tcg_gen_mov_i64(cpu_gpr
[reg
], t
);
6616 TCGv_i64 tmp
= tcg_temp_new_i64();
6617 tcg_gen_trunc_i64_i32(cpu_gpr
[reg
], t
);
6618 tcg_gen_shri_i64(tmp
, t
, 32);
6619 tcg_gen_trunc_i64_i32(cpu_gprh
[reg
], tmp
);
6620 tcg_temp_free_i64(tmp
);
6624 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
6625 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
6627 if (Rc(ctx->opcode)) \
6633 /* Handler for undefined SPE opcodes */
6634 static always_inline
void gen_speundef (DisasContext
*ctx
)
6636 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6640 #if defined(TARGET_PPC64)
6641 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6642 static always_inline void gen_##name (DisasContext *ctx) \
6644 if (unlikely(!ctx->spe_enabled)) { \
6645 gen_exception(ctx, POWERPC_EXCP_APU); \
6648 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6649 cpu_gpr[rB(ctx->opcode)]); \
6652 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6653 static always_inline void gen_##name (DisasContext *ctx) \
6655 if (unlikely(!ctx->spe_enabled)) { \
6656 gen_exception(ctx, POWERPC_EXCP_APU); \
6659 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6660 cpu_gpr[rB(ctx->opcode)]); \
6661 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6662 cpu_gprh[rB(ctx->opcode)]); \
6666 GEN_SPEOP_LOGIC2(evand
, tcg_gen_and_tl
);
6667 GEN_SPEOP_LOGIC2(evandc
, tcg_gen_andc_tl
);
6668 GEN_SPEOP_LOGIC2(evxor
, tcg_gen_xor_tl
);
6669 GEN_SPEOP_LOGIC2(evor
, tcg_gen_or_tl
);
6670 GEN_SPEOP_LOGIC2(evnor
, tcg_gen_nor_tl
);
6671 GEN_SPEOP_LOGIC2(eveqv
, tcg_gen_eqv_tl
);
6672 GEN_SPEOP_LOGIC2(evorc
, tcg_gen_orc_tl
);
6673 GEN_SPEOP_LOGIC2(evnand
, tcg_gen_nand_tl
);
6675 /* SPE logic immediate */
6676 #if defined(TARGET_PPC64)
6677 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6678 static always_inline void gen_##name (DisasContext *ctx) \
6680 if (unlikely(!ctx->spe_enabled)) { \
6681 gen_exception(ctx, POWERPC_EXCP_APU); \
6684 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6685 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6686 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6687 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6688 tcg_opi(t0, t0, rB(ctx->opcode)); \
6689 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6690 tcg_gen_trunc_i64_i32(t1, t2); \
6691 tcg_temp_free_i64(t2); \
6692 tcg_opi(t1, t1, rB(ctx->opcode)); \
6693 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6694 tcg_temp_free_i32(t0); \
6695 tcg_temp_free_i32(t1); \
6698 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6699 static always_inline void gen_##name (DisasContext *ctx) \
6701 if (unlikely(!ctx->spe_enabled)) { \
6702 gen_exception(ctx, POWERPC_EXCP_APU); \
6705 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6707 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6711 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi
, tcg_gen_shli_i32
);
6712 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu
, tcg_gen_shri_i32
);
6713 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis
, tcg_gen_sari_i32
);
6714 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi
, tcg_gen_rotli_i32
);
6716 /* SPE arithmetic */
6717 #if defined(TARGET_PPC64)
6718 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6719 static always_inline void gen_##name (DisasContext *ctx) \
6721 if (unlikely(!ctx->spe_enabled)) { \
6722 gen_exception(ctx, POWERPC_EXCP_APU); \
6725 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6726 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6727 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6728 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6730 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6731 tcg_gen_trunc_i64_i32(t1, t2); \
6732 tcg_temp_free_i64(t2); \
6734 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6735 tcg_temp_free_i32(t0); \
6736 tcg_temp_free_i32(t1); \
6739 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6740 static always_inline void gen_##name (DisasContext *ctx) \
6742 if (unlikely(!ctx->spe_enabled)) { \
6743 gen_exception(ctx, POWERPC_EXCP_APU); \
6746 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6747 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6751 static always_inline
void gen_op_evabs (TCGv_i32 ret
, TCGv_i32 arg1
)
6753 int l1
= gen_new_label();
6754 int l2
= gen_new_label();
6756 tcg_gen_brcondi_i32(TCG_COND_GE
, arg1
, 0, l1
);
6757 tcg_gen_neg_i32(ret
, arg1
);
6760 tcg_gen_mov_i32(ret
, arg1
);
6763 GEN_SPEOP_ARITH1(evabs
, gen_op_evabs
);
6764 GEN_SPEOP_ARITH1(evneg
, tcg_gen_neg_i32
);
6765 GEN_SPEOP_ARITH1(evextsb
, tcg_gen_ext8s_i32
);
6766 GEN_SPEOP_ARITH1(evextsh
, tcg_gen_ext16s_i32
);
6767 static always_inline
void gen_op_evrndw (TCGv_i32 ret
, TCGv_i32 arg1
)
6769 tcg_gen_addi_i32(ret
, arg1
, 0x8000);
6770 tcg_gen_ext16u_i32(ret
, ret
);
6772 GEN_SPEOP_ARITH1(evrndw
, gen_op_evrndw
);
6773 GEN_SPEOP_ARITH1(evcntlsw
, gen_helper_cntlsw32
);
6774 GEN_SPEOP_ARITH1(evcntlzw
, gen_helper_cntlzw32
);
6776 #if defined(TARGET_PPC64)
6777 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6778 static always_inline void gen_##name (DisasContext *ctx) \
6780 if (unlikely(!ctx->spe_enabled)) { \
6781 gen_exception(ctx, POWERPC_EXCP_APU); \
6784 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6785 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6786 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6787 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
6788 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6789 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6790 tcg_op(t0, t0, t2); \
6791 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6792 tcg_gen_trunc_i64_i32(t1, t3); \
6793 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6794 tcg_gen_trunc_i64_i32(t2, t3); \
6795 tcg_temp_free_i64(t3); \
6796 tcg_op(t1, t1, t2); \
6797 tcg_temp_free_i32(t2); \
6798 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6799 tcg_temp_free_i32(t0); \
6800 tcg_temp_free_i32(t1); \
6803 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6804 static always_inline void gen_##name (DisasContext *ctx) \
6806 if (unlikely(!ctx->spe_enabled)) { \
6807 gen_exception(ctx, POWERPC_EXCP_APU); \
6810 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6811 cpu_gpr[rB(ctx->opcode)]); \
6812 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6813 cpu_gprh[rB(ctx->opcode)]); \
6817 static always_inline
void gen_op_evsrwu (TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
6822 l1
= gen_new_label();
6823 l2
= gen_new_label();
6824 t0
= tcg_temp_local_new_i32();
6825 /* No error here: 6 bits are used */
6826 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
6827 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
6828 tcg_gen_shr_i32(ret
, arg1
, t0
);
6831 tcg_gen_movi_i32(ret
, 0);
6833 tcg_temp_free_i32(t0
);
6835 GEN_SPEOP_ARITH2(evsrwu
, gen_op_evsrwu
);
6836 static always_inline
void gen_op_evsrws (TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
6841 l1
= gen_new_label();
6842 l2
= gen_new_label();
6843 t0
= tcg_temp_local_new_i32();
6844 /* No error here: 6 bits are used */
6845 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
6846 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
6847 tcg_gen_sar_i32(ret
, arg1
, t0
);
6850 tcg_gen_movi_i32(ret
, 0);
6852 tcg_temp_free_i32(t0
);
6854 GEN_SPEOP_ARITH2(evsrws
, gen_op_evsrws
);
6855 static always_inline
void gen_op_evslw (TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
6860 l1
= gen_new_label();
6861 l2
= gen_new_label();
6862 t0
= tcg_temp_local_new_i32();
6863 /* No error here: 6 bits are used */
6864 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
6865 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
6866 tcg_gen_shl_i32(ret
, arg1
, t0
);
6869 tcg_gen_movi_i32(ret
, 0);
6871 tcg_temp_free_i32(t0
);
6873 GEN_SPEOP_ARITH2(evslw
, gen_op_evslw
);
6874 static always_inline
void gen_op_evrlw (TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
6876 TCGv_i32 t0
= tcg_temp_new_i32();
6877 tcg_gen_andi_i32(t0
, arg2
, 0x1F);
6878 tcg_gen_rotl_i32(ret
, arg1
, t0
);
6879 tcg_temp_free_i32(t0
);
6881 GEN_SPEOP_ARITH2(evrlw
, gen_op_evrlw
);
6882 static always_inline
void gen_evmergehi (DisasContext
*ctx
)
6884 if (unlikely(!ctx
->spe_enabled
)) {
6885 gen_exception(ctx
, POWERPC_EXCP_APU
);
6888 #if defined(TARGET_PPC64)
6889 TCGv t0
= tcg_temp_new();
6890 TCGv t1
= tcg_temp_new();
6891 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 32);
6892 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 0xFFFFFFFF0000000ULL
);
6893 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
6897 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
6898 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
6901 GEN_SPEOP_ARITH2(evaddw
, tcg_gen_add_i32
);
6902 static always_inline
void gen_op_evsubf (TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
6904 tcg_gen_sub_i32(ret
, arg2
, arg1
);
6906 GEN_SPEOP_ARITH2(evsubfw
, gen_op_evsubf
);
6908 /* SPE arithmetic immediate */
6909 #if defined(TARGET_PPC64)
6910 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6911 static always_inline void gen_##name (DisasContext *ctx) \
6913 if (unlikely(!ctx->spe_enabled)) { \
6914 gen_exception(ctx, POWERPC_EXCP_APU); \
6917 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6918 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6919 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6920 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6921 tcg_op(t0, t0, rA(ctx->opcode)); \
6922 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6923 tcg_gen_trunc_i64_i32(t1, t2); \
6924 tcg_temp_free_i64(t2); \
6925 tcg_op(t1, t1, rA(ctx->opcode)); \
6926 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6927 tcg_temp_free_i32(t0); \
6928 tcg_temp_free_i32(t1); \
6931 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6932 static always_inline void gen_##name (DisasContext *ctx) \
6934 if (unlikely(!ctx->spe_enabled)) { \
6935 gen_exception(ctx, POWERPC_EXCP_APU); \
6938 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6940 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6944 GEN_SPEOP_ARITH_IMM2(evaddiw
, tcg_gen_addi_i32
);
6945 GEN_SPEOP_ARITH_IMM2(evsubifw
, tcg_gen_subi_i32
);
6947 /* SPE comparison */
6948 #if defined(TARGET_PPC64)
6949 #define GEN_SPEOP_COMP(name, tcg_cond) \
6950 static always_inline void gen_##name (DisasContext *ctx) \
6952 if (unlikely(!ctx->spe_enabled)) { \
6953 gen_exception(ctx, POWERPC_EXCP_APU); \
6956 int l1 = gen_new_label(); \
6957 int l2 = gen_new_label(); \
6958 int l3 = gen_new_label(); \
6959 int l4 = gen_new_label(); \
6960 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6961 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6962 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6963 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6964 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6965 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
6966 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
6968 gen_set_label(l1); \
6969 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6970 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6971 gen_set_label(l2); \
6972 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6973 tcg_gen_trunc_i64_i32(t0, t2); \
6974 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6975 tcg_gen_trunc_i64_i32(t1, t2); \
6976 tcg_temp_free_i64(t2); \
6977 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
6978 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6979 ~(CRF_CH | CRF_CH_AND_CL)); \
6981 gen_set_label(l3); \
6982 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6983 CRF_CH | CRF_CH_OR_CL); \
6984 gen_set_label(l4); \
6985 tcg_temp_free_i32(t0); \
6986 tcg_temp_free_i32(t1); \
6989 #define GEN_SPEOP_COMP(name, tcg_cond) \
6990 static always_inline void gen_##name (DisasContext *ctx) \
6992 if (unlikely(!ctx->spe_enabled)) { \
6993 gen_exception(ctx, POWERPC_EXCP_APU); \
6996 int l1 = gen_new_label(); \
6997 int l2 = gen_new_label(); \
6998 int l3 = gen_new_label(); \
6999 int l4 = gen_new_label(); \
7001 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7002 cpu_gpr[rB(ctx->opcode)], l1); \
7003 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7005 gen_set_label(l1); \
7006 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7007 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7008 gen_set_label(l2); \
7009 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7010 cpu_gprh[rB(ctx->opcode)], l3); \
7011 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7012 ~(CRF_CH | CRF_CH_AND_CL)); \
7014 gen_set_label(l3); \
7015 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7016 CRF_CH | CRF_CH_OR_CL); \
7017 gen_set_label(l4); \
7020 GEN_SPEOP_COMP(evcmpgtu
, TCG_COND_GTU
);
7021 GEN_SPEOP_COMP(evcmpgts
, TCG_COND_GT
);
7022 GEN_SPEOP_COMP(evcmpltu
, TCG_COND_LTU
);
7023 GEN_SPEOP_COMP(evcmplts
, TCG_COND_LT
);
7024 GEN_SPEOP_COMP(evcmpeq
, TCG_COND_EQ
);
7027 static always_inline
void gen_brinc (DisasContext
*ctx
)
7029 /* Note: brinc is usable even if SPE is disabled */
7030 gen_helper_brinc(cpu_gpr
[rD(ctx
->opcode
)],
7031 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
7033 static always_inline
void gen_evmergelo (DisasContext
*ctx
)
7035 if (unlikely(!ctx
->spe_enabled
)) {
7036 gen_exception(ctx
, POWERPC_EXCP_APU
);
7039 #if defined(TARGET_PPC64)
7040 TCGv t0
= tcg_temp_new();
7041 TCGv t1
= tcg_temp_new();
7042 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x00000000FFFFFFFFLL
);
7043 tcg_gen_shli_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 32);
7044 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
7048 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
7049 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
7052 static always_inline
void gen_evmergehilo (DisasContext
*ctx
)
7054 if (unlikely(!ctx
->spe_enabled
)) {
7055 gen_exception(ctx
, POWERPC_EXCP_APU
);
7058 #if defined(TARGET_PPC64)
7059 TCGv t0
= tcg_temp_new();
7060 TCGv t1
= tcg_temp_new();
7061 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x00000000FFFFFFFFLL
);
7062 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 0xFFFFFFFF0000000ULL
);
7063 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
7067 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
7068 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
7071 static always_inline
void gen_evmergelohi (DisasContext
*ctx
)
7073 if (unlikely(!ctx
->spe_enabled
)) {
7074 gen_exception(ctx
, POWERPC_EXCP_APU
);
7077 #if defined(TARGET_PPC64)
7078 TCGv t0
= tcg_temp_new();
7079 TCGv t1
= tcg_temp_new();
7080 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 32);
7081 tcg_gen_shli_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 32);
7082 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
7086 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
7087 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
7090 static always_inline
void gen_evsplati (DisasContext
*ctx
)
7092 uint64_t imm
= ((int32_t)(rA(ctx
->opcode
) << 11)) >> 27;
7094 #if defined(TARGET_PPC64)
7095 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], (imm
<< 32) | imm
);
7097 tcg_gen_movi_i32(cpu_gpr
[rD(ctx
->opcode
)], imm
);
7098 tcg_gen_movi_i32(cpu_gprh
[rD(ctx
->opcode
)], imm
);
7101 static always_inline
void gen_evsplatfi (DisasContext
*ctx
)
7103 uint64_t imm
= rA(ctx
->opcode
) << 11;
7105 #if defined(TARGET_PPC64)
7106 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], (imm
<< 32) | imm
);
7108 tcg_gen_movi_i32(cpu_gpr
[rD(ctx
->opcode
)], imm
);
7109 tcg_gen_movi_i32(cpu_gprh
[rD(ctx
->opcode
)], imm
);
7113 static always_inline
void gen_evsel (DisasContext
*ctx
)
7115 int l1
= gen_new_label();
7116 int l2
= gen_new_label();
7117 int l3
= gen_new_label();
7118 int l4
= gen_new_label();
7119 TCGv_i32 t0
= tcg_temp_local_new_i32();
7120 #if defined(TARGET_PPC64)
7121 TCGv t1
= tcg_temp_local_new();
7122 TCGv t2
= tcg_temp_local_new();
7124 tcg_gen_andi_i32(t0
, cpu_crf
[ctx
->opcode
& 0x07], 1 << 3);
7125 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l1
);
7126 #if defined(TARGET_PPC64)
7127 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 0xFFFFFFFF00000000ULL
);
7129 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
7133 #if defined(TARGET_PPC64)
7134 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0xFFFFFFFF00000000ULL
);
7136 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
7139 tcg_gen_andi_i32(t0
, cpu_crf
[ctx
->opcode
& 0x07], 1 << 2);
7140 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l3
);
7141 #if defined(TARGET_PPC64)
7142 tcg_gen_andi_tl(t2
, cpu_gpr
[rA(ctx
->opcode
)], 0x00000000FFFFFFFFULL
);
7144 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
7148 #if defined(TARGET_PPC64)
7149 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x00000000FFFFFFFFULL
);
7151 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
7154 tcg_temp_free_i32(t0
);
7155 #if defined(TARGET_PPC64)
7156 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
, t2
);
7161 GEN_HANDLER2(evsel0
, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE
)
7165 GEN_HANDLER2(evsel1
, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE
)
7169 GEN_HANDLER2(evsel2
, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE
)
7173 GEN_HANDLER2(evsel3
, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE
)
7178 GEN_SPE(evaddw
, speundef
, 0x00, 0x08, 0x00000000, PPC_SPE
); ////
7179 GEN_SPE(evaddiw
, speundef
, 0x01, 0x08, 0x00000000, PPC_SPE
);
7180 GEN_SPE(evsubfw
, speundef
, 0x02, 0x08, 0x00000000, PPC_SPE
); ////
7181 GEN_SPE(evsubifw
, speundef
, 0x03, 0x08, 0x00000000, PPC_SPE
);
7182 GEN_SPE(evabs
, evneg
, 0x04, 0x08, 0x0000F800, PPC_SPE
); ////
7183 GEN_SPE(evextsb
, evextsh
, 0x05, 0x08, 0x0000F800, PPC_SPE
); ////
7184 GEN_SPE(evrndw
, evcntlzw
, 0x06, 0x08, 0x0000F800, PPC_SPE
); ////
7185 GEN_SPE(evcntlsw
, brinc
, 0x07, 0x08, 0x00000000, PPC_SPE
); //
7186 GEN_SPE(speundef
, evand
, 0x08, 0x08, 0x00000000, PPC_SPE
); ////
7187 GEN_SPE(evandc
, speundef
, 0x09, 0x08, 0x00000000, PPC_SPE
); ////
7188 GEN_SPE(evxor
, evor
, 0x0B, 0x08, 0x00000000, PPC_SPE
); ////
7189 GEN_SPE(evnor
, eveqv
, 0x0C, 0x08, 0x00000000, PPC_SPE
); ////
7190 GEN_SPE(speundef
, evorc
, 0x0D, 0x08, 0x00000000, PPC_SPE
); ////
7191 GEN_SPE(evnand
, speundef
, 0x0F, 0x08, 0x00000000, PPC_SPE
); ////
7192 GEN_SPE(evsrwu
, evsrws
, 0x10, 0x08, 0x00000000, PPC_SPE
); ////
7193 GEN_SPE(evsrwiu
, evsrwis
, 0x11, 0x08, 0x00000000, PPC_SPE
);
7194 GEN_SPE(evslw
, speundef
, 0x12, 0x08, 0x00000000, PPC_SPE
); ////
7195 GEN_SPE(evslwi
, speundef
, 0x13, 0x08, 0x00000000, PPC_SPE
);
7196 GEN_SPE(evrlw
, evsplati
, 0x14, 0x08, 0x00000000, PPC_SPE
); //
7197 GEN_SPE(evrlwi
, evsplatfi
, 0x15, 0x08, 0x00000000, PPC_SPE
);
7198 GEN_SPE(evmergehi
, evmergelo
, 0x16, 0x08, 0x00000000, PPC_SPE
); ////
7199 GEN_SPE(evmergehilo
, evmergelohi
, 0x17, 0x08, 0x00000000, PPC_SPE
); ////
7200 GEN_SPE(evcmpgtu
, evcmpgts
, 0x18, 0x08, 0x00600000, PPC_SPE
); ////
7201 GEN_SPE(evcmpltu
, evcmplts
, 0x19, 0x08, 0x00600000, PPC_SPE
); ////
7202 GEN_SPE(evcmpeq
, speundef
, 0x1A, 0x08, 0x00600000, PPC_SPE
); ////
7204 /* SPE load and stores */
7205 static always_inline
void gen_addr_spe_imm_index (DisasContext
*ctx
, TCGv EA
, int sh
)
7207 target_ulong uimm
= rB(ctx
->opcode
);
7209 if (rA(ctx
->opcode
) == 0) {
7210 tcg_gen_movi_tl(EA
, uimm
<< sh
);
7212 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], uimm
<< sh
);
7213 #if defined(TARGET_PPC64)
7214 if (!ctx
->sf_mode
) {
7215 tcg_gen_ext32u_tl(EA
, EA
);
7221 static always_inline
void gen_op_evldd(DisasContext
*ctx
, TCGv addr
)
7223 #if defined(TARGET_PPC64)
7224 gen_qemu_ld64(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7226 TCGv_i64 t0
= tcg_temp_new_i64();
7227 gen_qemu_ld64(ctx
, t0
, addr
);
7228 tcg_gen_trunc_i64_i32(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7229 tcg_gen_shri_i64(t0
, t0
, 32);
7230 tcg_gen_trunc_i64_i32(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7231 tcg_temp_free_i64(t0
);
7235 static always_inline
void gen_op_evldw(DisasContext
*ctx
, TCGv addr
)
7237 #if defined(TARGET_PPC64)
7238 TCGv t0
= tcg_temp_new();
7239 gen_qemu_ld32u(ctx
, t0
, addr
);
7240 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
7241 gen_addr_add(ctx
, addr
, addr
, 4);
7242 gen_qemu_ld32u(ctx
, t0
, addr
);
7243 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7246 gen_qemu_ld32u(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
7247 gen_addr_add(ctx
, addr
, addr
, 4);
7248 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7252 static always_inline
void gen_op_evldh(DisasContext
*ctx
, TCGv addr
)
7254 TCGv t0
= tcg_temp_new();
7255 #if defined(TARGET_PPC64)
7256 gen_qemu_ld16u(ctx
, t0
, addr
);
7257 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 48);
7258 gen_addr_add(ctx
, addr
, addr
, 2);
7259 gen_qemu_ld16u(ctx
, t0
, addr
);
7260 tcg_gen_shli_tl(t0
, t0
, 32);
7261 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7262 gen_addr_add(ctx
, addr
, addr
, 2);
7263 gen_qemu_ld16u(ctx
, t0
, addr
);
7264 tcg_gen_shli_tl(t0
, t0
, 16);
7265 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7266 gen_addr_add(ctx
, addr
, addr
, 2);
7267 gen_qemu_ld16u(ctx
, t0
, addr
);
7268 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7270 gen_qemu_ld16u(ctx
, t0
, addr
);
7271 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
7272 gen_addr_add(ctx
, addr
, addr
, 2);
7273 gen_qemu_ld16u(ctx
, t0
, addr
);
7274 tcg_gen_or_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
7275 gen_addr_add(ctx
, addr
, addr
, 2);
7276 gen_qemu_ld16u(ctx
, t0
, addr
);
7277 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
7278 gen_addr_add(ctx
, addr
, addr
, 2);
7279 gen_qemu_ld16u(ctx
, t0
, addr
);
7280 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7285 static always_inline
void gen_op_evlhhesplat(DisasContext
*ctx
, TCGv addr
)
7287 TCGv t0
= tcg_temp_new();
7288 gen_qemu_ld16u(ctx
, t0
, addr
);
7289 #if defined(TARGET_PPC64)
7290 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 48);
7291 tcg_gen_shli_tl(t0
, t0
, 16);
7292 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7294 tcg_gen_shli_tl(t0
, t0
, 16);
7295 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7296 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7301 static always_inline
void gen_op_evlhhousplat(DisasContext
*ctx
, TCGv addr
)
7303 TCGv t0
= tcg_temp_new();
7304 gen_qemu_ld16u(ctx
, t0
, addr
);
7305 #if defined(TARGET_PPC64)
7306 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
7307 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7309 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7310 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7315 static always_inline
void gen_op_evlhhossplat(DisasContext
*ctx
, TCGv addr
)
7317 TCGv t0
= tcg_temp_new();
7318 gen_qemu_ld16s(ctx
, t0
, addr
);
7319 #if defined(TARGET_PPC64)
7320 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
7321 tcg_gen_ext32u_tl(t0
, t0
);
7322 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7324 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7325 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7330 static always_inline
void gen_op_evlwhe(DisasContext
*ctx
, TCGv addr
)
7332 TCGv t0
= tcg_temp_new();
7333 #if defined(TARGET_PPC64)
7334 gen_qemu_ld16u(ctx
, t0
, addr
);
7335 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 48);
7336 gen_addr_add(ctx
, addr
, addr
, 2);
7337 gen_qemu_ld16u(ctx
, t0
, addr
);
7338 tcg_gen_shli_tl(t0
, t0
, 16);
7339 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7341 gen_qemu_ld16u(ctx
, t0
, addr
);
7342 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
7343 gen_addr_add(ctx
, addr
, addr
, 2);
7344 gen_qemu_ld16u(ctx
, t0
, addr
);
7345 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 16);
7350 static always_inline
void gen_op_evlwhou(DisasContext
*ctx
, TCGv addr
)
7352 #if defined(TARGET_PPC64)
7353 TCGv t0
= tcg_temp_new();
7354 gen_qemu_ld16u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7355 gen_addr_add(ctx
, addr
, addr
, 2);
7356 gen_qemu_ld16u(ctx
, t0
, addr
);
7357 tcg_gen_shli_tl(t0
, t0
, 32);
7358 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7361 gen_qemu_ld16u(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
7362 gen_addr_add(ctx
, addr
, addr
, 2);
7363 gen_qemu_ld16u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7367 static always_inline
void gen_op_evlwhos(DisasContext
*ctx
, TCGv addr
)
7369 #if defined(TARGET_PPC64)
7370 TCGv t0
= tcg_temp_new();
7371 gen_qemu_ld16s(ctx
, t0
, addr
);
7372 tcg_gen_ext32u_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7373 gen_addr_add(ctx
, addr
, addr
, 2);
7374 gen_qemu_ld16s(ctx
, t0
, addr
);
7375 tcg_gen_shli_tl(t0
, t0
, 32);
7376 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7379 gen_qemu_ld16s(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
7380 gen_addr_add(ctx
, addr
, addr
, 2);
7381 gen_qemu_ld16s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7385 static always_inline
void gen_op_evlwwsplat(DisasContext
*ctx
, TCGv addr
)
7387 TCGv t0
= tcg_temp_new();
7388 gen_qemu_ld32u(ctx
, t0
, addr
);
7389 #if defined(TARGET_PPC64)
7390 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
7391 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7393 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7394 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7399 static always_inline
void gen_op_evlwhsplat(DisasContext
*ctx
, TCGv addr
)
7401 TCGv t0
= tcg_temp_new();
7402 #if defined(TARGET_PPC64)
7403 gen_qemu_ld16u(ctx
, t0
, addr
);
7404 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 48);
7405 tcg_gen_shli_tl(t0
, t0
, 32);
7406 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7407 gen_addr_add(ctx
, addr
, addr
, 2);
7408 gen_qemu_ld16u(ctx
, t0
, addr
);
7409 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7410 tcg_gen_shli_tl(t0
, t0
, 16);
7411 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7413 gen_qemu_ld16u(ctx
, t0
, addr
);
7414 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
7415 tcg_gen_or_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
7416 gen_addr_add(ctx
, addr
, addr
, 2);
7417 gen_qemu_ld16u(ctx
, t0
, addr
);
7418 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 16);
7419 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
7424 static always_inline
void gen_op_evstdd(DisasContext
*ctx
, TCGv addr
)
7426 #if defined(TARGET_PPC64)
7427 gen_qemu_st64(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7429 TCGv_i64 t0
= tcg_temp_new_i64();
7430 tcg_gen_concat_i32_i64(t0
, cpu_gpr
[rS(ctx
->opcode
)], cpu_gprh
[rS(ctx
->opcode
)]);
7431 gen_qemu_st64(ctx
, t0
, addr
);
7432 tcg_temp_free_i64(t0
);
7436 static always_inline
void gen_op_evstdw(DisasContext
*ctx
, TCGv addr
)
7438 #if defined(TARGET_PPC64)
7439 TCGv t0
= tcg_temp_new();
7440 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 32);
7441 gen_qemu_st32(ctx
, t0
, addr
);
7444 gen_qemu_st32(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
7446 gen_addr_add(ctx
, addr
, addr
, 4);
7447 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7450 static always_inline
void gen_op_evstdh(DisasContext
*ctx
, TCGv addr
)
7452 TCGv t0
= tcg_temp_new();
7453 #if defined(TARGET_PPC64)
7454 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 48);
7456 tcg_gen_shri_tl(t0
, cpu_gprh
[rS(ctx
->opcode
)], 16);
7458 gen_qemu_st16(ctx
, t0
, addr
);
7459 gen_addr_add(ctx
, addr
, addr
, 2);
7460 #if defined(TARGET_PPC64)
7461 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 32);
7462 gen_qemu_st16(ctx
, t0
, addr
);
7464 gen_qemu_st16(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
7466 gen_addr_add(ctx
, addr
, addr
, 2);
7467 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 16);
7468 gen_qemu_st16(ctx
, t0
, addr
);
7470 gen_addr_add(ctx
, addr
, addr
, 2);
7471 gen_qemu_st16(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7474 static always_inline
void gen_op_evstwhe(DisasContext
*ctx
, TCGv addr
)
7476 TCGv t0
= tcg_temp_new();
7477 #if defined(TARGET_PPC64)
7478 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 48);
7480 tcg_gen_shri_tl(t0
, cpu_gprh
[rS(ctx
->opcode
)], 16);
7482 gen_qemu_st16(ctx
, t0
, addr
);
7483 gen_addr_add(ctx
, addr
, addr
, 2);
7484 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 16);
7485 gen_qemu_st16(ctx
, t0
, addr
);
7489 static always_inline
void gen_op_evstwho(DisasContext
*ctx
, TCGv addr
)
7491 #if defined(TARGET_PPC64)
7492 TCGv t0
= tcg_temp_new();
7493 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 32);
7494 gen_qemu_st16(ctx
, t0
, addr
);
7497 gen_qemu_st16(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
7499 gen_addr_add(ctx
, addr
, addr
, 2);
7500 gen_qemu_st16(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7503 static always_inline
void gen_op_evstwwe(DisasContext
*ctx
, TCGv addr
)
7505 #if defined(TARGET_PPC64)
7506 TCGv t0
= tcg_temp_new();
7507 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 32);
7508 gen_qemu_st32(ctx
, t0
, addr
);
7511 gen_qemu_st32(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
7515 static always_inline
void gen_op_evstwwo(DisasContext
*ctx
, TCGv addr
)
7517 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7520 #define GEN_SPEOP_LDST(name, opc2, sh) \
7521 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \
7524 if (unlikely(!ctx->spe_enabled)) { \
7525 gen_exception(ctx, POWERPC_EXCP_APU); \
7528 gen_set_access_type(ctx, ACCESS_INT); \
7529 t0 = tcg_temp_new(); \
7530 if (Rc(ctx->opcode)) { \
7531 gen_addr_spe_imm_index(ctx, t0, sh); \
7533 gen_addr_reg_index(ctx, t0); \
7535 gen_op_##name(ctx, t0); \
7536 tcg_temp_free(t0); \
7539 GEN_SPEOP_LDST(evldd
, 0x00, 3);
7540 GEN_SPEOP_LDST(evldw
, 0x01, 3);
7541 GEN_SPEOP_LDST(evldh
, 0x02, 3);
7542 GEN_SPEOP_LDST(evlhhesplat
, 0x04, 1);
7543 GEN_SPEOP_LDST(evlhhousplat
, 0x06, 1);
7544 GEN_SPEOP_LDST(evlhhossplat
, 0x07, 1);
7545 GEN_SPEOP_LDST(evlwhe
, 0x08, 2);
7546 GEN_SPEOP_LDST(evlwhou
, 0x0A, 2);
7547 GEN_SPEOP_LDST(evlwhos
, 0x0B, 2);
7548 GEN_SPEOP_LDST(evlwwsplat
, 0x0C, 2);
7549 GEN_SPEOP_LDST(evlwhsplat
, 0x0E, 2);
7551 GEN_SPEOP_LDST(evstdd
, 0x10, 3);
7552 GEN_SPEOP_LDST(evstdw
, 0x11, 3);
7553 GEN_SPEOP_LDST(evstdh
, 0x12, 3);
7554 GEN_SPEOP_LDST(evstwhe
, 0x18, 2);
7555 GEN_SPEOP_LDST(evstwho
, 0x1A, 2);
7556 GEN_SPEOP_LDST(evstwwe
, 0x1C, 2);
7557 GEN_SPEOP_LDST(evstwwo
, 0x1E, 2);
7559 /* Multiply and add - TODO */
7561 GEN_SPE(speundef
, evmhessf
, 0x01, 0x10, 0x00000000, PPC_SPE
);
7562 GEN_SPE(speundef
, evmhossf
, 0x03, 0x10, 0x00000000, PPC_SPE
);
7563 GEN_SPE(evmheumi
, evmhesmi
, 0x04, 0x10, 0x00000000, PPC_SPE
);
7564 GEN_SPE(speundef
, evmhesmf
, 0x05, 0x10, 0x00000000, PPC_SPE
);
7565 GEN_SPE(evmhoumi
, evmhosmi
, 0x06, 0x10, 0x00000000, PPC_SPE
);
7566 GEN_SPE(speundef
, evmhosmf
, 0x07, 0x10, 0x00000000, PPC_SPE
);
7567 GEN_SPE(speundef
, evmhessfa
, 0x11, 0x10, 0x00000000, PPC_SPE
);
7568 GEN_SPE(speundef
, evmhossfa
, 0x13, 0x10, 0x00000000, PPC_SPE
);
7569 GEN_SPE(evmheumia
, evmhesmia
, 0x14, 0x10, 0x00000000, PPC_SPE
);
7570 GEN_SPE(speundef
, evmhesmfa
, 0x15, 0x10, 0x00000000, PPC_SPE
);
7571 GEN_SPE(evmhoumia
, evmhosmia
, 0x16, 0x10, 0x00000000, PPC_SPE
);
7572 GEN_SPE(speundef
, evmhosmfa
, 0x17, 0x10, 0x00000000, PPC_SPE
);
7574 GEN_SPE(speundef
, evmwhssf
, 0x03, 0x11, 0x00000000, PPC_SPE
);
7575 GEN_SPE(evmwlumi
, speundef
, 0x04, 0x11, 0x00000000, PPC_SPE
);
7576 GEN_SPE(evmwhumi
, evmwhsmi
, 0x06, 0x11, 0x00000000, PPC_SPE
);
7577 GEN_SPE(speundef
, evmwhsmf
, 0x07, 0x11, 0x00000000, PPC_SPE
);
7578 GEN_SPE(speundef
, evmwssf
, 0x09, 0x11, 0x00000000, PPC_SPE
);
7579 GEN_SPE(evmwumi
, evmwsmi
, 0x0C, 0x11, 0x00000000, PPC_SPE
);
7580 GEN_SPE(speundef
, evmwsmf
, 0x0D, 0x11, 0x00000000, PPC_SPE
);
7581 GEN_SPE(speundef
, evmwhssfa
, 0x13, 0x11, 0x00000000, PPC_SPE
);
7582 GEN_SPE(evmwlumia
, speundef
, 0x14, 0x11, 0x00000000, PPC_SPE
);
7583 GEN_SPE(evmwhumia
, evmwhsmia
, 0x16, 0x11, 0x00000000, PPC_SPE
);
7584 GEN_SPE(speundef
, evmwhsmfa
, 0x17, 0x11, 0x00000000, PPC_SPE
);
7585 GEN_SPE(speundef
, evmwssfa
, 0x19, 0x11, 0x00000000, PPC_SPE
);
7586 GEN_SPE(evmwumia
, evmwsmia
, 0x1C, 0x11, 0x00000000, PPC_SPE
);
7587 GEN_SPE(speundef
, evmwsmfa
, 0x1D, 0x11, 0x00000000, PPC_SPE
);
7589 GEN_SPE(evadduiaaw
, evaddsiaaw
, 0x00, 0x13, 0x0000F800, PPC_SPE
);
7590 GEN_SPE(evsubfusiaaw
, evsubfssiaaw
, 0x01, 0x13, 0x0000F800, PPC_SPE
);
7591 GEN_SPE(evaddumiaaw
, evaddsmiaaw
, 0x04, 0x13, 0x0000F800, PPC_SPE
);
7592 GEN_SPE(evsubfumiaaw
, evsubfsmiaaw
, 0x05, 0x13, 0x0000F800, PPC_SPE
);
7593 GEN_SPE(evdivws
, evdivwu
, 0x06, 0x13, 0x00000000, PPC_SPE
);
7594 GEN_SPE(evmra
, speundef
, 0x07, 0x13, 0x0000F800, PPC_SPE
);
7596 GEN_SPE(evmheusiaaw
, evmhessiaaw
, 0x00, 0x14, 0x00000000, PPC_SPE
);
7597 GEN_SPE(speundef
, evmhessfaaw
, 0x01, 0x14, 0x00000000, PPC_SPE
);
7598 GEN_SPE(evmhousiaaw
, evmhossiaaw
, 0x02, 0x14, 0x00000000, PPC_SPE
);
7599 GEN_SPE(speundef
, evmhossfaaw
, 0x03, 0x14, 0x00000000, PPC_SPE
);
7600 GEN_SPE(evmheumiaaw
, evmhesmiaaw
, 0x04, 0x14, 0x00000000, PPC_SPE
);
7601 GEN_SPE(speundef
, evmhesmfaaw
, 0x05, 0x14, 0x00000000, PPC_SPE
);
7602 GEN_SPE(evmhoumiaaw
, evmhosmiaaw
, 0x06, 0x14, 0x00000000, PPC_SPE
);
7603 GEN_SPE(speundef
, evmhosmfaaw
, 0x07, 0x14, 0x00000000, PPC_SPE
);
7604 GEN_SPE(evmhegumiaa
, evmhegsmiaa
, 0x14, 0x14, 0x00000000, PPC_SPE
);
7605 GEN_SPE(speundef
, evmhegsmfaa
, 0x15, 0x14, 0x00000000, PPC_SPE
);
7606 GEN_SPE(evmhogumiaa
, evmhogsmiaa
, 0x16, 0x14, 0x00000000, PPC_SPE
);
7607 GEN_SPE(speundef
, evmhogsmfaa
, 0x17, 0x14, 0x00000000, PPC_SPE
);
7609 GEN_SPE(evmwlusiaaw
, evmwlssiaaw
, 0x00, 0x15, 0x00000000, PPC_SPE
);
7610 GEN_SPE(evmwlumiaaw
, evmwlsmiaaw
, 0x04, 0x15, 0x00000000, PPC_SPE
);
7611 GEN_SPE(speundef
, evmwssfaa
, 0x09, 0x15, 0x00000000, PPC_SPE
);
7612 GEN_SPE(evmwumiaa
, evmwsmiaa
, 0x0C, 0x15, 0x00000000, PPC_SPE
);
7613 GEN_SPE(speundef
, evmwsmfaa
, 0x0D, 0x15, 0x00000000, PPC_SPE
);
7615 GEN_SPE(evmheusianw
, evmhessianw
, 0x00, 0x16, 0x00000000, PPC_SPE
);
7616 GEN_SPE(speundef
, evmhessfanw
, 0x01, 0x16, 0x00000000, PPC_SPE
);
7617 GEN_SPE(evmhousianw
, evmhossianw
, 0x02, 0x16, 0x00000000, PPC_SPE
);
7618 GEN_SPE(speundef
, evmhossfanw
, 0x03, 0x16, 0x00000000, PPC_SPE
);
7619 GEN_SPE(evmheumianw
, evmhesmianw
, 0x04, 0x16, 0x00000000, PPC_SPE
);
7620 GEN_SPE(speundef
, evmhesmfanw
, 0x05, 0x16, 0x00000000, PPC_SPE
);
7621 GEN_SPE(evmhoumianw
, evmhosmianw
, 0x06, 0x16, 0x00000000, PPC_SPE
);
7622 GEN_SPE(speundef
, evmhosmfanw
, 0x07, 0x16, 0x00000000, PPC_SPE
);
7623 GEN_SPE(evmhegumian
, evmhegsmian
, 0x14, 0x16, 0x00000000, PPC_SPE
);
7624 GEN_SPE(speundef
, evmhegsmfan
, 0x15, 0x16, 0x00000000, PPC_SPE
);
7625 GEN_SPE(evmhigumian
, evmhigsmian
, 0x16, 0x16, 0x00000000, PPC_SPE
);
7626 GEN_SPE(speundef
, evmhogsmfan
, 0x17, 0x16, 0x00000000, PPC_SPE
);
7628 GEN_SPE(evmwlusianw
, evmwlssianw
, 0x00, 0x17, 0x00000000, PPC_SPE
);
7629 GEN_SPE(evmwlumianw
, evmwlsmianw
, 0x04, 0x17, 0x00000000, PPC_SPE
);
7630 GEN_SPE(speundef
, evmwssfan
, 0x09, 0x17, 0x00000000, PPC_SPE
);
7631 GEN_SPE(evmwumian
, evmwsmian
, 0x0C, 0x17, 0x00000000, PPC_SPE
);
7632 GEN_SPE(speundef
, evmwsmfan
, 0x0D, 0x17, 0x00000000, PPC_SPE
);
7635 /*** SPE floating-point extension ***/
7636 #if defined(TARGET_PPC64)
7637 #define GEN_SPEFPUOP_CONV_32_32(name) \
7638 static always_inline void gen_##name (DisasContext *ctx) \
7642 t0 = tcg_temp_new_i32(); \
7643 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7644 gen_helper_##name(t0, t0); \
7645 t1 = tcg_temp_new(); \
7646 tcg_gen_extu_i32_tl(t1, t0); \
7647 tcg_temp_free_i32(t0); \
7648 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7649 0xFFFFFFFF00000000ULL); \
7650 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7651 tcg_temp_free(t1); \
7653 #define GEN_SPEFPUOP_CONV_32_64(name) \
7654 static always_inline void gen_##name (DisasContext *ctx) \
7658 t0 = tcg_temp_new_i32(); \
7659 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7660 t1 = tcg_temp_new(); \
7661 tcg_gen_extu_i32_tl(t1, t0); \
7662 tcg_temp_free_i32(t0); \
7663 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7664 0xFFFFFFFF00000000ULL); \
7665 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7666 tcg_temp_free(t1); \
7668 #define GEN_SPEFPUOP_CONV_64_32(name) \
7669 static always_inline void gen_##name (DisasContext *ctx) \
7671 TCGv_i32 t0 = tcg_temp_new_i32(); \
7672 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7673 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7674 tcg_temp_free_i32(t0); \
7676 #define GEN_SPEFPUOP_CONV_64_64(name) \
7677 static always_inline void gen_##name (DisasContext *ctx) \
7679 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7681 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7682 static always_inline void gen_##name (DisasContext *ctx) \
7686 if (unlikely(!ctx->spe_enabled)) { \
7687 gen_exception(ctx, POWERPC_EXCP_APU); \
7690 t0 = tcg_temp_new_i32(); \
7691 t1 = tcg_temp_new_i32(); \
7692 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7693 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7694 gen_helper_##name(t0, t0, t1); \
7695 tcg_temp_free_i32(t1); \
7696 t2 = tcg_temp_new(); \
7697 tcg_gen_extu_i32_tl(t2, t0); \
7698 tcg_temp_free_i32(t0); \
7699 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7700 0xFFFFFFFF00000000ULL); \
7701 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
7702 tcg_temp_free(t2); \
7704 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7705 static always_inline void gen_##name (DisasContext *ctx) \
7707 if (unlikely(!ctx->spe_enabled)) { \
7708 gen_exception(ctx, POWERPC_EXCP_APU); \
7711 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7712 cpu_gpr[rB(ctx->opcode)]); \
7714 #define GEN_SPEFPUOP_COMP_32(name) \
7715 static always_inline void gen_##name (DisasContext *ctx) \
7718 if (unlikely(!ctx->spe_enabled)) { \
7719 gen_exception(ctx, POWERPC_EXCP_APU); \
7722 t0 = tcg_temp_new_i32(); \
7723 t1 = tcg_temp_new_i32(); \
7724 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7725 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7726 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7727 tcg_temp_free_i32(t0); \
7728 tcg_temp_free_i32(t1); \
7730 #define GEN_SPEFPUOP_COMP_64(name) \
7731 static always_inline void gen_##name (DisasContext *ctx) \
7733 if (unlikely(!ctx->spe_enabled)) { \
7734 gen_exception(ctx, POWERPC_EXCP_APU); \
7737 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7738 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7741 #define GEN_SPEFPUOP_CONV_32_32(name) \
7742 static always_inline void gen_##name (DisasContext *ctx) \
7744 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7746 #define GEN_SPEFPUOP_CONV_32_64(name) \
7747 static always_inline void gen_##name (DisasContext *ctx) \
7749 TCGv_i64 t0 = tcg_temp_new_i64(); \
7750 gen_load_gpr64(t0, rB(ctx->opcode)); \
7751 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7752 tcg_temp_free_i64(t0); \
7754 #define GEN_SPEFPUOP_CONV_64_32(name) \
7755 static always_inline void gen_##name (DisasContext *ctx) \
7757 TCGv_i64 t0 = tcg_temp_new_i64(); \
7758 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7759 gen_store_gpr64(rD(ctx->opcode), t0); \
7760 tcg_temp_free_i64(t0); \
7762 #define GEN_SPEFPUOP_CONV_64_64(name) \
7763 static always_inline void gen_##name (DisasContext *ctx) \
7765 TCGv_i64 t0 = tcg_temp_new_i64(); \
7766 gen_load_gpr64(t0, rB(ctx->opcode)); \
7767 gen_helper_##name(t0, t0); \
7768 gen_store_gpr64(rD(ctx->opcode), t0); \
7769 tcg_temp_free_i64(t0); \
7771 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7772 static always_inline void gen_##name (DisasContext *ctx) \
7774 if (unlikely(!ctx->spe_enabled)) { \
7775 gen_exception(ctx, POWERPC_EXCP_APU); \
7778 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7779 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7781 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7782 static always_inline void gen_##name (DisasContext *ctx) \
7785 if (unlikely(!ctx->spe_enabled)) { \
7786 gen_exception(ctx, POWERPC_EXCP_APU); \
7789 t0 = tcg_temp_new_i64(); \
7790 t1 = tcg_temp_new_i64(); \
7791 gen_load_gpr64(t0, rA(ctx->opcode)); \
7792 gen_load_gpr64(t1, rB(ctx->opcode)); \
7793 gen_helper_##name(t0, t0, t1); \
7794 gen_store_gpr64(rD(ctx->opcode), t0); \
7795 tcg_temp_free_i64(t0); \
7796 tcg_temp_free_i64(t1); \
7798 #define GEN_SPEFPUOP_COMP_32(name) \
7799 static always_inline void gen_##name (DisasContext *ctx) \
7801 if (unlikely(!ctx->spe_enabled)) { \
7802 gen_exception(ctx, POWERPC_EXCP_APU); \
7805 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7806 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7808 #define GEN_SPEFPUOP_COMP_64(name) \
7809 static always_inline void gen_##name (DisasContext *ctx) \
7812 if (unlikely(!ctx->spe_enabled)) { \
7813 gen_exception(ctx, POWERPC_EXCP_APU); \
7816 t0 = tcg_temp_new_i64(); \
7817 t1 = tcg_temp_new_i64(); \
7818 gen_load_gpr64(t0, rA(ctx->opcode)); \
7819 gen_load_gpr64(t1, rB(ctx->opcode)); \
7820 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7821 tcg_temp_free_i64(t0); \
7822 tcg_temp_free_i64(t1); \
7826 /* Single precision floating-point vectors operations */
7828 GEN_SPEFPUOP_ARITH2_64_64(evfsadd
);
7829 GEN_SPEFPUOP_ARITH2_64_64(evfssub
);
7830 GEN_SPEFPUOP_ARITH2_64_64(evfsmul
);
7831 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv
);
7832 static always_inline
void gen_evfsabs (DisasContext
*ctx
)
7834 if (unlikely(!ctx
->spe_enabled
)) {
7835 gen_exception(ctx
, POWERPC_EXCP_APU
);
7838 #if defined(TARGET_PPC64)
7839 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~0x8000000080000000LL
);
7841 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~0x80000000);
7842 tcg_gen_andi_tl(cpu_gprh
[rA(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], ~0x80000000);
7845 static always_inline
void gen_evfsnabs (DisasContext
*ctx
)
7847 if (unlikely(!ctx
->spe_enabled
)) {
7848 gen_exception(ctx
, POWERPC_EXCP_APU
);
7851 #if defined(TARGET_PPC64)
7852 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x8000000080000000LL
);
7854 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
7855 tcg_gen_ori_tl(cpu_gprh
[rA(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], 0x80000000);
7858 static always_inline
void gen_evfsneg (DisasContext
*ctx
)
7860 if (unlikely(!ctx
->spe_enabled
)) {
7861 gen_exception(ctx
, POWERPC_EXCP_APU
);
7864 #if defined(TARGET_PPC64)
7865 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x8000000080000000LL
);
7867 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
7868 tcg_gen_xori_tl(cpu_gprh
[rA(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], 0x80000000);
7873 GEN_SPEFPUOP_CONV_64_64(evfscfui
);
7874 GEN_SPEFPUOP_CONV_64_64(evfscfsi
);
7875 GEN_SPEFPUOP_CONV_64_64(evfscfuf
);
7876 GEN_SPEFPUOP_CONV_64_64(evfscfsf
);
7877 GEN_SPEFPUOP_CONV_64_64(evfsctui
);
7878 GEN_SPEFPUOP_CONV_64_64(evfsctsi
);
7879 GEN_SPEFPUOP_CONV_64_64(evfsctuf
);
7880 GEN_SPEFPUOP_CONV_64_64(evfsctsf
);
7881 GEN_SPEFPUOP_CONV_64_64(evfsctuiz
);
7882 GEN_SPEFPUOP_CONV_64_64(evfsctsiz
);
7885 GEN_SPEFPUOP_COMP_64(evfscmpgt
);
7886 GEN_SPEFPUOP_COMP_64(evfscmplt
);
7887 GEN_SPEFPUOP_COMP_64(evfscmpeq
);
7888 GEN_SPEFPUOP_COMP_64(evfststgt
);
7889 GEN_SPEFPUOP_COMP_64(evfststlt
);
7890 GEN_SPEFPUOP_COMP_64(evfststeq
);
7892 /* Opcodes definitions */
7893 GEN_SPE(evfsadd
, evfssub
, 0x00, 0x0A, 0x00000000, PPC_SPE_SINGLE
); //
7894 GEN_SPE(evfsabs
, evfsnabs
, 0x02, 0x0A, 0x0000F800, PPC_SPE_SINGLE
); //
7895 GEN_SPE(evfsneg
, speundef
, 0x03, 0x0A, 0x0000F800, PPC_SPE_SINGLE
); //
7896 GEN_SPE(evfsmul
, evfsdiv
, 0x04, 0x0A, 0x00000000, PPC_SPE_SINGLE
); //
7897 GEN_SPE(evfscmpgt
, evfscmplt
, 0x06, 0x0A, 0x00600000, PPC_SPE_SINGLE
); //
7898 GEN_SPE(evfscmpeq
, speundef
, 0x07, 0x0A, 0x00600000, PPC_SPE_SINGLE
); //
7899 GEN_SPE(evfscfui
, evfscfsi
, 0x08, 0x0A, 0x00180000, PPC_SPE_SINGLE
); //
7900 GEN_SPE(evfscfuf
, evfscfsf
, 0x09, 0x0A, 0x00180000, PPC_SPE_SINGLE
); //
7901 GEN_SPE(evfsctui
, evfsctsi
, 0x0A, 0x0A, 0x00180000, PPC_SPE_SINGLE
); //
7902 GEN_SPE(evfsctuf
, evfsctsf
, 0x0B, 0x0A, 0x00180000, PPC_SPE_SINGLE
); //
7903 GEN_SPE(evfsctuiz
, speundef
, 0x0C, 0x0A, 0x00180000, PPC_SPE_SINGLE
); //
7904 GEN_SPE(evfsctsiz
, speundef
, 0x0D, 0x0A, 0x00180000, PPC_SPE_SINGLE
); //
7905 GEN_SPE(evfststgt
, evfststlt
, 0x0E, 0x0A, 0x00600000, PPC_SPE_SINGLE
); //
7906 GEN_SPE(evfststeq
, speundef
, 0x0F, 0x0A, 0x00600000, PPC_SPE_SINGLE
); //
7908 /* Single precision floating-point operations */
7910 GEN_SPEFPUOP_ARITH2_32_32(efsadd
);
7911 GEN_SPEFPUOP_ARITH2_32_32(efssub
);
7912 GEN_SPEFPUOP_ARITH2_32_32(efsmul
);
7913 GEN_SPEFPUOP_ARITH2_32_32(efsdiv
);
7914 static always_inline
void gen_efsabs (DisasContext
*ctx
)
7916 if (unlikely(!ctx
->spe_enabled
)) {
7917 gen_exception(ctx
, POWERPC_EXCP_APU
);
7920 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], (target_long
)~0x80000000LL
);
7922 static always_inline
void gen_efsnabs (DisasContext
*ctx
)
7924 if (unlikely(!ctx
->spe_enabled
)) {
7925 gen_exception(ctx
, POWERPC_EXCP_APU
);
7928 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
7930 static always_inline
void gen_efsneg (DisasContext
*ctx
)
7932 if (unlikely(!ctx
->spe_enabled
)) {
7933 gen_exception(ctx
, POWERPC_EXCP_APU
);
7936 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
7940 GEN_SPEFPUOP_CONV_32_32(efscfui
);
7941 GEN_SPEFPUOP_CONV_32_32(efscfsi
);
7942 GEN_SPEFPUOP_CONV_32_32(efscfuf
);
7943 GEN_SPEFPUOP_CONV_32_32(efscfsf
);
7944 GEN_SPEFPUOP_CONV_32_32(efsctui
);
7945 GEN_SPEFPUOP_CONV_32_32(efsctsi
);
7946 GEN_SPEFPUOP_CONV_32_32(efsctuf
);
7947 GEN_SPEFPUOP_CONV_32_32(efsctsf
);
7948 GEN_SPEFPUOP_CONV_32_32(efsctuiz
);
7949 GEN_SPEFPUOP_CONV_32_32(efsctsiz
);
7950 GEN_SPEFPUOP_CONV_32_64(efscfd
);
7953 GEN_SPEFPUOP_COMP_32(efscmpgt
);
7954 GEN_SPEFPUOP_COMP_32(efscmplt
);
7955 GEN_SPEFPUOP_COMP_32(efscmpeq
);
7956 GEN_SPEFPUOP_COMP_32(efststgt
);
7957 GEN_SPEFPUOP_COMP_32(efststlt
);
7958 GEN_SPEFPUOP_COMP_32(efststeq
);
7960 /* Opcodes definitions */
7961 GEN_SPE(efsadd
, efssub
, 0x00, 0x0B, 0x00000000, PPC_SPE_SINGLE
); //
7962 GEN_SPE(efsabs
, efsnabs
, 0x02, 0x0B, 0x0000F800, PPC_SPE_SINGLE
); //
7963 GEN_SPE(efsneg
, speundef
, 0x03, 0x0B, 0x0000F800, PPC_SPE_SINGLE
); //
7964 GEN_SPE(efsmul
, efsdiv
, 0x04, 0x0B, 0x00000000, PPC_SPE_SINGLE
); //
7965 GEN_SPE(efscmpgt
, efscmplt
, 0x06, 0x0B, 0x00600000, PPC_SPE_SINGLE
); //
7966 GEN_SPE(efscmpeq
, efscfd
, 0x07, 0x0B, 0x00600000, PPC_SPE_SINGLE
); //
7967 GEN_SPE(efscfui
, efscfsi
, 0x08, 0x0B, 0x00180000, PPC_SPE_SINGLE
); //
7968 GEN_SPE(efscfuf
, efscfsf
, 0x09, 0x0B, 0x00180000, PPC_SPE_SINGLE
); //
7969 GEN_SPE(efsctui
, efsctsi
, 0x0A, 0x0B, 0x00180000, PPC_SPE_SINGLE
); //
7970 GEN_SPE(efsctuf
, efsctsf
, 0x0B, 0x0B, 0x00180000, PPC_SPE_SINGLE
); //
7971 GEN_SPE(efsctuiz
, speundef
, 0x0C, 0x0B, 0x00180000, PPC_SPE_SINGLE
); //
7972 GEN_SPE(efsctsiz
, speundef
, 0x0D, 0x0B, 0x00180000, PPC_SPE_SINGLE
); //
7973 GEN_SPE(efststgt
, efststlt
, 0x0E, 0x0B, 0x00600000, PPC_SPE_SINGLE
); //
7974 GEN_SPE(efststeq
, speundef
, 0x0F, 0x0B, 0x00600000, PPC_SPE_SINGLE
); //
7976 /* Double precision floating-point operations */
7978 GEN_SPEFPUOP_ARITH2_64_64(efdadd
);
7979 GEN_SPEFPUOP_ARITH2_64_64(efdsub
);
7980 GEN_SPEFPUOP_ARITH2_64_64(efdmul
);
7981 GEN_SPEFPUOP_ARITH2_64_64(efddiv
);
7982 static always_inline
void gen_efdabs (DisasContext
*ctx
)
7984 if (unlikely(!ctx
->spe_enabled
)) {
7985 gen_exception(ctx
, POWERPC_EXCP_APU
);
7988 #if defined(TARGET_PPC64)
7989 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~0x8000000000000000LL
);
7991 tcg_gen_andi_tl(cpu_gprh
[rA(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], ~0x80000000);
7994 static always_inline
void gen_efdnabs (DisasContext
*ctx
)
7996 if (unlikely(!ctx
->spe_enabled
)) {
7997 gen_exception(ctx
, POWERPC_EXCP_APU
);
8000 #if defined(TARGET_PPC64)
8001 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x8000000000000000LL
);
8003 tcg_gen_ori_tl(cpu_gprh
[rA(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], 0x80000000);
8006 static always_inline
void gen_efdneg (DisasContext
*ctx
)
8008 if (unlikely(!ctx
->spe_enabled
)) {
8009 gen_exception(ctx
, POWERPC_EXCP_APU
);
8012 #if defined(TARGET_PPC64)
8013 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x8000000000000000LL
);
8015 tcg_gen_xori_tl(cpu_gprh
[rA(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], 0x80000000);
8020 GEN_SPEFPUOP_CONV_64_32(efdcfui
);
8021 GEN_SPEFPUOP_CONV_64_32(efdcfsi
);
8022 GEN_SPEFPUOP_CONV_64_32(efdcfuf
);
8023 GEN_SPEFPUOP_CONV_64_32(efdcfsf
);
8024 GEN_SPEFPUOP_CONV_32_64(efdctui
);
8025 GEN_SPEFPUOP_CONV_32_64(efdctsi
);
8026 GEN_SPEFPUOP_CONV_32_64(efdctuf
);
8027 GEN_SPEFPUOP_CONV_32_64(efdctsf
);
8028 GEN_SPEFPUOP_CONV_32_64(efdctuiz
);
8029 GEN_SPEFPUOP_CONV_32_64(efdctsiz
);
8030 GEN_SPEFPUOP_CONV_64_32(efdcfs
);
8031 GEN_SPEFPUOP_CONV_64_64(efdcfuid
);
8032 GEN_SPEFPUOP_CONV_64_64(efdcfsid
);
8033 GEN_SPEFPUOP_CONV_64_64(efdctuidz
);
8034 GEN_SPEFPUOP_CONV_64_64(efdctsidz
);
8037 GEN_SPEFPUOP_COMP_64(efdcmpgt
);
8038 GEN_SPEFPUOP_COMP_64(efdcmplt
);
8039 GEN_SPEFPUOP_COMP_64(efdcmpeq
);
8040 GEN_SPEFPUOP_COMP_64(efdtstgt
);
8041 GEN_SPEFPUOP_COMP_64(efdtstlt
);
8042 GEN_SPEFPUOP_COMP_64(efdtsteq
);
8044 /* Opcodes definitions */
8045 GEN_SPE(efdadd
, efdsub
, 0x10, 0x0B, 0x00000000, PPC_SPE_DOUBLE
); //
8046 GEN_SPE(efdcfuid
, efdcfsid
, 0x11, 0x0B, 0x00180000, PPC_SPE_DOUBLE
); //
8047 GEN_SPE(efdabs
, efdnabs
, 0x12, 0x0B, 0x0000F800, PPC_SPE_DOUBLE
); //
8048 GEN_SPE(efdneg
, speundef
, 0x13, 0x0B, 0x0000F800, PPC_SPE_DOUBLE
); //
8049 GEN_SPE(efdmul
, efddiv
, 0x14, 0x0B, 0x00000000, PPC_SPE_DOUBLE
); //
8050 GEN_SPE(efdctuidz
, efdctsidz
, 0x15, 0x0B, 0x00180000, PPC_SPE_DOUBLE
); //
8051 GEN_SPE(efdcmpgt
, efdcmplt
, 0x16, 0x0B, 0x00600000, PPC_SPE_DOUBLE
); //
8052 GEN_SPE(efdcmpeq
, efdcfs
, 0x17, 0x0B, 0x00600000, PPC_SPE_DOUBLE
); //
8053 GEN_SPE(efdcfui
, efdcfsi
, 0x18, 0x0B, 0x00180000, PPC_SPE_DOUBLE
); //
8054 GEN_SPE(efdcfuf
, efdcfsf
, 0x19, 0x0B, 0x00180000, PPC_SPE_DOUBLE
); //
8055 GEN_SPE(efdctui
, efdctsi
, 0x1A, 0x0B, 0x00180000, PPC_SPE_DOUBLE
); //
8056 GEN_SPE(efdctuf
, efdctsf
, 0x1B, 0x0B, 0x00180000, PPC_SPE_DOUBLE
); //
8057 GEN_SPE(efdctuiz
, speundef
, 0x1C, 0x0B, 0x00180000, PPC_SPE_DOUBLE
); //
8058 GEN_SPE(efdctsiz
, speundef
, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE
); //
8059 GEN_SPE(efdtstgt
, efdtstlt
, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE
); //
8060 GEN_SPE(efdtsteq
, speundef
, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE
); //
8062 /* End opcode list */
8063 GEN_OPCODE_MARK(end
);
8065 #include "translate_init.c"
8066 #include "helper_regs.h"
8068 /*****************************************************************************/
8069 /* Misc PowerPC helpers */
8070 void cpu_dump_state (CPUState
*env
, FILE *f
,
8071 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
8079 cpu_fprintf(f
, "NIP " ADDRX
" LR " ADDRX
" CTR " ADDRX
" XER %08x\n",
8080 env
->nip
, env
->lr
, env
->ctr
, env
->xer
);
8081 cpu_fprintf(f
, "MSR " ADDRX
" HID0 " ADDRX
" HF " ADDRX
" idx %d\n",
8082 env
->msr
, env
->spr
[SPR_HID0
], env
->hflags
, env
->mmu_idx
);
8083 #if !defined(NO_TIMER_DUMP)
8084 cpu_fprintf(f
, "TB %08x %08x "
8085 #if !defined(CONFIG_USER_ONLY)
8089 cpu_ppc_load_tbu(env
), cpu_ppc_load_tbl(env
)
8090 #if !defined(CONFIG_USER_ONLY)
8091 , cpu_ppc_load_decr(env
)
8095 for (i
= 0; i
< 32; i
++) {
8096 if ((i
& (RGPL
- 1)) == 0)
8097 cpu_fprintf(f
, "GPR%02d", i
);
8098 cpu_fprintf(f
, " " REGX
, ppc_dump_gpr(env
, i
));
8099 if ((i
& (RGPL
- 1)) == (RGPL
- 1))
8100 cpu_fprintf(f
, "\n");
8102 cpu_fprintf(f
, "CR ");
8103 for (i
= 0; i
< 8; i
++)
8104 cpu_fprintf(f
, "%01x", env
->crf
[i
]);
8105 cpu_fprintf(f
, " [");
8106 for (i
= 0; i
< 8; i
++) {
8108 if (env
->crf
[i
] & 0x08)
8110 else if (env
->crf
[i
] & 0x04)
8112 else if (env
->crf
[i
] & 0x02)
8114 cpu_fprintf(f
, " %c%c", a
, env
->crf
[i
] & 0x01 ? 'O' : ' ');
8116 cpu_fprintf(f
, " ] RES " ADDRX
"\n", env
->reserve
);
8117 for (i
= 0; i
< 32; i
++) {
8118 if ((i
& (RFPL
- 1)) == 0)
8119 cpu_fprintf(f
, "FPR%02d", i
);
8120 cpu_fprintf(f
, " %016" PRIx64
, *((uint64_t *)&env
->fpr
[i
]));
8121 if ((i
& (RFPL
- 1)) == (RFPL
- 1))
8122 cpu_fprintf(f
, "\n");
8124 cpu_fprintf(f
, "FPSCR %08x\n", env
->fpscr
);
8125 #if !defined(CONFIG_USER_ONLY)
8126 cpu_fprintf(f
, "SRR0 " ADDRX
" SRR1 " ADDRX
" SDR1 " ADDRX
"\n",
8127 env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
], env
->sdr1
);
8134 void cpu_dump_statistics (CPUState
*env
, FILE*f
,
8135 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
8138 #if defined(DO_PPC_STATISTICS)
8139 opc_handler_t
**t1
, **t2
, **t3
, *handler
;
8143 for (op1
= 0; op1
< 64; op1
++) {
8145 if (is_indirect_opcode(handler
)) {
8146 t2
= ind_table(handler
);
8147 for (op2
= 0; op2
< 32; op2
++) {
8149 if (is_indirect_opcode(handler
)) {
8150 t3
= ind_table(handler
);
8151 for (op3
= 0; op3
< 32; op3
++) {
8153 if (handler
->count
== 0)
8155 cpu_fprintf(f
, "%02x %02x %02x (%02x %04d) %16s: "
8157 op1
, op2
, op3
, op1
, (op3
<< 5) | op2
,
8159 handler
->count
, handler
->count
);
8162 if (handler
->count
== 0)
8164 cpu_fprintf(f
, "%02x %02x (%02x %04d) %16s: "
8166 op1
, op2
, op1
, op2
, handler
->oname
,
8167 handler
->count
, handler
->count
);
8171 if (handler
->count
== 0)
8173 cpu_fprintf(f
, "%02x (%02x ) %16s: %016llx %lld\n",
8174 op1
, op1
, handler
->oname
,
8175 handler
->count
, handler
->count
);
8181 /*****************************************************************************/
8182 static always_inline
void gen_intermediate_code_internal (CPUState
*env
,
8183 TranslationBlock
*tb
,
8186 DisasContext ctx
, *ctxp
= &ctx
;
8187 opc_handler_t
**table
, *handler
;
8188 target_ulong pc_start
;
8189 uint16_t *gen_opc_end
;
8196 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
8199 ctx
.exception
= POWERPC_EXCP_NONE
;
8200 ctx
.spr_cb
= env
->spr_cb
;
8201 ctx
.mem_idx
= env
->mmu_idx
;
8202 ctx
.access_type
= -1;
8203 ctx
.le_mode
= env
->hflags
& (1 << MSR_LE
) ? 1 : 0;
8204 #if defined(TARGET_PPC64)
8205 ctx
.sf_mode
= msr_sf
;
8207 ctx
.fpu_enabled
= msr_fp
;
8208 if ((env
->flags
& POWERPC_FLAG_SPE
) && msr_spe
)
8209 ctx
.spe_enabled
= msr_spe
;
8211 ctx
.spe_enabled
= 0;
8212 if ((env
->flags
& POWERPC_FLAG_VRE
) && msr_vr
)
8213 ctx
.altivec_enabled
= msr_vr
;
8215 ctx
.altivec_enabled
= 0;
8216 if ((env
->flags
& POWERPC_FLAG_SE
) && msr_se
)
8217 ctx
.singlestep_enabled
= CPU_SINGLE_STEP
;
8219 ctx
.singlestep_enabled
= 0;
8220 if ((env
->flags
& POWERPC_FLAG_BE
) && msr_be
)
8221 ctx
.singlestep_enabled
|= CPU_BRANCH_STEP
;
8222 if (unlikely(env
->singlestep_enabled
))
8223 ctx
.singlestep_enabled
|= GDBSTUB_SINGLE_STEP
;
8224 #if defined (DO_SINGLE_STEP) && 0
8225 /* Single step trace mode */
8229 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
8231 max_insns
= CF_COUNT_MASK
;
8234 /* Set env in case of segfault during code fetch */
8235 while (ctx
.exception
== POWERPC_EXCP_NONE
&& gen_opc_ptr
< gen_opc_end
) {
8236 if (unlikely(!TAILQ_EMPTY(&env
->breakpoints
))) {
8237 TAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
8238 if (bp
->pc
== ctx
.nip
) {
8239 gen_debug_exception(ctxp
);
8244 if (unlikely(search_pc
)) {
8245 j
= gen_opc_ptr
- gen_opc_buf
;
8249 gen_opc_instr_start
[lj
++] = 0;
8250 gen_opc_pc
[lj
] = ctx
.nip
;
8251 gen_opc_instr_start
[lj
] = 1;
8252 gen_opc_icount
[lj
] = num_insns
;
8255 LOG_DISAS("----------------\n");
8256 LOG_DISAS("nip=" ADDRX
" super=%d ir=%d\n",
8257 ctx
.nip
, ctx
.mem_idx
, (int)msr_ir
);
8258 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
8260 if (unlikely(ctx
.le_mode
)) {
8261 ctx
.opcode
= bswap32(ldl_code(ctx
.nip
));
8263 ctx
.opcode
= ldl_code(ctx
.nip
);
8265 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
8266 ctx
.opcode
, opc1(ctx
.opcode
), opc2(ctx
.opcode
),
8267 opc3(ctx
.opcode
), little_endian
? "little" : "big");
8269 table
= env
->opcodes
;
8271 handler
= table
[opc1(ctx
.opcode
)];
8272 if (is_indirect_opcode(handler
)) {
8273 table
= ind_table(handler
);
8274 handler
= table
[opc2(ctx
.opcode
)];
8275 if (is_indirect_opcode(handler
)) {
8276 table
= ind_table(handler
);
8277 handler
= table
[opc3(ctx
.opcode
)];
8280 /* Is opcode *REALLY* valid ? */
8281 if (unlikely(handler
->handler
== &gen_invalid
)) {
8282 if (qemu_log_enabled()) {
8283 qemu_log("invalid/unsupported opcode: "
8284 "%02x - %02x - %02x (%08x) " ADDRX
" %d\n",
8285 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
8286 opc3(ctx
.opcode
), ctx
.opcode
, ctx
.nip
- 4, (int)msr_ir
);
8288 printf("invalid/unsupported opcode: "
8289 "%02x - %02x - %02x (%08x) " ADDRX
" %d\n",
8290 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
8291 opc3(ctx
.opcode
), ctx
.opcode
, ctx
.nip
- 4, (int)msr_ir
);
8294 if (unlikely((ctx
.opcode
& handler
->inval
) != 0)) {
8295 if (qemu_log_enabled()) {
8296 qemu_log("invalid bits: %08x for opcode: "
8297 "%02x - %02x - %02x (%08x) " ADDRX
"\n",
8298 ctx
.opcode
& handler
->inval
, opc1(ctx
.opcode
),
8299 opc2(ctx
.opcode
), opc3(ctx
.opcode
),
8300 ctx
.opcode
, ctx
.nip
- 4);
8302 printf("invalid bits: %08x for opcode: "
8303 "%02x - %02x - %02x (%08x) " ADDRX
"\n",
8304 ctx
.opcode
& handler
->inval
, opc1(ctx
.opcode
),
8305 opc2(ctx
.opcode
), opc3(ctx
.opcode
),
8306 ctx
.opcode
, ctx
.nip
- 4);
8308 gen_inval_exception(ctxp
, POWERPC_EXCP_INVAL_INVAL
);
8312 (*(handler
->handler
))(&ctx
);
8313 #if defined(DO_PPC_STATISTICS)
8316 /* Check trace mode exceptions */
8317 if (unlikely(ctx
.singlestep_enabled
& CPU_SINGLE_STEP
&&
8318 (ctx
.nip
<= 0x100 || ctx
.nip
> 0xF00) &&
8319 ctx
.exception
!= POWERPC_SYSCALL
&&
8320 ctx
.exception
!= POWERPC_EXCP_TRAP
&&
8321 ctx
.exception
!= POWERPC_EXCP_BRANCH
)) {
8322 gen_exception(ctxp
, POWERPC_EXCP_TRACE
);
8323 } else if (unlikely(((ctx
.nip
& (TARGET_PAGE_SIZE
- 1)) == 0) ||
8324 (env
->singlestep_enabled
) ||
8325 num_insns
>= max_insns
)) {
8326 /* if we reach a page boundary or are single stepping, stop
8331 #if defined (DO_SINGLE_STEP)
8335 if (tb
->cflags
& CF_LAST_IO
)
8337 if (ctx
.exception
== POWERPC_EXCP_NONE
) {
8338 gen_goto_tb(&ctx
, 0, ctx
.nip
);
8339 } else if (ctx
.exception
!= POWERPC_EXCP_BRANCH
) {
8340 if (unlikely(env
->singlestep_enabled
)) {
8341 gen_debug_exception(ctxp
);
8343 /* Generate the return instruction */
8346 gen_icount_end(tb
, num_insns
);
8347 *gen_opc_ptr
= INDEX_op_end
;
8348 if (unlikely(search_pc
)) {
8349 j
= gen_opc_ptr
- gen_opc_buf
;
8352 gen_opc_instr_start
[lj
++] = 0;
8354 tb
->size
= ctx
.nip
- pc_start
;
8355 tb
->icount
= num_insns
;
8357 #if defined(DEBUG_DISAS)
8358 qemu_log_mask(CPU_LOG_TB_CPU
, "---------------- excp: %04x\n", ctx
.exception
);
8359 log_cpu_state_mask(CPU_LOG_TB_CPU
, env
, 0);
8360 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
8362 flags
= env
->bfd_mach
;
8363 flags
|= ctx
.le_mode
<< 16;
8364 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
8365 log_target_disas(pc_start
, ctx
.nip
- pc_start
, flags
);
8371 void gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
8373 gen_intermediate_code_internal(env
, tb
, 0);
8376 void gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
8378 gen_intermediate_code_internal(env
, tb
, 1);
8381 void gen_pc_load(CPUState
*env
, TranslationBlock
*tb
,
8382 unsigned long searched_pc
, int pc_pos
, void *puc
)
8384 env
->nip
= gen_opc_pc
[pc_pos
];