2 * PowerPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
26 #include "qemu/host-utils.h"
27 #include "exec/cpu_ldst.h"
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
32 #include "trace-tcg.h"
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
40 /* Include definitions for instructions classes and implementations flags */
41 //#define PPC_DEBUG_DISAS
42 //#define DO_PPC_STATISTICS
44 #ifdef PPC_DEBUG_DISAS
45 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
47 # define LOG_DISAS(...) do { } while (0)
49 /*****************************************************************************/
50 /* Code translation helpers */
52 /* global register indexes */
53 static TCGv_env cpu_env
;
54 static char cpu_reg_names
[10*3 + 22*4 /* GPR */
55 + 10*4 + 22*5 /* SPE GPRh */
56 + 10*4 + 22*5 /* FPR */
57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
58 + 10*5 + 22*6 /* VSR */
60 static TCGv cpu_gpr
[32];
61 static TCGv cpu_gprh
[32];
62 static TCGv_i64 cpu_fpr
[32];
63 static TCGv_i64 cpu_avrh
[32], cpu_avrl
[32];
64 static TCGv_i64 cpu_vsr
[32];
65 static TCGv_i32 cpu_crf
[8];
70 #if defined(TARGET_PPC64)
73 static TCGv cpu_xer
, cpu_so
, cpu_ov
, cpu_ca
;
74 static TCGv cpu_reserve
;
75 static TCGv cpu_fpscr
;
76 static TCGv_i32 cpu_access_type
;
78 #include "exec/gen-icount.h"
80 void ppc_translate_init(void)
84 size_t cpu_reg_names_size
;
85 static int done_init
= 0;
90 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
91 tcg_ctx
.tcg_env
= cpu_env
;
94 cpu_reg_names_size
= sizeof(cpu_reg_names
);
96 for (i
= 0; i
< 8; i
++) {
97 snprintf(p
, cpu_reg_names_size
, "crf%d", i
);
98 cpu_crf
[i
] = tcg_global_mem_new_i32(cpu_env
,
99 offsetof(CPUPPCState
, crf
[i
]), p
);
101 cpu_reg_names_size
-= 5;
104 for (i
= 0; i
< 32; i
++) {
105 snprintf(p
, cpu_reg_names_size
, "r%d", i
);
106 cpu_gpr
[i
] = tcg_global_mem_new(cpu_env
,
107 offsetof(CPUPPCState
, gpr
[i
]), p
);
108 p
+= (i
< 10) ? 3 : 4;
109 cpu_reg_names_size
-= (i
< 10) ? 3 : 4;
110 snprintf(p
, cpu_reg_names_size
, "r%dH", i
);
111 cpu_gprh
[i
] = tcg_global_mem_new(cpu_env
,
112 offsetof(CPUPPCState
, gprh
[i
]), p
);
113 p
+= (i
< 10) ? 4 : 5;
114 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
116 snprintf(p
, cpu_reg_names_size
, "fp%d", i
);
117 cpu_fpr
[i
] = tcg_global_mem_new_i64(cpu_env
,
118 offsetof(CPUPPCState
, fpr
[i
]), p
);
119 p
+= (i
< 10) ? 4 : 5;
120 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
122 snprintf(p
, cpu_reg_names_size
, "avr%dH", i
);
123 #ifdef HOST_WORDS_BIGENDIAN
124 cpu_avrh
[i
] = tcg_global_mem_new_i64(cpu_env
,
125 offsetof(CPUPPCState
, avr
[i
].u64
[0]), p
);
127 cpu_avrh
[i
] = tcg_global_mem_new_i64(cpu_env
,
128 offsetof(CPUPPCState
, avr
[i
].u64
[1]), p
);
130 p
+= (i
< 10) ? 6 : 7;
131 cpu_reg_names_size
-= (i
< 10) ? 6 : 7;
133 snprintf(p
, cpu_reg_names_size
, "avr%dL", i
);
134 #ifdef HOST_WORDS_BIGENDIAN
135 cpu_avrl
[i
] = tcg_global_mem_new_i64(cpu_env
,
136 offsetof(CPUPPCState
, avr
[i
].u64
[1]), p
);
138 cpu_avrl
[i
] = tcg_global_mem_new_i64(cpu_env
,
139 offsetof(CPUPPCState
, avr
[i
].u64
[0]), p
);
141 p
+= (i
< 10) ? 6 : 7;
142 cpu_reg_names_size
-= (i
< 10) ? 6 : 7;
143 snprintf(p
, cpu_reg_names_size
, "vsr%d", i
);
144 cpu_vsr
[i
] = tcg_global_mem_new_i64(cpu_env
,
145 offsetof(CPUPPCState
, vsr
[i
]), p
);
146 p
+= (i
< 10) ? 5 : 6;
147 cpu_reg_names_size
-= (i
< 10) ? 5 : 6;
150 cpu_nip
= tcg_global_mem_new(cpu_env
,
151 offsetof(CPUPPCState
, nip
), "nip");
153 cpu_msr
= tcg_global_mem_new(cpu_env
,
154 offsetof(CPUPPCState
, msr
), "msr");
156 cpu_ctr
= tcg_global_mem_new(cpu_env
,
157 offsetof(CPUPPCState
, ctr
), "ctr");
159 cpu_lr
= tcg_global_mem_new(cpu_env
,
160 offsetof(CPUPPCState
, lr
), "lr");
162 #if defined(TARGET_PPC64)
163 cpu_cfar
= tcg_global_mem_new(cpu_env
,
164 offsetof(CPUPPCState
, cfar
), "cfar");
167 cpu_xer
= tcg_global_mem_new(cpu_env
,
168 offsetof(CPUPPCState
, xer
), "xer");
169 cpu_so
= tcg_global_mem_new(cpu_env
,
170 offsetof(CPUPPCState
, so
), "SO");
171 cpu_ov
= tcg_global_mem_new(cpu_env
,
172 offsetof(CPUPPCState
, ov
), "OV");
173 cpu_ca
= tcg_global_mem_new(cpu_env
,
174 offsetof(CPUPPCState
, ca
), "CA");
176 cpu_reserve
= tcg_global_mem_new(cpu_env
,
177 offsetof(CPUPPCState
, reserve_addr
),
180 cpu_fpscr
= tcg_global_mem_new(cpu_env
,
181 offsetof(CPUPPCState
, fpscr
), "fpscr");
183 cpu_access_type
= tcg_global_mem_new_i32(cpu_env
,
184 offsetof(CPUPPCState
, access_type
), "access_type");
189 /* internal defines */
190 struct DisasContext
{
191 struct TranslationBlock
*tb
;
195 /* Routine used to access memory */
196 bool pr
, hv
, dr
, le_mode
;
200 /* Translation flags */
201 TCGMemOp default_tcg_memop_mask
;
202 #if defined(TARGET_PPC64)
207 bool altivec_enabled
;
211 ppc_spr_t
*spr_cb
; /* Needed to check rights for mfspr/mtspr */
212 int singlestep_enabled
;
213 uint64_t insns_flags
;
214 uint64_t insns_flags2
;
217 /* Return true iff byteswap is needed in a scalar memop */
218 static inline bool need_byteswap(const DisasContext
*ctx
)
220 #if defined(TARGET_WORDS_BIGENDIAN)
223 return !ctx
->le_mode
;
227 /* True when active word size < size of target_long. */
229 # define NARROW_MODE(C) (!(C)->sf_mode)
231 # define NARROW_MODE(C) 0
234 struct opc_handler_t
{
235 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
237 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
239 /* instruction type */
241 /* extended instruction type */
244 void (*handler
)(DisasContext
*ctx
);
245 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
248 #if defined(DO_PPC_STATISTICS)
253 static inline void gen_set_access_type(DisasContext
*ctx
, int access_type
)
255 if (ctx
->access_type
!= access_type
) {
256 tcg_gen_movi_i32(cpu_access_type
, access_type
);
257 ctx
->access_type
= access_type
;
261 static inline void gen_update_nip(DisasContext
*ctx
, target_ulong nip
)
263 if (NARROW_MODE(ctx
)) {
266 tcg_gen_movi_tl(cpu_nip
, nip
);
269 void gen_update_current_nip(void *opaque
)
271 DisasContext
*ctx
= opaque
;
273 tcg_gen_movi_tl(cpu_nip
, ctx
->nip
);
276 static void gen_exception_err(DisasContext
*ctx
, uint32_t excp
, uint32_t error
)
279 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
280 gen_update_nip(ctx
, ctx
->nip
);
282 t0
= tcg_const_i32(excp
);
283 t1
= tcg_const_i32(error
);
284 gen_helper_raise_exception_err(cpu_env
, t0
, t1
);
285 tcg_temp_free_i32(t0
);
286 tcg_temp_free_i32(t1
);
287 ctx
->exception
= (excp
);
290 static void gen_exception(DisasContext
*ctx
, uint32_t excp
)
293 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
294 gen_update_nip(ctx
, ctx
->nip
);
296 t0
= tcg_const_i32(excp
);
297 gen_helper_raise_exception(cpu_env
, t0
);
298 tcg_temp_free_i32(t0
);
299 ctx
->exception
= (excp
);
302 static void gen_debug_exception(DisasContext
*ctx
)
306 if ((ctx
->exception
!= POWERPC_EXCP_BRANCH
) &&
307 (ctx
->exception
!= POWERPC_EXCP_SYNC
)) {
308 gen_update_nip(ctx
, ctx
->nip
);
310 t0
= tcg_const_i32(EXCP_DEBUG
);
311 gen_helper_raise_exception(cpu_env
, t0
);
312 tcg_temp_free_i32(t0
);
315 static inline void gen_inval_exception(DisasContext
*ctx
, uint32_t error
)
317 /* Will be converted to program check if needed */
318 gen_exception_err(ctx
, POWERPC_EXCP_HV_EMU
, POWERPC_EXCP_INVAL
| error
);
321 static inline void gen_priv_exception(DisasContext
*ctx
, uint32_t error
)
323 gen_exception_err(ctx
, POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_PRIV
| error
);
326 static inline void gen_hvpriv_exception(DisasContext
*ctx
, uint32_t error
)
328 /* Will be converted to program check if needed */
329 gen_exception_err(ctx
, POWERPC_EXCP_HV_EMU
, POWERPC_EXCP_PRIV
| error
);
332 /* Stop translation */
333 static inline void gen_stop_exception(DisasContext
*ctx
)
335 gen_update_nip(ctx
, ctx
->nip
);
336 ctx
->exception
= POWERPC_EXCP_STOP
;
339 #ifndef CONFIG_USER_ONLY
340 /* No need to update nip here, as execution flow will change */
341 static inline void gen_sync_exception(DisasContext
*ctx
)
343 ctx
->exception
= POWERPC_EXCP_SYNC
;
347 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
348 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
350 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
351 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
353 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
354 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
356 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
357 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
359 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
360 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
362 typedef struct opcode_t
{
363 unsigned char opc1
, opc2
, opc3
, opc4
;
364 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
365 unsigned char pad
[4];
367 opc_handler_t handler
;
371 /* Helpers for priv. check */
374 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
377 #if defined(CONFIG_USER_ONLY)
378 #define CHK_HV GEN_PRIV
379 #define CHK_SV GEN_PRIV
380 #define CHK_HVRM GEN_PRIV
384 if (unlikely(ctx->pr || !ctx->hv)) { \
390 if (unlikely(ctx->pr)) { \
396 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
405 /*****************************************************************************/
406 /*** Instruction decoding ***/
407 #define EXTRACT_HELPER(name, shift, nb) \
408 static inline uint32_t name(uint32_t opcode) \
410 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
413 #define EXTRACT_SHELPER(name, shift, nb) \
414 static inline int32_t name(uint32_t opcode) \
416 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
419 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
420 static inline uint32_t name(uint32_t opcode) \
422 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
423 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
426 #define EXTRACT_HELPER_DXFORM(name, \
427 d0_bits, shift_op_d0, shift_d0, \
428 d1_bits, shift_op_d1, shift_d1, \
429 d2_bits, shift_op_d2, shift_d2) \
430 static inline int16_t name(uint32_t opcode) \
433 (((opcode >> (shift_op_d0)) & ((1 << (d0_bits)) - 1)) << (shift_d0)) | \
434 (((opcode >> (shift_op_d1)) & ((1 << (d1_bits)) - 1)) << (shift_d1)) | \
435 (((opcode >> (shift_op_d2)) & ((1 << (d2_bits)) - 1)) << (shift_d2)); \
440 EXTRACT_HELPER(opc1
, 26, 6);
442 EXTRACT_HELPER(opc2
, 1, 5);
444 EXTRACT_HELPER(opc3
, 6, 5);
446 EXTRACT_HELPER(opc4
, 16, 5);
447 /* Update Cr0 flags */
448 EXTRACT_HELPER(Rc
, 0, 1);
449 /* Update Cr6 flags (Altivec) */
450 EXTRACT_HELPER(Rc21
, 10, 1);
452 EXTRACT_HELPER(rD
, 21, 5);
454 EXTRACT_HELPER(rS
, 21, 5);
456 EXTRACT_HELPER(rA
, 16, 5);
458 EXTRACT_HELPER(rB
, 11, 5);
460 EXTRACT_HELPER(rC
, 6, 5);
462 EXTRACT_HELPER(crfD
, 23, 3);
463 EXTRACT_HELPER(crfS
, 18, 3);
464 EXTRACT_HELPER(crbD
, 21, 5);
465 EXTRACT_HELPER(crbA
, 16, 5);
466 EXTRACT_HELPER(crbB
, 11, 5);
468 EXTRACT_HELPER(_SPR
, 11, 10);
469 static inline uint32_t SPR(uint32_t opcode
)
471 uint32_t sprn
= _SPR(opcode
);
473 return ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
475 /*** Get constants ***/
476 /* 16 bits signed immediate value */
477 EXTRACT_SHELPER(SIMM
, 0, 16);
478 /* 16 bits unsigned immediate value */
479 EXTRACT_HELPER(UIMM
, 0, 16);
480 /* 5 bits signed immediate value */
481 EXTRACT_HELPER(SIMM5
, 16, 5);
482 /* 5 bits signed immediate value */
483 EXTRACT_HELPER(UIMM5
, 16, 5);
485 EXTRACT_HELPER(NB
, 11, 5);
487 EXTRACT_HELPER(SH
, 11, 5);
488 /* Vector shift count */
489 EXTRACT_HELPER(VSH
, 6, 4);
491 EXTRACT_HELPER(MB
, 6, 5);
493 EXTRACT_HELPER(ME
, 1, 5);
495 EXTRACT_HELPER(TO
, 21, 5);
497 EXTRACT_HELPER(CRM
, 12, 8);
499 #ifndef CONFIG_USER_ONLY
500 EXTRACT_HELPER(SR
, 16, 4);
504 EXTRACT_HELPER(FPBF
, 23, 3);
505 EXTRACT_HELPER(FPIMM
, 12, 4);
506 EXTRACT_HELPER(FPL
, 25, 1);
507 EXTRACT_HELPER(FPFLM
, 17, 8);
508 EXTRACT_HELPER(FPW
, 16, 1);
511 EXTRACT_HELPER_DXFORM(DX
, 10, 6, 6, 5, 16, 1, 1, 0, 0)
513 /*** Jump target decoding ***/
514 /* Immediate address */
515 static inline target_ulong
LI(uint32_t opcode
)
517 return (opcode
>> 0) & 0x03FFFFFC;
520 static inline uint32_t BD(uint32_t opcode
)
522 return (opcode
>> 0) & 0xFFFC;
525 EXTRACT_HELPER(BO
, 21, 5);
526 EXTRACT_HELPER(BI
, 16, 5);
527 /* Absolute/relative address */
528 EXTRACT_HELPER(AA
, 1, 1);
530 EXTRACT_HELPER(LK
, 0, 1);
533 EXTRACT_HELPER(DCM
, 10, 6)
536 EXTRACT_HELPER(RMC
, 9, 2)
538 /* Create a mask between <start> and <end> bits */
539 static inline target_ulong
MASK(uint32_t start
, uint32_t end
)
543 #if defined(TARGET_PPC64)
544 if (likely(start
== 0)) {
545 ret
= UINT64_MAX
<< (63 - end
);
546 } else if (likely(end
== 63)) {
547 ret
= UINT64_MAX
>> start
;
550 if (likely(start
== 0)) {
551 ret
= UINT32_MAX
<< (31 - end
);
552 } else if (likely(end
== 31)) {
553 ret
= UINT32_MAX
>> start
;
557 ret
= (((target_ulong
)(-1ULL)) >> (start
)) ^
558 (((target_ulong
)(-1ULL) >> (end
)) >> 1);
559 if (unlikely(start
> end
))
566 EXTRACT_HELPER_SPLIT(xT
, 0, 1, 21, 5);
567 EXTRACT_HELPER_SPLIT(xS
, 0, 1, 21, 5);
568 EXTRACT_HELPER_SPLIT(xA
, 2, 1, 16, 5);
569 EXTRACT_HELPER_SPLIT(xB
, 1, 1, 11, 5);
570 EXTRACT_HELPER_SPLIT(xC
, 3, 1, 6, 5);
571 EXTRACT_HELPER(DM
, 8, 2);
572 EXTRACT_HELPER(UIM
, 16, 2);
573 EXTRACT_HELPER(SHW
, 8, 2);
574 EXTRACT_HELPER(SP
, 19, 2);
575 /*****************************************************************************/
576 /* PowerPC instructions table */
578 #if defined(DO_PPC_STATISTICS)
579 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
589 .handler = &gen_##name, \
590 .oname = stringify(name), \
592 .oname = stringify(name), \
594 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
605 .handler = &gen_##name, \
606 .oname = stringify(name), \
608 .oname = stringify(name), \
610 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
620 .handler = &gen_##name, \
625 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
635 .handler = &gen_##name, \
636 .oname = stringify(name), \
638 .oname = stringify(name), \
641 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
651 .handler = &gen_##name, \
653 .oname = stringify(name), \
655 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
666 .handler = &gen_##name, \
668 .oname = stringify(name), \
670 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
680 .handler = &gen_##name, \
684 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
694 .handler = &gen_##name, \
696 .oname = stringify(name), \
700 /* SPR load/store helpers */
701 static inline void gen_load_spr(TCGv t
, int reg
)
703 tcg_gen_ld_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
706 static inline void gen_store_spr(int reg
, TCGv t
)
708 tcg_gen_st_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
711 /* Invalid instruction */
712 static void gen_invalid(DisasContext
*ctx
)
714 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
717 static opc_handler_t invalid_handler
= {
718 .inval1
= 0xFFFFFFFF,
719 .inval2
= 0xFFFFFFFF,
722 .handler
= gen_invalid
,
725 /*** Integer comparison ***/
727 static inline void gen_op_cmp(TCGv arg0
, TCGv arg1
, int s
, int crf
)
729 TCGv t0
= tcg_temp_new();
730 TCGv_i32 t1
= tcg_temp_new_i32();
732 tcg_gen_trunc_tl_i32(cpu_crf
[crf
], cpu_so
);
734 tcg_gen_setcond_tl((s
? TCG_COND_LT
: TCG_COND_LTU
), t0
, arg0
, arg1
);
735 tcg_gen_trunc_tl_i32(t1
, t0
);
736 tcg_gen_shli_i32(t1
, t1
, CRF_LT
);
737 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
739 tcg_gen_setcond_tl((s
? TCG_COND_GT
: TCG_COND_GTU
), t0
, arg0
, arg1
);
740 tcg_gen_trunc_tl_i32(t1
, t0
);
741 tcg_gen_shli_i32(t1
, t1
, CRF_GT
);
742 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
744 tcg_gen_setcond_tl(TCG_COND_EQ
, t0
, arg0
, arg1
);
745 tcg_gen_trunc_tl_i32(t1
, t0
);
746 tcg_gen_shli_i32(t1
, t1
, CRF_EQ
);
747 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
750 tcg_temp_free_i32(t1
);
753 static inline void gen_op_cmpi(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
755 TCGv t0
= tcg_const_tl(arg1
);
756 gen_op_cmp(arg0
, t0
, s
, crf
);
760 static inline void gen_op_cmp32(TCGv arg0
, TCGv arg1
, int s
, int crf
)
766 tcg_gen_ext32s_tl(t0
, arg0
);
767 tcg_gen_ext32s_tl(t1
, arg1
);
769 tcg_gen_ext32u_tl(t0
, arg0
);
770 tcg_gen_ext32u_tl(t1
, arg1
);
772 gen_op_cmp(t0
, t1
, s
, crf
);
777 static inline void gen_op_cmpi32(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
779 TCGv t0
= tcg_const_tl(arg1
);
780 gen_op_cmp32(arg0
, t0
, s
, crf
);
784 static inline void gen_set_Rc0(DisasContext
*ctx
, TCGv reg
)
786 if (NARROW_MODE(ctx
)) {
787 gen_op_cmpi32(reg
, 0, 1, 0);
789 gen_op_cmpi(reg
, 0, 1, 0);
794 static void gen_cmp(DisasContext
*ctx
)
796 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
797 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
798 1, crfD(ctx
->opcode
));
800 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
801 1, crfD(ctx
->opcode
));
806 static void gen_cmpi(DisasContext
*ctx
)
808 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
809 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
810 1, crfD(ctx
->opcode
));
812 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
813 1, crfD(ctx
->opcode
));
818 static void gen_cmpl(DisasContext
*ctx
)
820 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
821 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
822 0, crfD(ctx
->opcode
));
824 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
825 0, crfD(ctx
->opcode
));
830 static void gen_cmpli(DisasContext
*ctx
)
832 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
833 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
834 0, crfD(ctx
->opcode
));
836 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
837 0, crfD(ctx
->opcode
));
841 /* cmprb - range comparison: isupper, isaplha, islower*/
842 static void gen_cmprb(DisasContext
*ctx
)
844 TCGv_i32 src1
= tcg_temp_new_i32();
845 TCGv_i32 src2
= tcg_temp_new_i32();
846 TCGv_i32 src2lo
= tcg_temp_new_i32();
847 TCGv_i32 src2hi
= tcg_temp_new_i32();
848 TCGv_i32 crf
= cpu_crf
[crfD(ctx
->opcode
)];
850 tcg_gen_trunc_tl_i32(src1
, cpu_gpr
[rA(ctx
->opcode
)]);
851 tcg_gen_trunc_tl_i32(src2
, cpu_gpr
[rB(ctx
->opcode
)]);
853 tcg_gen_andi_i32(src1
, src1
, 0xFF);
854 tcg_gen_ext8u_i32(src2lo
, src2
);
855 tcg_gen_shri_i32(src2
, src2
, 8);
856 tcg_gen_ext8u_i32(src2hi
, src2
);
858 tcg_gen_setcond_i32(TCG_COND_LEU
, src2lo
, src2lo
, src1
);
859 tcg_gen_setcond_i32(TCG_COND_LEU
, src2hi
, src1
, src2hi
);
860 tcg_gen_and_i32(crf
, src2lo
, src2hi
);
862 if (ctx
->opcode
& 0x00200000) {
863 tcg_gen_shri_i32(src2
, src2
, 8);
864 tcg_gen_ext8u_i32(src2lo
, src2
);
865 tcg_gen_shri_i32(src2
, src2
, 8);
866 tcg_gen_ext8u_i32(src2hi
, src2
);
867 tcg_gen_setcond_i32(TCG_COND_LEU
, src2lo
, src2lo
, src1
);
868 tcg_gen_setcond_i32(TCG_COND_LEU
, src2hi
, src1
, src2hi
);
869 tcg_gen_and_i32(src2lo
, src2lo
, src2hi
);
870 tcg_gen_or_i32(crf
, crf
, src2lo
);
872 tcg_gen_shli_i32(crf
, crf
, CRF_GT
);
873 tcg_temp_free_i32(src1
);
874 tcg_temp_free_i32(src2
);
875 tcg_temp_free_i32(src2lo
);
876 tcg_temp_free_i32(src2hi
);
879 #if defined(TARGET_PPC64)
881 static void gen_cmpeqb(DisasContext
*ctx
)
883 gen_helper_cmpeqb(cpu_crf
[crfD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
884 cpu_gpr
[rB(ctx
->opcode
)]);
888 /* isel (PowerPC 2.03 specification) */
889 static void gen_isel(DisasContext
*ctx
)
891 uint32_t bi
= rC(ctx
->opcode
);
892 uint32_t mask
= 0x08 >> (bi
& 0x03);
893 TCGv t0
= tcg_temp_new();
896 tcg_gen_extu_i32_tl(t0
, cpu_crf
[bi
>> 2]);
897 tcg_gen_andi_tl(t0
, t0
, mask
);
899 zr
= tcg_const_tl(0);
900 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_gpr
[rD(ctx
->opcode
)], t0
, zr
,
901 rA(ctx
->opcode
) ? cpu_gpr
[rA(ctx
->opcode
)] : zr
,
902 cpu_gpr
[rB(ctx
->opcode
)]);
907 /* cmpb: PowerPC 2.05 specification */
908 static void gen_cmpb(DisasContext
*ctx
)
910 gen_helper_cmpb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
911 cpu_gpr
[rB(ctx
->opcode
)]);
914 /*** Integer arithmetic ***/
916 static inline void gen_op_arith_compute_ov(DisasContext
*ctx
, TCGv arg0
,
917 TCGv arg1
, TCGv arg2
, int sub
)
919 TCGv t0
= tcg_temp_new();
921 tcg_gen_xor_tl(cpu_ov
, arg0
, arg2
);
922 tcg_gen_xor_tl(t0
, arg1
, arg2
);
924 tcg_gen_and_tl(cpu_ov
, cpu_ov
, t0
);
926 tcg_gen_andc_tl(cpu_ov
, cpu_ov
, t0
);
929 if (NARROW_MODE(ctx
)) {
930 tcg_gen_ext32s_tl(cpu_ov
, cpu_ov
);
932 tcg_gen_shri_tl(cpu_ov
, cpu_ov
, TARGET_LONG_BITS
- 1);
933 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
936 /* Common add function */
937 static inline void gen_op_arith_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
938 TCGv arg2
, bool add_ca
, bool compute_ca
,
939 bool compute_ov
, bool compute_rc0
)
943 if (compute_ca
|| compute_ov
) {
948 if (NARROW_MODE(ctx
)) {
949 /* Caution: a non-obvious corner case of the spec is that we
950 must produce the *entire* 64-bit addition, but produce the
951 carry into bit 32. */
952 TCGv t1
= tcg_temp_new();
953 tcg_gen_xor_tl(t1
, arg1
, arg2
); /* add without carry */
954 tcg_gen_add_tl(t0
, arg1
, arg2
);
956 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
958 tcg_gen_xor_tl(cpu_ca
, t0
, t1
); /* bits changed w/ carry */
960 tcg_gen_shri_tl(cpu_ca
, cpu_ca
, 32); /* extract bit 32 */
961 tcg_gen_andi_tl(cpu_ca
, cpu_ca
, 1);
963 TCGv zero
= tcg_const_tl(0);
965 tcg_gen_add2_tl(t0
, cpu_ca
, arg1
, zero
, cpu_ca
, zero
);
966 tcg_gen_add2_tl(t0
, cpu_ca
, t0
, cpu_ca
, arg2
, zero
);
968 tcg_gen_add2_tl(t0
, cpu_ca
, arg1
, zero
, arg2
, zero
);
973 tcg_gen_add_tl(t0
, arg1
, arg2
);
975 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
980 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 0);
982 if (unlikely(compute_rc0
)) {
983 gen_set_Rc0(ctx
, t0
);
986 if (!TCGV_EQUAL(t0
, ret
)) {
987 tcg_gen_mov_tl(ret
, t0
);
991 /* Add functions with two operands */
992 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
993 static void glue(gen_, name)(DisasContext *ctx) \
995 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
996 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
997 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
999 /* Add functions with one operand and one immediate */
1000 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
1001 add_ca, compute_ca, compute_ov) \
1002 static void glue(gen_, name)(DisasContext *ctx) \
1004 TCGv t0 = tcg_const_tl(const_val); \
1005 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1006 cpu_gpr[rA(ctx->opcode)], t0, \
1007 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1008 tcg_temp_free(t0); \
1011 /* add add. addo addo. */
1012 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
1013 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
1014 /* addc addc. addco addco. */
1015 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
1016 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
1017 /* adde adde. addeo addeo. */
1018 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
1019 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
1020 /* addme addme. addmeo addmeo. */
1021 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
1022 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
1023 /* addze addze. addzeo addzeo.*/
1024 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
1025 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
1027 static void gen_addi(DisasContext
*ctx
)
1029 target_long simm
= SIMM(ctx
->opcode
);
1031 if (rA(ctx
->opcode
) == 0) {
1033 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
);
1035 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)],
1036 cpu_gpr
[rA(ctx
->opcode
)], simm
);
1040 static inline void gen_op_addic(DisasContext
*ctx
, bool compute_rc0
)
1042 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
1043 gen_op_arith_add(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1044 c
, 0, 1, 0, compute_rc0
);
1048 static void gen_addic(DisasContext
*ctx
)
1050 gen_op_addic(ctx
, 0);
1053 static void gen_addic_(DisasContext
*ctx
)
1055 gen_op_addic(ctx
, 1);
1059 static void gen_addis(DisasContext
*ctx
)
1061 target_long simm
= SIMM(ctx
->opcode
);
1063 if (rA(ctx
->opcode
) == 0) {
1065 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
<< 16);
1067 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)],
1068 cpu_gpr
[rA(ctx
->opcode
)], simm
<< 16);
1073 static void gen_addpcis(DisasContext
*ctx
)
1075 target_long d
= DX(ctx
->opcode
);
1077 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], ctx
->nip
+ (d
<< 16));
1080 static inline void gen_op_arith_divw(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1081 TCGv arg2
, int sign
, int compute_ov
)
1083 TCGLabel
*l1
= gen_new_label();
1084 TCGLabel
*l2
= gen_new_label();
1085 TCGv_i32 t0
= tcg_temp_local_new_i32();
1086 TCGv_i32 t1
= tcg_temp_local_new_i32();
1088 tcg_gen_trunc_tl_i32(t0
, arg1
);
1089 tcg_gen_trunc_tl_i32(t1
, arg2
);
1090 tcg_gen_brcondi_i32(TCG_COND_EQ
, t1
, 0, l1
);
1092 TCGLabel
*l3
= gen_new_label();
1093 tcg_gen_brcondi_i32(TCG_COND_NE
, t1
, -1, l3
);
1094 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, INT32_MIN
, l1
);
1096 tcg_gen_div_i32(t0
, t0
, t1
);
1098 tcg_gen_divu_i32(t0
, t0
, t1
);
1101 tcg_gen_movi_tl(cpu_ov
, 0);
1106 tcg_gen_sari_i32(t0
, t0
, 31);
1108 tcg_gen_movi_i32(t0
, 0);
1111 tcg_gen_movi_tl(cpu_ov
, 1);
1112 tcg_gen_movi_tl(cpu_so
, 1);
1115 tcg_gen_extu_i32_tl(ret
, t0
);
1116 tcg_temp_free_i32(t0
);
1117 tcg_temp_free_i32(t1
);
1118 if (unlikely(Rc(ctx
->opcode
) != 0))
1119 gen_set_Rc0(ctx
, ret
);
1122 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1123 static void glue(gen_, name)(DisasContext *ctx) \
1125 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1126 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1127 sign, compute_ov); \
1129 /* divwu divwu. divwuo divwuo. */
1130 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0);
1131 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1);
1132 /* divw divw. divwo divwo. */
1133 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0);
1134 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1);
1136 /* div[wd]eu[o][.] */
1137 #define GEN_DIVE(name, hlpr, compute_ov) \
1138 static void gen_##name(DisasContext *ctx) \
1140 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1141 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1142 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1143 tcg_temp_free_i32(t0); \
1144 if (unlikely(Rc(ctx->opcode) != 0)) { \
1145 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1149 GEN_DIVE(divweu
, divweu
, 0);
1150 GEN_DIVE(divweuo
, divweu
, 1);
1151 GEN_DIVE(divwe
, divwe
, 0);
1152 GEN_DIVE(divweo
, divwe
, 1);
1154 #if defined(TARGET_PPC64)
1155 static inline void gen_op_arith_divd(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1156 TCGv arg2
, int sign
, int compute_ov
)
1158 TCGLabel
*l1
= gen_new_label();
1159 TCGLabel
*l2
= gen_new_label();
1161 tcg_gen_brcondi_i64(TCG_COND_EQ
, arg2
, 0, l1
);
1163 TCGLabel
*l3
= gen_new_label();
1164 tcg_gen_brcondi_i64(TCG_COND_NE
, arg2
, -1, l3
);
1165 tcg_gen_brcondi_i64(TCG_COND_EQ
, arg1
, INT64_MIN
, l1
);
1167 tcg_gen_div_i64(ret
, arg1
, arg2
);
1169 tcg_gen_divu_i64(ret
, arg1
, arg2
);
1172 tcg_gen_movi_tl(cpu_ov
, 0);
1177 tcg_gen_sari_i64(ret
, arg1
, 63);
1179 tcg_gen_movi_i64(ret
, 0);
1182 tcg_gen_movi_tl(cpu_ov
, 1);
1183 tcg_gen_movi_tl(cpu_so
, 1);
1186 if (unlikely(Rc(ctx
->opcode
) != 0))
1187 gen_set_Rc0(ctx
, ret
);
1189 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1190 static void glue(gen_, name)(DisasContext *ctx) \
1192 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1193 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1194 sign, compute_ov); \
1196 /* divwu divwu. divwuo divwuo. */
1197 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0);
1198 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1);
1199 /* divw divw. divwo divwo. */
1200 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0);
1201 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1);
1203 GEN_DIVE(divdeu
, divdeu
, 0);
1204 GEN_DIVE(divdeuo
, divdeu
, 1);
1205 GEN_DIVE(divde
, divde
, 0);
1206 GEN_DIVE(divdeo
, divde
, 1);
1209 static inline void gen_op_arith_modw(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1210 TCGv arg2
, int sign
)
1212 TCGv_i32 t0
= tcg_temp_new_i32();
1213 TCGv_i32 t1
= tcg_temp_new_i32();
1215 tcg_gen_trunc_tl_i32(t0
, arg1
);
1216 tcg_gen_trunc_tl_i32(t1
, arg2
);
1218 TCGv_i32 t2
= tcg_temp_new_i32();
1219 TCGv_i32 t3
= tcg_temp_new_i32();
1220 tcg_gen_setcondi_i32(TCG_COND_EQ
, t2
, t0
, INT_MIN
);
1221 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, -1);
1222 tcg_gen_and_i32(t2
, t2
, t3
);
1223 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, 0);
1224 tcg_gen_or_i32(t2
, t2
, t3
);
1225 tcg_gen_movi_i32(t3
, 0);
1226 tcg_gen_movcond_i32(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1227 tcg_gen_rem_i32(t3
, t0
, t1
);
1228 tcg_gen_ext_i32_tl(ret
, t3
);
1229 tcg_temp_free_i32(t2
);
1230 tcg_temp_free_i32(t3
);
1232 TCGv_i32 t2
= tcg_const_i32(1);
1233 TCGv_i32 t3
= tcg_const_i32(0);
1234 tcg_gen_movcond_i32(TCG_COND_EQ
, t1
, t1
, t3
, t2
, t1
);
1235 tcg_gen_remu_i32(t3
, t0
, t1
);
1236 tcg_gen_extu_i32_tl(ret
, t3
);
1237 tcg_temp_free_i32(t2
);
1238 tcg_temp_free_i32(t3
);
1240 tcg_temp_free_i32(t0
);
1241 tcg_temp_free_i32(t1
);
1244 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1245 static void glue(gen_, name)(DisasContext *ctx) \
1247 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1248 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1252 GEN_INT_ARITH_MODW(moduw
, 0x08, 0);
1253 GEN_INT_ARITH_MODW(modsw
, 0x18, 1);
1255 #if defined(TARGET_PPC64)
1256 static inline void gen_op_arith_modd(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1257 TCGv arg2
, int sign
)
1259 TCGv_i64 t0
= tcg_temp_new_i64();
1260 TCGv_i64 t1
= tcg_temp_new_i64();
1262 tcg_gen_mov_i64(t0
, arg1
);
1263 tcg_gen_mov_i64(t1
, arg2
);
1265 TCGv_i64 t2
= tcg_temp_new_i64();
1266 TCGv_i64 t3
= tcg_temp_new_i64();
1267 tcg_gen_setcondi_i64(TCG_COND_EQ
, t2
, t0
, INT64_MIN
);
1268 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, -1);
1269 tcg_gen_and_i64(t2
, t2
, t3
);
1270 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, 0);
1271 tcg_gen_or_i64(t2
, t2
, t3
);
1272 tcg_gen_movi_i64(t3
, 0);
1273 tcg_gen_movcond_i64(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1274 tcg_gen_rem_i64(ret
, t0
, t1
);
1275 tcg_temp_free_i64(t2
);
1276 tcg_temp_free_i64(t3
);
1278 TCGv_i64 t2
= tcg_const_i64(1);
1279 TCGv_i64 t3
= tcg_const_i64(0);
1280 tcg_gen_movcond_i64(TCG_COND_EQ
, t1
, t1
, t3
, t2
, t1
);
1281 tcg_gen_remu_i64(ret
, t0
, t1
);
1282 tcg_temp_free_i64(t2
);
1283 tcg_temp_free_i64(t3
);
1285 tcg_temp_free_i64(t0
);
1286 tcg_temp_free_i64(t1
);
1289 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1290 static void glue(gen_, name)(DisasContext *ctx) \
1292 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1293 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1297 GEN_INT_ARITH_MODD(modud
, 0x08, 0);
1298 GEN_INT_ARITH_MODD(modsd
, 0x18, 1);
1302 static void gen_mulhw(DisasContext
*ctx
)
1304 TCGv_i32 t0
= tcg_temp_new_i32();
1305 TCGv_i32 t1
= tcg_temp_new_i32();
1307 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1308 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1309 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
1310 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1311 tcg_temp_free_i32(t0
);
1312 tcg_temp_free_i32(t1
);
1313 if (unlikely(Rc(ctx
->opcode
) != 0))
1314 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1317 /* mulhwu mulhwu. */
1318 static void gen_mulhwu(DisasContext
*ctx
)
1320 TCGv_i32 t0
= tcg_temp_new_i32();
1321 TCGv_i32 t1
= tcg_temp_new_i32();
1323 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1324 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1325 tcg_gen_mulu2_i32(t0
, t1
, t0
, t1
);
1326 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1327 tcg_temp_free_i32(t0
);
1328 tcg_temp_free_i32(t1
);
1329 if (unlikely(Rc(ctx
->opcode
) != 0))
1330 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1334 static void gen_mullw(DisasContext
*ctx
)
1336 #if defined(TARGET_PPC64)
1338 t0
= tcg_temp_new_i64();
1339 t1
= tcg_temp_new_i64();
1340 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1341 tcg_gen_ext32s_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1342 tcg_gen_mul_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
1346 tcg_gen_mul_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1347 cpu_gpr
[rB(ctx
->opcode
)]);
1349 if (unlikely(Rc(ctx
->opcode
) != 0))
1350 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1353 /* mullwo mullwo. */
1354 static void gen_mullwo(DisasContext
*ctx
)
1356 TCGv_i32 t0
= tcg_temp_new_i32();
1357 TCGv_i32 t1
= tcg_temp_new_i32();
1359 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1360 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1361 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
1362 #if defined(TARGET_PPC64)
1363 tcg_gen_concat_i32_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
1365 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1368 tcg_gen_sari_i32(t0
, t0
, 31);
1369 tcg_gen_setcond_i32(TCG_COND_NE
, t0
, t0
, t1
);
1370 tcg_gen_extu_i32_tl(cpu_ov
, t0
);
1371 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1373 tcg_temp_free_i32(t0
);
1374 tcg_temp_free_i32(t1
);
1375 if (unlikely(Rc(ctx
->opcode
) != 0))
1376 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1380 static void gen_mulli(DisasContext
*ctx
)
1382 tcg_gen_muli_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1386 #if defined(TARGET_PPC64)
1388 static void gen_mulhd(DisasContext
*ctx
)
1390 TCGv lo
= tcg_temp_new();
1391 tcg_gen_muls2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
1392 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1394 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1395 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1399 /* mulhdu mulhdu. */
1400 static void gen_mulhdu(DisasContext
*ctx
)
1402 TCGv lo
= tcg_temp_new();
1403 tcg_gen_mulu2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
1404 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1406 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1407 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1412 static void gen_mulld(DisasContext
*ctx
)
1414 tcg_gen_mul_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1415 cpu_gpr
[rB(ctx
->opcode
)]);
1416 if (unlikely(Rc(ctx
->opcode
) != 0))
1417 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1420 /* mulldo mulldo. */
1421 static void gen_mulldo(DisasContext
*ctx
)
1423 TCGv_i64 t0
= tcg_temp_new_i64();
1424 TCGv_i64 t1
= tcg_temp_new_i64();
1426 tcg_gen_muls2_i64(t0
, t1
, cpu_gpr
[rA(ctx
->opcode
)],
1427 cpu_gpr
[rB(ctx
->opcode
)]);
1428 tcg_gen_mov_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1430 tcg_gen_sari_i64(t0
, t0
, 63);
1431 tcg_gen_setcond_i64(TCG_COND_NE
, cpu_ov
, t0
, t1
);
1432 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1434 tcg_temp_free_i64(t0
);
1435 tcg_temp_free_i64(t1
);
1437 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1438 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1443 /* Common subf function */
1444 static inline void gen_op_arith_subf(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1445 TCGv arg2
, bool add_ca
, bool compute_ca
,
1446 bool compute_ov
, bool compute_rc0
)
1450 if (compute_ca
|| compute_ov
) {
1451 t0
= tcg_temp_new();
1455 /* dest = ~arg1 + arg2 [+ ca]. */
1456 if (NARROW_MODE(ctx
)) {
1457 /* Caution: a non-obvious corner case of the spec is that we
1458 must produce the *entire* 64-bit addition, but produce the
1459 carry into bit 32. */
1460 TCGv inv1
= tcg_temp_new();
1461 TCGv t1
= tcg_temp_new();
1462 tcg_gen_not_tl(inv1
, arg1
);
1464 tcg_gen_add_tl(t0
, arg2
, cpu_ca
);
1466 tcg_gen_addi_tl(t0
, arg2
, 1);
1468 tcg_gen_xor_tl(t1
, arg2
, inv1
); /* add without carry */
1469 tcg_gen_add_tl(t0
, t0
, inv1
);
1470 tcg_temp_free(inv1
);
1471 tcg_gen_xor_tl(cpu_ca
, t0
, t1
); /* bits changes w/ carry */
1473 tcg_gen_shri_tl(cpu_ca
, cpu_ca
, 32); /* extract bit 32 */
1474 tcg_gen_andi_tl(cpu_ca
, cpu_ca
, 1);
1475 } else if (add_ca
) {
1476 TCGv zero
, inv1
= tcg_temp_new();
1477 tcg_gen_not_tl(inv1
, arg1
);
1478 zero
= tcg_const_tl(0);
1479 tcg_gen_add2_tl(t0
, cpu_ca
, arg2
, zero
, cpu_ca
, zero
);
1480 tcg_gen_add2_tl(t0
, cpu_ca
, t0
, cpu_ca
, inv1
, zero
);
1481 tcg_temp_free(zero
);
1482 tcg_temp_free(inv1
);
1484 tcg_gen_setcond_tl(TCG_COND_GEU
, cpu_ca
, arg2
, arg1
);
1485 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1487 } else if (add_ca
) {
1488 /* Since we're ignoring carry-out, we can simplify the
1489 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1490 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1491 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
1492 tcg_gen_subi_tl(t0
, t0
, 1);
1494 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1498 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 1);
1500 if (unlikely(compute_rc0
)) {
1501 gen_set_Rc0(ctx
, t0
);
1504 if (!TCGV_EQUAL(t0
, ret
)) {
1505 tcg_gen_mov_tl(ret
, t0
);
1509 /* Sub functions with Two operands functions */
1510 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1511 static void glue(gen_, name)(DisasContext *ctx) \
1513 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1514 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1515 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1517 /* Sub functions with one operand and one immediate */
1518 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1519 add_ca, compute_ca, compute_ov) \
1520 static void glue(gen_, name)(DisasContext *ctx) \
1522 TCGv t0 = tcg_const_tl(const_val); \
1523 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1524 cpu_gpr[rA(ctx->opcode)], t0, \
1525 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1526 tcg_temp_free(t0); \
1528 /* subf subf. subfo subfo. */
1529 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
1530 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
1531 /* subfc subfc. subfco subfco. */
1532 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
1533 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
1534 /* subfe subfe. subfeo subfo. */
1535 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
1536 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
1537 /* subfme subfme. subfmeo subfmeo. */
1538 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
1539 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
1540 /* subfze subfze. subfzeo subfzeo.*/
1541 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
1542 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
1545 static void gen_subfic(DisasContext
*ctx
)
1547 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
1548 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1553 /* neg neg. nego nego. */
1554 static inline void gen_op_arith_neg(DisasContext
*ctx
, bool compute_ov
)
1556 TCGv zero
= tcg_const_tl(0);
1557 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1558 zero
, 0, 0, compute_ov
, Rc(ctx
->opcode
));
1559 tcg_temp_free(zero
);
1562 static void gen_neg(DisasContext
*ctx
)
1564 gen_op_arith_neg(ctx
, 0);
1567 static void gen_nego(DisasContext
*ctx
)
1569 gen_op_arith_neg(ctx
, 1);
1572 /*** Integer logical ***/
1573 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1574 static void glue(gen_, name)(DisasContext *ctx) \
1576 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1577 cpu_gpr[rB(ctx->opcode)]); \
1578 if (unlikely(Rc(ctx->opcode) != 0)) \
1579 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1582 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1583 static void glue(gen_, name)(DisasContext *ctx) \
1585 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1586 if (unlikely(Rc(ctx->opcode) != 0)) \
1587 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1591 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
);
1593 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
);
1596 static void gen_andi_(DisasContext
*ctx
)
1598 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
));
1599 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1603 static void gen_andis_(DisasContext
*ctx
)
1605 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
) << 16);
1606 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1610 static void gen_cntlzw(DisasContext
*ctx
)
1612 gen_helper_cntlzw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1613 if (unlikely(Rc(ctx
->opcode
) != 0))
1614 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1618 static void gen_cnttzw(DisasContext
*ctx
)
1620 gen_helper_cnttzw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1621 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1622 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1627 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
);
1628 /* extsb & extsb. */
1629 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
);
1630 /* extsh & extsh. */
1631 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
);
1633 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
);
1635 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
);
1637 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1638 static void gen_pause(DisasContext
*ctx
)
1640 TCGv_i32 t0
= tcg_const_i32(0);
1641 tcg_gen_st_i32(t0
, cpu_env
,
1642 -offsetof(PowerPCCPU
, env
) + offsetof(CPUState
, halted
));
1643 tcg_temp_free_i32(t0
);
1645 /* Stop translation, this gives other CPUs a chance to run */
1646 gen_exception_err(ctx
, EXCP_HLT
, 1);
1648 #endif /* defined(TARGET_PPC64) */
1651 static void gen_or(DisasContext
*ctx
)
1655 rs
= rS(ctx
->opcode
);
1656 ra
= rA(ctx
->opcode
);
1657 rb
= rB(ctx
->opcode
);
1658 /* Optimisation for mr. ri case */
1659 if (rs
!= ra
|| rs
!= rb
) {
1661 tcg_gen_or_tl(cpu_gpr
[ra
], cpu_gpr
[rs
], cpu_gpr
[rb
]);
1663 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rs
]);
1664 if (unlikely(Rc(ctx
->opcode
) != 0))
1665 gen_set_Rc0(ctx
, cpu_gpr
[ra
]);
1666 } else if (unlikely(Rc(ctx
->opcode
) != 0)) {
1667 gen_set_Rc0(ctx
, cpu_gpr
[rs
]);
1668 #if defined(TARGET_PPC64)
1669 } else if (rs
!= 0) { /* 0 is nop */
1674 /* Set process priority to low */
1678 /* Set process priority to medium-low */
1682 /* Set process priority to normal */
1685 #if !defined(CONFIG_USER_ONLY)
1688 /* Set process priority to very low */
1694 /* Set process priority to medium-hight */
1700 /* Set process priority to high */
1705 if (ctx
->hv
&& !ctx
->pr
) {
1706 /* Set process priority to very high */
1715 TCGv t0
= tcg_temp_new();
1716 gen_load_spr(t0
, SPR_PPR
);
1717 tcg_gen_andi_tl(t0
, t0
, ~0x001C000000000000ULL
);
1718 tcg_gen_ori_tl(t0
, t0
, ((uint64_t)prio
) << 50);
1719 gen_store_spr(SPR_PPR
, t0
);
1722 #if !defined(CONFIG_USER_ONLY)
1723 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1724 * CPU and the kernel hangs. This applies to all encodings other
1725 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1726 * and all currently undefined.
1734 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
);
1737 static void gen_xor(DisasContext
*ctx
)
1739 /* Optimisation for "set to zero" case */
1740 if (rS(ctx
->opcode
) != rB(ctx
->opcode
))
1741 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1743 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
1744 if (unlikely(Rc(ctx
->opcode
) != 0))
1745 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1749 static void gen_ori(DisasContext
*ctx
)
1751 target_ulong uimm
= UIMM(ctx
->opcode
);
1753 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1756 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1760 static void gen_oris(DisasContext
*ctx
)
1762 target_ulong uimm
= UIMM(ctx
->opcode
);
1764 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1768 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1772 static void gen_xori(DisasContext
*ctx
)
1774 target_ulong uimm
= UIMM(ctx
->opcode
);
1776 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1780 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1784 static void gen_xoris(DisasContext
*ctx
)
1786 target_ulong uimm
= UIMM(ctx
->opcode
);
1788 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1792 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1795 /* popcntb : PowerPC 2.03 specification */
1796 static void gen_popcntb(DisasContext
*ctx
)
1798 gen_helper_popcntb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1801 static void gen_popcntw(DisasContext
*ctx
)
1803 gen_helper_popcntw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1806 #if defined(TARGET_PPC64)
1807 /* popcntd: PowerPC 2.06 specification */
1808 static void gen_popcntd(DisasContext
*ctx
)
1810 gen_helper_popcntd(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1814 /* prtyw: PowerPC 2.05 specification */
1815 static void gen_prtyw(DisasContext
*ctx
)
1817 TCGv ra
= cpu_gpr
[rA(ctx
->opcode
)];
1818 TCGv rs
= cpu_gpr
[rS(ctx
->opcode
)];
1819 TCGv t0
= tcg_temp_new();
1820 tcg_gen_shri_tl(t0
, rs
, 16);
1821 tcg_gen_xor_tl(ra
, rs
, t0
);
1822 tcg_gen_shri_tl(t0
, ra
, 8);
1823 tcg_gen_xor_tl(ra
, ra
, t0
);
1824 tcg_gen_andi_tl(ra
, ra
, (target_ulong
)0x100000001ULL
);
1828 #if defined(TARGET_PPC64)
1829 /* prtyd: PowerPC 2.05 specification */
1830 static void gen_prtyd(DisasContext
*ctx
)
1832 TCGv ra
= cpu_gpr
[rA(ctx
->opcode
)];
1833 TCGv rs
= cpu_gpr
[rS(ctx
->opcode
)];
1834 TCGv t0
= tcg_temp_new();
1835 tcg_gen_shri_tl(t0
, rs
, 32);
1836 tcg_gen_xor_tl(ra
, rs
, t0
);
1837 tcg_gen_shri_tl(t0
, ra
, 16);
1838 tcg_gen_xor_tl(ra
, ra
, t0
);
1839 tcg_gen_shri_tl(t0
, ra
, 8);
1840 tcg_gen_xor_tl(ra
, ra
, t0
);
1841 tcg_gen_andi_tl(ra
, ra
, 1);
1846 #if defined(TARGET_PPC64)
1848 static void gen_bpermd(DisasContext
*ctx
)
1850 gen_helper_bpermd(cpu_gpr
[rA(ctx
->opcode
)],
1851 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1855 #if defined(TARGET_PPC64)
1856 /* extsw & extsw. */
1857 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
);
1860 static void gen_cntlzd(DisasContext
*ctx
)
1862 gen_helper_cntlzd(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1863 if (unlikely(Rc(ctx
->opcode
) != 0))
1864 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1868 static void gen_cnttzd(DisasContext
*ctx
)
1870 gen_helper_cnttzd(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1871 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1872 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1877 /*** Integer rotate ***/
1879 /* rlwimi & rlwimi. */
1880 static void gen_rlwimi(DisasContext
*ctx
)
1882 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1883 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1884 uint32_t sh
= SH(ctx
->opcode
);
1885 uint32_t mb
= MB(ctx
->opcode
);
1886 uint32_t me
= ME(ctx
->opcode
);
1888 if (sh
== (31-me
) && mb
<= me
) {
1889 tcg_gen_deposit_tl(t_ra
, t_ra
, t_rs
, sh
, me
- mb
+ 1);
1894 #if defined(TARGET_PPC64)
1898 mask
= MASK(mb
, me
);
1900 t1
= tcg_temp_new();
1901 if (mask
<= 0xffffffffu
) {
1902 TCGv_i32 t0
= tcg_temp_new_i32();
1903 tcg_gen_trunc_tl_i32(t0
, t_rs
);
1904 tcg_gen_rotli_i32(t0
, t0
, sh
);
1905 tcg_gen_extu_i32_tl(t1
, t0
);
1906 tcg_temp_free_i32(t0
);
1908 #if defined(TARGET_PPC64)
1909 tcg_gen_deposit_i64(t1
, t_rs
, t_rs
, 32, 32);
1910 tcg_gen_rotli_i64(t1
, t1
, sh
);
1912 g_assert_not_reached();
1916 tcg_gen_andi_tl(t1
, t1
, mask
);
1917 tcg_gen_andi_tl(t_ra
, t_ra
, ~mask
);
1918 tcg_gen_or_tl(t_ra
, t_ra
, t1
);
1921 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1922 gen_set_Rc0(ctx
, t_ra
);
1926 /* rlwinm & rlwinm. */
1927 static void gen_rlwinm(DisasContext
*ctx
)
1929 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1930 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1931 uint32_t sh
= SH(ctx
->opcode
);
1932 uint32_t mb
= MB(ctx
->opcode
);
1933 uint32_t me
= ME(ctx
->opcode
);
1935 if (mb
== 0 && me
== (31 - sh
)) {
1936 tcg_gen_shli_tl(t_ra
, t_rs
, sh
);
1937 tcg_gen_ext32u_tl(t_ra
, t_ra
);
1938 } else if (sh
!= 0 && me
== 31 && sh
== (32 - mb
)) {
1939 tcg_gen_ext32u_tl(t_ra
, t_rs
);
1940 tcg_gen_shri_tl(t_ra
, t_ra
, mb
);
1943 #if defined(TARGET_PPC64)
1947 mask
= MASK(mb
, me
);
1949 if (mask
<= 0xffffffffu
) {
1950 TCGv_i32 t0
= tcg_temp_new_i32();
1951 tcg_gen_trunc_tl_i32(t0
, t_rs
);
1952 tcg_gen_rotli_i32(t0
, t0
, sh
);
1953 tcg_gen_andi_i32(t0
, t0
, mask
);
1954 tcg_gen_extu_i32_tl(t_ra
, t0
);
1955 tcg_temp_free_i32(t0
);
1957 #if defined(TARGET_PPC64)
1958 tcg_gen_deposit_i64(t_ra
, t_rs
, t_rs
, 32, 32);
1959 tcg_gen_rotli_i64(t_ra
, t_ra
, sh
);
1960 tcg_gen_andi_i64(t_ra
, t_ra
, mask
);
1962 g_assert_not_reached();
1966 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1967 gen_set_Rc0(ctx
, t_ra
);
1971 /* rlwnm & rlwnm. */
1972 static void gen_rlwnm(DisasContext
*ctx
)
1974 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1975 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1976 TCGv t_rb
= cpu_gpr
[rB(ctx
->opcode
)];
1977 uint32_t mb
= MB(ctx
->opcode
);
1978 uint32_t me
= ME(ctx
->opcode
);
1981 #if defined(TARGET_PPC64)
1985 mask
= MASK(mb
, me
);
1987 if (mask
<= 0xffffffffu
) {
1988 TCGv_i32 t0
= tcg_temp_new_i32();
1989 TCGv_i32 t1
= tcg_temp_new_i32();
1990 tcg_gen_trunc_tl_i32(t0
, t_rb
);
1991 tcg_gen_trunc_tl_i32(t1
, t_rs
);
1992 tcg_gen_andi_i32(t0
, t0
, 0x1f);
1993 tcg_gen_rotl_i32(t1
, t1
, t0
);
1994 tcg_gen_extu_i32_tl(t_ra
, t1
);
1995 tcg_temp_free_i32(t0
);
1996 tcg_temp_free_i32(t1
);
1998 #if defined(TARGET_PPC64)
1999 TCGv_i64 t0
= tcg_temp_new_i64();
2000 tcg_gen_andi_i64(t0
, t_rb
, 0x1f);
2001 tcg_gen_deposit_i64(t_ra
, t_rs
, t_rs
, 32, 32);
2002 tcg_gen_rotl_i64(t_ra
, t_ra
, t0
);
2003 tcg_temp_free_i64(t0
);
2005 g_assert_not_reached();
2009 tcg_gen_andi_tl(t_ra
, t_ra
, mask
);
2011 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2012 gen_set_Rc0(ctx
, t_ra
);
2016 #if defined(TARGET_PPC64)
2017 #define GEN_PPC64_R2(name, opc1, opc2) \
2018 static void glue(gen_, name##0)(DisasContext *ctx) \
2020 gen_##name(ctx, 0); \
2023 static void glue(gen_, name##1)(DisasContext *ctx) \
2025 gen_##name(ctx, 1); \
2027 #define GEN_PPC64_R4(name, opc1, opc2) \
2028 static void glue(gen_, name##0)(DisasContext *ctx) \
2030 gen_##name(ctx, 0, 0); \
2033 static void glue(gen_, name##1)(DisasContext *ctx) \
2035 gen_##name(ctx, 0, 1); \
2038 static void glue(gen_, name##2)(DisasContext *ctx) \
2040 gen_##name(ctx, 1, 0); \
2043 static void glue(gen_, name##3)(DisasContext *ctx) \
2045 gen_##name(ctx, 1, 1); \
2048 static void gen_rldinm(DisasContext
*ctx
, int mb
, int me
, int sh
)
2050 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2051 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2053 if (sh
!= 0 && mb
== 0 && me
== (63 - sh
)) {
2054 tcg_gen_shli_tl(t_ra
, t_rs
, sh
);
2055 } else if (sh
!= 0 && me
== 63 && sh
== (64 - mb
)) {
2056 tcg_gen_shri_tl(t_ra
, t_rs
, mb
);
2058 tcg_gen_rotli_tl(t_ra
, t_rs
, sh
);
2059 tcg_gen_andi_tl(t_ra
, t_ra
, MASK(mb
, me
));
2061 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2062 gen_set_Rc0(ctx
, t_ra
);
2066 /* rldicl - rldicl. */
2067 static inline void gen_rldicl(DisasContext
*ctx
, int mbn
, int shn
)
2071 sh
= SH(ctx
->opcode
) | (shn
<< 5);
2072 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2073 gen_rldinm(ctx
, mb
, 63, sh
);
2075 GEN_PPC64_R4(rldicl
, 0x1E, 0x00);
2077 /* rldicr - rldicr. */
2078 static inline void gen_rldicr(DisasContext
*ctx
, int men
, int shn
)
2082 sh
= SH(ctx
->opcode
) | (shn
<< 5);
2083 me
= MB(ctx
->opcode
) | (men
<< 5);
2084 gen_rldinm(ctx
, 0, me
, sh
);
2086 GEN_PPC64_R4(rldicr
, 0x1E, 0x02);
2088 /* rldic - rldic. */
2089 static inline void gen_rldic(DisasContext
*ctx
, int mbn
, int shn
)
2093 sh
= SH(ctx
->opcode
) | (shn
<< 5);
2094 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2095 gen_rldinm(ctx
, mb
, 63 - sh
, sh
);
2097 GEN_PPC64_R4(rldic
, 0x1E, 0x04);
2099 static void gen_rldnm(DisasContext
*ctx
, int mb
, int me
)
2101 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2102 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2103 TCGv t_rb
= cpu_gpr
[rB(ctx
->opcode
)];
2106 t0
= tcg_temp_new();
2107 tcg_gen_andi_tl(t0
, t_rb
, 0x3f);
2108 tcg_gen_rotl_tl(t_ra
, t_rs
, t0
);
2111 tcg_gen_andi_tl(t_ra
, t_ra
, MASK(mb
, me
));
2112 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2113 gen_set_Rc0(ctx
, t_ra
);
2117 /* rldcl - rldcl. */
2118 static inline void gen_rldcl(DisasContext
*ctx
, int mbn
)
2122 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2123 gen_rldnm(ctx
, mb
, 63);
2125 GEN_PPC64_R2(rldcl
, 0x1E, 0x08);
2127 /* rldcr - rldcr. */
2128 static inline void gen_rldcr(DisasContext
*ctx
, int men
)
2132 me
= MB(ctx
->opcode
) | (men
<< 5);
2133 gen_rldnm(ctx
, 0, me
);
2135 GEN_PPC64_R2(rldcr
, 0x1E, 0x09);
2137 /* rldimi - rldimi. */
2138 static void gen_rldimi(DisasContext
*ctx
, int mbn
, int shn
)
2140 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2141 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2142 uint32_t sh
= SH(ctx
->opcode
) | (shn
<< 5);
2143 uint32_t mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2144 uint32_t me
= 63 - sh
;
2147 tcg_gen_deposit_tl(t_ra
, t_ra
, t_rs
, sh
, me
- mb
+ 1);
2149 target_ulong mask
= MASK(mb
, me
);
2150 TCGv t1
= tcg_temp_new();
2152 tcg_gen_rotli_tl(t1
, t_rs
, sh
);
2153 tcg_gen_andi_tl(t1
, t1
, mask
);
2154 tcg_gen_andi_tl(t_ra
, t_ra
, ~mask
);
2155 tcg_gen_or_tl(t_ra
, t_ra
, t1
);
2158 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2159 gen_set_Rc0(ctx
, t_ra
);
2162 GEN_PPC64_R4(rldimi
, 0x1E, 0x06);
2165 /*** Integer shift ***/
2168 static void gen_slw(DisasContext
*ctx
)
2172 t0
= tcg_temp_new();
2173 /* AND rS with a mask that is 0 when rB >= 0x20 */
2174 #if defined(TARGET_PPC64)
2175 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
2176 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2178 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
2179 tcg_gen_sari_tl(t0
, t0
, 0x1f);
2181 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2182 t1
= tcg_temp_new();
2183 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
2184 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2187 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
2188 if (unlikely(Rc(ctx
->opcode
) != 0))
2189 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2193 static void gen_sraw(DisasContext
*ctx
)
2195 gen_helper_sraw(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
2196 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2197 if (unlikely(Rc(ctx
->opcode
) != 0))
2198 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2201 /* srawi & srawi. */
2202 static void gen_srawi(DisasContext
*ctx
)
2204 int sh
= SH(ctx
->opcode
);
2205 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
2206 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
2208 tcg_gen_ext32s_tl(dst
, src
);
2209 tcg_gen_movi_tl(cpu_ca
, 0);
2212 tcg_gen_ext32s_tl(dst
, src
);
2213 tcg_gen_andi_tl(cpu_ca
, dst
, (1ULL << sh
) - 1);
2214 t0
= tcg_temp_new();
2215 tcg_gen_sari_tl(t0
, dst
, TARGET_LONG_BITS
- 1);
2216 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
2218 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
2219 tcg_gen_sari_tl(dst
, dst
, sh
);
2221 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2222 gen_set_Rc0(ctx
, dst
);
2227 static void gen_srw(DisasContext
*ctx
)
2231 t0
= tcg_temp_new();
2232 /* AND rS with a mask that is 0 when rB >= 0x20 */
2233 #if defined(TARGET_PPC64)
2234 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
2235 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2237 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
2238 tcg_gen_sari_tl(t0
, t0
, 0x1f);
2240 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2241 tcg_gen_ext32u_tl(t0
, t0
);
2242 t1
= tcg_temp_new();
2243 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
2244 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2247 if (unlikely(Rc(ctx
->opcode
) != 0))
2248 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2251 #if defined(TARGET_PPC64)
2253 static void gen_sld(DisasContext
*ctx
)
2257 t0
= tcg_temp_new();
2258 /* AND rS with a mask that is 0 when rB >= 0x40 */
2259 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
2260 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2261 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2262 t1
= tcg_temp_new();
2263 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
2264 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2267 if (unlikely(Rc(ctx
->opcode
) != 0))
2268 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2272 static void gen_srad(DisasContext
*ctx
)
2274 gen_helper_srad(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
2275 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2276 if (unlikely(Rc(ctx
->opcode
) != 0))
2277 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2279 /* sradi & sradi. */
2280 static inline void gen_sradi(DisasContext
*ctx
, int n
)
2282 int sh
= SH(ctx
->opcode
) + (n
<< 5);
2283 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
2284 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
2286 tcg_gen_mov_tl(dst
, src
);
2287 tcg_gen_movi_tl(cpu_ca
, 0);
2290 tcg_gen_andi_tl(cpu_ca
, src
, (1ULL << sh
) - 1);
2291 t0
= tcg_temp_new();
2292 tcg_gen_sari_tl(t0
, src
, TARGET_LONG_BITS
- 1);
2293 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
2295 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
2296 tcg_gen_sari_tl(dst
, src
, sh
);
2298 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2299 gen_set_Rc0(ctx
, dst
);
2303 static void gen_sradi0(DisasContext
*ctx
)
2308 static void gen_sradi1(DisasContext
*ctx
)
2314 static void gen_srd(DisasContext
*ctx
)
2318 t0
= tcg_temp_new();
2319 /* AND rS with a mask that is 0 when rB >= 0x40 */
2320 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
2321 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2322 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2323 t1
= tcg_temp_new();
2324 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
2325 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2328 if (unlikely(Rc(ctx
->opcode
) != 0))
2329 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2333 /*** Addressing modes ***/
2334 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2335 static inline void gen_addr_imm_index(DisasContext
*ctx
, TCGv EA
,
2338 target_long simm
= SIMM(ctx
->opcode
);
2341 if (rA(ctx
->opcode
) == 0) {
2342 if (NARROW_MODE(ctx
)) {
2343 simm
= (uint32_t)simm
;
2345 tcg_gen_movi_tl(EA
, simm
);
2346 } else if (likely(simm
!= 0)) {
2347 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], simm
);
2348 if (NARROW_MODE(ctx
)) {
2349 tcg_gen_ext32u_tl(EA
, EA
);
2352 if (NARROW_MODE(ctx
)) {
2353 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2355 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2360 static inline void gen_addr_reg_index(DisasContext
*ctx
, TCGv EA
)
2362 if (rA(ctx
->opcode
) == 0) {
2363 if (NARROW_MODE(ctx
)) {
2364 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2366 tcg_gen_mov_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2369 tcg_gen_add_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2370 if (NARROW_MODE(ctx
)) {
2371 tcg_gen_ext32u_tl(EA
, EA
);
2376 static inline void gen_addr_register(DisasContext
*ctx
, TCGv EA
)
2378 if (rA(ctx
->opcode
) == 0) {
2379 tcg_gen_movi_tl(EA
, 0);
2380 } else if (NARROW_MODE(ctx
)) {
2381 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2383 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2387 static inline void gen_addr_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
2390 tcg_gen_addi_tl(ret
, arg1
, val
);
2391 if (NARROW_MODE(ctx
)) {
2392 tcg_gen_ext32u_tl(ret
, ret
);
2396 static inline void gen_check_align(DisasContext
*ctx
, TCGv EA
, int mask
)
2398 TCGLabel
*l1
= gen_new_label();
2399 TCGv t0
= tcg_temp_new();
2401 /* NIP cannot be restored if the memory exception comes from an helper */
2402 gen_update_nip(ctx
, ctx
->nip
- 4);
2403 tcg_gen_andi_tl(t0
, EA
, mask
);
2404 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
2405 t1
= tcg_const_i32(POWERPC_EXCP_ALIGN
);
2406 t2
= tcg_const_i32(0);
2407 gen_helper_raise_exception_err(cpu_env
, t1
, t2
);
2408 tcg_temp_free_i32(t1
);
2409 tcg_temp_free_i32(t2
);
2414 /*** Integer load ***/
2415 static inline void gen_qemu_ld8u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2417 tcg_gen_qemu_ld8u(arg1
, arg2
, ctx
->mem_idx
);
2420 static inline void gen_qemu_ld16u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2422 TCGMemOp op
= MO_UW
| ctx
->default_tcg_memop_mask
;
2423 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2426 static inline void gen_qemu_ld16s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2428 TCGMemOp op
= MO_SW
| ctx
->default_tcg_memop_mask
;
2429 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2432 static inline void gen_qemu_ld32u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2434 TCGMemOp op
= MO_UL
| ctx
->default_tcg_memop_mask
;
2435 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2438 static void gen_qemu_ld32u_i64(DisasContext
*ctx
, TCGv_i64 val
, TCGv addr
)
2440 TCGv tmp
= tcg_temp_new();
2441 gen_qemu_ld32u(ctx
, tmp
, addr
);
2442 tcg_gen_extu_tl_i64(val
, tmp
);
2446 static inline void gen_qemu_ld32s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2448 TCGMemOp op
= MO_SL
| ctx
->default_tcg_memop_mask
;
2449 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2452 static void gen_qemu_ld32s_i64(DisasContext
*ctx
, TCGv_i64 val
, TCGv addr
)
2454 TCGv tmp
= tcg_temp_new();
2455 gen_qemu_ld32s(ctx
, tmp
, addr
);
2456 tcg_gen_ext_tl_i64(val
, tmp
);
2460 static inline void gen_qemu_ld64(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
2462 TCGMemOp op
= MO_Q
| ctx
->default_tcg_memop_mask
;
2463 tcg_gen_qemu_ld_i64(arg1
, arg2
, ctx
->mem_idx
, op
);
2466 static inline void gen_qemu_st8(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2468 tcg_gen_qemu_st8(arg1
, arg2
, ctx
->mem_idx
);
2471 static inline void gen_qemu_st16(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2473 TCGMemOp op
= MO_UW
| ctx
->default_tcg_memop_mask
;
2474 tcg_gen_qemu_st_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2477 static inline void gen_qemu_st32(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2479 TCGMemOp op
= MO_UL
| ctx
->default_tcg_memop_mask
;
2480 tcg_gen_qemu_st_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2483 static void gen_qemu_st32_i64(DisasContext
*ctx
, TCGv_i64 val
, TCGv addr
)
2485 TCGv tmp
= tcg_temp_new();
2486 tcg_gen_trunc_i64_tl(tmp
, val
);
2487 gen_qemu_st32(ctx
, tmp
, addr
);
2491 static inline void gen_qemu_st64(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
2493 TCGMemOp op
= MO_Q
| ctx
->default_tcg_memop_mask
;
2494 tcg_gen_qemu_st_i64(arg1
, arg2
, ctx
->mem_idx
, op
);
2497 #define GEN_LD(name, ldop, opc, type) \
2498 static void glue(gen_, name)(DisasContext *ctx) \
2501 gen_set_access_type(ctx, ACCESS_INT); \
2502 EA = tcg_temp_new(); \
2503 gen_addr_imm_index(ctx, EA, 0); \
2504 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2505 tcg_temp_free(EA); \
2508 #define GEN_LDU(name, ldop, opc, type) \
2509 static void glue(gen_, name##u)(DisasContext *ctx) \
2512 if (unlikely(rA(ctx->opcode) == 0 || \
2513 rA(ctx->opcode) == rD(ctx->opcode))) { \
2514 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2517 gen_set_access_type(ctx, ACCESS_INT); \
2518 EA = tcg_temp_new(); \
2519 if (type == PPC_64B) \
2520 gen_addr_imm_index(ctx, EA, 0x03); \
2522 gen_addr_imm_index(ctx, EA, 0); \
2523 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2524 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2525 tcg_temp_free(EA); \
2528 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2529 static void glue(gen_, name##ux)(DisasContext *ctx) \
2532 if (unlikely(rA(ctx->opcode) == 0 || \
2533 rA(ctx->opcode) == rD(ctx->opcode))) { \
2534 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2537 gen_set_access_type(ctx, ACCESS_INT); \
2538 EA = tcg_temp_new(); \
2539 gen_addr_reg_index(ctx, EA); \
2540 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2541 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2542 tcg_temp_free(EA); \
2545 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2546 static void glue(gen_, name##x)(DisasContext *ctx) \
2550 gen_set_access_type(ctx, ACCESS_INT); \
2551 EA = tcg_temp_new(); \
2552 gen_addr_reg_index(ctx, EA); \
2553 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2554 tcg_temp_free(EA); \
2557 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2558 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2560 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2561 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2563 #define GEN_LDS(name, ldop, op, type) \
2564 GEN_LD(name, ldop, op | 0x20, type); \
2565 GEN_LDU(name, ldop, op | 0x21, type); \
2566 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2567 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2569 /* lbz lbzu lbzux lbzx */
2570 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
);
2571 /* lha lhau lhaux lhax */
2572 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
);
2573 /* lhz lhzu lhzux lhzx */
2574 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
);
2575 /* lwz lwzu lwzux lwzx */
2576 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
);
2577 #if defined(TARGET_PPC64)
2579 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
);
2581 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
);
2583 GEN_LDUX(ld
, ld64
, 0x15, 0x01, PPC_64B
);
2585 GEN_LDX(ld
, ld64
, 0x15, 0x00, PPC_64B
);
2587 /* CI load/store variants */
2588 GEN_LDX_HVRM(ldcix
, ld64
, 0x15, 0x1b, PPC_CILDST
)
2589 GEN_LDX_HVRM(lwzcix
, ld32u
, 0x15, 0x15, PPC_CILDST
)
2590 GEN_LDX_HVRM(lhzcix
, ld16u
, 0x15, 0x19, PPC_CILDST
)
2591 GEN_LDX_HVRM(lbzcix
, ld8u
, 0x15, 0x1a, PPC_CILDST
)
2593 static void gen_ld(DisasContext
*ctx
)
2596 if (Rc(ctx
->opcode
)) {
2597 if (unlikely(rA(ctx
->opcode
) == 0 ||
2598 rA(ctx
->opcode
) == rD(ctx
->opcode
))) {
2599 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2603 gen_set_access_type(ctx
, ACCESS_INT
);
2604 EA
= tcg_temp_new();
2605 gen_addr_imm_index(ctx
, EA
, 0x03);
2606 if (ctx
->opcode
& 0x02) {
2607 /* lwa (lwau is undefined) */
2608 gen_qemu_ld32s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2611 gen_qemu_ld64(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2613 if (Rc(ctx
->opcode
))
2614 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2619 static void gen_lq(DisasContext
*ctx
)
2624 /* lq is a legal user mode instruction starting in ISA 2.07 */
2625 bool legal_in_user_mode
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2626 bool le_is_supported
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2628 if (!legal_in_user_mode
&& ctx
->pr
) {
2629 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2633 if (!le_is_supported
&& ctx
->le_mode
) {
2634 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
2638 ra
= rA(ctx
->opcode
);
2639 rd
= rD(ctx
->opcode
);
2640 if (unlikely((rd
& 1) || rd
== ra
)) {
2641 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2645 gen_set_access_type(ctx
, ACCESS_INT
);
2646 EA
= tcg_temp_new();
2647 gen_addr_imm_index(ctx
, EA
, 0x0F);
2649 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2650 64-bit byteswap already. */
2651 if (unlikely(ctx
->le_mode
)) {
2652 gen_qemu_ld64(ctx
, cpu_gpr
[rd
+1], EA
);
2653 gen_addr_add(ctx
, EA
, EA
, 8);
2654 gen_qemu_ld64(ctx
, cpu_gpr
[rd
], EA
);
2656 gen_qemu_ld64(ctx
, cpu_gpr
[rd
], EA
);
2657 gen_addr_add(ctx
, EA
, EA
, 8);
2658 gen_qemu_ld64(ctx
, cpu_gpr
[rd
+1], EA
);
2664 /*** Integer store ***/
2665 #define GEN_ST(name, stop, opc, type) \
2666 static void glue(gen_, name)(DisasContext *ctx) \
2669 gen_set_access_type(ctx, ACCESS_INT); \
2670 EA = tcg_temp_new(); \
2671 gen_addr_imm_index(ctx, EA, 0); \
2672 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2673 tcg_temp_free(EA); \
2676 #define GEN_STU(name, stop, opc, type) \
2677 static void glue(gen_, stop##u)(DisasContext *ctx) \
2680 if (unlikely(rA(ctx->opcode) == 0)) { \
2681 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2684 gen_set_access_type(ctx, ACCESS_INT); \
2685 EA = tcg_temp_new(); \
2686 if (type == PPC_64B) \
2687 gen_addr_imm_index(ctx, EA, 0x03); \
2689 gen_addr_imm_index(ctx, EA, 0); \
2690 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2691 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2692 tcg_temp_free(EA); \
2695 #define GEN_STUX(name, stop, opc2, opc3, type) \
2696 static void glue(gen_, name##ux)(DisasContext *ctx) \
2699 if (unlikely(rA(ctx->opcode) == 0)) { \
2700 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2703 gen_set_access_type(ctx, ACCESS_INT); \
2704 EA = tcg_temp_new(); \
2705 gen_addr_reg_index(ctx, EA); \
2706 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2707 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2708 tcg_temp_free(EA); \
2711 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2712 static void glue(gen_, name##x)(DisasContext *ctx) \
2716 gen_set_access_type(ctx, ACCESS_INT); \
2717 EA = tcg_temp_new(); \
2718 gen_addr_reg_index(ctx, EA); \
2719 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2720 tcg_temp_free(EA); \
2722 #define GEN_STX(name, stop, opc2, opc3, type) \
2723 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2725 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2726 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2728 #define GEN_STS(name, stop, op, type) \
2729 GEN_ST(name, stop, op | 0x20, type); \
2730 GEN_STU(name, stop, op | 0x21, type); \
2731 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2732 GEN_STX(name, stop, 0x17, op | 0x00, type)
2734 /* stb stbu stbux stbx */
2735 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
);
2736 /* sth sthu sthux sthx */
2737 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
);
2738 /* stw stwu stwux stwx */
2739 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
);
2740 #if defined(TARGET_PPC64)
2741 GEN_STUX(std
, st64
, 0x15, 0x05, PPC_64B
);
2742 GEN_STX(std
, st64
, 0x15, 0x04, PPC_64B
);
2743 GEN_STX_HVRM(stdcix
, st64
, 0x15, 0x1f, PPC_CILDST
)
2744 GEN_STX_HVRM(stwcix
, st32
, 0x15, 0x1c, PPC_CILDST
)
2745 GEN_STX_HVRM(sthcix
, st16
, 0x15, 0x1d, PPC_CILDST
)
2746 GEN_STX_HVRM(stbcix
, st8
, 0x15, 0x1e, PPC_CILDST
)
2748 static void gen_std(DisasContext
*ctx
)
2753 rs
= rS(ctx
->opcode
);
2754 if ((ctx
->opcode
& 0x3) == 0x2) { /* stq */
2755 bool legal_in_user_mode
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2756 bool le_is_supported
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2758 if (!(ctx
->insns_flags
& PPC_64BX
)) {
2759 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2762 if (!legal_in_user_mode
&& ctx
->pr
) {
2763 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2767 if (!le_is_supported
&& ctx
->le_mode
) {
2768 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
2772 if (unlikely(rs
& 1)) {
2773 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2776 gen_set_access_type(ctx
, ACCESS_INT
);
2777 EA
= tcg_temp_new();
2778 gen_addr_imm_index(ctx
, EA
, 0x03);
2780 /* We only need to swap high and low halves. gen_qemu_st64 does
2781 necessary 64-bit byteswap already. */
2782 if (unlikely(ctx
->le_mode
)) {
2783 gen_qemu_st64(ctx
, cpu_gpr
[rs
+1], EA
);
2784 gen_addr_add(ctx
, EA
, EA
, 8);
2785 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
2787 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
2788 gen_addr_add(ctx
, EA
, EA
, 8);
2789 gen_qemu_st64(ctx
, cpu_gpr
[rs
+1], EA
);
2794 if (Rc(ctx
->opcode
)) {
2795 if (unlikely(rA(ctx
->opcode
) == 0)) {
2796 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2800 gen_set_access_type(ctx
, ACCESS_INT
);
2801 EA
= tcg_temp_new();
2802 gen_addr_imm_index(ctx
, EA
, 0x03);
2803 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
2804 if (Rc(ctx
->opcode
))
2805 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2810 /*** Integer load and store with byte reverse ***/
2813 static inline void gen_qemu_ld16ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2815 TCGMemOp op
= MO_UW
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
2816 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2818 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
);
2821 static inline void gen_qemu_ld32ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2823 TCGMemOp op
= MO_UL
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
2824 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2826 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
);
2828 #if defined(TARGET_PPC64)
2830 static inline void gen_qemu_ld64ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2832 TCGMemOp op
= MO_Q
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
2833 tcg_gen_qemu_ld_i64(arg1
, arg2
, ctx
->mem_idx
, op
);
2835 GEN_LDX_E(ldbr
, ld64ur
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
, CHK_NONE
);
2836 #endif /* TARGET_PPC64 */
2839 static inline void gen_qemu_st16r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2841 TCGMemOp op
= MO_UW
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
2842 tcg_gen_qemu_st_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2844 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
);
2847 static inline void gen_qemu_st32r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2849 TCGMemOp op
= MO_UL
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
2850 tcg_gen_qemu_st_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2852 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
);
2854 #if defined(TARGET_PPC64)
2856 static inline void gen_qemu_st64r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2858 TCGMemOp op
= MO_Q
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
2859 tcg_gen_qemu_st_i64(arg1
, arg2
, ctx
->mem_idx
, op
);
2861 GEN_STX_E(stdbr
, st64r
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
, CHK_NONE
);
2862 #endif /* TARGET_PPC64 */
2864 /*** Integer load and store multiple ***/
2867 static void gen_lmw(DisasContext
*ctx
)
2871 gen_set_access_type(ctx
, ACCESS_INT
);
2872 /* NIP cannot be restored if the memory exception comes from an helper */
2873 gen_update_nip(ctx
, ctx
->nip
- 4);
2874 t0
= tcg_temp_new();
2875 t1
= tcg_const_i32(rD(ctx
->opcode
));
2876 gen_addr_imm_index(ctx
, t0
, 0);
2877 gen_helper_lmw(cpu_env
, t0
, t1
);
2879 tcg_temp_free_i32(t1
);
2883 static void gen_stmw(DisasContext
*ctx
)
2887 gen_set_access_type(ctx
, ACCESS_INT
);
2888 /* NIP cannot be restored if the memory exception comes from an helper */
2889 gen_update_nip(ctx
, ctx
->nip
- 4);
2890 t0
= tcg_temp_new();
2891 t1
= tcg_const_i32(rS(ctx
->opcode
));
2892 gen_addr_imm_index(ctx
, t0
, 0);
2893 gen_helper_stmw(cpu_env
, t0
, t1
);
2895 tcg_temp_free_i32(t1
);
2898 /*** Integer load and store strings ***/
2901 /* PowerPC32 specification says we must generate an exception if
2902 * rA is in the range of registers to be loaded.
2903 * In an other hand, IBM says this is valid, but rA won't be loaded.
2904 * For now, I'll follow the spec...
2906 static void gen_lswi(DisasContext
*ctx
)
2910 int nb
= NB(ctx
->opcode
);
2911 int start
= rD(ctx
->opcode
);
2912 int ra
= rA(ctx
->opcode
);
2918 if (unlikely(lsw_reg_in_range(start
, nr
, ra
))) {
2919 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
2922 gen_set_access_type(ctx
, ACCESS_INT
);
2923 /* NIP cannot be restored if the memory exception comes from an helper */
2924 gen_update_nip(ctx
, ctx
->nip
- 4);
2925 t0
= tcg_temp_new();
2926 gen_addr_register(ctx
, t0
);
2927 t1
= tcg_const_i32(nb
);
2928 t2
= tcg_const_i32(start
);
2929 gen_helper_lsw(cpu_env
, t0
, t1
, t2
);
2931 tcg_temp_free_i32(t1
);
2932 tcg_temp_free_i32(t2
);
2936 static void gen_lswx(DisasContext
*ctx
)
2939 TCGv_i32 t1
, t2
, t3
;
2940 gen_set_access_type(ctx
, ACCESS_INT
);
2941 /* NIP cannot be restored if the memory exception comes from an helper */
2942 gen_update_nip(ctx
, ctx
->nip
- 4);
2943 t0
= tcg_temp_new();
2944 gen_addr_reg_index(ctx
, t0
);
2945 t1
= tcg_const_i32(rD(ctx
->opcode
));
2946 t2
= tcg_const_i32(rA(ctx
->opcode
));
2947 t3
= tcg_const_i32(rB(ctx
->opcode
));
2948 gen_helper_lswx(cpu_env
, t0
, t1
, t2
, t3
);
2950 tcg_temp_free_i32(t1
);
2951 tcg_temp_free_i32(t2
);
2952 tcg_temp_free_i32(t3
);
2956 static void gen_stswi(DisasContext
*ctx
)
2960 int nb
= NB(ctx
->opcode
);
2961 gen_set_access_type(ctx
, ACCESS_INT
);
2962 /* NIP cannot be restored if the memory exception comes from an helper */
2963 gen_update_nip(ctx
, ctx
->nip
- 4);
2964 t0
= tcg_temp_new();
2965 gen_addr_register(ctx
, t0
);
2968 t1
= tcg_const_i32(nb
);
2969 t2
= tcg_const_i32(rS(ctx
->opcode
));
2970 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
2972 tcg_temp_free_i32(t1
);
2973 tcg_temp_free_i32(t2
);
2977 static void gen_stswx(DisasContext
*ctx
)
2981 gen_set_access_type(ctx
, ACCESS_INT
);
2982 /* NIP cannot be restored if the memory exception comes from an helper */
2983 gen_update_nip(ctx
, ctx
->nip
- 4);
2984 t0
= tcg_temp_new();
2985 gen_addr_reg_index(ctx
, t0
);
2986 t1
= tcg_temp_new_i32();
2987 tcg_gen_trunc_tl_i32(t1
, cpu_xer
);
2988 tcg_gen_andi_i32(t1
, t1
, 0x7F);
2989 t2
= tcg_const_i32(rS(ctx
->opcode
));
2990 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
2992 tcg_temp_free_i32(t1
);
2993 tcg_temp_free_i32(t2
);
2996 /*** Memory synchronisation ***/
2998 static void gen_eieio(DisasContext
*ctx
)
3002 #if !defined(CONFIG_USER_ONLY)
3003 static inline void gen_check_tlb_flush(DisasContext
*ctx
)
3008 if (!ctx
->lazy_tlb_flush
) {
3011 l
= gen_new_label();
3012 t
= tcg_temp_new_i32();
3013 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUPPCState
, tlb_need_flush
));
3014 tcg_gen_brcondi_i32(TCG_COND_EQ
, t
, 0, l
);
3015 gen_helper_check_tlb_flush(cpu_env
);
3017 tcg_temp_free_i32(t
);
3020 static inline void gen_check_tlb_flush(DisasContext
*ctx
) { }
3024 static void gen_isync(DisasContext
*ctx
)
3027 * We need to check for a pending TLB flush. This can only happen in
3028 * kernel mode however so check MSR_PR
3031 gen_check_tlb_flush(ctx
);
3033 gen_stop_exception(ctx
);
3036 #define LARX(name, len, loadop) \
3037 static void gen_##name(DisasContext *ctx) \
3040 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3041 gen_set_access_type(ctx, ACCESS_RES); \
3042 t0 = tcg_temp_local_new(); \
3043 gen_addr_reg_index(ctx, t0); \
3045 gen_check_align(ctx, t0, (len)-1); \
3047 gen_qemu_##loadop(ctx, gpr, t0); \
3048 tcg_gen_mov_tl(cpu_reserve, t0); \
3049 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3050 tcg_temp_free(t0); \
3054 LARX(lbarx
, 1, ld8u
);
3055 LARX(lharx
, 2, ld16u
);
3056 LARX(lwarx
, 4, ld32u
);
3059 #if defined(CONFIG_USER_ONLY)
3060 static void gen_conditional_store(DisasContext
*ctx
, TCGv EA
,
3063 TCGv t0
= tcg_temp_new();
3064 uint32_t save_exception
= ctx
->exception
;
3066 tcg_gen_st_tl(EA
, cpu_env
, offsetof(CPUPPCState
, reserve_ea
));
3067 tcg_gen_movi_tl(t0
, (size
<< 5) | reg
);
3068 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUPPCState
, reserve_info
));
3070 gen_update_nip(ctx
, ctx
->nip
-4);
3071 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3072 gen_exception(ctx
, POWERPC_EXCP_STCX
);
3073 ctx
->exception
= save_exception
;
3076 static void gen_conditional_store(DisasContext
*ctx
, TCGv EA
,
3081 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
3082 l1
= gen_new_label();
3083 tcg_gen_brcond_tl(TCG_COND_NE
, EA
, cpu_reserve
, l1
);
3084 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 1 << CRF_EQ
);
3085 #if defined(TARGET_PPC64)
3087 gen_qemu_st64(ctx
, cpu_gpr
[reg
], EA
);
3091 gen_qemu_st32(ctx
, cpu_gpr
[reg
], EA
);
3092 } else if (size
== 2) {
3093 gen_qemu_st16(ctx
, cpu_gpr
[reg
], EA
);
3094 #if defined(TARGET_PPC64)
3095 } else if (size
== 16) {
3096 TCGv gpr1
, gpr2
, EA8
;
3097 if (unlikely(ctx
->le_mode
)) {
3098 gpr1
= cpu_gpr
[reg
+1];
3099 gpr2
= cpu_gpr
[reg
];
3101 gpr1
= cpu_gpr
[reg
];
3102 gpr2
= cpu_gpr
[reg
+1];
3104 gen_qemu_st64(ctx
, gpr1
, EA
);
3105 EA8
= tcg_temp_local_new();
3106 gen_addr_add(ctx
, EA8
, EA
, 8);
3107 gen_qemu_st64(ctx
, gpr2
, EA8
);
3111 gen_qemu_st8(ctx
, cpu_gpr
[reg
], EA
);
3114 tcg_gen_movi_tl(cpu_reserve
, -1);
3118 #define STCX(name, len) \
3119 static void gen_##name(DisasContext *ctx) \
3122 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3123 gen_inval_exception(ctx, \
3124 POWERPC_EXCP_INVAL_INVAL); \
3127 gen_set_access_type(ctx, ACCESS_RES); \
3128 t0 = tcg_temp_local_new(); \
3129 gen_addr_reg_index(ctx, t0); \
3131 gen_check_align(ctx, t0, (len)-1); \
3133 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3134 tcg_temp_free(t0); \
3141 #if defined(TARGET_PPC64)
3143 LARX(ldarx
, 8, ld64
);
3146 static void gen_lqarx(DisasContext
*ctx
)
3149 int rd
= rD(ctx
->opcode
);
3152 if (unlikely((rd
& 1) || (rd
== rA(ctx
->opcode
)) ||
3153 (rd
== rB(ctx
->opcode
)))) {
3154 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3158 gen_set_access_type(ctx
, ACCESS_RES
);
3159 EA
= tcg_temp_local_new();
3160 gen_addr_reg_index(ctx
, EA
);
3161 gen_check_align(ctx
, EA
, 15);
3162 if (unlikely(ctx
->le_mode
)) {
3163 gpr1
= cpu_gpr
[rd
+1];
3167 gpr2
= cpu_gpr
[rd
+1];
3169 gen_qemu_ld64(ctx
, gpr1
, EA
);
3170 tcg_gen_mov_tl(cpu_reserve
, EA
);
3172 gen_addr_add(ctx
, EA
, EA
, 8);
3173 gen_qemu_ld64(ctx
, gpr2
, EA
);
3175 tcg_gen_st_tl(gpr1
, cpu_env
, offsetof(CPUPPCState
, reserve_val
));
3176 tcg_gen_st_tl(gpr2
, cpu_env
, offsetof(CPUPPCState
, reserve_val2
));
3184 #endif /* defined(TARGET_PPC64) */
3187 static void gen_sync(DisasContext
*ctx
)
3189 uint32_t l
= (ctx
->opcode
>> 21) & 3;
3192 * We may need to check for a pending TLB flush.
3194 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3196 * Additionally, this can only happen in kernel mode however so
3197 * check MSR_PR as well.
3199 if (((l
== 2) || !(ctx
->insns_flags
& PPC_64B
)) && !ctx
->pr
) {
3200 gen_check_tlb_flush(ctx
);
3205 static void gen_wait(DisasContext
*ctx
)
3207 TCGv_i32 t0
= tcg_const_i32(1);
3208 tcg_gen_st_i32(t0
, cpu_env
,
3209 -offsetof(PowerPCCPU
, env
) + offsetof(CPUState
, halted
));
3210 tcg_temp_free_i32(t0
);
3211 /* Stop translation, as the CPU is supposed to sleep from now */
3212 gen_exception_err(ctx
, EXCP_HLT
, 1);
3215 #if defined(TARGET_PPC64)
3216 static void gen_doze(DisasContext
*ctx
)
3218 #if defined(CONFIG_USER_ONLY)
3224 t
= tcg_const_i32(PPC_PM_DOZE
);
3225 gen_helper_pminsn(cpu_env
, t
);
3226 tcg_temp_free_i32(t
);
3227 gen_stop_exception(ctx
);
3228 #endif /* defined(CONFIG_USER_ONLY) */
3231 static void gen_nap(DisasContext
*ctx
)
3233 #if defined(CONFIG_USER_ONLY)
3239 t
= tcg_const_i32(PPC_PM_NAP
);
3240 gen_helper_pminsn(cpu_env
, t
);
3241 tcg_temp_free_i32(t
);
3242 gen_stop_exception(ctx
);
3243 #endif /* defined(CONFIG_USER_ONLY) */
3246 static void gen_sleep(DisasContext
*ctx
)
3248 #if defined(CONFIG_USER_ONLY)
3254 t
= tcg_const_i32(PPC_PM_SLEEP
);
3255 gen_helper_pminsn(cpu_env
, t
);
3256 tcg_temp_free_i32(t
);
3257 gen_stop_exception(ctx
);
3258 #endif /* defined(CONFIG_USER_ONLY) */
3261 static void gen_rvwinkle(DisasContext
*ctx
)
3263 #if defined(CONFIG_USER_ONLY)
3269 t
= tcg_const_i32(PPC_PM_RVWINKLE
);
3270 gen_helper_pminsn(cpu_env
, t
);
3271 tcg_temp_free_i32(t
);
3272 gen_stop_exception(ctx
);
3273 #endif /* defined(CONFIG_USER_ONLY) */
3275 #endif /* #if defined(TARGET_PPC64) */
3277 static inline void gen_update_cfar(DisasContext
*ctx
, target_ulong nip
)
3279 #if defined(TARGET_PPC64)
3281 tcg_gen_movi_tl(cpu_cfar
, nip
);
3285 static inline bool use_goto_tb(DisasContext
*ctx
, target_ulong dest
)
3287 if (unlikely(ctx
->singlestep_enabled
)) {
3291 #ifndef CONFIG_USER_ONLY
3292 return (ctx
->tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
3299 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
3301 if (NARROW_MODE(ctx
)) {
3302 dest
= (uint32_t) dest
;
3304 if (use_goto_tb(ctx
, dest
)) {
3306 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3307 tcg_gen_exit_tb((uintptr_t)ctx
->tb
+ n
);
3309 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3310 if (unlikely(ctx
->singlestep_enabled
)) {
3311 if ((ctx
->singlestep_enabled
&
3312 (CPU_BRANCH_STEP
| CPU_SINGLE_STEP
)) &&
3313 (ctx
->exception
== POWERPC_EXCP_BRANCH
||
3314 ctx
->exception
== POWERPC_EXCP_TRACE
)) {
3315 target_ulong tmp
= ctx
->nip
;
3317 gen_exception(ctx
, POWERPC_EXCP_TRACE
);
3320 if (ctx
->singlestep_enabled
& GDBSTUB_SINGLE_STEP
) {
3321 gen_debug_exception(ctx
);
3328 static inline void gen_setlr(DisasContext
*ctx
, target_ulong nip
)
3330 if (NARROW_MODE(ctx
)) {
3331 nip
= (uint32_t)nip
;
3333 tcg_gen_movi_tl(cpu_lr
, nip
);
3337 static void gen_b(DisasContext
*ctx
)
3339 target_ulong li
, target
;
3341 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3342 /* sign extend LI */
3343 li
= LI(ctx
->opcode
);
3344 li
= (li
^ 0x02000000) - 0x02000000;
3345 if (likely(AA(ctx
->opcode
) == 0)) {
3346 target
= ctx
->nip
+ li
- 4;
3350 if (LK(ctx
->opcode
)) {
3351 gen_setlr(ctx
, ctx
->nip
);
3353 gen_update_cfar(ctx
, ctx
->nip
);
3354 gen_goto_tb(ctx
, 0, target
);
3362 static inline void gen_bcond(DisasContext
*ctx
, int type
)
3364 uint32_t bo
= BO(ctx
->opcode
);
3368 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3369 if (type
== BCOND_LR
|| type
== BCOND_CTR
|| type
== BCOND_TAR
) {
3370 target
= tcg_temp_local_new();
3371 if (type
== BCOND_CTR
)
3372 tcg_gen_mov_tl(target
, cpu_ctr
);
3373 else if (type
== BCOND_TAR
)
3374 gen_load_spr(target
, SPR_TAR
);
3376 tcg_gen_mov_tl(target
, cpu_lr
);
3378 TCGV_UNUSED(target
);
3380 if (LK(ctx
->opcode
))
3381 gen_setlr(ctx
, ctx
->nip
);
3382 l1
= gen_new_label();
3383 if ((bo
& 0x4) == 0) {
3384 /* Decrement and test CTR */
3385 TCGv temp
= tcg_temp_new();
3386 if (unlikely(type
== BCOND_CTR
)) {
3387 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3390 tcg_gen_subi_tl(cpu_ctr
, cpu_ctr
, 1);
3391 if (NARROW_MODE(ctx
)) {
3392 tcg_gen_ext32u_tl(temp
, cpu_ctr
);
3394 tcg_gen_mov_tl(temp
, cpu_ctr
);
3397 tcg_gen_brcondi_tl(TCG_COND_NE
, temp
, 0, l1
);
3399 tcg_gen_brcondi_tl(TCG_COND_EQ
, temp
, 0, l1
);
3401 tcg_temp_free(temp
);
3403 if ((bo
& 0x10) == 0) {
3405 uint32_t bi
= BI(ctx
->opcode
);
3406 uint32_t mask
= 0x08 >> (bi
& 0x03);
3407 TCGv_i32 temp
= tcg_temp_new_i32();
3410 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3411 tcg_gen_brcondi_i32(TCG_COND_EQ
, temp
, 0, l1
);
3413 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3414 tcg_gen_brcondi_i32(TCG_COND_NE
, temp
, 0, l1
);
3416 tcg_temp_free_i32(temp
);
3418 gen_update_cfar(ctx
, ctx
->nip
);
3419 if (type
== BCOND_IM
) {
3420 target_ulong li
= (target_long
)((int16_t)(BD(ctx
->opcode
)));
3421 if (likely(AA(ctx
->opcode
) == 0)) {
3422 gen_goto_tb(ctx
, 0, ctx
->nip
+ li
- 4);
3424 gen_goto_tb(ctx
, 0, li
);
3427 gen_goto_tb(ctx
, 1, ctx
->nip
);
3429 if (NARROW_MODE(ctx
)) {
3430 tcg_gen_andi_tl(cpu_nip
, target
, (uint32_t)~3);
3432 tcg_gen_andi_tl(cpu_nip
, target
, ~3);
3436 gen_update_nip(ctx
, ctx
->nip
);
3439 if (type
== BCOND_LR
|| type
== BCOND_CTR
|| type
== BCOND_TAR
) {
3440 tcg_temp_free(target
);
3444 static void gen_bc(DisasContext
*ctx
)
3446 gen_bcond(ctx
, BCOND_IM
);
3449 static void gen_bcctr(DisasContext
*ctx
)
3451 gen_bcond(ctx
, BCOND_CTR
);
3454 static void gen_bclr(DisasContext
*ctx
)
3456 gen_bcond(ctx
, BCOND_LR
);
3459 static void gen_bctar(DisasContext
*ctx
)
3461 gen_bcond(ctx
, BCOND_TAR
);
3464 /*** Condition register logical ***/
3465 #define GEN_CRLOGIC(name, tcg_op, opc) \
3466 static void glue(gen_, name)(DisasContext *ctx) \
3471 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3472 t0 = tcg_temp_new_i32(); \
3474 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3476 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3478 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3479 t1 = tcg_temp_new_i32(); \
3480 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3482 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3484 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3486 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3487 tcg_op(t0, t0, t1); \
3488 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3489 tcg_gen_andi_i32(t0, t0, bitmask); \
3490 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3491 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3492 tcg_temp_free_i32(t0); \
3493 tcg_temp_free_i32(t1); \
3497 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08);
3499 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04);
3501 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09);
3503 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07);
3505 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01);
3507 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E);
3509 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D);
3511 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06);
3514 static void gen_mcrf(DisasContext
*ctx
)
3516 tcg_gen_mov_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfS(ctx
->opcode
)]);
3519 /*** System linkage ***/
3521 /* rfi (supervisor only) */
3522 static void gen_rfi(DisasContext
*ctx
)
3524 #if defined(CONFIG_USER_ONLY)
3527 /* FIXME: This instruction doesn't exist anymore on 64-bit server
3528 * processors compliant with arch 2.x, we should remove it there,
3529 * but we need to fix OpenBIOS not to use it on 970 first
3531 /* Restore CPU state */
3533 gen_update_cfar(ctx
, ctx
->nip
);
3534 gen_helper_rfi(cpu_env
);
3535 gen_sync_exception(ctx
);
3539 #if defined(TARGET_PPC64)
3540 static void gen_rfid(DisasContext
*ctx
)
3542 #if defined(CONFIG_USER_ONLY)
3545 /* Restore CPU state */
3547 gen_update_cfar(ctx
, ctx
->nip
);
3548 gen_helper_rfid(cpu_env
);
3549 gen_sync_exception(ctx
);
3553 static void gen_hrfid(DisasContext
*ctx
)
3555 #if defined(CONFIG_USER_ONLY)
3558 /* Restore CPU state */
3560 gen_helper_hrfid(cpu_env
);
3561 gen_sync_exception(ctx
);
3567 #if defined(CONFIG_USER_ONLY)
3568 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3570 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3572 static void gen_sc(DisasContext
*ctx
)
3576 lev
= (ctx
->opcode
>> 5) & 0x7F;
3577 gen_exception_err(ctx
, POWERPC_SYSCALL
, lev
);
3583 static void gen_tw(DisasContext
*ctx
)
3585 TCGv_i32 t0
= tcg_const_i32(TO(ctx
->opcode
));
3586 /* Update the nip since this might generate a trap exception */
3587 gen_update_nip(ctx
, ctx
->nip
);
3588 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
3590 tcg_temp_free_i32(t0
);
3594 static void gen_twi(DisasContext
*ctx
)
3596 TCGv t0
= tcg_const_tl(SIMM(ctx
->opcode
));
3597 TCGv_i32 t1
= tcg_const_i32(TO(ctx
->opcode
));
3598 /* Update the nip since this might generate a trap exception */
3599 gen_update_nip(ctx
, ctx
->nip
);
3600 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
3602 tcg_temp_free_i32(t1
);
3605 #if defined(TARGET_PPC64)
3607 static void gen_td(DisasContext
*ctx
)
3609 TCGv_i32 t0
= tcg_const_i32(TO(ctx
->opcode
));
3610 /* Update the nip since this might generate a trap exception */
3611 gen_update_nip(ctx
, ctx
->nip
);
3612 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
3614 tcg_temp_free_i32(t0
);
3618 static void gen_tdi(DisasContext
*ctx
)
3620 TCGv t0
= tcg_const_tl(SIMM(ctx
->opcode
));
3621 TCGv_i32 t1
= tcg_const_i32(TO(ctx
->opcode
));
3622 /* Update the nip since this might generate a trap exception */
3623 gen_update_nip(ctx
, ctx
->nip
);
3624 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
3626 tcg_temp_free_i32(t1
);
3630 /*** Processor control ***/
3632 static void gen_read_xer(TCGv dst
)
3634 TCGv t0
= tcg_temp_new();
3635 TCGv t1
= tcg_temp_new();
3636 TCGv t2
= tcg_temp_new();
3637 tcg_gen_mov_tl(dst
, cpu_xer
);
3638 tcg_gen_shli_tl(t0
, cpu_so
, XER_SO
);
3639 tcg_gen_shli_tl(t1
, cpu_ov
, XER_OV
);
3640 tcg_gen_shli_tl(t2
, cpu_ca
, XER_CA
);
3641 tcg_gen_or_tl(t0
, t0
, t1
);
3642 tcg_gen_or_tl(dst
, dst
, t2
);
3643 tcg_gen_or_tl(dst
, dst
, t0
);
3649 static void gen_write_xer(TCGv src
)
3651 tcg_gen_andi_tl(cpu_xer
, src
,
3652 ~((1u << XER_SO
) | (1u << XER_OV
) | (1u << XER_CA
)));
3653 tcg_gen_shri_tl(cpu_so
, src
, XER_SO
);
3654 tcg_gen_shri_tl(cpu_ov
, src
, XER_OV
);
3655 tcg_gen_shri_tl(cpu_ca
, src
, XER_CA
);
3656 tcg_gen_andi_tl(cpu_so
, cpu_so
, 1);
3657 tcg_gen_andi_tl(cpu_ov
, cpu_ov
, 1);
3658 tcg_gen_andi_tl(cpu_ca
, cpu_ca
, 1);
3662 static void gen_mcrxr(DisasContext
*ctx
)
3664 TCGv_i32 t0
= tcg_temp_new_i32();
3665 TCGv_i32 t1
= tcg_temp_new_i32();
3666 TCGv_i32 dst
= cpu_crf
[crfD(ctx
->opcode
)];
3668 tcg_gen_trunc_tl_i32(t0
, cpu_so
);
3669 tcg_gen_trunc_tl_i32(t1
, cpu_ov
);
3670 tcg_gen_trunc_tl_i32(dst
, cpu_ca
);
3671 tcg_gen_shli_i32(t0
, t0
, 3);
3672 tcg_gen_shli_i32(t1
, t1
, 2);
3673 tcg_gen_shli_i32(dst
, dst
, 1);
3674 tcg_gen_or_i32(dst
, dst
, t0
);
3675 tcg_gen_or_i32(dst
, dst
, t1
);
3676 tcg_temp_free_i32(t0
);
3677 tcg_temp_free_i32(t1
);
3679 tcg_gen_movi_tl(cpu_so
, 0);
3680 tcg_gen_movi_tl(cpu_ov
, 0);
3681 tcg_gen_movi_tl(cpu_ca
, 0);
3685 static void gen_mfcr(DisasContext
*ctx
)
3689 if (likely(ctx
->opcode
& 0x00100000)) {
3690 crm
= CRM(ctx
->opcode
);
3691 if (likely(crm
&& ((crm
& (crm
- 1)) == 0))) {
3693 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_crf
[7 - crn
]);
3694 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)],
3695 cpu_gpr
[rD(ctx
->opcode
)], crn
* 4);
3698 TCGv_i32 t0
= tcg_temp_new_i32();
3699 tcg_gen_mov_i32(t0
, cpu_crf
[0]);
3700 tcg_gen_shli_i32(t0
, t0
, 4);
3701 tcg_gen_or_i32(t0
, t0
, cpu_crf
[1]);
3702 tcg_gen_shli_i32(t0
, t0
, 4);
3703 tcg_gen_or_i32(t0
, t0
, cpu_crf
[2]);
3704 tcg_gen_shli_i32(t0
, t0
, 4);
3705 tcg_gen_or_i32(t0
, t0
, cpu_crf
[3]);
3706 tcg_gen_shli_i32(t0
, t0
, 4);
3707 tcg_gen_or_i32(t0
, t0
, cpu_crf
[4]);
3708 tcg_gen_shli_i32(t0
, t0
, 4);
3709 tcg_gen_or_i32(t0
, t0
, cpu_crf
[5]);
3710 tcg_gen_shli_i32(t0
, t0
, 4);
3711 tcg_gen_or_i32(t0
, t0
, cpu_crf
[6]);
3712 tcg_gen_shli_i32(t0
, t0
, 4);
3713 tcg_gen_or_i32(t0
, t0
, cpu_crf
[7]);
3714 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
3715 tcg_temp_free_i32(t0
);
3720 static void gen_mfmsr(DisasContext
*ctx
)
3723 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_msr
);
3726 static void spr_noaccess(DisasContext
*ctx
, int gprn
, int sprn
)
3729 sprn
= ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
3730 printf("ERROR: try to access SPR %d !\n", sprn
);
3733 #define SPR_NOACCESS (&spr_noaccess)
3736 static inline void gen_op_mfspr(DisasContext
*ctx
)
3738 void (*read_cb
)(DisasContext
*ctx
, int gprn
, int sprn
);
3739 uint32_t sprn
= SPR(ctx
->opcode
);
3741 #if defined(CONFIG_USER_ONLY)
3742 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
3745 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
3746 } else if (ctx
->hv
) {
3747 read_cb
= ctx
->spr_cb
[sprn
].hea_read
;
3749 read_cb
= ctx
->spr_cb
[sprn
].oea_read
;
3752 if (likely(read_cb
!= NULL
)) {
3753 if (likely(read_cb
!= SPR_NOACCESS
)) {
3754 (*read_cb
)(ctx
, rD(ctx
->opcode
), sprn
);
3756 /* Privilege exception */
3757 /* This is a hack to avoid warnings when running Linux:
3758 * this OS breaks the PowerPC virtualisation model,
3759 * allowing userland application to read the PVR
3761 if (sprn
!= SPR_PVR
) {
3762 fprintf(stderr
, "Trying to read privileged spr %d (0x%03x) at "
3763 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
3764 if (qemu_log_separate()) {
3765 qemu_log("Trying to read privileged spr %d (0x%03x) at "
3766 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
3769 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3772 /* ISA 2.07 defines these as no-ops */
3773 if ((ctx
->insns_flags2
& PPC2_ISA207S
) &&
3774 (sprn
>= 808 && sprn
<= 811)) {
3779 fprintf(stderr
, "Trying to read invalid spr %d (0x%03x) at "
3780 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
3781 if (qemu_log_separate()) {
3782 qemu_log("Trying to read invalid spr %d (0x%03x) at "
3783 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
3786 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3787 * it can generate a priv, a hv emu or a no-op
3791 gen_priv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
3794 if (ctx
->pr
|| sprn
== 0 || sprn
== 4 || sprn
== 5 || sprn
== 6) {
3795 gen_hvpriv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
3801 static void gen_mfspr(DisasContext
*ctx
)
3807 static void gen_mftb(DisasContext
*ctx
)
3813 static void gen_mtcrf(DisasContext
*ctx
)
3817 crm
= CRM(ctx
->opcode
);
3818 if (likely((ctx
->opcode
& 0x00100000))) {
3819 if (crm
&& ((crm
& (crm
- 1)) == 0)) {
3820 TCGv_i32 temp
= tcg_temp_new_i32();
3822 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
3823 tcg_gen_shri_i32(temp
, temp
, crn
* 4);
3824 tcg_gen_andi_i32(cpu_crf
[7 - crn
], temp
, 0xf);
3825 tcg_temp_free_i32(temp
);
3828 TCGv_i32 temp
= tcg_temp_new_i32();
3829 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
3830 for (crn
= 0 ; crn
< 8 ; crn
++) {
3831 if (crm
& (1 << crn
)) {
3832 tcg_gen_shri_i32(cpu_crf
[7 - crn
], temp
, crn
* 4);
3833 tcg_gen_andi_i32(cpu_crf
[7 - crn
], cpu_crf
[7 - crn
], 0xf);
3836 tcg_temp_free_i32(temp
);
3841 #if defined(TARGET_PPC64)
3842 static void gen_mtmsrd(DisasContext
*ctx
)
3846 #if !defined(CONFIG_USER_ONLY)
3847 if (ctx
->opcode
& 0x00010000) {
3848 /* Special form that does not need any synchronisation */
3849 TCGv t0
= tcg_temp_new();
3850 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
3851 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(target_ulong
)((1 << MSR_RI
) | (1 << MSR_EE
)));
3852 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
3855 /* XXX: we need to update nip before the store
3856 * if we enter power saving mode, we will exit the loop
3857 * directly from ppc_store_msr
3859 gen_update_nip(ctx
, ctx
->nip
);
3860 gen_helper_store_msr(cpu_env
, cpu_gpr
[rS(ctx
->opcode
)]);
3861 /* Must stop the translation as machine state (may have) changed */
3862 /* Note that mtmsr is not always defined as context-synchronizing */
3863 gen_stop_exception(ctx
);
3865 #endif /* !defined(CONFIG_USER_ONLY) */
3867 #endif /* defined(TARGET_PPC64) */
3869 static void gen_mtmsr(DisasContext
*ctx
)
3873 #if !defined(CONFIG_USER_ONLY)
3874 if (ctx
->opcode
& 0x00010000) {
3875 /* Special form that does not need any synchronisation */
3876 TCGv t0
= tcg_temp_new();
3877 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
3878 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(target_ulong
)((1 << MSR_RI
) | (1 << MSR_EE
)));
3879 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
3882 TCGv msr
= tcg_temp_new();
3884 /* XXX: we need to update nip before the store
3885 * if we enter power saving mode, we will exit the loop
3886 * directly from ppc_store_msr
3888 gen_update_nip(ctx
, ctx
->nip
);
3889 #if defined(TARGET_PPC64)
3890 tcg_gen_deposit_tl(msr
, cpu_msr
, cpu_gpr
[rS(ctx
->opcode
)], 0, 32);
3892 tcg_gen_mov_tl(msr
, cpu_gpr
[rS(ctx
->opcode
)]);
3894 gen_helper_store_msr(cpu_env
, msr
);
3896 /* Must stop the translation as machine state (may have) changed */
3897 /* Note that mtmsr is not always defined as context-synchronizing */
3898 gen_stop_exception(ctx
);
3904 static void gen_mtspr(DisasContext
*ctx
)
3906 void (*write_cb
)(DisasContext
*ctx
, int sprn
, int gprn
);
3907 uint32_t sprn
= SPR(ctx
->opcode
);
3909 #if defined(CONFIG_USER_ONLY)
3910 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
3913 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
3914 } else if (ctx
->hv
) {
3915 write_cb
= ctx
->spr_cb
[sprn
].hea_write
;
3917 write_cb
= ctx
->spr_cb
[sprn
].oea_write
;
3920 if (likely(write_cb
!= NULL
)) {
3921 if (likely(write_cb
!= SPR_NOACCESS
)) {
3922 (*write_cb
)(ctx
, sprn
, rS(ctx
->opcode
));
3924 /* Privilege exception */
3925 fprintf(stderr
, "Trying to write privileged spr %d (0x%03x) at "
3926 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
3927 if (qemu_log_separate()) {
3928 qemu_log("Trying to write privileged spr %d (0x%03x) at "
3929 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
3931 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3934 /* ISA 2.07 defines these as no-ops */
3935 if ((ctx
->insns_flags2
& PPC2_ISA207S
) &&
3936 (sprn
>= 808 && sprn
<= 811)) {
3942 if (qemu_log_separate()) {
3943 qemu_log("Trying to write invalid spr %d (0x%03x) at "
3944 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
3946 fprintf(stderr
, "Trying to write invalid spr %d (0x%03x) at "
3947 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
3950 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3951 * it can generate a priv, a hv emu or a no-op
3955 gen_priv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
3958 if (ctx
->pr
|| sprn
== 0) {
3959 gen_hvpriv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
3965 #if defined(TARGET_PPC64)
3967 static void gen_setb(DisasContext
*ctx
)
3969 TCGv_i32 t0
= tcg_temp_new_i32();
3970 TCGv_i32 t8
= tcg_temp_new_i32();
3971 TCGv_i32 tm1
= tcg_temp_new_i32();
3972 int crf
= crfS(ctx
->opcode
);
3974 tcg_gen_setcondi_i32(TCG_COND_GEU
, t0
, cpu_crf
[crf
], 4);
3975 tcg_gen_movi_i32(t8
, 8);
3976 tcg_gen_movi_i32(tm1
, -1);
3977 tcg_gen_movcond_i32(TCG_COND_GEU
, t0
, cpu_crf
[crf
], t8
, tm1
, t0
);
3978 tcg_gen_ext_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
3980 tcg_temp_free_i32(t0
);
3981 tcg_temp_free_i32(t8
);
3982 tcg_temp_free_i32(tm1
);
3986 /*** Cache management ***/
3989 static void gen_dcbf(DisasContext
*ctx
)
3991 /* XXX: specification says this is treated as a load by the MMU */
3993 gen_set_access_type(ctx
, ACCESS_CACHE
);
3994 t0
= tcg_temp_new();
3995 gen_addr_reg_index(ctx
, t0
);
3996 gen_qemu_ld8u(ctx
, t0
, t0
);
4000 /* dcbi (Supervisor only) */
4001 static void gen_dcbi(DisasContext
*ctx
)
4003 #if defined(CONFIG_USER_ONLY)
4009 EA
= tcg_temp_new();
4010 gen_set_access_type(ctx
, ACCESS_CACHE
);
4011 gen_addr_reg_index(ctx
, EA
);
4012 val
= tcg_temp_new();
4013 /* XXX: specification says this should be treated as a store by the MMU */
4014 gen_qemu_ld8u(ctx
, val
, EA
);
4015 gen_qemu_st8(ctx
, val
, EA
);
4018 #endif /* defined(CONFIG_USER_ONLY) */
4022 static void gen_dcbst(DisasContext
*ctx
)
4024 /* XXX: specification say this is treated as a load by the MMU */
4026 gen_set_access_type(ctx
, ACCESS_CACHE
);
4027 t0
= tcg_temp_new();
4028 gen_addr_reg_index(ctx
, t0
);
4029 gen_qemu_ld8u(ctx
, t0
, t0
);
4034 static void gen_dcbt(DisasContext
*ctx
)
4036 /* interpreted as no-op */
4037 /* XXX: specification say this is treated as a load by the MMU
4038 * but does not generate any exception
4043 static void gen_dcbtst(DisasContext
*ctx
)
4045 /* interpreted as no-op */
4046 /* XXX: specification say this is treated as a load by the MMU
4047 * but does not generate any exception
4052 static void gen_dcbtls(DisasContext
*ctx
)
4054 /* Always fails locking the cache */
4055 TCGv t0
= tcg_temp_new();
4056 gen_load_spr(t0
, SPR_Exxx_L1CSR0
);
4057 tcg_gen_ori_tl(t0
, t0
, L1CSR0_CUL
);
4058 gen_store_spr(SPR_Exxx_L1CSR0
, t0
);
4063 static void gen_dcbz(DisasContext
*ctx
)
4066 TCGv_i32 tcgv_is_dcbzl
;
4067 int is_dcbzl
= ctx
->opcode
& 0x00200000 ? 1 : 0;
4069 gen_set_access_type(ctx
, ACCESS_CACHE
);
4070 /* NIP cannot be restored if the memory exception comes from an helper */
4071 gen_update_nip(ctx
, ctx
->nip
- 4);
4072 tcgv_addr
= tcg_temp_new();
4073 tcgv_is_dcbzl
= tcg_const_i32(is_dcbzl
);
4075 gen_addr_reg_index(ctx
, tcgv_addr
);
4076 gen_helper_dcbz(cpu_env
, tcgv_addr
, tcgv_is_dcbzl
);
4078 tcg_temp_free(tcgv_addr
);
4079 tcg_temp_free_i32(tcgv_is_dcbzl
);
4083 static void gen_dst(DisasContext
*ctx
)
4085 if (rA(ctx
->opcode
) == 0) {
4086 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
4088 /* interpreted as no-op */
4093 static void gen_dstst(DisasContext
*ctx
)
4095 if (rA(ctx
->opcode
) == 0) {
4096 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
4098 /* interpreted as no-op */
4104 static void gen_dss(DisasContext
*ctx
)
4106 /* interpreted as no-op */
4110 static void gen_icbi(DisasContext
*ctx
)
4113 gen_set_access_type(ctx
, ACCESS_CACHE
);
4114 /* NIP cannot be restored if the memory exception comes from an helper */
4115 gen_update_nip(ctx
, ctx
->nip
- 4);
4116 t0
= tcg_temp_new();
4117 gen_addr_reg_index(ctx
, t0
);
4118 gen_helper_icbi(cpu_env
, t0
);
4124 static void gen_dcba(DisasContext
*ctx
)
4126 /* interpreted as no-op */
4127 /* XXX: specification say this is treated as a store by the MMU
4128 * but does not generate any exception
4132 /*** Segment register manipulation ***/
4133 /* Supervisor only: */
4136 static void gen_mfsr(DisasContext
*ctx
)
4138 #if defined(CONFIG_USER_ONLY)
4144 t0
= tcg_const_tl(SR(ctx
->opcode
));
4145 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4147 #endif /* defined(CONFIG_USER_ONLY) */
4151 static void gen_mfsrin(DisasContext
*ctx
)
4153 #if defined(CONFIG_USER_ONLY)
4159 t0
= tcg_temp_new();
4160 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4161 tcg_gen_andi_tl(t0
, t0
, 0xF);
4162 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4164 #endif /* defined(CONFIG_USER_ONLY) */
4168 static void gen_mtsr(DisasContext
*ctx
)
4170 #if defined(CONFIG_USER_ONLY)
4176 t0
= tcg_const_tl(SR(ctx
->opcode
));
4177 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4179 #endif /* defined(CONFIG_USER_ONLY) */
4183 static void gen_mtsrin(DisasContext
*ctx
)
4185 #if defined(CONFIG_USER_ONLY)
4191 t0
= tcg_temp_new();
4192 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4193 tcg_gen_andi_tl(t0
, t0
, 0xF);
4194 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rD(ctx
->opcode
)]);
4196 #endif /* defined(CONFIG_USER_ONLY) */
4199 #if defined(TARGET_PPC64)
4200 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4203 static void gen_mfsr_64b(DisasContext
*ctx
)
4205 #if defined(CONFIG_USER_ONLY)
4211 t0
= tcg_const_tl(SR(ctx
->opcode
));
4212 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4214 #endif /* defined(CONFIG_USER_ONLY) */
4218 static void gen_mfsrin_64b(DisasContext
*ctx
)
4220 #if defined(CONFIG_USER_ONLY)
4226 t0
= tcg_temp_new();
4227 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4228 tcg_gen_andi_tl(t0
, t0
, 0xF);
4229 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4231 #endif /* defined(CONFIG_USER_ONLY) */
4235 static void gen_mtsr_64b(DisasContext
*ctx
)
4237 #if defined(CONFIG_USER_ONLY)
4243 t0
= tcg_const_tl(SR(ctx
->opcode
));
4244 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4246 #endif /* defined(CONFIG_USER_ONLY) */
4250 static void gen_mtsrin_64b(DisasContext
*ctx
)
4252 #if defined(CONFIG_USER_ONLY)
4258 t0
= tcg_temp_new();
4259 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4260 tcg_gen_andi_tl(t0
, t0
, 0xF);
4261 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4263 #endif /* defined(CONFIG_USER_ONLY) */
4267 static void gen_slbmte(DisasContext
*ctx
)
4269 #if defined(CONFIG_USER_ONLY)
4274 gen_helper_store_slb(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)],
4275 cpu_gpr
[rS(ctx
->opcode
)]);
4276 #endif /* defined(CONFIG_USER_ONLY) */
4279 static void gen_slbmfee(DisasContext
*ctx
)
4281 #if defined(CONFIG_USER_ONLY)
4286 gen_helper_load_slb_esid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4287 cpu_gpr
[rB(ctx
->opcode
)]);
4288 #endif /* defined(CONFIG_USER_ONLY) */
4291 static void gen_slbmfev(DisasContext
*ctx
)
4293 #if defined(CONFIG_USER_ONLY)
4298 gen_helper_load_slb_vsid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4299 cpu_gpr
[rB(ctx
->opcode
)]);
4300 #endif /* defined(CONFIG_USER_ONLY) */
4303 static void gen_slbfee_(DisasContext
*ctx
)
4305 #if defined(CONFIG_USER_ONLY)
4306 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4310 if (unlikely(ctx
->pr
)) {
4311 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4314 gen_helper_find_slb_vsid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4315 cpu_gpr
[rB(ctx
->opcode
)]);
4316 l1
= gen_new_label();
4317 l2
= gen_new_label();
4318 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
4319 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rS(ctx
->opcode
)], -1, l1
);
4320 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 1 << CRF_EQ
);
4323 tcg_gen_movi_tl(cpu_gpr
[rS(ctx
->opcode
)], 0);
4327 #endif /* defined(TARGET_PPC64) */
4329 /*** Lookaside buffer management ***/
4330 /* Optional & supervisor only: */
4333 static void gen_tlbia(DisasContext
*ctx
)
4335 #if defined(CONFIG_USER_ONLY)
4340 gen_helper_tlbia(cpu_env
);
4341 #endif /* defined(CONFIG_USER_ONLY) */
4345 static void gen_tlbiel(DisasContext
*ctx
)
4347 #if defined(CONFIG_USER_ONLY)
4352 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4353 #endif /* defined(CONFIG_USER_ONLY) */
4357 static void gen_tlbie(DisasContext
*ctx
)
4359 #if defined(CONFIG_USER_ONLY)
4364 if (NARROW_MODE(ctx
)) {
4365 TCGv t0
= tcg_temp_new();
4366 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
4367 gen_helper_tlbie(cpu_env
, t0
);
4370 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4372 #endif /* defined(CONFIG_USER_ONLY) */
4376 static void gen_tlbsync(DisasContext
*ctx
)
4378 #if defined(CONFIG_USER_ONLY)
4383 /* tlbsync is a nop for server, ptesync handles delayed tlb flush,
4384 * embedded however needs to deal with tlbsync. We don't try to be
4385 * fancy and swallow the overhead of checking for both.
4387 gen_check_tlb_flush(ctx
);
4388 #endif /* defined(CONFIG_USER_ONLY) */
4391 #if defined(TARGET_PPC64)
4393 static void gen_slbia(DisasContext
*ctx
)
4395 #if defined(CONFIG_USER_ONLY)
4400 gen_helper_slbia(cpu_env
);
4401 #endif /* defined(CONFIG_USER_ONLY) */
4405 static void gen_slbie(DisasContext
*ctx
)
4407 #if defined(CONFIG_USER_ONLY)
4412 gen_helper_slbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4413 #endif /* defined(CONFIG_USER_ONLY) */
4415 #endif /* defined(TARGET_PPC64) */
4417 /*** External control ***/
4421 static void gen_eciwx(DisasContext
*ctx
)
4424 /* Should check EAR[E] ! */
4425 gen_set_access_type(ctx
, ACCESS_EXT
);
4426 t0
= tcg_temp_new();
4427 gen_addr_reg_index(ctx
, t0
);
4428 gen_check_align(ctx
, t0
, 0x03);
4429 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
4434 static void gen_ecowx(DisasContext
*ctx
)
4437 /* Should check EAR[E] ! */
4438 gen_set_access_type(ctx
, ACCESS_EXT
);
4439 t0
= tcg_temp_new();
4440 gen_addr_reg_index(ctx
, t0
);
4441 gen_check_align(ctx
, t0
, 0x03);
4442 gen_qemu_st32(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
4446 /* PowerPC 601 specific instructions */
4449 static void gen_abs(DisasContext
*ctx
)
4451 TCGLabel
*l1
= gen_new_label();
4452 TCGLabel
*l2
= gen_new_label();
4453 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4454 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4457 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4459 if (unlikely(Rc(ctx
->opcode
) != 0))
4460 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4464 static void gen_abso(DisasContext
*ctx
)
4466 TCGLabel
*l1
= gen_new_label();
4467 TCGLabel
*l2
= gen_new_label();
4468 TCGLabel
*l3
= gen_new_label();
4469 /* Start with XER OV disabled, the most likely case */
4470 tcg_gen_movi_tl(cpu_ov
, 0);
4471 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l2
);
4472 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[rA(ctx
->opcode
)], 0x80000000, l1
);
4473 tcg_gen_movi_tl(cpu_ov
, 1);
4474 tcg_gen_movi_tl(cpu_so
, 1);
4477 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4480 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4482 if (unlikely(Rc(ctx
->opcode
) != 0))
4483 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4487 static void gen_clcs(DisasContext
*ctx
)
4489 TCGv_i32 t0
= tcg_const_i32(rA(ctx
->opcode
));
4490 gen_helper_clcs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4491 tcg_temp_free_i32(t0
);
4492 /* Rc=1 sets CR0 to an undefined state */
4496 static void gen_div(DisasContext
*ctx
)
4498 gen_helper_div(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4499 cpu_gpr
[rB(ctx
->opcode
)]);
4500 if (unlikely(Rc(ctx
->opcode
) != 0))
4501 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4505 static void gen_divo(DisasContext
*ctx
)
4507 gen_helper_divo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4508 cpu_gpr
[rB(ctx
->opcode
)]);
4509 if (unlikely(Rc(ctx
->opcode
) != 0))
4510 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4514 static void gen_divs(DisasContext
*ctx
)
4516 gen_helper_divs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4517 cpu_gpr
[rB(ctx
->opcode
)]);
4518 if (unlikely(Rc(ctx
->opcode
) != 0))
4519 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4522 /* divso - divso. */
4523 static void gen_divso(DisasContext
*ctx
)
4525 gen_helper_divso(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
4526 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4527 if (unlikely(Rc(ctx
->opcode
) != 0))
4528 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4532 static void gen_doz(DisasContext
*ctx
)
4534 TCGLabel
*l1
= gen_new_label();
4535 TCGLabel
*l2
= gen_new_label();
4536 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
4537 tcg_gen_sub_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4540 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4542 if (unlikely(Rc(ctx
->opcode
) != 0))
4543 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4547 static void gen_dozo(DisasContext
*ctx
)
4549 TCGLabel
*l1
= gen_new_label();
4550 TCGLabel
*l2
= gen_new_label();
4551 TCGv t0
= tcg_temp_new();
4552 TCGv t1
= tcg_temp_new();
4553 TCGv t2
= tcg_temp_new();
4554 /* Start with XER OV disabled, the most likely case */
4555 tcg_gen_movi_tl(cpu_ov
, 0);
4556 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
4557 tcg_gen_sub_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4558 tcg_gen_xor_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4559 tcg_gen_xor_tl(t2
, cpu_gpr
[rA(ctx
->opcode
)], t0
);
4560 tcg_gen_andc_tl(t1
, t1
, t2
);
4561 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4562 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
4563 tcg_gen_movi_tl(cpu_ov
, 1);
4564 tcg_gen_movi_tl(cpu_so
, 1);
4567 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4572 if (unlikely(Rc(ctx
->opcode
) != 0))
4573 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4577 static void gen_dozi(DisasContext
*ctx
)
4579 target_long simm
= SIMM(ctx
->opcode
);
4580 TCGLabel
*l1
= gen_new_label();
4581 TCGLabel
*l2
= gen_new_label();
4582 tcg_gen_brcondi_tl(TCG_COND_LT
, cpu_gpr
[rA(ctx
->opcode
)], simm
, l1
);
4583 tcg_gen_subfi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
, cpu_gpr
[rA(ctx
->opcode
)]);
4586 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4588 if (unlikely(Rc(ctx
->opcode
) != 0))
4589 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4592 /* lscbx - lscbx. */
4593 static void gen_lscbx(DisasContext
*ctx
)
4595 TCGv t0
= tcg_temp_new();
4596 TCGv_i32 t1
= tcg_const_i32(rD(ctx
->opcode
));
4597 TCGv_i32 t2
= tcg_const_i32(rA(ctx
->opcode
));
4598 TCGv_i32 t3
= tcg_const_i32(rB(ctx
->opcode
));
4600 gen_addr_reg_index(ctx
, t0
);
4601 /* NIP cannot be restored if the memory exception comes from an helper */
4602 gen_update_nip(ctx
, ctx
->nip
- 4);
4603 gen_helper_lscbx(t0
, cpu_env
, t0
, t1
, t2
, t3
);
4604 tcg_temp_free_i32(t1
);
4605 tcg_temp_free_i32(t2
);
4606 tcg_temp_free_i32(t3
);
4607 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~0x7F);
4608 tcg_gen_or_tl(cpu_xer
, cpu_xer
, t0
);
4609 if (unlikely(Rc(ctx
->opcode
) != 0))
4610 gen_set_Rc0(ctx
, t0
);
4614 /* maskg - maskg. */
4615 static void gen_maskg(DisasContext
*ctx
)
4617 TCGLabel
*l1
= gen_new_label();
4618 TCGv t0
= tcg_temp_new();
4619 TCGv t1
= tcg_temp_new();
4620 TCGv t2
= tcg_temp_new();
4621 TCGv t3
= tcg_temp_new();
4622 tcg_gen_movi_tl(t3
, 0xFFFFFFFF);
4623 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4624 tcg_gen_andi_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 0x1F);
4625 tcg_gen_addi_tl(t2
, t0
, 1);
4626 tcg_gen_shr_tl(t2
, t3
, t2
);
4627 tcg_gen_shr_tl(t3
, t3
, t1
);
4628 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], t2
, t3
);
4629 tcg_gen_brcond_tl(TCG_COND_GE
, t0
, t1
, l1
);
4630 tcg_gen_neg_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4636 if (unlikely(Rc(ctx
->opcode
) != 0))
4637 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4640 /* maskir - maskir. */
4641 static void gen_maskir(DisasContext
*ctx
)
4643 TCGv t0
= tcg_temp_new();
4644 TCGv t1
= tcg_temp_new();
4645 tcg_gen_and_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4646 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4647 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4650 if (unlikely(Rc(ctx
->opcode
) != 0))
4651 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4655 static void gen_mul(DisasContext
*ctx
)
4657 TCGv_i64 t0
= tcg_temp_new_i64();
4658 TCGv_i64 t1
= tcg_temp_new_i64();
4659 TCGv t2
= tcg_temp_new();
4660 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
4661 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
4662 tcg_gen_mul_i64(t0
, t0
, t1
);
4663 tcg_gen_trunc_i64_tl(t2
, t0
);
4664 gen_store_spr(SPR_MQ
, t2
);
4665 tcg_gen_shri_i64(t1
, t0
, 32);
4666 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
4667 tcg_temp_free_i64(t0
);
4668 tcg_temp_free_i64(t1
);
4670 if (unlikely(Rc(ctx
->opcode
) != 0))
4671 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4675 static void gen_mulo(DisasContext
*ctx
)
4677 TCGLabel
*l1
= gen_new_label();
4678 TCGv_i64 t0
= tcg_temp_new_i64();
4679 TCGv_i64 t1
= tcg_temp_new_i64();
4680 TCGv t2
= tcg_temp_new();
4681 /* Start with XER OV disabled, the most likely case */
4682 tcg_gen_movi_tl(cpu_ov
, 0);
4683 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
4684 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
4685 tcg_gen_mul_i64(t0
, t0
, t1
);
4686 tcg_gen_trunc_i64_tl(t2
, t0
);
4687 gen_store_spr(SPR_MQ
, t2
);
4688 tcg_gen_shri_i64(t1
, t0
, 32);
4689 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
4690 tcg_gen_ext32s_i64(t1
, t0
);
4691 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, t1
, l1
);
4692 tcg_gen_movi_tl(cpu_ov
, 1);
4693 tcg_gen_movi_tl(cpu_so
, 1);
4695 tcg_temp_free_i64(t0
);
4696 tcg_temp_free_i64(t1
);
4698 if (unlikely(Rc(ctx
->opcode
) != 0))
4699 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4703 static void gen_nabs(DisasContext
*ctx
)
4705 TCGLabel
*l1
= gen_new_label();
4706 TCGLabel
*l2
= gen_new_label();
4707 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4708 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4711 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4713 if (unlikely(Rc(ctx
->opcode
) != 0))
4714 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4717 /* nabso - nabso. */
4718 static void gen_nabso(DisasContext
*ctx
)
4720 TCGLabel
*l1
= gen_new_label();
4721 TCGLabel
*l2
= gen_new_label();
4722 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4723 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4726 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4728 /* nabs never overflows */
4729 tcg_gen_movi_tl(cpu_ov
, 0);
4730 if (unlikely(Rc(ctx
->opcode
) != 0))
4731 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4735 static void gen_rlmi(DisasContext
*ctx
)
4737 uint32_t mb
= MB(ctx
->opcode
);
4738 uint32_t me
= ME(ctx
->opcode
);
4739 TCGv t0
= tcg_temp_new();
4740 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4741 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4742 tcg_gen_andi_tl(t0
, t0
, MASK(mb
, me
));
4743 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~MASK(mb
, me
));
4744 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], t0
);
4746 if (unlikely(Rc(ctx
->opcode
) != 0))
4747 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4751 static void gen_rrib(DisasContext
*ctx
)
4753 TCGv t0
= tcg_temp_new();
4754 TCGv t1
= tcg_temp_new();
4755 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4756 tcg_gen_movi_tl(t1
, 0x80000000);
4757 tcg_gen_shr_tl(t1
, t1
, t0
);
4758 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4759 tcg_gen_and_tl(t0
, t0
, t1
);
4760 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], t1
);
4761 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4764 if (unlikely(Rc(ctx
->opcode
) != 0))
4765 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4769 static void gen_sle(DisasContext
*ctx
)
4771 TCGv t0
= tcg_temp_new();
4772 TCGv t1
= tcg_temp_new();
4773 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4774 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4775 tcg_gen_subfi_tl(t1
, 32, t1
);
4776 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4777 tcg_gen_or_tl(t1
, t0
, t1
);
4778 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4779 gen_store_spr(SPR_MQ
, t1
);
4782 if (unlikely(Rc(ctx
->opcode
) != 0))
4783 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4787 static void gen_sleq(DisasContext
*ctx
)
4789 TCGv t0
= tcg_temp_new();
4790 TCGv t1
= tcg_temp_new();
4791 TCGv t2
= tcg_temp_new();
4792 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4793 tcg_gen_movi_tl(t2
, 0xFFFFFFFF);
4794 tcg_gen_shl_tl(t2
, t2
, t0
);
4795 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4796 gen_load_spr(t1
, SPR_MQ
);
4797 gen_store_spr(SPR_MQ
, t0
);
4798 tcg_gen_and_tl(t0
, t0
, t2
);
4799 tcg_gen_andc_tl(t1
, t1
, t2
);
4800 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4804 if (unlikely(Rc(ctx
->opcode
) != 0))
4805 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4809 static void gen_sliq(DisasContext
*ctx
)
4811 int sh
= SH(ctx
->opcode
);
4812 TCGv t0
= tcg_temp_new();
4813 TCGv t1
= tcg_temp_new();
4814 tcg_gen_shli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
4815 tcg_gen_shri_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
4816 tcg_gen_or_tl(t1
, t0
, t1
);
4817 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4818 gen_store_spr(SPR_MQ
, t1
);
4821 if (unlikely(Rc(ctx
->opcode
) != 0))
4822 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4825 /* slliq - slliq. */
4826 static void gen_slliq(DisasContext
*ctx
)
4828 int sh
= SH(ctx
->opcode
);
4829 TCGv t0
= tcg_temp_new();
4830 TCGv t1
= tcg_temp_new();
4831 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
4832 gen_load_spr(t1
, SPR_MQ
);
4833 gen_store_spr(SPR_MQ
, t0
);
4834 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
<< sh
));
4835 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
<< sh
));
4836 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4839 if (unlikely(Rc(ctx
->opcode
) != 0))
4840 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4844 static void gen_sllq(DisasContext
*ctx
)
4846 TCGLabel
*l1
= gen_new_label();
4847 TCGLabel
*l2
= gen_new_label();
4848 TCGv t0
= tcg_temp_local_new();
4849 TCGv t1
= tcg_temp_local_new();
4850 TCGv t2
= tcg_temp_local_new();
4851 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4852 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
4853 tcg_gen_shl_tl(t1
, t1
, t2
);
4854 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
4855 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
4856 gen_load_spr(t0
, SPR_MQ
);
4857 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4860 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
4861 gen_load_spr(t2
, SPR_MQ
);
4862 tcg_gen_andc_tl(t1
, t2
, t1
);
4863 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4868 if (unlikely(Rc(ctx
->opcode
) != 0))
4869 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4873 static void gen_slq(DisasContext
*ctx
)
4875 TCGLabel
*l1
= gen_new_label();
4876 TCGv t0
= tcg_temp_new();
4877 TCGv t1
= tcg_temp_new();
4878 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4879 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4880 tcg_gen_subfi_tl(t1
, 32, t1
);
4881 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4882 tcg_gen_or_tl(t1
, t0
, t1
);
4883 gen_store_spr(SPR_MQ
, t1
);
4884 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
4885 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4886 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
4887 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
4891 if (unlikely(Rc(ctx
->opcode
) != 0))
4892 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4895 /* sraiq - sraiq. */
4896 static void gen_sraiq(DisasContext
*ctx
)
4898 int sh
= SH(ctx
->opcode
);
4899 TCGLabel
*l1
= gen_new_label();
4900 TCGv t0
= tcg_temp_new();
4901 TCGv t1
= tcg_temp_new();
4902 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
4903 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
4904 tcg_gen_or_tl(t0
, t0
, t1
);
4905 gen_store_spr(SPR_MQ
, t0
);
4906 tcg_gen_movi_tl(cpu_ca
, 0);
4907 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
4908 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rS(ctx
->opcode
)], 0, l1
);
4909 tcg_gen_movi_tl(cpu_ca
, 1);
4911 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
4914 if (unlikely(Rc(ctx
->opcode
) != 0))
4915 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4919 static void gen_sraq(DisasContext
*ctx
)
4921 TCGLabel
*l1
= gen_new_label();
4922 TCGLabel
*l2
= gen_new_label();
4923 TCGv t0
= tcg_temp_new();
4924 TCGv t1
= tcg_temp_local_new();
4925 TCGv t2
= tcg_temp_local_new();
4926 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4927 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
4928 tcg_gen_sar_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
4929 tcg_gen_subfi_tl(t2
, 32, t2
);
4930 tcg_gen_shl_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
4931 tcg_gen_or_tl(t0
, t0
, t2
);
4932 gen_store_spr(SPR_MQ
, t0
);
4933 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
4934 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l1
);
4935 tcg_gen_mov_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)]);
4936 tcg_gen_sari_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 31);
4939 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t1
);
4940 tcg_gen_movi_tl(cpu_ca
, 0);
4941 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
4942 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l2
);
4943 tcg_gen_movi_tl(cpu_ca
, 1);
4947 if (unlikely(Rc(ctx
->opcode
) != 0))
4948 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4952 static void gen_sre(DisasContext
*ctx
)
4954 TCGv t0
= tcg_temp_new();
4955 TCGv t1
= tcg_temp_new();
4956 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4957 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4958 tcg_gen_subfi_tl(t1
, 32, t1
);
4959 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4960 tcg_gen_or_tl(t1
, t0
, t1
);
4961 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4962 gen_store_spr(SPR_MQ
, t1
);
4965 if (unlikely(Rc(ctx
->opcode
) != 0))
4966 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4970 static void gen_srea(DisasContext
*ctx
)
4972 TCGv t0
= tcg_temp_new();
4973 TCGv t1
= tcg_temp_new();
4974 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4975 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4976 gen_store_spr(SPR_MQ
, t0
);
4977 tcg_gen_sar_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], t1
);
4980 if (unlikely(Rc(ctx
->opcode
) != 0))
4981 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4985 static void gen_sreq(DisasContext
*ctx
)
4987 TCGv t0
= tcg_temp_new();
4988 TCGv t1
= tcg_temp_new();
4989 TCGv t2
= tcg_temp_new();
4990 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4991 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
4992 tcg_gen_shr_tl(t1
, t1
, t0
);
4993 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4994 gen_load_spr(t2
, SPR_MQ
);
4995 gen_store_spr(SPR_MQ
, t0
);
4996 tcg_gen_and_tl(t0
, t0
, t1
);
4997 tcg_gen_andc_tl(t2
, t2
, t1
);
4998 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5002 if (unlikely(Rc(ctx
->opcode
) != 0))
5003 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5007 static void gen_sriq(DisasContext
*ctx
)
5009 int sh
= SH(ctx
->opcode
);
5010 TCGv t0
= tcg_temp_new();
5011 TCGv t1
= tcg_temp_new();
5012 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5013 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5014 tcg_gen_or_tl(t1
, t0
, t1
);
5015 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5016 gen_store_spr(SPR_MQ
, t1
);
5019 if (unlikely(Rc(ctx
->opcode
) != 0))
5020 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5024 static void gen_srliq(DisasContext
*ctx
)
5026 int sh
= SH(ctx
->opcode
);
5027 TCGv t0
= tcg_temp_new();
5028 TCGv t1
= tcg_temp_new();
5029 tcg_gen_rotri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5030 gen_load_spr(t1
, SPR_MQ
);
5031 gen_store_spr(SPR_MQ
, t0
);
5032 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
>> sh
));
5033 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
>> sh
));
5034 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5037 if (unlikely(Rc(ctx
->opcode
) != 0))
5038 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5042 static void gen_srlq(DisasContext
*ctx
)
5044 TCGLabel
*l1
= gen_new_label();
5045 TCGLabel
*l2
= gen_new_label();
5046 TCGv t0
= tcg_temp_local_new();
5047 TCGv t1
= tcg_temp_local_new();
5048 TCGv t2
= tcg_temp_local_new();
5049 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5050 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5051 tcg_gen_shr_tl(t2
, t1
, t2
);
5052 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5053 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5054 gen_load_spr(t0
, SPR_MQ
);
5055 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5058 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5059 tcg_gen_and_tl(t0
, t0
, t2
);
5060 gen_load_spr(t1
, SPR_MQ
);
5061 tcg_gen_andc_tl(t1
, t1
, t2
);
5062 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5067 if (unlikely(Rc(ctx
->opcode
) != 0))
5068 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5072 static void gen_srq(DisasContext
*ctx
)
5074 TCGLabel
*l1
= gen_new_label();
5075 TCGv t0
= tcg_temp_new();
5076 TCGv t1
= tcg_temp_new();
5077 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5078 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5079 tcg_gen_subfi_tl(t1
, 32, t1
);
5080 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5081 tcg_gen_or_tl(t1
, t0
, t1
);
5082 gen_store_spr(SPR_MQ
, t1
);
5083 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5084 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5085 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5086 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5090 if (unlikely(Rc(ctx
->opcode
) != 0))
5091 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5094 /* PowerPC 602 specific instructions */
5097 static void gen_dsa(DisasContext
*ctx
)
5100 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5104 static void gen_esa(DisasContext
*ctx
)
5107 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5111 static void gen_mfrom(DisasContext
*ctx
)
5113 #if defined(CONFIG_USER_ONLY)
5117 gen_helper_602_mfrom(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5118 #endif /* defined(CONFIG_USER_ONLY) */
5121 /* 602 - 603 - G2 TLB management */
5124 static void gen_tlbld_6xx(DisasContext
*ctx
)
5126 #if defined(CONFIG_USER_ONLY)
5130 gen_helper_6xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5131 #endif /* defined(CONFIG_USER_ONLY) */
5135 static void gen_tlbli_6xx(DisasContext
*ctx
)
5137 #if defined(CONFIG_USER_ONLY)
5141 gen_helper_6xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5142 #endif /* defined(CONFIG_USER_ONLY) */
5145 /* 74xx TLB management */
5148 static void gen_tlbld_74xx(DisasContext
*ctx
)
5150 #if defined(CONFIG_USER_ONLY)
5154 gen_helper_74xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5155 #endif /* defined(CONFIG_USER_ONLY) */
5159 static void gen_tlbli_74xx(DisasContext
*ctx
)
5161 #if defined(CONFIG_USER_ONLY)
5165 gen_helper_74xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5166 #endif /* defined(CONFIG_USER_ONLY) */
5169 /* POWER instructions not in PowerPC 601 */
5172 static void gen_clf(DisasContext
*ctx
)
5174 /* Cache line flush: implemented as no-op */
5178 static void gen_cli(DisasContext
*ctx
)
5180 #if defined(CONFIG_USER_ONLY)
5183 /* Cache line invalidate: privileged and treated as no-op */
5185 #endif /* defined(CONFIG_USER_ONLY) */
5189 static void gen_dclst(DisasContext
*ctx
)
5191 /* Data cache line store: treated as no-op */
5194 static void gen_mfsri(DisasContext
*ctx
)
5196 #if defined(CONFIG_USER_ONLY)
5199 int ra
= rA(ctx
->opcode
);
5200 int rd
= rD(ctx
->opcode
);
5204 t0
= tcg_temp_new();
5205 gen_addr_reg_index(ctx
, t0
);
5206 tcg_gen_shri_tl(t0
, t0
, 28);
5207 tcg_gen_andi_tl(t0
, t0
, 0xF);
5208 gen_helper_load_sr(cpu_gpr
[rd
], cpu_env
, t0
);
5210 if (ra
!= 0 && ra
!= rd
)
5211 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rd
]);
5212 #endif /* defined(CONFIG_USER_ONLY) */
5215 static void gen_rac(DisasContext
*ctx
)
5217 #if defined(CONFIG_USER_ONLY)
5223 t0
= tcg_temp_new();
5224 gen_addr_reg_index(ctx
, t0
);
5225 gen_helper_rac(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5227 #endif /* defined(CONFIG_USER_ONLY) */
5230 static void gen_rfsvc(DisasContext
*ctx
)
5232 #if defined(CONFIG_USER_ONLY)
5237 gen_helper_rfsvc(cpu_env
);
5238 gen_sync_exception(ctx
);
5239 #endif /* defined(CONFIG_USER_ONLY) */
5242 #include "translate/fp-impl.c"
5244 #include "translate/vmx-impl.c"
5246 /* svc is not implemented for now */
5248 /* BookE specific instructions */
5250 /* XXX: not implemented on 440 ? */
5251 static void gen_mfapidi(DisasContext
*ctx
)
5254 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5257 /* XXX: not implemented on 440 ? */
5258 static void gen_tlbiva(DisasContext
*ctx
)
5260 #if defined(CONFIG_USER_ONLY)
5266 t0
= tcg_temp_new();
5267 gen_addr_reg_index(ctx
, t0
);
5268 gen_helper_tlbiva(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5270 #endif /* defined(CONFIG_USER_ONLY) */
5273 /* All 405 MAC instructions are translated here */
5274 static inline void gen_405_mulladd_insn(DisasContext
*ctx
, int opc2
, int opc3
,
5275 int ra
, int rb
, int rt
, int Rc
)
5279 t0
= tcg_temp_local_new();
5280 t1
= tcg_temp_local_new();
5282 switch (opc3
& 0x0D) {
5284 /* macchw - macchw. - macchwo - macchwo. */
5285 /* macchws - macchws. - macchwso - macchwso. */
5286 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5287 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5288 /* mulchw - mulchw. */
5289 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5290 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5291 tcg_gen_ext16s_tl(t1
, t1
);
5294 /* macchwu - macchwu. - macchwuo - macchwuo. */
5295 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5296 /* mulchwu - mulchwu. */
5297 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5298 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5299 tcg_gen_ext16u_tl(t1
, t1
);
5302 /* machhw - machhw. - machhwo - machhwo. */
5303 /* machhws - machhws. - machhwso - machhwso. */
5304 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5305 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5306 /* mulhhw - mulhhw. */
5307 tcg_gen_sari_tl(t0
, cpu_gpr
[ra
], 16);
5308 tcg_gen_ext16s_tl(t0
, t0
);
5309 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5310 tcg_gen_ext16s_tl(t1
, t1
);
5313 /* machhwu - machhwu. - machhwuo - machhwuo. */
5314 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5315 /* mulhhwu - mulhhwu. */
5316 tcg_gen_shri_tl(t0
, cpu_gpr
[ra
], 16);
5317 tcg_gen_ext16u_tl(t0
, t0
);
5318 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5319 tcg_gen_ext16u_tl(t1
, t1
);
5322 /* maclhw - maclhw. - maclhwo - maclhwo. */
5323 /* maclhws - maclhws. - maclhwso - maclhwso. */
5324 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5325 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5326 /* mullhw - mullhw. */
5327 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5328 tcg_gen_ext16s_tl(t1
, cpu_gpr
[rb
]);
5331 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5332 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5333 /* mullhwu - mullhwu. */
5334 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5335 tcg_gen_ext16u_tl(t1
, cpu_gpr
[rb
]);
5339 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5340 tcg_gen_mul_tl(t1
, t0
, t1
);
5342 /* nmultiply-and-accumulate (0x0E) */
5343 tcg_gen_sub_tl(t0
, cpu_gpr
[rt
], t1
);
5345 /* multiply-and-accumulate (0x0C) */
5346 tcg_gen_add_tl(t0
, cpu_gpr
[rt
], t1
);
5350 /* Check overflow and/or saturate */
5351 TCGLabel
*l1
= gen_new_label();
5354 /* Start with XER OV disabled, the most likely case */
5355 tcg_gen_movi_tl(cpu_ov
, 0);
5359 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t1
);
5360 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
5361 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t0
);
5362 tcg_gen_brcondi_tl(TCG_COND_LT
, t1
, 0, l1
);
5365 tcg_gen_sari_tl(t0
, cpu_gpr
[rt
], 31);
5366 tcg_gen_xori_tl(t0
, t0
, 0x7fffffff);
5370 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
5373 tcg_gen_movi_tl(t0
, UINT32_MAX
);
5377 /* Check overflow */
5378 tcg_gen_movi_tl(cpu_ov
, 1);
5379 tcg_gen_movi_tl(cpu_so
, 1);
5382 tcg_gen_mov_tl(cpu_gpr
[rt
], t0
);
5385 tcg_gen_mul_tl(cpu_gpr
[rt
], t0
, t1
);
5389 if (unlikely(Rc
) != 0) {
5391 gen_set_Rc0(ctx
, cpu_gpr
[rt
]);
5395 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5396 static void glue(gen_, name)(DisasContext *ctx) \
5398 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5399 rD(ctx->opcode), Rc(ctx->opcode)); \
5402 /* macchw - macchw. */
5403 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05);
5404 /* macchwo - macchwo. */
5405 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15);
5406 /* macchws - macchws. */
5407 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07);
5408 /* macchwso - macchwso. */
5409 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17);
5410 /* macchwsu - macchwsu. */
5411 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06);
5412 /* macchwsuo - macchwsuo. */
5413 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16);
5414 /* macchwu - macchwu. */
5415 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04);
5416 /* macchwuo - macchwuo. */
5417 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14);
5418 /* machhw - machhw. */
5419 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01);
5420 /* machhwo - machhwo. */
5421 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11);
5422 /* machhws - machhws. */
5423 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03);
5424 /* machhwso - machhwso. */
5425 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13);
5426 /* machhwsu - machhwsu. */
5427 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02);
5428 /* machhwsuo - machhwsuo. */
5429 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12);
5430 /* machhwu - machhwu. */
5431 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00);
5432 /* machhwuo - machhwuo. */
5433 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10);
5434 /* maclhw - maclhw. */
5435 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D);
5436 /* maclhwo - maclhwo. */
5437 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D);
5438 /* maclhws - maclhws. */
5439 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F);
5440 /* maclhwso - maclhwso. */
5441 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F);
5442 /* maclhwu - maclhwu. */
5443 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C);
5444 /* maclhwuo - maclhwuo. */
5445 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C);
5446 /* maclhwsu - maclhwsu. */
5447 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E);
5448 /* maclhwsuo - maclhwsuo. */
5449 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E);
5450 /* nmacchw - nmacchw. */
5451 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05);
5452 /* nmacchwo - nmacchwo. */
5453 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15);
5454 /* nmacchws - nmacchws. */
5455 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07);
5456 /* nmacchwso - nmacchwso. */
5457 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17);
5458 /* nmachhw - nmachhw. */
5459 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01);
5460 /* nmachhwo - nmachhwo. */
5461 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11);
5462 /* nmachhws - nmachhws. */
5463 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03);
5464 /* nmachhwso - nmachhwso. */
5465 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13);
5466 /* nmaclhw - nmaclhw. */
5467 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D);
5468 /* nmaclhwo - nmaclhwo. */
5469 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D);
5470 /* nmaclhws - nmaclhws. */
5471 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F);
5472 /* nmaclhwso - nmaclhwso. */
5473 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F);
5475 /* mulchw - mulchw. */
5476 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05);
5477 /* mulchwu - mulchwu. */
5478 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04);
5479 /* mulhhw - mulhhw. */
5480 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01);
5481 /* mulhhwu - mulhhwu. */
5482 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00);
5483 /* mullhw - mullhw. */
5484 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D);
5485 /* mullhwu - mullhwu. */
5486 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C);
5489 static void gen_mfdcr(DisasContext
*ctx
)
5491 #if defined(CONFIG_USER_ONLY)
5497 /* NIP cannot be restored if the memory exception comes from an helper */
5498 gen_update_nip(ctx
, ctx
->nip
- 4);
5499 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
5500 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, dcrn
);
5501 tcg_temp_free(dcrn
);
5502 #endif /* defined(CONFIG_USER_ONLY) */
5506 static void gen_mtdcr(DisasContext
*ctx
)
5508 #if defined(CONFIG_USER_ONLY)
5514 /* NIP cannot be restored if the memory exception comes from an helper */
5515 gen_update_nip(ctx
, ctx
->nip
- 4);
5516 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
5517 gen_helper_store_dcr(cpu_env
, dcrn
, cpu_gpr
[rS(ctx
->opcode
)]);
5518 tcg_temp_free(dcrn
);
5519 #endif /* defined(CONFIG_USER_ONLY) */
5523 /* XXX: not implemented on 440 ? */
5524 static void gen_mfdcrx(DisasContext
*ctx
)
5526 #if defined(CONFIG_USER_ONLY)
5530 /* NIP cannot be restored if the memory exception comes from an helper */
5531 gen_update_nip(ctx
, ctx
->nip
- 4);
5532 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5533 cpu_gpr
[rA(ctx
->opcode
)]);
5534 /* Note: Rc update flag set leads to undefined state of Rc0 */
5535 #endif /* defined(CONFIG_USER_ONLY) */
5539 /* XXX: not implemented on 440 ? */
5540 static void gen_mtdcrx(DisasContext
*ctx
)
5542 #if defined(CONFIG_USER_ONLY)
5546 /* NIP cannot be restored if the memory exception comes from an helper */
5547 gen_update_nip(ctx
, ctx
->nip
- 4);
5548 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5549 cpu_gpr
[rS(ctx
->opcode
)]);
5550 /* Note: Rc update flag set leads to undefined state of Rc0 */
5551 #endif /* defined(CONFIG_USER_ONLY) */
5554 /* mfdcrux (PPC 460) : user-mode access to DCR */
5555 static void gen_mfdcrux(DisasContext
*ctx
)
5557 /* NIP cannot be restored if the memory exception comes from an helper */
5558 gen_update_nip(ctx
, ctx
->nip
- 4);
5559 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5560 cpu_gpr
[rA(ctx
->opcode
)]);
5561 /* Note: Rc update flag set leads to undefined state of Rc0 */
5564 /* mtdcrux (PPC 460) : user-mode access to DCR */
5565 static void gen_mtdcrux(DisasContext
*ctx
)
5567 /* NIP cannot be restored if the memory exception comes from an helper */
5568 gen_update_nip(ctx
, ctx
->nip
- 4);
5569 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5570 cpu_gpr
[rS(ctx
->opcode
)]);
5571 /* Note: Rc update flag set leads to undefined state of Rc0 */
5575 static void gen_dccci(DisasContext
*ctx
)
5578 /* interpreted as no-op */
5582 static void gen_dcread(DisasContext
*ctx
)
5584 #if defined(CONFIG_USER_ONLY)
5590 gen_set_access_type(ctx
, ACCESS_CACHE
);
5591 EA
= tcg_temp_new();
5592 gen_addr_reg_index(ctx
, EA
);
5593 val
= tcg_temp_new();
5594 gen_qemu_ld32u(ctx
, val
, EA
);
5596 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], EA
);
5598 #endif /* defined(CONFIG_USER_ONLY) */
5602 static void gen_icbt_40x(DisasContext
*ctx
)
5604 /* interpreted as no-op */
5605 /* XXX: specification say this is treated as a load by the MMU
5606 * but does not generate any exception
5611 static void gen_iccci(DisasContext
*ctx
)
5614 /* interpreted as no-op */
5618 static void gen_icread(DisasContext
*ctx
)
5621 /* interpreted as no-op */
5624 /* rfci (supervisor only) */
5625 static void gen_rfci_40x(DisasContext
*ctx
)
5627 #if defined(CONFIG_USER_ONLY)
5631 /* Restore CPU state */
5632 gen_helper_40x_rfci(cpu_env
);
5633 gen_sync_exception(ctx
);
5634 #endif /* defined(CONFIG_USER_ONLY) */
5637 static void gen_rfci(DisasContext
*ctx
)
5639 #if defined(CONFIG_USER_ONLY)
5643 /* Restore CPU state */
5644 gen_helper_rfci(cpu_env
);
5645 gen_sync_exception(ctx
);
5646 #endif /* defined(CONFIG_USER_ONLY) */
5649 /* BookE specific */
5651 /* XXX: not implemented on 440 ? */
5652 static void gen_rfdi(DisasContext
*ctx
)
5654 #if defined(CONFIG_USER_ONLY)
5658 /* Restore CPU state */
5659 gen_helper_rfdi(cpu_env
);
5660 gen_sync_exception(ctx
);
5661 #endif /* defined(CONFIG_USER_ONLY) */
5664 /* XXX: not implemented on 440 ? */
5665 static void gen_rfmci(DisasContext
*ctx
)
5667 #if defined(CONFIG_USER_ONLY)
5671 /* Restore CPU state */
5672 gen_helper_rfmci(cpu_env
);
5673 gen_sync_exception(ctx
);
5674 #endif /* defined(CONFIG_USER_ONLY) */
5677 /* TLB management - PowerPC 405 implementation */
5680 static void gen_tlbre_40x(DisasContext
*ctx
)
5682 #if defined(CONFIG_USER_ONLY)
5686 switch (rB(ctx
->opcode
)) {
5688 gen_helper_4xx_tlbre_hi(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5689 cpu_gpr
[rA(ctx
->opcode
)]);
5692 gen_helper_4xx_tlbre_lo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5693 cpu_gpr
[rA(ctx
->opcode
)]);
5696 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5699 #endif /* defined(CONFIG_USER_ONLY) */
5702 /* tlbsx - tlbsx. */
5703 static void gen_tlbsx_40x(DisasContext
*ctx
)
5705 #if defined(CONFIG_USER_ONLY)
5711 t0
= tcg_temp_new();
5712 gen_addr_reg_index(ctx
, t0
);
5713 gen_helper_4xx_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5715 if (Rc(ctx
->opcode
)) {
5716 TCGLabel
*l1
= gen_new_label();
5717 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
5718 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
5719 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
5722 #endif /* defined(CONFIG_USER_ONLY) */
5726 static void gen_tlbwe_40x(DisasContext
*ctx
)
5728 #if defined(CONFIG_USER_ONLY)
5733 switch (rB(ctx
->opcode
)) {
5735 gen_helper_4xx_tlbwe_hi(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5736 cpu_gpr
[rS(ctx
->opcode
)]);
5739 gen_helper_4xx_tlbwe_lo(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5740 cpu_gpr
[rS(ctx
->opcode
)]);
5743 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5746 #endif /* defined(CONFIG_USER_ONLY) */
5749 /* TLB management - PowerPC 440 implementation */
5752 static void gen_tlbre_440(DisasContext
*ctx
)
5754 #if defined(CONFIG_USER_ONLY)
5759 switch (rB(ctx
->opcode
)) {
5764 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
5765 gen_helper_440_tlbre(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5766 t0
, cpu_gpr
[rA(ctx
->opcode
)]);
5767 tcg_temp_free_i32(t0
);
5771 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5774 #endif /* defined(CONFIG_USER_ONLY) */
5777 /* tlbsx - tlbsx. */
5778 static void gen_tlbsx_440(DisasContext
*ctx
)
5780 #if defined(CONFIG_USER_ONLY)
5786 t0
= tcg_temp_new();
5787 gen_addr_reg_index(ctx
, t0
);
5788 gen_helper_440_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5790 if (Rc(ctx
->opcode
)) {
5791 TCGLabel
*l1
= gen_new_label();
5792 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
5793 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
5794 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
5797 #endif /* defined(CONFIG_USER_ONLY) */
5801 static void gen_tlbwe_440(DisasContext
*ctx
)
5803 #if defined(CONFIG_USER_ONLY)
5807 switch (rB(ctx
->opcode
)) {
5812 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
5813 gen_helper_440_tlbwe(cpu_env
, t0
, cpu_gpr
[rA(ctx
->opcode
)],
5814 cpu_gpr
[rS(ctx
->opcode
)]);
5815 tcg_temp_free_i32(t0
);
5819 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5822 #endif /* defined(CONFIG_USER_ONLY) */
5825 /* TLB management - PowerPC BookE 2.06 implementation */
5828 static void gen_tlbre_booke206(DisasContext
*ctx
)
5830 #if defined(CONFIG_USER_ONLY)
5834 gen_helper_booke206_tlbre(cpu_env
);
5835 #endif /* defined(CONFIG_USER_ONLY) */
5838 /* tlbsx - tlbsx. */
5839 static void gen_tlbsx_booke206(DisasContext
*ctx
)
5841 #if defined(CONFIG_USER_ONLY)
5847 if (rA(ctx
->opcode
)) {
5848 t0
= tcg_temp_new();
5849 tcg_gen_mov_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)]);
5851 t0
= tcg_const_tl(0);
5854 tcg_gen_add_tl(t0
, t0
, cpu_gpr
[rB(ctx
->opcode
)]);
5855 gen_helper_booke206_tlbsx(cpu_env
, t0
);
5857 #endif /* defined(CONFIG_USER_ONLY) */
5861 static void gen_tlbwe_booke206(DisasContext
*ctx
)
5863 #if defined(CONFIG_USER_ONLY)
5867 gen_update_nip(ctx
, ctx
->nip
- 4);
5868 gen_helper_booke206_tlbwe(cpu_env
);
5869 #endif /* defined(CONFIG_USER_ONLY) */
5872 static void gen_tlbivax_booke206(DisasContext
*ctx
)
5874 #if defined(CONFIG_USER_ONLY)
5880 t0
= tcg_temp_new();
5881 gen_addr_reg_index(ctx
, t0
);
5882 gen_helper_booke206_tlbivax(cpu_env
, t0
);
5884 #endif /* defined(CONFIG_USER_ONLY) */
5887 static void gen_tlbilx_booke206(DisasContext
*ctx
)
5889 #if defined(CONFIG_USER_ONLY)
5895 t0
= tcg_temp_new();
5896 gen_addr_reg_index(ctx
, t0
);
5898 switch((ctx
->opcode
>> 21) & 0x3) {
5900 gen_helper_booke206_tlbilx0(cpu_env
, t0
);
5903 gen_helper_booke206_tlbilx1(cpu_env
, t0
);
5906 gen_helper_booke206_tlbilx3(cpu_env
, t0
);
5909 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5914 #endif /* defined(CONFIG_USER_ONLY) */
5919 static void gen_wrtee(DisasContext
*ctx
)
5921 #if defined(CONFIG_USER_ONLY)
5927 t0
= tcg_temp_new();
5928 tcg_gen_andi_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)], (1 << MSR_EE
));
5929 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
5930 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
5932 /* Stop translation to have a chance to raise an exception
5933 * if we just set msr_ee to 1
5935 gen_stop_exception(ctx
);
5936 #endif /* defined(CONFIG_USER_ONLY) */
5940 static void gen_wrteei(DisasContext
*ctx
)
5942 #if defined(CONFIG_USER_ONLY)
5946 if (ctx
->opcode
& 0x00008000) {
5947 tcg_gen_ori_tl(cpu_msr
, cpu_msr
, (1 << MSR_EE
));
5948 /* Stop translation to have a chance to raise an exception */
5949 gen_stop_exception(ctx
);
5951 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
5953 #endif /* defined(CONFIG_USER_ONLY) */
5956 /* PowerPC 440 specific instructions */
5959 static void gen_dlmzb(DisasContext
*ctx
)
5961 TCGv_i32 t0
= tcg_const_i32(Rc(ctx
->opcode
));
5962 gen_helper_dlmzb(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
5963 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], t0
);
5964 tcg_temp_free_i32(t0
);
5967 /* mbar replaces eieio on 440 */
5968 static void gen_mbar(DisasContext
*ctx
)
5970 /* interpreted as no-op */
5973 /* msync replaces sync on 440 */
5974 static void gen_msync_4xx(DisasContext
*ctx
)
5976 /* interpreted as no-op */
5980 static void gen_icbt_440(DisasContext
*ctx
)
5982 /* interpreted as no-op */
5983 /* XXX: specification say this is treated as a load by the MMU
5984 * but does not generate any exception
5988 /* Embedded.Processor Control */
5990 static void gen_msgclr(DisasContext
*ctx
)
5992 #if defined(CONFIG_USER_ONLY)
5996 gen_helper_msgclr(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5997 #endif /* defined(CONFIG_USER_ONLY) */
6000 static void gen_msgsnd(DisasContext
*ctx
)
6002 #if defined(CONFIG_USER_ONLY)
6006 gen_helper_msgsnd(cpu_gpr
[rB(ctx
->opcode
)]);
6007 #endif /* defined(CONFIG_USER_ONLY) */
6011 #if defined(TARGET_PPC64)
6012 static void gen_maddld(DisasContext
*ctx
)
6014 TCGv_i64 t1
= tcg_temp_new_i64();
6016 tcg_gen_mul_i64(t1
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
6017 tcg_gen_add_i64(cpu_gpr
[rD(ctx
->opcode
)], t1
, cpu_gpr
[rC(ctx
->opcode
)]);
6018 tcg_temp_free_i64(t1
);
6021 /* maddhd maddhdu */
6022 static void gen_maddhd_maddhdu(DisasContext
*ctx
)
6024 TCGv_i64 lo
= tcg_temp_new_i64();
6025 TCGv_i64 hi
= tcg_temp_new_i64();
6026 TCGv_i64 t1
= tcg_temp_new_i64();
6028 if (Rc(ctx
->opcode
)) {
6029 tcg_gen_mulu2_i64(lo
, hi
, cpu_gpr
[rA(ctx
->opcode
)],
6030 cpu_gpr
[rB(ctx
->opcode
)]);
6031 tcg_gen_movi_i64(t1
, 0);
6033 tcg_gen_muls2_i64(lo
, hi
, cpu_gpr
[rA(ctx
->opcode
)],
6034 cpu_gpr
[rB(ctx
->opcode
)]);
6035 tcg_gen_sari_i64(t1
, cpu_gpr
[rC(ctx
->opcode
)], 63);
6037 tcg_gen_add2_i64(t1
, cpu_gpr
[rD(ctx
->opcode
)], lo
, hi
,
6038 cpu_gpr
[rC(ctx
->opcode
)], t1
);
6039 tcg_temp_free_i64(lo
);
6040 tcg_temp_free_i64(hi
);
6041 tcg_temp_free_i64(t1
);
6043 #endif /* defined(TARGET_PPC64) */
6045 /*** VSX extension ***/
6047 static inline TCGv_i64
cpu_vsrh(int n
)
6052 return cpu_avrh
[n
-32];
6056 static inline TCGv_i64
cpu_vsrl(int n
)
6061 return cpu_avrl
[n
-32];
6065 #define VSX_LOAD_SCALAR(name, operation) \
6066 static void gen_##name(DisasContext *ctx) \
6069 if (unlikely(!ctx->vsx_enabled)) { \
6070 gen_exception(ctx, POWERPC_EXCP_VSXU); \
6073 gen_set_access_type(ctx, ACCESS_INT); \
6074 EA = tcg_temp_new(); \
6075 gen_addr_reg_index(ctx, EA); \
6076 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
6077 /* NOTE: cpu_vsrl is undefined */ \
6078 tcg_temp_free(EA); \
6081 VSX_LOAD_SCALAR(lxsdx
, ld64
)
6082 VSX_LOAD_SCALAR(lxsiwax
, ld32s_i64
)
6083 VSX_LOAD_SCALAR(lxsiwzx
, ld32u_i64
)
6084 VSX_LOAD_SCALAR(lxsspx
, ld32fs
)
6086 static void gen_lxvd2x(DisasContext
*ctx
)
6089 if (unlikely(!ctx
->vsx_enabled
)) {
6090 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
6093 gen_set_access_type(ctx
, ACCESS_INT
);
6094 EA
= tcg_temp_new();
6095 gen_addr_reg_index(ctx
, EA
);
6096 gen_qemu_ld64(ctx
, cpu_vsrh(xT(ctx
->opcode
)), EA
);
6097 tcg_gen_addi_tl(EA
, EA
, 8);
6098 gen_qemu_ld64(ctx
, cpu_vsrl(xT(ctx
->opcode
)), EA
);
6102 static void gen_lxvdsx(DisasContext
*ctx
)
6105 if (unlikely(!ctx
->vsx_enabled
)) {
6106 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
6109 gen_set_access_type(ctx
, ACCESS_INT
);
6110 EA
= tcg_temp_new();
6111 gen_addr_reg_index(ctx
, EA
);
6112 gen_qemu_ld64(ctx
, cpu_vsrh(xT(ctx
->opcode
)), EA
);
6113 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), cpu_vsrh(xT(ctx
->opcode
)));
6117 static void gen_lxvw4x(DisasContext
*ctx
)
6121 TCGv_i64 xth
= cpu_vsrh(xT(ctx
->opcode
));
6122 TCGv_i64 xtl
= cpu_vsrl(xT(ctx
->opcode
));
6123 if (unlikely(!ctx
->vsx_enabled
)) {
6124 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
6127 gen_set_access_type(ctx
, ACCESS_INT
);
6128 EA
= tcg_temp_new();
6129 tmp
= tcg_temp_new_i64();
6131 gen_addr_reg_index(ctx
, EA
);
6132 gen_qemu_ld32u_i64(ctx
, tmp
, EA
);
6133 tcg_gen_addi_tl(EA
, EA
, 4);
6134 gen_qemu_ld32u_i64(ctx
, xth
, EA
);
6135 tcg_gen_deposit_i64(xth
, xth
, tmp
, 32, 32);
6137 tcg_gen_addi_tl(EA
, EA
, 4);
6138 gen_qemu_ld32u_i64(ctx
, tmp
, EA
);
6139 tcg_gen_addi_tl(EA
, EA
, 4);
6140 gen_qemu_ld32u_i64(ctx
, xtl
, EA
);
6141 tcg_gen_deposit_i64(xtl
, xtl
, tmp
, 32, 32);
6144 tcg_temp_free_i64(tmp
);
6147 #define VSX_STORE_SCALAR(name, operation) \
6148 static void gen_##name(DisasContext *ctx) \
6151 if (unlikely(!ctx->vsx_enabled)) { \
6152 gen_exception(ctx, POWERPC_EXCP_VSXU); \
6155 gen_set_access_type(ctx, ACCESS_INT); \
6156 EA = tcg_temp_new(); \
6157 gen_addr_reg_index(ctx, EA); \
6158 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
6159 tcg_temp_free(EA); \
6162 VSX_STORE_SCALAR(stxsdx
, st64
)
6163 VSX_STORE_SCALAR(stxsiwx
, st32_i64
)
6164 VSX_STORE_SCALAR(stxsspx
, st32fs
)
6166 static void gen_stxvd2x(DisasContext
*ctx
)
6169 if (unlikely(!ctx
->vsx_enabled
)) {
6170 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
6173 gen_set_access_type(ctx
, ACCESS_INT
);
6174 EA
= tcg_temp_new();
6175 gen_addr_reg_index(ctx
, EA
);
6176 gen_qemu_st64(ctx
, cpu_vsrh(xS(ctx
->opcode
)), EA
);
6177 tcg_gen_addi_tl(EA
, EA
, 8);
6178 gen_qemu_st64(ctx
, cpu_vsrl(xS(ctx
->opcode
)), EA
);
6182 static void gen_stxvw4x(DisasContext
*ctx
)
6186 if (unlikely(!ctx
->vsx_enabled
)) {
6187 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
6190 gen_set_access_type(ctx
, ACCESS_INT
);
6191 EA
= tcg_temp_new();
6192 gen_addr_reg_index(ctx
, EA
);
6193 tmp
= tcg_temp_new_i64();
6195 tcg_gen_shri_i64(tmp
, cpu_vsrh(xS(ctx
->opcode
)), 32);
6196 gen_qemu_st32_i64(ctx
, tmp
, EA
);
6197 tcg_gen_addi_tl(EA
, EA
, 4);
6198 gen_qemu_st32_i64(ctx
, cpu_vsrh(xS(ctx
->opcode
)), EA
);
6200 tcg_gen_shri_i64(tmp
, cpu_vsrl(xS(ctx
->opcode
)), 32);
6201 tcg_gen_addi_tl(EA
, EA
, 4);
6202 gen_qemu_st32_i64(ctx
, tmp
, EA
);
6203 tcg_gen_addi_tl(EA
, EA
, 4);
6204 gen_qemu_st32_i64(ctx
, cpu_vsrl(xS(ctx
->opcode
)), EA
);
6207 tcg_temp_free_i64(tmp
);
6210 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
6211 static void gen_##name(DisasContext *ctx) \
6213 if (xS(ctx->opcode) < 32) { \
6214 if (unlikely(!ctx->fpu_enabled)) { \
6215 gen_exception(ctx, POWERPC_EXCP_FPU); \
6219 if (unlikely(!ctx->altivec_enabled)) { \
6220 gen_exception(ctx, POWERPC_EXCP_VPU); \
6224 TCGv_i64 tmp = tcg_temp_new_i64(); \
6225 tcg_gen_##tcgop1(tmp, source); \
6226 tcg_gen_##tcgop2(target, tmp); \
6227 tcg_temp_free_i64(tmp); \
6231 MV_VSRW(mfvsrwz
, ext32u_i64
, trunc_i64_tl
, cpu_gpr
[rA(ctx
->opcode
)], \
6232 cpu_vsrh(xS(ctx
->opcode
)))
6233 MV_VSRW(mtvsrwa
, extu_tl_i64
, ext32s_i64
, cpu_vsrh(xT(ctx
->opcode
)), \
6234 cpu_gpr
[rA(ctx
->opcode
)])
6235 MV_VSRW(mtvsrwz
, extu_tl_i64
, ext32u_i64
, cpu_vsrh(xT(ctx
->opcode
)), \
6236 cpu_gpr
[rA(ctx
->opcode
)])
6238 #if defined(TARGET_PPC64)
6239 #define MV_VSRD(name, target, source) \
6240 static void gen_##name(DisasContext *ctx) \
6242 if (xS(ctx->opcode) < 32) { \
6243 if (unlikely(!ctx->fpu_enabled)) { \
6244 gen_exception(ctx, POWERPC_EXCP_FPU); \
6248 if (unlikely(!ctx->altivec_enabled)) { \
6249 gen_exception(ctx, POWERPC_EXCP_VPU); \
6253 tcg_gen_mov_i64(target, source); \
6256 MV_VSRD(mfvsrd
, cpu_gpr
[rA(ctx
->opcode
)], cpu_vsrh(xS(ctx
->opcode
)))
6257 MV_VSRD(mtvsrd
, cpu_vsrh(xT(ctx
->opcode
)), cpu_gpr
[rA(ctx
->opcode
)])
6261 static void gen_xxpermdi(DisasContext
*ctx
)
6263 if (unlikely(!ctx
->vsx_enabled
)) {
6264 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
6268 if (unlikely((xT(ctx
->opcode
) == xA(ctx
->opcode
)) ||
6269 (xT(ctx
->opcode
) == xB(ctx
->opcode
)))) {
6272 xh
= tcg_temp_new_i64();
6273 xl
= tcg_temp_new_i64();
6275 if ((DM(ctx
->opcode
) & 2) == 0) {
6276 tcg_gen_mov_i64(xh
, cpu_vsrh(xA(ctx
->opcode
)));
6278 tcg_gen_mov_i64(xh
, cpu_vsrl(xA(ctx
->opcode
)));
6280 if ((DM(ctx
->opcode
) & 1) == 0) {
6281 tcg_gen_mov_i64(xl
, cpu_vsrh(xB(ctx
->opcode
)));
6283 tcg_gen_mov_i64(xl
, cpu_vsrl(xB(ctx
->opcode
)));
6286 tcg_gen_mov_i64(cpu_vsrh(xT(ctx
->opcode
)), xh
);
6287 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), xl
);
6289 tcg_temp_free_i64(xh
);
6290 tcg_temp_free_i64(xl
);
6292 if ((DM(ctx
->opcode
) & 2) == 0) {
6293 tcg_gen_mov_i64(cpu_vsrh(xT(ctx
->opcode
)), cpu_vsrh(xA(ctx
->opcode
)));
6295 tcg_gen_mov_i64(cpu_vsrh(xT(ctx
->opcode
)), cpu_vsrl(xA(ctx
->opcode
)));
6297 if ((DM(ctx
->opcode
) & 1) == 0) {
6298 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), cpu_vsrh(xB(ctx
->opcode
)));
6300 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), cpu_vsrl(xB(ctx
->opcode
)));
6309 #define SGN_MASK_DP 0x8000000000000000ull
6310 #define SGN_MASK_SP 0x8000000080000000ull
6312 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
6313 static void glue(gen_, name)(DisasContext * ctx) \
6316 if (unlikely(!ctx->vsx_enabled)) { \
6317 gen_exception(ctx, POWERPC_EXCP_VSXU); \
6320 xb = tcg_temp_new_i64(); \
6321 sgm = tcg_temp_new_i64(); \
6322 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
6323 tcg_gen_movi_i64(sgm, sgn_mask); \
6326 tcg_gen_andc_i64(xb, xb, sgm); \
6330 tcg_gen_or_i64(xb, xb, sgm); \
6334 tcg_gen_xor_i64(xb, xb, sgm); \
6338 TCGv_i64 xa = tcg_temp_new_i64(); \
6339 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
6340 tcg_gen_and_i64(xa, xa, sgm); \
6341 tcg_gen_andc_i64(xb, xb, sgm); \
6342 tcg_gen_or_i64(xb, xb, xa); \
6343 tcg_temp_free_i64(xa); \
6347 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
6348 tcg_temp_free_i64(xb); \
6349 tcg_temp_free_i64(sgm); \
6352 VSX_SCALAR_MOVE(xsabsdp
, OP_ABS
, SGN_MASK_DP
)
6353 VSX_SCALAR_MOVE(xsnabsdp
, OP_NABS
, SGN_MASK_DP
)
6354 VSX_SCALAR_MOVE(xsnegdp
, OP_NEG
, SGN_MASK_DP
)
6355 VSX_SCALAR_MOVE(xscpsgndp
, OP_CPSGN
, SGN_MASK_DP
)
6357 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
6358 static void glue(gen_, name)(DisasContext * ctx) \
6360 TCGv_i64 xbh, xbl, sgm; \
6361 if (unlikely(!ctx->vsx_enabled)) { \
6362 gen_exception(ctx, POWERPC_EXCP_VSXU); \
6365 xbh = tcg_temp_new_i64(); \
6366 xbl = tcg_temp_new_i64(); \
6367 sgm = tcg_temp_new_i64(); \
6368 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
6369 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
6370 tcg_gen_movi_i64(sgm, sgn_mask); \
6373 tcg_gen_andc_i64(xbh, xbh, sgm); \
6374 tcg_gen_andc_i64(xbl, xbl, sgm); \
6378 tcg_gen_or_i64(xbh, xbh, sgm); \
6379 tcg_gen_or_i64(xbl, xbl, sgm); \
6383 tcg_gen_xor_i64(xbh, xbh, sgm); \
6384 tcg_gen_xor_i64(xbl, xbl, sgm); \
6388 TCGv_i64 xah = tcg_temp_new_i64(); \
6389 TCGv_i64 xal = tcg_temp_new_i64(); \
6390 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
6391 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
6392 tcg_gen_and_i64(xah, xah, sgm); \
6393 tcg_gen_and_i64(xal, xal, sgm); \
6394 tcg_gen_andc_i64(xbh, xbh, sgm); \
6395 tcg_gen_andc_i64(xbl, xbl, sgm); \
6396 tcg_gen_or_i64(xbh, xbh, xah); \
6397 tcg_gen_or_i64(xbl, xbl, xal); \
6398 tcg_temp_free_i64(xah); \
6399 tcg_temp_free_i64(xal); \
6403 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
6404 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
6405 tcg_temp_free_i64(xbh); \
6406 tcg_temp_free_i64(xbl); \
6407 tcg_temp_free_i64(sgm); \
6410 VSX_VECTOR_MOVE(xvabsdp
, OP_ABS
, SGN_MASK_DP
)
6411 VSX_VECTOR_MOVE(xvnabsdp
, OP_NABS
, SGN_MASK_DP
)
6412 VSX_VECTOR_MOVE(xvnegdp
, OP_NEG
, SGN_MASK_DP
)
6413 VSX_VECTOR_MOVE(xvcpsgndp
, OP_CPSGN
, SGN_MASK_DP
)
6414 VSX_VECTOR_MOVE(xvabssp
, OP_ABS
, SGN_MASK_SP
)
6415 VSX_VECTOR_MOVE(xvnabssp
, OP_NABS
, SGN_MASK_SP
)
6416 VSX_VECTOR_MOVE(xvnegsp
, OP_NEG
, SGN_MASK_SP
)
6417 VSX_VECTOR_MOVE(xvcpsgnsp
, OP_CPSGN
, SGN_MASK_SP
)
6419 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
6420 static void gen_##name(DisasContext * ctx) \
6423 if (unlikely(!ctx->vsx_enabled)) { \
6424 gen_exception(ctx, POWERPC_EXCP_VSXU); \
6427 /* NIP cannot be restored if the memory exception comes from an helper */ \
6428 gen_update_nip(ctx, ctx->nip - 4); \
6429 opc = tcg_const_i32(ctx->opcode); \
6430 gen_helper_##name(cpu_env, opc); \
6431 tcg_temp_free_i32(opc); \
6434 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
6435 static void gen_##name(DisasContext * ctx) \
6437 if (unlikely(!ctx->vsx_enabled)) { \
6438 gen_exception(ctx, POWERPC_EXCP_VSXU); \
6441 /* NIP cannot be restored if the exception comes */ \
6442 /* from a helper. */ \
6443 gen_update_nip(ctx, ctx->nip - 4); \
6445 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
6446 cpu_vsrh(xB(ctx->opcode))); \
6449 GEN_VSX_HELPER_2(xsadddp
, 0x00, 0x04, 0, PPC2_VSX
)
6450 GEN_VSX_HELPER_2(xssubdp
, 0x00, 0x05, 0, PPC2_VSX
)
6451 GEN_VSX_HELPER_2(xsmuldp
, 0x00, 0x06, 0, PPC2_VSX
)
6452 GEN_VSX_HELPER_2(xsdivdp
, 0x00, 0x07, 0, PPC2_VSX
)
6453 GEN_VSX_HELPER_2(xsredp
, 0x14, 0x05, 0, PPC2_VSX
)
6454 GEN_VSX_HELPER_2(xssqrtdp
, 0x16, 0x04, 0, PPC2_VSX
)
6455 GEN_VSX_HELPER_2(xsrsqrtedp
, 0x14, 0x04, 0, PPC2_VSX
)
6456 GEN_VSX_HELPER_2(xstdivdp
, 0x14, 0x07, 0, PPC2_VSX
)
6457 GEN_VSX_HELPER_2(xstsqrtdp
, 0x14, 0x06, 0, PPC2_VSX
)
6458 GEN_VSX_HELPER_2(xsmaddadp
, 0x04, 0x04, 0, PPC2_VSX
)
6459 GEN_VSX_HELPER_2(xsmaddmdp
, 0x04, 0x05, 0, PPC2_VSX
)
6460 GEN_VSX_HELPER_2(xsmsubadp
, 0x04, 0x06, 0, PPC2_VSX
)
6461 GEN_VSX_HELPER_2(xsmsubmdp
, 0x04, 0x07, 0, PPC2_VSX
)
6462 GEN_VSX_HELPER_2(xsnmaddadp
, 0x04, 0x14, 0, PPC2_VSX
)
6463 GEN_VSX_HELPER_2(xsnmaddmdp
, 0x04, 0x15, 0, PPC2_VSX
)
6464 GEN_VSX_HELPER_2(xsnmsubadp
, 0x04, 0x16, 0, PPC2_VSX
)
6465 GEN_VSX_HELPER_2(xsnmsubmdp
, 0x04, 0x17, 0, PPC2_VSX
)
6466 GEN_VSX_HELPER_2(xscmpodp
, 0x0C, 0x05, 0, PPC2_VSX
)
6467 GEN_VSX_HELPER_2(xscmpudp
, 0x0C, 0x04, 0, PPC2_VSX
)
6468 GEN_VSX_HELPER_2(xsmaxdp
, 0x00, 0x14, 0, PPC2_VSX
)
6469 GEN_VSX_HELPER_2(xsmindp
, 0x00, 0x15, 0, PPC2_VSX
)
6470 GEN_VSX_HELPER_2(xscvdpsp
, 0x12, 0x10, 0, PPC2_VSX
)
6471 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn
, 0x16, 0x10, 0, PPC2_VSX207
)
6472 GEN_VSX_HELPER_2(xscvspdp
, 0x12, 0x14, 0, PPC2_VSX
)
6473 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn
, 0x16, 0x14, 0, PPC2_VSX207
)
6474 GEN_VSX_HELPER_2(xscvdpsxds
, 0x10, 0x15, 0, PPC2_VSX
)
6475 GEN_VSX_HELPER_2(xscvdpsxws
, 0x10, 0x05, 0, PPC2_VSX
)
6476 GEN_VSX_HELPER_2(xscvdpuxds
, 0x10, 0x14, 0, PPC2_VSX
)
6477 GEN_VSX_HELPER_2(xscvdpuxws
, 0x10, 0x04, 0, PPC2_VSX
)
6478 GEN_VSX_HELPER_2(xscvsxddp
, 0x10, 0x17, 0, PPC2_VSX
)
6479 GEN_VSX_HELPER_2(xscvuxddp
, 0x10, 0x16, 0, PPC2_VSX
)
6480 GEN_VSX_HELPER_2(xsrdpi
, 0x12, 0x04, 0, PPC2_VSX
)
6481 GEN_VSX_HELPER_2(xsrdpic
, 0x16, 0x06, 0, PPC2_VSX
)
6482 GEN_VSX_HELPER_2(xsrdpim
, 0x12, 0x07, 0, PPC2_VSX
)
6483 GEN_VSX_HELPER_2(xsrdpip
, 0x12, 0x06, 0, PPC2_VSX
)
6484 GEN_VSX_HELPER_2(xsrdpiz
, 0x12, 0x05, 0, PPC2_VSX
)
6485 GEN_VSX_HELPER_XT_XB_ENV(xsrsp
, 0x12, 0x11, 0, PPC2_VSX207
)
6487 GEN_VSX_HELPER_2(xsaddsp
, 0x00, 0x00, 0, PPC2_VSX207
)
6488 GEN_VSX_HELPER_2(xssubsp
, 0x00, 0x01, 0, PPC2_VSX207
)
6489 GEN_VSX_HELPER_2(xsmulsp
, 0x00, 0x02, 0, PPC2_VSX207
)
6490 GEN_VSX_HELPER_2(xsdivsp
, 0x00, 0x03, 0, PPC2_VSX207
)
6491 GEN_VSX_HELPER_2(xsresp
, 0x14, 0x01, 0, PPC2_VSX207
)
6492 GEN_VSX_HELPER_2(xssqrtsp
, 0x16, 0x00, 0, PPC2_VSX207
)
6493 GEN_VSX_HELPER_2(xsrsqrtesp
, 0x14, 0x00, 0, PPC2_VSX207
)
6494 GEN_VSX_HELPER_2(xsmaddasp
, 0x04, 0x00, 0, PPC2_VSX207
)
6495 GEN_VSX_HELPER_2(xsmaddmsp
, 0x04, 0x01, 0, PPC2_VSX207
)
6496 GEN_VSX_HELPER_2(xsmsubasp
, 0x04, 0x02, 0, PPC2_VSX207
)
6497 GEN_VSX_HELPER_2(xsmsubmsp
, 0x04, 0x03, 0, PPC2_VSX207
)
6498 GEN_VSX_HELPER_2(xsnmaddasp
, 0x04, 0x10, 0, PPC2_VSX207
)
6499 GEN_VSX_HELPER_2(xsnmaddmsp
, 0x04, 0x11, 0, PPC2_VSX207
)
6500 GEN_VSX_HELPER_2(xsnmsubasp
, 0x04, 0x12, 0, PPC2_VSX207
)
6501 GEN_VSX_HELPER_2(xsnmsubmsp
, 0x04, 0x13, 0, PPC2_VSX207
)
6502 GEN_VSX_HELPER_2(xscvsxdsp
, 0x10, 0x13, 0, PPC2_VSX207
)
6503 GEN_VSX_HELPER_2(xscvuxdsp
, 0x10, 0x12, 0, PPC2_VSX207
)
6505 GEN_VSX_HELPER_2(xvadddp
, 0x00, 0x0C, 0, PPC2_VSX
)
6506 GEN_VSX_HELPER_2(xvsubdp
, 0x00, 0x0D, 0, PPC2_VSX
)
6507 GEN_VSX_HELPER_2(xvmuldp
, 0x00, 0x0E, 0, PPC2_VSX
)
6508 GEN_VSX_HELPER_2(xvdivdp
, 0x00, 0x0F, 0, PPC2_VSX
)
6509 GEN_VSX_HELPER_2(xvredp
, 0x14, 0x0D, 0, PPC2_VSX
)
6510 GEN_VSX_HELPER_2(xvsqrtdp
, 0x16, 0x0C, 0, PPC2_VSX
)
6511 GEN_VSX_HELPER_2(xvrsqrtedp
, 0x14, 0x0C, 0, PPC2_VSX
)
6512 GEN_VSX_HELPER_2(xvtdivdp
, 0x14, 0x0F, 0, PPC2_VSX
)
6513 GEN_VSX_HELPER_2(xvtsqrtdp
, 0x14, 0x0E, 0, PPC2_VSX
)
6514 GEN_VSX_HELPER_2(xvmaddadp
, 0x04, 0x0C, 0, PPC2_VSX
)
6515 GEN_VSX_HELPER_2(xvmaddmdp
, 0x04, 0x0D, 0, PPC2_VSX
)
6516 GEN_VSX_HELPER_2(xvmsubadp
, 0x04, 0x0E, 0, PPC2_VSX
)
6517 GEN_VSX_HELPER_2(xvmsubmdp
, 0x04, 0x0F, 0, PPC2_VSX
)
6518 GEN_VSX_HELPER_2(xvnmaddadp
, 0x04, 0x1C, 0, PPC2_VSX
)
6519 GEN_VSX_HELPER_2(xvnmaddmdp
, 0x04, 0x1D, 0, PPC2_VSX
)
6520 GEN_VSX_HELPER_2(xvnmsubadp
, 0x04, 0x1E, 0, PPC2_VSX
)
6521 GEN_VSX_HELPER_2(xvnmsubmdp
, 0x04, 0x1F, 0, PPC2_VSX
)
6522 GEN_VSX_HELPER_2(xvmaxdp
, 0x00, 0x1C, 0, PPC2_VSX
)
6523 GEN_VSX_HELPER_2(xvmindp
, 0x00, 0x1D, 0, PPC2_VSX
)
6524 GEN_VSX_HELPER_2(xvcmpeqdp
, 0x0C, 0x0C, 0, PPC2_VSX
)
6525 GEN_VSX_HELPER_2(xvcmpgtdp
, 0x0C, 0x0D, 0, PPC2_VSX
)
6526 GEN_VSX_HELPER_2(xvcmpgedp
, 0x0C, 0x0E, 0, PPC2_VSX
)
6527 GEN_VSX_HELPER_2(xvcvdpsp
, 0x12, 0x18, 0, PPC2_VSX
)
6528 GEN_VSX_HELPER_2(xvcvdpsxds
, 0x10, 0x1D, 0, PPC2_VSX
)
6529 GEN_VSX_HELPER_2(xvcvdpsxws
, 0x10, 0x0D, 0, PPC2_VSX
)
6530 GEN_VSX_HELPER_2(xvcvdpuxds
, 0x10, 0x1C, 0, PPC2_VSX
)
6531 GEN_VSX_HELPER_2(xvcvdpuxws
, 0x10, 0x0C, 0, PPC2_VSX
)
6532 GEN_VSX_HELPER_2(xvcvsxddp
, 0x10, 0x1F, 0, PPC2_VSX
)
6533 GEN_VSX_HELPER_2(xvcvuxddp
, 0x10, 0x1E, 0, PPC2_VSX
)
6534 GEN_VSX_HELPER_2(xvcvsxwdp
, 0x10, 0x0F, 0, PPC2_VSX
)
6535 GEN_VSX_HELPER_2(xvcvuxwdp
, 0x10, 0x0E, 0, PPC2_VSX
)
6536 GEN_VSX_HELPER_2(xvrdpi
, 0x12, 0x0C, 0, PPC2_VSX
)
6537 GEN_VSX_HELPER_2(xvrdpic
, 0x16, 0x0E, 0, PPC2_VSX
)
6538 GEN_VSX_HELPER_2(xvrdpim
, 0x12, 0x0F, 0, PPC2_VSX
)
6539 GEN_VSX_HELPER_2(xvrdpip
, 0x12, 0x0E, 0, PPC2_VSX
)
6540 GEN_VSX_HELPER_2(xvrdpiz
, 0x12, 0x0D, 0, PPC2_VSX
)
6542 GEN_VSX_HELPER_2(xvaddsp
, 0x00, 0x08, 0, PPC2_VSX
)
6543 GEN_VSX_HELPER_2(xvsubsp
, 0x00, 0x09, 0, PPC2_VSX
)
6544 GEN_VSX_HELPER_2(xvmulsp
, 0x00, 0x0A, 0, PPC2_VSX
)
6545 GEN_VSX_HELPER_2(xvdivsp
, 0x00, 0x0B, 0, PPC2_VSX
)
6546 GEN_VSX_HELPER_2(xvresp
, 0x14, 0x09, 0, PPC2_VSX
)
6547 GEN_VSX_HELPER_2(xvsqrtsp
, 0x16, 0x08, 0, PPC2_VSX
)
6548 GEN_VSX_HELPER_2(xvrsqrtesp
, 0x14, 0x08, 0, PPC2_VSX
)
6549 GEN_VSX_HELPER_2(xvtdivsp
, 0x14, 0x0B, 0, PPC2_VSX
)
6550 GEN_VSX_HELPER_2(xvtsqrtsp
, 0x14, 0x0A, 0, PPC2_VSX
)
6551 GEN_VSX_HELPER_2(xvmaddasp
, 0x04, 0x08, 0, PPC2_VSX
)
6552 GEN_VSX_HELPER_2(xvmaddmsp
, 0x04, 0x09, 0, PPC2_VSX
)
6553 GEN_VSX_HELPER_2(xvmsubasp
, 0x04, 0x0A, 0, PPC2_VSX
)
6554 GEN_VSX_HELPER_2(xvmsubmsp
, 0x04, 0x0B, 0, PPC2_VSX
)
6555 GEN_VSX_HELPER_2(xvnmaddasp
, 0x04, 0x18, 0, PPC2_VSX
)
6556 GEN_VSX_HELPER_2(xvnmaddmsp
, 0x04, 0x19, 0, PPC2_VSX
)
6557 GEN_VSX_HELPER_2(xvnmsubasp
, 0x04, 0x1A, 0, PPC2_VSX
)
6558 GEN_VSX_HELPER_2(xvnmsubmsp
, 0x04, 0x1B, 0, PPC2_VSX
)
6559 GEN_VSX_HELPER_2(xvmaxsp
, 0x00, 0x18, 0, PPC2_VSX
)
6560 GEN_VSX_HELPER_2(xvminsp
, 0x00, 0x19, 0, PPC2_VSX
)
6561 GEN_VSX_HELPER_2(xvcmpeqsp
, 0x0C, 0x08, 0, PPC2_VSX
)
6562 GEN_VSX_HELPER_2(xvcmpgtsp
, 0x0C, 0x09, 0, PPC2_VSX
)
6563 GEN_VSX_HELPER_2(xvcmpgesp
, 0x0C, 0x0A, 0, PPC2_VSX
)
6564 GEN_VSX_HELPER_2(xvcvspdp
, 0x12, 0x1C, 0, PPC2_VSX
)
6565 GEN_VSX_HELPER_2(xvcvspsxds
, 0x10, 0x19, 0, PPC2_VSX
)
6566 GEN_VSX_HELPER_2(xvcvspsxws
, 0x10, 0x09, 0, PPC2_VSX
)
6567 GEN_VSX_HELPER_2(xvcvspuxds
, 0x10, 0x18, 0, PPC2_VSX
)
6568 GEN_VSX_HELPER_2(xvcvspuxws
, 0x10, 0x08, 0, PPC2_VSX
)
6569 GEN_VSX_HELPER_2(xvcvsxdsp
, 0x10, 0x1B, 0, PPC2_VSX
)
6570 GEN_VSX_HELPER_2(xvcvuxdsp
, 0x10, 0x1A, 0, PPC2_VSX
)
6571 GEN_VSX_HELPER_2(xvcvsxwsp
, 0x10, 0x0B, 0, PPC2_VSX
)
6572 GEN_VSX_HELPER_2(xvcvuxwsp
, 0x10, 0x0A, 0, PPC2_VSX
)
6573 GEN_VSX_HELPER_2(xvrspi
, 0x12, 0x08, 0, PPC2_VSX
)
6574 GEN_VSX_HELPER_2(xvrspic
, 0x16, 0x0A, 0, PPC2_VSX
)
6575 GEN_VSX_HELPER_2(xvrspim
, 0x12, 0x0B, 0, PPC2_VSX
)
6576 GEN_VSX_HELPER_2(xvrspip
, 0x12, 0x0A, 0, PPC2_VSX
)
6577 GEN_VSX_HELPER_2(xvrspiz
, 0x12, 0x09, 0, PPC2_VSX
)
6579 #define VSX_LOGICAL(name, tcg_op) \
6580 static void glue(gen_, name)(DisasContext * ctx) \
6582 if (unlikely(!ctx->vsx_enabled)) { \
6583 gen_exception(ctx, POWERPC_EXCP_VSXU); \
6586 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
6587 cpu_vsrh(xB(ctx->opcode))); \
6588 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
6589 cpu_vsrl(xB(ctx->opcode))); \
6592 VSX_LOGICAL(xxland
, tcg_gen_and_i64
)
6593 VSX_LOGICAL(xxlandc
, tcg_gen_andc_i64
)
6594 VSX_LOGICAL(xxlor
, tcg_gen_or_i64
)
6595 VSX_LOGICAL(xxlxor
, tcg_gen_xor_i64
)
6596 VSX_LOGICAL(xxlnor
, tcg_gen_nor_i64
)
6597 VSX_LOGICAL(xxleqv
, tcg_gen_eqv_i64
)
6598 VSX_LOGICAL(xxlnand
, tcg_gen_nand_i64
)
6599 VSX_LOGICAL(xxlorc
, tcg_gen_orc_i64
)
6601 #define VSX_XXMRG(name, high) \
6602 static void glue(gen_, name)(DisasContext * ctx) \
6604 TCGv_i64 a0, a1, b0, b1; \
6605 if (unlikely(!ctx->vsx_enabled)) { \
6606 gen_exception(ctx, POWERPC_EXCP_VSXU); \
6609 a0 = tcg_temp_new_i64(); \
6610 a1 = tcg_temp_new_i64(); \
6611 b0 = tcg_temp_new_i64(); \
6612 b1 = tcg_temp_new_i64(); \
6614 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
6615 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
6616 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
6617 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
6619 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
6620 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
6621 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
6622 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
6624 tcg_gen_shri_i64(a0, a0, 32); \
6625 tcg_gen_shri_i64(b0, b0, 32); \
6626 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
6628 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
6630 tcg_temp_free_i64(a0); \
6631 tcg_temp_free_i64(a1); \
6632 tcg_temp_free_i64(b0); \
6633 tcg_temp_free_i64(b1); \
6636 VSX_XXMRG(xxmrghw
, 1)
6637 VSX_XXMRG(xxmrglw
, 0)
6639 static void gen_xxsel(DisasContext
* ctx
)
6642 if (unlikely(!ctx
->vsx_enabled
)) {
6643 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
6646 a
= tcg_temp_new_i64();
6647 b
= tcg_temp_new_i64();
6648 c
= tcg_temp_new_i64();
6650 tcg_gen_mov_i64(a
, cpu_vsrh(xA(ctx
->opcode
)));
6651 tcg_gen_mov_i64(b
, cpu_vsrh(xB(ctx
->opcode
)));
6652 tcg_gen_mov_i64(c
, cpu_vsrh(xC(ctx
->opcode
)));
6654 tcg_gen_and_i64(b
, b
, c
);
6655 tcg_gen_andc_i64(a
, a
, c
);
6656 tcg_gen_or_i64(cpu_vsrh(xT(ctx
->opcode
)), a
, b
);
6658 tcg_gen_mov_i64(a
, cpu_vsrl(xA(ctx
->opcode
)));
6659 tcg_gen_mov_i64(b
, cpu_vsrl(xB(ctx
->opcode
)));
6660 tcg_gen_mov_i64(c
, cpu_vsrl(xC(ctx
->opcode
)));
6662 tcg_gen_and_i64(b
, b
, c
);
6663 tcg_gen_andc_i64(a
, a
, c
);
6664 tcg_gen_or_i64(cpu_vsrl(xT(ctx
->opcode
)), a
, b
);
6666 tcg_temp_free_i64(a
);
6667 tcg_temp_free_i64(b
);
6668 tcg_temp_free_i64(c
);
6671 static void gen_xxspltw(DisasContext
*ctx
)
6674 TCGv_i64 vsr
= (UIM(ctx
->opcode
) & 2) ?
6675 cpu_vsrl(xB(ctx
->opcode
)) :
6676 cpu_vsrh(xB(ctx
->opcode
));
6678 if (unlikely(!ctx
->vsx_enabled
)) {
6679 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
6683 b
= tcg_temp_new_i64();
6684 b2
= tcg_temp_new_i64();
6686 if (UIM(ctx
->opcode
) & 1) {
6687 tcg_gen_ext32u_i64(b
, vsr
);
6689 tcg_gen_shri_i64(b
, vsr
, 32);
6692 tcg_gen_shli_i64(b2
, b
, 32);
6693 tcg_gen_or_i64(cpu_vsrh(xT(ctx
->opcode
)), b
, b2
);
6694 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), cpu_vsrh(xT(ctx
->opcode
)));
6696 tcg_temp_free_i64(b
);
6697 tcg_temp_free_i64(b2
);
6700 static void gen_xxsldwi(DisasContext
*ctx
)
6703 if (unlikely(!ctx
->vsx_enabled
)) {
6704 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
6707 xth
= tcg_temp_new_i64();
6708 xtl
= tcg_temp_new_i64();
6710 switch (SHW(ctx
->opcode
)) {
6712 tcg_gen_mov_i64(xth
, cpu_vsrh(xA(ctx
->opcode
)));
6713 tcg_gen_mov_i64(xtl
, cpu_vsrl(xA(ctx
->opcode
)));
6717 TCGv_i64 t0
= tcg_temp_new_i64();
6718 tcg_gen_mov_i64(xth
, cpu_vsrh(xA(ctx
->opcode
)));
6719 tcg_gen_shli_i64(xth
, xth
, 32);
6720 tcg_gen_mov_i64(t0
, cpu_vsrl(xA(ctx
->opcode
)));
6721 tcg_gen_shri_i64(t0
, t0
, 32);
6722 tcg_gen_or_i64(xth
, xth
, t0
);
6723 tcg_gen_mov_i64(xtl
, cpu_vsrl(xA(ctx
->opcode
)));
6724 tcg_gen_shli_i64(xtl
, xtl
, 32);
6725 tcg_gen_mov_i64(t0
, cpu_vsrh(xB(ctx
->opcode
)));
6726 tcg_gen_shri_i64(t0
, t0
, 32);
6727 tcg_gen_or_i64(xtl
, xtl
, t0
);
6728 tcg_temp_free_i64(t0
);
6732 tcg_gen_mov_i64(xth
, cpu_vsrl(xA(ctx
->opcode
)));
6733 tcg_gen_mov_i64(xtl
, cpu_vsrh(xB(ctx
->opcode
)));
6737 TCGv_i64 t0
= tcg_temp_new_i64();
6738 tcg_gen_mov_i64(xth
, cpu_vsrl(xA(ctx
->opcode
)));
6739 tcg_gen_shli_i64(xth
, xth
, 32);
6740 tcg_gen_mov_i64(t0
, cpu_vsrh(xB(ctx
->opcode
)));
6741 tcg_gen_shri_i64(t0
, t0
, 32);
6742 tcg_gen_or_i64(xth
, xth
, t0
);
6743 tcg_gen_mov_i64(xtl
, cpu_vsrh(xB(ctx
->opcode
)));
6744 tcg_gen_shli_i64(xtl
, xtl
, 32);
6745 tcg_gen_mov_i64(t0
, cpu_vsrl(xB(ctx
->opcode
)));
6746 tcg_gen_shri_i64(t0
, t0
, 32);
6747 tcg_gen_or_i64(xtl
, xtl
, t0
);
6748 tcg_temp_free_i64(t0
);
6753 tcg_gen_mov_i64(cpu_vsrh(xT(ctx
->opcode
)), xth
);
6754 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), xtl
);
6756 tcg_temp_free_i64(xth
);
6757 tcg_temp_free_i64(xtl
);
6760 #include "translate/dfp-impl.c"
6762 #include "translate/spe-impl.c"
6764 static void gen_tbegin(DisasContext
*ctx
)
6766 if (unlikely(!ctx
->tm_enabled
)) {
6767 gen_exception_err(ctx
, POWERPC_EXCP_FU
, FSCR_IC_TM
);
6770 gen_helper_tbegin(cpu_env
);
6773 #define GEN_TM_NOOP(name) \
6774 static inline void gen_##name(DisasContext *ctx) \
6776 if (unlikely(!ctx->tm_enabled)) { \
6777 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6780 /* Because tbegin always fails in QEMU, these user \
6781 * space instructions all have a simple implementation: \
6783 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6784 * = 0b0 || 0b00 || 0b0 \
6786 tcg_gen_movi_i32(cpu_crf[0], 0); \
6790 GEN_TM_NOOP(tabort
);
6791 GEN_TM_NOOP(tabortwc
);
6792 GEN_TM_NOOP(tabortwci
);
6793 GEN_TM_NOOP(tabortdc
);
6794 GEN_TM_NOOP(tabortdci
);
6797 static void gen_tcheck(DisasContext
*ctx
)
6799 if (unlikely(!ctx
->tm_enabled
)) {
6800 gen_exception_err(ctx
, POWERPC_EXCP_FU
, FSCR_IC_TM
);
6803 /* Because tbegin always fails, the tcheck implementation
6806 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6807 * = 0b1 || 0b00 || 0b0
6809 tcg_gen_movi_i32(cpu_crf
[crfD(ctx
->opcode
)], 0x8);
6812 #if defined(CONFIG_USER_ONLY)
6813 #define GEN_TM_PRIV_NOOP(name) \
6814 static inline void gen_##name(DisasContext *ctx) \
6816 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6821 #define GEN_TM_PRIV_NOOP(name) \
6822 static inline void gen_##name(DisasContext *ctx) \
6825 if (unlikely(!ctx->tm_enabled)) { \
6826 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6829 /* Because tbegin always fails, the implementation is \
6832 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6833 * = 0b0 || 0b00 | 0b0 \
6835 tcg_gen_movi_i32(cpu_crf[0], 0); \
6840 GEN_TM_PRIV_NOOP(treclaim
);
6841 GEN_TM_PRIV_NOOP(trechkpt
);
6843 static opcode_t opcodes
[] = {
6844 GEN_HANDLER(invalid
, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE
),
6845 GEN_HANDLER(cmp
, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER
),
6846 GEN_HANDLER(cmpi
, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
6847 GEN_HANDLER(cmpl
, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER
),
6848 GEN_HANDLER(cmpli
, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
6849 #if defined(TARGET_PPC64)
6850 GEN_HANDLER_E(cmpeqb
, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE
, PPC2_ISA300
),
6852 GEN_HANDLER_E(cmpb
, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE
, PPC2_ISA205
),
6853 GEN_HANDLER_E(cmprb
, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE
, PPC2_ISA300
),
6854 GEN_HANDLER(isel
, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL
),
6855 GEN_HANDLER(addi
, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6856 GEN_HANDLER(addic
, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6857 GEN_HANDLER2(addic_
, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6858 GEN_HANDLER(addis
, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6859 GEN_HANDLER_E(addpcis
, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA300
),
6860 GEN_HANDLER(mulhw
, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER
),
6861 GEN_HANDLER(mulhwu
, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER
),
6862 GEN_HANDLER(mullw
, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER
),
6863 GEN_HANDLER(mullwo
, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER
),
6864 GEN_HANDLER(mulli
, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6865 #if defined(TARGET_PPC64)
6866 GEN_HANDLER(mulld
, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B
),
6868 GEN_HANDLER(neg
, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER
),
6869 GEN_HANDLER(nego
, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER
),
6870 GEN_HANDLER(subfic
, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6871 GEN_HANDLER2(andi_
, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6872 GEN_HANDLER2(andis_
, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6873 GEN_HANDLER(cntlzw
, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER
),
6874 GEN_HANDLER_E(cnttzw
, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE
, PPC2_ISA300
),
6875 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER
),
6876 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER
),
6877 GEN_HANDLER(ori
, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6878 GEN_HANDLER(oris
, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6879 GEN_HANDLER(xori
, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6880 GEN_HANDLER(xoris
, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6881 GEN_HANDLER(popcntb
, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB
),
6882 GEN_HANDLER(popcntw
, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD
),
6883 GEN_HANDLER_E(prtyw
, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE
, PPC2_ISA205
),
6884 #if defined(TARGET_PPC64)
6885 GEN_HANDLER(popcntd
, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD
),
6886 GEN_HANDLER(cntlzd
, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B
),
6887 GEN_HANDLER_E(cnttzd
, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE
, PPC2_ISA300
),
6888 GEN_HANDLER_E(prtyd
, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE
, PPC2_ISA205
),
6889 GEN_HANDLER_E(bpermd
, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE
, PPC2_PERM_ISA206
),
6891 GEN_HANDLER(rlwimi
, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6892 GEN_HANDLER(rlwinm
, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6893 GEN_HANDLER(rlwnm
, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6894 GEN_HANDLER(slw
, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER
),
6895 GEN_HANDLER(sraw
, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER
),
6896 GEN_HANDLER(srawi
, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER
),
6897 GEN_HANDLER(srw
, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER
),
6898 #if defined(TARGET_PPC64)
6899 GEN_HANDLER(sld
, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B
),
6900 GEN_HANDLER(srad
, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B
),
6901 GEN_HANDLER2(sradi0
, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B
),
6902 GEN_HANDLER2(sradi1
, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B
),
6903 GEN_HANDLER(srd
, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B
),
6905 #if defined(TARGET_PPC64)
6906 GEN_HANDLER(ld
, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B
),
6907 GEN_HANDLER(lq
, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX
),
6908 GEN_HANDLER(std
, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B
),
6910 GEN_HANDLER(lmw
, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6911 GEN_HANDLER(stmw
, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6912 GEN_HANDLER(lswi
, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING
),
6913 GEN_HANDLER(lswx
, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING
),
6914 GEN_HANDLER(stswi
, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING
),
6915 GEN_HANDLER(stswx
, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING
),
6916 GEN_HANDLER(eieio
, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO
),
6917 GEN_HANDLER(isync
, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM
),
6918 GEN_HANDLER_E(lbarx
, 0x1F, 0x14, 0x01, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
6919 GEN_HANDLER_E(lharx
, 0x1F, 0x14, 0x03, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
6920 GEN_HANDLER(lwarx
, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES
),
6921 GEN_HANDLER_E(stbcx_
, 0x1F, 0x16, 0x15, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
6922 GEN_HANDLER_E(sthcx_
, 0x1F, 0x16, 0x16, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
6923 GEN_HANDLER2(stwcx_
, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES
),
6924 #if defined(TARGET_PPC64)
6925 GEN_HANDLER(ldarx
, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B
),
6926 GEN_HANDLER_E(lqarx
, 0x1F, 0x14, 0x08, 0, PPC_NONE
, PPC2_LSQ_ISA207
),
6927 GEN_HANDLER2(stdcx_
, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B
),
6928 GEN_HANDLER_E(stqcx_
, 0x1F, 0x16, 0x05, 0, PPC_NONE
, PPC2_LSQ_ISA207
),
6930 GEN_HANDLER(sync
, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC
),
6931 GEN_HANDLER(wait
, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT
),
6932 GEN_HANDLER(b
, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
6933 GEN_HANDLER(bc
, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
6934 GEN_HANDLER(bcctr
, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW
),
6935 GEN_HANDLER(bclr
, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW
),
6936 GEN_HANDLER_E(bctar
, 0x13, 0x10, 0x11, 0, PPC_NONE
, PPC2_BCTAR_ISA207
),
6937 GEN_HANDLER(mcrf
, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER
),
6938 GEN_HANDLER(rfi
, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW
),
6939 #if defined(TARGET_PPC64)
6940 GEN_HANDLER(rfid
, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B
),
6941 GEN_HANDLER_E(doze
, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
6942 GEN_HANDLER_E(nap
, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
6943 GEN_HANDLER_E(sleep
, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
6944 GEN_HANDLER_E(rvwinkle
, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
6945 GEN_HANDLER(hrfid
, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H
),
6947 GEN_HANDLER(sc
, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW
),
6948 GEN_HANDLER(tw
, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW
),
6949 GEN_HANDLER(twi
, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
6950 #if defined(TARGET_PPC64)
6951 GEN_HANDLER(td
, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B
),
6952 GEN_HANDLER(tdi
, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B
),
6954 GEN_HANDLER(mcrxr
, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC
),
6955 GEN_HANDLER(mfcr
, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC
),
6956 GEN_HANDLER(mfmsr
, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC
),
6957 GEN_HANDLER(mfspr
, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC
),
6958 GEN_HANDLER(mftb
, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB
),
6959 GEN_HANDLER(mtcrf
, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC
),
6960 #if defined(TARGET_PPC64)
6961 GEN_HANDLER(mtmsrd
, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B
),
6962 GEN_HANDLER_E(setb
, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE
, PPC2_ISA300
),
6964 GEN_HANDLER(mtmsr
, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC
),
6965 GEN_HANDLER(mtspr
, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC
),
6966 GEN_HANDLER(dcbf
, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE
),
6967 GEN_HANDLER(dcbi
, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE
),
6968 GEN_HANDLER(dcbst
, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE
),
6969 GEN_HANDLER(dcbt
, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE
),
6970 GEN_HANDLER(dcbtst
, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE
),
6971 GEN_HANDLER_E(dcbtls
, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE
, PPC2_BOOKE206
),
6972 GEN_HANDLER(dcbz
, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ
),
6973 GEN_HANDLER(dst
, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC
),
6974 GEN_HANDLER(dstst
, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC
),
6975 GEN_HANDLER(dss
, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC
),
6976 GEN_HANDLER(icbi
, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI
),
6977 GEN_HANDLER(dcba
, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA
),
6978 GEN_HANDLER(mfsr
, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT
),
6979 GEN_HANDLER(mfsrin
, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT
),
6980 GEN_HANDLER(mtsr
, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT
),
6981 GEN_HANDLER(mtsrin
, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT
),
6982 #if defined(TARGET_PPC64)
6983 GEN_HANDLER2(mfsr_64b
, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B
),
6984 GEN_HANDLER2(mfsrin_64b
, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6986 GEN_HANDLER2(mtsr_64b
, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B
),
6987 GEN_HANDLER2(mtsrin_64b
, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6989 GEN_HANDLER2(slbmte
, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B
),
6990 GEN_HANDLER2(slbmfee
, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B
),
6991 GEN_HANDLER2(slbmfev
, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B
),
6992 GEN_HANDLER2(slbfee_
, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B
),
6994 GEN_HANDLER(tlbia
, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA
),
6995 /* XXX Those instructions will need to be handled differently for
6996 * different ISA versions */
6997 GEN_HANDLER(tlbiel
, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE
),
6998 GEN_HANDLER(tlbie
, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE
),
6999 GEN_HANDLER(tlbsync
, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC
),
7000 #if defined(TARGET_PPC64)
7001 GEN_HANDLER(slbia
, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI
),
7002 GEN_HANDLER(slbie
, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI
),
7004 GEN_HANDLER(eciwx
, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN
),
7005 GEN_HANDLER(ecowx
, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN
),
7006 GEN_HANDLER(abs
, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR
),
7007 GEN_HANDLER(abso
, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR
),
7008 GEN_HANDLER(clcs
, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR
),
7009 GEN_HANDLER(div
, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR
),
7010 GEN_HANDLER(divo
, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR
),
7011 GEN_HANDLER(divs
, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR
),
7012 GEN_HANDLER(divso
, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR
),
7013 GEN_HANDLER(doz
, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR
),
7014 GEN_HANDLER(dozo
, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR
),
7015 GEN_HANDLER(dozi
, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
7016 GEN_HANDLER(lscbx
, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR
),
7017 GEN_HANDLER(maskg
, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR
),
7018 GEN_HANDLER(maskir
, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR
),
7019 GEN_HANDLER(mul
, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR
),
7020 GEN_HANDLER(mulo
, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR
),
7021 GEN_HANDLER(nabs
, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR
),
7022 GEN_HANDLER(nabso
, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR
),
7023 GEN_HANDLER(rlmi
, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
7024 GEN_HANDLER(rrib
, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR
),
7025 GEN_HANDLER(sle
, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR
),
7026 GEN_HANDLER(sleq
, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR
),
7027 GEN_HANDLER(sliq
, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR
),
7028 GEN_HANDLER(slliq
, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR
),
7029 GEN_HANDLER(sllq
, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR
),
7030 GEN_HANDLER(slq
, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR
),
7031 GEN_HANDLER(sraiq
, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR
),
7032 GEN_HANDLER(sraq
, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR
),
7033 GEN_HANDLER(sre
, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR
),
7034 GEN_HANDLER(srea
, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR
),
7035 GEN_HANDLER(sreq
, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR
),
7036 GEN_HANDLER(sriq
, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR
),
7037 GEN_HANDLER(srliq
, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR
),
7038 GEN_HANDLER(srlq
, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR
),
7039 GEN_HANDLER(srq
, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR
),
7040 GEN_HANDLER(dsa
, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC
),
7041 GEN_HANDLER(esa
, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC
),
7042 GEN_HANDLER(mfrom
, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC
),
7043 GEN_HANDLER2(tlbld_6xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB
),
7044 GEN_HANDLER2(tlbli_6xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB
),
7045 GEN_HANDLER2(tlbld_74xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB
),
7046 GEN_HANDLER2(tlbli_74xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB
),
7047 GEN_HANDLER(clf
, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER
),
7048 GEN_HANDLER(cli
, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER
),
7049 GEN_HANDLER(dclst
, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER
),
7050 GEN_HANDLER(mfsri
, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER
),
7051 GEN_HANDLER(rac
, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER
),
7052 GEN_HANDLER(rfsvc
, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER
),
7053 GEN_HANDLER(lfq
, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
7054 GEN_HANDLER(lfqu
, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
7055 GEN_HANDLER(lfqux
, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2
),
7056 GEN_HANDLER(lfqx
, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2
),
7057 GEN_HANDLER(stfq
, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
7058 GEN_HANDLER(stfqu
, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
7059 GEN_HANDLER(stfqux
, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2
),
7060 GEN_HANDLER(stfqx
, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2
),
7061 GEN_HANDLER(mfapidi
, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI
),
7062 GEN_HANDLER(tlbiva
, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA
),
7063 GEN_HANDLER(mfdcr
, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR
),
7064 GEN_HANDLER(mtdcr
, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR
),
7065 GEN_HANDLER(mfdcrx
, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX
),
7066 GEN_HANDLER(mtdcrx
, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX
),
7067 GEN_HANDLER(mfdcrux
, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX
),
7068 GEN_HANDLER(mtdcrux
, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX
),
7069 GEN_HANDLER(dccci
, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON
),
7070 GEN_HANDLER(dcread
, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON
),
7071 GEN_HANDLER2(icbt_40x
, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT
),
7072 GEN_HANDLER(iccci
, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON
),
7073 GEN_HANDLER(icread
, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON
),
7074 GEN_HANDLER2(rfci_40x
, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP
),
7075 GEN_HANDLER_E(rfci
, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE
, PPC2_BOOKE206
),
7076 GEN_HANDLER(rfdi
, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI
),
7077 GEN_HANDLER(rfmci
, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI
),
7078 GEN_HANDLER2(tlbre_40x
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB
),
7079 GEN_HANDLER2(tlbsx_40x
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB
),
7080 GEN_HANDLER2(tlbwe_40x
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB
),
7081 GEN_HANDLER2(tlbre_440
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE
),
7082 GEN_HANDLER2(tlbsx_440
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE
),
7083 GEN_HANDLER2(tlbwe_440
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE
),
7084 GEN_HANDLER2_E(tlbre_booke206
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
7085 PPC_NONE
, PPC2_BOOKE206
),
7086 GEN_HANDLER2_E(tlbsx_booke206
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
7087 PPC_NONE
, PPC2_BOOKE206
),
7088 GEN_HANDLER2_E(tlbwe_booke206
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
7089 PPC_NONE
, PPC2_BOOKE206
),
7090 GEN_HANDLER2_E(tlbivax_booke206
, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
7091 PPC_NONE
, PPC2_BOOKE206
),
7092 GEN_HANDLER2_E(tlbilx_booke206
, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
7093 PPC_NONE
, PPC2_BOOKE206
),
7094 GEN_HANDLER2_E(msgsnd
, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
7095 PPC_NONE
, PPC2_PRCNTL
),
7096 GEN_HANDLER2_E(msgclr
, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
7097 PPC_NONE
, PPC2_PRCNTL
),
7098 GEN_HANDLER(wrtee
, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE
),
7099 GEN_HANDLER(wrteei
, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE
),
7100 GEN_HANDLER(dlmzb
, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC
),
7101 GEN_HANDLER_E(mbar
, 0x1F, 0x16, 0x1a, 0x001FF801,
7102 PPC_BOOKE
, PPC2_BOOKE206
),
7103 GEN_HANDLER(msync_4xx
, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE
),
7104 GEN_HANDLER2_E(icbt_440
, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
7105 PPC_BOOKE
, PPC2_BOOKE206
),
7106 GEN_HANDLER(lvsl
, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC
),
7107 GEN_HANDLER(lvsr
, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC
),
7108 GEN_HANDLER(mfvscr
, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC
),
7109 GEN_HANDLER(mtvscr
, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC
),
7110 GEN_HANDLER(vmladduhm
, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC
),
7111 #if defined(TARGET_PPC64)
7112 GEN_HANDLER_E(maddhd_maddhdu
, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE
,
7114 GEN_HANDLER_E(maddld
, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA300
),
7117 #undef GEN_INT_ARITH_ADD
7118 #undef GEN_INT_ARITH_ADD_CONST
7119 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
7120 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
7121 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
7122 add_ca, compute_ca, compute_ov) \
7123 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
7124 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
7125 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
7126 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
7127 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
7128 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
7129 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
7130 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
7131 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
7132 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
7133 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
7135 #undef GEN_INT_ARITH_DIVW
7136 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
7137 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
7138 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0),
7139 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1),
7140 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0),
7141 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1),
7142 GEN_HANDLER_E(divwe
, 0x1F, 0x0B, 0x0D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7143 GEN_HANDLER_E(divweo
, 0x1F, 0x0B, 0x1D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7144 GEN_HANDLER_E(divweu
, 0x1F, 0x0B, 0x0C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7145 GEN_HANDLER_E(divweuo
, 0x1F, 0x0B, 0x1C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7146 GEN_HANDLER_E(modsw
, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7147 GEN_HANDLER_E(moduw
, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7149 #if defined(TARGET_PPC64)
7150 #undef GEN_INT_ARITH_DIVD
7151 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
7152 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
7153 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0),
7154 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1),
7155 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0),
7156 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1),
7158 GEN_HANDLER_E(divdeu
, 0x1F, 0x09, 0x0C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7159 GEN_HANDLER_E(divdeuo
, 0x1F, 0x09, 0x1C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7160 GEN_HANDLER_E(divde
, 0x1F, 0x09, 0x0D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7161 GEN_HANDLER_E(divdeo
, 0x1F, 0x09, 0x1D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7162 GEN_HANDLER_E(modsd
, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7163 GEN_HANDLER_E(modud
, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7165 #undef GEN_INT_ARITH_MUL_HELPER
7166 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
7167 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
7168 GEN_INT_ARITH_MUL_HELPER(mulhdu
, 0x00),
7169 GEN_INT_ARITH_MUL_HELPER(mulhd
, 0x02),
7170 GEN_INT_ARITH_MUL_HELPER(mulldo
, 0x17),
7173 #undef GEN_INT_ARITH_SUBF
7174 #undef GEN_INT_ARITH_SUBF_CONST
7175 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
7176 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
7177 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
7178 add_ca, compute_ca, compute_ov) \
7179 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
7180 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
7181 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
7182 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
7183 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
7184 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
7185 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
7186 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
7187 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
7188 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
7189 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
7193 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
7194 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
7195 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
7196 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
7197 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
),
7198 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
),
7199 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
),
7200 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
),
7201 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
),
7202 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
),
7203 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
),
7204 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
),
7205 #if defined(TARGET_PPC64)
7206 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
),
7209 #if defined(TARGET_PPC64)
7212 #define GEN_PPC64_R2(name, opc1, opc2) \
7213 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
7214 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
7216 #define GEN_PPC64_R4(name, opc1, opc2) \
7217 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
7218 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
7220 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
7222 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
7224 GEN_PPC64_R4(rldicl
, 0x1E, 0x00),
7225 GEN_PPC64_R4(rldicr
, 0x1E, 0x02),
7226 GEN_PPC64_R4(rldic
, 0x1E, 0x04),
7227 GEN_PPC64_R2(rldcl
, 0x1E, 0x08),
7228 GEN_PPC64_R2(rldcr
, 0x1E, 0x09),
7229 GEN_PPC64_R4(rldimi
, 0x1E, 0x06),
7237 #define GEN_LD(name, ldop, opc, type) \
7238 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
7239 #define GEN_LDU(name, ldop, opc, type) \
7240 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
7241 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
7242 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
7243 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
7244 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
7245 #define GEN_LDS(name, ldop, op, type) \
7246 GEN_LD(name, ldop, op | 0x20, type) \
7247 GEN_LDU(name, ldop, op | 0x21, type) \
7248 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
7249 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
7251 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
)
7252 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
)
7253 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
)
7254 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
)
7255 #if defined(TARGET_PPC64)
7256 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
)
7257 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
)
7258 GEN_LDUX(ld
, ld64
, 0x15, 0x01, PPC_64B
)
7259 GEN_LDX(ld
, ld64
, 0x15, 0x00, PPC_64B
)
7260 GEN_LDX_E(ldbr
, ld64ur
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
, CHK_NONE
)
7262 /* HV/P7 and later only */
7263 GEN_LDX_HVRM(ldcix
, ld64
, 0x15, 0x1b, PPC_CILDST
)
7264 GEN_LDX_HVRM(lwzcix
, ld32u
, 0x15, 0x18, PPC_CILDST
)
7265 GEN_LDX_HVRM(lhzcix
, ld16u
, 0x15, 0x19, PPC_CILDST
)
7266 GEN_LDX_HVRM(lbzcix
, ld8u
, 0x15, 0x1a, PPC_CILDST
)
7268 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
)
7269 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
)
7276 #define GEN_ST(name, stop, opc, type) \
7277 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
7278 #define GEN_STU(name, stop, opc, type) \
7279 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
7280 #define GEN_STUX(name, stop, opc2, opc3, type) \
7281 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
7282 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
7283 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
7284 #define GEN_STS(name, stop, op, type) \
7285 GEN_ST(name, stop, op | 0x20, type) \
7286 GEN_STU(name, stop, op | 0x21, type) \
7287 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
7288 GEN_STX(name, stop, 0x17, op | 0x00, type)
7290 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
)
7291 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
)
7292 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
)
7293 #if defined(TARGET_PPC64)
7294 GEN_STUX(std
, st64
, 0x15, 0x05, PPC_64B
)
7295 GEN_STX(std
, st64
, 0x15, 0x04, PPC_64B
)
7296 GEN_STX_E(stdbr
, st64r
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
, CHK_NONE
)
7297 GEN_STX_HVRM(stdcix
, st64
, 0x15, 0x1f, PPC_CILDST
)
7298 GEN_STX_HVRM(stwcix
, st32
, 0x15, 0x1c, PPC_CILDST
)
7299 GEN_STX_HVRM(sthcix
, st16
, 0x15, 0x1d, PPC_CILDST
)
7300 GEN_STX_HVRM(stbcix
, st8
, 0x15, 0x1e, PPC_CILDST
)
7302 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
)
7303 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
)
7306 #define GEN_CRLOGIC(name, tcg_op, opc) \
7307 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
7308 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08),
7309 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04),
7310 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09),
7311 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07),
7312 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01),
7313 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E),
7314 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D),
7315 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06),
7317 #undef GEN_MAC_HANDLER
7318 #define GEN_MAC_HANDLER(name, opc2, opc3) \
7319 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
7320 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05),
7321 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15),
7322 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07),
7323 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17),
7324 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06),
7325 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16),
7326 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04),
7327 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14),
7328 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01),
7329 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11),
7330 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03),
7331 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13),
7332 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02),
7333 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12),
7334 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00),
7335 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10),
7336 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D),
7337 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D),
7338 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F),
7339 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F),
7340 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C),
7341 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C),
7342 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E),
7343 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E),
7344 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05),
7345 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15),
7346 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07),
7347 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17),
7348 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01),
7349 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11),
7350 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03),
7351 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13),
7352 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D),
7353 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D),
7354 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F),
7355 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F),
7356 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05),
7357 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04),
7358 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01),
7359 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00),
7360 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D),
7361 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C),
7363 #include "translate/fp-ops.c"
7365 #include "translate/vmx-ops.c"
7367 GEN_HANDLER_E(lxsdx
, 0x1F, 0x0C, 0x12, 0, PPC_NONE
, PPC2_VSX
),
7368 GEN_HANDLER_E(lxsiwax
, 0x1F, 0x0C, 0x02, 0, PPC_NONE
, PPC2_VSX207
),
7369 GEN_HANDLER_E(lxsiwzx
, 0x1F, 0x0C, 0x00, 0, PPC_NONE
, PPC2_VSX207
),
7370 GEN_HANDLER_E(lxsspx
, 0x1F, 0x0C, 0x10, 0, PPC_NONE
, PPC2_VSX207
),
7371 GEN_HANDLER_E(lxvd2x
, 0x1F, 0x0C, 0x1A, 0, PPC_NONE
, PPC2_VSX
),
7372 GEN_HANDLER_E(lxvdsx
, 0x1F, 0x0C, 0x0A, 0, PPC_NONE
, PPC2_VSX
),
7373 GEN_HANDLER_E(lxvw4x
, 0x1F, 0x0C, 0x18, 0, PPC_NONE
, PPC2_VSX
),
7375 GEN_HANDLER_E(stxsdx
, 0x1F, 0xC, 0x16, 0, PPC_NONE
, PPC2_VSX
),
7376 GEN_HANDLER_E(stxsiwx
, 0x1F, 0xC, 0x04, 0, PPC_NONE
, PPC2_VSX207
),
7377 GEN_HANDLER_E(stxsspx
, 0x1F, 0xC, 0x14, 0, PPC_NONE
, PPC2_VSX207
),
7378 GEN_HANDLER_E(stxvd2x
, 0x1F, 0xC, 0x1E, 0, PPC_NONE
, PPC2_VSX
),
7379 GEN_HANDLER_E(stxvw4x
, 0x1F, 0xC, 0x1C, 0, PPC_NONE
, PPC2_VSX
),
7381 GEN_HANDLER_E(mfvsrwz
, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
7382 GEN_HANDLER_E(mtvsrwa
, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
7383 GEN_HANDLER_E(mtvsrwz
, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
7384 #if defined(TARGET_PPC64)
7385 GEN_HANDLER_E(mfvsrd
, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
7386 GEN_HANDLER_E(mtvsrd
, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
7390 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
7391 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
7392 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
7395 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
7396 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
7397 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
7398 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
7399 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
7402 #define GEN_XX2IFORM(name, opc2, opc3, fl2) \
7403 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \
7404 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \
7405 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \
7406 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
7408 #undef GEN_XX3_RC_FORM
7409 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
7410 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
7411 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
7412 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
7413 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
7414 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
7415 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
7416 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
7417 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
7419 #undef GEN_XX3FORM_DM
7420 #define GEN_XX3FORM_DM(name, opc2, opc3) \
7421 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
7422 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
7423 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
7424 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
7425 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
7426 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
7427 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
7428 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
7429 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
7430 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
7431 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
7432 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
7433 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
7434 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
7435 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
7436 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
7438 GEN_XX2FORM(xsabsdp
, 0x12, 0x15, PPC2_VSX
),
7439 GEN_XX2FORM(xsnabsdp
, 0x12, 0x16, PPC2_VSX
),
7440 GEN_XX2FORM(xsnegdp
, 0x12, 0x17, PPC2_VSX
),
7441 GEN_XX3FORM(xscpsgndp
, 0x00, 0x16, PPC2_VSX
),
7443 GEN_XX2FORM(xvabsdp
, 0x12, 0x1D, PPC2_VSX
),
7444 GEN_XX2FORM(xvnabsdp
, 0x12, 0x1E, PPC2_VSX
),
7445 GEN_XX2FORM(xvnegdp
, 0x12, 0x1F, PPC2_VSX
),
7446 GEN_XX3FORM(xvcpsgndp
, 0x00, 0x1E, PPC2_VSX
),
7447 GEN_XX2FORM(xvabssp
, 0x12, 0x19, PPC2_VSX
),
7448 GEN_XX2FORM(xvnabssp
, 0x12, 0x1A, PPC2_VSX
),
7449 GEN_XX2FORM(xvnegsp
, 0x12, 0x1B, PPC2_VSX
),
7450 GEN_XX3FORM(xvcpsgnsp
, 0x00, 0x1A, PPC2_VSX
),
7452 GEN_XX3FORM(xsadddp
, 0x00, 0x04, PPC2_VSX
),
7453 GEN_XX3FORM(xssubdp
, 0x00, 0x05, PPC2_VSX
),
7454 GEN_XX3FORM(xsmuldp
, 0x00, 0x06, PPC2_VSX
),
7455 GEN_XX3FORM(xsdivdp
, 0x00, 0x07, PPC2_VSX
),
7456 GEN_XX2FORM(xsredp
, 0x14, 0x05, PPC2_VSX
),
7457 GEN_XX2FORM(xssqrtdp
, 0x16, 0x04, PPC2_VSX
),
7458 GEN_XX2FORM(xsrsqrtedp
, 0x14, 0x04, PPC2_VSX
),
7459 GEN_XX3FORM(xstdivdp
, 0x14, 0x07, PPC2_VSX
),
7460 GEN_XX2FORM(xstsqrtdp
, 0x14, 0x06, PPC2_VSX
),
7461 GEN_XX3FORM(xsmaddadp
, 0x04, 0x04, PPC2_VSX
),
7462 GEN_XX3FORM(xsmaddmdp
, 0x04, 0x05, PPC2_VSX
),
7463 GEN_XX3FORM(xsmsubadp
, 0x04, 0x06, PPC2_VSX
),
7464 GEN_XX3FORM(xsmsubmdp
, 0x04, 0x07, PPC2_VSX
),
7465 GEN_XX3FORM(xsnmaddadp
, 0x04, 0x14, PPC2_VSX
),
7466 GEN_XX3FORM(xsnmaddmdp
, 0x04, 0x15, PPC2_VSX
),
7467 GEN_XX3FORM(xsnmsubadp
, 0x04, 0x16, PPC2_VSX
),
7468 GEN_XX3FORM(xsnmsubmdp
, 0x04, 0x17, PPC2_VSX
),
7469 GEN_XX2IFORM(xscmpodp
, 0x0C, 0x05, PPC2_VSX
),
7470 GEN_XX2IFORM(xscmpudp
, 0x0C, 0x04, PPC2_VSX
),
7471 GEN_XX3FORM(xsmaxdp
, 0x00, 0x14, PPC2_VSX
),
7472 GEN_XX3FORM(xsmindp
, 0x00, 0x15, PPC2_VSX
),
7473 GEN_XX2FORM(xscvdpsp
, 0x12, 0x10, PPC2_VSX
),
7474 GEN_XX2FORM(xscvdpspn
, 0x16, 0x10, PPC2_VSX207
),
7475 GEN_XX2FORM(xscvspdp
, 0x12, 0x14, PPC2_VSX
),
7476 GEN_XX2FORM(xscvspdpn
, 0x16, 0x14, PPC2_VSX207
),
7477 GEN_XX2FORM(xscvdpsxds
, 0x10, 0x15, PPC2_VSX
),
7478 GEN_XX2FORM(xscvdpsxws
, 0x10, 0x05, PPC2_VSX
),
7479 GEN_XX2FORM(xscvdpuxds
, 0x10, 0x14, PPC2_VSX
),
7480 GEN_XX2FORM(xscvdpuxws
, 0x10, 0x04, PPC2_VSX
),
7481 GEN_XX2FORM(xscvsxddp
, 0x10, 0x17, PPC2_VSX
),
7482 GEN_XX2FORM(xscvuxddp
, 0x10, 0x16, PPC2_VSX
),
7483 GEN_XX2FORM(xsrdpi
, 0x12, 0x04, PPC2_VSX
),
7484 GEN_XX2FORM(xsrdpic
, 0x16, 0x06, PPC2_VSX
),
7485 GEN_XX2FORM(xsrdpim
, 0x12, 0x07, PPC2_VSX
),
7486 GEN_XX2FORM(xsrdpip
, 0x12, 0x06, PPC2_VSX
),
7487 GEN_XX2FORM(xsrdpiz
, 0x12, 0x05, PPC2_VSX
),
7489 GEN_XX3FORM(xsaddsp
, 0x00, 0x00, PPC2_VSX207
),
7490 GEN_XX3FORM(xssubsp
, 0x00, 0x01, PPC2_VSX207
),
7491 GEN_XX3FORM(xsmulsp
, 0x00, 0x02, PPC2_VSX207
),
7492 GEN_XX3FORM(xsdivsp
, 0x00, 0x03, PPC2_VSX207
),
7493 GEN_XX2FORM(xsresp
, 0x14, 0x01, PPC2_VSX207
),
7494 GEN_XX2FORM(xsrsp
, 0x12, 0x11, PPC2_VSX207
),
7495 GEN_XX2FORM(xssqrtsp
, 0x16, 0x00, PPC2_VSX207
),
7496 GEN_XX2FORM(xsrsqrtesp
, 0x14, 0x00, PPC2_VSX207
),
7497 GEN_XX3FORM(xsmaddasp
, 0x04, 0x00, PPC2_VSX207
),
7498 GEN_XX3FORM(xsmaddmsp
, 0x04, 0x01, PPC2_VSX207
),
7499 GEN_XX3FORM(xsmsubasp
, 0x04, 0x02, PPC2_VSX207
),
7500 GEN_XX3FORM(xsmsubmsp
, 0x04, 0x03, PPC2_VSX207
),
7501 GEN_XX3FORM(xsnmaddasp
, 0x04, 0x10, PPC2_VSX207
),
7502 GEN_XX3FORM(xsnmaddmsp
, 0x04, 0x11, PPC2_VSX207
),
7503 GEN_XX3FORM(xsnmsubasp
, 0x04, 0x12, PPC2_VSX207
),
7504 GEN_XX3FORM(xsnmsubmsp
, 0x04, 0x13, PPC2_VSX207
),
7505 GEN_XX2FORM(xscvsxdsp
, 0x10, 0x13, PPC2_VSX207
),
7506 GEN_XX2FORM(xscvuxdsp
, 0x10, 0x12, PPC2_VSX207
),
7508 GEN_XX3FORM(xvadddp
, 0x00, 0x0C, PPC2_VSX
),
7509 GEN_XX3FORM(xvsubdp
, 0x00, 0x0D, PPC2_VSX
),
7510 GEN_XX3FORM(xvmuldp
, 0x00, 0x0E, PPC2_VSX
),
7511 GEN_XX3FORM(xvdivdp
, 0x00, 0x0F, PPC2_VSX
),
7512 GEN_XX2FORM(xvredp
, 0x14, 0x0D, PPC2_VSX
),
7513 GEN_XX2FORM(xvsqrtdp
, 0x16, 0x0C, PPC2_VSX
),
7514 GEN_XX2FORM(xvrsqrtedp
, 0x14, 0x0C, PPC2_VSX
),
7515 GEN_XX3FORM(xvtdivdp
, 0x14, 0x0F, PPC2_VSX
),
7516 GEN_XX2FORM(xvtsqrtdp
, 0x14, 0x0E, PPC2_VSX
),
7517 GEN_XX3FORM(xvmaddadp
, 0x04, 0x0C, PPC2_VSX
),
7518 GEN_XX3FORM(xvmaddmdp
, 0x04, 0x0D, PPC2_VSX
),
7519 GEN_XX3FORM(xvmsubadp
, 0x04, 0x0E, PPC2_VSX
),
7520 GEN_XX3FORM(xvmsubmdp
, 0x04, 0x0F, PPC2_VSX
),
7521 GEN_XX3FORM(xvnmaddadp
, 0x04, 0x1C, PPC2_VSX
),
7522 GEN_XX3FORM(xvnmaddmdp
, 0x04, 0x1D, PPC2_VSX
),
7523 GEN_XX3FORM(xvnmsubadp
, 0x04, 0x1E, PPC2_VSX
),
7524 GEN_XX3FORM(xvnmsubmdp
, 0x04, 0x1F, PPC2_VSX
),
7525 GEN_XX3FORM(xvmaxdp
, 0x00, 0x1C, PPC2_VSX
),
7526 GEN_XX3FORM(xvmindp
, 0x00, 0x1D, PPC2_VSX
),
7527 GEN_XX3_RC_FORM(xvcmpeqdp
, 0x0C, 0x0C, PPC2_VSX
),
7528 GEN_XX3_RC_FORM(xvcmpgtdp
, 0x0C, 0x0D, PPC2_VSX
),
7529 GEN_XX3_RC_FORM(xvcmpgedp
, 0x0C, 0x0E, PPC2_VSX
),
7530 GEN_XX2FORM(xvcvdpsp
, 0x12, 0x18, PPC2_VSX
),
7531 GEN_XX2FORM(xvcvdpsxds
, 0x10, 0x1D, PPC2_VSX
),
7532 GEN_XX2FORM(xvcvdpsxws
, 0x10, 0x0D, PPC2_VSX
),
7533 GEN_XX2FORM(xvcvdpuxds
, 0x10, 0x1C, PPC2_VSX
),
7534 GEN_XX2FORM(xvcvdpuxws
, 0x10, 0x0C, PPC2_VSX
),
7535 GEN_XX2FORM(xvcvsxddp
, 0x10, 0x1F, PPC2_VSX
),
7536 GEN_XX2FORM(xvcvuxddp
, 0x10, 0x1E, PPC2_VSX
),
7537 GEN_XX2FORM(xvcvsxwdp
, 0x10, 0x0F, PPC2_VSX
),
7538 GEN_XX2FORM(xvcvuxwdp
, 0x10, 0x0E, PPC2_VSX
),
7539 GEN_XX2FORM(xvrdpi
, 0x12, 0x0C, PPC2_VSX
),
7540 GEN_XX2FORM(xvrdpic
, 0x16, 0x0E, PPC2_VSX
),
7541 GEN_XX2FORM(xvrdpim
, 0x12, 0x0F, PPC2_VSX
),
7542 GEN_XX2FORM(xvrdpip
, 0x12, 0x0E, PPC2_VSX
),
7543 GEN_XX2FORM(xvrdpiz
, 0x12, 0x0D, PPC2_VSX
),
7545 GEN_XX3FORM(xvaddsp
, 0x00, 0x08, PPC2_VSX
),
7546 GEN_XX3FORM(xvsubsp
, 0x00, 0x09, PPC2_VSX
),
7547 GEN_XX3FORM(xvmulsp
, 0x00, 0x0A, PPC2_VSX
),
7548 GEN_XX3FORM(xvdivsp
, 0x00, 0x0B, PPC2_VSX
),
7549 GEN_XX2FORM(xvresp
, 0x14, 0x09, PPC2_VSX
),
7550 GEN_XX2FORM(xvsqrtsp
, 0x16, 0x08, PPC2_VSX
),
7551 GEN_XX2FORM(xvrsqrtesp
, 0x14, 0x08, PPC2_VSX
),
7552 GEN_XX3FORM(xvtdivsp
, 0x14, 0x0B, PPC2_VSX
),
7553 GEN_XX2FORM(xvtsqrtsp
, 0x14, 0x0A, PPC2_VSX
),
7554 GEN_XX3FORM(xvmaddasp
, 0x04, 0x08, PPC2_VSX
),
7555 GEN_XX3FORM(xvmaddmsp
, 0x04, 0x09, PPC2_VSX
),
7556 GEN_XX3FORM(xvmsubasp
, 0x04, 0x0A, PPC2_VSX
),
7557 GEN_XX3FORM(xvmsubmsp
, 0x04, 0x0B, PPC2_VSX
),
7558 GEN_XX3FORM(xvnmaddasp
, 0x04, 0x18, PPC2_VSX
),
7559 GEN_XX3FORM(xvnmaddmsp
, 0x04, 0x19, PPC2_VSX
),
7560 GEN_XX3FORM(xvnmsubasp
, 0x04, 0x1A, PPC2_VSX
),
7561 GEN_XX3FORM(xvnmsubmsp
, 0x04, 0x1B, PPC2_VSX
),
7562 GEN_XX3FORM(xvmaxsp
, 0x00, 0x18, PPC2_VSX
),
7563 GEN_XX3FORM(xvminsp
, 0x00, 0x19, PPC2_VSX
),
7564 GEN_XX3_RC_FORM(xvcmpeqsp
, 0x0C, 0x08, PPC2_VSX
),
7565 GEN_XX3_RC_FORM(xvcmpgtsp
, 0x0C, 0x09, PPC2_VSX
),
7566 GEN_XX3_RC_FORM(xvcmpgesp
, 0x0C, 0x0A, PPC2_VSX
),
7567 GEN_XX2FORM(xvcvspdp
, 0x12, 0x1C, PPC2_VSX
),
7568 GEN_XX2FORM(xvcvspsxds
, 0x10, 0x19, PPC2_VSX
),
7569 GEN_XX2FORM(xvcvspsxws
, 0x10, 0x09, PPC2_VSX
),
7570 GEN_XX2FORM(xvcvspuxds
, 0x10, 0x18, PPC2_VSX
),
7571 GEN_XX2FORM(xvcvspuxws
, 0x10, 0x08, PPC2_VSX
),
7572 GEN_XX2FORM(xvcvsxdsp
, 0x10, 0x1B, PPC2_VSX
),
7573 GEN_XX2FORM(xvcvuxdsp
, 0x10, 0x1A, PPC2_VSX
),
7574 GEN_XX2FORM(xvcvsxwsp
, 0x10, 0x0B, PPC2_VSX
),
7575 GEN_XX2FORM(xvcvuxwsp
, 0x10, 0x0A, PPC2_VSX
),
7576 GEN_XX2FORM(xvrspi
, 0x12, 0x08, PPC2_VSX
),
7577 GEN_XX2FORM(xvrspic
, 0x16, 0x0A, PPC2_VSX
),
7578 GEN_XX2FORM(xvrspim
, 0x12, 0x0B, PPC2_VSX
),
7579 GEN_XX2FORM(xvrspip
, 0x12, 0x0A, PPC2_VSX
),
7580 GEN_XX2FORM(xvrspiz
, 0x12, 0x09, PPC2_VSX
),
7583 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
7584 GEN_XX3FORM(name, opc2, opc3, fl2)
7586 VSX_LOGICAL(xxland
, 0x8, 0x10, PPC2_VSX
),
7587 VSX_LOGICAL(xxlandc
, 0x8, 0x11, PPC2_VSX
),
7588 VSX_LOGICAL(xxlor
, 0x8, 0x12, PPC2_VSX
),
7589 VSX_LOGICAL(xxlxor
, 0x8, 0x13, PPC2_VSX
),
7590 VSX_LOGICAL(xxlnor
, 0x8, 0x14, PPC2_VSX
),
7591 VSX_LOGICAL(xxleqv
, 0x8, 0x17, PPC2_VSX207
),
7592 VSX_LOGICAL(xxlnand
, 0x8, 0x16, PPC2_VSX207
),
7593 VSX_LOGICAL(xxlorc
, 0x8, 0x15, PPC2_VSX207
),
7594 GEN_XX3FORM(xxmrghw
, 0x08, 0x02, PPC2_VSX
),
7595 GEN_XX3FORM(xxmrglw
, 0x08, 0x06, PPC2_VSX
),
7596 GEN_XX2FORM(xxspltw
, 0x08, 0x0A, PPC2_VSX
),
7597 GEN_XX3FORM_DM(xxsldwi
, 0x08, 0x00),
7599 #define GEN_XXSEL_ROW(opc3) \
7600 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
7601 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
7602 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
7603 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
7604 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
7605 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
7606 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
7607 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
7642 GEN_XX3FORM_DM(xxpermdi
, 0x08, 0x01),
7644 #include "translate/dfp-ops.c"
7646 #include "translate/spe-ops.c"
7648 GEN_HANDLER2_E(tbegin
, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
7650 GEN_HANDLER2_E(tend
, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
7652 GEN_HANDLER2_E(tabort
, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
7654 GEN_HANDLER2_E(tabortwc
, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
7656 GEN_HANDLER2_E(tabortwci
, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
7658 GEN_HANDLER2_E(tabortdc
, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
7660 GEN_HANDLER2_E(tabortdci
, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
7662 GEN_HANDLER2_E(tsr
, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
7664 GEN_HANDLER2_E(tcheck
, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
7666 GEN_HANDLER2_E(treclaim
, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
7668 GEN_HANDLER2_E(trechkpt
, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
7672 #include "helper_regs.h"
7673 #include "translate_init.c"
7675 /*****************************************************************************/
7676 /* Misc PowerPC helpers */
7677 void ppc_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
7683 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
7684 CPUPPCState
*env
= &cpu
->env
;
7687 cpu_fprintf(f
, "NIP " TARGET_FMT_lx
" LR " TARGET_FMT_lx
" CTR "
7688 TARGET_FMT_lx
" XER " TARGET_FMT_lx
" CPU#%d\n",
7689 env
->nip
, env
->lr
, env
->ctr
, cpu_read_xer(env
),
7691 cpu_fprintf(f
, "MSR " TARGET_FMT_lx
" HID0 " TARGET_FMT_lx
" HF "
7692 TARGET_FMT_lx
" iidx %d didx %d\n",
7693 env
->msr
, env
->spr
[SPR_HID0
],
7694 env
->hflags
, env
->immu_idx
, env
->dmmu_idx
);
7695 #if !defined(NO_TIMER_DUMP)
7696 cpu_fprintf(f
, "TB %08" PRIu32
" %08" PRIu64
7697 #if !defined(CONFIG_USER_ONLY)
7701 cpu_ppc_load_tbu(env
), cpu_ppc_load_tbl(env
)
7702 #if !defined(CONFIG_USER_ONLY)
7703 , cpu_ppc_load_decr(env
)
7707 for (i
= 0; i
< 32; i
++) {
7708 if ((i
& (RGPL
- 1)) == 0)
7709 cpu_fprintf(f
, "GPR%02d", i
);
7710 cpu_fprintf(f
, " %016" PRIx64
, ppc_dump_gpr(env
, i
));
7711 if ((i
& (RGPL
- 1)) == (RGPL
- 1))
7712 cpu_fprintf(f
, "\n");
7714 cpu_fprintf(f
, "CR ");
7715 for (i
= 0; i
< 8; i
++)
7716 cpu_fprintf(f
, "%01x", env
->crf
[i
]);
7717 cpu_fprintf(f
, " [");
7718 for (i
= 0; i
< 8; i
++) {
7720 if (env
->crf
[i
] & 0x08)
7722 else if (env
->crf
[i
] & 0x04)
7724 else if (env
->crf
[i
] & 0x02)
7726 cpu_fprintf(f
, " %c%c", a
, env
->crf
[i
] & 0x01 ? 'O' : ' ');
7728 cpu_fprintf(f
, " ] RES " TARGET_FMT_lx
"\n",
7730 for (i
= 0; i
< 32; i
++) {
7731 if ((i
& (RFPL
- 1)) == 0)
7732 cpu_fprintf(f
, "FPR%02d", i
);
7733 cpu_fprintf(f
, " %016" PRIx64
, *((uint64_t *)&env
->fpr
[i
]));
7734 if ((i
& (RFPL
- 1)) == (RFPL
- 1))
7735 cpu_fprintf(f
, "\n");
7737 cpu_fprintf(f
, "FPSCR " TARGET_FMT_lx
"\n", env
->fpscr
);
7738 #if !defined(CONFIG_USER_ONLY)
7739 cpu_fprintf(f
, " SRR0 " TARGET_FMT_lx
" SRR1 " TARGET_FMT_lx
7740 " PVR " TARGET_FMT_lx
" VRSAVE " TARGET_FMT_lx
"\n",
7741 env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
],
7742 env
->spr
[SPR_PVR
], env
->spr
[SPR_VRSAVE
]);
7744 cpu_fprintf(f
, "SPRG0 " TARGET_FMT_lx
" SPRG1 " TARGET_FMT_lx
7745 " SPRG2 " TARGET_FMT_lx
" SPRG3 " TARGET_FMT_lx
"\n",
7746 env
->spr
[SPR_SPRG0
], env
->spr
[SPR_SPRG1
],
7747 env
->spr
[SPR_SPRG2
], env
->spr
[SPR_SPRG3
]);
7749 cpu_fprintf(f
, "SPRG4 " TARGET_FMT_lx
" SPRG5 " TARGET_FMT_lx
7750 " SPRG6 " TARGET_FMT_lx
" SPRG7 " TARGET_FMT_lx
"\n",
7751 env
->spr
[SPR_SPRG4
], env
->spr
[SPR_SPRG5
],
7752 env
->spr
[SPR_SPRG6
], env
->spr
[SPR_SPRG7
]);
7754 #if defined(TARGET_PPC64)
7755 if (env
->excp_model
== POWERPC_EXCP_POWER7
||
7756 env
->excp_model
== POWERPC_EXCP_POWER8
) {
7757 cpu_fprintf(f
, "HSRR0 " TARGET_FMT_lx
" HSRR1 " TARGET_FMT_lx
"\n",
7758 env
->spr
[SPR_HSRR0
], env
->spr
[SPR_HSRR1
]);
7761 if (env
->excp_model
== POWERPC_EXCP_BOOKE
) {
7762 cpu_fprintf(f
, "CSRR0 " TARGET_FMT_lx
" CSRR1 " TARGET_FMT_lx
7763 " MCSRR0 " TARGET_FMT_lx
" MCSRR1 " TARGET_FMT_lx
"\n",
7764 env
->spr
[SPR_BOOKE_CSRR0
], env
->spr
[SPR_BOOKE_CSRR1
],
7765 env
->spr
[SPR_BOOKE_MCSRR0
], env
->spr
[SPR_BOOKE_MCSRR1
]);
7767 cpu_fprintf(f
, " TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
7768 " ESR " TARGET_FMT_lx
" DEAR " TARGET_FMT_lx
"\n",
7769 env
->spr
[SPR_BOOKE_TCR
], env
->spr
[SPR_BOOKE_TSR
],
7770 env
->spr
[SPR_BOOKE_ESR
], env
->spr
[SPR_BOOKE_DEAR
]);
7772 cpu_fprintf(f
, " PIR " TARGET_FMT_lx
" DECAR " TARGET_FMT_lx
7773 " IVPR " TARGET_FMT_lx
" EPCR " TARGET_FMT_lx
"\n",
7774 env
->spr
[SPR_BOOKE_PIR
], env
->spr
[SPR_BOOKE_DECAR
],
7775 env
->spr
[SPR_BOOKE_IVPR
], env
->spr
[SPR_BOOKE_EPCR
]);
7777 cpu_fprintf(f
, " MCSR " TARGET_FMT_lx
" SPRG8 " TARGET_FMT_lx
7778 " EPR " TARGET_FMT_lx
"\n",
7779 env
->spr
[SPR_BOOKE_MCSR
], env
->spr
[SPR_BOOKE_SPRG8
],
7780 env
->spr
[SPR_BOOKE_EPR
]);
7783 cpu_fprintf(f
, " MCAR " TARGET_FMT_lx
" PID1 " TARGET_FMT_lx
7784 " PID2 " TARGET_FMT_lx
" SVR " TARGET_FMT_lx
"\n",
7785 env
->spr
[SPR_Exxx_MCAR
], env
->spr
[SPR_BOOKE_PID1
],
7786 env
->spr
[SPR_BOOKE_PID2
], env
->spr
[SPR_E500_SVR
]);
7789 * IVORs are left out as they are large and do not change often --
7790 * they can be read with "p $ivor0", "p $ivor1", etc.
7794 #if defined(TARGET_PPC64)
7795 if (env
->flags
& POWERPC_FLAG_CFAR
) {
7796 cpu_fprintf(f
, " CFAR " TARGET_FMT_lx
"\n", env
->cfar
);
7800 switch (env
->mmu_model
) {
7801 case POWERPC_MMU_32B
:
7802 case POWERPC_MMU_601
:
7803 case POWERPC_MMU_SOFT_6xx
:
7804 case POWERPC_MMU_SOFT_74xx
:
7805 #if defined(TARGET_PPC64)
7806 case POWERPC_MMU_64B
:
7807 case POWERPC_MMU_2_03
:
7808 case POWERPC_MMU_2_06
:
7809 case POWERPC_MMU_2_06a
:
7810 case POWERPC_MMU_2_07
:
7811 case POWERPC_MMU_2_07a
:
7813 cpu_fprintf(f
, " SDR1 " TARGET_FMT_lx
" DAR " TARGET_FMT_lx
7814 " DSISR " TARGET_FMT_lx
"\n", env
->spr
[SPR_SDR1
],
7815 env
->spr
[SPR_DAR
], env
->spr
[SPR_DSISR
]);
7817 case POWERPC_MMU_BOOKE206
:
7818 cpu_fprintf(f
, " MAS0 " TARGET_FMT_lx
" MAS1 " TARGET_FMT_lx
7819 " MAS2 " TARGET_FMT_lx
" MAS3 " TARGET_FMT_lx
"\n",
7820 env
->spr
[SPR_BOOKE_MAS0
], env
->spr
[SPR_BOOKE_MAS1
],
7821 env
->spr
[SPR_BOOKE_MAS2
], env
->spr
[SPR_BOOKE_MAS3
]);
7823 cpu_fprintf(f
, " MAS4 " TARGET_FMT_lx
" MAS6 " TARGET_FMT_lx
7824 " MAS7 " TARGET_FMT_lx
" PID " TARGET_FMT_lx
"\n",
7825 env
->spr
[SPR_BOOKE_MAS4
], env
->spr
[SPR_BOOKE_MAS6
],
7826 env
->spr
[SPR_BOOKE_MAS7
], env
->spr
[SPR_BOOKE_PID
]);
7828 cpu_fprintf(f
, "MMUCFG " TARGET_FMT_lx
" TLB0CFG " TARGET_FMT_lx
7829 " TLB1CFG " TARGET_FMT_lx
"\n",
7830 env
->spr
[SPR_MMUCFG
], env
->spr
[SPR_BOOKE_TLB0CFG
],
7831 env
->spr
[SPR_BOOKE_TLB1CFG
]);
7842 void ppc_cpu_dump_statistics(CPUState
*cs
, FILE*f
,
7843 fprintf_function cpu_fprintf
, int flags
)
7845 #if defined(DO_PPC_STATISTICS)
7846 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
7847 opc_handler_t
**t1
, **t2
, **t3
, *handler
;
7850 t1
= cpu
->env
.opcodes
;
7851 for (op1
= 0; op1
< 64; op1
++) {
7853 if (is_indirect_opcode(handler
)) {
7854 t2
= ind_table(handler
);
7855 for (op2
= 0; op2
< 32; op2
++) {
7857 if (is_indirect_opcode(handler
)) {
7858 t3
= ind_table(handler
);
7859 for (op3
= 0; op3
< 32; op3
++) {
7861 if (handler
->count
== 0)
7863 cpu_fprintf(f
, "%02x %02x %02x (%02x %04d) %16s: "
7864 "%016" PRIx64
" %" PRId64
"\n",
7865 op1
, op2
, op3
, op1
, (op3
<< 5) | op2
,
7867 handler
->count
, handler
->count
);
7870 if (handler
->count
== 0)
7872 cpu_fprintf(f
, "%02x %02x (%02x %04d) %16s: "
7873 "%016" PRIx64
" %" PRId64
"\n",
7874 op1
, op2
, op1
, op2
, handler
->oname
,
7875 handler
->count
, handler
->count
);
7879 if (handler
->count
== 0)
7881 cpu_fprintf(f
, "%02x (%02x ) %16s: %016" PRIx64
7883 op1
, op1
, handler
->oname
,
7884 handler
->count
, handler
->count
);
7890 /*****************************************************************************/
7891 void gen_intermediate_code(CPUPPCState
*env
, struct TranslationBlock
*tb
)
7893 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
7894 CPUState
*cs
= CPU(cpu
);
7895 DisasContext ctx
, *ctxp
= &ctx
;
7896 opc_handler_t
**table
, *handler
;
7897 target_ulong pc_start
;
7904 ctx
.exception
= POWERPC_EXCP_NONE
;
7905 ctx
.spr_cb
= env
->spr_cb
;
7907 ctx
.mem_idx
= env
->dmmu_idx
;
7909 #if !defined(CONFIG_USER_ONLY)
7910 ctx
.hv
= msr_hv
|| !env
->has_hv_mode
;
7912 ctx
.insns_flags
= env
->insns_flags
;
7913 ctx
.insns_flags2
= env
->insns_flags2
;
7914 ctx
.access_type
= -1;
7915 ctx
.le_mode
= !!(env
->hflags
& (1 << MSR_LE
));
7916 ctx
.default_tcg_memop_mask
= ctx
.le_mode
? MO_LE
: MO_BE
;
7917 #if defined(TARGET_PPC64)
7918 ctx
.sf_mode
= msr_is_64bit(env
, env
->msr
);
7919 ctx
.has_cfar
= !!(env
->flags
& POWERPC_FLAG_CFAR
);
7921 if (env
->mmu_model
== POWERPC_MMU_32B
||
7922 env
->mmu_model
== POWERPC_MMU_601
||
7923 (env
->mmu_model
& POWERPC_MMU_64B
))
7924 ctx
.lazy_tlb_flush
= true;
7926 ctx
.fpu_enabled
= !!msr_fp
;
7927 if ((env
->flags
& POWERPC_FLAG_SPE
) && msr_spe
)
7928 ctx
.spe_enabled
= !!msr_spe
;
7930 ctx
.spe_enabled
= false;
7931 if ((env
->flags
& POWERPC_FLAG_VRE
) && msr_vr
)
7932 ctx
.altivec_enabled
= !!msr_vr
;
7934 ctx
.altivec_enabled
= false;
7935 if ((env
->flags
& POWERPC_FLAG_VSX
) && msr_vsx
) {
7936 ctx
.vsx_enabled
= !!msr_vsx
;
7938 ctx
.vsx_enabled
= false;
7940 #if defined(TARGET_PPC64)
7941 if ((env
->flags
& POWERPC_FLAG_TM
) && msr_tm
) {
7942 ctx
.tm_enabled
= !!msr_tm
;
7944 ctx
.tm_enabled
= false;
7947 if ((env
->flags
& POWERPC_FLAG_SE
) && msr_se
)
7948 ctx
.singlestep_enabled
= CPU_SINGLE_STEP
;
7950 ctx
.singlestep_enabled
= 0;
7951 if ((env
->flags
& POWERPC_FLAG_BE
) && msr_be
)
7952 ctx
.singlestep_enabled
|= CPU_BRANCH_STEP
;
7953 if (unlikely(cs
->singlestep_enabled
)) {
7954 ctx
.singlestep_enabled
|= GDBSTUB_SINGLE_STEP
;
7956 #if defined (DO_SINGLE_STEP) && 0
7957 /* Single step trace mode */
7961 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
7962 if (max_insns
== 0) {
7963 max_insns
= CF_COUNT_MASK
;
7965 if (max_insns
> TCG_MAX_INSNS
) {
7966 max_insns
= TCG_MAX_INSNS
;
7970 tcg_clear_temp_count();
7971 /* Set env in case of segfault during code fetch */
7972 while (ctx
.exception
== POWERPC_EXCP_NONE
&& !tcg_op_buf_full()) {
7973 tcg_gen_insn_start(ctx
.nip
);
7976 if (unlikely(cpu_breakpoint_test(cs
, ctx
.nip
, BP_ANY
))) {
7977 gen_debug_exception(ctxp
);
7978 /* The address covered by the breakpoint must be included in
7979 [tb->pc, tb->pc + tb->size) in order to for it to be
7980 properly cleared -- thus we increment the PC here so that
7981 the logic setting tb->size below does the right thing. */
7986 LOG_DISAS("----------------\n");
7987 LOG_DISAS("nip=" TARGET_FMT_lx
" super=%d ir=%d\n",
7988 ctx
.nip
, ctx
.mem_idx
, (int)msr_ir
);
7989 if (num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
))
7991 if (unlikely(need_byteswap(&ctx
))) {
7992 ctx
.opcode
= bswap32(cpu_ldl_code(env
, ctx
.nip
));
7994 ctx
.opcode
= cpu_ldl_code(env
, ctx
.nip
);
7996 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7997 ctx
.opcode
, opc1(ctx
.opcode
), opc2(ctx
.opcode
),
7998 opc3(ctx
.opcode
), opc4(ctx
.opcode
),
7999 ctx
.le_mode
? "little" : "big");
8001 table
= env
->opcodes
;
8002 handler
= table
[opc1(ctx
.opcode
)];
8003 if (is_indirect_opcode(handler
)) {
8004 table
= ind_table(handler
);
8005 handler
= table
[opc2(ctx
.opcode
)];
8006 if (is_indirect_opcode(handler
)) {
8007 table
= ind_table(handler
);
8008 handler
= table
[opc3(ctx
.opcode
)];
8009 if (is_indirect_opcode(handler
)) {
8010 table
= ind_table(handler
);
8011 handler
= table
[opc4(ctx
.opcode
)];
8015 /* Is opcode *REALLY* valid ? */
8016 if (unlikely(handler
->handler
== &gen_invalid
)) {
8017 qemu_log_mask(LOG_GUEST_ERROR
, "invalid/unsupported opcode: "
8018 "%02x - %02x - %02x - %02x (%08x) "
8019 TARGET_FMT_lx
" %d\n",
8020 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
8021 opc3(ctx
.opcode
), opc4(ctx
.opcode
),
8022 ctx
.opcode
, ctx
.nip
- 4, (int)msr_ir
);
8026 if (unlikely(handler
->type
& (PPC_SPE
| PPC_SPE_SINGLE
| PPC_SPE_DOUBLE
) && Rc(ctx
.opcode
))) {
8027 inval
= handler
->inval2
;
8029 inval
= handler
->inval1
;
8032 if (unlikely((ctx
.opcode
& inval
) != 0)) {
8033 qemu_log_mask(LOG_GUEST_ERROR
, "invalid bits: %08x for opcode: "
8034 "%02x - %02x - %02x - %02x (%08x) "
8035 TARGET_FMT_lx
"\n", ctx
.opcode
& inval
,
8036 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
8037 opc3(ctx
.opcode
), opc4(ctx
.opcode
),
8038 ctx
.opcode
, ctx
.nip
- 4);
8039 gen_inval_exception(ctxp
, POWERPC_EXCP_INVAL_INVAL
);
8043 (*(handler
->handler
))(&ctx
);
8044 #if defined(DO_PPC_STATISTICS)
8047 /* Check trace mode exceptions */
8048 if (unlikely(ctx
.singlestep_enabled
& CPU_SINGLE_STEP
&&
8049 (ctx
.nip
<= 0x100 || ctx
.nip
> 0xF00) &&
8050 ctx
.exception
!= POWERPC_SYSCALL
&&
8051 ctx
.exception
!= POWERPC_EXCP_TRAP
&&
8052 ctx
.exception
!= POWERPC_EXCP_BRANCH
)) {
8053 gen_exception(ctxp
, POWERPC_EXCP_TRACE
);
8054 } else if (unlikely(((ctx
.nip
& (TARGET_PAGE_SIZE
- 1)) == 0) ||
8055 (cs
->singlestep_enabled
) ||
8057 num_insns
>= max_insns
)) {
8058 /* if we reach a page boundary or are single stepping, stop
8063 if (tcg_check_temp_count()) {
8064 fprintf(stderr
, "Opcode %02x %02x %02x %02x (%08x) leaked "
8065 "temporaries\n", opc1(ctx
.opcode
), opc2(ctx
.opcode
),
8066 opc3(ctx
.opcode
), opc4(ctx
.opcode
), ctx
.opcode
);
8070 if (tb
->cflags
& CF_LAST_IO
)
8072 if (ctx
.exception
== POWERPC_EXCP_NONE
) {
8073 gen_goto_tb(&ctx
, 0, ctx
.nip
);
8074 } else if (ctx
.exception
!= POWERPC_EXCP_BRANCH
) {
8075 if (unlikely(cs
->singlestep_enabled
)) {
8076 gen_debug_exception(ctxp
);
8078 /* Generate the return instruction */
8081 gen_tb_end(tb
, num_insns
);
8083 tb
->size
= ctx
.nip
- pc_start
;
8084 tb
->icount
= num_insns
;
8086 #if defined(DEBUG_DISAS)
8087 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)
8088 && qemu_log_in_addr_range(pc_start
)) {
8090 flags
= env
->bfd_mach
;
8091 flags
|= ctx
.le_mode
<< 16;
8092 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
8093 log_target_disas(cs
, pc_start
, ctx
.nip
- pc_start
, flags
);
8099 void restore_state_to_opc(CPUPPCState
*env
, TranslationBlock
*tb
,