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ppc: Don't update NIP in lswi/lswx/stswi/stswx
[mirror_qemu.git] / target-ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg-op.h"
26 #include "qemu/host-utils.h"
27 #include "exec/cpu_ldst.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "trace-tcg.h"
33 #include "exec/log.h"
34
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define PPC_DEBUG_DISAS
42 //#define DO_PPC_STATISTICS
43
44 #ifdef PPC_DEBUG_DISAS
45 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
46 #else
47 # define LOG_DISAS(...) do { } while (0)
48 #endif
49 /*****************************************************************************/
50 /* Code translation helpers */
51
52 /* global register indexes */
53 static TCGv_env cpu_env;
54 static char cpu_reg_names[10*3 + 22*4 /* GPR */
55 + 10*4 + 22*5 /* SPE GPRh */
56 + 10*4 + 22*5 /* FPR */
57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
58 + 10*5 + 22*6 /* VSR */
59 + 8*5 /* CRF */];
60 static TCGv cpu_gpr[32];
61 static TCGv cpu_gprh[32];
62 static TCGv_i64 cpu_fpr[32];
63 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64 static TCGv_i64 cpu_vsr[32];
65 static TCGv_i32 cpu_crf[8];
66 static TCGv cpu_nip;
67 static TCGv cpu_msr;
68 static TCGv cpu_ctr;
69 static TCGv cpu_lr;
70 #if defined(TARGET_PPC64)
71 static TCGv cpu_cfar;
72 #endif
73 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
74 static TCGv cpu_reserve;
75 static TCGv cpu_fpscr;
76 static TCGv_i32 cpu_access_type;
77
78 #include "exec/gen-icount.h"
79
80 void ppc_translate_init(void)
81 {
82 int i;
83 char* p;
84 size_t cpu_reg_names_size;
85 static int done_init = 0;
86
87 if (done_init)
88 return;
89
90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
91 tcg_ctx.tcg_env = cpu_env;
92
93 p = cpu_reg_names;
94 cpu_reg_names_size = sizeof(cpu_reg_names);
95
96 for (i = 0; i < 8; i++) {
97 snprintf(p, cpu_reg_names_size, "crf%d", i);
98 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
99 offsetof(CPUPPCState, crf[i]), p);
100 p += 5;
101 cpu_reg_names_size -= 5;
102 }
103
104 for (i = 0; i < 32; i++) {
105 snprintf(p, cpu_reg_names_size, "r%d", i);
106 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
107 offsetof(CPUPPCState, gpr[i]), p);
108 p += (i < 10) ? 3 : 4;
109 cpu_reg_names_size -= (i < 10) ? 3 : 4;
110 snprintf(p, cpu_reg_names_size, "r%dH", i);
111 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
112 offsetof(CPUPPCState, gprh[i]), p);
113 p += (i < 10) ? 4 : 5;
114 cpu_reg_names_size -= (i < 10) ? 4 : 5;
115
116 snprintf(p, cpu_reg_names_size, "fp%d", i);
117 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
118 offsetof(CPUPPCState, fpr[i]), p);
119 p += (i < 10) ? 4 : 5;
120 cpu_reg_names_size -= (i < 10) ? 4 : 5;
121
122 snprintf(p, cpu_reg_names_size, "avr%dH", i);
123 #ifdef HOST_WORDS_BIGENDIAN
124 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
125 offsetof(CPUPPCState, avr[i].u64[0]), p);
126 #else
127 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
128 offsetof(CPUPPCState, avr[i].u64[1]), p);
129 #endif
130 p += (i < 10) ? 6 : 7;
131 cpu_reg_names_size -= (i < 10) ? 6 : 7;
132
133 snprintf(p, cpu_reg_names_size, "avr%dL", i);
134 #ifdef HOST_WORDS_BIGENDIAN
135 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
136 offsetof(CPUPPCState, avr[i].u64[1]), p);
137 #else
138 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
139 offsetof(CPUPPCState, avr[i].u64[0]), p);
140 #endif
141 p += (i < 10) ? 6 : 7;
142 cpu_reg_names_size -= (i < 10) ? 6 : 7;
143 snprintf(p, cpu_reg_names_size, "vsr%d", i);
144 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
145 offsetof(CPUPPCState, vsr[i]), p);
146 p += (i < 10) ? 5 : 6;
147 cpu_reg_names_size -= (i < 10) ? 5 : 6;
148 }
149
150 cpu_nip = tcg_global_mem_new(cpu_env,
151 offsetof(CPUPPCState, nip), "nip");
152
153 cpu_msr = tcg_global_mem_new(cpu_env,
154 offsetof(CPUPPCState, msr), "msr");
155
156 cpu_ctr = tcg_global_mem_new(cpu_env,
157 offsetof(CPUPPCState, ctr), "ctr");
158
159 cpu_lr = tcg_global_mem_new(cpu_env,
160 offsetof(CPUPPCState, lr), "lr");
161
162 #if defined(TARGET_PPC64)
163 cpu_cfar = tcg_global_mem_new(cpu_env,
164 offsetof(CPUPPCState, cfar), "cfar");
165 #endif
166
167 cpu_xer = tcg_global_mem_new(cpu_env,
168 offsetof(CPUPPCState, xer), "xer");
169 cpu_so = tcg_global_mem_new(cpu_env,
170 offsetof(CPUPPCState, so), "SO");
171 cpu_ov = tcg_global_mem_new(cpu_env,
172 offsetof(CPUPPCState, ov), "OV");
173 cpu_ca = tcg_global_mem_new(cpu_env,
174 offsetof(CPUPPCState, ca), "CA");
175
176 cpu_reserve = tcg_global_mem_new(cpu_env,
177 offsetof(CPUPPCState, reserve_addr),
178 "reserve_addr");
179
180 cpu_fpscr = tcg_global_mem_new(cpu_env,
181 offsetof(CPUPPCState, fpscr), "fpscr");
182
183 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
184 offsetof(CPUPPCState, access_type), "access_type");
185
186 done_init = 1;
187 }
188
189 /* internal defines */
190 struct DisasContext {
191 struct TranslationBlock *tb;
192 target_ulong nip;
193 uint32_t opcode;
194 uint32_t exception;
195 /* Routine used to access memory */
196 bool pr, hv, dr, le_mode;
197 bool lazy_tlb_flush;
198 int mem_idx;
199 int access_type;
200 /* Translation flags */
201 TCGMemOp default_tcg_memop_mask;
202 #if defined(TARGET_PPC64)
203 bool sf_mode;
204 bool has_cfar;
205 #endif
206 bool fpu_enabled;
207 bool altivec_enabled;
208 bool vsx_enabled;
209 bool spe_enabled;
210 bool tm_enabled;
211 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
212 int singlestep_enabled;
213 uint64_t insns_flags;
214 uint64_t insns_flags2;
215 };
216
217 /* Return true iff byteswap is needed in a scalar memop */
218 static inline bool need_byteswap(const DisasContext *ctx)
219 {
220 #if defined(TARGET_WORDS_BIGENDIAN)
221 return ctx->le_mode;
222 #else
223 return !ctx->le_mode;
224 #endif
225 }
226
227 /* True when active word size < size of target_long. */
228 #ifdef TARGET_PPC64
229 # define NARROW_MODE(C) (!(C)->sf_mode)
230 #else
231 # define NARROW_MODE(C) 0
232 #endif
233
234 struct opc_handler_t {
235 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
236 uint32_t inval1;
237 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
238 uint32_t inval2;
239 /* instruction type */
240 uint64_t type;
241 /* extended instruction type */
242 uint64_t type2;
243 /* handler */
244 void (*handler)(DisasContext *ctx);
245 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
246 const char *oname;
247 #endif
248 #if defined(DO_PPC_STATISTICS)
249 uint64_t count;
250 #endif
251 };
252
253 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
254 {
255 if (ctx->access_type != access_type) {
256 tcg_gen_movi_i32(cpu_access_type, access_type);
257 ctx->access_type = access_type;
258 }
259 }
260
261 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
262 {
263 if (NARROW_MODE(ctx)) {
264 nip = (uint32_t)nip;
265 }
266 tcg_gen_movi_tl(cpu_nip, nip);
267 }
268
269 void gen_update_current_nip(void *opaque)
270 {
271 DisasContext *ctx = opaque;
272
273 tcg_gen_movi_tl(cpu_nip, ctx->nip);
274 }
275
276 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
277 {
278 TCGv_i32 t0, t1;
279 if (ctx->exception == POWERPC_EXCP_NONE) {
280 gen_update_nip(ctx, ctx->nip);
281 }
282 t0 = tcg_const_i32(excp);
283 t1 = tcg_const_i32(error);
284 gen_helper_raise_exception_err(cpu_env, t0, t1);
285 tcg_temp_free_i32(t0);
286 tcg_temp_free_i32(t1);
287 ctx->exception = (excp);
288 }
289
290 static void gen_exception(DisasContext *ctx, uint32_t excp)
291 {
292 TCGv_i32 t0;
293 if (ctx->exception == POWERPC_EXCP_NONE) {
294 gen_update_nip(ctx, ctx->nip);
295 }
296 t0 = tcg_const_i32(excp);
297 gen_helper_raise_exception(cpu_env, t0);
298 tcg_temp_free_i32(t0);
299 ctx->exception = (excp);
300 }
301
302 static void gen_debug_exception(DisasContext *ctx)
303 {
304 TCGv_i32 t0;
305
306 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
307 (ctx->exception != POWERPC_EXCP_SYNC)) {
308 gen_update_nip(ctx, ctx->nip);
309 }
310 t0 = tcg_const_i32(EXCP_DEBUG);
311 gen_helper_raise_exception(cpu_env, t0);
312 tcg_temp_free_i32(t0);
313 }
314
315 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
316 {
317 /* Will be converted to program check if needed */
318 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
319 }
320
321 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
322 {
323 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
324 }
325
326 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
327 {
328 /* Will be converted to program check if needed */
329 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
330 }
331
332 /* Stop translation */
333 static inline void gen_stop_exception(DisasContext *ctx)
334 {
335 gen_update_nip(ctx, ctx->nip);
336 ctx->exception = POWERPC_EXCP_STOP;
337 }
338
339 #ifndef CONFIG_USER_ONLY
340 /* No need to update nip here, as execution flow will change */
341 static inline void gen_sync_exception(DisasContext *ctx)
342 {
343 ctx->exception = POWERPC_EXCP_SYNC;
344 }
345 #endif
346
347 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
348 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
349
350 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
351 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
352
353 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
354 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
355
356 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
357 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
358
359 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
360 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
361
362 typedef struct opcode_t {
363 unsigned char opc1, opc2, opc3, opc4;
364 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
365 unsigned char pad[4];
366 #endif
367 opc_handler_t handler;
368 const char *oname;
369 } opcode_t;
370
371 /* Helpers for priv. check */
372 #define GEN_PRIV \
373 do { \
374 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
375 } while (0)
376
377 #if defined(CONFIG_USER_ONLY)
378 #define CHK_HV GEN_PRIV
379 #define CHK_SV GEN_PRIV
380 #define CHK_HVRM GEN_PRIV
381 #else
382 #define CHK_HV \
383 do { \
384 if (unlikely(ctx->pr || !ctx->hv)) { \
385 GEN_PRIV; \
386 } \
387 } while (0)
388 #define CHK_SV \
389 do { \
390 if (unlikely(ctx->pr)) { \
391 GEN_PRIV; \
392 } \
393 } while (0)
394 #define CHK_HVRM \
395 do { \
396 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
397 GEN_PRIV; \
398 } \
399 } while (0)
400 #endif
401
402 #define CHK_NONE
403
404
405 /*****************************************************************************/
406 /*** Instruction decoding ***/
407 #define EXTRACT_HELPER(name, shift, nb) \
408 static inline uint32_t name(uint32_t opcode) \
409 { \
410 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
411 }
412
413 #define EXTRACT_SHELPER(name, shift, nb) \
414 static inline int32_t name(uint32_t opcode) \
415 { \
416 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
417 }
418
419 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
420 static inline uint32_t name(uint32_t opcode) \
421 { \
422 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
423 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
424 }
425
426 #define EXTRACT_HELPER_DXFORM(name, \
427 d0_bits, shift_op_d0, shift_d0, \
428 d1_bits, shift_op_d1, shift_d1, \
429 d2_bits, shift_op_d2, shift_d2) \
430 static inline int16_t name(uint32_t opcode) \
431 { \
432 return \
433 (((opcode >> (shift_op_d0)) & ((1 << (d0_bits)) - 1)) << (shift_d0)) | \
434 (((opcode >> (shift_op_d1)) & ((1 << (d1_bits)) - 1)) << (shift_d1)) | \
435 (((opcode >> (shift_op_d2)) & ((1 << (d2_bits)) - 1)) << (shift_d2)); \
436 }
437
438
439 /* Opcode part 1 */
440 EXTRACT_HELPER(opc1, 26, 6);
441 /* Opcode part 2 */
442 EXTRACT_HELPER(opc2, 1, 5);
443 /* Opcode part 3 */
444 EXTRACT_HELPER(opc3, 6, 5);
445 /* Opcode part 4 */
446 EXTRACT_HELPER(opc4, 16, 5);
447 /* Update Cr0 flags */
448 EXTRACT_HELPER(Rc, 0, 1);
449 /* Update Cr6 flags (Altivec) */
450 EXTRACT_HELPER(Rc21, 10, 1);
451 /* Destination */
452 EXTRACT_HELPER(rD, 21, 5);
453 /* Source */
454 EXTRACT_HELPER(rS, 21, 5);
455 /* First operand */
456 EXTRACT_HELPER(rA, 16, 5);
457 /* Second operand */
458 EXTRACT_HELPER(rB, 11, 5);
459 /* Third operand */
460 EXTRACT_HELPER(rC, 6, 5);
461 /*** Get CRn ***/
462 EXTRACT_HELPER(crfD, 23, 3);
463 EXTRACT_HELPER(crfS, 18, 3);
464 EXTRACT_HELPER(crbD, 21, 5);
465 EXTRACT_HELPER(crbA, 16, 5);
466 EXTRACT_HELPER(crbB, 11, 5);
467 /* SPR / TBL */
468 EXTRACT_HELPER(_SPR, 11, 10);
469 static inline uint32_t SPR(uint32_t opcode)
470 {
471 uint32_t sprn = _SPR(opcode);
472
473 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
474 }
475 /*** Get constants ***/
476 /* 16 bits signed immediate value */
477 EXTRACT_SHELPER(SIMM, 0, 16);
478 /* 16 bits unsigned immediate value */
479 EXTRACT_HELPER(UIMM, 0, 16);
480 /* 5 bits signed immediate value */
481 EXTRACT_HELPER(SIMM5, 16, 5);
482 /* 5 bits signed immediate value */
483 EXTRACT_HELPER(UIMM5, 16, 5);
484 /* Bit count */
485 EXTRACT_HELPER(NB, 11, 5);
486 /* Shift count */
487 EXTRACT_HELPER(SH, 11, 5);
488 /* Vector shift count */
489 EXTRACT_HELPER(VSH, 6, 4);
490 /* Mask start */
491 EXTRACT_HELPER(MB, 6, 5);
492 /* Mask end */
493 EXTRACT_HELPER(ME, 1, 5);
494 /* Trap operand */
495 EXTRACT_HELPER(TO, 21, 5);
496
497 EXTRACT_HELPER(CRM, 12, 8);
498
499 #ifndef CONFIG_USER_ONLY
500 EXTRACT_HELPER(SR, 16, 4);
501 #endif
502
503 /* mtfsf/mtfsfi */
504 EXTRACT_HELPER(FPBF, 23, 3);
505 EXTRACT_HELPER(FPIMM, 12, 4);
506 EXTRACT_HELPER(FPL, 25, 1);
507 EXTRACT_HELPER(FPFLM, 17, 8);
508 EXTRACT_HELPER(FPW, 16, 1);
509
510 /* addpcis */
511 EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
512
513 /*** Jump target decoding ***/
514 /* Immediate address */
515 static inline target_ulong LI(uint32_t opcode)
516 {
517 return (opcode >> 0) & 0x03FFFFFC;
518 }
519
520 static inline uint32_t BD(uint32_t opcode)
521 {
522 return (opcode >> 0) & 0xFFFC;
523 }
524
525 EXTRACT_HELPER(BO, 21, 5);
526 EXTRACT_HELPER(BI, 16, 5);
527 /* Absolute/relative address */
528 EXTRACT_HELPER(AA, 1, 1);
529 /* Link */
530 EXTRACT_HELPER(LK, 0, 1);
531
532 /* DFP Z22-form */
533 EXTRACT_HELPER(DCM, 10, 6)
534
535 /* DFP Z23-form */
536 EXTRACT_HELPER(RMC, 9, 2)
537
538 /* Create a mask between <start> and <end> bits */
539 static inline target_ulong MASK(uint32_t start, uint32_t end)
540 {
541 target_ulong ret;
542
543 #if defined(TARGET_PPC64)
544 if (likely(start == 0)) {
545 ret = UINT64_MAX << (63 - end);
546 } else if (likely(end == 63)) {
547 ret = UINT64_MAX >> start;
548 }
549 #else
550 if (likely(start == 0)) {
551 ret = UINT32_MAX << (31 - end);
552 } else if (likely(end == 31)) {
553 ret = UINT32_MAX >> start;
554 }
555 #endif
556 else {
557 ret = (((target_ulong)(-1ULL)) >> (start)) ^
558 (((target_ulong)(-1ULL) >> (end)) >> 1);
559 if (unlikely(start > end))
560 return ~ret;
561 }
562
563 return ret;
564 }
565
566 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
567 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
568 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
569 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
570 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
571 EXTRACT_HELPER(DM, 8, 2);
572 EXTRACT_HELPER(UIM, 16, 2);
573 EXTRACT_HELPER(SHW, 8, 2);
574 EXTRACT_HELPER(SP, 19, 2);
575 /*****************************************************************************/
576 /* PowerPC instructions table */
577
578 #if defined(DO_PPC_STATISTICS)
579 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
580 { \
581 .opc1 = op1, \
582 .opc2 = op2, \
583 .opc3 = op3, \
584 .opc4 = 0xff, \
585 .handler = { \
586 .inval1 = invl, \
587 .type = _typ, \
588 .type2 = _typ2, \
589 .handler = &gen_##name, \
590 .oname = stringify(name), \
591 }, \
592 .oname = stringify(name), \
593 }
594 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
595 { \
596 .opc1 = op1, \
597 .opc2 = op2, \
598 .opc3 = op3, \
599 .opc4 = 0xff, \
600 .handler = { \
601 .inval1 = invl1, \
602 .inval2 = invl2, \
603 .type = _typ, \
604 .type2 = _typ2, \
605 .handler = &gen_##name, \
606 .oname = stringify(name), \
607 }, \
608 .oname = stringify(name), \
609 }
610 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
611 { \
612 .opc1 = op1, \
613 .opc2 = op2, \
614 .opc3 = op3, \
615 .opc4 = 0xff, \
616 .handler = { \
617 .inval1 = invl, \
618 .type = _typ, \
619 .type2 = _typ2, \
620 .handler = &gen_##name, \
621 .oname = onam, \
622 }, \
623 .oname = onam, \
624 }
625 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
626 { \
627 .opc1 = op1, \
628 .opc2 = op2, \
629 .opc3 = op3, \
630 .opc4 = op4, \
631 .handler = { \
632 .inval1 = invl, \
633 .type = _typ, \
634 .type2 = _typ2, \
635 .handler = &gen_##name, \
636 .oname = stringify(name), \
637 }, \
638 .oname = stringify(name), \
639 }
640 #else
641 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
642 { \
643 .opc1 = op1, \
644 .opc2 = op2, \
645 .opc3 = op3, \
646 .opc4 = 0xff, \
647 .handler = { \
648 .inval1 = invl, \
649 .type = _typ, \
650 .type2 = _typ2, \
651 .handler = &gen_##name, \
652 }, \
653 .oname = stringify(name), \
654 }
655 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
656 { \
657 .opc1 = op1, \
658 .opc2 = op2, \
659 .opc3 = op3, \
660 .opc4 = 0xff, \
661 .handler = { \
662 .inval1 = invl1, \
663 .inval2 = invl2, \
664 .type = _typ, \
665 .type2 = _typ2, \
666 .handler = &gen_##name, \
667 }, \
668 .oname = stringify(name), \
669 }
670 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
671 { \
672 .opc1 = op1, \
673 .opc2 = op2, \
674 .opc3 = op3, \
675 .opc4 = 0xff, \
676 .handler = { \
677 .inval1 = invl, \
678 .type = _typ, \
679 .type2 = _typ2, \
680 .handler = &gen_##name, \
681 }, \
682 .oname = onam, \
683 }
684 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
685 { \
686 .opc1 = op1, \
687 .opc2 = op2, \
688 .opc3 = op3, \
689 .opc4 = op4, \
690 .handler = { \
691 .inval1 = invl, \
692 .type = _typ, \
693 .type2 = _typ2, \
694 .handler = &gen_##name, \
695 }, \
696 .oname = stringify(name), \
697 }
698 #endif
699
700 /* SPR load/store helpers */
701 static inline void gen_load_spr(TCGv t, int reg)
702 {
703 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
704 }
705
706 static inline void gen_store_spr(int reg, TCGv t)
707 {
708 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
709 }
710
711 /* Invalid instruction */
712 static void gen_invalid(DisasContext *ctx)
713 {
714 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
715 }
716
717 static opc_handler_t invalid_handler = {
718 .inval1 = 0xFFFFFFFF,
719 .inval2 = 0xFFFFFFFF,
720 .type = PPC_NONE,
721 .type2 = PPC_NONE,
722 .handler = gen_invalid,
723 };
724
725 /*** Integer comparison ***/
726
727 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
728 {
729 TCGv t0 = tcg_temp_new();
730 TCGv_i32 t1 = tcg_temp_new_i32();
731
732 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
733
734 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
735 tcg_gen_trunc_tl_i32(t1, t0);
736 tcg_gen_shli_i32(t1, t1, CRF_LT);
737 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
738
739 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
740 tcg_gen_trunc_tl_i32(t1, t0);
741 tcg_gen_shli_i32(t1, t1, CRF_GT);
742 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
743
744 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
745 tcg_gen_trunc_tl_i32(t1, t0);
746 tcg_gen_shli_i32(t1, t1, CRF_EQ);
747 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
748
749 tcg_temp_free(t0);
750 tcg_temp_free_i32(t1);
751 }
752
753 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
754 {
755 TCGv t0 = tcg_const_tl(arg1);
756 gen_op_cmp(arg0, t0, s, crf);
757 tcg_temp_free(t0);
758 }
759
760 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
761 {
762 TCGv t0, t1;
763 t0 = tcg_temp_new();
764 t1 = tcg_temp_new();
765 if (s) {
766 tcg_gen_ext32s_tl(t0, arg0);
767 tcg_gen_ext32s_tl(t1, arg1);
768 } else {
769 tcg_gen_ext32u_tl(t0, arg0);
770 tcg_gen_ext32u_tl(t1, arg1);
771 }
772 gen_op_cmp(t0, t1, s, crf);
773 tcg_temp_free(t1);
774 tcg_temp_free(t0);
775 }
776
777 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
778 {
779 TCGv t0 = tcg_const_tl(arg1);
780 gen_op_cmp32(arg0, t0, s, crf);
781 tcg_temp_free(t0);
782 }
783
784 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
785 {
786 if (NARROW_MODE(ctx)) {
787 gen_op_cmpi32(reg, 0, 1, 0);
788 } else {
789 gen_op_cmpi(reg, 0, 1, 0);
790 }
791 }
792
793 /* cmp */
794 static void gen_cmp(DisasContext *ctx)
795 {
796 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
797 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
798 1, crfD(ctx->opcode));
799 } else {
800 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
801 1, crfD(ctx->opcode));
802 }
803 }
804
805 /* cmpi */
806 static void gen_cmpi(DisasContext *ctx)
807 {
808 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
809 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
810 1, crfD(ctx->opcode));
811 } else {
812 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
813 1, crfD(ctx->opcode));
814 }
815 }
816
817 /* cmpl */
818 static void gen_cmpl(DisasContext *ctx)
819 {
820 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
821 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
822 0, crfD(ctx->opcode));
823 } else {
824 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
825 0, crfD(ctx->opcode));
826 }
827 }
828
829 /* cmpli */
830 static void gen_cmpli(DisasContext *ctx)
831 {
832 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
833 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
834 0, crfD(ctx->opcode));
835 } else {
836 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
837 0, crfD(ctx->opcode));
838 }
839 }
840
841 /* cmprb - range comparison: isupper, isaplha, islower*/
842 static void gen_cmprb(DisasContext *ctx)
843 {
844 TCGv_i32 src1 = tcg_temp_new_i32();
845 TCGv_i32 src2 = tcg_temp_new_i32();
846 TCGv_i32 src2lo = tcg_temp_new_i32();
847 TCGv_i32 src2hi = tcg_temp_new_i32();
848 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
849
850 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
851 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
852
853 tcg_gen_andi_i32(src1, src1, 0xFF);
854 tcg_gen_ext8u_i32(src2lo, src2);
855 tcg_gen_shri_i32(src2, src2, 8);
856 tcg_gen_ext8u_i32(src2hi, src2);
857
858 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
859 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
860 tcg_gen_and_i32(crf, src2lo, src2hi);
861
862 if (ctx->opcode & 0x00200000) {
863 tcg_gen_shri_i32(src2, src2, 8);
864 tcg_gen_ext8u_i32(src2lo, src2);
865 tcg_gen_shri_i32(src2, src2, 8);
866 tcg_gen_ext8u_i32(src2hi, src2);
867 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
868 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
869 tcg_gen_and_i32(src2lo, src2lo, src2hi);
870 tcg_gen_or_i32(crf, crf, src2lo);
871 }
872 tcg_gen_shli_i32(crf, crf, CRF_GT);
873 tcg_temp_free_i32(src1);
874 tcg_temp_free_i32(src2);
875 tcg_temp_free_i32(src2lo);
876 tcg_temp_free_i32(src2hi);
877 }
878
879 #if defined(TARGET_PPC64)
880 /* cmpeqb */
881 static void gen_cmpeqb(DisasContext *ctx)
882 {
883 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
884 cpu_gpr[rB(ctx->opcode)]);
885 }
886 #endif
887
888 /* isel (PowerPC 2.03 specification) */
889 static void gen_isel(DisasContext *ctx)
890 {
891 uint32_t bi = rC(ctx->opcode);
892 uint32_t mask = 0x08 >> (bi & 0x03);
893 TCGv t0 = tcg_temp_new();
894 TCGv zr;
895
896 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
897 tcg_gen_andi_tl(t0, t0, mask);
898
899 zr = tcg_const_tl(0);
900 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
901 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
902 cpu_gpr[rB(ctx->opcode)]);
903 tcg_temp_free(zr);
904 tcg_temp_free(t0);
905 }
906
907 /* cmpb: PowerPC 2.05 specification */
908 static void gen_cmpb(DisasContext *ctx)
909 {
910 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
911 cpu_gpr[rB(ctx->opcode)]);
912 }
913
914 /*** Integer arithmetic ***/
915
916 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
917 TCGv arg1, TCGv arg2, int sub)
918 {
919 TCGv t0 = tcg_temp_new();
920
921 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
922 tcg_gen_xor_tl(t0, arg1, arg2);
923 if (sub) {
924 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
925 } else {
926 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
927 }
928 tcg_temp_free(t0);
929 if (NARROW_MODE(ctx)) {
930 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
931 }
932 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
933 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
934 }
935
936 /* Common add function */
937 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
938 TCGv arg2, bool add_ca, bool compute_ca,
939 bool compute_ov, bool compute_rc0)
940 {
941 TCGv t0 = ret;
942
943 if (compute_ca || compute_ov) {
944 t0 = tcg_temp_new();
945 }
946
947 if (compute_ca) {
948 if (NARROW_MODE(ctx)) {
949 /* Caution: a non-obvious corner case of the spec is that we
950 must produce the *entire* 64-bit addition, but produce the
951 carry into bit 32. */
952 TCGv t1 = tcg_temp_new();
953 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
954 tcg_gen_add_tl(t0, arg1, arg2);
955 if (add_ca) {
956 tcg_gen_add_tl(t0, t0, cpu_ca);
957 }
958 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
959 tcg_temp_free(t1);
960 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
961 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
962 } else {
963 TCGv zero = tcg_const_tl(0);
964 if (add_ca) {
965 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
966 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
967 } else {
968 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
969 }
970 tcg_temp_free(zero);
971 }
972 } else {
973 tcg_gen_add_tl(t0, arg1, arg2);
974 if (add_ca) {
975 tcg_gen_add_tl(t0, t0, cpu_ca);
976 }
977 }
978
979 if (compute_ov) {
980 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
981 }
982 if (unlikely(compute_rc0)) {
983 gen_set_Rc0(ctx, t0);
984 }
985
986 if (!TCGV_EQUAL(t0, ret)) {
987 tcg_gen_mov_tl(ret, t0);
988 tcg_temp_free(t0);
989 }
990 }
991 /* Add functions with two operands */
992 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
993 static void glue(gen_, name)(DisasContext *ctx) \
994 { \
995 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
996 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
997 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
998 }
999 /* Add functions with one operand and one immediate */
1000 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
1001 add_ca, compute_ca, compute_ov) \
1002 static void glue(gen_, name)(DisasContext *ctx) \
1003 { \
1004 TCGv t0 = tcg_const_tl(const_val); \
1005 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1006 cpu_gpr[rA(ctx->opcode)], t0, \
1007 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1008 tcg_temp_free(t0); \
1009 }
1010
1011 /* add add. addo addo. */
1012 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
1013 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
1014 /* addc addc. addco addco. */
1015 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
1016 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
1017 /* adde adde. addeo addeo. */
1018 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1019 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1020 /* addme addme. addmeo addmeo. */
1021 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1022 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1023 /* addze addze. addzeo addzeo.*/
1024 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1025 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1026 /* addi */
1027 static void gen_addi(DisasContext *ctx)
1028 {
1029 target_long simm = SIMM(ctx->opcode);
1030
1031 if (rA(ctx->opcode) == 0) {
1032 /* li case */
1033 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1034 } else {
1035 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1036 cpu_gpr[rA(ctx->opcode)], simm);
1037 }
1038 }
1039 /* addic addic.*/
1040 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
1041 {
1042 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1043 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1044 c, 0, 1, 0, compute_rc0);
1045 tcg_temp_free(c);
1046 }
1047
1048 static void gen_addic(DisasContext *ctx)
1049 {
1050 gen_op_addic(ctx, 0);
1051 }
1052
1053 static void gen_addic_(DisasContext *ctx)
1054 {
1055 gen_op_addic(ctx, 1);
1056 }
1057
1058 /* addis */
1059 static void gen_addis(DisasContext *ctx)
1060 {
1061 target_long simm = SIMM(ctx->opcode);
1062
1063 if (rA(ctx->opcode) == 0) {
1064 /* lis case */
1065 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1066 } else {
1067 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1068 cpu_gpr[rA(ctx->opcode)], simm << 16);
1069 }
1070 }
1071
1072 /* addpcis */
1073 static void gen_addpcis(DisasContext *ctx)
1074 {
1075 target_long d = DX(ctx->opcode);
1076
1077 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16));
1078 }
1079
1080 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
1081 TCGv arg2, int sign, int compute_ov)
1082 {
1083 TCGLabel *l1 = gen_new_label();
1084 TCGLabel *l2 = gen_new_label();
1085 TCGv_i32 t0 = tcg_temp_local_new_i32();
1086 TCGv_i32 t1 = tcg_temp_local_new_i32();
1087
1088 tcg_gen_trunc_tl_i32(t0, arg1);
1089 tcg_gen_trunc_tl_i32(t1, arg2);
1090 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
1091 if (sign) {
1092 TCGLabel *l3 = gen_new_label();
1093 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1094 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
1095 gen_set_label(l3);
1096 tcg_gen_div_i32(t0, t0, t1);
1097 } else {
1098 tcg_gen_divu_i32(t0, t0, t1);
1099 }
1100 if (compute_ov) {
1101 tcg_gen_movi_tl(cpu_ov, 0);
1102 }
1103 tcg_gen_br(l2);
1104 gen_set_label(l1);
1105 if (sign) {
1106 tcg_gen_sari_i32(t0, t0, 31);
1107 } else {
1108 tcg_gen_movi_i32(t0, 0);
1109 }
1110 if (compute_ov) {
1111 tcg_gen_movi_tl(cpu_ov, 1);
1112 tcg_gen_movi_tl(cpu_so, 1);
1113 }
1114 gen_set_label(l2);
1115 tcg_gen_extu_i32_tl(ret, t0);
1116 tcg_temp_free_i32(t0);
1117 tcg_temp_free_i32(t1);
1118 if (unlikely(Rc(ctx->opcode) != 0))
1119 gen_set_Rc0(ctx, ret);
1120 }
1121 /* Div functions */
1122 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1123 static void glue(gen_, name)(DisasContext *ctx) \
1124 { \
1125 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1126 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1127 sign, compute_ov); \
1128 }
1129 /* divwu divwu. divwuo divwuo. */
1130 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1131 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1132 /* divw divw. divwo divwo. */
1133 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1134 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1135
1136 /* div[wd]eu[o][.] */
1137 #define GEN_DIVE(name, hlpr, compute_ov) \
1138 static void gen_##name(DisasContext *ctx) \
1139 { \
1140 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1141 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1142 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1143 tcg_temp_free_i32(t0); \
1144 if (unlikely(Rc(ctx->opcode) != 0)) { \
1145 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1146 } \
1147 }
1148
1149 GEN_DIVE(divweu, divweu, 0);
1150 GEN_DIVE(divweuo, divweu, 1);
1151 GEN_DIVE(divwe, divwe, 0);
1152 GEN_DIVE(divweo, divwe, 1);
1153
1154 #if defined(TARGET_PPC64)
1155 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1156 TCGv arg2, int sign, int compute_ov)
1157 {
1158 TCGLabel *l1 = gen_new_label();
1159 TCGLabel *l2 = gen_new_label();
1160
1161 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1162 if (sign) {
1163 TCGLabel *l3 = gen_new_label();
1164 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1165 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1166 gen_set_label(l3);
1167 tcg_gen_div_i64(ret, arg1, arg2);
1168 } else {
1169 tcg_gen_divu_i64(ret, arg1, arg2);
1170 }
1171 if (compute_ov) {
1172 tcg_gen_movi_tl(cpu_ov, 0);
1173 }
1174 tcg_gen_br(l2);
1175 gen_set_label(l1);
1176 if (sign) {
1177 tcg_gen_sari_i64(ret, arg1, 63);
1178 } else {
1179 tcg_gen_movi_i64(ret, 0);
1180 }
1181 if (compute_ov) {
1182 tcg_gen_movi_tl(cpu_ov, 1);
1183 tcg_gen_movi_tl(cpu_so, 1);
1184 }
1185 gen_set_label(l2);
1186 if (unlikely(Rc(ctx->opcode) != 0))
1187 gen_set_Rc0(ctx, ret);
1188 }
1189 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1190 static void glue(gen_, name)(DisasContext *ctx) \
1191 { \
1192 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1193 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1194 sign, compute_ov); \
1195 }
1196 /* divwu divwu. divwuo divwuo. */
1197 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1198 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1199 /* divw divw. divwo divwo. */
1200 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1201 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1202
1203 GEN_DIVE(divdeu, divdeu, 0);
1204 GEN_DIVE(divdeuo, divdeu, 1);
1205 GEN_DIVE(divde, divde, 0);
1206 GEN_DIVE(divdeo, divde, 1);
1207 #endif
1208
1209 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1210 TCGv arg2, int sign)
1211 {
1212 TCGv_i32 t0 = tcg_temp_new_i32();
1213 TCGv_i32 t1 = tcg_temp_new_i32();
1214
1215 tcg_gen_trunc_tl_i32(t0, arg1);
1216 tcg_gen_trunc_tl_i32(t1, arg2);
1217 if (sign) {
1218 TCGv_i32 t2 = tcg_temp_new_i32();
1219 TCGv_i32 t3 = tcg_temp_new_i32();
1220 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1221 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1222 tcg_gen_and_i32(t2, t2, t3);
1223 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1224 tcg_gen_or_i32(t2, t2, t3);
1225 tcg_gen_movi_i32(t3, 0);
1226 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1227 tcg_gen_rem_i32(t3, t0, t1);
1228 tcg_gen_ext_i32_tl(ret, t3);
1229 tcg_temp_free_i32(t2);
1230 tcg_temp_free_i32(t3);
1231 } else {
1232 TCGv_i32 t2 = tcg_const_i32(1);
1233 TCGv_i32 t3 = tcg_const_i32(0);
1234 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1235 tcg_gen_remu_i32(t3, t0, t1);
1236 tcg_gen_extu_i32_tl(ret, t3);
1237 tcg_temp_free_i32(t2);
1238 tcg_temp_free_i32(t3);
1239 }
1240 tcg_temp_free_i32(t0);
1241 tcg_temp_free_i32(t1);
1242 }
1243
1244 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1245 static void glue(gen_, name)(DisasContext *ctx) \
1246 { \
1247 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1248 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1249 sign); \
1250 }
1251
1252 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1253 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1254
1255 #if defined(TARGET_PPC64)
1256 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1257 TCGv arg2, int sign)
1258 {
1259 TCGv_i64 t0 = tcg_temp_new_i64();
1260 TCGv_i64 t1 = tcg_temp_new_i64();
1261
1262 tcg_gen_mov_i64(t0, arg1);
1263 tcg_gen_mov_i64(t1, arg2);
1264 if (sign) {
1265 TCGv_i64 t2 = tcg_temp_new_i64();
1266 TCGv_i64 t3 = tcg_temp_new_i64();
1267 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1268 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1269 tcg_gen_and_i64(t2, t2, t3);
1270 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1271 tcg_gen_or_i64(t2, t2, t3);
1272 tcg_gen_movi_i64(t3, 0);
1273 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1274 tcg_gen_rem_i64(ret, t0, t1);
1275 tcg_temp_free_i64(t2);
1276 tcg_temp_free_i64(t3);
1277 } else {
1278 TCGv_i64 t2 = tcg_const_i64(1);
1279 TCGv_i64 t3 = tcg_const_i64(0);
1280 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1281 tcg_gen_remu_i64(ret, t0, t1);
1282 tcg_temp_free_i64(t2);
1283 tcg_temp_free_i64(t3);
1284 }
1285 tcg_temp_free_i64(t0);
1286 tcg_temp_free_i64(t1);
1287 }
1288
1289 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1290 static void glue(gen_, name)(DisasContext *ctx) \
1291 { \
1292 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1293 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1294 sign); \
1295 }
1296
1297 GEN_INT_ARITH_MODD(modud, 0x08, 0);
1298 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1299 #endif
1300
1301 /* mulhw mulhw. */
1302 static void gen_mulhw(DisasContext *ctx)
1303 {
1304 TCGv_i32 t0 = tcg_temp_new_i32();
1305 TCGv_i32 t1 = tcg_temp_new_i32();
1306
1307 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1308 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1309 tcg_gen_muls2_i32(t0, t1, t0, t1);
1310 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1311 tcg_temp_free_i32(t0);
1312 tcg_temp_free_i32(t1);
1313 if (unlikely(Rc(ctx->opcode) != 0))
1314 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1315 }
1316
1317 /* mulhwu mulhwu. */
1318 static void gen_mulhwu(DisasContext *ctx)
1319 {
1320 TCGv_i32 t0 = tcg_temp_new_i32();
1321 TCGv_i32 t1 = tcg_temp_new_i32();
1322
1323 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1324 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1325 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1326 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1327 tcg_temp_free_i32(t0);
1328 tcg_temp_free_i32(t1);
1329 if (unlikely(Rc(ctx->opcode) != 0))
1330 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1331 }
1332
1333 /* mullw mullw. */
1334 static void gen_mullw(DisasContext *ctx)
1335 {
1336 #if defined(TARGET_PPC64)
1337 TCGv_i64 t0, t1;
1338 t0 = tcg_temp_new_i64();
1339 t1 = tcg_temp_new_i64();
1340 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1341 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1342 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1343 tcg_temp_free(t0);
1344 tcg_temp_free(t1);
1345 #else
1346 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1347 cpu_gpr[rB(ctx->opcode)]);
1348 #endif
1349 if (unlikely(Rc(ctx->opcode) != 0))
1350 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1351 }
1352
1353 /* mullwo mullwo. */
1354 static void gen_mullwo(DisasContext *ctx)
1355 {
1356 TCGv_i32 t0 = tcg_temp_new_i32();
1357 TCGv_i32 t1 = tcg_temp_new_i32();
1358
1359 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1360 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1361 tcg_gen_muls2_i32(t0, t1, t0, t1);
1362 #if defined(TARGET_PPC64)
1363 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1364 #else
1365 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1366 #endif
1367
1368 tcg_gen_sari_i32(t0, t0, 31);
1369 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1370 tcg_gen_extu_i32_tl(cpu_ov, t0);
1371 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1372
1373 tcg_temp_free_i32(t0);
1374 tcg_temp_free_i32(t1);
1375 if (unlikely(Rc(ctx->opcode) != 0))
1376 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1377 }
1378
1379 /* mulli */
1380 static void gen_mulli(DisasContext *ctx)
1381 {
1382 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1383 SIMM(ctx->opcode));
1384 }
1385
1386 #if defined(TARGET_PPC64)
1387 /* mulhd mulhd. */
1388 static void gen_mulhd(DisasContext *ctx)
1389 {
1390 TCGv lo = tcg_temp_new();
1391 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1392 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1393 tcg_temp_free(lo);
1394 if (unlikely(Rc(ctx->opcode) != 0)) {
1395 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1396 }
1397 }
1398
1399 /* mulhdu mulhdu. */
1400 static void gen_mulhdu(DisasContext *ctx)
1401 {
1402 TCGv lo = tcg_temp_new();
1403 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1404 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1405 tcg_temp_free(lo);
1406 if (unlikely(Rc(ctx->opcode) != 0)) {
1407 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1408 }
1409 }
1410
1411 /* mulld mulld. */
1412 static void gen_mulld(DisasContext *ctx)
1413 {
1414 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1415 cpu_gpr[rB(ctx->opcode)]);
1416 if (unlikely(Rc(ctx->opcode) != 0))
1417 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1418 }
1419
1420 /* mulldo mulldo. */
1421 static void gen_mulldo(DisasContext *ctx)
1422 {
1423 TCGv_i64 t0 = tcg_temp_new_i64();
1424 TCGv_i64 t1 = tcg_temp_new_i64();
1425
1426 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1427 cpu_gpr[rB(ctx->opcode)]);
1428 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1429
1430 tcg_gen_sari_i64(t0, t0, 63);
1431 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1432 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1433
1434 tcg_temp_free_i64(t0);
1435 tcg_temp_free_i64(t1);
1436
1437 if (unlikely(Rc(ctx->opcode) != 0)) {
1438 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1439 }
1440 }
1441 #endif
1442
1443 /* Common subf function */
1444 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1445 TCGv arg2, bool add_ca, bool compute_ca,
1446 bool compute_ov, bool compute_rc0)
1447 {
1448 TCGv t0 = ret;
1449
1450 if (compute_ca || compute_ov) {
1451 t0 = tcg_temp_new();
1452 }
1453
1454 if (compute_ca) {
1455 /* dest = ~arg1 + arg2 [+ ca]. */
1456 if (NARROW_MODE(ctx)) {
1457 /* Caution: a non-obvious corner case of the spec is that we
1458 must produce the *entire* 64-bit addition, but produce the
1459 carry into bit 32. */
1460 TCGv inv1 = tcg_temp_new();
1461 TCGv t1 = tcg_temp_new();
1462 tcg_gen_not_tl(inv1, arg1);
1463 if (add_ca) {
1464 tcg_gen_add_tl(t0, arg2, cpu_ca);
1465 } else {
1466 tcg_gen_addi_tl(t0, arg2, 1);
1467 }
1468 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1469 tcg_gen_add_tl(t0, t0, inv1);
1470 tcg_temp_free(inv1);
1471 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1472 tcg_temp_free(t1);
1473 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1474 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1475 } else if (add_ca) {
1476 TCGv zero, inv1 = tcg_temp_new();
1477 tcg_gen_not_tl(inv1, arg1);
1478 zero = tcg_const_tl(0);
1479 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1480 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1481 tcg_temp_free(zero);
1482 tcg_temp_free(inv1);
1483 } else {
1484 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1485 tcg_gen_sub_tl(t0, arg2, arg1);
1486 }
1487 } else if (add_ca) {
1488 /* Since we're ignoring carry-out, we can simplify the
1489 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1490 tcg_gen_sub_tl(t0, arg2, arg1);
1491 tcg_gen_add_tl(t0, t0, cpu_ca);
1492 tcg_gen_subi_tl(t0, t0, 1);
1493 } else {
1494 tcg_gen_sub_tl(t0, arg2, arg1);
1495 }
1496
1497 if (compute_ov) {
1498 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1499 }
1500 if (unlikely(compute_rc0)) {
1501 gen_set_Rc0(ctx, t0);
1502 }
1503
1504 if (!TCGV_EQUAL(t0, ret)) {
1505 tcg_gen_mov_tl(ret, t0);
1506 tcg_temp_free(t0);
1507 }
1508 }
1509 /* Sub functions with Two operands functions */
1510 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1511 static void glue(gen_, name)(DisasContext *ctx) \
1512 { \
1513 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1514 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1515 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1516 }
1517 /* Sub functions with one operand and one immediate */
1518 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1519 add_ca, compute_ca, compute_ov) \
1520 static void glue(gen_, name)(DisasContext *ctx) \
1521 { \
1522 TCGv t0 = tcg_const_tl(const_val); \
1523 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1524 cpu_gpr[rA(ctx->opcode)], t0, \
1525 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1526 tcg_temp_free(t0); \
1527 }
1528 /* subf subf. subfo subfo. */
1529 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1530 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1531 /* subfc subfc. subfco subfco. */
1532 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1533 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1534 /* subfe subfe. subfeo subfo. */
1535 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1536 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1537 /* subfme subfme. subfmeo subfmeo. */
1538 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1539 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1540 /* subfze subfze. subfzeo subfzeo.*/
1541 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1542 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1543
1544 /* subfic */
1545 static void gen_subfic(DisasContext *ctx)
1546 {
1547 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1548 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1549 c, 0, 1, 0, 0);
1550 tcg_temp_free(c);
1551 }
1552
1553 /* neg neg. nego nego. */
1554 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1555 {
1556 TCGv zero = tcg_const_tl(0);
1557 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1558 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1559 tcg_temp_free(zero);
1560 }
1561
1562 static void gen_neg(DisasContext *ctx)
1563 {
1564 gen_op_arith_neg(ctx, 0);
1565 }
1566
1567 static void gen_nego(DisasContext *ctx)
1568 {
1569 gen_op_arith_neg(ctx, 1);
1570 }
1571
1572 /*** Integer logical ***/
1573 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1574 static void glue(gen_, name)(DisasContext *ctx) \
1575 { \
1576 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1577 cpu_gpr[rB(ctx->opcode)]); \
1578 if (unlikely(Rc(ctx->opcode) != 0)) \
1579 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1580 }
1581
1582 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1583 static void glue(gen_, name)(DisasContext *ctx) \
1584 { \
1585 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1586 if (unlikely(Rc(ctx->opcode) != 0)) \
1587 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1588 }
1589
1590 /* and & and. */
1591 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1592 /* andc & andc. */
1593 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1594
1595 /* andi. */
1596 static void gen_andi_(DisasContext *ctx)
1597 {
1598 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1599 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1600 }
1601
1602 /* andis. */
1603 static void gen_andis_(DisasContext *ctx)
1604 {
1605 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1606 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1607 }
1608
1609 /* cntlzw */
1610 static void gen_cntlzw(DisasContext *ctx)
1611 {
1612 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1613 if (unlikely(Rc(ctx->opcode) != 0))
1614 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1615 }
1616
1617 /* cnttzw */
1618 static void gen_cnttzw(DisasContext *ctx)
1619 {
1620 gen_helper_cnttzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1621 if (unlikely(Rc(ctx->opcode) != 0)) {
1622 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1623 }
1624 }
1625
1626 /* eqv & eqv. */
1627 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1628 /* extsb & extsb. */
1629 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1630 /* extsh & extsh. */
1631 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1632 /* nand & nand. */
1633 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1634 /* nor & nor. */
1635 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1636
1637 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1638 static void gen_pause(DisasContext *ctx)
1639 {
1640 TCGv_i32 t0 = tcg_const_i32(0);
1641 tcg_gen_st_i32(t0, cpu_env,
1642 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1643 tcg_temp_free_i32(t0);
1644
1645 /* Stop translation, this gives other CPUs a chance to run */
1646 gen_exception_err(ctx, EXCP_HLT, 1);
1647 }
1648 #endif /* defined(TARGET_PPC64) */
1649
1650 /* or & or. */
1651 static void gen_or(DisasContext *ctx)
1652 {
1653 int rs, ra, rb;
1654
1655 rs = rS(ctx->opcode);
1656 ra = rA(ctx->opcode);
1657 rb = rB(ctx->opcode);
1658 /* Optimisation for mr. ri case */
1659 if (rs != ra || rs != rb) {
1660 if (rs != rb)
1661 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1662 else
1663 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1664 if (unlikely(Rc(ctx->opcode) != 0))
1665 gen_set_Rc0(ctx, cpu_gpr[ra]);
1666 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1667 gen_set_Rc0(ctx, cpu_gpr[rs]);
1668 #if defined(TARGET_PPC64)
1669 } else if (rs != 0) { /* 0 is nop */
1670 int prio = 0;
1671
1672 switch (rs) {
1673 case 1:
1674 /* Set process priority to low */
1675 prio = 2;
1676 break;
1677 case 6:
1678 /* Set process priority to medium-low */
1679 prio = 3;
1680 break;
1681 case 2:
1682 /* Set process priority to normal */
1683 prio = 4;
1684 break;
1685 #if !defined(CONFIG_USER_ONLY)
1686 case 31:
1687 if (!ctx->pr) {
1688 /* Set process priority to very low */
1689 prio = 1;
1690 }
1691 break;
1692 case 5:
1693 if (!ctx->pr) {
1694 /* Set process priority to medium-hight */
1695 prio = 5;
1696 }
1697 break;
1698 case 3:
1699 if (!ctx->pr) {
1700 /* Set process priority to high */
1701 prio = 6;
1702 }
1703 break;
1704 case 7:
1705 if (ctx->hv && !ctx->pr) {
1706 /* Set process priority to very high */
1707 prio = 7;
1708 }
1709 break;
1710 #endif
1711 default:
1712 break;
1713 }
1714 if (prio) {
1715 TCGv t0 = tcg_temp_new();
1716 gen_load_spr(t0, SPR_PPR);
1717 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1718 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1719 gen_store_spr(SPR_PPR, t0);
1720 tcg_temp_free(t0);
1721 }
1722 #if !defined(CONFIG_USER_ONLY)
1723 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1724 * CPU and the kernel hangs. This applies to all encodings other
1725 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1726 * and all currently undefined.
1727 */
1728 gen_pause(ctx);
1729 #endif
1730 #endif
1731 }
1732 }
1733 /* orc & orc. */
1734 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1735
1736 /* xor & xor. */
1737 static void gen_xor(DisasContext *ctx)
1738 {
1739 /* Optimisation for "set to zero" case */
1740 if (rS(ctx->opcode) != rB(ctx->opcode))
1741 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1742 else
1743 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1744 if (unlikely(Rc(ctx->opcode) != 0))
1745 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1746 }
1747
1748 /* ori */
1749 static void gen_ori(DisasContext *ctx)
1750 {
1751 target_ulong uimm = UIMM(ctx->opcode);
1752
1753 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1754 return;
1755 }
1756 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1757 }
1758
1759 /* oris */
1760 static void gen_oris(DisasContext *ctx)
1761 {
1762 target_ulong uimm = UIMM(ctx->opcode);
1763
1764 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1765 /* NOP */
1766 return;
1767 }
1768 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1769 }
1770
1771 /* xori */
1772 static void gen_xori(DisasContext *ctx)
1773 {
1774 target_ulong uimm = UIMM(ctx->opcode);
1775
1776 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1777 /* NOP */
1778 return;
1779 }
1780 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1781 }
1782
1783 /* xoris */
1784 static void gen_xoris(DisasContext *ctx)
1785 {
1786 target_ulong uimm = UIMM(ctx->opcode);
1787
1788 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1789 /* NOP */
1790 return;
1791 }
1792 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1793 }
1794
1795 /* popcntb : PowerPC 2.03 specification */
1796 static void gen_popcntb(DisasContext *ctx)
1797 {
1798 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1799 }
1800
1801 static void gen_popcntw(DisasContext *ctx)
1802 {
1803 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1804 }
1805
1806 #if defined(TARGET_PPC64)
1807 /* popcntd: PowerPC 2.06 specification */
1808 static void gen_popcntd(DisasContext *ctx)
1809 {
1810 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1811 }
1812 #endif
1813
1814 /* prtyw: PowerPC 2.05 specification */
1815 static void gen_prtyw(DisasContext *ctx)
1816 {
1817 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1818 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1819 TCGv t0 = tcg_temp_new();
1820 tcg_gen_shri_tl(t0, rs, 16);
1821 tcg_gen_xor_tl(ra, rs, t0);
1822 tcg_gen_shri_tl(t0, ra, 8);
1823 tcg_gen_xor_tl(ra, ra, t0);
1824 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1825 tcg_temp_free(t0);
1826 }
1827
1828 #if defined(TARGET_PPC64)
1829 /* prtyd: PowerPC 2.05 specification */
1830 static void gen_prtyd(DisasContext *ctx)
1831 {
1832 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1833 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1834 TCGv t0 = tcg_temp_new();
1835 tcg_gen_shri_tl(t0, rs, 32);
1836 tcg_gen_xor_tl(ra, rs, t0);
1837 tcg_gen_shri_tl(t0, ra, 16);
1838 tcg_gen_xor_tl(ra, ra, t0);
1839 tcg_gen_shri_tl(t0, ra, 8);
1840 tcg_gen_xor_tl(ra, ra, t0);
1841 tcg_gen_andi_tl(ra, ra, 1);
1842 tcg_temp_free(t0);
1843 }
1844 #endif
1845
1846 #if defined(TARGET_PPC64)
1847 /* bpermd */
1848 static void gen_bpermd(DisasContext *ctx)
1849 {
1850 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1851 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1852 }
1853 #endif
1854
1855 #if defined(TARGET_PPC64)
1856 /* extsw & extsw. */
1857 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1858
1859 /* cntlzd */
1860 static void gen_cntlzd(DisasContext *ctx)
1861 {
1862 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1863 if (unlikely(Rc(ctx->opcode) != 0))
1864 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1865 }
1866
1867 /* cnttzd */
1868 static void gen_cnttzd(DisasContext *ctx)
1869 {
1870 gen_helper_cnttzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1871 if (unlikely(Rc(ctx->opcode) != 0)) {
1872 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1873 }
1874 }
1875 #endif
1876
1877 /*** Integer rotate ***/
1878
1879 /* rlwimi & rlwimi. */
1880 static void gen_rlwimi(DisasContext *ctx)
1881 {
1882 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1883 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1884 uint32_t sh = SH(ctx->opcode);
1885 uint32_t mb = MB(ctx->opcode);
1886 uint32_t me = ME(ctx->opcode);
1887
1888 if (sh == (31-me) && mb <= me) {
1889 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1890 } else {
1891 target_ulong mask;
1892 TCGv t1;
1893
1894 #if defined(TARGET_PPC64)
1895 mb += 32;
1896 me += 32;
1897 #endif
1898 mask = MASK(mb, me);
1899
1900 t1 = tcg_temp_new();
1901 if (mask <= 0xffffffffu) {
1902 TCGv_i32 t0 = tcg_temp_new_i32();
1903 tcg_gen_trunc_tl_i32(t0, t_rs);
1904 tcg_gen_rotli_i32(t0, t0, sh);
1905 tcg_gen_extu_i32_tl(t1, t0);
1906 tcg_temp_free_i32(t0);
1907 } else {
1908 #if defined(TARGET_PPC64)
1909 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1910 tcg_gen_rotli_i64(t1, t1, sh);
1911 #else
1912 g_assert_not_reached();
1913 #endif
1914 }
1915
1916 tcg_gen_andi_tl(t1, t1, mask);
1917 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1918 tcg_gen_or_tl(t_ra, t_ra, t1);
1919 tcg_temp_free(t1);
1920 }
1921 if (unlikely(Rc(ctx->opcode) != 0)) {
1922 gen_set_Rc0(ctx, t_ra);
1923 }
1924 }
1925
1926 /* rlwinm & rlwinm. */
1927 static void gen_rlwinm(DisasContext *ctx)
1928 {
1929 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1930 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1931 uint32_t sh = SH(ctx->opcode);
1932 uint32_t mb = MB(ctx->opcode);
1933 uint32_t me = ME(ctx->opcode);
1934
1935 if (mb == 0 && me == (31 - sh)) {
1936 tcg_gen_shli_tl(t_ra, t_rs, sh);
1937 tcg_gen_ext32u_tl(t_ra, t_ra);
1938 } else if (sh != 0 && me == 31 && sh == (32 - mb)) {
1939 tcg_gen_ext32u_tl(t_ra, t_rs);
1940 tcg_gen_shri_tl(t_ra, t_ra, mb);
1941 } else {
1942 target_ulong mask;
1943 #if defined(TARGET_PPC64)
1944 mb += 32;
1945 me += 32;
1946 #endif
1947 mask = MASK(mb, me);
1948
1949 if (mask <= 0xffffffffu) {
1950 TCGv_i32 t0 = tcg_temp_new_i32();
1951 tcg_gen_trunc_tl_i32(t0, t_rs);
1952 tcg_gen_rotli_i32(t0, t0, sh);
1953 tcg_gen_andi_i32(t0, t0, mask);
1954 tcg_gen_extu_i32_tl(t_ra, t0);
1955 tcg_temp_free_i32(t0);
1956 } else {
1957 #if defined(TARGET_PPC64)
1958 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1959 tcg_gen_rotli_i64(t_ra, t_ra, sh);
1960 tcg_gen_andi_i64(t_ra, t_ra, mask);
1961 #else
1962 g_assert_not_reached();
1963 #endif
1964 }
1965 }
1966 if (unlikely(Rc(ctx->opcode) != 0)) {
1967 gen_set_Rc0(ctx, t_ra);
1968 }
1969 }
1970
1971 /* rlwnm & rlwnm. */
1972 static void gen_rlwnm(DisasContext *ctx)
1973 {
1974 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1975 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1976 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1977 uint32_t mb = MB(ctx->opcode);
1978 uint32_t me = ME(ctx->opcode);
1979 target_ulong mask;
1980
1981 #if defined(TARGET_PPC64)
1982 mb += 32;
1983 me += 32;
1984 #endif
1985 mask = MASK(mb, me);
1986
1987 if (mask <= 0xffffffffu) {
1988 TCGv_i32 t0 = tcg_temp_new_i32();
1989 TCGv_i32 t1 = tcg_temp_new_i32();
1990 tcg_gen_trunc_tl_i32(t0, t_rb);
1991 tcg_gen_trunc_tl_i32(t1, t_rs);
1992 tcg_gen_andi_i32(t0, t0, 0x1f);
1993 tcg_gen_rotl_i32(t1, t1, t0);
1994 tcg_gen_extu_i32_tl(t_ra, t1);
1995 tcg_temp_free_i32(t0);
1996 tcg_temp_free_i32(t1);
1997 } else {
1998 #if defined(TARGET_PPC64)
1999 TCGv_i64 t0 = tcg_temp_new_i64();
2000 tcg_gen_andi_i64(t0, t_rb, 0x1f);
2001 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
2002 tcg_gen_rotl_i64(t_ra, t_ra, t0);
2003 tcg_temp_free_i64(t0);
2004 #else
2005 g_assert_not_reached();
2006 #endif
2007 }
2008
2009 tcg_gen_andi_tl(t_ra, t_ra, mask);
2010
2011 if (unlikely(Rc(ctx->opcode) != 0)) {
2012 gen_set_Rc0(ctx, t_ra);
2013 }
2014 }
2015
2016 #if defined(TARGET_PPC64)
2017 #define GEN_PPC64_R2(name, opc1, opc2) \
2018 static void glue(gen_, name##0)(DisasContext *ctx) \
2019 { \
2020 gen_##name(ctx, 0); \
2021 } \
2022 \
2023 static void glue(gen_, name##1)(DisasContext *ctx) \
2024 { \
2025 gen_##name(ctx, 1); \
2026 }
2027 #define GEN_PPC64_R4(name, opc1, opc2) \
2028 static void glue(gen_, name##0)(DisasContext *ctx) \
2029 { \
2030 gen_##name(ctx, 0, 0); \
2031 } \
2032 \
2033 static void glue(gen_, name##1)(DisasContext *ctx) \
2034 { \
2035 gen_##name(ctx, 0, 1); \
2036 } \
2037 \
2038 static void glue(gen_, name##2)(DisasContext *ctx) \
2039 { \
2040 gen_##name(ctx, 1, 0); \
2041 } \
2042 \
2043 static void glue(gen_, name##3)(DisasContext *ctx) \
2044 { \
2045 gen_##name(ctx, 1, 1); \
2046 }
2047
2048 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
2049 {
2050 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2051 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2052
2053 if (sh != 0 && mb == 0 && me == (63 - sh)) {
2054 tcg_gen_shli_tl(t_ra, t_rs, sh);
2055 } else if (sh != 0 && me == 63 && sh == (64 - mb)) {
2056 tcg_gen_shri_tl(t_ra, t_rs, mb);
2057 } else {
2058 tcg_gen_rotli_tl(t_ra, t_rs, sh);
2059 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2060 }
2061 if (unlikely(Rc(ctx->opcode) != 0)) {
2062 gen_set_Rc0(ctx, t_ra);
2063 }
2064 }
2065
2066 /* rldicl - rldicl. */
2067 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
2068 {
2069 uint32_t sh, mb;
2070
2071 sh = SH(ctx->opcode) | (shn << 5);
2072 mb = MB(ctx->opcode) | (mbn << 5);
2073 gen_rldinm(ctx, mb, 63, sh);
2074 }
2075 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
2076
2077 /* rldicr - rldicr. */
2078 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
2079 {
2080 uint32_t sh, me;
2081
2082 sh = SH(ctx->opcode) | (shn << 5);
2083 me = MB(ctx->opcode) | (men << 5);
2084 gen_rldinm(ctx, 0, me, sh);
2085 }
2086 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2087
2088 /* rldic - rldic. */
2089 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2090 {
2091 uint32_t sh, mb;
2092
2093 sh = SH(ctx->opcode) | (shn << 5);
2094 mb = MB(ctx->opcode) | (mbn << 5);
2095 gen_rldinm(ctx, mb, 63 - sh, sh);
2096 }
2097 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2098
2099 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2100 {
2101 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2102 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2103 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2104 TCGv t0;
2105
2106 t0 = tcg_temp_new();
2107 tcg_gen_andi_tl(t0, t_rb, 0x3f);
2108 tcg_gen_rotl_tl(t_ra, t_rs, t0);
2109 tcg_temp_free(t0);
2110
2111 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2112 if (unlikely(Rc(ctx->opcode) != 0)) {
2113 gen_set_Rc0(ctx, t_ra);
2114 }
2115 }
2116
2117 /* rldcl - rldcl. */
2118 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2119 {
2120 uint32_t mb;
2121
2122 mb = MB(ctx->opcode) | (mbn << 5);
2123 gen_rldnm(ctx, mb, 63);
2124 }
2125 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2126
2127 /* rldcr - rldcr. */
2128 static inline void gen_rldcr(DisasContext *ctx, int men)
2129 {
2130 uint32_t me;
2131
2132 me = MB(ctx->opcode) | (men << 5);
2133 gen_rldnm(ctx, 0, me);
2134 }
2135 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2136
2137 /* rldimi - rldimi. */
2138 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2139 {
2140 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2141 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2142 uint32_t sh = SH(ctx->opcode) | (shn << 5);
2143 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2144 uint32_t me = 63 - sh;
2145
2146 if (mb <= me) {
2147 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2148 } else {
2149 target_ulong mask = MASK(mb, me);
2150 TCGv t1 = tcg_temp_new();
2151
2152 tcg_gen_rotli_tl(t1, t_rs, sh);
2153 tcg_gen_andi_tl(t1, t1, mask);
2154 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2155 tcg_gen_or_tl(t_ra, t_ra, t1);
2156 tcg_temp_free(t1);
2157 }
2158 if (unlikely(Rc(ctx->opcode) != 0)) {
2159 gen_set_Rc0(ctx, t_ra);
2160 }
2161 }
2162 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2163 #endif
2164
2165 /*** Integer shift ***/
2166
2167 /* slw & slw. */
2168 static void gen_slw(DisasContext *ctx)
2169 {
2170 TCGv t0, t1;
2171
2172 t0 = tcg_temp_new();
2173 /* AND rS with a mask that is 0 when rB >= 0x20 */
2174 #if defined(TARGET_PPC64)
2175 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2176 tcg_gen_sari_tl(t0, t0, 0x3f);
2177 #else
2178 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2179 tcg_gen_sari_tl(t0, t0, 0x1f);
2180 #endif
2181 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2182 t1 = tcg_temp_new();
2183 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2184 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2185 tcg_temp_free(t1);
2186 tcg_temp_free(t0);
2187 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2188 if (unlikely(Rc(ctx->opcode) != 0))
2189 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2190 }
2191
2192 /* sraw & sraw. */
2193 static void gen_sraw(DisasContext *ctx)
2194 {
2195 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
2196 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2197 if (unlikely(Rc(ctx->opcode) != 0))
2198 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2199 }
2200
2201 /* srawi & srawi. */
2202 static void gen_srawi(DisasContext *ctx)
2203 {
2204 int sh = SH(ctx->opcode);
2205 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2206 TCGv src = cpu_gpr[rS(ctx->opcode)];
2207 if (sh == 0) {
2208 tcg_gen_ext32s_tl(dst, src);
2209 tcg_gen_movi_tl(cpu_ca, 0);
2210 } else {
2211 TCGv t0;
2212 tcg_gen_ext32s_tl(dst, src);
2213 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2214 t0 = tcg_temp_new();
2215 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2216 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2217 tcg_temp_free(t0);
2218 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2219 tcg_gen_sari_tl(dst, dst, sh);
2220 }
2221 if (unlikely(Rc(ctx->opcode) != 0)) {
2222 gen_set_Rc0(ctx, dst);
2223 }
2224 }
2225
2226 /* srw & srw. */
2227 static void gen_srw(DisasContext *ctx)
2228 {
2229 TCGv t0, t1;
2230
2231 t0 = tcg_temp_new();
2232 /* AND rS with a mask that is 0 when rB >= 0x20 */
2233 #if defined(TARGET_PPC64)
2234 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2235 tcg_gen_sari_tl(t0, t0, 0x3f);
2236 #else
2237 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2238 tcg_gen_sari_tl(t0, t0, 0x1f);
2239 #endif
2240 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2241 tcg_gen_ext32u_tl(t0, t0);
2242 t1 = tcg_temp_new();
2243 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2244 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2245 tcg_temp_free(t1);
2246 tcg_temp_free(t0);
2247 if (unlikely(Rc(ctx->opcode) != 0))
2248 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2249 }
2250
2251 #if defined(TARGET_PPC64)
2252 /* sld & sld. */
2253 static void gen_sld(DisasContext *ctx)
2254 {
2255 TCGv t0, t1;
2256
2257 t0 = tcg_temp_new();
2258 /* AND rS with a mask that is 0 when rB >= 0x40 */
2259 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2260 tcg_gen_sari_tl(t0, t0, 0x3f);
2261 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2262 t1 = tcg_temp_new();
2263 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2264 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2265 tcg_temp_free(t1);
2266 tcg_temp_free(t0);
2267 if (unlikely(Rc(ctx->opcode) != 0))
2268 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2269 }
2270
2271 /* srad & srad. */
2272 static void gen_srad(DisasContext *ctx)
2273 {
2274 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2275 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2276 if (unlikely(Rc(ctx->opcode) != 0))
2277 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2278 }
2279 /* sradi & sradi. */
2280 static inline void gen_sradi(DisasContext *ctx, int n)
2281 {
2282 int sh = SH(ctx->opcode) + (n << 5);
2283 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2284 TCGv src = cpu_gpr[rS(ctx->opcode)];
2285 if (sh == 0) {
2286 tcg_gen_mov_tl(dst, src);
2287 tcg_gen_movi_tl(cpu_ca, 0);
2288 } else {
2289 TCGv t0;
2290 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2291 t0 = tcg_temp_new();
2292 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2293 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2294 tcg_temp_free(t0);
2295 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2296 tcg_gen_sari_tl(dst, src, sh);
2297 }
2298 if (unlikely(Rc(ctx->opcode) != 0)) {
2299 gen_set_Rc0(ctx, dst);
2300 }
2301 }
2302
2303 static void gen_sradi0(DisasContext *ctx)
2304 {
2305 gen_sradi(ctx, 0);
2306 }
2307
2308 static void gen_sradi1(DisasContext *ctx)
2309 {
2310 gen_sradi(ctx, 1);
2311 }
2312
2313 /* srd & srd. */
2314 static void gen_srd(DisasContext *ctx)
2315 {
2316 TCGv t0, t1;
2317
2318 t0 = tcg_temp_new();
2319 /* AND rS with a mask that is 0 when rB >= 0x40 */
2320 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2321 tcg_gen_sari_tl(t0, t0, 0x3f);
2322 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2323 t1 = tcg_temp_new();
2324 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2325 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2326 tcg_temp_free(t1);
2327 tcg_temp_free(t0);
2328 if (unlikely(Rc(ctx->opcode) != 0))
2329 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2330 }
2331 #endif
2332
2333 /*** Addressing modes ***/
2334 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2335 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2336 target_long maskl)
2337 {
2338 target_long simm = SIMM(ctx->opcode);
2339
2340 simm &= ~maskl;
2341 if (rA(ctx->opcode) == 0) {
2342 if (NARROW_MODE(ctx)) {
2343 simm = (uint32_t)simm;
2344 }
2345 tcg_gen_movi_tl(EA, simm);
2346 } else if (likely(simm != 0)) {
2347 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2348 if (NARROW_MODE(ctx)) {
2349 tcg_gen_ext32u_tl(EA, EA);
2350 }
2351 } else {
2352 if (NARROW_MODE(ctx)) {
2353 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2354 } else {
2355 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2356 }
2357 }
2358 }
2359
2360 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2361 {
2362 if (rA(ctx->opcode) == 0) {
2363 if (NARROW_MODE(ctx)) {
2364 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2365 } else {
2366 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2367 }
2368 } else {
2369 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2370 if (NARROW_MODE(ctx)) {
2371 tcg_gen_ext32u_tl(EA, EA);
2372 }
2373 }
2374 }
2375
2376 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2377 {
2378 if (rA(ctx->opcode) == 0) {
2379 tcg_gen_movi_tl(EA, 0);
2380 } else if (NARROW_MODE(ctx)) {
2381 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2382 } else {
2383 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2384 }
2385 }
2386
2387 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2388 target_long val)
2389 {
2390 tcg_gen_addi_tl(ret, arg1, val);
2391 if (NARROW_MODE(ctx)) {
2392 tcg_gen_ext32u_tl(ret, ret);
2393 }
2394 }
2395
2396 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2397 {
2398 TCGLabel *l1 = gen_new_label();
2399 TCGv t0 = tcg_temp_new();
2400 TCGv_i32 t1, t2;
2401 /* NIP cannot be restored if the memory exception comes from an helper */
2402 gen_update_nip(ctx, ctx->nip - 4);
2403 tcg_gen_andi_tl(t0, EA, mask);
2404 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2405 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2406 t2 = tcg_const_i32(0);
2407 gen_helper_raise_exception_err(cpu_env, t1, t2);
2408 tcg_temp_free_i32(t1);
2409 tcg_temp_free_i32(t2);
2410 gen_set_label(l1);
2411 tcg_temp_free(t0);
2412 }
2413
2414 /*** Integer load ***/
2415 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2416 {
2417 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2418 }
2419
2420 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2421 {
2422 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2423 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2424 }
2425
2426 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2427 {
2428 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2429 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2430 }
2431
2432 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2433 {
2434 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2435 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2436 }
2437
2438 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2439 {
2440 TCGv tmp = tcg_temp_new();
2441 gen_qemu_ld32u(ctx, tmp, addr);
2442 tcg_gen_extu_tl_i64(val, tmp);
2443 tcg_temp_free(tmp);
2444 }
2445
2446 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2447 {
2448 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2449 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2450 }
2451
2452 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2453 {
2454 TCGv tmp = tcg_temp_new();
2455 gen_qemu_ld32s(ctx, tmp, addr);
2456 tcg_gen_ext_tl_i64(val, tmp);
2457 tcg_temp_free(tmp);
2458 }
2459
2460 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2461 {
2462 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2463 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2464 }
2465
2466 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2467 {
2468 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2469 }
2470
2471 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2472 {
2473 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2474 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2475 }
2476
2477 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2478 {
2479 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2480 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2481 }
2482
2483 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2484 {
2485 TCGv tmp = tcg_temp_new();
2486 tcg_gen_trunc_i64_tl(tmp, val);
2487 gen_qemu_st32(ctx, tmp, addr);
2488 tcg_temp_free(tmp);
2489 }
2490
2491 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2492 {
2493 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2494 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2495 }
2496
2497 #define GEN_LD(name, ldop, opc, type) \
2498 static void glue(gen_, name)(DisasContext *ctx) \
2499 { \
2500 TCGv EA; \
2501 gen_set_access_type(ctx, ACCESS_INT); \
2502 EA = tcg_temp_new(); \
2503 gen_addr_imm_index(ctx, EA, 0); \
2504 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2505 tcg_temp_free(EA); \
2506 }
2507
2508 #define GEN_LDU(name, ldop, opc, type) \
2509 static void glue(gen_, name##u)(DisasContext *ctx) \
2510 { \
2511 TCGv EA; \
2512 if (unlikely(rA(ctx->opcode) == 0 || \
2513 rA(ctx->opcode) == rD(ctx->opcode))) { \
2514 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2515 return; \
2516 } \
2517 gen_set_access_type(ctx, ACCESS_INT); \
2518 EA = tcg_temp_new(); \
2519 if (type == PPC_64B) \
2520 gen_addr_imm_index(ctx, EA, 0x03); \
2521 else \
2522 gen_addr_imm_index(ctx, EA, 0); \
2523 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2524 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2525 tcg_temp_free(EA); \
2526 }
2527
2528 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2529 static void glue(gen_, name##ux)(DisasContext *ctx) \
2530 { \
2531 TCGv EA; \
2532 if (unlikely(rA(ctx->opcode) == 0 || \
2533 rA(ctx->opcode) == rD(ctx->opcode))) { \
2534 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2535 return; \
2536 } \
2537 gen_set_access_type(ctx, ACCESS_INT); \
2538 EA = tcg_temp_new(); \
2539 gen_addr_reg_index(ctx, EA); \
2540 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2541 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2542 tcg_temp_free(EA); \
2543 }
2544
2545 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2546 static void glue(gen_, name##x)(DisasContext *ctx) \
2547 { \
2548 TCGv EA; \
2549 chk; \
2550 gen_set_access_type(ctx, ACCESS_INT); \
2551 EA = tcg_temp_new(); \
2552 gen_addr_reg_index(ctx, EA); \
2553 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2554 tcg_temp_free(EA); \
2555 }
2556
2557 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2558 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2559
2560 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2561 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2562
2563 #define GEN_LDS(name, ldop, op, type) \
2564 GEN_LD(name, ldop, op | 0x20, type); \
2565 GEN_LDU(name, ldop, op | 0x21, type); \
2566 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2567 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2568
2569 /* lbz lbzu lbzux lbzx */
2570 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2571 /* lha lhau lhaux lhax */
2572 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2573 /* lhz lhzu lhzux lhzx */
2574 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2575 /* lwz lwzu lwzux lwzx */
2576 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2577 #if defined(TARGET_PPC64)
2578 /* lwaux */
2579 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2580 /* lwax */
2581 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2582 /* ldux */
2583 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2584 /* ldx */
2585 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2586
2587 /* CI load/store variants */
2588 GEN_LDX_HVRM(ldcix, ld64, 0x15, 0x1b, PPC_CILDST)
2589 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
2590 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
2591 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
2592
2593 static void gen_ld(DisasContext *ctx)
2594 {
2595 TCGv EA;
2596 if (Rc(ctx->opcode)) {
2597 if (unlikely(rA(ctx->opcode) == 0 ||
2598 rA(ctx->opcode) == rD(ctx->opcode))) {
2599 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2600 return;
2601 }
2602 }
2603 gen_set_access_type(ctx, ACCESS_INT);
2604 EA = tcg_temp_new();
2605 gen_addr_imm_index(ctx, EA, 0x03);
2606 if (ctx->opcode & 0x02) {
2607 /* lwa (lwau is undefined) */
2608 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2609 } else {
2610 /* ld - ldu */
2611 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2612 }
2613 if (Rc(ctx->opcode))
2614 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2615 tcg_temp_free(EA);
2616 }
2617
2618 /* lq */
2619 static void gen_lq(DisasContext *ctx)
2620 {
2621 int ra, rd;
2622 TCGv EA;
2623
2624 /* lq is a legal user mode instruction starting in ISA 2.07 */
2625 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2626 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2627
2628 if (!legal_in_user_mode && ctx->pr) {
2629 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2630 return;
2631 }
2632
2633 if (!le_is_supported && ctx->le_mode) {
2634 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2635 return;
2636 }
2637
2638 ra = rA(ctx->opcode);
2639 rd = rD(ctx->opcode);
2640 if (unlikely((rd & 1) || rd == ra)) {
2641 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2642 return;
2643 }
2644
2645 gen_set_access_type(ctx, ACCESS_INT);
2646 EA = tcg_temp_new();
2647 gen_addr_imm_index(ctx, EA, 0x0F);
2648
2649 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2650 64-bit byteswap already. */
2651 if (unlikely(ctx->le_mode)) {
2652 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2653 gen_addr_add(ctx, EA, EA, 8);
2654 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2655 } else {
2656 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2657 gen_addr_add(ctx, EA, EA, 8);
2658 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2659 }
2660 tcg_temp_free(EA);
2661 }
2662 #endif
2663
2664 /*** Integer store ***/
2665 #define GEN_ST(name, stop, opc, type) \
2666 static void glue(gen_, name)(DisasContext *ctx) \
2667 { \
2668 TCGv EA; \
2669 gen_set_access_type(ctx, ACCESS_INT); \
2670 EA = tcg_temp_new(); \
2671 gen_addr_imm_index(ctx, EA, 0); \
2672 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2673 tcg_temp_free(EA); \
2674 }
2675
2676 #define GEN_STU(name, stop, opc, type) \
2677 static void glue(gen_, stop##u)(DisasContext *ctx) \
2678 { \
2679 TCGv EA; \
2680 if (unlikely(rA(ctx->opcode) == 0)) { \
2681 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2682 return; \
2683 } \
2684 gen_set_access_type(ctx, ACCESS_INT); \
2685 EA = tcg_temp_new(); \
2686 if (type == PPC_64B) \
2687 gen_addr_imm_index(ctx, EA, 0x03); \
2688 else \
2689 gen_addr_imm_index(ctx, EA, 0); \
2690 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2691 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2692 tcg_temp_free(EA); \
2693 }
2694
2695 #define GEN_STUX(name, stop, opc2, opc3, type) \
2696 static void glue(gen_, name##ux)(DisasContext *ctx) \
2697 { \
2698 TCGv EA; \
2699 if (unlikely(rA(ctx->opcode) == 0)) { \
2700 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2701 return; \
2702 } \
2703 gen_set_access_type(ctx, ACCESS_INT); \
2704 EA = tcg_temp_new(); \
2705 gen_addr_reg_index(ctx, EA); \
2706 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2707 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2708 tcg_temp_free(EA); \
2709 }
2710
2711 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2712 static void glue(gen_, name##x)(DisasContext *ctx) \
2713 { \
2714 TCGv EA; \
2715 chk; \
2716 gen_set_access_type(ctx, ACCESS_INT); \
2717 EA = tcg_temp_new(); \
2718 gen_addr_reg_index(ctx, EA); \
2719 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2720 tcg_temp_free(EA); \
2721 }
2722 #define GEN_STX(name, stop, opc2, opc3, type) \
2723 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2724
2725 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2726 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2727
2728 #define GEN_STS(name, stop, op, type) \
2729 GEN_ST(name, stop, op | 0x20, type); \
2730 GEN_STU(name, stop, op | 0x21, type); \
2731 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2732 GEN_STX(name, stop, 0x17, op | 0x00, type)
2733
2734 /* stb stbu stbux stbx */
2735 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2736 /* sth sthu sthux sthx */
2737 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2738 /* stw stwu stwux stwx */
2739 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2740 #if defined(TARGET_PPC64)
2741 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2742 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2743 GEN_STX_HVRM(stdcix, st64, 0x15, 0x1f, PPC_CILDST)
2744 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
2745 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
2746 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
2747
2748 static void gen_std(DisasContext *ctx)
2749 {
2750 int rs;
2751 TCGv EA;
2752
2753 rs = rS(ctx->opcode);
2754 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2755 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2756 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2757
2758 if (!(ctx->insns_flags & PPC_64BX)) {
2759 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2760 }
2761
2762 if (!legal_in_user_mode && ctx->pr) {
2763 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2764 return;
2765 }
2766
2767 if (!le_is_supported && ctx->le_mode) {
2768 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2769 return;
2770 }
2771
2772 if (unlikely(rs & 1)) {
2773 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2774 return;
2775 }
2776 gen_set_access_type(ctx, ACCESS_INT);
2777 EA = tcg_temp_new();
2778 gen_addr_imm_index(ctx, EA, 0x03);
2779
2780 /* We only need to swap high and low halves. gen_qemu_st64 does
2781 necessary 64-bit byteswap already. */
2782 if (unlikely(ctx->le_mode)) {
2783 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2784 gen_addr_add(ctx, EA, EA, 8);
2785 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2786 } else {
2787 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2788 gen_addr_add(ctx, EA, EA, 8);
2789 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2790 }
2791 tcg_temp_free(EA);
2792 } else {
2793 /* std / stdu*/
2794 if (Rc(ctx->opcode)) {
2795 if (unlikely(rA(ctx->opcode) == 0)) {
2796 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2797 return;
2798 }
2799 }
2800 gen_set_access_type(ctx, ACCESS_INT);
2801 EA = tcg_temp_new();
2802 gen_addr_imm_index(ctx, EA, 0x03);
2803 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2804 if (Rc(ctx->opcode))
2805 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2806 tcg_temp_free(EA);
2807 }
2808 }
2809 #endif
2810 /*** Integer load and store with byte reverse ***/
2811
2812 /* lhbrx */
2813 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2814 {
2815 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2816 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2817 }
2818 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2819
2820 /* lwbrx */
2821 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2822 {
2823 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2824 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2825 }
2826 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2827
2828 #if defined(TARGET_PPC64)
2829 /* ldbrx */
2830 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2831 {
2832 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2833 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2834 }
2835 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
2836 #endif /* TARGET_PPC64 */
2837
2838 /* sthbrx */
2839 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2840 {
2841 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2842 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2843 }
2844 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2845
2846 /* stwbrx */
2847 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2848 {
2849 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2850 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2851 }
2852 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2853
2854 #if defined(TARGET_PPC64)
2855 /* stdbrx */
2856 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2857 {
2858 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2859 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2860 }
2861 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
2862 #endif /* TARGET_PPC64 */
2863
2864 /*** Integer load and store multiple ***/
2865
2866 /* lmw */
2867 static void gen_lmw(DisasContext *ctx)
2868 {
2869 TCGv t0;
2870 TCGv_i32 t1;
2871 gen_set_access_type(ctx, ACCESS_INT);
2872 /* NIP cannot be restored if the memory exception comes from an helper */
2873 gen_update_nip(ctx, ctx->nip - 4);
2874 t0 = tcg_temp_new();
2875 t1 = tcg_const_i32(rD(ctx->opcode));
2876 gen_addr_imm_index(ctx, t0, 0);
2877 gen_helper_lmw(cpu_env, t0, t1);
2878 tcg_temp_free(t0);
2879 tcg_temp_free_i32(t1);
2880 }
2881
2882 /* stmw */
2883 static void gen_stmw(DisasContext *ctx)
2884 {
2885 TCGv t0;
2886 TCGv_i32 t1;
2887 gen_set_access_type(ctx, ACCESS_INT);
2888 /* NIP cannot be restored if the memory exception comes from an helper */
2889 gen_update_nip(ctx, ctx->nip - 4);
2890 t0 = tcg_temp_new();
2891 t1 = tcg_const_i32(rS(ctx->opcode));
2892 gen_addr_imm_index(ctx, t0, 0);
2893 gen_helper_stmw(cpu_env, t0, t1);
2894 tcg_temp_free(t0);
2895 tcg_temp_free_i32(t1);
2896 }
2897
2898 /*** Integer load and store strings ***/
2899
2900 /* lswi */
2901 /* PowerPC32 specification says we must generate an exception if
2902 * rA is in the range of registers to be loaded.
2903 * In an other hand, IBM says this is valid, but rA won't be loaded.
2904 * For now, I'll follow the spec...
2905 */
2906 static void gen_lswi(DisasContext *ctx)
2907 {
2908 TCGv t0;
2909 TCGv_i32 t1, t2;
2910 int nb = NB(ctx->opcode);
2911 int start = rD(ctx->opcode);
2912 int ra = rA(ctx->opcode);
2913 int nr;
2914
2915 if (nb == 0)
2916 nb = 32;
2917 nr = (nb + 3) / 4;
2918 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
2919 /* The handler expects the PC to point to *this* instruction,
2920 * so setting ctx->exception here prevents it from being
2921 * improperly updated again by gen_inval_exception
2922 */
2923 gen_update_nip(ctx, ctx->nip - 4);
2924 ctx->exception = POWERPC_EXCP_HV_EMU;
2925 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2926 return;
2927 }
2928 gen_set_access_type(ctx, ACCESS_INT);
2929 t0 = tcg_temp_new();
2930 gen_addr_register(ctx, t0);
2931 t1 = tcg_const_i32(nb);
2932 t2 = tcg_const_i32(start);
2933 gen_helper_lsw(cpu_env, t0, t1, t2);
2934 tcg_temp_free(t0);
2935 tcg_temp_free_i32(t1);
2936 tcg_temp_free_i32(t2);
2937 }
2938
2939 /* lswx */
2940 static void gen_lswx(DisasContext *ctx)
2941 {
2942 TCGv t0;
2943 TCGv_i32 t1, t2, t3;
2944 gen_set_access_type(ctx, ACCESS_INT);
2945 t0 = tcg_temp_new();
2946 gen_addr_reg_index(ctx, t0);
2947 t1 = tcg_const_i32(rD(ctx->opcode));
2948 t2 = tcg_const_i32(rA(ctx->opcode));
2949 t3 = tcg_const_i32(rB(ctx->opcode));
2950 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
2951 tcg_temp_free(t0);
2952 tcg_temp_free_i32(t1);
2953 tcg_temp_free_i32(t2);
2954 tcg_temp_free_i32(t3);
2955 }
2956
2957 /* stswi */
2958 static void gen_stswi(DisasContext *ctx)
2959 {
2960 TCGv t0;
2961 TCGv_i32 t1, t2;
2962 int nb = NB(ctx->opcode);
2963 gen_set_access_type(ctx, ACCESS_INT);
2964 t0 = tcg_temp_new();
2965 gen_addr_register(ctx, t0);
2966 if (nb == 0)
2967 nb = 32;
2968 t1 = tcg_const_i32(nb);
2969 t2 = tcg_const_i32(rS(ctx->opcode));
2970 gen_helper_stsw(cpu_env, t0, t1, t2);
2971 tcg_temp_free(t0);
2972 tcg_temp_free_i32(t1);
2973 tcg_temp_free_i32(t2);
2974 }
2975
2976 /* stswx */
2977 static void gen_stswx(DisasContext *ctx)
2978 {
2979 TCGv t0;
2980 TCGv_i32 t1, t2;
2981 gen_set_access_type(ctx, ACCESS_INT);
2982 t0 = tcg_temp_new();
2983 gen_addr_reg_index(ctx, t0);
2984 t1 = tcg_temp_new_i32();
2985 tcg_gen_trunc_tl_i32(t1, cpu_xer);
2986 tcg_gen_andi_i32(t1, t1, 0x7F);
2987 t2 = tcg_const_i32(rS(ctx->opcode));
2988 gen_helper_stsw(cpu_env, t0, t1, t2);
2989 tcg_temp_free(t0);
2990 tcg_temp_free_i32(t1);
2991 tcg_temp_free_i32(t2);
2992 }
2993
2994 /*** Memory synchronisation ***/
2995 /* eieio */
2996 static void gen_eieio(DisasContext *ctx)
2997 {
2998 }
2999
3000 #if !defined(CONFIG_USER_ONLY)
3001 static inline void gen_check_tlb_flush(DisasContext *ctx)
3002 {
3003 TCGv_i32 t;
3004 TCGLabel *l;
3005
3006 if (!ctx->lazy_tlb_flush) {
3007 return;
3008 }
3009 l = gen_new_label();
3010 t = tcg_temp_new_i32();
3011 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3012 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3013 gen_helper_check_tlb_flush(cpu_env);
3014 gen_set_label(l);
3015 tcg_temp_free_i32(t);
3016 }
3017 #else
3018 static inline void gen_check_tlb_flush(DisasContext *ctx) { }
3019 #endif
3020
3021 /* isync */
3022 static void gen_isync(DisasContext *ctx)
3023 {
3024 /*
3025 * We need to check for a pending TLB flush. This can only happen in
3026 * kernel mode however so check MSR_PR
3027 */
3028 if (!ctx->pr) {
3029 gen_check_tlb_flush(ctx);
3030 }
3031 gen_stop_exception(ctx);
3032 }
3033
3034 #define LARX(name, len, loadop) \
3035 static void gen_##name(DisasContext *ctx) \
3036 { \
3037 TCGv t0; \
3038 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3039 gen_set_access_type(ctx, ACCESS_RES); \
3040 t0 = tcg_temp_local_new(); \
3041 gen_addr_reg_index(ctx, t0); \
3042 if ((len) > 1) { \
3043 gen_check_align(ctx, t0, (len)-1); \
3044 } \
3045 gen_qemu_##loadop(ctx, gpr, t0); \
3046 tcg_gen_mov_tl(cpu_reserve, t0); \
3047 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3048 tcg_temp_free(t0); \
3049 }
3050
3051 /* lwarx */
3052 LARX(lbarx, 1, ld8u);
3053 LARX(lharx, 2, ld16u);
3054 LARX(lwarx, 4, ld32u);
3055
3056
3057 #if defined(CONFIG_USER_ONLY)
3058 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3059 int reg, int size)
3060 {
3061 TCGv t0 = tcg_temp_new();
3062 uint32_t save_exception = ctx->exception;
3063
3064 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3065 tcg_gen_movi_tl(t0, (size << 5) | reg);
3066 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3067 tcg_temp_free(t0);
3068 gen_update_nip(ctx, ctx->nip-4);
3069 ctx->exception = POWERPC_EXCP_BRANCH;
3070 gen_exception(ctx, POWERPC_EXCP_STCX);
3071 ctx->exception = save_exception;
3072 }
3073 #else
3074 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3075 int reg, int size)
3076 {
3077 TCGLabel *l1;
3078
3079 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3080 l1 = gen_new_label();
3081 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3082 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3083 #if defined(TARGET_PPC64)
3084 if (size == 8) {
3085 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3086 } else
3087 #endif
3088 if (size == 4) {
3089 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3090 } else if (size == 2) {
3091 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3092 #if defined(TARGET_PPC64)
3093 } else if (size == 16) {
3094 TCGv gpr1, gpr2 , EA8;
3095 if (unlikely(ctx->le_mode)) {
3096 gpr1 = cpu_gpr[reg+1];
3097 gpr2 = cpu_gpr[reg];
3098 } else {
3099 gpr1 = cpu_gpr[reg];
3100 gpr2 = cpu_gpr[reg+1];
3101 }
3102 gen_qemu_st64(ctx, gpr1, EA);
3103 EA8 = tcg_temp_local_new();
3104 gen_addr_add(ctx, EA8, EA, 8);
3105 gen_qemu_st64(ctx, gpr2, EA8);
3106 tcg_temp_free(EA8);
3107 #endif
3108 } else {
3109 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3110 }
3111 gen_set_label(l1);
3112 tcg_gen_movi_tl(cpu_reserve, -1);
3113 }
3114 #endif
3115
3116 #define STCX(name, len) \
3117 static void gen_##name(DisasContext *ctx) \
3118 { \
3119 TCGv t0; \
3120 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3121 gen_inval_exception(ctx, \
3122 POWERPC_EXCP_INVAL_INVAL); \
3123 return; \
3124 } \
3125 gen_set_access_type(ctx, ACCESS_RES); \
3126 t0 = tcg_temp_local_new(); \
3127 gen_addr_reg_index(ctx, t0); \
3128 if (len > 1) { \
3129 gen_check_align(ctx, t0, (len)-1); \
3130 } \
3131 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3132 tcg_temp_free(t0); \
3133 }
3134
3135 STCX(stbcx_, 1);
3136 STCX(sthcx_, 2);
3137 STCX(stwcx_, 4);
3138
3139 #if defined(TARGET_PPC64)
3140 /* ldarx */
3141 LARX(ldarx, 8, ld64);
3142
3143 /* lqarx */
3144 static void gen_lqarx(DisasContext *ctx)
3145 {
3146 TCGv EA;
3147 int rd = rD(ctx->opcode);
3148 TCGv gpr1, gpr2;
3149
3150 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3151 (rd == rB(ctx->opcode)))) {
3152 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3153 return;
3154 }
3155
3156 gen_set_access_type(ctx, ACCESS_RES);
3157 EA = tcg_temp_local_new();
3158 gen_addr_reg_index(ctx, EA);
3159 gen_check_align(ctx, EA, 15);
3160 if (unlikely(ctx->le_mode)) {
3161 gpr1 = cpu_gpr[rd+1];
3162 gpr2 = cpu_gpr[rd];
3163 } else {
3164 gpr1 = cpu_gpr[rd];
3165 gpr2 = cpu_gpr[rd+1];
3166 }
3167 gen_qemu_ld64(ctx, gpr1, EA);
3168 tcg_gen_mov_tl(cpu_reserve, EA);
3169
3170 gen_addr_add(ctx, EA, EA, 8);
3171 gen_qemu_ld64(ctx, gpr2, EA);
3172
3173 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3174 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3175
3176 tcg_temp_free(EA);
3177 }
3178
3179 /* stdcx. */
3180 STCX(stdcx_, 8);
3181 STCX(stqcx_, 16);
3182 #endif /* defined(TARGET_PPC64) */
3183
3184 /* sync */
3185 static void gen_sync(DisasContext *ctx)
3186 {
3187 uint32_t l = (ctx->opcode >> 21) & 3;
3188
3189 /*
3190 * We may need to check for a pending TLB flush.
3191 *
3192 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3193 *
3194 * Additionally, this can only happen in kernel mode however so
3195 * check MSR_PR as well.
3196 */
3197 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3198 gen_check_tlb_flush(ctx);
3199 }
3200 }
3201
3202 /* wait */
3203 static void gen_wait(DisasContext *ctx)
3204 {
3205 TCGv_i32 t0 = tcg_const_i32(1);
3206 tcg_gen_st_i32(t0, cpu_env,
3207 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3208 tcg_temp_free_i32(t0);
3209 /* Stop translation, as the CPU is supposed to sleep from now */
3210 gen_exception_err(ctx, EXCP_HLT, 1);
3211 }
3212
3213 #if defined(TARGET_PPC64)
3214 static void gen_doze(DisasContext *ctx)
3215 {
3216 #if defined(CONFIG_USER_ONLY)
3217 GEN_PRIV;
3218 #else
3219 TCGv_i32 t;
3220
3221 CHK_HV;
3222 t = tcg_const_i32(PPC_PM_DOZE);
3223 gen_helper_pminsn(cpu_env, t);
3224 tcg_temp_free_i32(t);
3225 gen_stop_exception(ctx);
3226 #endif /* defined(CONFIG_USER_ONLY) */
3227 }
3228
3229 static void gen_nap(DisasContext *ctx)
3230 {
3231 #if defined(CONFIG_USER_ONLY)
3232 GEN_PRIV;
3233 #else
3234 TCGv_i32 t;
3235
3236 CHK_HV;
3237 t = tcg_const_i32(PPC_PM_NAP);
3238 gen_helper_pminsn(cpu_env, t);
3239 tcg_temp_free_i32(t);
3240 gen_stop_exception(ctx);
3241 #endif /* defined(CONFIG_USER_ONLY) */
3242 }
3243
3244 static void gen_sleep(DisasContext *ctx)
3245 {
3246 #if defined(CONFIG_USER_ONLY)
3247 GEN_PRIV;
3248 #else
3249 TCGv_i32 t;
3250
3251 CHK_HV;
3252 t = tcg_const_i32(PPC_PM_SLEEP);
3253 gen_helper_pminsn(cpu_env, t);
3254 tcg_temp_free_i32(t);
3255 gen_stop_exception(ctx);
3256 #endif /* defined(CONFIG_USER_ONLY) */
3257 }
3258
3259 static void gen_rvwinkle(DisasContext *ctx)
3260 {
3261 #if defined(CONFIG_USER_ONLY)
3262 GEN_PRIV;
3263 #else
3264 TCGv_i32 t;
3265
3266 CHK_HV;
3267 t = tcg_const_i32(PPC_PM_RVWINKLE);
3268 gen_helper_pminsn(cpu_env, t);
3269 tcg_temp_free_i32(t);
3270 gen_stop_exception(ctx);
3271 #endif /* defined(CONFIG_USER_ONLY) */
3272 }
3273 #endif /* #if defined(TARGET_PPC64) */
3274
3275 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3276 {
3277 #if defined(TARGET_PPC64)
3278 if (ctx->has_cfar)
3279 tcg_gen_movi_tl(cpu_cfar, nip);
3280 #endif
3281 }
3282
3283 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3284 {
3285 if (unlikely(ctx->singlestep_enabled)) {
3286 return false;
3287 }
3288
3289 #ifndef CONFIG_USER_ONLY
3290 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3291 #else
3292 return true;
3293 #endif
3294 }
3295
3296 /*** Branch ***/
3297 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3298 {
3299 if (NARROW_MODE(ctx)) {
3300 dest = (uint32_t) dest;
3301 }
3302 if (use_goto_tb(ctx, dest)) {
3303 tcg_gen_goto_tb(n);
3304 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3305 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
3306 } else {
3307 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3308 if (unlikely(ctx->singlestep_enabled)) {
3309 if ((ctx->singlestep_enabled &
3310 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3311 (ctx->exception == POWERPC_EXCP_BRANCH ||
3312 ctx->exception == POWERPC_EXCP_TRACE)) {
3313 target_ulong tmp = ctx->nip;
3314 ctx->nip = dest;
3315 gen_exception(ctx, POWERPC_EXCP_TRACE);
3316 ctx->nip = tmp;
3317 }
3318 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3319 gen_debug_exception(ctx);
3320 }
3321 }
3322 tcg_gen_exit_tb(0);
3323 }
3324 }
3325
3326 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3327 {
3328 if (NARROW_MODE(ctx)) {
3329 nip = (uint32_t)nip;
3330 }
3331 tcg_gen_movi_tl(cpu_lr, nip);
3332 }
3333
3334 /* b ba bl bla */
3335 static void gen_b(DisasContext *ctx)
3336 {
3337 target_ulong li, target;
3338
3339 ctx->exception = POWERPC_EXCP_BRANCH;
3340 /* sign extend LI */
3341 li = LI(ctx->opcode);
3342 li = (li ^ 0x02000000) - 0x02000000;
3343 if (likely(AA(ctx->opcode) == 0)) {
3344 target = ctx->nip + li - 4;
3345 } else {
3346 target = li;
3347 }
3348 if (LK(ctx->opcode)) {
3349 gen_setlr(ctx, ctx->nip);
3350 }
3351 gen_update_cfar(ctx, ctx->nip);
3352 gen_goto_tb(ctx, 0, target);
3353 }
3354
3355 #define BCOND_IM 0
3356 #define BCOND_LR 1
3357 #define BCOND_CTR 2
3358 #define BCOND_TAR 3
3359
3360 static inline void gen_bcond(DisasContext *ctx, int type)
3361 {
3362 uint32_t bo = BO(ctx->opcode);
3363 TCGLabel *l1;
3364 TCGv target;
3365
3366 ctx->exception = POWERPC_EXCP_BRANCH;
3367 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3368 target = tcg_temp_local_new();
3369 if (type == BCOND_CTR)
3370 tcg_gen_mov_tl(target, cpu_ctr);
3371 else if (type == BCOND_TAR)
3372 gen_load_spr(target, SPR_TAR);
3373 else
3374 tcg_gen_mov_tl(target, cpu_lr);
3375 } else {
3376 TCGV_UNUSED(target);
3377 }
3378 if (LK(ctx->opcode))
3379 gen_setlr(ctx, ctx->nip);
3380 l1 = gen_new_label();
3381 if ((bo & 0x4) == 0) {
3382 /* Decrement and test CTR */
3383 TCGv temp = tcg_temp_new();
3384 if (unlikely(type == BCOND_CTR)) {
3385 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3386 return;
3387 }
3388 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3389 if (NARROW_MODE(ctx)) {
3390 tcg_gen_ext32u_tl(temp, cpu_ctr);
3391 } else {
3392 tcg_gen_mov_tl(temp, cpu_ctr);
3393 }
3394 if (bo & 0x2) {
3395 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3396 } else {
3397 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3398 }
3399 tcg_temp_free(temp);
3400 }
3401 if ((bo & 0x10) == 0) {
3402 /* Test CR */
3403 uint32_t bi = BI(ctx->opcode);
3404 uint32_t mask = 0x08 >> (bi & 0x03);
3405 TCGv_i32 temp = tcg_temp_new_i32();
3406
3407 if (bo & 0x8) {
3408 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3409 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3410 } else {
3411 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3412 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3413 }
3414 tcg_temp_free_i32(temp);
3415 }
3416 gen_update_cfar(ctx, ctx->nip);
3417 if (type == BCOND_IM) {
3418 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3419 if (likely(AA(ctx->opcode) == 0)) {
3420 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3421 } else {
3422 gen_goto_tb(ctx, 0, li);
3423 }
3424 gen_set_label(l1);
3425 gen_goto_tb(ctx, 1, ctx->nip);
3426 } else {
3427 if (NARROW_MODE(ctx)) {
3428 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3429 } else {
3430 tcg_gen_andi_tl(cpu_nip, target, ~3);
3431 }
3432 tcg_gen_exit_tb(0);
3433 gen_set_label(l1);
3434 gen_update_nip(ctx, ctx->nip);
3435 tcg_gen_exit_tb(0);
3436 }
3437 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3438 tcg_temp_free(target);
3439 }
3440 }
3441
3442 static void gen_bc(DisasContext *ctx)
3443 {
3444 gen_bcond(ctx, BCOND_IM);
3445 }
3446
3447 static void gen_bcctr(DisasContext *ctx)
3448 {
3449 gen_bcond(ctx, BCOND_CTR);
3450 }
3451
3452 static void gen_bclr(DisasContext *ctx)
3453 {
3454 gen_bcond(ctx, BCOND_LR);
3455 }
3456
3457 static void gen_bctar(DisasContext *ctx)
3458 {
3459 gen_bcond(ctx, BCOND_TAR);
3460 }
3461
3462 /*** Condition register logical ***/
3463 #define GEN_CRLOGIC(name, tcg_op, opc) \
3464 static void glue(gen_, name)(DisasContext *ctx) \
3465 { \
3466 uint8_t bitmask; \
3467 int sh; \
3468 TCGv_i32 t0, t1; \
3469 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3470 t0 = tcg_temp_new_i32(); \
3471 if (sh > 0) \
3472 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3473 else if (sh < 0) \
3474 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3475 else \
3476 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3477 t1 = tcg_temp_new_i32(); \
3478 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3479 if (sh > 0) \
3480 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3481 else if (sh < 0) \
3482 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3483 else \
3484 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3485 tcg_op(t0, t0, t1); \
3486 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3487 tcg_gen_andi_i32(t0, t0, bitmask); \
3488 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3489 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3490 tcg_temp_free_i32(t0); \
3491 tcg_temp_free_i32(t1); \
3492 }
3493
3494 /* crand */
3495 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3496 /* crandc */
3497 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3498 /* creqv */
3499 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3500 /* crnand */
3501 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3502 /* crnor */
3503 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3504 /* cror */
3505 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3506 /* crorc */
3507 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3508 /* crxor */
3509 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3510
3511 /* mcrf */
3512 static void gen_mcrf(DisasContext *ctx)
3513 {
3514 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3515 }
3516
3517 /*** System linkage ***/
3518
3519 /* rfi (supervisor only) */
3520 static void gen_rfi(DisasContext *ctx)
3521 {
3522 #if defined(CONFIG_USER_ONLY)
3523 GEN_PRIV;
3524 #else
3525 /* FIXME: This instruction doesn't exist anymore on 64-bit server
3526 * processors compliant with arch 2.x, we should remove it there,
3527 * but we need to fix OpenBIOS not to use it on 970 first
3528 */
3529 /* Restore CPU state */
3530 CHK_SV;
3531 gen_update_cfar(ctx, ctx->nip);
3532 gen_helper_rfi(cpu_env);
3533 gen_sync_exception(ctx);
3534 #endif
3535 }
3536
3537 #if defined(TARGET_PPC64)
3538 static void gen_rfid(DisasContext *ctx)
3539 {
3540 #if defined(CONFIG_USER_ONLY)
3541 GEN_PRIV;
3542 #else
3543 /* Restore CPU state */
3544 CHK_SV;
3545 gen_update_cfar(ctx, ctx->nip);
3546 gen_helper_rfid(cpu_env);
3547 gen_sync_exception(ctx);
3548 #endif
3549 }
3550
3551 static void gen_hrfid(DisasContext *ctx)
3552 {
3553 #if defined(CONFIG_USER_ONLY)
3554 GEN_PRIV;
3555 #else
3556 /* Restore CPU state */
3557 CHK_HV;
3558 gen_helper_hrfid(cpu_env);
3559 gen_sync_exception(ctx);
3560 #endif
3561 }
3562 #endif
3563
3564 /* sc */
3565 #if defined(CONFIG_USER_ONLY)
3566 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3567 #else
3568 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3569 #endif
3570 static void gen_sc(DisasContext *ctx)
3571 {
3572 uint32_t lev;
3573
3574 lev = (ctx->opcode >> 5) & 0x7F;
3575 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3576 }
3577
3578 /*** Trap ***/
3579
3580 /* tw */
3581 static void gen_tw(DisasContext *ctx)
3582 {
3583 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3584 /* Update the nip since this might generate a trap exception */
3585 gen_update_nip(ctx, ctx->nip);
3586 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3587 t0);
3588 tcg_temp_free_i32(t0);
3589 }
3590
3591 /* twi */
3592 static void gen_twi(DisasContext *ctx)
3593 {
3594 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3595 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3596 /* Update the nip since this might generate a trap exception */
3597 gen_update_nip(ctx, ctx->nip);
3598 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3599 tcg_temp_free(t0);
3600 tcg_temp_free_i32(t1);
3601 }
3602
3603 #if defined(TARGET_PPC64)
3604 /* td */
3605 static void gen_td(DisasContext *ctx)
3606 {
3607 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3608 /* Update the nip since this might generate a trap exception */
3609 gen_update_nip(ctx, ctx->nip);
3610 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3611 t0);
3612 tcg_temp_free_i32(t0);
3613 }
3614
3615 /* tdi */
3616 static void gen_tdi(DisasContext *ctx)
3617 {
3618 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3619 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3620 /* Update the nip since this might generate a trap exception */
3621 gen_update_nip(ctx, ctx->nip);
3622 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3623 tcg_temp_free(t0);
3624 tcg_temp_free_i32(t1);
3625 }
3626 #endif
3627
3628 /*** Processor control ***/
3629
3630 static void gen_read_xer(TCGv dst)
3631 {
3632 TCGv t0 = tcg_temp_new();
3633 TCGv t1 = tcg_temp_new();
3634 TCGv t2 = tcg_temp_new();
3635 tcg_gen_mov_tl(dst, cpu_xer);
3636 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3637 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3638 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3639 tcg_gen_or_tl(t0, t0, t1);
3640 tcg_gen_or_tl(dst, dst, t2);
3641 tcg_gen_or_tl(dst, dst, t0);
3642 tcg_temp_free(t0);
3643 tcg_temp_free(t1);
3644 tcg_temp_free(t2);
3645 }
3646
3647 static void gen_write_xer(TCGv src)
3648 {
3649 tcg_gen_andi_tl(cpu_xer, src,
3650 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3651 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3652 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3653 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3654 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3655 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3656 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3657 }
3658
3659 /* mcrxr */
3660 static void gen_mcrxr(DisasContext *ctx)
3661 {
3662 TCGv_i32 t0 = tcg_temp_new_i32();
3663 TCGv_i32 t1 = tcg_temp_new_i32();
3664 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3665
3666 tcg_gen_trunc_tl_i32(t0, cpu_so);
3667 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3668 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3669 tcg_gen_shli_i32(t0, t0, 3);
3670 tcg_gen_shli_i32(t1, t1, 2);
3671 tcg_gen_shli_i32(dst, dst, 1);
3672 tcg_gen_or_i32(dst, dst, t0);
3673 tcg_gen_or_i32(dst, dst, t1);
3674 tcg_temp_free_i32(t0);
3675 tcg_temp_free_i32(t1);
3676
3677 tcg_gen_movi_tl(cpu_so, 0);
3678 tcg_gen_movi_tl(cpu_ov, 0);
3679 tcg_gen_movi_tl(cpu_ca, 0);
3680 }
3681
3682 /* mfcr mfocrf */
3683 static void gen_mfcr(DisasContext *ctx)
3684 {
3685 uint32_t crm, crn;
3686
3687 if (likely(ctx->opcode & 0x00100000)) {
3688 crm = CRM(ctx->opcode);
3689 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3690 crn = ctz32 (crm);
3691 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3692 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3693 cpu_gpr[rD(ctx->opcode)], crn * 4);
3694 }
3695 } else {
3696 TCGv_i32 t0 = tcg_temp_new_i32();
3697 tcg_gen_mov_i32(t0, cpu_crf[0]);
3698 tcg_gen_shli_i32(t0, t0, 4);
3699 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3700 tcg_gen_shli_i32(t0, t0, 4);
3701 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3702 tcg_gen_shli_i32(t0, t0, 4);
3703 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3704 tcg_gen_shli_i32(t0, t0, 4);
3705 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3706 tcg_gen_shli_i32(t0, t0, 4);
3707 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3708 tcg_gen_shli_i32(t0, t0, 4);
3709 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3710 tcg_gen_shli_i32(t0, t0, 4);
3711 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3712 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3713 tcg_temp_free_i32(t0);
3714 }
3715 }
3716
3717 /* mfmsr */
3718 static void gen_mfmsr(DisasContext *ctx)
3719 {
3720 CHK_SV;
3721 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3722 }
3723
3724 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
3725 {
3726 #if 0
3727 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3728 printf("ERROR: try to access SPR %d !\n", sprn);
3729 #endif
3730 }
3731 #define SPR_NOACCESS (&spr_noaccess)
3732
3733 /* mfspr */
3734 static inline void gen_op_mfspr(DisasContext *ctx)
3735 {
3736 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
3737 uint32_t sprn = SPR(ctx->opcode);
3738
3739 #if defined(CONFIG_USER_ONLY)
3740 read_cb = ctx->spr_cb[sprn].uea_read;
3741 #else
3742 if (ctx->pr) {
3743 read_cb = ctx->spr_cb[sprn].uea_read;
3744 } else if (ctx->hv) {
3745 read_cb = ctx->spr_cb[sprn].hea_read;
3746 } else {
3747 read_cb = ctx->spr_cb[sprn].oea_read;
3748 }
3749 #endif
3750 if (likely(read_cb != NULL)) {
3751 if (likely(read_cb != SPR_NOACCESS)) {
3752 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3753 } else {
3754 /* Privilege exception */
3755 /* This is a hack to avoid warnings when running Linux:
3756 * this OS breaks the PowerPC virtualisation model,
3757 * allowing userland application to read the PVR
3758 */
3759 if (sprn != SPR_PVR) {
3760 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
3761 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3762 if (qemu_log_separate()) {
3763 qemu_log("Trying to read privileged spr %d (0x%03x) at "
3764 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3765 }
3766 }
3767 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
3768 }
3769 } else {
3770 /* ISA 2.07 defines these as no-ops */
3771 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
3772 (sprn >= 808 && sprn <= 811)) {
3773 /* This is a nop */
3774 return;
3775 }
3776 /* Not defined */
3777 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
3778 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3779 if (qemu_log_separate()) {
3780 qemu_log("Trying to read invalid spr %d (0x%03x) at "
3781 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3782 }
3783
3784 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3785 * it can generate a priv, a hv emu or a no-op
3786 */
3787 if (sprn & 0x10) {
3788 if (ctx->pr) {
3789 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3790 }
3791 } else {
3792 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
3793 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3794 }
3795 }
3796 }
3797 }
3798
3799 static void gen_mfspr(DisasContext *ctx)
3800 {
3801 gen_op_mfspr(ctx);
3802 }
3803
3804 /* mftb */
3805 static void gen_mftb(DisasContext *ctx)
3806 {
3807 gen_op_mfspr(ctx);
3808 }
3809
3810 /* mtcrf mtocrf*/
3811 static void gen_mtcrf(DisasContext *ctx)
3812 {
3813 uint32_t crm, crn;
3814
3815 crm = CRM(ctx->opcode);
3816 if (likely((ctx->opcode & 0x00100000))) {
3817 if (crm && ((crm & (crm - 1)) == 0)) {
3818 TCGv_i32 temp = tcg_temp_new_i32();
3819 crn = ctz32 (crm);
3820 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3821 tcg_gen_shri_i32(temp, temp, crn * 4);
3822 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3823 tcg_temp_free_i32(temp);
3824 }
3825 } else {
3826 TCGv_i32 temp = tcg_temp_new_i32();
3827 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3828 for (crn = 0 ; crn < 8 ; crn++) {
3829 if (crm & (1 << crn)) {
3830 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3831 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3832 }
3833 }
3834 tcg_temp_free_i32(temp);
3835 }
3836 }
3837
3838 /* mtmsr */
3839 #if defined(TARGET_PPC64)
3840 static void gen_mtmsrd(DisasContext *ctx)
3841 {
3842 CHK_SV;
3843
3844 #if !defined(CONFIG_USER_ONLY)
3845 if (ctx->opcode & 0x00010000) {
3846 /* Special form that does not need any synchronisation */
3847 TCGv t0 = tcg_temp_new();
3848 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3849 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
3850 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3851 tcg_temp_free(t0);
3852 } else {
3853 /* XXX: we need to update nip before the store
3854 * if we enter power saving mode, we will exit the loop
3855 * directly from ppc_store_msr
3856 */
3857 gen_update_nip(ctx, ctx->nip);
3858 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3859 /* Must stop the translation as machine state (may have) changed */
3860 /* Note that mtmsr is not always defined as context-synchronizing */
3861 gen_stop_exception(ctx);
3862 }
3863 #endif /* !defined(CONFIG_USER_ONLY) */
3864 }
3865 #endif /* defined(TARGET_PPC64) */
3866
3867 static void gen_mtmsr(DisasContext *ctx)
3868 {
3869 CHK_SV;
3870
3871 #if !defined(CONFIG_USER_ONLY)
3872 if (ctx->opcode & 0x00010000) {
3873 /* Special form that does not need any synchronisation */
3874 TCGv t0 = tcg_temp_new();
3875 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3876 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
3877 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3878 tcg_temp_free(t0);
3879 } else {
3880 TCGv msr = tcg_temp_new();
3881
3882 /* XXX: we need to update nip before the store
3883 * if we enter power saving mode, we will exit the loop
3884 * directly from ppc_store_msr
3885 */
3886 gen_update_nip(ctx, ctx->nip);
3887 #if defined(TARGET_PPC64)
3888 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3889 #else
3890 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3891 #endif
3892 gen_helper_store_msr(cpu_env, msr);
3893 tcg_temp_free(msr);
3894 /* Must stop the translation as machine state (may have) changed */
3895 /* Note that mtmsr is not always defined as context-synchronizing */
3896 gen_stop_exception(ctx);
3897 }
3898 #endif
3899 }
3900
3901 /* mtspr */
3902 static void gen_mtspr(DisasContext *ctx)
3903 {
3904 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
3905 uint32_t sprn = SPR(ctx->opcode);
3906
3907 #if defined(CONFIG_USER_ONLY)
3908 write_cb = ctx->spr_cb[sprn].uea_write;
3909 #else
3910 if (ctx->pr) {
3911 write_cb = ctx->spr_cb[sprn].uea_write;
3912 } else if (ctx->hv) {
3913 write_cb = ctx->spr_cb[sprn].hea_write;
3914 } else {
3915 write_cb = ctx->spr_cb[sprn].oea_write;
3916 }
3917 #endif
3918 if (likely(write_cb != NULL)) {
3919 if (likely(write_cb != SPR_NOACCESS)) {
3920 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3921 } else {
3922 /* Privilege exception */
3923 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
3924 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3925 if (qemu_log_separate()) {
3926 qemu_log("Trying to write privileged spr %d (0x%03x) at "
3927 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3928 }
3929 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
3930 }
3931 } else {
3932 /* ISA 2.07 defines these as no-ops */
3933 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
3934 (sprn >= 808 && sprn <= 811)) {
3935 /* This is a nop */
3936 return;
3937 }
3938
3939 /* Not defined */
3940 if (qemu_log_separate()) {
3941 qemu_log("Trying to write invalid spr %d (0x%03x) at "
3942 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3943 }
3944 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
3945 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3946
3947
3948 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3949 * it can generate a priv, a hv emu or a no-op
3950 */
3951 if (sprn & 0x10) {
3952 if (ctx->pr) {
3953 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3954 }
3955 } else {
3956 if (ctx->pr || sprn == 0) {
3957 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3958 }
3959 }
3960 }
3961 }
3962
3963 #if defined(TARGET_PPC64)
3964 /* setb */
3965 static void gen_setb(DisasContext *ctx)
3966 {
3967 TCGv_i32 t0 = tcg_temp_new_i32();
3968 TCGv_i32 t8 = tcg_temp_new_i32();
3969 TCGv_i32 tm1 = tcg_temp_new_i32();
3970 int crf = crfS(ctx->opcode);
3971
3972 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
3973 tcg_gen_movi_i32(t8, 8);
3974 tcg_gen_movi_i32(tm1, -1);
3975 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
3976 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3977
3978 tcg_temp_free_i32(t0);
3979 tcg_temp_free_i32(t8);
3980 tcg_temp_free_i32(tm1);
3981 }
3982 #endif
3983
3984 /*** Cache management ***/
3985
3986 /* dcbf */
3987 static void gen_dcbf(DisasContext *ctx)
3988 {
3989 /* XXX: specification says this is treated as a load by the MMU */
3990 TCGv t0;
3991 gen_set_access_type(ctx, ACCESS_CACHE);
3992 t0 = tcg_temp_new();
3993 gen_addr_reg_index(ctx, t0);
3994 gen_qemu_ld8u(ctx, t0, t0);
3995 tcg_temp_free(t0);
3996 }
3997
3998 /* dcbi (Supervisor only) */
3999 static void gen_dcbi(DisasContext *ctx)
4000 {
4001 #if defined(CONFIG_USER_ONLY)
4002 GEN_PRIV;
4003 #else
4004 TCGv EA, val;
4005
4006 CHK_SV;
4007 EA = tcg_temp_new();
4008 gen_set_access_type(ctx, ACCESS_CACHE);
4009 gen_addr_reg_index(ctx, EA);
4010 val = tcg_temp_new();
4011 /* XXX: specification says this should be treated as a store by the MMU */
4012 gen_qemu_ld8u(ctx, val, EA);
4013 gen_qemu_st8(ctx, val, EA);
4014 tcg_temp_free(val);
4015 tcg_temp_free(EA);
4016 #endif /* defined(CONFIG_USER_ONLY) */
4017 }
4018
4019 /* dcdst */
4020 static void gen_dcbst(DisasContext *ctx)
4021 {
4022 /* XXX: specification say this is treated as a load by the MMU */
4023 TCGv t0;
4024 gen_set_access_type(ctx, ACCESS_CACHE);
4025 t0 = tcg_temp_new();
4026 gen_addr_reg_index(ctx, t0);
4027 gen_qemu_ld8u(ctx, t0, t0);
4028 tcg_temp_free(t0);
4029 }
4030
4031 /* dcbt */
4032 static void gen_dcbt(DisasContext *ctx)
4033 {
4034 /* interpreted as no-op */
4035 /* XXX: specification say this is treated as a load by the MMU
4036 * but does not generate any exception
4037 */
4038 }
4039
4040 /* dcbtst */
4041 static void gen_dcbtst(DisasContext *ctx)
4042 {
4043 /* interpreted as no-op */
4044 /* XXX: specification say this is treated as a load by the MMU
4045 * but does not generate any exception
4046 */
4047 }
4048
4049 /* dcbtls */
4050 static void gen_dcbtls(DisasContext *ctx)
4051 {
4052 /* Always fails locking the cache */
4053 TCGv t0 = tcg_temp_new();
4054 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4055 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4056 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4057 tcg_temp_free(t0);
4058 }
4059
4060 /* dcbz */
4061 static void gen_dcbz(DisasContext *ctx)
4062 {
4063 TCGv tcgv_addr;
4064 TCGv_i32 tcgv_is_dcbzl;
4065 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4066
4067 gen_set_access_type(ctx, ACCESS_CACHE);
4068 /* NIP cannot be restored if the memory exception comes from an helper */
4069 gen_update_nip(ctx, ctx->nip - 4);
4070 tcgv_addr = tcg_temp_new();
4071 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4072
4073 gen_addr_reg_index(ctx, tcgv_addr);
4074 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4075
4076 tcg_temp_free(tcgv_addr);
4077 tcg_temp_free_i32(tcgv_is_dcbzl);
4078 }
4079
4080 /* dst / dstt */
4081 static void gen_dst(DisasContext *ctx)
4082 {
4083 if (rA(ctx->opcode) == 0) {
4084 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4085 } else {
4086 /* interpreted as no-op */
4087 }
4088 }
4089
4090 /* dstst /dststt */
4091 static void gen_dstst(DisasContext *ctx)
4092 {
4093 if (rA(ctx->opcode) == 0) {
4094 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4095 } else {
4096 /* interpreted as no-op */
4097 }
4098
4099 }
4100
4101 /* dss / dssall */
4102 static void gen_dss(DisasContext *ctx)
4103 {
4104 /* interpreted as no-op */
4105 }
4106
4107 /* icbi */
4108 static void gen_icbi(DisasContext *ctx)
4109 {
4110 TCGv t0;
4111 gen_set_access_type(ctx, ACCESS_CACHE);
4112 /* NIP cannot be restored if the memory exception comes from an helper */
4113 gen_update_nip(ctx, ctx->nip - 4);
4114 t0 = tcg_temp_new();
4115 gen_addr_reg_index(ctx, t0);
4116 gen_helper_icbi(cpu_env, t0);
4117 tcg_temp_free(t0);
4118 }
4119
4120 /* Optional: */
4121 /* dcba */
4122 static void gen_dcba(DisasContext *ctx)
4123 {
4124 /* interpreted as no-op */
4125 /* XXX: specification say this is treated as a store by the MMU
4126 * but does not generate any exception
4127 */
4128 }
4129
4130 /*** Segment register manipulation ***/
4131 /* Supervisor only: */
4132
4133 /* mfsr */
4134 static void gen_mfsr(DisasContext *ctx)
4135 {
4136 #if defined(CONFIG_USER_ONLY)
4137 GEN_PRIV;
4138 #else
4139 TCGv t0;
4140
4141 CHK_SV;
4142 t0 = tcg_const_tl(SR(ctx->opcode));
4143 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4144 tcg_temp_free(t0);
4145 #endif /* defined(CONFIG_USER_ONLY) */
4146 }
4147
4148 /* mfsrin */
4149 static void gen_mfsrin(DisasContext *ctx)
4150 {
4151 #if defined(CONFIG_USER_ONLY)
4152 GEN_PRIV;
4153 #else
4154 TCGv t0;
4155
4156 CHK_SV;
4157 t0 = tcg_temp_new();
4158 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4159 tcg_gen_andi_tl(t0, t0, 0xF);
4160 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4161 tcg_temp_free(t0);
4162 #endif /* defined(CONFIG_USER_ONLY) */
4163 }
4164
4165 /* mtsr */
4166 static void gen_mtsr(DisasContext *ctx)
4167 {
4168 #if defined(CONFIG_USER_ONLY)
4169 GEN_PRIV;
4170 #else
4171 TCGv t0;
4172
4173 CHK_SV;
4174 t0 = tcg_const_tl(SR(ctx->opcode));
4175 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4176 tcg_temp_free(t0);
4177 #endif /* defined(CONFIG_USER_ONLY) */
4178 }
4179
4180 /* mtsrin */
4181 static void gen_mtsrin(DisasContext *ctx)
4182 {
4183 #if defined(CONFIG_USER_ONLY)
4184 GEN_PRIV;
4185 #else
4186 TCGv t0;
4187 CHK_SV;
4188
4189 t0 = tcg_temp_new();
4190 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4191 tcg_gen_andi_tl(t0, t0, 0xF);
4192 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4193 tcg_temp_free(t0);
4194 #endif /* defined(CONFIG_USER_ONLY) */
4195 }
4196
4197 #if defined(TARGET_PPC64)
4198 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4199
4200 /* mfsr */
4201 static void gen_mfsr_64b(DisasContext *ctx)
4202 {
4203 #if defined(CONFIG_USER_ONLY)
4204 GEN_PRIV;
4205 #else
4206 TCGv t0;
4207
4208 CHK_SV;
4209 t0 = tcg_const_tl(SR(ctx->opcode));
4210 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4211 tcg_temp_free(t0);
4212 #endif /* defined(CONFIG_USER_ONLY) */
4213 }
4214
4215 /* mfsrin */
4216 static void gen_mfsrin_64b(DisasContext *ctx)
4217 {
4218 #if defined(CONFIG_USER_ONLY)
4219 GEN_PRIV;
4220 #else
4221 TCGv t0;
4222
4223 CHK_SV;
4224 t0 = tcg_temp_new();
4225 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4226 tcg_gen_andi_tl(t0, t0, 0xF);
4227 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4228 tcg_temp_free(t0);
4229 #endif /* defined(CONFIG_USER_ONLY) */
4230 }
4231
4232 /* mtsr */
4233 static void gen_mtsr_64b(DisasContext *ctx)
4234 {
4235 #if defined(CONFIG_USER_ONLY)
4236 GEN_PRIV;
4237 #else
4238 TCGv t0;
4239
4240 CHK_SV;
4241 t0 = tcg_const_tl(SR(ctx->opcode));
4242 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4243 tcg_temp_free(t0);
4244 #endif /* defined(CONFIG_USER_ONLY) */
4245 }
4246
4247 /* mtsrin */
4248 static void gen_mtsrin_64b(DisasContext *ctx)
4249 {
4250 #if defined(CONFIG_USER_ONLY)
4251 GEN_PRIV;
4252 #else
4253 TCGv t0;
4254
4255 CHK_SV;
4256 t0 = tcg_temp_new();
4257 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4258 tcg_gen_andi_tl(t0, t0, 0xF);
4259 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4260 tcg_temp_free(t0);
4261 #endif /* defined(CONFIG_USER_ONLY) */
4262 }
4263
4264 /* slbmte */
4265 static void gen_slbmte(DisasContext *ctx)
4266 {
4267 #if defined(CONFIG_USER_ONLY)
4268 GEN_PRIV;
4269 #else
4270 CHK_SV;
4271
4272 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4273 cpu_gpr[rS(ctx->opcode)]);
4274 #endif /* defined(CONFIG_USER_ONLY) */
4275 }
4276
4277 static void gen_slbmfee(DisasContext *ctx)
4278 {
4279 #if defined(CONFIG_USER_ONLY)
4280 GEN_PRIV;
4281 #else
4282 CHK_SV;
4283
4284 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4285 cpu_gpr[rB(ctx->opcode)]);
4286 #endif /* defined(CONFIG_USER_ONLY) */
4287 }
4288
4289 static void gen_slbmfev(DisasContext *ctx)
4290 {
4291 #if defined(CONFIG_USER_ONLY)
4292 GEN_PRIV;
4293 #else
4294 CHK_SV;
4295
4296 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4297 cpu_gpr[rB(ctx->opcode)]);
4298 #endif /* defined(CONFIG_USER_ONLY) */
4299 }
4300
4301 static void gen_slbfee_(DisasContext *ctx)
4302 {
4303 #if defined(CONFIG_USER_ONLY)
4304 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4305 #else
4306 TCGLabel *l1, *l2;
4307
4308 if (unlikely(ctx->pr)) {
4309 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4310 return;
4311 }
4312 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4313 cpu_gpr[rB(ctx->opcode)]);
4314 l1 = gen_new_label();
4315 l2 = gen_new_label();
4316 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4317 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4318 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
4319 tcg_gen_br(l2);
4320 gen_set_label(l1);
4321 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4322 gen_set_label(l2);
4323 #endif
4324 }
4325 #endif /* defined(TARGET_PPC64) */
4326
4327 /*** Lookaside buffer management ***/
4328 /* Optional & supervisor only: */
4329
4330 /* tlbia */
4331 static void gen_tlbia(DisasContext *ctx)
4332 {
4333 #if defined(CONFIG_USER_ONLY)
4334 GEN_PRIV;
4335 #else
4336 CHK_HV;
4337
4338 gen_helper_tlbia(cpu_env);
4339 #endif /* defined(CONFIG_USER_ONLY) */
4340 }
4341
4342 /* tlbiel */
4343 static void gen_tlbiel(DisasContext *ctx)
4344 {
4345 #if defined(CONFIG_USER_ONLY)
4346 GEN_PRIV;
4347 #else
4348 CHK_SV;
4349
4350 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4351 #endif /* defined(CONFIG_USER_ONLY) */
4352 }
4353
4354 /* tlbie */
4355 static void gen_tlbie(DisasContext *ctx)
4356 {
4357 #if defined(CONFIG_USER_ONLY)
4358 GEN_PRIV;
4359 #else
4360 CHK_HV;
4361
4362 if (NARROW_MODE(ctx)) {
4363 TCGv t0 = tcg_temp_new();
4364 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4365 gen_helper_tlbie(cpu_env, t0);
4366 tcg_temp_free(t0);
4367 } else {
4368 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4369 }
4370 #endif /* defined(CONFIG_USER_ONLY) */
4371 }
4372
4373 /* tlbsync */
4374 static void gen_tlbsync(DisasContext *ctx)
4375 {
4376 #if defined(CONFIG_USER_ONLY)
4377 GEN_PRIV;
4378 #else
4379 CHK_HV;
4380
4381 /* tlbsync is a nop for server, ptesync handles delayed tlb flush,
4382 * embedded however needs to deal with tlbsync. We don't try to be
4383 * fancy and swallow the overhead of checking for both.
4384 */
4385 gen_check_tlb_flush(ctx);
4386 #endif /* defined(CONFIG_USER_ONLY) */
4387 }
4388
4389 #if defined(TARGET_PPC64)
4390 /* slbia */
4391 static void gen_slbia(DisasContext *ctx)
4392 {
4393 #if defined(CONFIG_USER_ONLY)
4394 GEN_PRIV;
4395 #else
4396 CHK_SV;
4397
4398 gen_helper_slbia(cpu_env);
4399 #endif /* defined(CONFIG_USER_ONLY) */
4400 }
4401
4402 /* slbie */
4403 static void gen_slbie(DisasContext *ctx)
4404 {
4405 #if defined(CONFIG_USER_ONLY)
4406 GEN_PRIV;
4407 #else
4408 CHK_SV;
4409
4410 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4411 #endif /* defined(CONFIG_USER_ONLY) */
4412 }
4413 #endif /* defined(TARGET_PPC64) */
4414
4415 /*** External control ***/
4416 /* Optional: */
4417
4418 /* eciwx */
4419 static void gen_eciwx(DisasContext *ctx)
4420 {
4421 TCGv t0;
4422 /* Should check EAR[E] ! */
4423 gen_set_access_type(ctx, ACCESS_EXT);
4424 t0 = tcg_temp_new();
4425 gen_addr_reg_index(ctx, t0);
4426 gen_check_align(ctx, t0, 0x03);
4427 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4428 tcg_temp_free(t0);
4429 }
4430
4431 /* ecowx */
4432 static void gen_ecowx(DisasContext *ctx)
4433 {
4434 TCGv t0;
4435 /* Should check EAR[E] ! */
4436 gen_set_access_type(ctx, ACCESS_EXT);
4437 t0 = tcg_temp_new();
4438 gen_addr_reg_index(ctx, t0);
4439 gen_check_align(ctx, t0, 0x03);
4440 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4441 tcg_temp_free(t0);
4442 }
4443
4444 /* PowerPC 601 specific instructions */
4445
4446 /* abs - abs. */
4447 static void gen_abs(DisasContext *ctx)
4448 {
4449 TCGLabel *l1 = gen_new_label();
4450 TCGLabel *l2 = gen_new_label();
4451 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4452 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4453 tcg_gen_br(l2);
4454 gen_set_label(l1);
4455 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4456 gen_set_label(l2);
4457 if (unlikely(Rc(ctx->opcode) != 0))
4458 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4459 }
4460
4461 /* abso - abso. */
4462 static void gen_abso(DisasContext *ctx)
4463 {
4464 TCGLabel *l1 = gen_new_label();
4465 TCGLabel *l2 = gen_new_label();
4466 TCGLabel *l3 = gen_new_label();
4467 /* Start with XER OV disabled, the most likely case */
4468 tcg_gen_movi_tl(cpu_ov, 0);
4469 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4470 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4471 tcg_gen_movi_tl(cpu_ov, 1);
4472 tcg_gen_movi_tl(cpu_so, 1);
4473 tcg_gen_br(l2);
4474 gen_set_label(l1);
4475 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4476 tcg_gen_br(l3);
4477 gen_set_label(l2);
4478 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4479 gen_set_label(l3);
4480 if (unlikely(Rc(ctx->opcode) != 0))
4481 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4482 }
4483
4484 /* clcs */
4485 static void gen_clcs(DisasContext *ctx)
4486 {
4487 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4488 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4489 tcg_temp_free_i32(t0);
4490 /* Rc=1 sets CR0 to an undefined state */
4491 }
4492
4493 /* div - div. */
4494 static void gen_div(DisasContext *ctx)
4495 {
4496 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4497 cpu_gpr[rB(ctx->opcode)]);
4498 if (unlikely(Rc(ctx->opcode) != 0))
4499 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4500 }
4501
4502 /* divo - divo. */
4503 static void gen_divo(DisasContext *ctx)
4504 {
4505 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4506 cpu_gpr[rB(ctx->opcode)]);
4507 if (unlikely(Rc(ctx->opcode) != 0))
4508 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4509 }
4510
4511 /* divs - divs. */
4512 static void gen_divs(DisasContext *ctx)
4513 {
4514 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4515 cpu_gpr[rB(ctx->opcode)]);
4516 if (unlikely(Rc(ctx->opcode) != 0))
4517 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4518 }
4519
4520 /* divso - divso. */
4521 static void gen_divso(DisasContext *ctx)
4522 {
4523 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4524 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4525 if (unlikely(Rc(ctx->opcode) != 0))
4526 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4527 }
4528
4529 /* doz - doz. */
4530 static void gen_doz(DisasContext *ctx)
4531 {
4532 TCGLabel *l1 = gen_new_label();
4533 TCGLabel *l2 = gen_new_label();
4534 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4535 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4536 tcg_gen_br(l2);
4537 gen_set_label(l1);
4538 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4539 gen_set_label(l2);
4540 if (unlikely(Rc(ctx->opcode) != 0))
4541 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4542 }
4543
4544 /* dozo - dozo. */
4545 static void gen_dozo(DisasContext *ctx)
4546 {
4547 TCGLabel *l1 = gen_new_label();
4548 TCGLabel *l2 = gen_new_label();
4549 TCGv t0 = tcg_temp_new();
4550 TCGv t1 = tcg_temp_new();
4551 TCGv t2 = tcg_temp_new();
4552 /* Start with XER OV disabled, the most likely case */
4553 tcg_gen_movi_tl(cpu_ov, 0);
4554 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4555 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4556 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4557 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4558 tcg_gen_andc_tl(t1, t1, t2);
4559 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4560 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4561 tcg_gen_movi_tl(cpu_ov, 1);
4562 tcg_gen_movi_tl(cpu_so, 1);
4563 tcg_gen_br(l2);
4564 gen_set_label(l1);
4565 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4566 gen_set_label(l2);
4567 tcg_temp_free(t0);
4568 tcg_temp_free(t1);
4569 tcg_temp_free(t2);
4570 if (unlikely(Rc(ctx->opcode) != 0))
4571 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4572 }
4573
4574 /* dozi */
4575 static void gen_dozi(DisasContext *ctx)
4576 {
4577 target_long simm = SIMM(ctx->opcode);
4578 TCGLabel *l1 = gen_new_label();
4579 TCGLabel *l2 = gen_new_label();
4580 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4581 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4582 tcg_gen_br(l2);
4583 gen_set_label(l1);
4584 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4585 gen_set_label(l2);
4586 if (unlikely(Rc(ctx->opcode) != 0))
4587 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4588 }
4589
4590 /* lscbx - lscbx. */
4591 static void gen_lscbx(DisasContext *ctx)
4592 {
4593 TCGv t0 = tcg_temp_new();
4594 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4595 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4596 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4597
4598 gen_addr_reg_index(ctx, t0);
4599 /* NIP cannot be restored if the memory exception comes from an helper */
4600 gen_update_nip(ctx, ctx->nip - 4);
4601 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4602 tcg_temp_free_i32(t1);
4603 tcg_temp_free_i32(t2);
4604 tcg_temp_free_i32(t3);
4605 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4606 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4607 if (unlikely(Rc(ctx->opcode) != 0))
4608 gen_set_Rc0(ctx, t0);
4609 tcg_temp_free(t0);
4610 }
4611
4612 /* maskg - maskg. */
4613 static void gen_maskg(DisasContext *ctx)
4614 {
4615 TCGLabel *l1 = gen_new_label();
4616 TCGv t0 = tcg_temp_new();
4617 TCGv t1 = tcg_temp_new();
4618 TCGv t2 = tcg_temp_new();
4619 TCGv t3 = tcg_temp_new();
4620 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4621 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4622 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4623 tcg_gen_addi_tl(t2, t0, 1);
4624 tcg_gen_shr_tl(t2, t3, t2);
4625 tcg_gen_shr_tl(t3, t3, t1);
4626 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4627 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4628 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4629 gen_set_label(l1);
4630 tcg_temp_free(t0);
4631 tcg_temp_free(t1);
4632 tcg_temp_free(t2);
4633 tcg_temp_free(t3);
4634 if (unlikely(Rc(ctx->opcode) != 0))
4635 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4636 }
4637
4638 /* maskir - maskir. */
4639 static void gen_maskir(DisasContext *ctx)
4640 {
4641 TCGv t0 = tcg_temp_new();
4642 TCGv t1 = tcg_temp_new();
4643 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4644 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4645 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4646 tcg_temp_free(t0);
4647 tcg_temp_free(t1);
4648 if (unlikely(Rc(ctx->opcode) != 0))
4649 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4650 }
4651
4652 /* mul - mul. */
4653 static void gen_mul(DisasContext *ctx)
4654 {
4655 TCGv_i64 t0 = tcg_temp_new_i64();
4656 TCGv_i64 t1 = tcg_temp_new_i64();
4657 TCGv t2 = tcg_temp_new();
4658 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4659 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4660 tcg_gen_mul_i64(t0, t0, t1);
4661 tcg_gen_trunc_i64_tl(t2, t0);
4662 gen_store_spr(SPR_MQ, t2);
4663 tcg_gen_shri_i64(t1, t0, 32);
4664 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4665 tcg_temp_free_i64(t0);
4666 tcg_temp_free_i64(t1);
4667 tcg_temp_free(t2);
4668 if (unlikely(Rc(ctx->opcode) != 0))
4669 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4670 }
4671
4672 /* mulo - mulo. */
4673 static void gen_mulo(DisasContext *ctx)
4674 {
4675 TCGLabel *l1 = gen_new_label();
4676 TCGv_i64 t0 = tcg_temp_new_i64();
4677 TCGv_i64 t1 = tcg_temp_new_i64();
4678 TCGv t2 = tcg_temp_new();
4679 /* Start with XER OV disabled, the most likely case */
4680 tcg_gen_movi_tl(cpu_ov, 0);
4681 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4682 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4683 tcg_gen_mul_i64(t0, t0, t1);
4684 tcg_gen_trunc_i64_tl(t2, t0);
4685 gen_store_spr(SPR_MQ, t2);
4686 tcg_gen_shri_i64(t1, t0, 32);
4687 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4688 tcg_gen_ext32s_i64(t1, t0);
4689 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4690 tcg_gen_movi_tl(cpu_ov, 1);
4691 tcg_gen_movi_tl(cpu_so, 1);
4692 gen_set_label(l1);
4693 tcg_temp_free_i64(t0);
4694 tcg_temp_free_i64(t1);
4695 tcg_temp_free(t2);
4696 if (unlikely(Rc(ctx->opcode) != 0))
4697 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4698 }
4699
4700 /* nabs - nabs. */
4701 static void gen_nabs(DisasContext *ctx)
4702 {
4703 TCGLabel *l1 = gen_new_label();
4704 TCGLabel *l2 = gen_new_label();
4705 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4706 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4707 tcg_gen_br(l2);
4708 gen_set_label(l1);
4709 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4710 gen_set_label(l2);
4711 if (unlikely(Rc(ctx->opcode) != 0))
4712 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4713 }
4714
4715 /* nabso - nabso. */
4716 static void gen_nabso(DisasContext *ctx)
4717 {
4718 TCGLabel *l1 = gen_new_label();
4719 TCGLabel *l2 = gen_new_label();
4720 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4721 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4722 tcg_gen_br(l2);
4723 gen_set_label(l1);
4724 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4725 gen_set_label(l2);
4726 /* nabs never overflows */
4727 tcg_gen_movi_tl(cpu_ov, 0);
4728 if (unlikely(Rc(ctx->opcode) != 0))
4729 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4730 }
4731
4732 /* rlmi - rlmi. */
4733 static void gen_rlmi(DisasContext *ctx)
4734 {
4735 uint32_t mb = MB(ctx->opcode);
4736 uint32_t me = ME(ctx->opcode);
4737 TCGv t0 = tcg_temp_new();
4738 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4739 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4740 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4741 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4742 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4743 tcg_temp_free(t0);
4744 if (unlikely(Rc(ctx->opcode) != 0))
4745 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4746 }
4747
4748 /* rrib - rrib. */
4749 static void gen_rrib(DisasContext *ctx)
4750 {
4751 TCGv t0 = tcg_temp_new();
4752 TCGv t1 = tcg_temp_new();
4753 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4754 tcg_gen_movi_tl(t1, 0x80000000);
4755 tcg_gen_shr_tl(t1, t1, t0);
4756 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4757 tcg_gen_and_tl(t0, t0, t1);
4758 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4759 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4760 tcg_temp_free(t0);
4761 tcg_temp_free(t1);
4762 if (unlikely(Rc(ctx->opcode) != 0))
4763 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4764 }
4765
4766 /* sle - sle. */
4767 static void gen_sle(DisasContext *ctx)
4768 {
4769 TCGv t0 = tcg_temp_new();
4770 TCGv t1 = tcg_temp_new();
4771 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4772 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4773 tcg_gen_subfi_tl(t1, 32, t1);
4774 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4775 tcg_gen_or_tl(t1, t0, t1);
4776 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4777 gen_store_spr(SPR_MQ, t1);
4778 tcg_temp_free(t0);
4779 tcg_temp_free(t1);
4780 if (unlikely(Rc(ctx->opcode) != 0))
4781 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4782 }
4783
4784 /* sleq - sleq. */
4785 static void gen_sleq(DisasContext *ctx)
4786 {
4787 TCGv t0 = tcg_temp_new();
4788 TCGv t1 = tcg_temp_new();
4789 TCGv t2 = tcg_temp_new();
4790 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4791 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4792 tcg_gen_shl_tl(t2, t2, t0);
4793 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4794 gen_load_spr(t1, SPR_MQ);
4795 gen_store_spr(SPR_MQ, t0);
4796 tcg_gen_and_tl(t0, t0, t2);
4797 tcg_gen_andc_tl(t1, t1, t2);
4798 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4799 tcg_temp_free(t0);
4800 tcg_temp_free(t1);
4801 tcg_temp_free(t2);
4802 if (unlikely(Rc(ctx->opcode) != 0))
4803 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4804 }
4805
4806 /* sliq - sliq. */
4807 static void gen_sliq(DisasContext *ctx)
4808 {
4809 int sh = SH(ctx->opcode);
4810 TCGv t0 = tcg_temp_new();
4811 TCGv t1 = tcg_temp_new();
4812 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4813 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4814 tcg_gen_or_tl(t1, t0, t1);
4815 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4816 gen_store_spr(SPR_MQ, t1);
4817 tcg_temp_free(t0);
4818 tcg_temp_free(t1);
4819 if (unlikely(Rc(ctx->opcode) != 0))
4820 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4821 }
4822
4823 /* slliq - slliq. */
4824 static void gen_slliq(DisasContext *ctx)
4825 {
4826 int sh = SH(ctx->opcode);
4827 TCGv t0 = tcg_temp_new();
4828 TCGv t1 = tcg_temp_new();
4829 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4830 gen_load_spr(t1, SPR_MQ);
4831 gen_store_spr(SPR_MQ, t0);
4832 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4833 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4834 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4835 tcg_temp_free(t0);
4836 tcg_temp_free(t1);
4837 if (unlikely(Rc(ctx->opcode) != 0))
4838 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4839 }
4840
4841 /* sllq - sllq. */
4842 static void gen_sllq(DisasContext *ctx)
4843 {
4844 TCGLabel *l1 = gen_new_label();
4845 TCGLabel *l2 = gen_new_label();
4846 TCGv t0 = tcg_temp_local_new();
4847 TCGv t1 = tcg_temp_local_new();
4848 TCGv t2 = tcg_temp_local_new();
4849 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4850 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4851 tcg_gen_shl_tl(t1, t1, t2);
4852 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4853 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4854 gen_load_spr(t0, SPR_MQ);
4855 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4856 tcg_gen_br(l2);
4857 gen_set_label(l1);
4858 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4859 gen_load_spr(t2, SPR_MQ);
4860 tcg_gen_andc_tl(t1, t2, t1);
4861 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4862 gen_set_label(l2);
4863 tcg_temp_free(t0);
4864 tcg_temp_free(t1);
4865 tcg_temp_free(t2);
4866 if (unlikely(Rc(ctx->opcode) != 0))
4867 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4868 }
4869
4870 /* slq - slq. */
4871 static void gen_slq(DisasContext *ctx)
4872 {
4873 TCGLabel *l1 = gen_new_label();
4874 TCGv t0 = tcg_temp_new();
4875 TCGv t1 = tcg_temp_new();
4876 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4877 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4878 tcg_gen_subfi_tl(t1, 32, t1);
4879 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4880 tcg_gen_or_tl(t1, t0, t1);
4881 gen_store_spr(SPR_MQ, t1);
4882 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4883 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4884 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4885 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4886 gen_set_label(l1);
4887 tcg_temp_free(t0);
4888 tcg_temp_free(t1);
4889 if (unlikely(Rc(ctx->opcode) != 0))
4890 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4891 }
4892
4893 /* sraiq - sraiq. */
4894 static void gen_sraiq(DisasContext *ctx)
4895 {
4896 int sh = SH(ctx->opcode);
4897 TCGLabel *l1 = gen_new_label();
4898 TCGv t0 = tcg_temp_new();
4899 TCGv t1 = tcg_temp_new();
4900 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4901 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4902 tcg_gen_or_tl(t0, t0, t1);
4903 gen_store_spr(SPR_MQ, t0);
4904 tcg_gen_movi_tl(cpu_ca, 0);
4905 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4906 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4907 tcg_gen_movi_tl(cpu_ca, 1);
4908 gen_set_label(l1);
4909 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4910 tcg_temp_free(t0);
4911 tcg_temp_free(t1);
4912 if (unlikely(Rc(ctx->opcode) != 0))
4913 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4914 }
4915
4916 /* sraq - sraq. */
4917 static void gen_sraq(DisasContext *ctx)
4918 {
4919 TCGLabel *l1 = gen_new_label();
4920 TCGLabel *l2 = gen_new_label();
4921 TCGv t0 = tcg_temp_new();
4922 TCGv t1 = tcg_temp_local_new();
4923 TCGv t2 = tcg_temp_local_new();
4924 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4925 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4926 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4927 tcg_gen_subfi_tl(t2, 32, t2);
4928 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4929 tcg_gen_or_tl(t0, t0, t2);
4930 gen_store_spr(SPR_MQ, t0);
4931 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4932 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4933 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4934 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4935 gen_set_label(l1);
4936 tcg_temp_free(t0);
4937 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4938 tcg_gen_movi_tl(cpu_ca, 0);
4939 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4940 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4941 tcg_gen_movi_tl(cpu_ca, 1);
4942 gen_set_label(l2);
4943 tcg_temp_free(t1);
4944 tcg_temp_free(t2);
4945 if (unlikely(Rc(ctx->opcode) != 0))
4946 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4947 }
4948
4949 /* sre - sre. */
4950 static void gen_sre(DisasContext *ctx)
4951 {
4952 TCGv t0 = tcg_temp_new();
4953 TCGv t1 = tcg_temp_new();
4954 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4955 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4956 tcg_gen_subfi_tl(t1, 32, t1);
4957 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4958 tcg_gen_or_tl(t1, t0, t1);
4959 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4960 gen_store_spr(SPR_MQ, t1);
4961 tcg_temp_free(t0);
4962 tcg_temp_free(t1);
4963 if (unlikely(Rc(ctx->opcode) != 0))
4964 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4965 }
4966
4967 /* srea - srea. */
4968 static void gen_srea(DisasContext *ctx)
4969 {
4970 TCGv t0 = tcg_temp_new();
4971 TCGv t1 = tcg_temp_new();
4972 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4973 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4974 gen_store_spr(SPR_MQ, t0);
4975 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4976 tcg_temp_free(t0);
4977 tcg_temp_free(t1);
4978 if (unlikely(Rc(ctx->opcode) != 0))
4979 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4980 }
4981
4982 /* sreq */
4983 static void gen_sreq(DisasContext *ctx)
4984 {
4985 TCGv t0 = tcg_temp_new();
4986 TCGv t1 = tcg_temp_new();
4987 TCGv t2 = tcg_temp_new();
4988 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4989 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4990 tcg_gen_shr_tl(t1, t1, t0);
4991 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4992 gen_load_spr(t2, SPR_MQ);
4993 gen_store_spr(SPR_MQ, t0);
4994 tcg_gen_and_tl(t0, t0, t1);
4995 tcg_gen_andc_tl(t2, t2, t1);
4996 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4997 tcg_temp_free(t0);
4998 tcg_temp_free(t1);
4999 tcg_temp_free(t2);
5000 if (unlikely(Rc(ctx->opcode) != 0))
5001 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5002 }
5003
5004 /* sriq */
5005 static void gen_sriq(DisasContext *ctx)
5006 {
5007 int sh = SH(ctx->opcode);
5008 TCGv t0 = tcg_temp_new();
5009 TCGv t1 = tcg_temp_new();
5010 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5011 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5012 tcg_gen_or_tl(t1, t0, t1);
5013 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5014 gen_store_spr(SPR_MQ, t1);
5015 tcg_temp_free(t0);
5016 tcg_temp_free(t1);
5017 if (unlikely(Rc(ctx->opcode) != 0))
5018 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5019 }
5020
5021 /* srliq */
5022 static void gen_srliq(DisasContext *ctx)
5023 {
5024 int sh = SH(ctx->opcode);
5025 TCGv t0 = tcg_temp_new();
5026 TCGv t1 = tcg_temp_new();
5027 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5028 gen_load_spr(t1, SPR_MQ);
5029 gen_store_spr(SPR_MQ, t0);
5030 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5031 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5032 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5033 tcg_temp_free(t0);
5034 tcg_temp_free(t1);
5035 if (unlikely(Rc(ctx->opcode) != 0))
5036 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5037 }
5038
5039 /* srlq */
5040 static void gen_srlq(DisasContext *ctx)
5041 {
5042 TCGLabel *l1 = gen_new_label();
5043 TCGLabel *l2 = gen_new_label();
5044 TCGv t0 = tcg_temp_local_new();
5045 TCGv t1 = tcg_temp_local_new();
5046 TCGv t2 = tcg_temp_local_new();
5047 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5048 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5049 tcg_gen_shr_tl(t2, t1, t2);
5050 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5051 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5052 gen_load_spr(t0, SPR_MQ);
5053 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5054 tcg_gen_br(l2);
5055 gen_set_label(l1);
5056 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5057 tcg_gen_and_tl(t0, t0, t2);
5058 gen_load_spr(t1, SPR_MQ);
5059 tcg_gen_andc_tl(t1, t1, t2);
5060 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5061 gen_set_label(l2);
5062 tcg_temp_free(t0);
5063 tcg_temp_free(t1);
5064 tcg_temp_free(t2);
5065 if (unlikely(Rc(ctx->opcode) != 0))
5066 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5067 }
5068
5069 /* srq */
5070 static void gen_srq(DisasContext *ctx)
5071 {
5072 TCGLabel *l1 = gen_new_label();
5073 TCGv t0 = tcg_temp_new();
5074 TCGv t1 = tcg_temp_new();
5075 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5076 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5077 tcg_gen_subfi_tl(t1, 32, t1);
5078 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5079 tcg_gen_or_tl(t1, t0, t1);
5080 gen_store_spr(SPR_MQ, t1);
5081 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5082 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5083 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5084 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5085 gen_set_label(l1);
5086 tcg_temp_free(t0);
5087 tcg_temp_free(t1);
5088 if (unlikely(Rc(ctx->opcode) != 0))
5089 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5090 }
5091
5092 /* PowerPC 602 specific instructions */
5093
5094 /* dsa */
5095 static void gen_dsa(DisasContext *ctx)
5096 {
5097 /* XXX: TODO */
5098 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5099 }
5100
5101 /* esa */
5102 static void gen_esa(DisasContext *ctx)
5103 {
5104 /* XXX: TODO */
5105 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5106 }
5107
5108 /* mfrom */
5109 static void gen_mfrom(DisasContext *ctx)
5110 {
5111 #if defined(CONFIG_USER_ONLY)
5112 GEN_PRIV;
5113 #else
5114 CHK_SV;
5115 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5116 #endif /* defined(CONFIG_USER_ONLY) */
5117 }
5118
5119 /* 602 - 603 - G2 TLB management */
5120
5121 /* tlbld */
5122 static void gen_tlbld_6xx(DisasContext *ctx)
5123 {
5124 #if defined(CONFIG_USER_ONLY)
5125 GEN_PRIV;
5126 #else
5127 CHK_SV;
5128 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5129 #endif /* defined(CONFIG_USER_ONLY) */
5130 }
5131
5132 /* tlbli */
5133 static void gen_tlbli_6xx(DisasContext *ctx)
5134 {
5135 #if defined(CONFIG_USER_ONLY)
5136 GEN_PRIV;
5137 #else
5138 CHK_SV;
5139 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5140 #endif /* defined(CONFIG_USER_ONLY) */
5141 }
5142
5143 /* 74xx TLB management */
5144
5145 /* tlbld */
5146 static void gen_tlbld_74xx(DisasContext *ctx)
5147 {
5148 #if defined(CONFIG_USER_ONLY)
5149 GEN_PRIV;
5150 #else
5151 CHK_SV;
5152 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5153 #endif /* defined(CONFIG_USER_ONLY) */
5154 }
5155
5156 /* tlbli */
5157 static void gen_tlbli_74xx(DisasContext *ctx)
5158 {
5159 #if defined(CONFIG_USER_ONLY)
5160 GEN_PRIV;
5161 #else
5162 CHK_SV;
5163 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5164 #endif /* defined(CONFIG_USER_ONLY) */
5165 }
5166
5167 /* POWER instructions not in PowerPC 601 */
5168
5169 /* clf */
5170 static void gen_clf(DisasContext *ctx)
5171 {
5172 /* Cache line flush: implemented as no-op */
5173 }
5174
5175 /* cli */
5176 static void gen_cli(DisasContext *ctx)
5177 {
5178 #if defined(CONFIG_USER_ONLY)
5179 GEN_PRIV;
5180 #else
5181 /* Cache line invalidate: privileged and treated as no-op */
5182 CHK_SV;
5183 #endif /* defined(CONFIG_USER_ONLY) */
5184 }
5185
5186 /* dclst */
5187 static void gen_dclst(DisasContext *ctx)
5188 {
5189 /* Data cache line store: treated as no-op */
5190 }
5191
5192 static void gen_mfsri(DisasContext *ctx)
5193 {
5194 #if defined(CONFIG_USER_ONLY)
5195 GEN_PRIV;
5196 #else
5197 int ra = rA(ctx->opcode);
5198 int rd = rD(ctx->opcode);
5199 TCGv t0;
5200
5201 CHK_SV;
5202 t0 = tcg_temp_new();
5203 gen_addr_reg_index(ctx, t0);
5204 tcg_gen_shri_tl(t0, t0, 28);
5205 tcg_gen_andi_tl(t0, t0, 0xF);
5206 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5207 tcg_temp_free(t0);
5208 if (ra != 0 && ra != rd)
5209 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5210 #endif /* defined(CONFIG_USER_ONLY) */
5211 }
5212
5213 static void gen_rac(DisasContext *ctx)
5214 {
5215 #if defined(CONFIG_USER_ONLY)
5216 GEN_PRIV;
5217 #else
5218 TCGv t0;
5219
5220 CHK_SV;
5221 t0 = tcg_temp_new();
5222 gen_addr_reg_index(ctx, t0);
5223 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5224 tcg_temp_free(t0);
5225 #endif /* defined(CONFIG_USER_ONLY) */
5226 }
5227
5228 static void gen_rfsvc(DisasContext *ctx)
5229 {
5230 #if defined(CONFIG_USER_ONLY)
5231 GEN_PRIV;
5232 #else
5233 CHK_SV;
5234
5235 gen_helper_rfsvc(cpu_env);
5236 gen_sync_exception(ctx);
5237 #endif /* defined(CONFIG_USER_ONLY) */
5238 }
5239
5240 #include "translate/fp-impl.c"
5241
5242 #include "translate/vmx-impl.c"
5243
5244 #include "translate/vsx-impl.c"
5245
5246 /* svc is not implemented for now */
5247
5248 /* BookE specific instructions */
5249
5250 /* XXX: not implemented on 440 ? */
5251 static void gen_mfapidi(DisasContext *ctx)
5252 {
5253 /* XXX: TODO */
5254 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5255 }
5256
5257 /* XXX: not implemented on 440 ? */
5258 static void gen_tlbiva(DisasContext *ctx)
5259 {
5260 #if defined(CONFIG_USER_ONLY)
5261 GEN_PRIV;
5262 #else
5263 TCGv t0;
5264
5265 CHK_SV;
5266 t0 = tcg_temp_new();
5267 gen_addr_reg_index(ctx, t0);
5268 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5269 tcg_temp_free(t0);
5270 #endif /* defined(CONFIG_USER_ONLY) */
5271 }
5272
5273 /* All 405 MAC instructions are translated here */
5274 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5275 int ra, int rb, int rt, int Rc)
5276 {
5277 TCGv t0, t1;
5278
5279 t0 = tcg_temp_local_new();
5280 t1 = tcg_temp_local_new();
5281
5282 switch (opc3 & 0x0D) {
5283 case 0x05:
5284 /* macchw - macchw. - macchwo - macchwo. */
5285 /* macchws - macchws. - macchwso - macchwso. */
5286 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5287 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5288 /* mulchw - mulchw. */
5289 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5290 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5291 tcg_gen_ext16s_tl(t1, t1);
5292 break;
5293 case 0x04:
5294 /* macchwu - macchwu. - macchwuo - macchwuo. */
5295 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5296 /* mulchwu - mulchwu. */
5297 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5298 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5299 tcg_gen_ext16u_tl(t1, t1);
5300 break;
5301 case 0x01:
5302 /* machhw - machhw. - machhwo - machhwo. */
5303 /* machhws - machhws. - machhwso - machhwso. */
5304 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5305 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5306 /* mulhhw - mulhhw. */
5307 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5308 tcg_gen_ext16s_tl(t0, t0);
5309 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5310 tcg_gen_ext16s_tl(t1, t1);
5311 break;
5312 case 0x00:
5313 /* machhwu - machhwu. - machhwuo - machhwuo. */
5314 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5315 /* mulhhwu - mulhhwu. */
5316 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5317 tcg_gen_ext16u_tl(t0, t0);
5318 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5319 tcg_gen_ext16u_tl(t1, t1);
5320 break;
5321 case 0x0D:
5322 /* maclhw - maclhw. - maclhwo - maclhwo. */
5323 /* maclhws - maclhws. - maclhwso - maclhwso. */
5324 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5325 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5326 /* mullhw - mullhw. */
5327 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5328 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5329 break;
5330 case 0x0C:
5331 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5332 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5333 /* mullhwu - mullhwu. */
5334 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5335 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5336 break;
5337 }
5338 if (opc2 & 0x04) {
5339 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5340 tcg_gen_mul_tl(t1, t0, t1);
5341 if (opc2 & 0x02) {
5342 /* nmultiply-and-accumulate (0x0E) */
5343 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5344 } else {
5345 /* multiply-and-accumulate (0x0C) */
5346 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5347 }
5348
5349 if (opc3 & 0x12) {
5350 /* Check overflow and/or saturate */
5351 TCGLabel *l1 = gen_new_label();
5352
5353 if (opc3 & 0x10) {
5354 /* Start with XER OV disabled, the most likely case */
5355 tcg_gen_movi_tl(cpu_ov, 0);
5356 }
5357 if (opc3 & 0x01) {
5358 /* Signed */
5359 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5360 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5361 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5362 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5363 if (opc3 & 0x02) {
5364 /* Saturate */
5365 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5366 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5367 }
5368 } else {
5369 /* Unsigned */
5370 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5371 if (opc3 & 0x02) {
5372 /* Saturate */
5373 tcg_gen_movi_tl(t0, UINT32_MAX);
5374 }
5375 }
5376 if (opc3 & 0x10) {
5377 /* Check overflow */
5378 tcg_gen_movi_tl(cpu_ov, 1);
5379 tcg_gen_movi_tl(cpu_so, 1);
5380 }
5381 gen_set_label(l1);
5382 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5383 }
5384 } else {
5385 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5386 }
5387 tcg_temp_free(t0);
5388 tcg_temp_free(t1);
5389 if (unlikely(Rc) != 0) {
5390 /* Update Rc0 */
5391 gen_set_Rc0(ctx, cpu_gpr[rt]);
5392 }
5393 }
5394
5395 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5396 static void glue(gen_, name)(DisasContext *ctx) \
5397 { \
5398 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5399 rD(ctx->opcode), Rc(ctx->opcode)); \
5400 }
5401
5402 /* macchw - macchw. */
5403 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5404 /* macchwo - macchwo. */
5405 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5406 /* macchws - macchws. */
5407 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5408 /* macchwso - macchwso. */
5409 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5410 /* macchwsu - macchwsu. */
5411 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5412 /* macchwsuo - macchwsuo. */
5413 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5414 /* macchwu - macchwu. */
5415 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5416 /* macchwuo - macchwuo. */
5417 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5418 /* machhw - machhw. */
5419 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5420 /* machhwo - machhwo. */
5421 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5422 /* machhws - machhws. */
5423 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5424 /* machhwso - machhwso. */
5425 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5426 /* machhwsu - machhwsu. */
5427 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5428 /* machhwsuo - machhwsuo. */
5429 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5430 /* machhwu - machhwu. */
5431 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5432 /* machhwuo - machhwuo. */
5433 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5434 /* maclhw - maclhw. */
5435 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5436 /* maclhwo - maclhwo. */
5437 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5438 /* maclhws - maclhws. */
5439 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5440 /* maclhwso - maclhwso. */
5441 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5442 /* maclhwu - maclhwu. */
5443 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5444 /* maclhwuo - maclhwuo. */
5445 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5446 /* maclhwsu - maclhwsu. */
5447 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5448 /* maclhwsuo - maclhwsuo. */
5449 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5450 /* nmacchw - nmacchw. */
5451 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5452 /* nmacchwo - nmacchwo. */
5453 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5454 /* nmacchws - nmacchws. */
5455 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5456 /* nmacchwso - nmacchwso. */
5457 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5458 /* nmachhw - nmachhw. */
5459 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5460 /* nmachhwo - nmachhwo. */
5461 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5462 /* nmachhws - nmachhws. */
5463 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5464 /* nmachhwso - nmachhwso. */
5465 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5466 /* nmaclhw - nmaclhw. */
5467 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5468 /* nmaclhwo - nmaclhwo. */
5469 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5470 /* nmaclhws - nmaclhws. */
5471 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5472 /* nmaclhwso - nmaclhwso. */
5473 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5474
5475 /* mulchw - mulchw. */
5476 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5477 /* mulchwu - mulchwu. */
5478 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5479 /* mulhhw - mulhhw. */
5480 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5481 /* mulhhwu - mulhhwu. */
5482 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5483 /* mullhw - mullhw. */
5484 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5485 /* mullhwu - mullhwu. */
5486 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5487
5488 /* mfdcr */
5489 static void gen_mfdcr(DisasContext *ctx)
5490 {
5491 #if defined(CONFIG_USER_ONLY)
5492 GEN_PRIV;
5493 #else
5494 TCGv dcrn;
5495
5496 CHK_SV;
5497 /* NIP cannot be restored if the memory exception comes from an helper */
5498 gen_update_nip(ctx, ctx->nip - 4);
5499 dcrn = tcg_const_tl(SPR(ctx->opcode));
5500 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5501 tcg_temp_free(dcrn);
5502 #endif /* defined(CONFIG_USER_ONLY) */
5503 }
5504
5505 /* mtdcr */
5506 static void gen_mtdcr(DisasContext *ctx)
5507 {
5508 #if defined(CONFIG_USER_ONLY)
5509 GEN_PRIV;
5510 #else
5511 TCGv dcrn;
5512
5513 CHK_SV;
5514 /* NIP cannot be restored if the memory exception comes from an helper */
5515 gen_update_nip(ctx, ctx->nip - 4);
5516 dcrn = tcg_const_tl(SPR(ctx->opcode));
5517 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5518 tcg_temp_free(dcrn);
5519 #endif /* defined(CONFIG_USER_ONLY) */
5520 }
5521
5522 /* mfdcrx */
5523 /* XXX: not implemented on 440 ? */
5524 static void gen_mfdcrx(DisasContext *ctx)
5525 {
5526 #if defined(CONFIG_USER_ONLY)
5527 GEN_PRIV;
5528 #else
5529 CHK_SV;
5530 /* NIP cannot be restored if the memory exception comes from an helper */
5531 gen_update_nip(ctx, ctx->nip - 4);
5532 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5533 cpu_gpr[rA(ctx->opcode)]);
5534 /* Note: Rc update flag set leads to undefined state of Rc0 */
5535 #endif /* defined(CONFIG_USER_ONLY) */
5536 }
5537
5538 /* mtdcrx */
5539 /* XXX: not implemented on 440 ? */
5540 static void gen_mtdcrx(DisasContext *ctx)
5541 {
5542 #if defined(CONFIG_USER_ONLY)
5543 GEN_PRIV;
5544 #else
5545 CHK_SV;
5546 /* NIP cannot be restored if the memory exception comes from an helper */
5547 gen_update_nip(ctx, ctx->nip - 4);
5548 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5549 cpu_gpr[rS(ctx->opcode)]);
5550 /* Note: Rc update flag set leads to undefined state of Rc0 */
5551 #endif /* defined(CONFIG_USER_ONLY) */
5552 }
5553
5554 /* mfdcrux (PPC 460) : user-mode access to DCR */
5555 static void gen_mfdcrux(DisasContext *ctx)
5556 {
5557 /* NIP cannot be restored if the memory exception comes from an helper */
5558 gen_update_nip(ctx, ctx->nip - 4);
5559 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5560 cpu_gpr[rA(ctx->opcode)]);
5561 /* Note: Rc update flag set leads to undefined state of Rc0 */
5562 }
5563
5564 /* mtdcrux (PPC 460) : user-mode access to DCR */
5565 static void gen_mtdcrux(DisasContext *ctx)
5566 {
5567 /* NIP cannot be restored if the memory exception comes from an helper */
5568 gen_update_nip(ctx, ctx->nip - 4);
5569 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5570 cpu_gpr[rS(ctx->opcode)]);
5571 /* Note: Rc update flag set leads to undefined state of Rc0 */
5572 }
5573
5574 /* dccci */
5575 static void gen_dccci(DisasContext *ctx)
5576 {
5577 CHK_SV;
5578 /* interpreted as no-op */
5579 }
5580
5581 /* dcread */
5582 static void gen_dcread(DisasContext *ctx)
5583 {
5584 #if defined(CONFIG_USER_ONLY)
5585 GEN_PRIV;
5586 #else
5587 TCGv EA, val;
5588
5589 CHK_SV;
5590 gen_set_access_type(ctx, ACCESS_CACHE);
5591 EA = tcg_temp_new();
5592 gen_addr_reg_index(ctx, EA);
5593 val = tcg_temp_new();
5594 gen_qemu_ld32u(ctx, val, EA);
5595 tcg_temp_free(val);
5596 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5597 tcg_temp_free(EA);
5598 #endif /* defined(CONFIG_USER_ONLY) */
5599 }
5600
5601 /* icbt */
5602 static void gen_icbt_40x(DisasContext *ctx)
5603 {
5604 /* interpreted as no-op */
5605 /* XXX: specification say this is treated as a load by the MMU
5606 * but does not generate any exception
5607 */
5608 }
5609
5610 /* iccci */
5611 static void gen_iccci(DisasContext *ctx)
5612 {
5613 CHK_SV;
5614 /* interpreted as no-op */
5615 }
5616
5617 /* icread */
5618 static void gen_icread(DisasContext *ctx)
5619 {
5620 CHK_SV;
5621 /* interpreted as no-op */
5622 }
5623
5624 /* rfci (supervisor only) */
5625 static void gen_rfci_40x(DisasContext *ctx)
5626 {
5627 #if defined(CONFIG_USER_ONLY)
5628 GEN_PRIV;
5629 #else
5630 CHK_SV;
5631 /* Restore CPU state */
5632 gen_helper_40x_rfci(cpu_env);
5633 gen_sync_exception(ctx);
5634 #endif /* defined(CONFIG_USER_ONLY) */
5635 }
5636
5637 static void gen_rfci(DisasContext *ctx)
5638 {
5639 #if defined(CONFIG_USER_ONLY)
5640 GEN_PRIV;
5641 #else
5642 CHK_SV;
5643 /* Restore CPU state */
5644 gen_helper_rfci(cpu_env);
5645 gen_sync_exception(ctx);
5646 #endif /* defined(CONFIG_USER_ONLY) */
5647 }
5648
5649 /* BookE specific */
5650
5651 /* XXX: not implemented on 440 ? */
5652 static void gen_rfdi(DisasContext *ctx)
5653 {
5654 #if defined(CONFIG_USER_ONLY)
5655 GEN_PRIV;
5656 #else
5657 CHK_SV;
5658 /* Restore CPU state */
5659 gen_helper_rfdi(cpu_env);
5660 gen_sync_exception(ctx);
5661 #endif /* defined(CONFIG_USER_ONLY) */
5662 }
5663
5664 /* XXX: not implemented on 440 ? */
5665 static void gen_rfmci(DisasContext *ctx)
5666 {
5667 #if defined(CONFIG_USER_ONLY)
5668 GEN_PRIV;
5669 #else
5670 CHK_SV;
5671 /* Restore CPU state */
5672 gen_helper_rfmci(cpu_env);
5673 gen_sync_exception(ctx);
5674 #endif /* defined(CONFIG_USER_ONLY) */
5675 }
5676
5677 /* TLB management - PowerPC 405 implementation */
5678
5679 /* tlbre */
5680 static void gen_tlbre_40x(DisasContext *ctx)
5681 {
5682 #if defined(CONFIG_USER_ONLY)
5683 GEN_PRIV;
5684 #else
5685 CHK_SV;
5686 switch (rB(ctx->opcode)) {
5687 case 0:
5688 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5689 cpu_gpr[rA(ctx->opcode)]);
5690 break;
5691 case 1:
5692 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5693 cpu_gpr[rA(ctx->opcode)]);
5694 break;
5695 default:
5696 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5697 break;
5698 }
5699 #endif /* defined(CONFIG_USER_ONLY) */
5700 }
5701
5702 /* tlbsx - tlbsx. */
5703 static void gen_tlbsx_40x(DisasContext *ctx)
5704 {
5705 #if defined(CONFIG_USER_ONLY)
5706 GEN_PRIV;
5707 #else
5708 TCGv t0;
5709
5710 CHK_SV;
5711 t0 = tcg_temp_new();
5712 gen_addr_reg_index(ctx, t0);
5713 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5714 tcg_temp_free(t0);
5715 if (Rc(ctx->opcode)) {
5716 TCGLabel *l1 = gen_new_label();
5717 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5718 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5719 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5720 gen_set_label(l1);
5721 }
5722 #endif /* defined(CONFIG_USER_ONLY) */
5723 }
5724
5725 /* tlbwe */
5726 static void gen_tlbwe_40x(DisasContext *ctx)
5727 {
5728 #if defined(CONFIG_USER_ONLY)
5729 GEN_PRIV;
5730 #else
5731 CHK_SV;
5732
5733 switch (rB(ctx->opcode)) {
5734 case 0:
5735 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5736 cpu_gpr[rS(ctx->opcode)]);
5737 break;
5738 case 1:
5739 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5740 cpu_gpr[rS(ctx->opcode)]);
5741 break;
5742 default:
5743 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5744 break;
5745 }
5746 #endif /* defined(CONFIG_USER_ONLY) */
5747 }
5748
5749 /* TLB management - PowerPC 440 implementation */
5750
5751 /* tlbre */
5752 static void gen_tlbre_440(DisasContext *ctx)
5753 {
5754 #if defined(CONFIG_USER_ONLY)
5755 GEN_PRIV;
5756 #else
5757 CHK_SV;
5758
5759 switch (rB(ctx->opcode)) {
5760 case 0:
5761 case 1:
5762 case 2:
5763 {
5764 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5765 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5766 t0, cpu_gpr[rA(ctx->opcode)]);
5767 tcg_temp_free_i32(t0);
5768 }
5769 break;
5770 default:
5771 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5772 break;
5773 }
5774 #endif /* defined(CONFIG_USER_ONLY) */
5775 }
5776
5777 /* tlbsx - tlbsx. */
5778 static void gen_tlbsx_440(DisasContext *ctx)
5779 {
5780 #if defined(CONFIG_USER_ONLY)
5781 GEN_PRIV;
5782 #else
5783 TCGv t0;
5784
5785 CHK_SV;
5786 t0 = tcg_temp_new();
5787 gen_addr_reg_index(ctx, t0);
5788 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5789 tcg_temp_free(t0);
5790 if (Rc(ctx->opcode)) {
5791 TCGLabel *l1 = gen_new_label();
5792 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5793 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5794 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5795 gen_set_label(l1);
5796 }
5797 #endif /* defined(CONFIG_USER_ONLY) */
5798 }
5799
5800 /* tlbwe */
5801 static void gen_tlbwe_440(DisasContext *ctx)
5802 {
5803 #if defined(CONFIG_USER_ONLY)
5804 GEN_PRIV;
5805 #else
5806 CHK_SV;
5807 switch (rB(ctx->opcode)) {
5808 case 0:
5809 case 1:
5810 case 2:
5811 {
5812 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5813 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
5814 cpu_gpr[rS(ctx->opcode)]);
5815 tcg_temp_free_i32(t0);
5816 }
5817 break;
5818 default:
5819 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5820 break;
5821 }
5822 #endif /* defined(CONFIG_USER_ONLY) */
5823 }
5824
5825 /* TLB management - PowerPC BookE 2.06 implementation */
5826
5827 /* tlbre */
5828 static void gen_tlbre_booke206(DisasContext *ctx)
5829 {
5830 #if defined(CONFIG_USER_ONLY)
5831 GEN_PRIV;
5832 #else
5833 CHK_SV;
5834 gen_helper_booke206_tlbre(cpu_env);
5835 #endif /* defined(CONFIG_USER_ONLY) */
5836 }
5837
5838 /* tlbsx - tlbsx. */
5839 static void gen_tlbsx_booke206(DisasContext *ctx)
5840 {
5841 #if defined(CONFIG_USER_ONLY)
5842 GEN_PRIV;
5843 #else
5844 TCGv t0;
5845
5846 CHK_SV;
5847 if (rA(ctx->opcode)) {
5848 t0 = tcg_temp_new();
5849 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
5850 } else {
5851 t0 = tcg_const_tl(0);
5852 }
5853
5854 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
5855 gen_helper_booke206_tlbsx(cpu_env, t0);
5856 tcg_temp_free(t0);
5857 #endif /* defined(CONFIG_USER_ONLY) */
5858 }
5859
5860 /* tlbwe */
5861 static void gen_tlbwe_booke206(DisasContext *ctx)
5862 {
5863 #if defined(CONFIG_USER_ONLY)
5864 GEN_PRIV;
5865 #else
5866 CHK_SV;
5867 gen_update_nip(ctx, ctx->nip - 4);
5868 gen_helper_booke206_tlbwe(cpu_env);
5869 #endif /* defined(CONFIG_USER_ONLY) */
5870 }
5871
5872 static void gen_tlbivax_booke206(DisasContext *ctx)
5873 {
5874 #if defined(CONFIG_USER_ONLY)
5875 GEN_PRIV;
5876 #else
5877 TCGv t0;
5878
5879 CHK_SV;
5880 t0 = tcg_temp_new();
5881 gen_addr_reg_index(ctx, t0);
5882 gen_helper_booke206_tlbivax(cpu_env, t0);
5883 tcg_temp_free(t0);
5884 #endif /* defined(CONFIG_USER_ONLY) */
5885 }
5886
5887 static void gen_tlbilx_booke206(DisasContext *ctx)
5888 {
5889 #if defined(CONFIG_USER_ONLY)
5890 GEN_PRIV;
5891 #else
5892 TCGv t0;
5893
5894 CHK_SV;
5895 t0 = tcg_temp_new();
5896 gen_addr_reg_index(ctx, t0);
5897
5898 switch((ctx->opcode >> 21) & 0x3) {
5899 case 0:
5900 gen_helper_booke206_tlbilx0(cpu_env, t0);
5901 break;
5902 case 1:
5903 gen_helper_booke206_tlbilx1(cpu_env, t0);
5904 break;
5905 case 3:
5906 gen_helper_booke206_tlbilx3(cpu_env, t0);
5907 break;
5908 default:
5909 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5910 break;
5911 }
5912
5913 tcg_temp_free(t0);
5914 #endif /* defined(CONFIG_USER_ONLY) */
5915 }
5916
5917
5918 /* wrtee */
5919 static void gen_wrtee(DisasContext *ctx)
5920 {
5921 #if defined(CONFIG_USER_ONLY)
5922 GEN_PRIV;
5923 #else
5924 TCGv t0;
5925
5926 CHK_SV;
5927 t0 = tcg_temp_new();
5928 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
5929 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
5930 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
5931 tcg_temp_free(t0);
5932 /* Stop translation to have a chance to raise an exception
5933 * if we just set msr_ee to 1
5934 */
5935 gen_stop_exception(ctx);
5936 #endif /* defined(CONFIG_USER_ONLY) */
5937 }
5938
5939 /* wrteei */
5940 static void gen_wrteei(DisasContext *ctx)
5941 {
5942 #if defined(CONFIG_USER_ONLY)
5943 GEN_PRIV;
5944 #else
5945 CHK_SV;
5946 if (ctx->opcode & 0x00008000) {
5947 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
5948 /* Stop translation to have a chance to raise an exception */
5949 gen_stop_exception(ctx);
5950 } else {
5951 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
5952 }
5953 #endif /* defined(CONFIG_USER_ONLY) */
5954 }
5955
5956 /* PowerPC 440 specific instructions */
5957
5958 /* dlmzb */
5959 static void gen_dlmzb(DisasContext *ctx)
5960 {
5961 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
5962 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
5963 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
5964 tcg_temp_free_i32(t0);
5965 }
5966
5967 /* mbar replaces eieio on 440 */
5968 static void gen_mbar(DisasContext *ctx)
5969 {
5970 /* interpreted as no-op */
5971 }
5972
5973 /* msync replaces sync on 440 */
5974 static void gen_msync_4xx(DisasContext *ctx)
5975 {
5976 /* interpreted as no-op */
5977 }
5978
5979 /* icbt */
5980 static void gen_icbt_440(DisasContext *ctx)
5981 {
5982 /* interpreted as no-op */
5983 /* XXX: specification say this is treated as a load by the MMU
5984 * but does not generate any exception
5985 */
5986 }
5987
5988 /* Embedded.Processor Control */
5989
5990 static void gen_msgclr(DisasContext *ctx)
5991 {
5992 #if defined(CONFIG_USER_ONLY)
5993 GEN_PRIV;
5994 #else
5995 CHK_SV;
5996 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5997 #endif /* defined(CONFIG_USER_ONLY) */
5998 }
5999
6000 static void gen_msgsnd(DisasContext *ctx)
6001 {
6002 #if defined(CONFIG_USER_ONLY)
6003 GEN_PRIV;
6004 #else
6005 CHK_SV;
6006 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6007 #endif /* defined(CONFIG_USER_ONLY) */
6008 }
6009
6010
6011 #if defined(TARGET_PPC64)
6012 static void gen_maddld(DisasContext *ctx)
6013 {
6014 TCGv_i64 t1 = tcg_temp_new_i64();
6015
6016 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6017 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
6018 tcg_temp_free_i64(t1);
6019 }
6020
6021 /* maddhd maddhdu */
6022 static void gen_maddhd_maddhdu(DisasContext *ctx)
6023 {
6024 TCGv_i64 lo = tcg_temp_new_i64();
6025 TCGv_i64 hi = tcg_temp_new_i64();
6026 TCGv_i64 t1 = tcg_temp_new_i64();
6027
6028 if (Rc(ctx->opcode)) {
6029 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6030 cpu_gpr[rB(ctx->opcode)]);
6031 tcg_gen_movi_i64(t1, 0);
6032 } else {
6033 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6034 cpu_gpr[rB(ctx->opcode)]);
6035 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
6036 }
6037 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
6038 cpu_gpr[rC(ctx->opcode)], t1);
6039 tcg_temp_free_i64(lo);
6040 tcg_temp_free_i64(hi);
6041 tcg_temp_free_i64(t1);
6042 }
6043 #endif /* defined(TARGET_PPC64) */
6044
6045 #include "translate/dfp-impl.c"
6046
6047 #include "translate/spe-impl.c"
6048
6049 static void gen_tbegin(DisasContext *ctx)
6050 {
6051 if (unlikely(!ctx->tm_enabled)) {
6052 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6053 return;
6054 }
6055 gen_helper_tbegin(cpu_env);
6056 }
6057
6058 #define GEN_TM_NOOP(name) \
6059 static inline void gen_##name(DisasContext *ctx) \
6060 { \
6061 if (unlikely(!ctx->tm_enabled)) { \
6062 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6063 return; \
6064 } \
6065 /* Because tbegin always fails in QEMU, these user \
6066 * space instructions all have a simple implementation: \
6067 * \
6068 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6069 * = 0b0 || 0b00 || 0b0 \
6070 */ \
6071 tcg_gen_movi_i32(cpu_crf[0], 0); \
6072 }
6073
6074 GEN_TM_NOOP(tend);
6075 GEN_TM_NOOP(tabort);
6076 GEN_TM_NOOP(tabortwc);
6077 GEN_TM_NOOP(tabortwci);
6078 GEN_TM_NOOP(tabortdc);
6079 GEN_TM_NOOP(tabortdci);
6080 GEN_TM_NOOP(tsr);
6081
6082 static void gen_tcheck(DisasContext *ctx)
6083 {
6084 if (unlikely(!ctx->tm_enabled)) {
6085 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6086 return;
6087 }
6088 /* Because tbegin always fails, the tcheck implementation
6089 * is simple:
6090 *
6091 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6092 * = 0b1 || 0b00 || 0b0
6093 */
6094 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
6095 }
6096
6097 #if defined(CONFIG_USER_ONLY)
6098 #define GEN_TM_PRIV_NOOP(name) \
6099 static inline void gen_##name(DisasContext *ctx) \
6100 { \
6101 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6102 }
6103
6104 #else
6105
6106 #define GEN_TM_PRIV_NOOP(name) \
6107 static inline void gen_##name(DisasContext *ctx) \
6108 { \
6109 CHK_SV; \
6110 if (unlikely(!ctx->tm_enabled)) { \
6111 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6112 return; \
6113 } \
6114 /* Because tbegin always fails, the implementation is \
6115 * simple: \
6116 * \
6117 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6118 * = 0b0 || 0b00 | 0b0 \
6119 */ \
6120 tcg_gen_movi_i32(cpu_crf[0], 0); \
6121 }
6122
6123 #endif
6124
6125 GEN_TM_PRIV_NOOP(treclaim);
6126 GEN_TM_PRIV_NOOP(trechkpt);
6127
6128 static opcode_t opcodes[] = {
6129 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
6130 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
6131 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6132 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
6133 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6134 #if defined(TARGET_PPC64)
6135 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
6136 #endif
6137 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
6138 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
6139 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
6140 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6141 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6142 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6143 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6144 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6145 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
6146 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
6147 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
6148 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
6149 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6150 #if defined(TARGET_PPC64)
6151 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
6152 #endif
6153 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
6154 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
6155 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6156 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6157 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6158 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
6159 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
6160 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
6161 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
6162 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6163 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6164 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6165 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6166 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
6167 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
6168 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
6169 #if defined(TARGET_PPC64)
6170 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
6171 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
6172 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
6173 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
6174 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
6175 #endif
6176 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6177 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6178 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6179 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
6180 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
6181 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
6182 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
6183 #if defined(TARGET_PPC64)
6184 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
6185 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
6186 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
6187 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
6188 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
6189 #endif
6190 #if defined(TARGET_PPC64)
6191 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
6192 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
6193 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
6194 #endif
6195 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6196 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6197 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
6198 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
6199 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
6200 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
6201 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
6202 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
6203 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6204 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6205 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
6206 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6207 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6208 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
6209 #if defined(TARGET_PPC64)
6210 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
6211 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
6212 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
6213 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
6214 #endif
6215 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
6216 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
6217 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6218 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6219 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
6220 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
6221 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
6222 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
6223 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
6224 #if defined(TARGET_PPC64)
6225 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
6226 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6227 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6228 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6229 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6230 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
6231 #endif
6232 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
6233 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
6234 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6235 #if defined(TARGET_PPC64)
6236 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
6237 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
6238 #endif
6239 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
6240 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
6241 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
6242 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
6243 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
6244 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
6245 #if defined(TARGET_PPC64)
6246 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
6247 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
6248 #endif
6249 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
6250 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
6251 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
6252 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
6253 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
6254 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
6255 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
6256 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
6257 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
6258 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
6259 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
6260 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
6261 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
6262 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
6263 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
6264 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
6265 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
6266 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
6267 #if defined(TARGET_PPC64)
6268 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
6269 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6270 PPC_SEGMENT_64B),
6271 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
6272 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6273 PPC_SEGMENT_64B),
6274 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
6275 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
6276 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
6277 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
6278 #endif
6279 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
6280 /* XXX Those instructions will need to be handled differently for
6281 * different ISA versions */
6282 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
6283 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
6284 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
6285 #if defined(TARGET_PPC64)
6286 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
6287 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
6288 #endif
6289 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
6290 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
6291 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
6292 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
6293 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
6294 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
6295 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
6296 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
6297 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
6298 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
6299 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
6300 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6301 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
6302 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
6303 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
6304 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
6305 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
6306 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
6307 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
6308 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6309 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
6310 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
6311 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
6312 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
6313 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
6314 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
6315 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
6316 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
6317 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
6318 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
6319 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
6320 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
6321 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
6322 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
6323 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
6324 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
6325 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
6326 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
6327 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
6328 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
6329 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
6330 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
6331 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
6332 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
6333 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
6334 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
6335 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
6336 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
6337 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
6338 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6339 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6340 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
6341 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
6342 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6343 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6344 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
6345 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
6346 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
6347 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
6348 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
6349 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
6350 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
6351 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
6352 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
6353 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
6354 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
6355 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
6356 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
6357 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
6358 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
6359 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
6360 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
6361 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
6362 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
6363 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
6364 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
6365 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
6366 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
6367 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
6368 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
6369 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
6370 PPC_NONE, PPC2_BOOKE206),
6371 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
6372 PPC_NONE, PPC2_BOOKE206),
6373 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
6374 PPC_NONE, PPC2_BOOKE206),
6375 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
6376 PPC_NONE, PPC2_BOOKE206),
6377 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
6378 PPC_NONE, PPC2_BOOKE206),
6379 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
6380 PPC_NONE, PPC2_PRCNTL),
6381 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
6382 PPC_NONE, PPC2_PRCNTL),
6383 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
6384 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
6385 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
6386 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
6387 PPC_BOOKE, PPC2_BOOKE206),
6388 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
6389 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
6390 PPC_BOOKE, PPC2_BOOKE206),
6391 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
6392 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
6393 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
6394 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
6395 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
6396 #if defined(TARGET_PPC64)
6397 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
6398 PPC2_ISA300),
6399 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6400 #endif
6401
6402 #undef GEN_INT_ARITH_ADD
6403 #undef GEN_INT_ARITH_ADD_CONST
6404 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
6405 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
6406 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
6407 add_ca, compute_ca, compute_ov) \
6408 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
6409 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
6410 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
6411 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
6412 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
6413 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
6414 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
6415 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
6416 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
6417 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
6418 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
6419
6420 #undef GEN_INT_ARITH_DIVW
6421 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
6422 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
6423 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
6424 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
6425 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
6426 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
6427 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6428 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6429 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6430 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6431 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6432 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6433
6434 #if defined(TARGET_PPC64)
6435 #undef GEN_INT_ARITH_DIVD
6436 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
6437 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6438 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
6439 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
6440 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
6441 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
6442
6443 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6444 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6445 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6446 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6447 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6448 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6449
6450 #undef GEN_INT_ARITH_MUL_HELPER
6451 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
6452 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6453 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
6454 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
6455 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
6456 #endif
6457
6458 #undef GEN_INT_ARITH_SUBF
6459 #undef GEN_INT_ARITH_SUBF_CONST
6460 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
6461 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
6462 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
6463 add_ca, compute_ca, compute_ov) \
6464 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
6465 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
6466 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
6467 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
6468 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
6469 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
6470 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
6471 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
6472 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
6473 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
6474 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
6475
6476 #undef GEN_LOGICAL1
6477 #undef GEN_LOGICAL2
6478 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
6479 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
6480 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
6481 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
6482 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
6483 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
6484 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
6485 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
6486 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
6487 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
6488 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
6489 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
6490 #if defined(TARGET_PPC64)
6491 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
6492 #endif
6493
6494 #if defined(TARGET_PPC64)
6495 #undef GEN_PPC64_R2
6496 #undef GEN_PPC64_R4
6497 #define GEN_PPC64_R2(name, opc1, opc2) \
6498 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6499 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6500 PPC_64B)
6501 #define GEN_PPC64_R4(name, opc1, opc2) \
6502 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6503 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
6504 PPC_64B), \
6505 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6506 PPC_64B), \
6507 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
6508 PPC_64B)
6509 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
6510 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
6511 GEN_PPC64_R4(rldic, 0x1E, 0x04),
6512 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
6513 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
6514 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
6515 #endif
6516
6517 #undef GEN_LD
6518 #undef GEN_LDU
6519 #undef GEN_LDUX
6520 #undef GEN_LDX_E
6521 #undef GEN_LDS
6522 #define GEN_LD(name, ldop, opc, type) \
6523 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6524 #define GEN_LDU(name, ldop, opc, type) \
6525 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
6526 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
6527 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6528 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
6529 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6530 #define GEN_LDS(name, ldop, op, type) \
6531 GEN_LD(name, ldop, op | 0x20, type) \
6532 GEN_LDU(name, ldop, op | 0x21, type) \
6533 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
6534 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
6535
6536 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
6537 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
6538 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
6539 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
6540 #if defined(TARGET_PPC64)
6541 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
6542 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
6543 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
6544 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
6545 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
6546
6547 /* HV/P7 and later only */
6548 GEN_LDX_HVRM(ldcix, ld64, 0x15, 0x1b, PPC_CILDST)
6549 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
6550 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
6551 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
6552 #endif
6553 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
6554 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
6555
6556 #undef GEN_ST
6557 #undef GEN_STU
6558 #undef GEN_STUX
6559 #undef GEN_STX_E
6560 #undef GEN_STS
6561 #define GEN_ST(name, stop, opc, type) \
6562 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6563 #define GEN_STU(name, stop, opc, type) \
6564 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
6565 #define GEN_STUX(name, stop, opc2, opc3, type) \
6566 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6567 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
6568 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6569 #define GEN_STS(name, stop, op, type) \
6570 GEN_ST(name, stop, op | 0x20, type) \
6571 GEN_STU(name, stop, op | 0x21, type) \
6572 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
6573 GEN_STX(name, stop, 0x17, op | 0x00, type)
6574
6575 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
6576 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
6577 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
6578 #if defined(TARGET_PPC64)
6579 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
6580 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
6581 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
6582 GEN_STX_HVRM(stdcix, st64, 0x15, 0x1f, PPC_CILDST)
6583 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
6584 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
6585 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
6586 #endif
6587 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
6588 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
6589
6590 #undef GEN_CRLOGIC
6591 #define GEN_CRLOGIC(name, tcg_op, opc) \
6592 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
6593 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
6594 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
6595 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
6596 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
6597 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
6598 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
6599 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
6600 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
6601
6602 #undef GEN_MAC_HANDLER
6603 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6604 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
6605 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
6606 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
6607 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
6608 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
6609 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
6610 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
6611 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
6612 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
6613 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
6614 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
6615 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
6616 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
6617 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
6618 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
6619 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
6620 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
6621 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
6622 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
6623 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
6624 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
6625 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
6626 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
6627 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
6628 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
6629 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
6630 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
6631 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
6632 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
6633 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
6634 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
6635 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
6636 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
6637 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
6638 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
6639 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
6640 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
6641 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
6642 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
6643 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
6644 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
6645 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
6646 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
6647
6648 #include "translate/fp-ops.c"
6649
6650 #include "translate/vmx-ops.c"
6651
6652 #include "translate/vsx-ops.c"
6653
6654 #include "translate/dfp-ops.c"
6655
6656 #include "translate/spe-ops.c"
6657
6658 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
6659 PPC_NONE, PPC2_TM),
6660 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
6661 PPC_NONE, PPC2_TM),
6662 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
6663 PPC_NONE, PPC2_TM),
6664 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
6665 PPC_NONE, PPC2_TM),
6666 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
6667 PPC_NONE, PPC2_TM),
6668 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
6669 PPC_NONE, PPC2_TM),
6670 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
6671 PPC_NONE, PPC2_TM),
6672 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
6673 PPC_NONE, PPC2_TM),
6674 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
6675 PPC_NONE, PPC2_TM),
6676 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
6677 PPC_NONE, PPC2_TM),
6678 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
6679 PPC_NONE, PPC2_TM),
6680 };
6681
6682 #include "helper_regs.h"
6683 #include "translate_init.c"
6684
6685 /*****************************************************************************/
6686 /* Misc PowerPC helpers */
6687 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
6688 int flags)
6689 {
6690 #define RGPL 4
6691 #define RFPL 4
6692
6693 PowerPCCPU *cpu = POWERPC_CPU(cs);
6694 CPUPPCState *env = &cpu->env;
6695 int i;
6696
6697 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
6698 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
6699 env->nip, env->lr, env->ctr, cpu_read_xer(env),
6700 cs->cpu_index);
6701 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
6702 TARGET_FMT_lx " iidx %d didx %d\n",
6703 env->msr, env->spr[SPR_HID0],
6704 env->hflags, env->immu_idx, env->dmmu_idx);
6705 #if !defined(NO_TIMER_DUMP)
6706 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
6707 #if !defined(CONFIG_USER_ONLY)
6708 " DECR %08" PRIu32
6709 #endif
6710 "\n",
6711 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
6712 #if !defined(CONFIG_USER_ONLY)
6713 , cpu_ppc_load_decr(env)
6714 #endif
6715 );
6716 #endif
6717 for (i = 0; i < 32; i++) {
6718 if ((i & (RGPL - 1)) == 0)
6719 cpu_fprintf(f, "GPR%02d", i);
6720 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
6721 if ((i & (RGPL - 1)) == (RGPL - 1))
6722 cpu_fprintf(f, "\n");
6723 }
6724 cpu_fprintf(f, "CR ");
6725 for (i = 0; i < 8; i++)
6726 cpu_fprintf(f, "%01x", env->crf[i]);
6727 cpu_fprintf(f, " [");
6728 for (i = 0; i < 8; i++) {
6729 char a = '-';
6730 if (env->crf[i] & 0x08)
6731 a = 'L';
6732 else if (env->crf[i] & 0x04)
6733 a = 'G';
6734 else if (env->crf[i] & 0x02)
6735 a = 'E';
6736 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
6737 }
6738 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
6739 env->reserve_addr);
6740 for (i = 0; i < 32; i++) {
6741 if ((i & (RFPL - 1)) == 0)
6742 cpu_fprintf(f, "FPR%02d", i);
6743 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
6744 if ((i & (RFPL - 1)) == (RFPL - 1))
6745 cpu_fprintf(f, "\n");
6746 }
6747 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
6748 #if !defined(CONFIG_USER_ONLY)
6749 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
6750 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
6751 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
6752 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
6753
6754 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
6755 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
6756 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
6757 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
6758
6759 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
6760 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
6761 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
6762 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
6763
6764 #if defined(TARGET_PPC64)
6765 if (env->excp_model == POWERPC_EXCP_POWER7 ||
6766 env->excp_model == POWERPC_EXCP_POWER8) {
6767 cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
6768 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
6769 }
6770 #endif
6771 if (env->excp_model == POWERPC_EXCP_BOOKE) {
6772 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
6773 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
6774 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
6775 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
6776
6777 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
6778 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
6779 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
6780 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
6781
6782 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
6783 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
6784 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
6785 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
6786
6787 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
6788 " EPR " TARGET_FMT_lx "\n",
6789 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
6790 env->spr[SPR_BOOKE_EPR]);
6791
6792 /* FSL-specific */
6793 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
6794 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
6795 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
6796 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
6797
6798 /*
6799 * IVORs are left out as they are large and do not change often --
6800 * they can be read with "p $ivor0", "p $ivor1", etc.
6801 */
6802 }
6803
6804 #if defined(TARGET_PPC64)
6805 if (env->flags & POWERPC_FLAG_CFAR) {
6806 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
6807 }
6808 #endif
6809
6810 switch (env->mmu_model) {
6811 case POWERPC_MMU_32B:
6812 case POWERPC_MMU_601:
6813 case POWERPC_MMU_SOFT_6xx:
6814 case POWERPC_MMU_SOFT_74xx:
6815 #if defined(TARGET_PPC64)
6816 case POWERPC_MMU_64B:
6817 case POWERPC_MMU_2_03:
6818 case POWERPC_MMU_2_06:
6819 case POWERPC_MMU_2_06a:
6820 case POWERPC_MMU_2_07:
6821 case POWERPC_MMU_2_07a:
6822 #endif
6823 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
6824 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
6825 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
6826 break;
6827 case POWERPC_MMU_BOOKE206:
6828 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
6829 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
6830 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
6831 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
6832
6833 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
6834 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
6835 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
6836 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
6837
6838 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
6839 " TLB1CFG " TARGET_FMT_lx "\n",
6840 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
6841 env->spr[SPR_BOOKE_TLB1CFG]);
6842 break;
6843 default:
6844 break;
6845 }
6846 #endif
6847
6848 #undef RGPL
6849 #undef RFPL
6850 }
6851
6852 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
6853 fprintf_function cpu_fprintf, int flags)
6854 {
6855 #if defined(DO_PPC_STATISTICS)
6856 PowerPCCPU *cpu = POWERPC_CPU(cs);
6857 opc_handler_t **t1, **t2, **t3, *handler;
6858 int op1, op2, op3;
6859
6860 t1 = cpu->env.opcodes;
6861 for (op1 = 0; op1 < 64; op1++) {
6862 handler = t1[op1];
6863 if (is_indirect_opcode(handler)) {
6864 t2 = ind_table(handler);
6865 for (op2 = 0; op2 < 32; op2++) {
6866 handler = t2[op2];
6867 if (is_indirect_opcode(handler)) {
6868 t3 = ind_table(handler);
6869 for (op3 = 0; op3 < 32; op3++) {
6870 handler = t3[op3];
6871 if (handler->count == 0)
6872 continue;
6873 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6874 "%016" PRIx64 " %" PRId64 "\n",
6875 op1, op2, op3, op1, (op3 << 5) | op2,
6876 handler->oname,
6877 handler->count, handler->count);
6878 }
6879 } else {
6880 if (handler->count == 0)
6881 continue;
6882 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6883 "%016" PRIx64 " %" PRId64 "\n",
6884 op1, op2, op1, op2, handler->oname,
6885 handler->count, handler->count);
6886 }
6887 }
6888 } else {
6889 if (handler->count == 0)
6890 continue;
6891 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
6892 " %" PRId64 "\n",
6893 op1, op1, handler->oname,
6894 handler->count, handler->count);
6895 }
6896 }
6897 #endif
6898 }
6899
6900 /*****************************************************************************/
6901 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
6902 {
6903 PowerPCCPU *cpu = ppc_env_get_cpu(env);
6904 CPUState *cs = CPU(cpu);
6905 DisasContext ctx, *ctxp = &ctx;
6906 opc_handler_t **table, *handler;
6907 target_ulong pc_start;
6908 int num_insns;
6909 int max_insns;
6910
6911 pc_start = tb->pc;
6912 ctx.nip = pc_start;
6913 ctx.tb = tb;
6914 ctx.exception = POWERPC_EXCP_NONE;
6915 ctx.spr_cb = env->spr_cb;
6916 ctx.pr = msr_pr;
6917 ctx.mem_idx = env->dmmu_idx;
6918 ctx.dr = msr_dr;
6919 #if !defined(CONFIG_USER_ONLY)
6920 ctx.hv = msr_hv || !env->has_hv_mode;
6921 #endif
6922 ctx.insns_flags = env->insns_flags;
6923 ctx.insns_flags2 = env->insns_flags2;
6924 ctx.access_type = -1;
6925 ctx.le_mode = !!(env->hflags & (1 << MSR_LE));
6926 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
6927 #if defined(TARGET_PPC64)
6928 ctx.sf_mode = msr_is_64bit(env, env->msr);
6929 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
6930 #endif
6931 if (env->mmu_model == POWERPC_MMU_32B ||
6932 env->mmu_model == POWERPC_MMU_601 ||
6933 (env->mmu_model & POWERPC_MMU_64B))
6934 ctx.lazy_tlb_flush = true;
6935
6936 ctx.fpu_enabled = !!msr_fp;
6937 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
6938 ctx.spe_enabled = !!msr_spe;
6939 else
6940 ctx.spe_enabled = false;
6941 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
6942 ctx.altivec_enabled = !!msr_vr;
6943 else
6944 ctx.altivec_enabled = false;
6945 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
6946 ctx.vsx_enabled = !!msr_vsx;
6947 } else {
6948 ctx.vsx_enabled = false;
6949 }
6950 #if defined(TARGET_PPC64)
6951 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
6952 ctx.tm_enabled = !!msr_tm;
6953 } else {
6954 ctx.tm_enabled = false;
6955 }
6956 #endif
6957 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
6958 ctx.singlestep_enabled = CPU_SINGLE_STEP;
6959 else
6960 ctx.singlestep_enabled = 0;
6961 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
6962 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
6963 if (unlikely(cs->singlestep_enabled)) {
6964 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
6965 }
6966 #if defined (DO_SINGLE_STEP) && 0
6967 /* Single step trace mode */
6968 msr_se = 1;
6969 #endif
6970 num_insns = 0;
6971 max_insns = tb->cflags & CF_COUNT_MASK;
6972 if (max_insns == 0) {
6973 max_insns = CF_COUNT_MASK;
6974 }
6975 if (max_insns > TCG_MAX_INSNS) {
6976 max_insns = TCG_MAX_INSNS;
6977 }
6978
6979 gen_tb_start(tb);
6980 tcg_clear_temp_count();
6981 /* Set env in case of segfault during code fetch */
6982 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
6983 tcg_gen_insn_start(ctx.nip);
6984 num_insns++;
6985
6986 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
6987 gen_debug_exception(ctxp);
6988 /* The address covered by the breakpoint must be included in
6989 [tb->pc, tb->pc + tb->size) in order to for it to be
6990 properly cleared -- thus we increment the PC here so that
6991 the logic setting tb->size below does the right thing. */
6992 ctx.nip += 4;
6993 break;
6994 }
6995
6996 LOG_DISAS("----------------\n");
6997 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
6998 ctx.nip, ctx.mem_idx, (int)msr_ir);
6999 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
7000 gen_io_start();
7001 if (unlikely(need_byteswap(&ctx))) {
7002 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
7003 } else {
7004 ctx.opcode = cpu_ldl_code(env, ctx.nip);
7005 }
7006 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7007 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
7008 opc3(ctx.opcode), opc4(ctx.opcode),
7009 ctx.le_mode ? "little" : "big");
7010 ctx.nip += 4;
7011 table = env->opcodes;
7012 handler = table[opc1(ctx.opcode)];
7013 if (is_indirect_opcode(handler)) {
7014 table = ind_table(handler);
7015 handler = table[opc2(ctx.opcode)];
7016 if (is_indirect_opcode(handler)) {
7017 table = ind_table(handler);
7018 handler = table[opc3(ctx.opcode)];
7019 if (is_indirect_opcode(handler)) {
7020 table = ind_table(handler);
7021 handler = table[opc4(ctx.opcode)];
7022 }
7023 }
7024 }
7025 /* Is opcode *REALLY* valid ? */
7026 if (unlikely(handler->handler == &gen_invalid)) {
7027 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
7028 "%02x - %02x - %02x - %02x (%08x) "
7029 TARGET_FMT_lx " %d\n",
7030 opc1(ctx.opcode), opc2(ctx.opcode),
7031 opc3(ctx.opcode), opc4(ctx.opcode),
7032 ctx.opcode, ctx.nip - 4, (int)msr_ir);
7033 } else {
7034 uint32_t inval;
7035
7036 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
7037 inval = handler->inval2;
7038 } else {
7039 inval = handler->inval1;
7040 }
7041
7042 if (unlikely((ctx.opcode & inval) != 0)) {
7043 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
7044 "%02x - %02x - %02x - %02x (%08x) "
7045 TARGET_FMT_lx "\n", ctx.opcode & inval,
7046 opc1(ctx.opcode), opc2(ctx.opcode),
7047 opc3(ctx.opcode), opc4(ctx.opcode),
7048 ctx.opcode, ctx.nip - 4);
7049 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
7050 break;
7051 }
7052 }
7053 (*(handler->handler))(&ctx);
7054 #if defined(DO_PPC_STATISTICS)
7055 handler->count++;
7056 #endif
7057 /* Check trace mode exceptions */
7058 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7059 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7060 ctx.exception != POWERPC_SYSCALL &&
7061 ctx.exception != POWERPC_EXCP_TRAP &&
7062 ctx.exception != POWERPC_EXCP_BRANCH)) {
7063 gen_exception(ctxp, POWERPC_EXCP_TRACE);
7064 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
7065 (cs->singlestep_enabled) ||
7066 singlestep ||
7067 num_insns >= max_insns)) {
7068 /* if we reach a page boundary or are single stepping, stop
7069 * generation
7070 */
7071 break;
7072 }
7073 if (tcg_check_temp_count()) {
7074 fprintf(stderr, "Opcode %02x %02x %02x %02x (%08x) leaked "
7075 "temporaries\n", opc1(ctx.opcode), opc2(ctx.opcode),
7076 opc3(ctx.opcode), opc4(ctx.opcode), ctx.opcode);
7077 exit(1);
7078 }
7079 }
7080 if (tb->cflags & CF_LAST_IO)
7081 gen_io_end();
7082 if (ctx.exception == POWERPC_EXCP_NONE) {
7083 gen_goto_tb(&ctx, 0, ctx.nip);
7084 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
7085 if (unlikely(cs->singlestep_enabled)) {
7086 gen_debug_exception(ctxp);
7087 }
7088 /* Generate the return instruction */
7089 tcg_gen_exit_tb(0);
7090 }
7091 gen_tb_end(tb, num_insns);
7092
7093 tb->size = ctx.nip - pc_start;
7094 tb->icount = num_insns;
7095
7096 #if defined(DEBUG_DISAS)
7097 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
7098 && qemu_log_in_addr_range(pc_start)) {
7099 int flags;
7100 flags = env->bfd_mach;
7101 flags |= ctx.le_mode << 16;
7102 qemu_log("IN: %s\n", lookup_symbol(pc_start));
7103 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
7104 qemu_log("\n");
7105 }
7106 #endif
7107 }
7108
7109 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
7110 target_ulong *data)
7111 {
7112 env->nip = data[0];
7113 }
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