2 * PowerPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
26 #include "qemu/host-utils.h"
27 #include "exec/cpu_ldst.h"
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
32 #include "trace-tcg.h"
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
40 /* Include definitions for instructions classes and implementations flags */
41 //#define PPC_DEBUG_DISAS
42 //#define DO_PPC_STATISTICS
44 #ifdef PPC_DEBUG_DISAS
45 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
47 # define LOG_DISAS(...) do { } while (0)
49 /*****************************************************************************/
50 /* Code translation helpers */
52 /* global register indexes */
53 static TCGv_env cpu_env
;
54 static char cpu_reg_names
[10*3 + 22*4 /* GPR */
55 + 10*4 + 22*5 /* SPE GPRh */
56 + 10*4 + 22*5 /* FPR */
57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
58 + 10*5 + 22*6 /* VSR */
60 static TCGv cpu_gpr
[32];
61 static TCGv cpu_gprh
[32];
62 static TCGv_i64 cpu_fpr
[32];
63 static TCGv_i64 cpu_avrh
[32], cpu_avrl
[32];
64 static TCGv_i64 cpu_vsr
[32];
65 static TCGv_i32 cpu_crf
[8];
70 #if defined(TARGET_PPC64)
73 static TCGv cpu_xer
, cpu_so
, cpu_ov
, cpu_ca
;
74 static TCGv cpu_reserve
;
75 static TCGv cpu_fpscr
;
76 static TCGv_i32 cpu_access_type
;
78 #include "exec/gen-icount.h"
80 void ppc_translate_init(void)
84 size_t cpu_reg_names_size
;
85 static int done_init
= 0;
90 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
91 tcg_ctx
.tcg_env
= cpu_env
;
94 cpu_reg_names_size
= sizeof(cpu_reg_names
);
96 for (i
= 0; i
< 8; i
++) {
97 snprintf(p
, cpu_reg_names_size
, "crf%d", i
);
98 cpu_crf
[i
] = tcg_global_mem_new_i32(cpu_env
,
99 offsetof(CPUPPCState
, crf
[i
]), p
);
101 cpu_reg_names_size
-= 5;
104 for (i
= 0; i
< 32; i
++) {
105 snprintf(p
, cpu_reg_names_size
, "r%d", i
);
106 cpu_gpr
[i
] = tcg_global_mem_new(cpu_env
,
107 offsetof(CPUPPCState
, gpr
[i
]), p
);
108 p
+= (i
< 10) ? 3 : 4;
109 cpu_reg_names_size
-= (i
< 10) ? 3 : 4;
110 snprintf(p
, cpu_reg_names_size
, "r%dH", i
);
111 cpu_gprh
[i
] = tcg_global_mem_new(cpu_env
,
112 offsetof(CPUPPCState
, gprh
[i
]), p
);
113 p
+= (i
< 10) ? 4 : 5;
114 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
116 snprintf(p
, cpu_reg_names_size
, "fp%d", i
);
117 cpu_fpr
[i
] = tcg_global_mem_new_i64(cpu_env
,
118 offsetof(CPUPPCState
, fpr
[i
]), p
);
119 p
+= (i
< 10) ? 4 : 5;
120 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
122 snprintf(p
, cpu_reg_names_size
, "avr%dH", i
);
123 #ifdef HOST_WORDS_BIGENDIAN
124 cpu_avrh
[i
] = tcg_global_mem_new_i64(cpu_env
,
125 offsetof(CPUPPCState
, avr
[i
].u64
[0]), p
);
127 cpu_avrh
[i
] = tcg_global_mem_new_i64(cpu_env
,
128 offsetof(CPUPPCState
, avr
[i
].u64
[1]), p
);
130 p
+= (i
< 10) ? 6 : 7;
131 cpu_reg_names_size
-= (i
< 10) ? 6 : 7;
133 snprintf(p
, cpu_reg_names_size
, "avr%dL", i
);
134 #ifdef HOST_WORDS_BIGENDIAN
135 cpu_avrl
[i
] = tcg_global_mem_new_i64(cpu_env
,
136 offsetof(CPUPPCState
, avr
[i
].u64
[1]), p
);
138 cpu_avrl
[i
] = tcg_global_mem_new_i64(cpu_env
,
139 offsetof(CPUPPCState
, avr
[i
].u64
[0]), p
);
141 p
+= (i
< 10) ? 6 : 7;
142 cpu_reg_names_size
-= (i
< 10) ? 6 : 7;
143 snprintf(p
, cpu_reg_names_size
, "vsr%d", i
);
144 cpu_vsr
[i
] = tcg_global_mem_new_i64(cpu_env
,
145 offsetof(CPUPPCState
, vsr
[i
]), p
);
146 p
+= (i
< 10) ? 5 : 6;
147 cpu_reg_names_size
-= (i
< 10) ? 5 : 6;
150 cpu_nip
= tcg_global_mem_new(cpu_env
,
151 offsetof(CPUPPCState
, nip
), "nip");
153 cpu_msr
= tcg_global_mem_new(cpu_env
,
154 offsetof(CPUPPCState
, msr
), "msr");
156 cpu_ctr
= tcg_global_mem_new(cpu_env
,
157 offsetof(CPUPPCState
, ctr
), "ctr");
159 cpu_lr
= tcg_global_mem_new(cpu_env
,
160 offsetof(CPUPPCState
, lr
), "lr");
162 #if defined(TARGET_PPC64)
163 cpu_cfar
= tcg_global_mem_new(cpu_env
,
164 offsetof(CPUPPCState
, cfar
), "cfar");
167 cpu_xer
= tcg_global_mem_new(cpu_env
,
168 offsetof(CPUPPCState
, xer
), "xer");
169 cpu_so
= tcg_global_mem_new(cpu_env
,
170 offsetof(CPUPPCState
, so
), "SO");
171 cpu_ov
= tcg_global_mem_new(cpu_env
,
172 offsetof(CPUPPCState
, ov
), "OV");
173 cpu_ca
= tcg_global_mem_new(cpu_env
,
174 offsetof(CPUPPCState
, ca
), "CA");
176 cpu_reserve
= tcg_global_mem_new(cpu_env
,
177 offsetof(CPUPPCState
, reserve_addr
),
180 cpu_fpscr
= tcg_global_mem_new(cpu_env
,
181 offsetof(CPUPPCState
, fpscr
), "fpscr");
183 cpu_access_type
= tcg_global_mem_new_i32(cpu_env
,
184 offsetof(CPUPPCState
, access_type
), "access_type");
189 /* internal defines */
190 struct DisasContext
{
191 struct TranslationBlock
*tb
;
195 /* Routine used to access memory */
196 bool pr
, hv
, dr
, le_mode
;
200 /* Translation flags */
201 TCGMemOp default_tcg_memop_mask
;
202 #if defined(TARGET_PPC64)
207 bool altivec_enabled
;
211 ppc_spr_t
*spr_cb
; /* Needed to check rights for mfspr/mtspr */
212 int singlestep_enabled
;
213 uint64_t insns_flags
;
214 uint64_t insns_flags2
;
217 /* Return true iff byteswap is needed in a scalar memop */
218 static inline bool need_byteswap(const DisasContext
*ctx
)
220 #if defined(TARGET_WORDS_BIGENDIAN)
223 return !ctx
->le_mode
;
227 /* True when active word size < size of target_long. */
229 # define NARROW_MODE(C) (!(C)->sf_mode)
231 # define NARROW_MODE(C) 0
234 struct opc_handler_t
{
235 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
237 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
239 /* instruction type */
241 /* extended instruction type */
244 void (*handler
)(DisasContext
*ctx
);
245 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
248 #if defined(DO_PPC_STATISTICS)
253 static inline void gen_set_access_type(DisasContext
*ctx
, int access_type
)
255 if (ctx
->access_type
!= access_type
) {
256 tcg_gen_movi_i32(cpu_access_type
, access_type
);
257 ctx
->access_type
= access_type
;
261 static inline void gen_update_nip(DisasContext
*ctx
, target_ulong nip
)
263 if (NARROW_MODE(ctx
)) {
266 tcg_gen_movi_tl(cpu_nip
, nip
);
269 void gen_update_current_nip(void *opaque
)
271 DisasContext
*ctx
= opaque
;
273 tcg_gen_movi_tl(cpu_nip
, ctx
->nip
);
276 static void gen_exception_err(DisasContext
*ctx
, uint32_t excp
, uint32_t error
)
279 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
280 gen_update_nip(ctx
, ctx
->nip
);
282 t0
= tcg_const_i32(excp
);
283 t1
= tcg_const_i32(error
);
284 gen_helper_raise_exception_err(cpu_env
, t0
, t1
);
285 tcg_temp_free_i32(t0
);
286 tcg_temp_free_i32(t1
);
287 ctx
->exception
= (excp
);
290 static void gen_exception(DisasContext
*ctx
, uint32_t excp
)
293 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
294 gen_update_nip(ctx
, ctx
->nip
);
296 t0
= tcg_const_i32(excp
);
297 gen_helper_raise_exception(cpu_env
, t0
);
298 tcg_temp_free_i32(t0
);
299 ctx
->exception
= (excp
);
302 static void gen_debug_exception(DisasContext
*ctx
)
306 if ((ctx
->exception
!= POWERPC_EXCP_BRANCH
) &&
307 (ctx
->exception
!= POWERPC_EXCP_SYNC
)) {
308 gen_update_nip(ctx
, ctx
->nip
);
310 t0
= tcg_const_i32(EXCP_DEBUG
);
311 gen_helper_raise_exception(cpu_env
, t0
);
312 tcg_temp_free_i32(t0
);
315 static inline void gen_inval_exception(DisasContext
*ctx
, uint32_t error
)
317 /* Will be converted to program check if needed */
318 gen_exception_err(ctx
, POWERPC_EXCP_HV_EMU
, POWERPC_EXCP_INVAL
| error
);
321 static inline void gen_priv_exception(DisasContext
*ctx
, uint32_t error
)
323 gen_exception_err(ctx
, POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_PRIV
| error
);
326 static inline void gen_hvpriv_exception(DisasContext
*ctx
, uint32_t error
)
328 /* Will be converted to program check if needed */
329 gen_exception_err(ctx
, POWERPC_EXCP_HV_EMU
, POWERPC_EXCP_PRIV
| error
);
332 /* Stop translation */
333 static inline void gen_stop_exception(DisasContext
*ctx
)
335 gen_update_nip(ctx
, ctx
->nip
);
336 ctx
->exception
= POWERPC_EXCP_STOP
;
339 #ifndef CONFIG_USER_ONLY
340 /* No need to update nip here, as execution flow will change */
341 static inline void gen_sync_exception(DisasContext
*ctx
)
343 ctx
->exception
= POWERPC_EXCP_SYNC
;
347 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
348 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
350 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
351 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
353 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
354 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
356 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
357 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
359 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
360 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
362 typedef struct opcode_t
{
363 unsigned char opc1
, opc2
, opc3
, opc4
;
364 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
365 unsigned char pad
[4];
367 opc_handler_t handler
;
371 /* Helpers for priv. check */
374 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
377 #if defined(CONFIG_USER_ONLY)
378 #define CHK_HV GEN_PRIV
379 #define CHK_SV GEN_PRIV
380 #define CHK_HVRM GEN_PRIV
384 if (unlikely(ctx->pr || !ctx->hv)) { \
390 if (unlikely(ctx->pr)) { \
396 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
405 /*****************************************************************************/
406 /*** Instruction decoding ***/
407 #define EXTRACT_HELPER(name, shift, nb) \
408 static inline uint32_t name(uint32_t opcode) \
410 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
413 #define EXTRACT_SHELPER(name, shift, nb) \
414 static inline int32_t name(uint32_t opcode) \
416 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
419 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
420 static inline uint32_t name(uint32_t opcode) \
422 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
423 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
426 #define EXTRACT_HELPER_DXFORM(name, \
427 d0_bits, shift_op_d0, shift_d0, \
428 d1_bits, shift_op_d1, shift_d1, \
429 d2_bits, shift_op_d2, shift_d2) \
430 static inline int16_t name(uint32_t opcode) \
433 (((opcode >> (shift_op_d0)) & ((1 << (d0_bits)) - 1)) << (shift_d0)) | \
434 (((opcode >> (shift_op_d1)) & ((1 << (d1_bits)) - 1)) << (shift_d1)) | \
435 (((opcode >> (shift_op_d2)) & ((1 << (d2_bits)) - 1)) << (shift_d2)); \
440 EXTRACT_HELPER(opc1
, 26, 6);
442 EXTRACT_HELPER(opc2
, 1, 5);
444 EXTRACT_HELPER(opc3
, 6, 5);
446 EXTRACT_HELPER(opc4
, 16, 5);
447 /* Update Cr0 flags */
448 EXTRACT_HELPER(Rc
, 0, 1);
449 /* Update Cr6 flags (Altivec) */
450 EXTRACT_HELPER(Rc21
, 10, 1);
452 EXTRACT_HELPER(rD
, 21, 5);
454 EXTRACT_HELPER(rS
, 21, 5);
456 EXTRACT_HELPER(rA
, 16, 5);
458 EXTRACT_HELPER(rB
, 11, 5);
460 EXTRACT_HELPER(rC
, 6, 5);
462 EXTRACT_HELPER(crfD
, 23, 3);
463 EXTRACT_HELPER(crfS
, 18, 3);
464 EXTRACT_HELPER(crbD
, 21, 5);
465 EXTRACT_HELPER(crbA
, 16, 5);
466 EXTRACT_HELPER(crbB
, 11, 5);
468 EXTRACT_HELPER(_SPR
, 11, 10);
469 static inline uint32_t SPR(uint32_t opcode
)
471 uint32_t sprn
= _SPR(opcode
);
473 return ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
475 /*** Get constants ***/
476 /* 16 bits signed immediate value */
477 EXTRACT_SHELPER(SIMM
, 0, 16);
478 /* 16 bits unsigned immediate value */
479 EXTRACT_HELPER(UIMM
, 0, 16);
480 /* 5 bits signed immediate value */
481 EXTRACT_HELPER(SIMM5
, 16, 5);
482 /* 5 bits signed immediate value */
483 EXTRACT_HELPER(UIMM5
, 16, 5);
485 EXTRACT_HELPER(NB
, 11, 5);
487 EXTRACT_HELPER(SH
, 11, 5);
488 /* Vector shift count */
489 EXTRACT_HELPER(VSH
, 6, 4);
491 EXTRACT_HELPER(MB
, 6, 5);
493 EXTRACT_HELPER(ME
, 1, 5);
495 EXTRACT_HELPER(TO
, 21, 5);
497 EXTRACT_HELPER(CRM
, 12, 8);
499 #ifndef CONFIG_USER_ONLY
500 EXTRACT_HELPER(SR
, 16, 4);
504 EXTRACT_HELPER(FPBF
, 23, 3);
505 EXTRACT_HELPER(FPIMM
, 12, 4);
506 EXTRACT_HELPER(FPL
, 25, 1);
507 EXTRACT_HELPER(FPFLM
, 17, 8);
508 EXTRACT_HELPER(FPW
, 16, 1);
511 EXTRACT_HELPER_DXFORM(DX
, 10, 6, 6, 5, 16, 1, 1, 0, 0)
513 /*** Jump target decoding ***/
514 /* Immediate address */
515 static inline target_ulong
LI(uint32_t opcode
)
517 return (opcode
>> 0) & 0x03FFFFFC;
520 static inline uint32_t BD(uint32_t opcode
)
522 return (opcode
>> 0) & 0xFFFC;
525 EXTRACT_HELPER(BO
, 21, 5);
526 EXTRACT_HELPER(BI
, 16, 5);
527 /* Absolute/relative address */
528 EXTRACT_HELPER(AA
, 1, 1);
530 EXTRACT_HELPER(LK
, 0, 1);
533 EXTRACT_HELPER(DCM
, 10, 6)
536 EXTRACT_HELPER(RMC
, 9, 2)
538 /* Create a mask between <start> and <end> bits */
539 static inline target_ulong
MASK(uint32_t start
, uint32_t end
)
543 #if defined(TARGET_PPC64)
544 if (likely(start
== 0)) {
545 ret
= UINT64_MAX
<< (63 - end
);
546 } else if (likely(end
== 63)) {
547 ret
= UINT64_MAX
>> start
;
550 if (likely(start
== 0)) {
551 ret
= UINT32_MAX
<< (31 - end
);
552 } else if (likely(end
== 31)) {
553 ret
= UINT32_MAX
>> start
;
557 ret
= (((target_ulong
)(-1ULL)) >> (start
)) ^
558 (((target_ulong
)(-1ULL) >> (end
)) >> 1);
559 if (unlikely(start
> end
))
566 EXTRACT_HELPER_SPLIT(xT
, 0, 1, 21, 5);
567 EXTRACT_HELPER_SPLIT(xS
, 0, 1, 21, 5);
568 EXTRACT_HELPER_SPLIT(xA
, 2, 1, 16, 5);
569 EXTRACT_HELPER_SPLIT(xB
, 1, 1, 11, 5);
570 EXTRACT_HELPER_SPLIT(xC
, 3, 1, 6, 5);
571 EXTRACT_HELPER(DM
, 8, 2);
572 EXTRACT_HELPER(UIM
, 16, 2);
573 EXTRACT_HELPER(SHW
, 8, 2);
574 EXTRACT_HELPER(SP
, 19, 2);
575 /*****************************************************************************/
576 /* PowerPC instructions table */
578 #if defined(DO_PPC_STATISTICS)
579 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
589 .handler = &gen_##name, \
590 .oname = stringify(name), \
592 .oname = stringify(name), \
594 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
605 .handler = &gen_##name, \
606 .oname = stringify(name), \
608 .oname = stringify(name), \
610 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
620 .handler = &gen_##name, \
625 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
635 .handler = &gen_##name, \
636 .oname = stringify(name), \
638 .oname = stringify(name), \
641 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
651 .handler = &gen_##name, \
653 .oname = stringify(name), \
655 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
666 .handler = &gen_##name, \
668 .oname = stringify(name), \
670 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
680 .handler = &gen_##name, \
684 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
694 .handler = &gen_##name, \
696 .oname = stringify(name), \
700 /* SPR load/store helpers */
701 static inline void gen_load_spr(TCGv t
, int reg
)
703 tcg_gen_ld_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
706 static inline void gen_store_spr(int reg
, TCGv t
)
708 tcg_gen_st_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
711 /* Invalid instruction */
712 static void gen_invalid(DisasContext
*ctx
)
714 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
717 static opc_handler_t invalid_handler
= {
718 .inval1
= 0xFFFFFFFF,
719 .inval2
= 0xFFFFFFFF,
722 .handler
= gen_invalid
,
725 /*** Integer comparison ***/
727 static inline void gen_op_cmp(TCGv arg0
, TCGv arg1
, int s
, int crf
)
729 TCGv t0
= tcg_temp_new();
730 TCGv_i32 t1
= tcg_temp_new_i32();
732 tcg_gen_trunc_tl_i32(cpu_crf
[crf
], cpu_so
);
734 tcg_gen_setcond_tl((s
? TCG_COND_LT
: TCG_COND_LTU
), t0
, arg0
, arg1
);
735 tcg_gen_trunc_tl_i32(t1
, t0
);
736 tcg_gen_shli_i32(t1
, t1
, CRF_LT
);
737 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
739 tcg_gen_setcond_tl((s
? TCG_COND_GT
: TCG_COND_GTU
), t0
, arg0
, arg1
);
740 tcg_gen_trunc_tl_i32(t1
, t0
);
741 tcg_gen_shli_i32(t1
, t1
, CRF_GT
);
742 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
744 tcg_gen_setcond_tl(TCG_COND_EQ
, t0
, arg0
, arg1
);
745 tcg_gen_trunc_tl_i32(t1
, t0
);
746 tcg_gen_shli_i32(t1
, t1
, CRF_EQ
);
747 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
750 tcg_temp_free_i32(t1
);
753 static inline void gen_op_cmpi(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
755 TCGv t0
= tcg_const_tl(arg1
);
756 gen_op_cmp(arg0
, t0
, s
, crf
);
760 static inline void gen_op_cmp32(TCGv arg0
, TCGv arg1
, int s
, int crf
)
766 tcg_gen_ext32s_tl(t0
, arg0
);
767 tcg_gen_ext32s_tl(t1
, arg1
);
769 tcg_gen_ext32u_tl(t0
, arg0
);
770 tcg_gen_ext32u_tl(t1
, arg1
);
772 gen_op_cmp(t0
, t1
, s
, crf
);
777 static inline void gen_op_cmpi32(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
779 TCGv t0
= tcg_const_tl(arg1
);
780 gen_op_cmp32(arg0
, t0
, s
, crf
);
784 static inline void gen_set_Rc0(DisasContext
*ctx
, TCGv reg
)
786 if (NARROW_MODE(ctx
)) {
787 gen_op_cmpi32(reg
, 0, 1, 0);
789 gen_op_cmpi(reg
, 0, 1, 0);
794 static void gen_cmp(DisasContext
*ctx
)
796 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
797 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
798 1, crfD(ctx
->opcode
));
800 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
801 1, crfD(ctx
->opcode
));
806 static void gen_cmpi(DisasContext
*ctx
)
808 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
809 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
810 1, crfD(ctx
->opcode
));
812 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
813 1, crfD(ctx
->opcode
));
818 static void gen_cmpl(DisasContext
*ctx
)
820 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
821 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
822 0, crfD(ctx
->opcode
));
824 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
825 0, crfD(ctx
->opcode
));
830 static void gen_cmpli(DisasContext
*ctx
)
832 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
833 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
834 0, crfD(ctx
->opcode
));
836 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
837 0, crfD(ctx
->opcode
));
841 /* cmprb - range comparison: isupper, isaplha, islower*/
842 static void gen_cmprb(DisasContext
*ctx
)
844 TCGv_i32 src1
= tcg_temp_new_i32();
845 TCGv_i32 src2
= tcg_temp_new_i32();
846 TCGv_i32 src2lo
= tcg_temp_new_i32();
847 TCGv_i32 src2hi
= tcg_temp_new_i32();
848 TCGv_i32 crf
= cpu_crf
[crfD(ctx
->opcode
)];
850 tcg_gen_trunc_tl_i32(src1
, cpu_gpr
[rA(ctx
->opcode
)]);
851 tcg_gen_trunc_tl_i32(src2
, cpu_gpr
[rB(ctx
->opcode
)]);
853 tcg_gen_andi_i32(src1
, src1
, 0xFF);
854 tcg_gen_ext8u_i32(src2lo
, src2
);
855 tcg_gen_shri_i32(src2
, src2
, 8);
856 tcg_gen_ext8u_i32(src2hi
, src2
);
858 tcg_gen_setcond_i32(TCG_COND_LEU
, src2lo
, src2lo
, src1
);
859 tcg_gen_setcond_i32(TCG_COND_LEU
, src2hi
, src1
, src2hi
);
860 tcg_gen_and_i32(crf
, src2lo
, src2hi
);
862 if (ctx
->opcode
& 0x00200000) {
863 tcg_gen_shri_i32(src2
, src2
, 8);
864 tcg_gen_ext8u_i32(src2lo
, src2
);
865 tcg_gen_shri_i32(src2
, src2
, 8);
866 tcg_gen_ext8u_i32(src2hi
, src2
);
867 tcg_gen_setcond_i32(TCG_COND_LEU
, src2lo
, src2lo
, src1
);
868 tcg_gen_setcond_i32(TCG_COND_LEU
, src2hi
, src1
, src2hi
);
869 tcg_gen_and_i32(src2lo
, src2lo
, src2hi
);
870 tcg_gen_or_i32(crf
, crf
, src2lo
);
872 tcg_gen_shli_i32(crf
, crf
, CRF_GT
);
873 tcg_temp_free_i32(src1
);
874 tcg_temp_free_i32(src2
);
875 tcg_temp_free_i32(src2lo
);
876 tcg_temp_free_i32(src2hi
);
879 #if defined(TARGET_PPC64)
881 static void gen_cmpeqb(DisasContext
*ctx
)
883 gen_helper_cmpeqb(cpu_crf
[crfD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
884 cpu_gpr
[rB(ctx
->opcode
)]);
888 /* isel (PowerPC 2.03 specification) */
889 static void gen_isel(DisasContext
*ctx
)
891 uint32_t bi
= rC(ctx
->opcode
);
892 uint32_t mask
= 0x08 >> (bi
& 0x03);
893 TCGv t0
= tcg_temp_new();
896 tcg_gen_extu_i32_tl(t0
, cpu_crf
[bi
>> 2]);
897 tcg_gen_andi_tl(t0
, t0
, mask
);
899 zr
= tcg_const_tl(0);
900 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_gpr
[rD(ctx
->opcode
)], t0
, zr
,
901 rA(ctx
->opcode
) ? cpu_gpr
[rA(ctx
->opcode
)] : zr
,
902 cpu_gpr
[rB(ctx
->opcode
)]);
907 /* cmpb: PowerPC 2.05 specification */
908 static void gen_cmpb(DisasContext
*ctx
)
910 gen_helper_cmpb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
911 cpu_gpr
[rB(ctx
->opcode
)]);
914 /*** Integer arithmetic ***/
916 static inline void gen_op_arith_compute_ov(DisasContext
*ctx
, TCGv arg0
,
917 TCGv arg1
, TCGv arg2
, int sub
)
919 TCGv t0
= tcg_temp_new();
921 tcg_gen_xor_tl(cpu_ov
, arg0
, arg2
);
922 tcg_gen_xor_tl(t0
, arg1
, arg2
);
924 tcg_gen_and_tl(cpu_ov
, cpu_ov
, t0
);
926 tcg_gen_andc_tl(cpu_ov
, cpu_ov
, t0
);
929 if (NARROW_MODE(ctx
)) {
930 tcg_gen_ext32s_tl(cpu_ov
, cpu_ov
);
932 tcg_gen_shri_tl(cpu_ov
, cpu_ov
, TARGET_LONG_BITS
- 1);
933 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
936 /* Common add function */
937 static inline void gen_op_arith_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
938 TCGv arg2
, bool add_ca
, bool compute_ca
,
939 bool compute_ov
, bool compute_rc0
)
943 if (compute_ca
|| compute_ov
) {
948 if (NARROW_MODE(ctx
)) {
949 /* Caution: a non-obvious corner case of the spec is that we
950 must produce the *entire* 64-bit addition, but produce the
951 carry into bit 32. */
952 TCGv t1
= tcg_temp_new();
953 tcg_gen_xor_tl(t1
, arg1
, arg2
); /* add without carry */
954 tcg_gen_add_tl(t0
, arg1
, arg2
);
956 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
958 tcg_gen_xor_tl(cpu_ca
, t0
, t1
); /* bits changed w/ carry */
960 tcg_gen_shri_tl(cpu_ca
, cpu_ca
, 32); /* extract bit 32 */
961 tcg_gen_andi_tl(cpu_ca
, cpu_ca
, 1);
963 TCGv zero
= tcg_const_tl(0);
965 tcg_gen_add2_tl(t0
, cpu_ca
, arg1
, zero
, cpu_ca
, zero
);
966 tcg_gen_add2_tl(t0
, cpu_ca
, t0
, cpu_ca
, arg2
, zero
);
968 tcg_gen_add2_tl(t0
, cpu_ca
, arg1
, zero
, arg2
, zero
);
973 tcg_gen_add_tl(t0
, arg1
, arg2
);
975 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
980 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 0);
982 if (unlikely(compute_rc0
)) {
983 gen_set_Rc0(ctx
, t0
);
986 if (!TCGV_EQUAL(t0
, ret
)) {
987 tcg_gen_mov_tl(ret
, t0
);
991 /* Add functions with two operands */
992 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
993 static void glue(gen_, name)(DisasContext *ctx) \
995 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
996 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
997 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
999 /* Add functions with one operand and one immediate */
1000 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
1001 add_ca, compute_ca, compute_ov) \
1002 static void glue(gen_, name)(DisasContext *ctx) \
1004 TCGv t0 = tcg_const_tl(const_val); \
1005 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1006 cpu_gpr[rA(ctx->opcode)], t0, \
1007 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1008 tcg_temp_free(t0); \
1011 /* add add. addo addo. */
1012 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
1013 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
1014 /* addc addc. addco addco. */
1015 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
1016 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
1017 /* adde adde. addeo addeo. */
1018 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
1019 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
1020 /* addme addme. addmeo addmeo. */
1021 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
1022 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
1023 /* addze addze. addzeo addzeo.*/
1024 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
1025 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
1027 static void gen_addi(DisasContext
*ctx
)
1029 target_long simm
= SIMM(ctx
->opcode
);
1031 if (rA(ctx
->opcode
) == 0) {
1033 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
);
1035 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)],
1036 cpu_gpr
[rA(ctx
->opcode
)], simm
);
1040 static inline void gen_op_addic(DisasContext
*ctx
, bool compute_rc0
)
1042 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
1043 gen_op_arith_add(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1044 c
, 0, 1, 0, compute_rc0
);
1048 static void gen_addic(DisasContext
*ctx
)
1050 gen_op_addic(ctx
, 0);
1053 static void gen_addic_(DisasContext
*ctx
)
1055 gen_op_addic(ctx
, 1);
1059 static void gen_addis(DisasContext
*ctx
)
1061 target_long simm
= SIMM(ctx
->opcode
);
1063 if (rA(ctx
->opcode
) == 0) {
1065 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
<< 16);
1067 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)],
1068 cpu_gpr
[rA(ctx
->opcode
)], simm
<< 16);
1073 static void gen_addpcis(DisasContext
*ctx
)
1075 target_long d
= DX(ctx
->opcode
);
1077 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], ctx
->nip
+ (d
<< 16));
1080 static inline void gen_op_arith_divw(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1081 TCGv arg2
, int sign
, int compute_ov
)
1083 TCGLabel
*l1
= gen_new_label();
1084 TCGLabel
*l2
= gen_new_label();
1085 TCGv_i32 t0
= tcg_temp_local_new_i32();
1086 TCGv_i32 t1
= tcg_temp_local_new_i32();
1088 tcg_gen_trunc_tl_i32(t0
, arg1
);
1089 tcg_gen_trunc_tl_i32(t1
, arg2
);
1090 tcg_gen_brcondi_i32(TCG_COND_EQ
, t1
, 0, l1
);
1092 TCGLabel
*l3
= gen_new_label();
1093 tcg_gen_brcondi_i32(TCG_COND_NE
, t1
, -1, l3
);
1094 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, INT32_MIN
, l1
);
1096 tcg_gen_div_i32(t0
, t0
, t1
);
1098 tcg_gen_divu_i32(t0
, t0
, t1
);
1101 tcg_gen_movi_tl(cpu_ov
, 0);
1106 tcg_gen_sari_i32(t0
, t0
, 31);
1108 tcg_gen_movi_i32(t0
, 0);
1111 tcg_gen_movi_tl(cpu_ov
, 1);
1112 tcg_gen_movi_tl(cpu_so
, 1);
1115 tcg_gen_extu_i32_tl(ret
, t0
);
1116 tcg_temp_free_i32(t0
);
1117 tcg_temp_free_i32(t1
);
1118 if (unlikely(Rc(ctx
->opcode
) != 0))
1119 gen_set_Rc0(ctx
, ret
);
1122 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1123 static void glue(gen_, name)(DisasContext *ctx) \
1125 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1126 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1127 sign, compute_ov); \
1129 /* divwu divwu. divwuo divwuo. */
1130 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0);
1131 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1);
1132 /* divw divw. divwo divwo. */
1133 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0);
1134 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1);
1136 /* div[wd]eu[o][.] */
1137 #define GEN_DIVE(name, hlpr, compute_ov) \
1138 static void gen_##name(DisasContext *ctx) \
1140 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1141 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1142 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1143 tcg_temp_free_i32(t0); \
1144 if (unlikely(Rc(ctx->opcode) != 0)) { \
1145 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1149 GEN_DIVE(divweu
, divweu
, 0);
1150 GEN_DIVE(divweuo
, divweu
, 1);
1151 GEN_DIVE(divwe
, divwe
, 0);
1152 GEN_DIVE(divweo
, divwe
, 1);
1154 #if defined(TARGET_PPC64)
1155 static inline void gen_op_arith_divd(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1156 TCGv arg2
, int sign
, int compute_ov
)
1158 TCGLabel
*l1
= gen_new_label();
1159 TCGLabel
*l2
= gen_new_label();
1161 tcg_gen_brcondi_i64(TCG_COND_EQ
, arg2
, 0, l1
);
1163 TCGLabel
*l3
= gen_new_label();
1164 tcg_gen_brcondi_i64(TCG_COND_NE
, arg2
, -1, l3
);
1165 tcg_gen_brcondi_i64(TCG_COND_EQ
, arg1
, INT64_MIN
, l1
);
1167 tcg_gen_div_i64(ret
, arg1
, arg2
);
1169 tcg_gen_divu_i64(ret
, arg1
, arg2
);
1172 tcg_gen_movi_tl(cpu_ov
, 0);
1177 tcg_gen_sari_i64(ret
, arg1
, 63);
1179 tcg_gen_movi_i64(ret
, 0);
1182 tcg_gen_movi_tl(cpu_ov
, 1);
1183 tcg_gen_movi_tl(cpu_so
, 1);
1186 if (unlikely(Rc(ctx
->opcode
) != 0))
1187 gen_set_Rc0(ctx
, ret
);
1189 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1190 static void glue(gen_, name)(DisasContext *ctx) \
1192 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1193 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1194 sign, compute_ov); \
1196 /* divwu divwu. divwuo divwuo. */
1197 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0);
1198 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1);
1199 /* divw divw. divwo divwo. */
1200 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0);
1201 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1);
1203 GEN_DIVE(divdeu
, divdeu
, 0);
1204 GEN_DIVE(divdeuo
, divdeu
, 1);
1205 GEN_DIVE(divde
, divde
, 0);
1206 GEN_DIVE(divdeo
, divde
, 1);
1209 static inline void gen_op_arith_modw(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1210 TCGv arg2
, int sign
)
1212 TCGv_i32 t0
= tcg_temp_new_i32();
1213 TCGv_i32 t1
= tcg_temp_new_i32();
1215 tcg_gen_trunc_tl_i32(t0
, arg1
);
1216 tcg_gen_trunc_tl_i32(t1
, arg2
);
1218 TCGv_i32 t2
= tcg_temp_new_i32();
1219 TCGv_i32 t3
= tcg_temp_new_i32();
1220 tcg_gen_setcondi_i32(TCG_COND_EQ
, t2
, t0
, INT_MIN
);
1221 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, -1);
1222 tcg_gen_and_i32(t2
, t2
, t3
);
1223 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, 0);
1224 tcg_gen_or_i32(t2
, t2
, t3
);
1225 tcg_gen_movi_i32(t3
, 0);
1226 tcg_gen_movcond_i32(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1227 tcg_gen_rem_i32(t3
, t0
, t1
);
1228 tcg_gen_ext_i32_tl(ret
, t3
);
1229 tcg_temp_free_i32(t2
);
1230 tcg_temp_free_i32(t3
);
1232 TCGv_i32 t2
= tcg_const_i32(1);
1233 TCGv_i32 t3
= tcg_const_i32(0);
1234 tcg_gen_movcond_i32(TCG_COND_EQ
, t1
, t1
, t3
, t2
, t1
);
1235 tcg_gen_remu_i32(t3
, t0
, t1
);
1236 tcg_gen_extu_i32_tl(ret
, t3
);
1237 tcg_temp_free_i32(t2
);
1238 tcg_temp_free_i32(t3
);
1240 tcg_temp_free_i32(t0
);
1241 tcg_temp_free_i32(t1
);
1244 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1245 static void glue(gen_, name)(DisasContext *ctx) \
1247 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1248 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1252 GEN_INT_ARITH_MODW(moduw
, 0x08, 0);
1253 GEN_INT_ARITH_MODW(modsw
, 0x18, 1);
1255 #if defined(TARGET_PPC64)
1256 static inline void gen_op_arith_modd(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1257 TCGv arg2
, int sign
)
1259 TCGv_i64 t0
= tcg_temp_new_i64();
1260 TCGv_i64 t1
= tcg_temp_new_i64();
1262 tcg_gen_mov_i64(t0
, arg1
);
1263 tcg_gen_mov_i64(t1
, arg2
);
1265 TCGv_i64 t2
= tcg_temp_new_i64();
1266 TCGv_i64 t3
= tcg_temp_new_i64();
1267 tcg_gen_setcondi_i64(TCG_COND_EQ
, t2
, t0
, INT64_MIN
);
1268 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, -1);
1269 tcg_gen_and_i64(t2
, t2
, t3
);
1270 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, 0);
1271 tcg_gen_or_i64(t2
, t2
, t3
);
1272 tcg_gen_movi_i64(t3
, 0);
1273 tcg_gen_movcond_i64(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1274 tcg_gen_rem_i64(ret
, t0
, t1
);
1275 tcg_temp_free_i64(t2
);
1276 tcg_temp_free_i64(t3
);
1278 TCGv_i64 t2
= tcg_const_i64(1);
1279 TCGv_i64 t3
= tcg_const_i64(0);
1280 tcg_gen_movcond_i64(TCG_COND_EQ
, t1
, t1
, t3
, t2
, t1
);
1281 tcg_gen_remu_i64(ret
, t0
, t1
);
1282 tcg_temp_free_i64(t2
);
1283 tcg_temp_free_i64(t3
);
1285 tcg_temp_free_i64(t0
);
1286 tcg_temp_free_i64(t1
);
1289 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1290 static void glue(gen_, name)(DisasContext *ctx) \
1292 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1293 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1297 GEN_INT_ARITH_MODD(modud
, 0x08, 0);
1298 GEN_INT_ARITH_MODD(modsd
, 0x18, 1);
1302 static void gen_mulhw(DisasContext
*ctx
)
1304 TCGv_i32 t0
= tcg_temp_new_i32();
1305 TCGv_i32 t1
= tcg_temp_new_i32();
1307 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1308 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1309 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
1310 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1311 tcg_temp_free_i32(t0
);
1312 tcg_temp_free_i32(t1
);
1313 if (unlikely(Rc(ctx
->opcode
) != 0))
1314 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1317 /* mulhwu mulhwu. */
1318 static void gen_mulhwu(DisasContext
*ctx
)
1320 TCGv_i32 t0
= tcg_temp_new_i32();
1321 TCGv_i32 t1
= tcg_temp_new_i32();
1323 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1324 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1325 tcg_gen_mulu2_i32(t0
, t1
, t0
, t1
);
1326 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1327 tcg_temp_free_i32(t0
);
1328 tcg_temp_free_i32(t1
);
1329 if (unlikely(Rc(ctx
->opcode
) != 0))
1330 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1334 static void gen_mullw(DisasContext
*ctx
)
1336 #if defined(TARGET_PPC64)
1338 t0
= tcg_temp_new_i64();
1339 t1
= tcg_temp_new_i64();
1340 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1341 tcg_gen_ext32s_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1342 tcg_gen_mul_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
1346 tcg_gen_mul_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1347 cpu_gpr
[rB(ctx
->opcode
)]);
1349 if (unlikely(Rc(ctx
->opcode
) != 0))
1350 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1353 /* mullwo mullwo. */
1354 static void gen_mullwo(DisasContext
*ctx
)
1356 TCGv_i32 t0
= tcg_temp_new_i32();
1357 TCGv_i32 t1
= tcg_temp_new_i32();
1359 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1360 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1361 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
1362 #if defined(TARGET_PPC64)
1363 tcg_gen_concat_i32_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
1365 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1368 tcg_gen_sari_i32(t0
, t0
, 31);
1369 tcg_gen_setcond_i32(TCG_COND_NE
, t0
, t0
, t1
);
1370 tcg_gen_extu_i32_tl(cpu_ov
, t0
);
1371 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1373 tcg_temp_free_i32(t0
);
1374 tcg_temp_free_i32(t1
);
1375 if (unlikely(Rc(ctx
->opcode
) != 0))
1376 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1380 static void gen_mulli(DisasContext
*ctx
)
1382 tcg_gen_muli_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1386 #if defined(TARGET_PPC64)
1388 static void gen_mulhd(DisasContext
*ctx
)
1390 TCGv lo
= tcg_temp_new();
1391 tcg_gen_muls2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
1392 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1394 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1395 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1399 /* mulhdu mulhdu. */
1400 static void gen_mulhdu(DisasContext
*ctx
)
1402 TCGv lo
= tcg_temp_new();
1403 tcg_gen_mulu2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
1404 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1406 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1407 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1412 static void gen_mulld(DisasContext
*ctx
)
1414 tcg_gen_mul_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1415 cpu_gpr
[rB(ctx
->opcode
)]);
1416 if (unlikely(Rc(ctx
->opcode
) != 0))
1417 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1420 /* mulldo mulldo. */
1421 static void gen_mulldo(DisasContext
*ctx
)
1423 TCGv_i64 t0
= tcg_temp_new_i64();
1424 TCGv_i64 t1
= tcg_temp_new_i64();
1426 tcg_gen_muls2_i64(t0
, t1
, cpu_gpr
[rA(ctx
->opcode
)],
1427 cpu_gpr
[rB(ctx
->opcode
)]);
1428 tcg_gen_mov_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1430 tcg_gen_sari_i64(t0
, t0
, 63);
1431 tcg_gen_setcond_i64(TCG_COND_NE
, cpu_ov
, t0
, t1
);
1432 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1434 tcg_temp_free_i64(t0
);
1435 tcg_temp_free_i64(t1
);
1437 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1438 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1443 /* Common subf function */
1444 static inline void gen_op_arith_subf(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1445 TCGv arg2
, bool add_ca
, bool compute_ca
,
1446 bool compute_ov
, bool compute_rc0
)
1450 if (compute_ca
|| compute_ov
) {
1451 t0
= tcg_temp_new();
1455 /* dest = ~arg1 + arg2 [+ ca]. */
1456 if (NARROW_MODE(ctx
)) {
1457 /* Caution: a non-obvious corner case of the spec is that we
1458 must produce the *entire* 64-bit addition, but produce the
1459 carry into bit 32. */
1460 TCGv inv1
= tcg_temp_new();
1461 TCGv t1
= tcg_temp_new();
1462 tcg_gen_not_tl(inv1
, arg1
);
1464 tcg_gen_add_tl(t0
, arg2
, cpu_ca
);
1466 tcg_gen_addi_tl(t0
, arg2
, 1);
1468 tcg_gen_xor_tl(t1
, arg2
, inv1
); /* add without carry */
1469 tcg_gen_add_tl(t0
, t0
, inv1
);
1470 tcg_temp_free(inv1
);
1471 tcg_gen_xor_tl(cpu_ca
, t0
, t1
); /* bits changes w/ carry */
1473 tcg_gen_shri_tl(cpu_ca
, cpu_ca
, 32); /* extract bit 32 */
1474 tcg_gen_andi_tl(cpu_ca
, cpu_ca
, 1);
1475 } else if (add_ca
) {
1476 TCGv zero
, inv1
= tcg_temp_new();
1477 tcg_gen_not_tl(inv1
, arg1
);
1478 zero
= tcg_const_tl(0);
1479 tcg_gen_add2_tl(t0
, cpu_ca
, arg2
, zero
, cpu_ca
, zero
);
1480 tcg_gen_add2_tl(t0
, cpu_ca
, t0
, cpu_ca
, inv1
, zero
);
1481 tcg_temp_free(zero
);
1482 tcg_temp_free(inv1
);
1484 tcg_gen_setcond_tl(TCG_COND_GEU
, cpu_ca
, arg2
, arg1
);
1485 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1487 } else if (add_ca
) {
1488 /* Since we're ignoring carry-out, we can simplify the
1489 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1490 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1491 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
1492 tcg_gen_subi_tl(t0
, t0
, 1);
1494 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1498 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 1);
1500 if (unlikely(compute_rc0
)) {
1501 gen_set_Rc0(ctx
, t0
);
1504 if (!TCGV_EQUAL(t0
, ret
)) {
1505 tcg_gen_mov_tl(ret
, t0
);
1509 /* Sub functions with Two operands functions */
1510 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1511 static void glue(gen_, name)(DisasContext *ctx) \
1513 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1514 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1515 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1517 /* Sub functions with one operand and one immediate */
1518 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1519 add_ca, compute_ca, compute_ov) \
1520 static void glue(gen_, name)(DisasContext *ctx) \
1522 TCGv t0 = tcg_const_tl(const_val); \
1523 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1524 cpu_gpr[rA(ctx->opcode)], t0, \
1525 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1526 tcg_temp_free(t0); \
1528 /* subf subf. subfo subfo. */
1529 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
1530 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
1531 /* subfc subfc. subfco subfco. */
1532 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
1533 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
1534 /* subfe subfe. subfeo subfo. */
1535 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
1536 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
1537 /* subfme subfme. subfmeo subfmeo. */
1538 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
1539 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
1540 /* subfze subfze. subfzeo subfzeo.*/
1541 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
1542 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
1545 static void gen_subfic(DisasContext
*ctx
)
1547 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
1548 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1553 /* neg neg. nego nego. */
1554 static inline void gen_op_arith_neg(DisasContext
*ctx
, bool compute_ov
)
1556 TCGv zero
= tcg_const_tl(0);
1557 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1558 zero
, 0, 0, compute_ov
, Rc(ctx
->opcode
));
1559 tcg_temp_free(zero
);
1562 static void gen_neg(DisasContext
*ctx
)
1564 gen_op_arith_neg(ctx
, 0);
1567 static void gen_nego(DisasContext
*ctx
)
1569 gen_op_arith_neg(ctx
, 1);
1572 /*** Integer logical ***/
1573 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1574 static void glue(gen_, name)(DisasContext *ctx) \
1576 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1577 cpu_gpr[rB(ctx->opcode)]); \
1578 if (unlikely(Rc(ctx->opcode) != 0)) \
1579 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1582 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1583 static void glue(gen_, name)(DisasContext *ctx) \
1585 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1586 if (unlikely(Rc(ctx->opcode) != 0)) \
1587 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1591 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
);
1593 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
);
1596 static void gen_andi_(DisasContext
*ctx
)
1598 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
));
1599 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1603 static void gen_andis_(DisasContext
*ctx
)
1605 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
) << 16);
1606 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1610 static void gen_cntlzw(DisasContext
*ctx
)
1612 gen_helper_cntlzw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1613 if (unlikely(Rc(ctx
->opcode
) != 0))
1614 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1618 static void gen_cnttzw(DisasContext
*ctx
)
1620 gen_helper_cnttzw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1621 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1622 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1627 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
);
1628 /* extsb & extsb. */
1629 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
);
1630 /* extsh & extsh. */
1631 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
);
1633 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
);
1635 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
);
1637 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1638 static void gen_pause(DisasContext
*ctx
)
1640 TCGv_i32 t0
= tcg_const_i32(0);
1641 tcg_gen_st_i32(t0
, cpu_env
,
1642 -offsetof(PowerPCCPU
, env
) + offsetof(CPUState
, halted
));
1643 tcg_temp_free_i32(t0
);
1645 /* Stop translation, this gives other CPUs a chance to run */
1646 gen_exception_err(ctx
, EXCP_HLT
, 1);
1648 #endif /* defined(TARGET_PPC64) */
1651 static void gen_or(DisasContext
*ctx
)
1655 rs
= rS(ctx
->opcode
);
1656 ra
= rA(ctx
->opcode
);
1657 rb
= rB(ctx
->opcode
);
1658 /* Optimisation for mr. ri case */
1659 if (rs
!= ra
|| rs
!= rb
) {
1661 tcg_gen_or_tl(cpu_gpr
[ra
], cpu_gpr
[rs
], cpu_gpr
[rb
]);
1663 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rs
]);
1664 if (unlikely(Rc(ctx
->opcode
) != 0))
1665 gen_set_Rc0(ctx
, cpu_gpr
[ra
]);
1666 } else if (unlikely(Rc(ctx
->opcode
) != 0)) {
1667 gen_set_Rc0(ctx
, cpu_gpr
[rs
]);
1668 #if defined(TARGET_PPC64)
1669 } else if (rs
!= 0) { /* 0 is nop */
1674 /* Set process priority to low */
1678 /* Set process priority to medium-low */
1682 /* Set process priority to normal */
1685 #if !defined(CONFIG_USER_ONLY)
1688 /* Set process priority to very low */
1694 /* Set process priority to medium-hight */
1700 /* Set process priority to high */
1705 if (ctx
->hv
&& !ctx
->pr
) {
1706 /* Set process priority to very high */
1715 TCGv t0
= tcg_temp_new();
1716 gen_load_spr(t0
, SPR_PPR
);
1717 tcg_gen_andi_tl(t0
, t0
, ~0x001C000000000000ULL
);
1718 tcg_gen_ori_tl(t0
, t0
, ((uint64_t)prio
) << 50);
1719 gen_store_spr(SPR_PPR
, t0
);
1722 #if !defined(CONFIG_USER_ONLY)
1723 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1724 * CPU and the kernel hangs. This applies to all encodings other
1725 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1726 * and all currently undefined.
1734 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
);
1737 static void gen_xor(DisasContext
*ctx
)
1739 /* Optimisation for "set to zero" case */
1740 if (rS(ctx
->opcode
) != rB(ctx
->opcode
))
1741 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1743 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
1744 if (unlikely(Rc(ctx
->opcode
) != 0))
1745 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1749 static void gen_ori(DisasContext
*ctx
)
1751 target_ulong uimm
= UIMM(ctx
->opcode
);
1753 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1756 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1760 static void gen_oris(DisasContext
*ctx
)
1762 target_ulong uimm
= UIMM(ctx
->opcode
);
1764 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1768 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1772 static void gen_xori(DisasContext
*ctx
)
1774 target_ulong uimm
= UIMM(ctx
->opcode
);
1776 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1780 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1784 static void gen_xoris(DisasContext
*ctx
)
1786 target_ulong uimm
= UIMM(ctx
->opcode
);
1788 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1792 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1795 /* popcntb : PowerPC 2.03 specification */
1796 static void gen_popcntb(DisasContext
*ctx
)
1798 gen_helper_popcntb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1801 static void gen_popcntw(DisasContext
*ctx
)
1803 gen_helper_popcntw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1806 #if defined(TARGET_PPC64)
1807 /* popcntd: PowerPC 2.06 specification */
1808 static void gen_popcntd(DisasContext
*ctx
)
1810 gen_helper_popcntd(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1814 /* prtyw: PowerPC 2.05 specification */
1815 static void gen_prtyw(DisasContext
*ctx
)
1817 TCGv ra
= cpu_gpr
[rA(ctx
->opcode
)];
1818 TCGv rs
= cpu_gpr
[rS(ctx
->opcode
)];
1819 TCGv t0
= tcg_temp_new();
1820 tcg_gen_shri_tl(t0
, rs
, 16);
1821 tcg_gen_xor_tl(ra
, rs
, t0
);
1822 tcg_gen_shri_tl(t0
, ra
, 8);
1823 tcg_gen_xor_tl(ra
, ra
, t0
);
1824 tcg_gen_andi_tl(ra
, ra
, (target_ulong
)0x100000001ULL
);
1828 #if defined(TARGET_PPC64)
1829 /* prtyd: PowerPC 2.05 specification */
1830 static void gen_prtyd(DisasContext
*ctx
)
1832 TCGv ra
= cpu_gpr
[rA(ctx
->opcode
)];
1833 TCGv rs
= cpu_gpr
[rS(ctx
->opcode
)];
1834 TCGv t0
= tcg_temp_new();
1835 tcg_gen_shri_tl(t0
, rs
, 32);
1836 tcg_gen_xor_tl(ra
, rs
, t0
);
1837 tcg_gen_shri_tl(t0
, ra
, 16);
1838 tcg_gen_xor_tl(ra
, ra
, t0
);
1839 tcg_gen_shri_tl(t0
, ra
, 8);
1840 tcg_gen_xor_tl(ra
, ra
, t0
);
1841 tcg_gen_andi_tl(ra
, ra
, 1);
1846 #if defined(TARGET_PPC64)
1848 static void gen_bpermd(DisasContext
*ctx
)
1850 gen_helper_bpermd(cpu_gpr
[rA(ctx
->opcode
)],
1851 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1855 #if defined(TARGET_PPC64)
1856 /* extsw & extsw. */
1857 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
);
1860 static void gen_cntlzd(DisasContext
*ctx
)
1862 gen_helper_cntlzd(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1863 if (unlikely(Rc(ctx
->opcode
) != 0))
1864 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1868 static void gen_cnttzd(DisasContext
*ctx
)
1870 gen_helper_cnttzd(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1871 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1872 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1877 /*** Integer rotate ***/
1879 /* rlwimi & rlwimi. */
1880 static void gen_rlwimi(DisasContext
*ctx
)
1882 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1883 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1884 uint32_t sh
= SH(ctx
->opcode
);
1885 uint32_t mb
= MB(ctx
->opcode
);
1886 uint32_t me
= ME(ctx
->opcode
);
1888 if (sh
== (31-me
) && mb
<= me
) {
1889 tcg_gen_deposit_tl(t_ra
, t_ra
, t_rs
, sh
, me
- mb
+ 1);
1894 #if defined(TARGET_PPC64)
1898 mask
= MASK(mb
, me
);
1900 t1
= tcg_temp_new();
1901 if (mask
<= 0xffffffffu
) {
1902 TCGv_i32 t0
= tcg_temp_new_i32();
1903 tcg_gen_trunc_tl_i32(t0
, t_rs
);
1904 tcg_gen_rotli_i32(t0
, t0
, sh
);
1905 tcg_gen_extu_i32_tl(t1
, t0
);
1906 tcg_temp_free_i32(t0
);
1908 #if defined(TARGET_PPC64)
1909 tcg_gen_deposit_i64(t1
, t_rs
, t_rs
, 32, 32);
1910 tcg_gen_rotli_i64(t1
, t1
, sh
);
1912 g_assert_not_reached();
1916 tcg_gen_andi_tl(t1
, t1
, mask
);
1917 tcg_gen_andi_tl(t_ra
, t_ra
, ~mask
);
1918 tcg_gen_or_tl(t_ra
, t_ra
, t1
);
1921 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1922 gen_set_Rc0(ctx
, t_ra
);
1926 /* rlwinm & rlwinm. */
1927 static void gen_rlwinm(DisasContext
*ctx
)
1929 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1930 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1931 uint32_t sh
= SH(ctx
->opcode
);
1932 uint32_t mb
= MB(ctx
->opcode
);
1933 uint32_t me
= ME(ctx
->opcode
);
1935 if (mb
== 0 && me
== (31 - sh
)) {
1936 tcg_gen_shli_tl(t_ra
, t_rs
, sh
);
1937 tcg_gen_ext32u_tl(t_ra
, t_ra
);
1938 } else if (sh
!= 0 && me
== 31 && sh
== (32 - mb
)) {
1939 tcg_gen_ext32u_tl(t_ra
, t_rs
);
1940 tcg_gen_shri_tl(t_ra
, t_ra
, mb
);
1943 #if defined(TARGET_PPC64)
1947 mask
= MASK(mb
, me
);
1949 if (mask
<= 0xffffffffu
) {
1950 TCGv_i32 t0
= tcg_temp_new_i32();
1951 tcg_gen_trunc_tl_i32(t0
, t_rs
);
1952 tcg_gen_rotli_i32(t0
, t0
, sh
);
1953 tcg_gen_andi_i32(t0
, t0
, mask
);
1954 tcg_gen_extu_i32_tl(t_ra
, t0
);
1955 tcg_temp_free_i32(t0
);
1957 #if defined(TARGET_PPC64)
1958 tcg_gen_deposit_i64(t_ra
, t_rs
, t_rs
, 32, 32);
1959 tcg_gen_rotli_i64(t_ra
, t_ra
, sh
);
1960 tcg_gen_andi_i64(t_ra
, t_ra
, mask
);
1962 g_assert_not_reached();
1966 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1967 gen_set_Rc0(ctx
, t_ra
);
1971 /* rlwnm & rlwnm. */
1972 static void gen_rlwnm(DisasContext
*ctx
)
1974 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1975 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1976 TCGv t_rb
= cpu_gpr
[rB(ctx
->opcode
)];
1977 uint32_t mb
= MB(ctx
->opcode
);
1978 uint32_t me
= ME(ctx
->opcode
);
1981 #if defined(TARGET_PPC64)
1985 mask
= MASK(mb
, me
);
1987 if (mask
<= 0xffffffffu
) {
1988 TCGv_i32 t0
= tcg_temp_new_i32();
1989 TCGv_i32 t1
= tcg_temp_new_i32();
1990 tcg_gen_trunc_tl_i32(t0
, t_rb
);
1991 tcg_gen_trunc_tl_i32(t1
, t_rs
);
1992 tcg_gen_andi_i32(t0
, t0
, 0x1f);
1993 tcg_gen_rotl_i32(t1
, t1
, t0
);
1994 tcg_gen_extu_i32_tl(t_ra
, t1
);
1995 tcg_temp_free_i32(t0
);
1996 tcg_temp_free_i32(t1
);
1998 #if defined(TARGET_PPC64)
1999 TCGv_i64 t0
= tcg_temp_new_i64();
2000 tcg_gen_andi_i64(t0
, t_rb
, 0x1f);
2001 tcg_gen_deposit_i64(t_ra
, t_rs
, t_rs
, 32, 32);
2002 tcg_gen_rotl_i64(t_ra
, t_ra
, t0
);
2003 tcg_temp_free_i64(t0
);
2005 g_assert_not_reached();
2009 tcg_gen_andi_tl(t_ra
, t_ra
, mask
);
2011 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2012 gen_set_Rc0(ctx
, t_ra
);
2016 #if defined(TARGET_PPC64)
2017 #define GEN_PPC64_R2(name, opc1, opc2) \
2018 static void glue(gen_, name##0)(DisasContext *ctx) \
2020 gen_##name(ctx, 0); \
2023 static void glue(gen_, name##1)(DisasContext *ctx) \
2025 gen_##name(ctx, 1); \
2027 #define GEN_PPC64_R4(name, opc1, opc2) \
2028 static void glue(gen_, name##0)(DisasContext *ctx) \
2030 gen_##name(ctx, 0, 0); \
2033 static void glue(gen_, name##1)(DisasContext *ctx) \
2035 gen_##name(ctx, 0, 1); \
2038 static void glue(gen_, name##2)(DisasContext *ctx) \
2040 gen_##name(ctx, 1, 0); \
2043 static void glue(gen_, name##3)(DisasContext *ctx) \
2045 gen_##name(ctx, 1, 1); \
2048 static void gen_rldinm(DisasContext
*ctx
, int mb
, int me
, int sh
)
2050 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2051 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2053 if (sh
!= 0 && mb
== 0 && me
== (63 - sh
)) {
2054 tcg_gen_shli_tl(t_ra
, t_rs
, sh
);
2055 } else if (sh
!= 0 && me
== 63 && sh
== (64 - mb
)) {
2056 tcg_gen_shri_tl(t_ra
, t_rs
, mb
);
2058 tcg_gen_rotli_tl(t_ra
, t_rs
, sh
);
2059 tcg_gen_andi_tl(t_ra
, t_ra
, MASK(mb
, me
));
2061 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2062 gen_set_Rc0(ctx
, t_ra
);
2066 /* rldicl - rldicl. */
2067 static inline void gen_rldicl(DisasContext
*ctx
, int mbn
, int shn
)
2071 sh
= SH(ctx
->opcode
) | (shn
<< 5);
2072 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2073 gen_rldinm(ctx
, mb
, 63, sh
);
2075 GEN_PPC64_R4(rldicl
, 0x1E, 0x00);
2077 /* rldicr - rldicr. */
2078 static inline void gen_rldicr(DisasContext
*ctx
, int men
, int shn
)
2082 sh
= SH(ctx
->opcode
) | (shn
<< 5);
2083 me
= MB(ctx
->opcode
) | (men
<< 5);
2084 gen_rldinm(ctx
, 0, me
, sh
);
2086 GEN_PPC64_R4(rldicr
, 0x1E, 0x02);
2088 /* rldic - rldic. */
2089 static inline void gen_rldic(DisasContext
*ctx
, int mbn
, int shn
)
2093 sh
= SH(ctx
->opcode
) | (shn
<< 5);
2094 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2095 gen_rldinm(ctx
, mb
, 63 - sh
, sh
);
2097 GEN_PPC64_R4(rldic
, 0x1E, 0x04);
2099 static void gen_rldnm(DisasContext
*ctx
, int mb
, int me
)
2101 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2102 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2103 TCGv t_rb
= cpu_gpr
[rB(ctx
->opcode
)];
2106 t0
= tcg_temp_new();
2107 tcg_gen_andi_tl(t0
, t_rb
, 0x3f);
2108 tcg_gen_rotl_tl(t_ra
, t_rs
, t0
);
2111 tcg_gen_andi_tl(t_ra
, t_ra
, MASK(mb
, me
));
2112 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2113 gen_set_Rc0(ctx
, t_ra
);
2117 /* rldcl - rldcl. */
2118 static inline void gen_rldcl(DisasContext
*ctx
, int mbn
)
2122 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2123 gen_rldnm(ctx
, mb
, 63);
2125 GEN_PPC64_R2(rldcl
, 0x1E, 0x08);
2127 /* rldcr - rldcr. */
2128 static inline void gen_rldcr(DisasContext
*ctx
, int men
)
2132 me
= MB(ctx
->opcode
) | (men
<< 5);
2133 gen_rldnm(ctx
, 0, me
);
2135 GEN_PPC64_R2(rldcr
, 0x1E, 0x09);
2137 /* rldimi - rldimi. */
2138 static void gen_rldimi(DisasContext
*ctx
, int mbn
, int shn
)
2140 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2141 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2142 uint32_t sh
= SH(ctx
->opcode
) | (shn
<< 5);
2143 uint32_t mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2144 uint32_t me
= 63 - sh
;
2147 tcg_gen_deposit_tl(t_ra
, t_ra
, t_rs
, sh
, me
- mb
+ 1);
2149 target_ulong mask
= MASK(mb
, me
);
2150 TCGv t1
= tcg_temp_new();
2152 tcg_gen_rotli_tl(t1
, t_rs
, sh
);
2153 tcg_gen_andi_tl(t1
, t1
, mask
);
2154 tcg_gen_andi_tl(t_ra
, t_ra
, ~mask
);
2155 tcg_gen_or_tl(t_ra
, t_ra
, t1
);
2158 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2159 gen_set_Rc0(ctx
, t_ra
);
2162 GEN_PPC64_R4(rldimi
, 0x1E, 0x06);
2165 /*** Integer shift ***/
2168 static void gen_slw(DisasContext
*ctx
)
2172 t0
= tcg_temp_new();
2173 /* AND rS with a mask that is 0 when rB >= 0x20 */
2174 #if defined(TARGET_PPC64)
2175 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
2176 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2178 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
2179 tcg_gen_sari_tl(t0
, t0
, 0x1f);
2181 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2182 t1
= tcg_temp_new();
2183 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
2184 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2187 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
2188 if (unlikely(Rc(ctx
->opcode
) != 0))
2189 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2193 static void gen_sraw(DisasContext
*ctx
)
2195 gen_helper_sraw(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
2196 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2197 if (unlikely(Rc(ctx
->opcode
) != 0))
2198 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2201 /* srawi & srawi. */
2202 static void gen_srawi(DisasContext
*ctx
)
2204 int sh
= SH(ctx
->opcode
);
2205 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
2206 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
2208 tcg_gen_ext32s_tl(dst
, src
);
2209 tcg_gen_movi_tl(cpu_ca
, 0);
2212 tcg_gen_ext32s_tl(dst
, src
);
2213 tcg_gen_andi_tl(cpu_ca
, dst
, (1ULL << sh
) - 1);
2214 t0
= tcg_temp_new();
2215 tcg_gen_sari_tl(t0
, dst
, TARGET_LONG_BITS
- 1);
2216 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
2218 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
2219 tcg_gen_sari_tl(dst
, dst
, sh
);
2221 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2222 gen_set_Rc0(ctx
, dst
);
2227 static void gen_srw(DisasContext
*ctx
)
2231 t0
= tcg_temp_new();
2232 /* AND rS with a mask that is 0 when rB >= 0x20 */
2233 #if defined(TARGET_PPC64)
2234 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
2235 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2237 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
2238 tcg_gen_sari_tl(t0
, t0
, 0x1f);
2240 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2241 tcg_gen_ext32u_tl(t0
, t0
);
2242 t1
= tcg_temp_new();
2243 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
2244 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2247 if (unlikely(Rc(ctx
->opcode
) != 0))
2248 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2251 #if defined(TARGET_PPC64)
2253 static void gen_sld(DisasContext
*ctx
)
2257 t0
= tcg_temp_new();
2258 /* AND rS with a mask that is 0 when rB >= 0x40 */
2259 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
2260 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2261 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2262 t1
= tcg_temp_new();
2263 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
2264 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2267 if (unlikely(Rc(ctx
->opcode
) != 0))
2268 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2272 static void gen_srad(DisasContext
*ctx
)
2274 gen_helper_srad(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
2275 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2276 if (unlikely(Rc(ctx
->opcode
) != 0))
2277 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2279 /* sradi & sradi. */
2280 static inline void gen_sradi(DisasContext
*ctx
, int n
)
2282 int sh
= SH(ctx
->opcode
) + (n
<< 5);
2283 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
2284 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
2286 tcg_gen_mov_tl(dst
, src
);
2287 tcg_gen_movi_tl(cpu_ca
, 0);
2290 tcg_gen_andi_tl(cpu_ca
, src
, (1ULL << sh
) - 1);
2291 t0
= tcg_temp_new();
2292 tcg_gen_sari_tl(t0
, src
, TARGET_LONG_BITS
- 1);
2293 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
2295 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
2296 tcg_gen_sari_tl(dst
, src
, sh
);
2298 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2299 gen_set_Rc0(ctx
, dst
);
2303 static void gen_sradi0(DisasContext
*ctx
)
2308 static void gen_sradi1(DisasContext
*ctx
)
2314 static void gen_srd(DisasContext
*ctx
)
2318 t0
= tcg_temp_new();
2319 /* AND rS with a mask that is 0 when rB >= 0x40 */
2320 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
2321 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2322 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2323 t1
= tcg_temp_new();
2324 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
2325 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2328 if (unlikely(Rc(ctx
->opcode
) != 0))
2329 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2333 /*** Addressing modes ***/
2334 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2335 static inline void gen_addr_imm_index(DisasContext
*ctx
, TCGv EA
,
2338 target_long simm
= SIMM(ctx
->opcode
);
2341 if (rA(ctx
->opcode
) == 0) {
2342 if (NARROW_MODE(ctx
)) {
2343 simm
= (uint32_t)simm
;
2345 tcg_gen_movi_tl(EA
, simm
);
2346 } else if (likely(simm
!= 0)) {
2347 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], simm
);
2348 if (NARROW_MODE(ctx
)) {
2349 tcg_gen_ext32u_tl(EA
, EA
);
2352 if (NARROW_MODE(ctx
)) {
2353 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2355 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2360 static inline void gen_addr_reg_index(DisasContext
*ctx
, TCGv EA
)
2362 if (rA(ctx
->opcode
) == 0) {
2363 if (NARROW_MODE(ctx
)) {
2364 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2366 tcg_gen_mov_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2369 tcg_gen_add_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2370 if (NARROW_MODE(ctx
)) {
2371 tcg_gen_ext32u_tl(EA
, EA
);
2376 static inline void gen_addr_register(DisasContext
*ctx
, TCGv EA
)
2378 if (rA(ctx
->opcode
) == 0) {
2379 tcg_gen_movi_tl(EA
, 0);
2380 } else if (NARROW_MODE(ctx
)) {
2381 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2383 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2387 static inline void gen_addr_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
2390 tcg_gen_addi_tl(ret
, arg1
, val
);
2391 if (NARROW_MODE(ctx
)) {
2392 tcg_gen_ext32u_tl(ret
, ret
);
2396 static inline void gen_check_align(DisasContext
*ctx
, TCGv EA
, int mask
)
2398 TCGLabel
*l1
= gen_new_label();
2399 TCGv t0
= tcg_temp_new();
2401 /* NIP cannot be restored if the memory exception comes from an helper */
2402 gen_update_nip(ctx
, ctx
->nip
- 4);
2403 tcg_gen_andi_tl(t0
, EA
, mask
);
2404 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
2405 t1
= tcg_const_i32(POWERPC_EXCP_ALIGN
);
2406 t2
= tcg_const_i32(0);
2407 gen_helper_raise_exception_err(cpu_env
, t1
, t2
);
2408 tcg_temp_free_i32(t1
);
2409 tcg_temp_free_i32(t2
);
2414 /*** Integer load ***/
2415 static inline void gen_qemu_ld8u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2417 tcg_gen_qemu_ld8u(arg1
, arg2
, ctx
->mem_idx
);
2420 static inline void gen_qemu_ld16u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2422 TCGMemOp op
= MO_UW
| ctx
->default_tcg_memop_mask
;
2423 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2426 static inline void gen_qemu_ld16s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2428 TCGMemOp op
= MO_SW
| ctx
->default_tcg_memop_mask
;
2429 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2432 static inline void gen_qemu_ld32u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2434 TCGMemOp op
= MO_UL
| ctx
->default_tcg_memop_mask
;
2435 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2438 static void gen_qemu_ld32u_i64(DisasContext
*ctx
, TCGv_i64 val
, TCGv addr
)
2440 TCGv tmp
= tcg_temp_new();
2441 gen_qemu_ld32u(ctx
, tmp
, addr
);
2442 tcg_gen_extu_tl_i64(val
, tmp
);
2446 static inline void gen_qemu_ld32s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2448 TCGMemOp op
= MO_SL
| ctx
->default_tcg_memop_mask
;
2449 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2452 static void gen_qemu_ld32s_i64(DisasContext
*ctx
, TCGv_i64 val
, TCGv addr
)
2454 TCGv tmp
= tcg_temp_new();
2455 gen_qemu_ld32s(ctx
, tmp
, addr
);
2456 tcg_gen_ext_tl_i64(val
, tmp
);
2460 static inline void gen_qemu_ld64(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
2462 TCGMemOp op
= MO_Q
| ctx
->default_tcg_memop_mask
;
2463 tcg_gen_qemu_ld_i64(arg1
, arg2
, ctx
->mem_idx
, op
);
2466 static inline void gen_qemu_st8(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2468 tcg_gen_qemu_st8(arg1
, arg2
, ctx
->mem_idx
);
2471 static inline void gen_qemu_st16(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2473 TCGMemOp op
= MO_UW
| ctx
->default_tcg_memop_mask
;
2474 tcg_gen_qemu_st_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2477 static inline void gen_qemu_st32(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2479 TCGMemOp op
= MO_UL
| ctx
->default_tcg_memop_mask
;
2480 tcg_gen_qemu_st_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2483 static void gen_qemu_st32_i64(DisasContext
*ctx
, TCGv_i64 val
, TCGv addr
)
2485 TCGv tmp
= tcg_temp_new();
2486 tcg_gen_trunc_i64_tl(tmp
, val
);
2487 gen_qemu_st32(ctx
, tmp
, addr
);
2491 static inline void gen_qemu_st64(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
2493 TCGMemOp op
= MO_Q
| ctx
->default_tcg_memop_mask
;
2494 tcg_gen_qemu_st_i64(arg1
, arg2
, ctx
->mem_idx
, op
);
2497 #define GEN_LD(name, ldop, opc, type) \
2498 static void glue(gen_, name)(DisasContext *ctx) \
2501 gen_set_access_type(ctx, ACCESS_INT); \
2502 EA = tcg_temp_new(); \
2503 gen_addr_imm_index(ctx, EA, 0); \
2504 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2505 tcg_temp_free(EA); \
2508 #define GEN_LDU(name, ldop, opc, type) \
2509 static void glue(gen_, name##u)(DisasContext *ctx) \
2512 if (unlikely(rA(ctx->opcode) == 0 || \
2513 rA(ctx->opcode) == rD(ctx->opcode))) { \
2514 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2517 gen_set_access_type(ctx, ACCESS_INT); \
2518 EA = tcg_temp_new(); \
2519 if (type == PPC_64B) \
2520 gen_addr_imm_index(ctx, EA, 0x03); \
2522 gen_addr_imm_index(ctx, EA, 0); \
2523 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2524 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2525 tcg_temp_free(EA); \
2528 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2529 static void glue(gen_, name##ux)(DisasContext *ctx) \
2532 if (unlikely(rA(ctx->opcode) == 0 || \
2533 rA(ctx->opcode) == rD(ctx->opcode))) { \
2534 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2537 gen_set_access_type(ctx, ACCESS_INT); \
2538 EA = tcg_temp_new(); \
2539 gen_addr_reg_index(ctx, EA); \
2540 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2541 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2542 tcg_temp_free(EA); \
2545 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2546 static void glue(gen_, name##x)(DisasContext *ctx) \
2550 gen_set_access_type(ctx, ACCESS_INT); \
2551 EA = tcg_temp_new(); \
2552 gen_addr_reg_index(ctx, EA); \
2553 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2554 tcg_temp_free(EA); \
2557 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2558 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2560 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2561 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2563 #define GEN_LDS(name, ldop, op, type) \
2564 GEN_LD(name, ldop, op | 0x20, type); \
2565 GEN_LDU(name, ldop, op | 0x21, type); \
2566 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2567 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2569 /* lbz lbzu lbzux lbzx */
2570 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
);
2571 /* lha lhau lhaux lhax */
2572 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
);
2573 /* lhz lhzu lhzux lhzx */
2574 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
);
2575 /* lwz lwzu lwzux lwzx */
2576 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
);
2577 #if defined(TARGET_PPC64)
2579 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
);
2581 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
);
2583 GEN_LDUX(ld
, ld64
, 0x15, 0x01, PPC_64B
);
2585 GEN_LDX(ld
, ld64
, 0x15, 0x00, PPC_64B
);
2587 /* CI load/store variants */
2588 GEN_LDX_HVRM(ldcix
, ld64
, 0x15, 0x1b, PPC_CILDST
)
2589 GEN_LDX_HVRM(lwzcix
, ld32u
, 0x15, 0x15, PPC_CILDST
)
2590 GEN_LDX_HVRM(lhzcix
, ld16u
, 0x15, 0x19, PPC_CILDST
)
2591 GEN_LDX_HVRM(lbzcix
, ld8u
, 0x15, 0x1a, PPC_CILDST
)
2593 static void gen_ld(DisasContext
*ctx
)
2596 if (Rc(ctx
->opcode
)) {
2597 if (unlikely(rA(ctx
->opcode
) == 0 ||
2598 rA(ctx
->opcode
) == rD(ctx
->opcode
))) {
2599 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2603 gen_set_access_type(ctx
, ACCESS_INT
);
2604 EA
= tcg_temp_new();
2605 gen_addr_imm_index(ctx
, EA
, 0x03);
2606 if (ctx
->opcode
& 0x02) {
2607 /* lwa (lwau is undefined) */
2608 gen_qemu_ld32s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2611 gen_qemu_ld64(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2613 if (Rc(ctx
->opcode
))
2614 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2619 static void gen_lq(DisasContext
*ctx
)
2624 /* lq is a legal user mode instruction starting in ISA 2.07 */
2625 bool legal_in_user_mode
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2626 bool le_is_supported
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2628 if (!legal_in_user_mode
&& ctx
->pr
) {
2629 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2633 if (!le_is_supported
&& ctx
->le_mode
) {
2634 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
2638 ra
= rA(ctx
->opcode
);
2639 rd
= rD(ctx
->opcode
);
2640 if (unlikely((rd
& 1) || rd
== ra
)) {
2641 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2645 gen_set_access_type(ctx
, ACCESS_INT
);
2646 EA
= tcg_temp_new();
2647 gen_addr_imm_index(ctx
, EA
, 0x0F);
2649 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2650 64-bit byteswap already. */
2651 if (unlikely(ctx
->le_mode
)) {
2652 gen_qemu_ld64(ctx
, cpu_gpr
[rd
+1], EA
);
2653 gen_addr_add(ctx
, EA
, EA
, 8);
2654 gen_qemu_ld64(ctx
, cpu_gpr
[rd
], EA
);
2656 gen_qemu_ld64(ctx
, cpu_gpr
[rd
], EA
);
2657 gen_addr_add(ctx
, EA
, EA
, 8);
2658 gen_qemu_ld64(ctx
, cpu_gpr
[rd
+1], EA
);
2664 /*** Integer store ***/
2665 #define GEN_ST(name, stop, opc, type) \
2666 static void glue(gen_, name)(DisasContext *ctx) \
2669 gen_set_access_type(ctx, ACCESS_INT); \
2670 EA = tcg_temp_new(); \
2671 gen_addr_imm_index(ctx, EA, 0); \
2672 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2673 tcg_temp_free(EA); \
2676 #define GEN_STU(name, stop, opc, type) \
2677 static void glue(gen_, stop##u)(DisasContext *ctx) \
2680 if (unlikely(rA(ctx->opcode) == 0)) { \
2681 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2684 gen_set_access_type(ctx, ACCESS_INT); \
2685 EA = tcg_temp_new(); \
2686 if (type == PPC_64B) \
2687 gen_addr_imm_index(ctx, EA, 0x03); \
2689 gen_addr_imm_index(ctx, EA, 0); \
2690 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2691 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2692 tcg_temp_free(EA); \
2695 #define GEN_STUX(name, stop, opc2, opc3, type) \
2696 static void glue(gen_, name##ux)(DisasContext *ctx) \
2699 if (unlikely(rA(ctx->opcode) == 0)) { \
2700 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2703 gen_set_access_type(ctx, ACCESS_INT); \
2704 EA = tcg_temp_new(); \
2705 gen_addr_reg_index(ctx, EA); \
2706 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2707 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2708 tcg_temp_free(EA); \
2711 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2712 static void glue(gen_, name##x)(DisasContext *ctx) \
2716 gen_set_access_type(ctx, ACCESS_INT); \
2717 EA = tcg_temp_new(); \
2718 gen_addr_reg_index(ctx, EA); \
2719 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2720 tcg_temp_free(EA); \
2722 #define GEN_STX(name, stop, opc2, opc3, type) \
2723 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2725 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2726 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2728 #define GEN_STS(name, stop, op, type) \
2729 GEN_ST(name, stop, op | 0x20, type); \
2730 GEN_STU(name, stop, op | 0x21, type); \
2731 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2732 GEN_STX(name, stop, 0x17, op | 0x00, type)
2734 /* stb stbu stbux stbx */
2735 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
);
2736 /* sth sthu sthux sthx */
2737 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
);
2738 /* stw stwu stwux stwx */
2739 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
);
2740 #if defined(TARGET_PPC64)
2741 GEN_STUX(std
, st64
, 0x15, 0x05, PPC_64B
);
2742 GEN_STX(std
, st64
, 0x15, 0x04, PPC_64B
);
2743 GEN_STX_HVRM(stdcix
, st64
, 0x15, 0x1f, PPC_CILDST
)
2744 GEN_STX_HVRM(stwcix
, st32
, 0x15, 0x1c, PPC_CILDST
)
2745 GEN_STX_HVRM(sthcix
, st16
, 0x15, 0x1d, PPC_CILDST
)
2746 GEN_STX_HVRM(stbcix
, st8
, 0x15, 0x1e, PPC_CILDST
)
2748 static void gen_std(DisasContext
*ctx
)
2753 rs
= rS(ctx
->opcode
);
2754 if ((ctx
->opcode
& 0x3) == 0x2) { /* stq */
2755 bool legal_in_user_mode
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2756 bool le_is_supported
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2758 if (!(ctx
->insns_flags
& PPC_64BX
)) {
2759 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2762 if (!legal_in_user_mode
&& ctx
->pr
) {
2763 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2767 if (!le_is_supported
&& ctx
->le_mode
) {
2768 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
2772 if (unlikely(rs
& 1)) {
2773 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2776 gen_set_access_type(ctx
, ACCESS_INT
);
2777 EA
= tcg_temp_new();
2778 gen_addr_imm_index(ctx
, EA
, 0x03);
2780 /* We only need to swap high and low halves. gen_qemu_st64 does
2781 necessary 64-bit byteswap already. */
2782 if (unlikely(ctx
->le_mode
)) {
2783 gen_qemu_st64(ctx
, cpu_gpr
[rs
+1], EA
);
2784 gen_addr_add(ctx
, EA
, EA
, 8);
2785 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
2787 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
2788 gen_addr_add(ctx
, EA
, EA
, 8);
2789 gen_qemu_st64(ctx
, cpu_gpr
[rs
+1], EA
);
2794 if (Rc(ctx
->opcode
)) {
2795 if (unlikely(rA(ctx
->opcode
) == 0)) {
2796 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2800 gen_set_access_type(ctx
, ACCESS_INT
);
2801 EA
= tcg_temp_new();
2802 gen_addr_imm_index(ctx
, EA
, 0x03);
2803 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
2804 if (Rc(ctx
->opcode
))
2805 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2810 /*** Integer load and store with byte reverse ***/
2813 static inline void gen_qemu_ld16ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2815 TCGMemOp op
= MO_UW
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
2816 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2818 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
);
2821 static inline void gen_qemu_ld32ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2823 TCGMemOp op
= MO_UL
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
2824 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2826 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
);
2828 #if defined(TARGET_PPC64)
2830 static inline void gen_qemu_ld64ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2832 TCGMemOp op
= MO_Q
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
2833 tcg_gen_qemu_ld_i64(arg1
, arg2
, ctx
->mem_idx
, op
);
2835 GEN_LDX_E(ldbr
, ld64ur
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
, CHK_NONE
);
2836 #endif /* TARGET_PPC64 */
2839 static inline void gen_qemu_st16r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2841 TCGMemOp op
= MO_UW
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
2842 tcg_gen_qemu_st_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2844 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
);
2847 static inline void gen_qemu_st32r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2849 TCGMemOp op
= MO_UL
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
2850 tcg_gen_qemu_st_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2852 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
);
2854 #if defined(TARGET_PPC64)
2856 static inline void gen_qemu_st64r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2858 TCGMemOp op
= MO_Q
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
2859 tcg_gen_qemu_st_i64(arg1
, arg2
, ctx
->mem_idx
, op
);
2861 GEN_STX_E(stdbr
, st64r
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
, CHK_NONE
);
2862 #endif /* TARGET_PPC64 */
2864 /*** Integer load and store multiple ***/
2867 static void gen_lmw(DisasContext
*ctx
)
2871 gen_set_access_type(ctx
, ACCESS_INT
);
2872 /* NIP cannot be restored if the memory exception comes from an helper */
2873 gen_update_nip(ctx
, ctx
->nip
- 4);
2874 t0
= tcg_temp_new();
2875 t1
= tcg_const_i32(rD(ctx
->opcode
));
2876 gen_addr_imm_index(ctx
, t0
, 0);
2877 gen_helper_lmw(cpu_env
, t0
, t1
);
2879 tcg_temp_free_i32(t1
);
2883 static void gen_stmw(DisasContext
*ctx
)
2887 gen_set_access_type(ctx
, ACCESS_INT
);
2888 /* NIP cannot be restored if the memory exception comes from an helper */
2889 gen_update_nip(ctx
, ctx
->nip
- 4);
2890 t0
= tcg_temp_new();
2891 t1
= tcg_const_i32(rS(ctx
->opcode
));
2892 gen_addr_imm_index(ctx
, t0
, 0);
2893 gen_helper_stmw(cpu_env
, t0
, t1
);
2895 tcg_temp_free_i32(t1
);
2898 /*** Integer load and store strings ***/
2901 /* PowerPC32 specification says we must generate an exception if
2902 * rA is in the range of registers to be loaded.
2903 * In an other hand, IBM says this is valid, but rA won't be loaded.
2904 * For now, I'll follow the spec...
2906 static void gen_lswi(DisasContext
*ctx
)
2910 int nb
= NB(ctx
->opcode
);
2911 int start
= rD(ctx
->opcode
);
2912 int ra
= rA(ctx
->opcode
);
2918 if (unlikely(lsw_reg_in_range(start
, nr
, ra
))) {
2919 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
2922 gen_set_access_type(ctx
, ACCESS_INT
);
2923 /* NIP cannot be restored if the memory exception comes from an helper */
2924 gen_update_nip(ctx
, ctx
->nip
- 4);
2925 t0
= tcg_temp_new();
2926 gen_addr_register(ctx
, t0
);
2927 t1
= tcg_const_i32(nb
);
2928 t2
= tcg_const_i32(start
);
2929 gen_helper_lsw(cpu_env
, t0
, t1
, t2
);
2931 tcg_temp_free_i32(t1
);
2932 tcg_temp_free_i32(t2
);
2936 static void gen_lswx(DisasContext
*ctx
)
2939 TCGv_i32 t1
, t2
, t3
;
2940 gen_set_access_type(ctx
, ACCESS_INT
);
2941 /* NIP cannot be restored if the memory exception comes from an helper */
2942 gen_update_nip(ctx
, ctx
->nip
- 4);
2943 t0
= tcg_temp_new();
2944 gen_addr_reg_index(ctx
, t0
);
2945 t1
= tcg_const_i32(rD(ctx
->opcode
));
2946 t2
= tcg_const_i32(rA(ctx
->opcode
));
2947 t3
= tcg_const_i32(rB(ctx
->opcode
));
2948 gen_helper_lswx(cpu_env
, t0
, t1
, t2
, t3
);
2950 tcg_temp_free_i32(t1
);
2951 tcg_temp_free_i32(t2
);
2952 tcg_temp_free_i32(t3
);
2956 static void gen_stswi(DisasContext
*ctx
)
2960 int nb
= NB(ctx
->opcode
);
2961 gen_set_access_type(ctx
, ACCESS_INT
);
2962 /* NIP cannot be restored if the memory exception comes from an helper */
2963 gen_update_nip(ctx
, ctx
->nip
- 4);
2964 t0
= tcg_temp_new();
2965 gen_addr_register(ctx
, t0
);
2968 t1
= tcg_const_i32(nb
);
2969 t2
= tcg_const_i32(rS(ctx
->opcode
));
2970 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
2972 tcg_temp_free_i32(t1
);
2973 tcg_temp_free_i32(t2
);
2977 static void gen_stswx(DisasContext
*ctx
)
2981 gen_set_access_type(ctx
, ACCESS_INT
);
2982 /* NIP cannot be restored if the memory exception comes from an helper */
2983 gen_update_nip(ctx
, ctx
->nip
- 4);
2984 t0
= tcg_temp_new();
2985 gen_addr_reg_index(ctx
, t0
);
2986 t1
= tcg_temp_new_i32();
2987 tcg_gen_trunc_tl_i32(t1
, cpu_xer
);
2988 tcg_gen_andi_i32(t1
, t1
, 0x7F);
2989 t2
= tcg_const_i32(rS(ctx
->opcode
));
2990 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
2992 tcg_temp_free_i32(t1
);
2993 tcg_temp_free_i32(t2
);
2996 /*** Memory synchronisation ***/
2998 static void gen_eieio(DisasContext
*ctx
)
3002 #if !defined(CONFIG_USER_ONLY)
3003 static inline void gen_check_tlb_flush(DisasContext
*ctx
)
3008 if (!ctx
->lazy_tlb_flush
) {
3011 l
= gen_new_label();
3012 t
= tcg_temp_new_i32();
3013 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUPPCState
, tlb_need_flush
));
3014 tcg_gen_brcondi_i32(TCG_COND_EQ
, t
, 0, l
);
3015 gen_helper_check_tlb_flush(cpu_env
);
3017 tcg_temp_free_i32(t
);
3020 static inline void gen_check_tlb_flush(DisasContext
*ctx
) { }
3024 static void gen_isync(DisasContext
*ctx
)
3027 * We need to check for a pending TLB flush. This can only happen in
3028 * kernel mode however so check MSR_PR
3031 gen_check_tlb_flush(ctx
);
3033 gen_stop_exception(ctx
);
3036 #define LARX(name, len, loadop) \
3037 static void gen_##name(DisasContext *ctx) \
3040 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3041 gen_set_access_type(ctx, ACCESS_RES); \
3042 t0 = tcg_temp_local_new(); \
3043 gen_addr_reg_index(ctx, t0); \
3045 gen_check_align(ctx, t0, (len)-1); \
3047 gen_qemu_##loadop(ctx, gpr, t0); \
3048 tcg_gen_mov_tl(cpu_reserve, t0); \
3049 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3050 tcg_temp_free(t0); \
3054 LARX(lbarx
, 1, ld8u
);
3055 LARX(lharx
, 2, ld16u
);
3056 LARX(lwarx
, 4, ld32u
);
3059 #if defined(CONFIG_USER_ONLY)
3060 static void gen_conditional_store(DisasContext
*ctx
, TCGv EA
,
3063 TCGv t0
= tcg_temp_new();
3064 uint32_t save_exception
= ctx
->exception
;
3066 tcg_gen_st_tl(EA
, cpu_env
, offsetof(CPUPPCState
, reserve_ea
));
3067 tcg_gen_movi_tl(t0
, (size
<< 5) | reg
);
3068 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUPPCState
, reserve_info
));
3070 gen_update_nip(ctx
, ctx
->nip
-4);
3071 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3072 gen_exception(ctx
, POWERPC_EXCP_STCX
);
3073 ctx
->exception
= save_exception
;
3076 static void gen_conditional_store(DisasContext
*ctx
, TCGv EA
,
3081 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
3082 l1
= gen_new_label();
3083 tcg_gen_brcond_tl(TCG_COND_NE
, EA
, cpu_reserve
, l1
);
3084 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 1 << CRF_EQ
);
3085 #if defined(TARGET_PPC64)
3087 gen_qemu_st64(ctx
, cpu_gpr
[reg
], EA
);
3091 gen_qemu_st32(ctx
, cpu_gpr
[reg
], EA
);
3092 } else if (size
== 2) {
3093 gen_qemu_st16(ctx
, cpu_gpr
[reg
], EA
);
3094 #if defined(TARGET_PPC64)
3095 } else if (size
== 16) {
3096 TCGv gpr1
, gpr2
, EA8
;
3097 if (unlikely(ctx
->le_mode
)) {
3098 gpr1
= cpu_gpr
[reg
+1];
3099 gpr2
= cpu_gpr
[reg
];
3101 gpr1
= cpu_gpr
[reg
];
3102 gpr2
= cpu_gpr
[reg
+1];
3104 gen_qemu_st64(ctx
, gpr1
, EA
);
3105 EA8
= tcg_temp_local_new();
3106 gen_addr_add(ctx
, EA8
, EA
, 8);
3107 gen_qemu_st64(ctx
, gpr2
, EA8
);
3111 gen_qemu_st8(ctx
, cpu_gpr
[reg
], EA
);
3114 tcg_gen_movi_tl(cpu_reserve
, -1);
3118 #define STCX(name, len) \
3119 static void gen_##name(DisasContext *ctx) \
3122 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3123 gen_inval_exception(ctx, \
3124 POWERPC_EXCP_INVAL_INVAL); \
3127 gen_set_access_type(ctx, ACCESS_RES); \
3128 t0 = tcg_temp_local_new(); \
3129 gen_addr_reg_index(ctx, t0); \
3131 gen_check_align(ctx, t0, (len)-1); \
3133 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3134 tcg_temp_free(t0); \
3141 #if defined(TARGET_PPC64)
3143 LARX(ldarx
, 8, ld64
);
3146 static void gen_lqarx(DisasContext
*ctx
)
3149 int rd
= rD(ctx
->opcode
);
3152 if (unlikely((rd
& 1) || (rd
== rA(ctx
->opcode
)) ||
3153 (rd
== rB(ctx
->opcode
)))) {
3154 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3158 gen_set_access_type(ctx
, ACCESS_RES
);
3159 EA
= tcg_temp_local_new();
3160 gen_addr_reg_index(ctx
, EA
);
3161 gen_check_align(ctx
, EA
, 15);
3162 if (unlikely(ctx
->le_mode
)) {
3163 gpr1
= cpu_gpr
[rd
+1];
3167 gpr2
= cpu_gpr
[rd
+1];
3169 gen_qemu_ld64(ctx
, gpr1
, EA
);
3170 tcg_gen_mov_tl(cpu_reserve
, EA
);
3172 gen_addr_add(ctx
, EA
, EA
, 8);
3173 gen_qemu_ld64(ctx
, gpr2
, EA
);
3175 tcg_gen_st_tl(gpr1
, cpu_env
, offsetof(CPUPPCState
, reserve_val
));
3176 tcg_gen_st_tl(gpr2
, cpu_env
, offsetof(CPUPPCState
, reserve_val2
));
3184 #endif /* defined(TARGET_PPC64) */
3187 static void gen_sync(DisasContext
*ctx
)
3189 uint32_t l
= (ctx
->opcode
>> 21) & 3;
3192 * We may need to check for a pending TLB flush.
3194 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3196 * Additionally, this can only happen in kernel mode however so
3197 * check MSR_PR as well.
3199 if (((l
== 2) || !(ctx
->insns_flags
& PPC_64B
)) && !ctx
->pr
) {
3200 gen_check_tlb_flush(ctx
);
3205 static void gen_wait(DisasContext
*ctx
)
3207 TCGv_i32 t0
= tcg_const_i32(1);
3208 tcg_gen_st_i32(t0
, cpu_env
,
3209 -offsetof(PowerPCCPU
, env
) + offsetof(CPUState
, halted
));
3210 tcg_temp_free_i32(t0
);
3211 /* Stop translation, as the CPU is supposed to sleep from now */
3212 gen_exception_err(ctx
, EXCP_HLT
, 1);
3215 #if defined(TARGET_PPC64)
3216 static void gen_doze(DisasContext
*ctx
)
3218 #if defined(CONFIG_USER_ONLY)
3224 t
= tcg_const_i32(PPC_PM_DOZE
);
3225 gen_helper_pminsn(cpu_env
, t
);
3226 tcg_temp_free_i32(t
);
3227 gen_stop_exception(ctx
);
3228 #endif /* defined(CONFIG_USER_ONLY) */
3231 static void gen_nap(DisasContext
*ctx
)
3233 #if defined(CONFIG_USER_ONLY)
3239 t
= tcg_const_i32(PPC_PM_NAP
);
3240 gen_helper_pminsn(cpu_env
, t
);
3241 tcg_temp_free_i32(t
);
3242 gen_stop_exception(ctx
);
3243 #endif /* defined(CONFIG_USER_ONLY) */
3246 static void gen_sleep(DisasContext
*ctx
)
3248 #if defined(CONFIG_USER_ONLY)
3254 t
= tcg_const_i32(PPC_PM_SLEEP
);
3255 gen_helper_pminsn(cpu_env
, t
);
3256 tcg_temp_free_i32(t
);
3257 gen_stop_exception(ctx
);
3258 #endif /* defined(CONFIG_USER_ONLY) */
3261 static void gen_rvwinkle(DisasContext
*ctx
)
3263 #if defined(CONFIG_USER_ONLY)
3269 t
= tcg_const_i32(PPC_PM_RVWINKLE
);
3270 gen_helper_pminsn(cpu_env
, t
);
3271 tcg_temp_free_i32(t
);
3272 gen_stop_exception(ctx
);
3273 #endif /* defined(CONFIG_USER_ONLY) */
3275 #endif /* #if defined(TARGET_PPC64) */
3277 static inline void gen_update_cfar(DisasContext
*ctx
, target_ulong nip
)
3279 #if defined(TARGET_PPC64)
3281 tcg_gen_movi_tl(cpu_cfar
, nip
);
3285 static inline bool use_goto_tb(DisasContext
*ctx
, target_ulong dest
)
3287 if (unlikely(ctx
->singlestep_enabled
)) {
3291 #ifndef CONFIG_USER_ONLY
3292 return (ctx
->tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
3299 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
3301 if (NARROW_MODE(ctx
)) {
3302 dest
= (uint32_t) dest
;
3304 if (use_goto_tb(ctx
, dest
)) {
3306 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3307 tcg_gen_exit_tb((uintptr_t)ctx
->tb
+ n
);
3309 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3310 if (unlikely(ctx
->singlestep_enabled
)) {
3311 if ((ctx
->singlestep_enabled
&
3312 (CPU_BRANCH_STEP
| CPU_SINGLE_STEP
)) &&
3313 (ctx
->exception
== POWERPC_EXCP_BRANCH
||
3314 ctx
->exception
== POWERPC_EXCP_TRACE
)) {
3315 target_ulong tmp
= ctx
->nip
;
3317 gen_exception(ctx
, POWERPC_EXCP_TRACE
);
3320 if (ctx
->singlestep_enabled
& GDBSTUB_SINGLE_STEP
) {
3321 gen_debug_exception(ctx
);
3328 static inline void gen_setlr(DisasContext
*ctx
, target_ulong nip
)
3330 if (NARROW_MODE(ctx
)) {
3331 nip
= (uint32_t)nip
;
3333 tcg_gen_movi_tl(cpu_lr
, nip
);
3337 static void gen_b(DisasContext
*ctx
)
3339 target_ulong li
, target
;
3341 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3342 /* sign extend LI */
3343 li
= LI(ctx
->opcode
);
3344 li
= (li
^ 0x02000000) - 0x02000000;
3345 if (likely(AA(ctx
->opcode
) == 0)) {
3346 target
= ctx
->nip
+ li
- 4;
3350 if (LK(ctx
->opcode
)) {
3351 gen_setlr(ctx
, ctx
->nip
);
3353 gen_update_cfar(ctx
, ctx
->nip
);
3354 gen_goto_tb(ctx
, 0, target
);
3362 static inline void gen_bcond(DisasContext
*ctx
, int type
)
3364 uint32_t bo
= BO(ctx
->opcode
);
3368 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3369 if (type
== BCOND_LR
|| type
== BCOND_CTR
|| type
== BCOND_TAR
) {
3370 target
= tcg_temp_local_new();
3371 if (type
== BCOND_CTR
)
3372 tcg_gen_mov_tl(target
, cpu_ctr
);
3373 else if (type
== BCOND_TAR
)
3374 gen_load_spr(target
, SPR_TAR
);
3376 tcg_gen_mov_tl(target
, cpu_lr
);
3378 TCGV_UNUSED(target
);
3380 if (LK(ctx
->opcode
))
3381 gen_setlr(ctx
, ctx
->nip
);
3382 l1
= gen_new_label();
3383 if ((bo
& 0x4) == 0) {
3384 /* Decrement and test CTR */
3385 TCGv temp
= tcg_temp_new();
3386 if (unlikely(type
== BCOND_CTR
)) {
3387 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3390 tcg_gen_subi_tl(cpu_ctr
, cpu_ctr
, 1);
3391 if (NARROW_MODE(ctx
)) {
3392 tcg_gen_ext32u_tl(temp
, cpu_ctr
);
3394 tcg_gen_mov_tl(temp
, cpu_ctr
);
3397 tcg_gen_brcondi_tl(TCG_COND_NE
, temp
, 0, l1
);
3399 tcg_gen_brcondi_tl(TCG_COND_EQ
, temp
, 0, l1
);
3401 tcg_temp_free(temp
);
3403 if ((bo
& 0x10) == 0) {
3405 uint32_t bi
= BI(ctx
->opcode
);
3406 uint32_t mask
= 0x08 >> (bi
& 0x03);
3407 TCGv_i32 temp
= tcg_temp_new_i32();
3410 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3411 tcg_gen_brcondi_i32(TCG_COND_EQ
, temp
, 0, l1
);
3413 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3414 tcg_gen_brcondi_i32(TCG_COND_NE
, temp
, 0, l1
);
3416 tcg_temp_free_i32(temp
);
3418 gen_update_cfar(ctx
, ctx
->nip
);
3419 if (type
== BCOND_IM
) {
3420 target_ulong li
= (target_long
)((int16_t)(BD(ctx
->opcode
)));
3421 if (likely(AA(ctx
->opcode
) == 0)) {
3422 gen_goto_tb(ctx
, 0, ctx
->nip
+ li
- 4);
3424 gen_goto_tb(ctx
, 0, li
);
3427 gen_goto_tb(ctx
, 1, ctx
->nip
);
3429 if (NARROW_MODE(ctx
)) {
3430 tcg_gen_andi_tl(cpu_nip
, target
, (uint32_t)~3);
3432 tcg_gen_andi_tl(cpu_nip
, target
, ~3);
3436 gen_update_nip(ctx
, ctx
->nip
);
3439 if (type
== BCOND_LR
|| type
== BCOND_CTR
|| type
== BCOND_TAR
) {
3440 tcg_temp_free(target
);
3444 static void gen_bc(DisasContext
*ctx
)
3446 gen_bcond(ctx
, BCOND_IM
);
3449 static void gen_bcctr(DisasContext
*ctx
)
3451 gen_bcond(ctx
, BCOND_CTR
);
3454 static void gen_bclr(DisasContext
*ctx
)
3456 gen_bcond(ctx
, BCOND_LR
);
3459 static void gen_bctar(DisasContext
*ctx
)
3461 gen_bcond(ctx
, BCOND_TAR
);
3464 /*** Condition register logical ***/
3465 #define GEN_CRLOGIC(name, tcg_op, opc) \
3466 static void glue(gen_, name)(DisasContext *ctx) \
3471 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3472 t0 = tcg_temp_new_i32(); \
3474 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3476 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3478 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3479 t1 = tcg_temp_new_i32(); \
3480 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3482 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3484 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3486 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3487 tcg_op(t0, t0, t1); \
3488 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3489 tcg_gen_andi_i32(t0, t0, bitmask); \
3490 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3491 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3492 tcg_temp_free_i32(t0); \
3493 tcg_temp_free_i32(t1); \
3497 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08);
3499 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04);
3501 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09);
3503 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07);
3505 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01);
3507 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E);
3509 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D);
3511 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06);
3514 static void gen_mcrf(DisasContext
*ctx
)
3516 tcg_gen_mov_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfS(ctx
->opcode
)]);
3519 /*** System linkage ***/
3521 /* rfi (supervisor only) */
3522 static void gen_rfi(DisasContext
*ctx
)
3524 #if defined(CONFIG_USER_ONLY)
3527 /* FIXME: This instruction doesn't exist anymore on 64-bit server
3528 * processors compliant with arch 2.x, we should remove it there,
3529 * but we need to fix OpenBIOS not to use it on 970 first
3531 /* Restore CPU state */
3533 gen_update_cfar(ctx
, ctx
->nip
);
3534 gen_helper_rfi(cpu_env
);
3535 gen_sync_exception(ctx
);
3539 #if defined(TARGET_PPC64)
3540 static void gen_rfid(DisasContext
*ctx
)
3542 #if defined(CONFIG_USER_ONLY)
3545 /* Restore CPU state */
3547 gen_update_cfar(ctx
, ctx
->nip
);
3548 gen_helper_rfid(cpu_env
);
3549 gen_sync_exception(ctx
);
3553 static void gen_hrfid(DisasContext
*ctx
)
3555 #if defined(CONFIG_USER_ONLY)
3558 /* Restore CPU state */
3560 gen_helper_hrfid(cpu_env
);
3561 gen_sync_exception(ctx
);
3567 #if defined(CONFIG_USER_ONLY)
3568 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3570 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3572 static void gen_sc(DisasContext
*ctx
)
3576 lev
= (ctx
->opcode
>> 5) & 0x7F;
3577 gen_exception_err(ctx
, POWERPC_SYSCALL
, lev
);
3583 static void gen_tw(DisasContext
*ctx
)
3585 TCGv_i32 t0
= tcg_const_i32(TO(ctx
->opcode
));
3586 /* Update the nip since this might generate a trap exception */
3587 gen_update_nip(ctx
, ctx
->nip
);
3588 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
3590 tcg_temp_free_i32(t0
);
3594 static void gen_twi(DisasContext
*ctx
)
3596 TCGv t0
= tcg_const_tl(SIMM(ctx
->opcode
));
3597 TCGv_i32 t1
= tcg_const_i32(TO(ctx
->opcode
));
3598 /* Update the nip since this might generate a trap exception */
3599 gen_update_nip(ctx
, ctx
->nip
);
3600 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
3602 tcg_temp_free_i32(t1
);
3605 #if defined(TARGET_PPC64)
3607 static void gen_td(DisasContext
*ctx
)
3609 TCGv_i32 t0
= tcg_const_i32(TO(ctx
->opcode
));
3610 /* Update the nip since this might generate a trap exception */
3611 gen_update_nip(ctx
, ctx
->nip
);
3612 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
3614 tcg_temp_free_i32(t0
);
3618 static void gen_tdi(DisasContext
*ctx
)
3620 TCGv t0
= tcg_const_tl(SIMM(ctx
->opcode
));
3621 TCGv_i32 t1
= tcg_const_i32(TO(ctx
->opcode
));
3622 /* Update the nip since this might generate a trap exception */
3623 gen_update_nip(ctx
, ctx
->nip
);
3624 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
3626 tcg_temp_free_i32(t1
);
3630 /*** Processor control ***/
3632 static void gen_read_xer(TCGv dst
)
3634 TCGv t0
= tcg_temp_new();
3635 TCGv t1
= tcg_temp_new();
3636 TCGv t2
= tcg_temp_new();
3637 tcg_gen_mov_tl(dst
, cpu_xer
);
3638 tcg_gen_shli_tl(t0
, cpu_so
, XER_SO
);
3639 tcg_gen_shli_tl(t1
, cpu_ov
, XER_OV
);
3640 tcg_gen_shli_tl(t2
, cpu_ca
, XER_CA
);
3641 tcg_gen_or_tl(t0
, t0
, t1
);
3642 tcg_gen_or_tl(dst
, dst
, t2
);
3643 tcg_gen_or_tl(dst
, dst
, t0
);
3649 static void gen_write_xer(TCGv src
)
3651 tcg_gen_andi_tl(cpu_xer
, src
,
3652 ~((1u << XER_SO
) | (1u << XER_OV
) | (1u << XER_CA
)));
3653 tcg_gen_shri_tl(cpu_so
, src
, XER_SO
);
3654 tcg_gen_shri_tl(cpu_ov
, src
, XER_OV
);
3655 tcg_gen_shri_tl(cpu_ca
, src
, XER_CA
);
3656 tcg_gen_andi_tl(cpu_so
, cpu_so
, 1);
3657 tcg_gen_andi_tl(cpu_ov
, cpu_ov
, 1);
3658 tcg_gen_andi_tl(cpu_ca
, cpu_ca
, 1);
3662 static void gen_mcrxr(DisasContext
*ctx
)
3664 TCGv_i32 t0
= tcg_temp_new_i32();
3665 TCGv_i32 t1
= tcg_temp_new_i32();
3666 TCGv_i32 dst
= cpu_crf
[crfD(ctx
->opcode
)];
3668 tcg_gen_trunc_tl_i32(t0
, cpu_so
);
3669 tcg_gen_trunc_tl_i32(t1
, cpu_ov
);
3670 tcg_gen_trunc_tl_i32(dst
, cpu_ca
);
3671 tcg_gen_shli_i32(t0
, t0
, 3);
3672 tcg_gen_shli_i32(t1
, t1
, 2);
3673 tcg_gen_shli_i32(dst
, dst
, 1);
3674 tcg_gen_or_i32(dst
, dst
, t0
);
3675 tcg_gen_or_i32(dst
, dst
, t1
);
3676 tcg_temp_free_i32(t0
);
3677 tcg_temp_free_i32(t1
);
3679 tcg_gen_movi_tl(cpu_so
, 0);
3680 tcg_gen_movi_tl(cpu_ov
, 0);
3681 tcg_gen_movi_tl(cpu_ca
, 0);
3685 static void gen_mfcr(DisasContext
*ctx
)
3689 if (likely(ctx
->opcode
& 0x00100000)) {
3690 crm
= CRM(ctx
->opcode
);
3691 if (likely(crm
&& ((crm
& (crm
- 1)) == 0))) {
3693 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_crf
[7 - crn
]);
3694 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)],
3695 cpu_gpr
[rD(ctx
->opcode
)], crn
* 4);
3698 TCGv_i32 t0
= tcg_temp_new_i32();
3699 tcg_gen_mov_i32(t0
, cpu_crf
[0]);
3700 tcg_gen_shli_i32(t0
, t0
, 4);
3701 tcg_gen_or_i32(t0
, t0
, cpu_crf
[1]);
3702 tcg_gen_shli_i32(t0
, t0
, 4);
3703 tcg_gen_or_i32(t0
, t0
, cpu_crf
[2]);
3704 tcg_gen_shli_i32(t0
, t0
, 4);
3705 tcg_gen_or_i32(t0
, t0
, cpu_crf
[3]);
3706 tcg_gen_shli_i32(t0
, t0
, 4);
3707 tcg_gen_or_i32(t0
, t0
, cpu_crf
[4]);
3708 tcg_gen_shli_i32(t0
, t0
, 4);
3709 tcg_gen_or_i32(t0
, t0
, cpu_crf
[5]);
3710 tcg_gen_shli_i32(t0
, t0
, 4);
3711 tcg_gen_or_i32(t0
, t0
, cpu_crf
[6]);
3712 tcg_gen_shli_i32(t0
, t0
, 4);
3713 tcg_gen_or_i32(t0
, t0
, cpu_crf
[7]);
3714 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
3715 tcg_temp_free_i32(t0
);
3720 static void gen_mfmsr(DisasContext
*ctx
)
3723 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_msr
);
3726 static void spr_noaccess(DisasContext
*ctx
, int gprn
, int sprn
)
3729 sprn
= ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
3730 printf("ERROR: try to access SPR %d !\n", sprn
);
3733 #define SPR_NOACCESS (&spr_noaccess)
3736 static inline void gen_op_mfspr(DisasContext
*ctx
)
3738 void (*read_cb
)(DisasContext
*ctx
, int gprn
, int sprn
);
3739 uint32_t sprn
= SPR(ctx
->opcode
);
3741 #if defined(CONFIG_USER_ONLY)
3742 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
3745 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
3746 } else if (ctx
->hv
) {
3747 read_cb
= ctx
->spr_cb
[sprn
].hea_read
;
3749 read_cb
= ctx
->spr_cb
[sprn
].oea_read
;
3752 if (likely(read_cb
!= NULL
)) {
3753 if (likely(read_cb
!= SPR_NOACCESS
)) {
3754 (*read_cb
)(ctx
, rD(ctx
->opcode
), sprn
);
3756 /* Privilege exception */
3757 /* This is a hack to avoid warnings when running Linux:
3758 * this OS breaks the PowerPC virtualisation model,
3759 * allowing userland application to read the PVR
3761 if (sprn
!= SPR_PVR
) {
3762 fprintf(stderr
, "Trying to read privileged spr %d (0x%03x) at "
3763 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
3764 if (qemu_log_separate()) {
3765 qemu_log("Trying to read privileged spr %d (0x%03x) at "
3766 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
3769 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3772 /* ISA 2.07 defines these as no-ops */
3773 if ((ctx
->insns_flags2
& PPC2_ISA207S
) &&
3774 (sprn
>= 808 && sprn
<= 811)) {
3779 fprintf(stderr
, "Trying to read invalid spr %d (0x%03x) at "
3780 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
3781 if (qemu_log_separate()) {
3782 qemu_log("Trying to read invalid spr %d (0x%03x) at "
3783 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
3786 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3787 * it can generate a priv, a hv emu or a no-op
3791 gen_priv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
3794 if (ctx
->pr
|| sprn
== 0 || sprn
== 4 || sprn
== 5 || sprn
== 6) {
3795 gen_hvpriv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
3801 static void gen_mfspr(DisasContext
*ctx
)
3807 static void gen_mftb(DisasContext
*ctx
)
3813 static void gen_mtcrf(DisasContext
*ctx
)
3817 crm
= CRM(ctx
->opcode
);
3818 if (likely((ctx
->opcode
& 0x00100000))) {
3819 if (crm
&& ((crm
& (crm
- 1)) == 0)) {
3820 TCGv_i32 temp
= tcg_temp_new_i32();
3822 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
3823 tcg_gen_shri_i32(temp
, temp
, crn
* 4);
3824 tcg_gen_andi_i32(cpu_crf
[7 - crn
], temp
, 0xf);
3825 tcg_temp_free_i32(temp
);
3828 TCGv_i32 temp
= tcg_temp_new_i32();
3829 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
3830 for (crn
= 0 ; crn
< 8 ; crn
++) {
3831 if (crm
& (1 << crn
)) {
3832 tcg_gen_shri_i32(cpu_crf
[7 - crn
], temp
, crn
* 4);
3833 tcg_gen_andi_i32(cpu_crf
[7 - crn
], cpu_crf
[7 - crn
], 0xf);
3836 tcg_temp_free_i32(temp
);
3841 #if defined(TARGET_PPC64)
3842 static void gen_mtmsrd(DisasContext
*ctx
)
3846 #if !defined(CONFIG_USER_ONLY)
3847 if (ctx
->opcode
& 0x00010000) {
3848 /* Special form that does not need any synchronisation */
3849 TCGv t0
= tcg_temp_new();
3850 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
3851 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(target_ulong
)((1 << MSR_RI
) | (1 << MSR_EE
)));
3852 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
3855 /* XXX: we need to update nip before the store
3856 * if we enter power saving mode, we will exit the loop
3857 * directly from ppc_store_msr
3859 gen_update_nip(ctx
, ctx
->nip
);
3860 gen_helper_store_msr(cpu_env
, cpu_gpr
[rS(ctx
->opcode
)]);
3861 /* Must stop the translation as machine state (may have) changed */
3862 /* Note that mtmsr is not always defined as context-synchronizing */
3863 gen_stop_exception(ctx
);
3865 #endif /* !defined(CONFIG_USER_ONLY) */
3867 #endif /* defined(TARGET_PPC64) */
3869 static void gen_mtmsr(DisasContext
*ctx
)
3873 #if !defined(CONFIG_USER_ONLY)
3874 if (ctx
->opcode
& 0x00010000) {
3875 /* Special form that does not need any synchronisation */
3876 TCGv t0
= tcg_temp_new();
3877 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
3878 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(target_ulong
)((1 << MSR_RI
) | (1 << MSR_EE
)));
3879 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
3882 TCGv msr
= tcg_temp_new();
3884 /* XXX: we need to update nip before the store
3885 * if we enter power saving mode, we will exit the loop
3886 * directly from ppc_store_msr
3888 gen_update_nip(ctx
, ctx
->nip
);
3889 #if defined(TARGET_PPC64)
3890 tcg_gen_deposit_tl(msr
, cpu_msr
, cpu_gpr
[rS(ctx
->opcode
)], 0, 32);
3892 tcg_gen_mov_tl(msr
, cpu_gpr
[rS(ctx
->opcode
)]);
3894 gen_helper_store_msr(cpu_env
, msr
);
3896 /* Must stop the translation as machine state (may have) changed */
3897 /* Note that mtmsr is not always defined as context-synchronizing */
3898 gen_stop_exception(ctx
);
3904 static void gen_mtspr(DisasContext
*ctx
)
3906 void (*write_cb
)(DisasContext
*ctx
, int sprn
, int gprn
);
3907 uint32_t sprn
= SPR(ctx
->opcode
);
3909 #if defined(CONFIG_USER_ONLY)
3910 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
3913 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
3914 } else if (ctx
->hv
) {
3915 write_cb
= ctx
->spr_cb
[sprn
].hea_write
;
3917 write_cb
= ctx
->spr_cb
[sprn
].oea_write
;
3920 if (likely(write_cb
!= NULL
)) {
3921 if (likely(write_cb
!= SPR_NOACCESS
)) {
3922 (*write_cb
)(ctx
, sprn
, rS(ctx
->opcode
));
3924 /* Privilege exception */
3925 fprintf(stderr
, "Trying to write privileged spr %d (0x%03x) at "
3926 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
3927 if (qemu_log_separate()) {
3928 qemu_log("Trying to write privileged spr %d (0x%03x) at "
3929 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
3931 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3934 /* ISA 2.07 defines these as no-ops */
3935 if ((ctx
->insns_flags2
& PPC2_ISA207S
) &&
3936 (sprn
>= 808 && sprn
<= 811)) {
3942 if (qemu_log_separate()) {
3943 qemu_log("Trying to write invalid spr %d (0x%03x) at "
3944 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
3946 fprintf(stderr
, "Trying to write invalid spr %d (0x%03x) at "
3947 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
3950 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3951 * it can generate a priv, a hv emu or a no-op
3955 gen_priv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
3958 if (ctx
->pr
|| sprn
== 0) {
3959 gen_hvpriv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
3965 #if defined(TARGET_PPC64)
3967 static void gen_setb(DisasContext
*ctx
)
3969 TCGv_i32 t0
= tcg_temp_new_i32();
3970 TCGv_i32 t8
= tcg_temp_new_i32();
3971 TCGv_i32 tm1
= tcg_temp_new_i32();
3972 int crf
= crfS(ctx
->opcode
);
3974 tcg_gen_setcondi_i32(TCG_COND_GEU
, t0
, cpu_crf
[crf
], 4);
3975 tcg_gen_movi_i32(t8
, 8);
3976 tcg_gen_movi_i32(tm1
, -1);
3977 tcg_gen_movcond_i32(TCG_COND_GEU
, t0
, cpu_crf
[crf
], t8
, tm1
, t0
);
3978 tcg_gen_ext_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
3980 tcg_temp_free_i32(t0
);
3981 tcg_temp_free_i32(t8
);
3982 tcg_temp_free_i32(tm1
);
3986 /*** Cache management ***/
3989 static void gen_dcbf(DisasContext
*ctx
)
3991 /* XXX: specification says this is treated as a load by the MMU */
3993 gen_set_access_type(ctx
, ACCESS_CACHE
);
3994 t0
= tcg_temp_new();
3995 gen_addr_reg_index(ctx
, t0
);
3996 gen_qemu_ld8u(ctx
, t0
, t0
);
4000 /* dcbi (Supervisor only) */
4001 static void gen_dcbi(DisasContext
*ctx
)
4003 #if defined(CONFIG_USER_ONLY)
4009 EA
= tcg_temp_new();
4010 gen_set_access_type(ctx
, ACCESS_CACHE
);
4011 gen_addr_reg_index(ctx
, EA
);
4012 val
= tcg_temp_new();
4013 /* XXX: specification says this should be treated as a store by the MMU */
4014 gen_qemu_ld8u(ctx
, val
, EA
);
4015 gen_qemu_st8(ctx
, val
, EA
);
4018 #endif /* defined(CONFIG_USER_ONLY) */
4022 static void gen_dcbst(DisasContext
*ctx
)
4024 /* XXX: specification say this is treated as a load by the MMU */
4026 gen_set_access_type(ctx
, ACCESS_CACHE
);
4027 t0
= tcg_temp_new();
4028 gen_addr_reg_index(ctx
, t0
);
4029 gen_qemu_ld8u(ctx
, t0
, t0
);
4034 static void gen_dcbt(DisasContext
*ctx
)
4036 /* interpreted as no-op */
4037 /* XXX: specification say this is treated as a load by the MMU
4038 * but does not generate any exception
4043 static void gen_dcbtst(DisasContext
*ctx
)
4045 /* interpreted as no-op */
4046 /* XXX: specification say this is treated as a load by the MMU
4047 * but does not generate any exception
4052 static void gen_dcbtls(DisasContext
*ctx
)
4054 /* Always fails locking the cache */
4055 TCGv t0
= tcg_temp_new();
4056 gen_load_spr(t0
, SPR_Exxx_L1CSR0
);
4057 tcg_gen_ori_tl(t0
, t0
, L1CSR0_CUL
);
4058 gen_store_spr(SPR_Exxx_L1CSR0
, t0
);
4063 static void gen_dcbz(DisasContext
*ctx
)
4066 TCGv_i32 tcgv_is_dcbzl
;
4067 int is_dcbzl
= ctx
->opcode
& 0x00200000 ? 1 : 0;
4069 gen_set_access_type(ctx
, ACCESS_CACHE
);
4070 /* NIP cannot be restored if the memory exception comes from an helper */
4071 gen_update_nip(ctx
, ctx
->nip
- 4);
4072 tcgv_addr
= tcg_temp_new();
4073 tcgv_is_dcbzl
= tcg_const_i32(is_dcbzl
);
4075 gen_addr_reg_index(ctx
, tcgv_addr
);
4076 gen_helper_dcbz(cpu_env
, tcgv_addr
, tcgv_is_dcbzl
);
4078 tcg_temp_free(tcgv_addr
);
4079 tcg_temp_free_i32(tcgv_is_dcbzl
);
4083 static void gen_dst(DisasContext
*ctx
)
4085 if (rA(ctx
->opcode
) == 0) {
4086 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
4088 /* interpreted as no-op */
4093 static void gen_dstst(DisasContext
*ctx
)
4095 if (rA(ctx
->opcode
) == 0) {
4096 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
4098 /* interpreted as no-op */
4104 static void gen_dss(DisasContext
*ctx
)
4106 /* interpreted as no-op */
4110 static void gen_icbi(DisasContext
*ctx
)
4113 gen_set_access_type(ctx
, ACCESS_CACHE
);
4114 /* NIP cannot be restored if the memory exception comes from an helper */
4115 gen_update_nip(ctx
, ctx
->nip
- 4);
4116 t0
= tcg_temp_new();
4117 gen_addr_reg_index(ctx
, t0
);
4118 gen_helper_icbi(cpu_env
, t0
);
4124 static void gen_dcba(DisasContext
*ctx
)
4126 /* interpreted as no-op */
4127 /* XXX: specification say this is treated as a store by the MMU
4128 * but does not generate any exception
4132 /*** Segment register manipulation ***/
4133 /* Supervisor only: */
4136 static void gen_mfsr(DisasContext
*ctx
)
4138 #if defined(CONFIG_USER_ONLY)
4144 t0
= tcg_const_tl(SR(ctx
->opcode
));
4145 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4147 #endif /* defined(CONFIG_USER_ONLY) */
4151 static void gen_mfsrin(DisasContext
*ctx
)
4153 #if defined(CONFIG_USER_ONLY)
4159 t0
= tcg_temp_new();
4160 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4161 tcg_gen_andi_tl(t0
, t0
, 0xF);
4162 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4164 #endif /* defined(CONFIG_USER_ONLY) */
4168 static void gen_mtsr(DisasContext
*ctx
)
4170 #if defined(CONFIG_USER_ONLY)
4176 t0
= tcg_const_tl(SR(ctx
->opcode
));
4177 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4179 #endif /* defined(CONFIG_USER_ONLY) */
4183 static void gen_mtsrin(DisasContext
*ctx
)
4185 #if defined(CONFIG_USER_ONLY)
4191 t0
= tcg_temp_new();
4192 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4193 tcg_gen_andi_tl(t0
, t0
, 0xF);
4194 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rD(ctx
->opcode
)]);
4196 #endif /* defined(CONFIG_USER_ONLY) */
4199 #if defined(TARGET_PPC64)
4200 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4203 static void gen_mfsr_64b(DisasContext
*ctx
)
4205 #if defined(CONFIG_USER_ONLY)
4211 t0
= tcg_const_tl(SR(ctx
->opcode
));
4212 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4214 #endif /* defined(CONFIG_USER_ONLY) */
4218 static void gen_mfsrin_64b(DisasContext
*ctx
)
4220 #if defined(CONFIG_USER_ONLY)
4226 t0
= tcg_temp_new();
4227 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4228 tcg_gen_andi_tl(t0
, t0
, 0xF);
4229 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4231 #endif /* defined(CONFIG_USER_ONLY) */
4235 static void gen_mtsr_64b(DisasContext
*ctx
)
4237 #if defined(CONFIG_USER_ONLY)
4243 t0
= tcg_const_tl(SR(ctx
->opcode
));
4244 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4246 #endif /* defined(CONFIG_USER_ONLY) */
4250 static void gen_mtsrin_64b(DisasContext
*ctx
)
4252 #if defined(CONFIG_USER_ONLY)
4258 t0
= tcg_temp_new();
4259 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4260 tcg_gen_andi_tl(t0
, t0
, 0xF);
4261 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4263 #endif /* defined(CONFIG_USER_ONLY) */
4267 static void gen_slbmte(DisasContext
*ctx
)
4269 #if defined(CONFIG_USER_ONLY)
4274 gen_helper_store_slb(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)],
4275 cpu_gpr
[rS(ctx
->opcode
)]);
4276 #endif /* defined(CONFIG_USER_ONLY) */
4279 static void gen_slbmfee(DisasContext
*ctx
)
4281 #if defined(CONFIG_USER_ONLY)
4286 gen_helper_load_slb_esid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4287 cpu_gpr
[rB(ctx
->opcode
)]);
4288 #endif /* defined(CONFIG_USER_ONLY) */
4291 static void gen_slbmfev(DisasContext
*ctx
)
4293 #if defined(CONFIG_USER_ONLY)
4298 gen_helper_load_slb_vsid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4299 cpu_gpr
[rB(ctx
->opcode
)]);
4300 #endif /* defined(CONFIG_USER_ONLY) */
4303 static void gen_slbfee_(DisasContext
*ctx
)
4305 #if defined(CONFIG_USER_ONLY)
4306 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4310 if (unlikely(ctx
->pr
)) {
4311 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4314 gen_helper_find_slb_vsid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4315 cpu_gpr
[rB(ctx
->opcode
)]);
4316 l1
= gen_new_label();
4317 l2
= gen_new_label();
4318 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
4319 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rS(ctx
->opcode
)], -1, l1
);
4320 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 1 << CRF_EQ
);
4323 tcg_gen_movi_tl(cpu_gpr
[rS(ctx
->opcode
)], 0);
4327 #endif /* defined(TARGET_PPC64) */
4329 /*** Lookaside buffer management ***/
4330 /* Optional & supervisor only: */
4333 static void gen_tlbia(DisasContext
*ctx
)
4335 #if defined(CONFIG_USER_ONLY)
4340 gen_helper_tlbia(cpu_env
);
4341 #endif /* defined(CONFIG_USER_ONLY) */
4345 static void gen_tlbiel(DisasContext
*ctx
)
4347 #if defined(CONFIG_USER_ONLY)
4352 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4353 #endif /* defined(CONFIG_USER_ONLY) */
4357 static void gen_tlbie(DisasContext
*ctx
)
4359 #if defined(CONFIG_USER_ONLY)
4364 if (NARROW_MODE(ctx
)) {
4365 TCGv t0
= tcg_temp_new();
4366 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
4367 gen_helper_tlbie(cpu_env
, t0
);
4370 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4372 #endif /* defined(CONFIG_USER_ONLY) */
4376 static void gen_tlbsync(DisasContext
*ctx
)
4378 #if defined(CONFIG_USER_ONLY)
4383 /* tlbsync is a nop for server, ptesync handles delayed tlb flush,
4384 * embedded however needs to deal with tlbsync. We don't try to be
4385 * fancy and swallow the overhead of checking for both.
4387 gen_check_tlb_flush(ctx
);
4388 #endif /* defined(CONFIG_USER_ONLY) */
4391 #if defined(TARGET_PPC64)
4393 static void gen_slbia(DisasContext
*ctx
)
4395 #if defined(CONFIG_USER_ONLY)
4400 gen_helper_slbia(cpu_env
);
4401 #endif /* defined(CONFIG_USER_ONLY) */
4405 static void gen_slbie(DisasContext
*ctx
)
4407 #if defined(CONFIG_USER_ONLY)
4412 gen_helper_slbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4413 #endif /* defined(CONFIG_USER_ONLY) */
4415 #endif /* defined(TARGET_PPC64) */
4417 /*** External control ***/
4421 static void gen_eciwx(DisasContext
*ctx
)
4424 /* Should check EAR[E] ! */
4425 gen_set_access_type(ctx
, ACCESS_EXT
);
4426 t0
= tcg_temp_new();
4427 gen_addr_reg_index(ctx
, t0
);
4428 gen_check_align(ctx
, t0
, 0x03);
4429 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
4434 static void gen_ecowx(DisasContext
*ctx
)
4437 /* Should check EAR[E] ! */
4438 gen_set_access_type(ctx
, ACCESS_EXT
);
4439 t0
= tcg_temp_new();
4440 gen_addr_reg_index(ctx
, t0
);
4441 gen_check_align(ctx
, t0
, 0x03);
4442 gen_qemu_st32(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
4446 /* PowerPC 601 specific instructions */
4449 static void gen_abs(DisasContext
*ctx
)
4451 TCGLabel
*l1
= gen_new_label();
4452 TCGLabel
*l2
= gen_new_label();
4453 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4454 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4457 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4459 if (unlikely(Rc(ctx
->opcode
) != 0))
4460 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4464 static void gen_abso(DisasContext
*ctx
)
4466 TCGLabel
*l1
= gen_new_label();
4467 TCGLabel
*l2
= gen_new_label();
4468 TCGLabel
*l3
= gen_new_label();
4469 /* Start with XER OV disabled, the most likely case */
4470 tcg_gen_movi_tl(cpu_ov
, 0);
4471 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l2
);
4472 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[rA(ctx
->opcode
)], 0x80000000, l1
);
4473 tcg_gen_movi_tl(cpu_ov
, 1);
4474 tcg_gen_movi_tl(cpu_so
, 1);
4477 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4480 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4482 if (unlikely(Rc(ctx
->opcode
) != 0))
4483 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4487 static void gen_clcs(DisasContext
*ctx
)
4489 TCGv_i32 t0
= tcg_const_i32(rA(ctx
->opcode
));
4490 gen_helper_clcs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4491 tcg_temp_free_i32(t0
);
4492 /* Rc=1 sets CR0 to an undefined state */
4496 static void gen_div(DisasContext
*ctx
)
4498 gen_helper_div(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4499 cpu_gpr
[rB(ctx
->opcode
)]);
4500 if (unlikely(Rc(ctx
->opcode
) != 0))
4501 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4505 static void gen_divo(DisasContext
*ctx
)
4507 gen_helper_divo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4508 cpu_gpr
[rB(ctx
->opcode
)]);
4509 if (unlikely(Rc(ctx
->opcode
) != 0))
4510 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4514 static void gen_divs(DisasContext
*ctx
)
4516 gen_helper_divs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4517 cpu_gpr
[rB(ctx
->opcode
)]);
4518 if (unlikely(Rc(ctx
->opcode
) != 0))
4519 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4522 /* divso - divso. */
4523 static void gen_divso(DisasContext
*ctx
)
4525 gen_helper_divso(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
4526 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4527 if (unlikely(Rc(ctx
->opcode
) != 0))
4528 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4532 static void gen_doz(DisasContext
*ctx
)
4534 TCGLabel
*l1
= gen_new_label();
4535 TCGLabel
*l2
= gen_new_label();
4536 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
4537 tcg_gen_sub_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4540 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4542 if (unlikely(Rc(ctx
->opcode
) != 0))
4543 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4547 static void gen_dozo(DisasContext
*ctx
)
4549 TCGLabel
*l1
= gen_new_label();
4550 TCGLabel
*l2
= gen_new_label();
4551 TCGv t0
= tcg_temp_new();
4552 TCGv t1
= tcg_temp_new();
4553 TCGv t2
= tcg_temp_new();
4554 /* Start with XER OV disabled, the most likely case */
4555 tcg_gen_movi_tl(cpu_ov
, 0);
4556 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
4557 tcg_gen_sub_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4558 tcg_gen_xor_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4559 tcg_gen_xor_tl(t2
, cpu_gpr
[rA(ctx
->opcode
)], t0
);
4560 tcg_gen_andc_tl(t1
, t1
, t2
);
4561 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4562 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
4563 tcg_gen_movi_tl(cpu_ov
, 1);
4564 tcg_gen_movi_tl(cpu_so
, 1);
4567 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4572 if (unlikely(Rc(ctx
->opcode
) != 0))
4573 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4577 static void gen_dozi(DisasContext
*ctx
)
4579 target_long simm
= SIMM(ctx
->opcode
);
4580 TCGLabel
*l1
= gen_new_label();
4581 TCGLabel
*l2
= gen_new_label();
4582 tcg_gen_brcondi_tl(TCG_COND_LT
, cpu_gpr
[rA(ctx
->opcode
)], simm
, l1
);
4583 tcg_gen_subfi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
, cpu_gpr
[rA(ctx
->opcode
)]);
4586 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4588 if (unlikely(Rc(ctx
->opcode
) != 0))
4589 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4592 /* lscbx - lscbx. */
4593 static void gen_lscbx(DisasContext
*ctx
)
4595 TCGv t0
= tcg_temp_new();
4596 TCGv_i32 t1
= tcg_const_i32(rD(ctx
->opcode
));
4597 TCGv_i32 t2
= tcg_const_i32(rA(ctx
->opcode
));
4598 TCGv_i32 t3
= tcg_const_i32(rB(ctx
->opcode
));
4600 gen_addr_reg_index(ctx
, t0
);
4601 /* NIP cannot be restored if the memory exception comes from an helper */
4602 gen_update_nip(ctx
, ctx
->nip
- 4);
4603 gen_helper_lscbx(t0
, cpu_env
, t0
, t1
, t2
, t3
);
4604 tcg_temp_free_i32(t1
);
4605 tcg_temp_free_i32(t2
);
4606 tcg_temp_free_i32(t3
);
4607 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~0x7F);
4608 tcg_gen_or_tl(cpu_xer
, cpu_xer
, t0
);
4609 if (unlikely(Rc(ctx
->opcode
) != 0))
4610 gen_set_Rc0(ctx
, t0
);
4614 /* maskg - maskg. */
4615 static void gen_maskg(DisasContext
*ctx
)
4617 TCGLabel
*l1
= gen_new_label();
4618 TCGv t0
= tcg_temp_new();
4619 TCGv t1
= tcg_temp_new();
4620 TCGv t2
= tcg_temp_new();
4621 TCGv t3
= tcg_temp_new();
4622 tcg_gen_movi_tl(t3
, 0xFFFFFFFF);
4623 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4624 tcg_gen_andi_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 0x1F);
4625 tcg_gen_addi_tl(t2
, t0
, 1);
4626 tcg_gen_shr_tl(t2
, t3
, t2
);
4627 tcg_gen_shr_tl(t3
, t3
, t1
);
4628 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], t2
, t3
);
4629 tcg_gen_brcond_tl(TCG_COND_GE
, t0
, t1
, l1
);
4630 tcg_gen_neg_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4636 if (unlikely(Rc(ctx
->opcode
) != 0))
4637 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4640 /* maskir - maskir. */
4641 static void gen_maskir(DisasContext
*ctx
)
4643 TCGv t0
= tcg_temp_new();
4644 TCGv t1
= tcg_temp_new();
4645 tcg_gen_and_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4646 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4647 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4650 if (unlikely(Rc(ctx
->opcode
) != 0))
4651 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4655 static void gen_mul(DisasContext
*ctx
)
4657 TCGv_i64 t0
= tcg_temp_new_i64();
4658 TCGv_i64 t1
= tcg_temp_new_i64();
4659 TCGv t2
= tcg_temp_new();
4660 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
4661 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
4662 tcg_gen_mul_i64(t0
, t0
, t1
);
4663 tcg_gen_trunc_i64_tl(t2
, t0
);
4664 gen_store_spr(SPR_MQ
, t2
);
4665 tcg_gen_shri_i64(t1
, t0
, 32);
4666 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
4667 tcg_temp_free_i64(t0
);
4668 tcg_temp_free_i64(t1
);
4670 if (unlikely(Rc(ctx
->opcode
) != 0))
4671 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4675 static void gen_mulo(DisasContext
*ctx
)
4677 TCGLabel
*l1
= gen_new_label();
4678 TCGv_i64 t0
= tcg_temp_new_i64();
4679 TCGv_i64 t1
= tcg_temp_new_i64();
4680 TCGv t2
= tcg_temp_new();
4681 /* Start with XER OV disabled, the most likely case */
4682 tcg_gen_movi_tl(cpu_ov
, 0);
4683 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
4684 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
4685 tcg_gen_mul_i64(t0
, t0
, t1
);
4686 tcg_gen_trunc_i64_tl(t2
, t0
);
4687 gen_store_spr(SPR_MQ
, t2
);
4688 tcg_gen_shri_i64(t1
, t0
, 32);
4689 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
4690 tcg_gen_ext32s_i64(t1
, t0
);
4691 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, t1
, l1
);
4692 tcg_gen_movi_tl(cpu_ov
, 1);
4693 tcg_gen_movi_tl(cpu_so
, 1);
4695 tcg_temp_free_i64(t0
);
4696 tcg_temp_free_i64(t1
);
4698 if (unlikely(Rc(ctx
->opcode
) != 0))
4699 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4703 static void gen_nabs(DisasContext
*ctx
)
4705 TCGLabel
*l1
= gen_new_label();
4706 TCGLabel
*l2
= gen_new_label();
4707 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4708 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4711 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4713 if (unlikely(Rc(ctx
->opcode
) != 0))
4714 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4717 /* nabso - nabso. */
4718 static void gen_nabso(DisasContext
*ctx
)
4720 TCGLabel
*l1
= gen_new_label();
4721 TCGLabel
*l2
= gen_new_label();
4722 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4723 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4726 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4728 /* nabs never overflows */
4729 tcg_gen_movi_tl(cpu_ov
, 0);
4730 if (unlikely(Rc(ctx
->opcode
) != 0))
4731 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4735 static void gen_rlmi(DisasContext
*ctx
)
4737 uint32_t mb
= MB(ctx
->opcode
);
4738 uint32_t me
= ME(ctx
->opcode
);
4739 TCGv t0
= tcg_temp_new();
4740 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4741 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4742 tcg_gen_andi_tl(t0
, t0
, MASK(mb
, me
));
4743 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~MASK(mb
, me
));
4744 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], t0
);
4746 if (unlikely(Rc(ctx
->opcode
) != 0))
4747 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4751 static void gen_rrib(DisasContext
*ctx
)
4753 TCGv t0
= tcg_temp_new();
4754 TCGv t1
= tcg_temp_new();
4755 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4756 tcg_gen_movi_tl(t1
, 0x80000000);
4757 tcg_gen_shr_tl(t1
, t1
, t0
);
4758 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4759 tcg_gen_and_tl(t0
, t0
, t1
);
4760 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], t1
);
4761 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4764 if (unlikely(Rc(ctx
->opcode
) != 0))
4765 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4769 static void gen_sle(DisasContext
*ctx
)
4771 TCGv t0
= tcg_temp_new();
4772 TCGv t1
= tcg_temp_new();
4773 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4774 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4775 tcg_gen_subfi_tl(t1
, 32, t1
);
4776 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4777 tcg_gen_or_tl(t1
, t0
, t1
);
4778 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4779 gen_store_spr(SPR_MQ
, t1
);
4782 if (unlikely(Rc(ctx
->opcode
) != 0))
4783 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4787 static void gen_sleq(DisasContext
*ctx
)
4789 TCGv t0
= tcg_temp_new();
4790 TCGv t1
= tcg_temp_new();
4791 TCGv t2
= tcg_temp_new();
4792 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4793 tcg_gen_movi_tl(t2
, 0xFFFFFFFF);
4794 tcg_gen_shl_tl(t2
, t2
, t0
);
4795 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4796 gen_load_spr(t1
, SPR_MQ
);
4797 gen_store_spr(SPR_MQ
, t0
);
4798 tcg_gen_and_tl(t0
, t0
, t2
);
4799 tcg_gen_andc_tl(t1
, t1
, t2
);
4800 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4804 if (unlikely(Rc(ctx
->opcode
) != 0))
4805 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4809 static void gen_sliq(DisasContext
*ctx
)
4811 int sh
= SH(ctx
->opcode
);
4812 TCGv t0
= tcg_temp_new();
4813 TCGv t1
= tcg_temp_new();
4814 tcg_gen_shli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
4815 tcg_gen_shri_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
4816 tcg_gen_or_tl(t1
, t0
, t1
);
4817 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4818 gen_store_spr(SPR_MQ
, t1
);
4821 if (unlikely(Rc(ctx
->opcode
) != 0))
4822 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4825 /* slliq - slliq. */
4826 static void gen_slliq(DisasContext
*ctx
)
4828 int sh
= SH(ctx
->opcode
);
4829 TCGv t0
= tcg_temp_new();
4830 TCGv t1
= tcg_temp_new();
4831 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
4832 gen_load_spr(t1
, SPR_MQ
);
4833 gen_store_spr(SPR_MQ
, t0
);
4834 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
<< sh
));
4835 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
<< sh
));
4836 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4839 if (unlikely(Rc(ctx
->opcode
) != 0))
4840 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4844 static void gen_sllq(DisasContext
*ctx
)
4846 TCGLabel
*l1
= gen_new_label();
4847 TCGLabel
*l2
= gen_new_label();
4848 TCGv t0
= tcg_temp_local_new();
4849 TCGv t1
= tcg_temp_local_new();
4850 TCGv t2
= tcg_temp_local_new();
4851 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4852 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
4853 tcg_gen_shl_tl(t1
, t1
, t2
);
4854 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
4855 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
4856 gen_load_spr(t0
, SPR_MQ
);
4857 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4860 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
4861 gen_load_spr(t2
, SPR_MQ
);
4862 tcg_gen_andc_tl(t1
, t2
, t1
);
4863 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4868 if (unlikely(Rc(ctx
->opcode
) != 0))
4869 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4873 static void gen_slq(DisasContext
*ctx
)
4875 TCGLabel
*l1
= gen_new_label();
4876 TCGv t0
= tcg_temp_new();
4877 TCGv t1
= tcg_temp_new();
4878 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4879 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4880 tcg_gen_subfi_tl(t1
, 32, t1
);
4881 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4882 tcg_gen_or_tl(t1
, t0
, t1
);
4883 gen_store_spr(SPR_MQ
, t1
);
4884 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
4885 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4886 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
4887 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
4891 if (unlikely(Rc(ctx
->opcode
) != 0))
4892 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4895 /* sraiq - sraiq. */
4896 static void gen_sraiq(DisasContext
*ctx
)
4898 int sh
= SH(ctx
->opcode
);
4899 TCGLabel
*l1
= gen_new_label();
4900 TCGv t0
= tcg_temp_new();
4901 TCGv t1
= tcg_temp_new();
4902 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
4903 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
4904 tcg_gen_or_tl(t0
, t0
, t1
);
4905 gen_store_spr(SPR_MQ
, t0
);
4906 tcg_gen_movi_tl(cpu_ca
, 0);
4907 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
4908 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rS(ctx
->opcode
)], 0, l1
);
4909 tcg_gen_movi_tl(cpu_ca
, 1);
4911 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
4914 if (unlikely(Rc(ctx
->opcode
) != 0))
4915 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4919 static void gen_sraq(DisasContext
*ctx
)
4921 TCGLabel
*l1
= gen_new_label();
4922 TCGLabel
*l2
= gen_new_label();
4923 TCGv t0
= tcg_temp_new();
4924 TCGv t1
= tcg_temp_local_new();
4925 TCGv t2
= tcg_temp_local_new();
4926 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4927 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
4928 tcg_gen_sar_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
4929 tcg_gen_subfi_tl(t2
, 32, t2
);
4930 tcg_gen_shl_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
4931 tcg_gen_or_tl(t0
, t0
, t2
);
4932 gen_store_spr(SPR_MQ
, t0
);
4933 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
4934 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l1
);
4935 tcg_gen_mov_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)]);
4936 tcg_gen_sari_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 31);
4939 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t1
);
4940 tcg_gen_movi_tl(cpu_ca
, 0);
4941 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
4942 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l2
);
4943 tcg_gen_movi_tl(cpu_ca
, 1);
4947 if (unlikely(Rc(ctx
->opcode
) != 0))
4948 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4952 static void gen_sre(DisasContext
*ctx
)
4954 TCGv t0
= tcg_temp_new();
4955 TCGv t1
= tcg_temp_new();
4956 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4957 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4958 tcg_gen_subfi_tl(t1
, 32, t1
);
4959 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4960 tcg_gen_or_tl(t1
, t0
, t1
);
4961 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4962 gen_store_spr(SPR_MQ
, t1
);
4965 if (unlikely(Rc(ctx
->opcode
) != 0))
4966 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4970 static void gen_srea(DisasContext
*ctx
)
4972 TCGv t0
= tcg_temp_new();
4973 TCGv t1
= tcg_temp_new();
4974 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4975 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4976 gen_store_spr(SPR_MQ
, t0
);
4977 tcg_gen_sar_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], t1
);
4980 if (unlikely(Rc(ctx
->opcode
) != 0))
4981 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4985 static void gen_sreq(DisasContext
*ctx
)
4987 TCGv t0
= tcg_temp_new();
4988 TCGv t1
= tcg_temp_new();
4989 TCGv t2
= tcg_temp_new();
4990 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4991 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
4992 tcg_gen_shr_tl(t1
, t1
, t0
);
4993 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4994 gen_load_spr(t2
, SPR_MQ
);
4995 gen_store_spr(SPR_MQ
, t0
);
4996 tcg_gen_and_tl(t0
, t0
, t1
);
4997 tcg_gen_andc_tl(t2
, t2
, t1
);
4998 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5002 if (unlikely(Rc(ctx
->opcode
) != 0))
5003 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5007 static void gen_sriq(DisasContext
*ctx
)
5009 int sh
= SH(ctx
->opcode
);
5010 TCGv t0
= tcg_temp_new();
5011 TCGv t1
= tcg_temp_new();
5012 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5013 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5014 tcg_gen_or_tl(t1
, t0
, t1
);
5015 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5016 gen_store_spr(SPR_MQ
, t1
);
5019 if (unlikely(Rc(ctx
->opcode
) != 0))
5020 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5024 static void gen_srliq(DisasContext
*ctx
)
5026 int sh
= SH(ctx
->opcode
);
5027 TCGv t0
= tcg_temp_new();
5028 TCGv t1
= tcg_temp_new();
5029 tcg_gen_rotri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5030 gen_load_spr(t1
, SPR_MQ
);
5031 gen_store_spr(SPR_MQ
, t0
);
5032 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
>> sh
));
5033 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
>> sh
));
5034 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5037 if (unlikely(Rc(ctx
->opcode
) != 0))
5038 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5042 static void gen_srlq(DisasContext
*ctx
)
5044 TCGLabel
*l1
= gen_new_label();
5045 TCGLabel
*l2
= gen_new_label();
5046 TCGv t0
= tcg_temp_local_new();
5047 TCGv t1
= tcg_temp_local_new();
5048 TCGv t2
= tcg_temp_local_new();
5049 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5050 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5051 tcg_gen_shr_tl(t2
, t1
, t2
);
5052 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5053 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5054 gen_load_spr(t0
, SPR_MQ
);
5055 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5058 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5059 tcg_gen_and_tl(t0
, t0
, t2
);
5060 gen_load_spr(t1
, SPR_MQ
);
5061 tcg_gen_andc_tl(t1
, t1
, t2
);
5062 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5067 if (unlikely(Rc(ctx
->opcode
) != 0))
5068 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5072 static void gen_srq(DisasContext
*ctx
)
5074 TCGLabel
*l1
= gen_new_label();
5075 TCGv t0
= tcg_temp_new();
5076 TCGv t1
= tcg_temp_new();
5077 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5078 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5079 tcg_gen_subfi_tl(t1
, 32, t1
);
5080 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5081 tcg_gen_or_tl(t1
, t0
, t1
);
5082 gen_store_spr(SPR_MQ
, t1
);
5083 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5084 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5085 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5086 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5090 if (unlikely(Rc(ctx
->opcode
) != 0))
5091 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5094 /* PowerPC 602 specific instructions */
5097 static void gen_dsa(DisasContext
*ctx
)
5100 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5104 static void gen_esa(DisasContext
*ctx
)
5107 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5111 static void gen_mfrom(DisasContext
*ctx
)
5113 #if defined(CONFIG_USER_ONLY)
5117 gen_helper_602_mfrom(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5118 #endif /* defined(CONFIG_USER_ONLY) */
5121 /* 602 - 603 - G2 TLB management */
5124 static void gen_tlbld_6xx(DisasContext
*ctx
)
5126 #if defined(CONFIG_USER_ONLY)
5130 gen_helper_6xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5131 #endif /* defined(CONFIG_USER_ONLY) */
5135 static void gen_tlbli_6xx(DisasContext
*ctx
)
5137 #if defined(CONFIG_USER_ONLY)
5141 gen_helper_6xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5142 #endif /* defined(CONFIG_USER_ONLY) */
5145 /* 74xx TLB management */
5148 static void gen_tlbld_74xx(DisasContext
*ctx
)
5150 #if defined(CONFIG_USER_ONLY)
5154 gen_helper_74xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5155 #endif /* defined(CONFIG_USER_ONLY) */
5159 static void gen_tlbli_74xx(DisasContext
*ctx
)
5161 #if defined(CONFIG_USER_ONLY)
5165 gen_helper_74xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5166 #endif /* defined(CONFIG_USER_ONLY) */
5169 /* POWER instructions not in PowerPC 601 */
5172 static void gen_clf(DisasContext
*ctx
)
5174 /* Cache line flush: implemented as no-op */
5178 static void gen_cli(DisasContext
*ctx
)
5180 #if defined(CONFIG_USER_ONLY)
5183 /* Cache line invalidate: privileged and treated as no-op */
5185 #endif /* defined(CONFIG_USER_ONLY) */
5189 static void gen_dclst(DisasContext
*ctx
)
5191 /* Data cache line store: treated as no-op */
5194 static void gen_mfsri(DisasContext
*ctx
)
5196 #if defined(CONFIG_USER_ONLY)
5199 int ra
= rA(ctx
->opcode
);
5200 int rd
= rD(ctx
->opcode
);
5204 t0
= tcg_temp_new();
5205 gen_addr_reg_index(ctx
, t0
);
5206 tcg_gen_shri_tl(t0
, t0
, 28);
5207 tcg_gen_andi_tl(t0
, t0
, 0xF);
5208 gen_helper_load_sr(cpu_gpr
[rd
], cpu_env
, t0
);
5210 if (ra
!= 0 && ra
!= rd
)
5211 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rd
]);
5212 #endif /* defined(CONFIG_USER_ONLY) */
5215 static void gen_rac(DisasContext
*ctx
)
5217 #if defined(CONFIG_USER_ONLY)
5223 t0
= tcg_temp_new();
5224 gen_addr_reg_index(ctx
, t0
);
5225 gen_helper_rac(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5227 #endif /* defined(CONFIG_USER_ONLY) */
5230 static void gen_rfsvc(DisasContext
*ctx
)
5232 #if defined(CONFIG_USER_ONLY)
5237 gen_helper_rfsvc(cpu_env
);
5238 gen_sync_exception(ctx
);
5239 #endif /* defined(CONFIG_USER_ONLY) */
5242 #include "translate/fp-impl.c"
5244 /* svc is not implemented for now */
5246 /* BookE specific instructions */
5248 /* XXX: not implemented on 440 ? */
5249 static void gen_mfapidi(DisasContext
*ctx
)
5252 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5255 /* XXX: not implemented on 440 ? */
5256 static void gen_tlbiva(DisasContext
*ctx
)
5258 #if defined(CONFIG_USER_ONLY)
5264 t0
= tcg_temp_new();
5265 gen_addr_reg_index(ctx
, t0
);
5266 gen_helper_tlbiva(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5268 #endif /* defined(CONFIG_USER_ONLY) */
5271 /* All 405 MAC instructions are translated here */
5272 static inline void gen_405_mulladd_insn(DisasContext
*ctx
, int opc2
, int opc3
,
5273 int ra
, int rb
, int rt
, int Rc
)
5277 t0
= tcg_temp_local_new();
5278 t1
= tcg_temp_local_new();
5280 switch (opc3
& 0x0D) {
5282 /* macchw - macchw. - macchwo - macchwo. */
5283 /* macchws - macchws. - macchwso - macchwso. */
5284 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5285 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5286 /* mulchw - mulchw. */
5287 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5288 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5289 tcg_gen_ext16s_tl(t1
, t1
);
5292 /* macchwu - macchwu. - macchwuo - macchwuo. */
5293 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5294 /* mulchwu - mulchwu. */
5295 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5296 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5297 tcg_gen_ext16u_tl(t1
, t1
);
5300 /* machhw - machhw. - machhwo - machhwo. */
5301 /* machhws - machhws. - machhwso - machhwso. */
5302 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5303 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5304 /* mulhhw - mulhhw. */
5305 tcg_gen_sari_tl(t0
, cpu_gpr
[ra
], 16);
5306 tcg_gen_ext16s_tl(t0
, t0
);
5307 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5308 tcg_gen_ext16s_tl(t1
, t1
);
5311 /* machhwu - machhwu. - machhwuo - machhwuo. */
5312 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5313 /* mulhhwu - mulhhwu. */
5314 tcg_gen_shri_tl(t0
, cpu_gpr
[ra
], 16);
5315 tcg_gen_ext16u_tl(t0
, t0
);
5316 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5317 tcg_gen_ext16u_tl(t1
, t1
);
5320 /* maclhw - maclhw. - maclhwo - maclhwo. */
5321 /* maclhws - maclhws. - maclhwso - maclhwso. */
5322 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5323 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5324 /* mullhw - mullhw. */
5325 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5326 tcg_gen_ext16s_tl(t1
, cpu_gpr
[rb
]);
5329 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5330 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5331 /* mullhwu - mullhwu. */
5332 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5333 tcg_gen_ext16u_tl(t1
, cpu_gpr
[rb
]);
5337 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5338 tcg_gen_mul_tl(t1
, t0
, t1
);
5340 /* nmultiply-and-accumulate (0x0E) */
5341 tcg_gen_sub_tl(t0
, cpu_gpr
[rt
], t1
);
5343 /* multiply-and-accumulate (0x0C) */
5344 tcg_gen_add_tl(t0
, cpu_gpr
[rt
], t1
);
5348 /* Check overflow and/or saturate */
5349 TCGLabel
*l1
= gen_new_label();
5352 /* Start with XER OV disabled, the most likely case */
5353 tcg_gen_movi_tl(cpu_ov
, 0);
5357 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t1
);
5358 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
5359 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t0
);
5360 tcg_gen_brcondi_tl(TCG_COND_LT
, t1
, 0, l1
);
5363 tcg_gen_sari_tl(t0
, cpu_gpr
[rt
], 31);
5364 tcg_gen_xori_tl(t0
, t0
, 0x7fffffff);
5368 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
5371 tcg_gen_movi_tl(t0
, UINT32_MAX
);
5375 /* Check overflow */
5376 tcg_gen_movi_tl(cpu_ov
, 1);
5377 tcg_gen_movi_tl(cpu_so
, 1);
5380 tcg_gen_mov_tl(cpu_gpr
[rt
], t0
);
5383 tcg_gen_mul_tl(cpu_gpr
[rt
], t0
, t1
);
5387 if (unlikely(Rc
) != 0) {
5389 gen_set_Rc0(ctx
, cpu_gpr
[rt
]);
5393 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5394 static void glue(gen_, name)(DisasContext *ctx) \
5396 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5397 rD(ctx->opcode), Rc(ctx->opcode)); \
5400 /* macchw - macchw. */
5401 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05);
5402 /* macchwo - macchwo. */
5403 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15);
5404 /* macchws - macchws. */
5405 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07);
5406 /* macchwso - macchwso. */
5407 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17);
5408 /* macchwsu - macchwsu. */
5409 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06);
5410 /* macchwsuo - macchwsuo. */
5411 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16);
5412 /* macchwu - macchwu. */
5413 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04);
5414 /* macchwuo - macchwuo. */
5415 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14);
5416 /* machhw - machhw. */
5417 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01);
5418 /* machhwo - machhwo. */
5419 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11);
5420 /* machhws - machhws. */
5421 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03);
5422 /* machhwso - machhwso. */
5423 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13);
5424 /* machhwsu - machhwsu. */
5425 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02);
5426 /* machhwsuo - machhwsuo. */
5427 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12);
5428 /* machhwu - machhwu. */
5429 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00);
5430 /* machhwuo - machhwuo. */
5431 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10);
5432 /* maclhw - maclhw. */
5433 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D);
5434 /* maclhwo - maclhwo. */
5435 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D);
5436 /* maclhws - maclhws. */
5437 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F);
5438 /* maclhwso - maclhwso. */
5439 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F);
5440 /* maclhwu - maclhwu. */
5441 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C);
5442 /* maclhwuo - maclhwuo. */
5443 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C);
5444 /* maclhwsu - maclhwsu. */
5445 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E);
5446 /* maclhwsuo - maclhwsuo. */
5447 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E);
5448 /* nmacchw - nmacchw. */
5449 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05);
5450 /* nmacchwo - nmacchwo. */
5451 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15);
5452 /* nmacchws - nmacchws. */
5453 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07);
5454 /* nmacchwso - nmacchwso. */
5455 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17);
5456 /* nmachhw - nmachhw. */
5457 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01);
5458 /* nmachhwo - nmachhwo. */
5459 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11);
5460 /* nmachhws - nmachhws. */
5461 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03);
5462 /* nmachhwso - nmachhwso. */
5463 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13);
5464 /* nmaclhw - nmaclhw. */
5465 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D);
5466 /* nmaclhwo - nmaclhwo. */
5467 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D);
5468 /* nmaclhws - nmaclhws. */
5469 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F);
5470 /* nmaclhwso - nmaclhwso. */
5471 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F);
5473 /* mulchw - mulchw. */
5474 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05);
5475 /* mulchwu - mulchwu. */
5476 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04);
5477 /* mulhhw - mulhhw. */
5478 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01);
5479 /* mulhhwu - mulhhwu. */
5480 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00);
5481 /* mullhw - mullhw. */
5482 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D);
5483 /* mullhwu - mullhwu. */
5484 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C);
5487 static void gen_mfdcr(DisasContext
*ctx
)
5489 #if defined(CONFIG_USER_ONLY)
5495 /* NIP cannot be restored if the memory exception comes from an helper */
5496 gen_update_nip(ctx
, ctx
->nip
- 4);
5497 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
5498 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, dcrn
);
5499 tcg_temp_free(dcrn
);
5500 #endif /* defined(CONFIG_USER_ONLY) */
5504 static void gen_mtdcr(DisasContext
*ctx
)
5506 #if defined(CONFIG_USER_ONLY)
5512 /* NIP cannot be restored if the memory exception comes from an helper */
5513 gen_update_nip(ctx
, ctx
->nip
- 4);
5514 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
5515 gen_helper_store_dcr(cpu_env
, dcrn
, cpu_gpr
[rS(ctx
->opcode
)]);
5516 tcg_temp_free(dcrn
);
5517 #endif /* defined(CONFIG_USER_ONLY) */
5521 /* XXX: not implemented on 440 ? */
5522 static void gen_mfdcrx(DisasContext
*ctx
)
5524 #if defined(CONFIG_USER_ONLY)
5528 /* NIP cannot be restored if the memory exception comes from an helper */
5529 gen_update_nip(ctx
, ctx
->nip
- 4);
5530 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5531 cpu_gpr
[rA(ctx
->opcode
)]);
5532 /* Note: Rc update flag set leads to undefined state of Rc0 */
5533 #endif /* defined(CONFIG_USER_ONLY) */
5537 /* XXX: not implemented on 440 ? */
5538 static void gen_mtdcrx(DisasContext
*ctx
)
5540 #if defined(CONFIG_USER_ONLY)
5544 /* NIP cannot be restored if the memory exception comes from an helper */
5545 gen_update_nip(ctx
, ctx
->nip
- 4);
5546 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5547 cpu_gpr
[rS(ctx
->opcode
)]);
5548 /* Note: Rc update flag set leads to undefined state of Rc0 */
5549 #endif /* defined(CONFIG_USER_ONLY) */
5552 /* mfdcrux (PPC 460) : user-mode access to DCR */
5553 static void gen_mfdcrux(DisasContext
*ctx
)
5555 /* NIP cannot be restored if the memory exception comes from an helper */
5556 gen_update_nip(ctx
, ctx
->nip
- 4);
5557 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5558 cpu_gpr
[rA(ctx
->opcode
)]);
5559 /* Note: Rc update flag set leads to undefined state of Rc0 */
5562 /* mtdcrux (PPC 460) : user-mode access to DCR */
5563 static void gen_mtdcrux(DisasContext
*ctx
)
5565 /* NIP cannot be restored if the memory exception comes from an helper */
5566 gen_update_nip(ctx
, ctx
->nip
- 4);
5567 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5568 cpu_gpr
[rS(ctx
->opcode
)]);
5569 /* Note: Rc update flag set leads to undefined state of Rc0 */
5573 static void gen_dccci(DisasContext
*ctx
)
5576 /* interpreted as no-op */
5580 static void gen_dcread(DisasContext
*ctx
)
5582 #if defined(CONFIG_USER_ONLY)
5588 gen_set_access_type(ctx
, ACCESS_CACHE
);
5589 EA
= tcg_temp_new();
5590 gen_addr_reg_index(ctx
, EA
);
5591 val
= tcg_temp_new();
5592 gen_qemu_ld32u(ctx
, val
, EA
);
5594 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], EA
);
5596 #endif /* defined(CONFIG_USER_ONLY) */
5600 static void gen_icbt_40x(DisasContext
*ctx
)
5602 /* interpreted as no-op */
5603 /* XXX: specification say this is treated as a load by the MMU
5604 * but does not generate any exception
5609 static void gen_iccci(DisasContext
*ctx
)
5612 /* interpreted as no-op */
5616 static void gen_icread(DisasContext
*ctx
)
5619 /* interpreted as no-op */
5622 /* rfci (supervisor only) */
5623 static void gen_rfci_40x(DisasContext
*ctx
)
5625 #if defined(CONFIG_USER_ONLY)
5629 /* Restore CPU state */
5630 gen_helper_40x_rfci(cpu_env
);
5631 gen_sync_exception(ctx
);
5632 #endif /* defined(CONFIG_USER_ONLY) */
5635 static void gen_rfci(DisasContext
*ctx
)
5637 #if defined(CONFIG_USER_ONLY)
5641 /* Restore CPU state */
5642 gen_helper_rfci(cpu_env
);
5643 gen_sync_exception(ctx
);
5644 #endif /* defined(CONFIG_USER_ONLY) */
5647 /* BookE specific */
5649 /* XXX: not implemented on 440 ? */
5650 static void gen_rfdi(DisasContext
*ctx
)
5652 #if defined(CONFIG_USER_ONLY)
5656 /* Restore CPU state */
5657 gen_helper_rfdi(cpu_env
);
5658 gen_sync_exception(ctx
);
5659 #endif /* defined(CONFIG_USER_ONLY) */
5662 /* XXX: not implemented on 440 ? */
5663 static void gen_rfmci(DisasContext
*ctx
)
5665 #if defined(CONFIG_USER_ONLY)
5669 /* Restore CPU state */
5670 gen_helper_rfmci(cpu_env
);
5671 gen_sync_exception(ctx
);
5672 #endif /* defined(CONFIG_USER_ONLY) */
5675 /* TLB management - PowerPC 405 implementation */
5678 static void gen_tlbre_40x(DisasContext
*ctx
)
5680 #if defined(CONFIG_USER_ONLY)
5684 switch (rB(ctx
->opcode
)) {
5686 gen_helper_4xx_tlbre_hi(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5687 cpu_gpr
[rA(ctx
->opcode
)]);
5690 gen_helper_4xx_tlbre_lo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5691 cpu_gpr
[rA(ctx
->opcode
)]);
5694 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5697 #endif /* defined(CONFIG_USER_ONLY) */
5700 /* tlbsx - tlbsx. */
5701 static void gen_tlbsx_40x(DisasContext
*ctx
)
5703 #if defined(CONFIG_USER_ONLY)
5709 t0
= tcg_temp_new();
5710 gen_addr_reg_index(ctx
, t0
);
5711 gen_helper_4xx_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5713 if (Rc(ctx
->opcode
)) {
5714 TCGLabel
*l1
= gen_new_label();
5715 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
5716 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
5717 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
5720 #endif /* defined(CONFIG_USER_ONLY) */
5724 static void gen_tlbwe_40x(DisasContext
*ctx
)
5726 #if defined(CONFIG_USER_ONLY)
5731 switch (rB(ctx
->opcode
)) {
5733 gen_helper_4xx_tlbwe_hi(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5734 cpu_gpr
[rS(ctx
->opcode
)]);
5737 gen_helper_4xx_tlbwe_lo(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5738 cpu_gpr
[rS(ctx
->opcode
)]);
5741 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5744 #endif /* defined(CONFIG_USER_ONLY) */
5747 /* TLB management - PowerPC 440 implementation */
5750 static void gen_tlbre_440(DisasContext
*ctx
)
5752 #if defined(CONFIG_USER_ONLY)
5757 switch (rB(ctx
->opcode
)) {
5762 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
5763 gen_helper_440_tlbre(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5764 t0
, cpu_gpr
[rA(ctx
->opcode
)]);
5765 tcg_temp_free_i32(t0
);
5769 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5772 #endif /* defined(CONFIG_USER_ONLY) */
5775 /* tlbsx - tlbsx. */
5776 static void gen_tlbsx_440(DisasContext
*ctx
)
5778 #if defined(CONFIG_USER_ONLY)
5784 t0
= tcg_temp_new();
5785 gen_addr_reg_index(ctx
, t0
);
5786 gen_helper_440_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5788 if (Rc(ctx
->opcode
)) {
5789 TCGLabel
*l1
= gen_new_label();
5790 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
5791 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
5792 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
5795 #endif /* defined(CONFIG_USER_ONLY) */
5799 static void gen_tlbwe_440(DisasContext
*ctx
)
5801 #if defined(CONFIG_USER_ONLY)
5805 switch (rB(ctx
->opcode
)) {
5810 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
5811 gen_helper_440_tlbwe(cpu_env
, t0
, cpu_gpr
[rA(ctx
->opcode
)],
5812 cpu_gpr
[rS(ctx
->opcode
)]);
5813 tcg_temp_free_i32(t0
);
5817 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5820 #endif /* defined(CONFIG_USER_ONLY) */
5823 /* TLB management - PowerPC BookE 2.06 implementation */
5826 static void gen_tlbre_booke206(DisasContext
*ctx
)
5828 #if defined(CONFIG_USER_ONLY)
5832 gen_helper_booke206_tlbre(cpu_env
);
5833 #endif /* defined(CONFIG_USER_ONLY) */
5836 /* tlbsx - tlbsx. */
5837 static void gen_tlbsx_booke206(DisasContext
*ctx
)
5839 #if defined(CONFIG_USER_ONLY)
5845 if (rA(ctx
->opcode
)) {
5846 t0
= tcg_temp_new();
5847 tcg_gen_mov_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)]);
5849 t0
= tcg_const_tl(0);
5852 tcg_gen_add_tl(t0
, t0
, cpu_gpr
[rB(ctx
->opcode
)]);
5853 gen_helper_booke206_tlbsx(cpu_env
, t0
);
5855 #endif /* defined(CONFIG_USER_ONLY) */
5859 static void gen_tlbwe_booke206(DisasContext
*ctx
)
5861 #if defined(CONFIG_USER_ONLY)
5865 gen_update_nip(ctx
, ctx
->nip
- 4);
5866 gen_helper_booke206_tlbwe(cpu_env
);
5867 #endif /* defined(CONFIG_USER_ONLY) */
5870 static void gen_tlbivax_booke206(DisasContext
*ctx
)
5872 #if defined(CONFIG_USER_ONLY)
5878 t0
= tcg_temp_new();
5879 gen_addr_reg_index(ctx
, t0
);
5880 gen_helper_booke206_tlbivax(cpu_env
, t0
);
5882 #endif /* defined(CONFIG_USER_ONLY) */
5885 static void gen_tlbilx_booke206(DisasContext
*ctx
)
5887 #if defined(CONFIG_USER_ONLY)
5893 t0
= tcg_temp_new();
5894 gen_addr_reg_index(ctx
, t0
);
5896 switch((ctx
->opcode
>> 21) & 0x3) {
5898 gen_helper_booke206_tlbilx0(cpu_env
, t0
);
5901 gen_helper_booke206_tlbilx1(cpu_env
, t0
);
5904 gen_helper_booke206_tlbilx3(cpu_env
, t0
);
5907 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5912 #endif /* defined(CONFIG_USER_ONLY) */
5917 static void gen_wrtee(DisasContext
*ctx
)
5919 #if defined(CONFIG_USER_ONLY)
5925 t0
= tcg_temp_new();
5926 tcg_gen_andi_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)], (1 << MSR_EE
));
5927 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
5928 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
5930 /* Stop translation to have a chance to raise an exception
5931 * if we just set msr_ee to 1
5933 gen_stop_exception(ctx
);
5934 #endif /* defined(CONFIG_USER_ONLY) */
5938 static void gen_wrteei(DisasContext
*ctx
)
5940 #if defined(CONFIG_USER_ONLY)
5944 if (ctx
->opcode
& 0x00008000) {
5945 tcg_gen_ori_tl(cpu_msr
, cpu_msr
, (1 << MSR_EE
));
5946 /* Stop translation to have a chance to raise an exception */
5947 gen_stop_exception(ctx
);
5949 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
5951 #endif /* defined(CONFIG_USER_ONLY) */
5954 /* PowerPC 440 specific instructions */
5957 static void gen_dlmzb(DisasContext
*ctx
)
5959 TCGv_i32 t0
= tcg_const_i32(Rc(ctx
->opcode
));
5960 gen_helper_dlmzb(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
5961 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], t0
);
5962 tcg_temp_free_i32(t0
);
5965 /* mbar replaces eieio on 440 */
5966 static void gen_mbar(DisasContext
*ctx
)
5968 /* interpreted as no-op */
5971 /* msync replaces sync on 440 */
5972 static void gen_msync_4xx(DisasContext
*ctx
)
5974 /* interpreted as no-op */
5978 static void gen_icbt_440(DisasContext
*ctx
)
5980 /* interpreted as no-op */
5981 /* XXX: specification say this is treated as a load by the MMU
5982 * but does not generate any exception
5986 /* Embedded.Processor Control */
5988 static void gen_msgclr(DisasContext
*ctx
)
5990 #if defined(CONFIG_USER_ONLY)
5994 gen_helper_msgclr(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5995 #endif /* defined(CONFIG_USER_ONLY) */
5998 static void gen_msgsnd(DisasContext
*ctx
)
6000 #if defined(CONFIG_USER_ONLY)
6004 gen_helper_msgsnd(cpu_gpr
[rB(ctx
->opcode
)]);
6005 #endif /* defined(CONFIG_USER_ONLY) */
6008 /*** Altivec vector extension ***/
6009 /* Altivec registers moves */
6011 static inline TCGv_ptr
gen_avr_ptr(int reg
)
6013 TCGv_ptr r
= tcg_temp_new_ptr();
6014 tcg_gen_addi_ptr(r
, cpu_env
, offsetof(CPUPPCState
, avr
[reg
]));
6018 #define GEN_VR_LDX(name, opc2, opc3) \
6019 static void glue(gen_, name)(DisasContext *ctx) \
6022 if (unlikely(!ctx->altivec_enabled)) { \
6023 gen_exception(ctx, POWERPC_EXCP_VPU); \
6026 gen_set_access_type(ctx, ACCESS_INT); \
6027 EA = tcg_temp_new(); \
6028 gen_addr_reg_index(ctx, EA); \
6029 tcg_gen_andi_tl(EA, EA, ~0xf); \
6030 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6031 64-bit byteswap already. */ \
6032 if (ctx->le_mode) { \
6033 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6034 tcg_gen_addi_tl(EA, EA, 8); \
6035 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6037 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6038 tcg_gen_addi_tl(EA, EA, 8); \
6039 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6041 tcg_temp_free(EA); \
6044 #define GEN_VR_STX(name, opc2, opc3) \
6045 static void gen_st##name(DisasContext *ctx) \
6048 if (unlikely(!ctx->altivec_enabled)) { \
6049 gen_exception(ctx, POWERPC_EXCP_VPU); \
6052 gen_set_access_type(ctx, ACCESS_INT); \
6053 EA = tcg_temp_new(); \
6054 gen_addr_reg_index(ctx, EA); \
6055 tcg_gen_andi_tl(EA, EA, ~0xf); \
6056 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6057 64-bit byteswap already. */ \
6058 if (ctx->le_mode) { \
6059 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6060 tcg_gen_addi_tl(EA, EA, 8); \
6061 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6063 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6064 tcg_gen_addi_tl(EA, EA, 8); \
6065 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6067 tcg_temp_free(EA); \
6070 #define GEN_VR_LVE(name, opc2, opc3, size) \
6071 static void gen_lve##name(DisasContext *ctx) \
6075 if (unlikely(!ctx->altivec_enabled)) { \
6076 gen_exception(ctx, POWERPC_EXCP_VPU); \
6079 gen_set_access_type(ctx, ACCESS_INT); \
6080 EA = tcg_temp_new(); \
6081 gen_addr_reg_index(ctx, EA); \
6083 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6085 rs = gen_avr_ptr(rS(ctx->opcode)); \
6086 gen_helper_lve##name(cpu_env, rs, EA); \
6087 tcg_temp_free(EA); \
6088 tcg_temp_free_ptr(rs); \
6091 #define GEN_VR_STVE(name, opc2, opc3, size) \
6092 static void gen_stve##name(DisasContext *ctx) \
6096 if (unlikely(!ctx->altivec_enabled)) { \
6097 gen_exception(ctx, POWERPC_EXCP_VPU); \
6100 gen_set_access_type(ctx, ACCESS_INT); \
6101 EA = tcg_temp_new(); \
6102 gen_addr_reg_index(ctx, EA); \
6104 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6106 rs = gen_avr_ptr(rS(ctx->opcode)); \
6107 gen_helper_stve##name(cpu_env, rs, EA); \
6108 tcg_temp_free(EA); \
6109 tcg_temp_free_ptr(rs); \
6112 GEN_VR_LDX(lvx
, 0x07, 0x03);
6113 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6114 GEN_VR_LDX(lvxl
, 0x07, 0x0B);
6116 GEN_VR_LVE(bx
, 0x07, 0x00, 1);
6117 GEN_VR_LVE(hx
, 0x07, 0x01, 2);
6118 GEN_VR_LVE(wx
, 0x07, 0x02, 4);
6120 GEN_VR_STX(svx
, 0x07, 0x07);
6121 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6122 GEN_VR_STX(svxl
, 0x07, 0x0F);
6124 GEN_VR_STVE(bx
, 0x07, 0x04, 1);
6125 GEN_VR_STVE(hx
, 0x07, 0x05, 2);
6126 GEN_VR_STVE(wx
, 0x07, 0x06, 4);
6128 static void gen_lvsl(DisasContext
*ctx
)
6132 if (unlikely(!ctx
->altivec_enabled
)) {
6133 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6136 EA
= tcg_temp_new();
6137 gen_addr_reg_index(ctx
, EA
);
6138 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6139 gen_helper_lvsl(rd
, EA
);
6141 tcg_temp_free_ptr(rd
);
6144 static void gen_lvsr(DisasContext
*ctx
)
6148 if (unlikely(!ctx
->altivec_enabled
)) {
6149 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6152 EA
= tcg_temp_new();
6153 gen_addr_reg_index(ctx
, EA
);
6154 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6155 gen_helper_lvsr(rd
, EA
);
6157 tcg_temp_free_ptr(rd
);
6160 static void gen_mfvscr(DisasContext
*ctx
)
6163 if (unlikely(!ctx
->altivec_enabled
)) {
6164 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6167 tcg_gen_movi_i64(cpu_avrh
[rD(ctx
->opcode
)], 0);
6168 t
= tcg_temp_new_i32();
6169 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUPPCState
, vscr
));
6170 tcg_gen_extu_i32_i64(cpu_avrl
[rD(ctx
->opcode
)], t
);
6171 tcg_temp_free_i32(t
);
6174 static void gen_mtvscr(DisasContext
*ctx
)
6177 if (unlikely(!ctx
->altivec_enabled
)) {
6178 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6181 p
= gen_avr_ptr(rB(ctx
->opcode
));
6182 gen_helper_mtvscr(cpu_env
, p
);
6183 tcg_temp_free_ptr(p
);
6186 /* Logical operations */
6187 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6188 static void glue(gen_, name)(DisasContext *ctx) \
6190 if (unlikely(!ctx->altivec_enabled)) { \
6191 gen_exception(ctx, POWERPC_EXCP_VPU); \
6194 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6195 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6198 GEN_VX_LOGICAL(vand
, tcg_gen_and_i64
, 2, 16);
6199 GEN_VX_LOGICAL(vandc
, tcg_gen_andc_i64
, 2, 17);
6200 GEN_VX_LOGICAL(vor
, tcg_gen_or_i64
, 2, 18);
6201 GEN_VX_LOGICAL(vxor
, tcg_gen_xor_i64
, 2, 19);
6202 GEN_VX_LOGICAL(vnor
, tcg_gen_nor_i64
, 2, 20);
6203 GEN_VX_LOGICAL(veqv
, tcg_gen_eqv_i64
, 2, 26);
6204 GEN_VX_LOGICAL(vnand
, tcg_gen_nand_i64
, 2, 22);
6205 GEN_VX_LOGICAL(vorc
, tcg_gen_orc_i64
, 2, 21);
6207 #define GEN_VXFORM(name, opc2, opc3) \
6208 static void glue(gen_, name)(DisasContext *ctx) \
6210 TCGv_ptr ra, rb, rd; \
6211 if (unlikely(!ctx->altivec_enabled)) { \
6212 gen_exception(ctx, POWERPC_EXCP_VPU); \
6215 ra = gen_avr_ptr(rA(ctx->opcode)); \
6216 rb = gen_avr_ptr(rB(ctx->opcode)); \
6217 rd = gen_avr_ptr(rD(ctx->opcode)); \
6218 gen_helper_##name (rd, ra, rb); \
6219 tcg_temp_free_ptr(ra); \
6220 tcg_temp_free_ptr(rb); \
6221 tcg_temp_free_ptr(rd); \
6224 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6225 static void glue(gen_, name)(DisasContext *ctx) \
6227 TCGv_ptr ra, rb, rd; \
6228 if (unlikely(!ctx->altivec_enabled)) { \
6229 gen_exception(ctx, POWERPC_EXCP_VPU); \
6232 ra = gen_avr_ptr(rA(ctx->opcode)); \
6233 rb = gen_avr_ptr(rB(ctx->opcode)); \
6234 rd = gen_avr_ptr(rD(ctx->opcode)); \
6235 gen_helper_##name(cpu_env, rd, ra, rb); \
6236 tcg_temp_free_ptr(ra); \
6237 tcg_temp_free_ptr(rb); \
6238 tcg_temp_free_ptr(rd); \
6241 #define GEN_VXFORM3(name, opc2, opc3) \
6242 static void glue(gen_, name)(DisasContext *ctx) \
6244 TCGv_ptr ra, rb, rc, rd; \
6245 if (unlikely(!ctx->altivec_enabled)) { \
6246 gen_exception(ctx, POWERPC_EXCP_VPU); \
6249 ra = gen_avr_ptr(rA(ctx->opcode)); \
6250 rb = gen_avr_ptr(rB(ctx->opcode)); \
6251 rc = gen_avr_ptr(rC(ctx->opcode)); \
6252 rd = gen_avr_ptr(rD(ctx->opcode)); \
6253 gen_helper_##name(rd, ra, rb, rc); \
6254 tcg_temp_free_ptr(ra); \
6255 tcg_temp_free_ptr(rb); \
6256 tcg_temp_free_ptr(rc); \
6257 tcg_temp_free_ptr(rd); \
6261 * Support for Altivec instruction pairs that use bit 31 (Rc) as
6262 * an opcode bit. In general, these pairs come from different
6263 * versions of the ISA, so we must also support a pair of flags for
6266 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
6267 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6269 if ((Rc(ctx->opcode) == 0) && \
6270 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
6272 } else if ((Rc(ctx->opcode) == 1) && \
6273 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
6276 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
6280 GEN_VXFORM(vaddubm
, 0, 0);
6281 GEN_VXFORM(vadduhm
, 0, 1);
6282 GEN_VXFORM(vadduwm
, 0, 2);
6283 GEN_VXFORM(vaddudm
, 0, 3);
6284 GEN_VXFORM(vsububm
, 0, 16);
6285 GEN_VXFORM(vsubuhm
, 0, 17);
6286 GEN_VXFORM(vsubuwm
, 0, 18);
6287 GEN_VXFORM(vsubudm
, 0, 19);
6288 GEN_VXFORM(vmaxub
, 1, 0);
6289 GEN_VXFORM(vmaxuh
, 1, 1);
6290 GEN_VXFORM(vmaxuw
, 1, 2);
6291 GEN_VXFORM(vmaxud
, 1, 3);
6292 GEN_VXFORM(vmaxsb
, 1, 4);
6293 GEN_VXFORM(vmaxsh
, 1, 5);
6294 GEN_VXFORM(vmaxsw
, 1, 6);
6295 GEN_VXFORM(vmaxsd
, 1, 7);
6296 GEN_VXFORM(vminub
, 1, 8);
6297 GEN_VXFORM(vminuh
, 1, 9);
6298 GEN_VXFORM(vminuw
, 1, 10);
6299 GEN_VXFORM(vminud
, 1, 11);
6300 GEN_VXFORM(vminsb
, 1, 12);
6301 GEN_VXFORM(vminsh
, 1, 13);
6302 GEN_VXFORM(vminsw
, 1, 14);
6303 GEN_VXFORM(vminsd
, 1, 15);
6304 GEN_VXFORM(vavgub
, 1, 16);
6305 GEN_VXFORM(vavguh
, 1, 17);
6306 GEN_VXFORM(vavguw
, 1, 18);
6307 GEN_VXFORM(vavgsb
, 1, 20);
6308 GEN_VXFORM(vavgsh
, 1, 21);
6309 GEN_VXFORM(vavgsw
, 1, 22);
6310 GEN_VXFORM(vmrghb
, 6, 0);
6311 GEN_VXFORM(vmrghh
, 6, 1);
6312 GEN_VXFORM(vmrghw
, 6, 2);
6313 GEN_VXFORM(vmrglb
, 6, 4);
6314 GEN_VXFORM(vmrglh
, 6, 5);
6315 GEN_VXFORM(vmrglw
, 6, 6);
6317 static void gen_vmrgew(DisasContext
*ctx
)
6321 if (unlikely(!ctx
->altivec_enabled
)) {
6322 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6325 VT
= rD(ctx
->opcode
);
6326 VA
= rA(ctx
->opcode
);
6327 VB
= rB(ctx
->opcode
);
6328 tmp
= tcg_temp_new_i64();
6329 tcg_gen_shri_i64(tmp
, cpu_avrh
[VB
], 32);
6330 tcg_gen_deposit_i64(cpu_avrh
[VT
], cpu_avrh
[VA
], tmp
, 0, 32);
6331 tcg_gen_shri_i64(tmp
, cpu_avrl
[VB
], 32);
6332 tcg_gen_deposit_i64(cpu_avrl
[VT
], cpu_avrl
[VA
], tmp
, 0, 32);
6333 tcg_temp_free_i64(tmp
);
6336 static void gen_vmrgow(DisasContext
*ctx
)
6339 if (unlikely(!ctx
->altivec_enabled
)) {
6340 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6343 VT
= rD(ctx
->opcode
);
6344 VA
= rA(ctx
->opcode
);
6345 VB
= rB(ctx
->opcode
);
6347 tcg_gen_deposit_i64(cpu_avrh
[VT
], cpu_avrh
[VB
], cpu_avrh
[VA
], 32, 32);
6348 tcg_gen_deposit_i64(cpu_avrl
[VT
], cpu_avrl
[VB
], cpu_avrl
[VA
], 32, 32);
6351 GEN_VXFORM(vmuloub
, 4, 0);
6352 GEN_VXFORM(vmulouh
, 4, 1);
6353 GEN_VXFORM(vmulouw
, 4, 2);
6354 GEN_VXFORM(vmuluwm
, 4, 2);
6355 GEN_VXFORM_DUAL(vmulouw
, PPC_ALTIVEC
, PPC_NONE
,
6356 vmuluwm
, PPC_NONE
, PPC2_ALTIVEC_207
)
6357 GEN_VXFORM(vmulosb
, 4, 4);
6358 GEN_VXFORM(vmulosh
, 4, 5);
6359 GEN_VXFORM(vmulosw
, 4, 6);
6360 GEN_VXFORM(vmuleub
, 4, 8);
6361 GEN_VXFORM(vmuleuh
, 4, 9);
6362 GEN_VXFORM(vmuleuw
, 4, 10);
6363 GEN_VXFORM(vmulesb
, 4, 12);
6364 GEN_VXFORM(vmulesh
, 4, 13);
6365 GEN_VXFORM(vmulesw
, 4, 14);
6366 GEN_VXFORM(vslb
, 2, 4);
6367 GEN_VXFORM(vslh
, 2, 5);
6368 GEN_VXFORM(vslw
, 2, 6);
6369 GEN_VXFORM(vsld
, 2, 23);
6370 GEN_VXFORM(vsrb
, 2, 8);
6371 GEN_VXFORM(vsrh
, 2, 9);
6372 GEN_VXFORM(vsrw
, 2, 10);
6373 GEN_VXFORM(vsrd
, 2, 27);
6374 GEN_VXFORM(vsrab
, 2, 12);
6375 GEN_VXFORM(vsrah
, 2, 13);
6376 GEN_VXFORM(vsraw
, 2, 14);
6377 GEN_VXFORM(vsrad
, 2, 15);
6378 GEN_VXFORM(vslo
, 6, 16);
6379 GEN_VXFORM(vsro
, 6, 17);
6380 GEN_VXFORM(vaddcuw
, 0, 6);
6381 GEN_VXFORM(vsubcuw
, 0, 22);
6382 GEN_VXFORM_ENV(vaddubs
, 0, 8);
6383 GEN_VXFORM_ENV(vadduhs
, 0, 9);
6384 GEN_VXFORM_ENV(vadduws
, 0, 10);
6385 GEN_VXFORM_ENV(vaddsbs
, 0, 12);
6386 GEN_VXFORM_ENV(vaddshs
, 0, 13);
6387 GEN_VXFORM_ENV(vaddsws
, 0, 14);
6388 GEN_VXFORM_ENV(vsububs
, 0, 24);
6389 GEN_VXFORM_ENV(vsubuhs
, 0, 25);
6390 GEN_VXFORM_ENV(vsubuws
, 0, 26);
6391 GEN_VXFORM_ENV(vsubsbs
, 0, 28);
6392 GEN_VXFORM_ENV(vsubshs
, 0, 29);
6393 GEN_VXFORM_ENV(vsubsws
, 0, 30);
6394 GEN_VXFORM(vadduqm
, 0, 4);
6395 GEN_VXFORM(vaddcuq
, 0, 5);
6396 GEN_VXFORM3(vaddeuqm
, 30, 0);
6397 GEN_VXFORM3(vaddecuq
, 30, 0);
6398 GEN_VXFORM_DUAL(vaddeuqm
, PPC_NONE
, PPC2_ALTIVEC_207
, \
6399 vaddecuq
, PPC_NONE
, PPC2_ALTIVEC_207
)
6400 GEN_VXFORM(vsubuqm
, 0, 20);
6401 GEN_VXFORM(vsubcuq
, 0, 21);
6402 GEN_VXFORM3(vsubeuqm
, 31, 0);
6403 GEN_VXFORM3(vsubecuq
, 31, 0);
6404 GEN_VXFORM_DUAL(vsubeuqm
, PPC_NONE
, PPC2_ALTIVEC_207
, \
6405 vsubecuq
, PPC_NONE
, PPC2_ALTIVEC_207
)
6406 GEN_VXFORM(vrlb
, 2, 0);
6407 GEN_VXFORM(vrlh
, 2, 1);
6408 GEN_VXFORM(vrlw
, 2, 2);
6409 GEN_VXFORM(vrld
, 2, 3);
6410 GEN_VXFORM(vsl
, 2, 7);
6411 GEN_VXFORM(vsr
, 2, 11);
6412 GEN_VXFORM_ENV(vpkuhum
, 7, 0);
6413 GEN_VXFORM_ENV(vpkuwum
, 7, 1);
6414 GEN_VXFORM_ENV(vpkudum
, 7, 17);
6415 GEN_VXFORM_ENV(vpkuhus
, 7, 2);
6416 GEN_VXFORM_ENV(vpkuwus
, 7, 3);
6417 GEN_VXFORM_ENV(vpkudus
, 7, 19);
6418 GEN_VXFORM_ENV(vpkshus
, 7, 4);
6419 GEN_VXFORM_ENV(vpkswus
, 7, 5);
6420 GEN_VXFORM_ENV(vpksdus
, 7, 21);
6421 GEN_VXFORM_ENV(vpkshss
, 7, 6);
6422 GEN_VXFORM_ENV(vpkswss
, 7, 7);
6423 GEN_VXFORM_ENV(vpksdss
, 7, 23);
6424 GEN_VXFORM(vpkpx
, 7, 12);
6425 GEN_VXFORM_ENV(vsum4ubs
, 4, 24);
6426 GEN_VXFORM_ENV(vsum4sbs
, 4, 28);
6427 GEN_VXFORM_ENV(vsum4shs
, 4, 25);
6428 GEN_VXFORM_ENV(vsum2sws
, 4, 26);
6429 GEN_VXFORM_ENV(vsumsws
, 4, 30);
6430 GEN_VXFORM_ENV(vaddfp
, 5, 0);
6431 GEN_VXFORM_ENV(vsubfp
, 5, 1);
6432 GEN_VXFORM_ENV(vmaxfp
, 5, 16);
6433 GEN_VXFORM_ENV(vminfp
, 5, 17);
6435 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6436 static void glue(gen_, name)(DisasContext *ctx) \
6438 TCGv_ptr ra, rb, rd; \
6439 if (unlikely(!ctx->altivec_enabled)) { \
6440 gen_exception(ctx, POWERPC_EXCP_VPU); \
6443 ra = gen_avr_ptr(rA(ctx->opcode)); \
6444 rb = gen_avr_ptr(rB(ctx->opcode)); \
6445 rd = gen_avr_ptr(rD(ctx->opcode)); \
6446 gen_helper_##opname(cpu_env, rd, ra, rb); \
6447 tcg_temp_free_ptr(ra); \
6448 tcg_temp_free_ptr(rb); \
6449 tcg_temp_free_ptr(rd); \
6452 #define GEN_VXRFORM(name, opc2, opc3) \
6453 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6454 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6457 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
6458 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
6459 * come from different versions of the ISA, so we must also support a
6460 * pair of flags for each instruction.
6462 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
6463 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6465 if ((Rc(ctx->opcode) == 0) && \
6466 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
6467 if (Rc21(ctx->opcode) == 0) { \
6470 gen_##name0##_(ctx); \
6472 } else if ((Rc(ctx->opcode) == 1) && \
6473 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
6474 if (Rc21(ctx->opcode) == 0) { \
6477 gen_##name1##_(ctx); \
6480 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
6484 GEN_VXRFORM(vcmpequb
, 3, 0)
6485 GEN_VXRFORM(vcmpequh
, 3, 1)
6486 GEN_VXRFORM(vcmpequw
, 3, 2)
6487 GEN_VXRFORM(vcmpequd
, 3, 3)
6488 GEN_VXRFORM(vcmpgtsb
, 3, 12)
6489 GEN_VXRFORM(vcmpgtsh
, 3, 13)
6490 GEN_VXRFORM(vcmpgtsw
, 3, 14)
6491 GEN_VXRFORM(vcmpgtsd
, 3, 15)
6492 GEN_VXRFORM(vcmpgtub
, 3, 8)
6493 GEN_VXRFORM(vcmpgtuh
, 3, 9)
6494 GEN_VXRFORM(vcmpgtuw
, 3, 10)
6495 GEN_VXRFORM(vcmpgtud
, 3, 11)
6496 GEN_VXRFORM(vcmpeqfp
, 3, 3)
6497 GEN_VXRFORM(vcmpgefp
, 3, 7)
6498 GEN_VXRFORM(vcmpgtfp
, 3, 11)
6499 GEN_VXRFORM(vcmpbfp
, 3, 15)
6501 GEN_VXRFORM_DUAL(vcmpeqfp
, PPC_ALTIVEC
, PPC_NONE
, \
6502 vcmpequd
, PPC_NONE
, PPC2_ALTIVEC_207
)
6503 GEN_VXRFORM_DUAL(vcmpbfp
, PPC_ALTIVEC
, PPC_NONE
, \
6504 vcmpgtsd
, PPC_NONE
, PPC2_ALTIVEC_207
)
6505 GEN_VXRFORM_DUAL(vcmpgtfp
, PPC_ALTIVEC
, PPC_NONE
, \
6506 vcmpgtud
, PPC_NONE
, PPC2_ALTIVEC_207
)
6508 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6509 static void glue(gen_, name)(DisasContext *ctx) \
6513 if (unlikely(!ctx->altivec_enabled)) { \
6514 gen_exception(ctx, POWERPC_EXCP_VPU); \
6517 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6518 rd = gen_avr_ptr(rD(ctx->opcode)); \
6519 gen_helper_##name (rd, simm); \
6520 tcg_temp_free_i32(simm); \
6521 tcg_temp_free_ptr(rd); \
6524 GEN_VXFORM_SIMM(vspltisb
, 6, 12);
6525 GEN_VXFORM_SIMM(vspltish
, 6, 13);
6526 GEN_VXFORM_SIMM(vspltisw
, 6, 14);
6528 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6529 static void glue(gen_, name)(DisasContext *ctx) \
6532 if (unlikely(!ctx->altivec_enabled)) { \
6533 gen_exception(ctx, POWERPC_EXCP_VPU); \
6536 rb = gen_avr_ptr(rB(ctx->opcode)); \
6537 rd = gen_avr_ptr(rD(ctx->opcode)); \
6538 gen_helper_##name (rd, rb); \
6539 tcg_temp_free_ptr(rb); \
6540 tcg_temp_free_ptr(rd); \
6543 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
6544 static void glue(gen_, name)(DisasContext *ctx) \
6548 if (unlikely(!ctx->altivec_enabled)) { \
6549 gen_exception(ctx, POWERPC_EXCP_VPU); \
6552 rb = gen_avr_ptr(rB(ctx->opcode)); \
6553 rd = gen_avr_ptr(rD(ctx->opcode)); \
6554 gen_helper_##name(cpu_env, rd, rb); \
6555 tcg_temp_free_ptr(rb); \
6556 tcg_temp_free_ptr(rd); \
6559 GEN_VXFORM_NOA(vupkhsb
, 7, 8);
6560 GEN_VXFORM_NOA(vupkhsh
, 7, 9);
6561 GEN_VXFORM_NOA(vupkhsw
, 7, 25);
6562 GEN_VXFORM_NOA(vupklsb
, 7, 10);
6563 GEN_VXFORM_NOA(vupklsh
, 7, 11);
6564 GEN_VXFORM_NOA(vupklsw
, 7, 27);
6565 GEN_VXFORM_NOA(vupkhpx
, 7, 13);
6566 GEN_VXFORM_NOA(vupklpx
, 7, 15);
6567 GEN_VXFORM_NOA_ENV(vrefp
, 5, 4);
6568 GEN_VXFORM_NOA_ENV(vrsqrtefp
, 5, 5);
6569 GEN_VXFORM_NOA_ENV(vexptefp
, 5, 6);
6570 GEN_VXFORM_NOA_ENV(vlogefp
, 5, 7);
6571 GEN_VXFORM_NOA_ENV(vrfim
, 5, 11);
6572 GEN_VXFORM_NOA_ENV(vrfin
, 5, 8);
6573 GEN_VXFORM_NOA_ENV(vrfip
, 5, 10);
6574 GEN_VXFORM_NOA_ENV(vrfiz
, 5, 9);
6576 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6577 static void glue(gen_, name)(DisasContext *ctx) \
6581 if (unlikely(!ctx->altivec_enabled)) { \
6582 gen_exception(ctx, POWERPC_EXCP_VPU); \
6585 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6586 rd = gen_avr_ptr(rD(ctx->opcode)); \
6587 gen_helper_##name (rd, simm); \
6588 tcg_temp_free_i32(simm); \
6589 tcg_temp_free_ptr(rd); \
6592 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6593 static void glue(gen_, name)(DisasContext *ctx) \
6597 if (unlikely(!ctx->altivec_enabled)) { \
6598 gen_exception(ctx, POWERPC_EXCP_VPU); \
6601 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6602 rb = gen_avr_ptr(rB(ctx->opcode)); \
6603 rd = gen_avr_ptr(rD(ctx->opcode)); \
6604 gen_helper_##name (rd, rb, uimm); \
6605 tcg_temp_free_i32(uimm); \
6606 tcg_temp_free_ptr(rb); \
6607 tcg_temp_free_ptr(rd); \
6610 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
6611 static void glue(gen_, name)(DisasContext *ctx) \
6616 if (unlikely(!ctx->altivec_enabled)) { \
6617 gen_exception(ctx, POWERPC_EXCP_VPU); \
6620 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6621 rb = gen_avr_ptr(rB(ctx->opcode)); \
6622 rd = gen_avr_ptr(rD(ctx->opcode)); \
6623 gen_helper_##name(cpu_env, rd, rb, uimm); \
6624 tcg_temp_free_i32(uimm); \
6625 tcg_temp_free_ptr(rb); \
6626 tcg_temp_free_ptr(rd); \
6629 GEN_VXFORM_UIMM(vspltb
, 6, 8);
6630 GEN_VXFORM_UIMM(vsplth
, 6, 9);
6631 GEN_VXFORM_UIMM(vspltw
, 6, 10);
6632 GEN_VXFORM_UIMM_ENV(vcfux
, 5, 12);
6633 GEN_VXFORM_UIMM_ENV(vcfsx
, 5, 13);
6634 GEN_VXFORM_UIMM_ENV(vctuxs
, 5, 14);
6635 GEN_VXFORM_UIMM_ENV(vctsxs
, 5, 15);
6637 static void gen_vsldoi(DisasContext
*ctx
)
6639 TCGv_ptr ra
, rb
, rd
;
6641 if (unlikely(!ctx
->altivec_enabled
)) {
6642 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6645 ra
= gen_avr_ptr(rA(ctx
->opcode
));
6646 rb
= gen_avr_ptr(rB(ctx
->opcode
));
6647 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6648 sh
= tcg_const_i32(VSH(ctx
->opcode
));
6649 gen_helper_vsldoi (rd
, ra
, rb
, sh
);
6650 tcg_temp_free_ptr(ra
);
6651 tcg_temp_free_ptr(rb
);
6652 tcg_temp_free_ptr(rd
);
6653 tcg_temp_free_i32(sh
);
6656 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6657 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6659 TCGv_ptr ra, rb, rc, rd; \
6660 if (unlikely(!ctx->altivec_enabled)) { \
6661 gen_exception(ctx, POWERPC_EXCP_VPU); \
6664 ra = gen_avr_ptr(rA(ctx->opcode)); \
6665 rb = gen_avr_ptr(rB(ctx->opcode)); \
6666 rc = gen_avr_ptr(rC(ctx->opcode)); \
6667 rd = gen_avr_ptr(rD(ctx->opcode)); \
6668 if (Rc(ctx->opcode)) { \
6669 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
6671 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
6673 tcg_temp_free_ptr(ra); \
6674 tcg_temp_free_ptr(rb); \
6675 tcg_temp_free_ptr(rc); \
6676 tcg_temp_free_ptr(rd); \
6679 GEN_VAFORM_PAIRED(vmhaddshs
, vmhraddshs
, 16)
6681 static void gen_vmladduhm(DisasContext
*ctx
)
6683 TCGv_ptr ra
, rb
, rc
, rd
;
6684 if (unlikely(!ctx
->altivec_enabled
)) {
6685 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6688 ra
= gen_avr_ptr(rA(ctx
->opcode
));
6689 rb
= gen_avr_ptr(rB(ctx
->opcode
));
6690 rc
= gen_avr_ptr(rC(ctx
->opcode
));
6691 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6692 gen_helper_vmladduhm(rd
, ra
, rb
, rc
);
6693 tcg_temp_free_ptr(ra
);
6694 tcg_temp_free_ptr(rb
);
6695 tcg_temp_free_ptr(rc
);
6696 tcg_temp_free_ptr(rd
);
6699 GEN_VAFORM_PAIRED(vmsumubm
, vmsummbm
, 18)
6700 GEN_VAFORM_PAIRED(vmsumuhm
, vmsumuhs
, 19)
6701 GEN_VAFORM_PAIRED(vmsumshm
, vmsumshs
, 20)
6702 GEN_VAFORM_PAIRED(vsel
, vperm
, 21)
6703 GEN_VAFORM_PAIRED(vmaddfp
, vnmsubfp
, 23)
6705 #if defined(TARGET_PPC64)
6706 static void gen_maddld(DisasContext
*ctx
)
6708 TCGv_i64 t1
= tcg_temp_new_i64();
6710 tcg_gen_mul_i64(t1
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
6711 tcg_gen_add_i64(cpu_gpr
[rD(ctx
->opcode
)], t1
, cpu_gpr
[rC(ctx
->opcode
)]);
6712 tcg_temp_free_i64(t1
);
6715 /* maddhd maddhdu */
6716 static void gen_maddhd_maddhdu(DisasContext
*ctx
)
6718 TCGv_i64 lo
= tcg_temp_new_i64();
6719 TCGv_i64 hi
= tcg_temp_new_i64();
6720 TCGv_i64 t1
= tcg_temp_new_i64();
6722 if (Rc(ctx
->opcode
)) {
6723 tcg_gen_mulu2_i64(lo
, hi
, cpu_gpr
[rA(ctx
->opcode
)],
6724 cpu_gpr
[rB(ctx
->opcode
)]);
6725 tcg_gen_movi_i64(t1
, 0);
6727 tcg_gen_muls2_i64(lo
, hi
, cpu_gpr
[rA(ctx
->opcode
)],
6728 cpu_gpr
[rB(ctx
->opcode
)]);
6729 tcg_gen_sari_i64(t1
, cpu_gpr
[rC(ctx
->opcode
)], 63);
6731 tcg_gen_add2_i64(t1
, cpu_gpr
[rD(ctx
->opcode
)], lo
, hi
,
6732 cpu_gpr
[rC(ctx
->opcode
)], t1
);
6733 tcg_temp_free_i64(lo
);
6734 tcg_temp_free_i64(hi
);
6735 tcg_temp_free_i64(t1
);
6737 #endif /* defined(TARGET_PPC64) */
6739 GEN_VXFORM_NOA(vclzb
, 1, 28)
6740 GEN_VXFORM_NOA(vclzh
, 1, 29)
6741 GEN_VXFORM_NOA(vclzw
, 1, 30)
6742 GEN_VXFORM_NOA(vclzd
, 1, 31)
6743 GEN_VXFORM_NOA(vpopcntb
, 1, 28)
6744 GEN_VXFORM_NOA(vpopcnth
, 1, 29)
6745 GEN_VXFORM_NOA(vpopcntw
, 1, 30)
6746 GEN_VXFORM_NOA(vpopcntd
, 1, 31)
6747 GEN_VXFORM_DUAL(vclzb
, PPC_NONE
, PPC2_ALTIVEC_207
, \
6748 vpopcntb
, PPC_NONE
, PPC2_ALTIVEC_207
)
6749 GEN_VXFORM_DUAL(vclzh
, PPC_NONE
, PPC2_ALTIVEC_207
, \
6750 vpopcnth
, PPC_NONE
, PPC2_ALTIVEC_207
)
6751 GEN_VXFORM_DUAL(vclzw
, PPC_NONE
, PPC2_ALTIVEC_207
, \
6752 vpopcntw
, PPC_NONE
, PPC2_ALTIVEC_207
)
6753 GEN_VXFORM_DUAL(vclzd
, PPC_NONE
, PPC2_ALTIVEC_207
, \
6754 vpopcntd
, PPC_NONE
, PPC2_ALTIVEC_207
)
6755 GEN_VXFORM(vbpermq
, 6, 21);
6756 GEN_VXFORM_NOA(vgbbd
, 6, 20);
6757 GEN_VXFORM(vpmsumb
, 4, 16)
6758 GEN_VXFORM(vpmsumh
, 4, 17)
6759 GEN_VXFORM(vpmsumw
, 4, 18)
6760 GEN_VXFORM(vpmsumd
, 4, 19)
6762 #define GEN_BCD(op) \
6763 static void gen_##op(DisasContext *ctx) \
6765 TCGv_ptr ra, rb, rd; \
6768 if (unlikely(!ctx->altivec_enabled)) { \
6769 gen_exception(ctx, POWERPC_EXCP_VPU); \
6773 ra = gen_avr_ptr(rA(ctx->opcode)); \
6774 rb = gen_avr_ptr(rB(ctx->opcode)); \
6775 rd = gen_avr_ptr(rD(ctx->opcode)); \
6777 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
6779 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
6781 tcg_temp_free_ptr(ra); \
6782 tcg_temp_free_ptr(rb); \
6783 tcg_temp_free_ptr(rd); \
6784 tcg_temp_free_i32(ps); \
6790 GEN_VXFORM_DUAL(vsububm
, PPC_ALTIVEC
, PPC_NONE
, \
6791 bcdadd
, PPC_NONE
, PPC2_ALTIVEC_207
)
6792 GEN_VXFORM_DUAL(vsububs
, PPC_ALTIVEC
, PPC_NONE
, \
6793 bcdadd
, PPC_NONE
, PPC2_ALTIVEC_207
)
6794 GEN_VXFORM_DUAL(vsubuhm
, PPC_ALTIVEC
, PPC_NONE
, \
6795 bcdsub
, PPC_NONE
, PPC2_ALTIVEC_207
)
6796 GEN_VXFORM_DUAL(vsubuhs
, PPC_ALTIVEC
, PPC_NONE
, \
6797 bcdsub
, PPC_NONE
, PPC2_ALTIVEC_207
)
6799 static void gen_vsbox(DisasContext
*ctx
)
6802 if (unlikely(!ctx
->altivec_enabled
)) {
6803 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6806 ra
= gen_avr_ptr(rA(ctx
->opcode
));
6807 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6808 gen_helper_vsbox(rd
, ra
);
6809 tcg_temp_free_ptr(ra
);
6810 tcg_temp_free_ptr(rd
);
6813 GEN_VXFORM(vcipher
, 4, 20)
6814 GEN_VXFORM(vcipherlast
, 4, 20)
6815 GEN_VXFORM(vncipher
, 4, 21)
6816 GEN_VXFORM(vncipherlast
, 4, 21)
6818 GEN_VXFORM_DUAL(vcipher
, PPC_NONE
, PPC2_ALTIVEC_207
,
6819 vcipherlast
, PPC_NONE
, PPC2_ALTIVEC_207
)
6820 GEN_VXFORM_DUAL(vncipher
, PPC_NONE
, PPC2_ALTIVEC_207
,
6821 vncipherlast
, PPC_NONE
, PPC2_ALTIVEC_207
)
6823 #define VSHASIGMA(op) \
6824 static void gen_##op(DisasContext *ctx) \
6828 if (unlikely(!ctx->altivec_enabled)) { \
6829 gen_exception(ctx, POWERPC_EXCP_VPU); \
6832 ra = gen_avr_ptr(rA(ctx->opcode)); \
6833 rd = gen_avr_ptr(rD(ctx->opcode)); \
6834 st_six = tcg_const_i32(rB(ctx->opcode)); \
6835 gen_helper_##op(rd, ra, st_six); \
6836 tcg_temp_free_ptr(ra); \
6837 tcg_temp_free_ptr(rd); \
6838 tcg_temp_free_i32(st_six); \
6841 VSHASIGMA(vshasigmaw
)
6842 VSHASIGMA(vshasigmad
)
6844 GEN_VXFORM3(vpermxor
, 22, 0xFF)
6845 GEN_VXFORM_DUAL(vsldoi
, PPC_ALTIVEC
, PPC_NONE
,
6846 vpermxor
, PPC_NONE
, PPC2_ALTIVEC_207
)
6848 /*** VSX extension ***/
6850 static inline TCGv_i64
cpu_vsrh(int n
)
6855 return cpu_avrh
[n
-32];
6859 static inline TCGv_i64
cpu_vsrl(int n
)
6864 return cpu_avrl
[n
-32];
6868 #define VSX_LOAD_SCALAR(name, operation) \
6869 static void gen_##name(DisasContext *ctx) \
6872 if (unlikely(!ctx->vsx_enabled)) { \
6873 gen_exception(ctx, POWERPC_EXCP_VSXU); \
6876 gen_set_access_type(ctx, ACCESS_INT); \
6877 EA = tcg_temp_new(); \
6878 gen_addr_reg_index(ctx, EA); \
6879 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
6880 /* NOTE: cpu_vsrl is undefined */ \
6881 tcg_temp_free(EA); \
6884 VSX_LOAD_SCALAR(lxsdx
, ld64
)
6885 VSX_LOAD_SCALAR(lxsiwax
, ld32s_i64
)
6886 VSX_LOAD_SCALAR(lxsiwzx
, ld32u_i64
)
6887 VSX_LOAD_SCALAR(lxsspx
, ld32fs
)
6889 static void gen_lxvd2x(DisasContext
*ctx
)
6892 if (unlikely(!ctx
->vsx_enabled
)) {
6893 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
6896 gen_set_access_type(ctx
, ACCESS_INT
);
6897 EA
= tcg_temp_new();
6898 gen_addr_reg_index(ctx
, EA
);
6899 gen_qemu_ld64(ctx
, cpu_vsrh(xT(ctx
->opcode
)), EA
);
6900 tcg_gen_addi_tl(EA
, EA
, 8);
6901 gen_qemu_ld64(ctx
, cpu_vsrl(xT(ctx
->opcode
)), EA
);
6905 static void gen_lxvdsx(DisasContext
*ctx
)
6908 if (unlikely(!ctx
->vsx_enabled
)) {
6909 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
6912 gen_set_access_type(ctx
, ACCESS_INT
);
6913 EA
= tcg_temp_new();
6914 gen_addr_reg_index(ctx
, EA
);
6915 gen_qemu_ld64(ctx
, cpu_vsrh(xT(ctx
->opcode
)), EA
);
6916 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), cpu_vsrh(xT(ctx
->opcode
)));
6920 static void gen_lxvw4x(DisasContext
*ctx
)
6924 TCGv_i64 xth
= cpu_vsrh(xT(ctx
->opcode
));
6925 TCGv_i64 xtl
= cpu_vsrl(xT(ctx
->opcode
));
6926 if (unlikely(!ctx
->vsx_enabled
)) {
6927 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
6930 gen_set_access_type(ctx
, ACCESS_INT
);
6931 EA
= tcg_temp_new();
6932 tmp
= tcg_temp_new_i64();
6934 gen_addr_reg_index(ctx
, EA
);
6935 gen_qemu_ld32u_i64(ctx
, tmp
, EA
);
6936 tcg_gen_addi_tl(EA
, EA
, 4);
6937 gen_qemu_ld32u_i64(ctx
, xth
, EA
);
6938 tcg_gen_deposit_i64(xth
, xth
, tmp
, 32, 32);
6940 tcg_gen_addi_tl(EA
, EA
, 4);
6941 gen_qemu_ld32u_i64(ctx
, tmp
, EA
);
6942 tcg_gen_addi_tl(EA
, EA
, 4);
6943 gen_qemu_ld32u_i64(ctx
, xtl
, EA
);
6944 tcg_gen_deposit_i64(xtl
, xtl
, tmp
, 32, 32);
6947 tcg_temp_free_i64(tmp
);
6950 #define VSX_STORE_SCALAR(name, operation) \
6951 static void gen_##name(DisasContext *ctx) \
6954 if (unlikely(!ctx->vsx_enabled)) { \
6955 gen_exception(ctx, POWERPC_EXCP_VSXU); \
6958 gen_set_access_type(ctx, ACCESS_INT); \
6959 EA = tcg_temp_new(); \
6960 gen_addr_reg_index(ctx, EA); \
6961 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
6962 tcg_temp_free(EA); \
6965 VSX_STORE_SCALAR(stxsdx
, st64
)
6966 VSX_STORE_SCALAR(stxsiwx
, st32_i64
)
6967 VSX_STORE_SCALAR(stxsspx
, st32fs
)
6969 static void gen_stxvd2x(DisasContext
*ctx
)
6972 if (unlikely(!ctx
->vsx_enabled
)) {
6973 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
6976 gen_set_access_type(ctx
, ACCESS_INT
);
6977 EA
= tcg_temp_new();
6978 gen_addr_reg_index(ctx
, EA
);
6979 gen_qemu_st64(ctx
, cpu_vsrh(xS(ctx
->opcode
)), EA
);
6980 tcg_gen_addi_tl(EA
, EA
, 8);
6981 gen_qemu_st64(ctx
, cpu_vsrl(xS(ctx
->opcode
)), EA
);
6985 static void gen_stxvw4x(DisasContext
*ctx
)
6989 if (unlikely(!ctx
->vsx_enabled
)) {
6990 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
6993 gen_set_access_type(ctx
, ACCESS_INT
);
6994 EA
= tcg_temp_new();
6995 gen_addr_reg_index(ctx
, EA
);
6996 tmp
= tcg_temp_new_i64();
6998 tcg_gen_shri_i64(tmp
, cpu_vsrh(xS(ctx
->opcode
)), 32);
6999 gen_qemu_st32_i64(ctx
, tmp
, EA
);
7000 tcg_gen_addi_tl(EA
, EA
, 4);
7001 gen_qemu_st32_i64(ctx
, cpu_vsrh(xS(ctx
->opcode
)), EA
);
7003 tcg_gen_shri_i64(tmp
, cpu_vsrl(xS(ctx
->opcode
)), 32);
7004 tcg_gen_addi_tl(EA
, EA
, 4);
7005 gen_qemu_st32_i64(ctx
, tmp
, EA
);
7006 tcg_gen_addi_tl(EA
, EA
, 4);
7007 gen_qemu_st32_i64(ctx
, cpu_vsrl(xS(ctx
->opcode
)), EA
);
7010 tcg_temp_free_i64(tmp
);
7013 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7014 static void gen_##name(DisasContext *ctx) \
7016 if (xS(ctx->opcode) < 32) { \
7017 if (unlikely(!ctx->fpu_enabled)) { \
7018 gen_exception(ctx, POWERPC_EXCP_FPU); \
7022 if (unlikely(!ctx->altivec_enabled)) { \
7023 gen_exception(ctx, POWERPC_EXCP_VPU); \
7027 TCGv_i64 tmp = tcg_temp_new_i64(); \
7028 tcg_gen_##tcgop1(tmp, source); \
7029 tcg_gen_##tcgop2(target, tmp); \
7030 tcg_temp_free_i64(tmp); \
7034 MV_VSRW(mfvsrwz
, ext32u_i64
, trunc_i64_tl
, cpu_gpr
[rA(ctx
->opcode
)], \
7035 cpu_vsrh(xS(ctx
->opcode
)))
7036 MV_VSRW(mtvsrwa
, extu_tl_i64
, ext32s_i64
, cpu_vsrh(xT(ctx
->opcode
)), \
7037 cpu_gpr
[rA(ctx
->opcode
)])
7038 MV_VSRW(mtvsrwz
, extu_tl_i64
, ext32u_i64
, cpu_vsrh(xT(ctx
->opcode
)), \
7039 cpu_gpr
[rA(ctx
->opcode
)])
7041 #if defined(TARGET_PPC64)
7042 #define MV_VSRD(name, target, source) \
7043 static void gen_##name(DisasContext *ctx) \
7045 if (xS(ctx->opcode) < 32) { \
7046 if (unlikely(!ctx->fpu_enabled)) { \
7047 gen_exception(ctx, POWERPC_EXCP_FPU); \
7051 if (unlikely(!ctx->altivec_enabled)) { \
7052 gen_exception(ctx, POWERPC_EXCP_VPU); \
7056 tcg_gen_mov_i64(target, source); \
7059 MV_VSRD(mfvsrd
, cpu_gpr
[rA(ctx
->opcode
)], cpu_vsrh(xS(ctx
->opcode
)))
7060 MV_VSRD(mtvsrd
, cpu_vsrh(xT(ctx
->opcode
)), cpu_gpr
[rA(ctx
->opcode
)])
7064 static void gen_xxpermdi(DisasContext
*ctx
)
7066 if (unlikely(!ctx
->vsx_enabled
)) {
7067 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
7071 if (unlikely((xT(ctx
->opcode
) == xA(ctx
->opcode
)) ||
7072 (xT(ctx
->opcode
) == xB(ctx
->opcode
)))) {
7075 xh
= tcg_temp_new_i64();
7076 xl
= tcg_temp_new_i64();
7078 if ((DM(ctx
->opcode
) & 2) == 0) {
7079 tcg_gen_mov_i64(xh
, cpu_vsrh(xA(ctx
->opcode
)));
7081 tcg_gen_mov_i64(xh
, cpu_vsrl(xA(ctx
->opcode
)));
7083 if ((DM(ctx
->opcode
) & 1) == 0) {
7084 tcg_gen_mov_i64(xl
, cpu_vsrh(xB(ctx
->opcode
)));
7086 tcg_gen_mov_i64(xl
, cpu_vsrl(xB(ctx
->opcode
)));
7089 tcg_gen_mov_i64(cpu_vsrh(xT(ctx
->opcode
)), xh
);
7090 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), xl
);
7092 tcg_temp_free_i64(xh
);
7093 tcg_temp_free_i64(xl
);
7095 if ((DM(ctx
->opcode
) & 2) == 0) {
7096 tcg_gen_mov_i64(cpu_vsrh(xT(ctx
->opcode
)), cpu_vsrh(xA(ctx
->opcode
)));
7098 tcg_gen_mov_i64(cpu_vsrh(xT(ctx
->opcode
)), cpu_vsrl(xA(ctx
->opcode
)));
7100 if ((DM(ctx
->opcode
) & 1) == 0) {
7101 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), cpu_vsrh(xB(ctx
->opcode
)));
7103 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), cpu_vsrl(xB(ctx
->opcode
)));
7112 #define SGN_MASK_DP 0x8000000000000000ull
7113 #define SGN_MASK_SP 0x8000000080000000ull
7115 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7116 static void glue(gen_, name)(DisasContext * ctx) \
7119 if (unlikely(!ctx->vsx_enabled)) { \
7120 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7123 xb = tcg_temp_new_i64(); \
7124 sgm = tcg_temp_new_i64(); \
7125 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7126 tcg_gen_movi_i64(sgm, sgn_mask); \
7129 tcg_gen_andc_i64(xb, xb, sgm); \
7133 tcg_gen_or_i64(xb, xb, sgm); \
7137 tcg_gen_xor_i64(xb, xb, sgm); \
7141 TCGv_i64 xa = tcg_temp_new_i64(); \
7142 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7143 tcg_gen_and_i64(xa, xa, sgm); \
7144 tcg_gen_andc_i64(xb, xb, sgm); \
7145 tcg_gen_or_i64(xb, xb, xa); \
7146 tcg_temp_free_i64(xa); \
7150 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7151 tcg_temp_free_i64(xb); \
7152 tcg_temp_free_i64(sgm); \
7155 VSX_SCALAR_MOVE(xsabsdp
, OP_ABS
, SGN_MASK_DP
)
7156 VSX_SCALAR_MOVE(xsnabsdp
, OP_NABS
, SGN_MASK_DP
)
7157 VSX_SCALAR_MOVE(xsnegdp
, OP_NEG
, SGN_MASK_DP
)
7158 VSX_SCALAR_MOVE(xscpsgndp
, OP_CPSGN
, SGN_MASK_DP
)
7160 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7161 static void glue(gen_, name)(DisasContext * ctx) \
7163 TCGv_i64 xbh, xbl, sgm; \
7164 if (unlikely(!ctx->vsx_enabled)) { \
7165 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7168 xbh = tcg_temp_new_i64(); \
7169 xbl = tcg_temp_new_i64(); \
7170 sgm = tcg_temp_new_i64(); \
7171 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7172 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7173 tcg_gen_movi_i64(sgm, sgn_mask); \
7176 tcg_gen_andc_i64(xbh, xbh, sgm); \
7177 tcg_gen_andc_i64(xbl, xbl, sgm); \
7181 tcg_gen_or_i64(xbh, xbh, sgm); \
7182 tcg_gen_or_i64(xbl, xbl, sgm); \
7186 tcg_gen_xor_i64(xbh, xbh, sgm); \
7187 tcg_gen_xor_i64(xbl, xbl, sgm); \
7191 TCGv_i64 xah = tcg_temp_new_i64(); \
7192 TCGv_i64 xal = tcg_temp_new_i64(); \
7193 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7194 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7195 tcg_gen_and_i64(xah, xah, sgm); \
7196 tcg_gen_and_i64(xal, xal, sgm); \
7197 tcg_gen_andc_i64(xbh, xbh, sgm); \
7198 tcg_gen_andc_i64(xbl, xbl, sgm); \
7199 tcg_gen_or_i64(xbh, xbh, xah); \
7200 tcg_gen_or_i64(xbl, xbl, xal); \
7201 tcg_temp_free_i64(xah); \
7202 tcg_temp_free_i64(xal); \
7206 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7207 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7208 tcg_temp_free_i64(xbh); \
7209 tcg_temp_free_i64(xbl); \
7210 tcg_temp_free_i64(sgm); \
7213 VSX_VECTOR_MOVE(xvabsdp
, OP_ABS
, SGN_MASK_DP
)
7214 VSX_VECTOR_MOVE(xvnabsdp
, OP_NABS
, SGN_MASK_DP
)
7215 VSX_VECTOR_MOVE(xvnegdp
, OP_NEG
, SGN_MASK_DP
)
7216 VSX_VECTOR_MOVE(xvcpsgndp
, OP_CPSGN
, SGN_MASK_DP
)
7217 VSX_VECTOR_MOVE(xvabssp
, OP_ABS
, SGN_MASK_SP
)
7218 VSX_VECTOR_MOVE(xvnabssp
, OP_NABS
, SGN_MASK_SP
)
7219 VSX_VECTOR_MOVE(xvnegsp
, OP_NEG
, SGN_MASK_SP
)
7220 VSX_VECTOR_MOVE(xvcpsgnsp
, OP_CPSGN
, SGN_MASK_SP
)
7222 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7223 static void gen_##name(DisasContext * ctx) \
7226 if (unlikely(!ctx->vsx_enabled)) { \
7227 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7230 /* NIP cannot be restored if the memory exception comes from an helper */ \
7231 gen_update_nip(ctx, ctx->nip - 4); \
7232 opc = tcg_const_i32(ctx->opcode); \
7233 gen_helper_##name(cpu_env, opc); \
7234 tcg_temp_free_i32(opc); \
7237 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7238 static void gen_##name(DisasContext * ctx) \
7240 if (unlikely(!ctx->vsx_enabled)) { \
7241 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7244 /* NIP cannot be restored if the exception comes */ \
7245 /* from a helper. */ \
7246 gen_update_nip(ctx, ctx->nip - 4); \
7248 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7249 cpu_vsrh(xB(ctx->opcode))); \
7252 GEN_VSX_HELPER_2(xsadddp
, 0x00, 0x04, 0, PPC2_VSX
)
7253 GEN_VSX_HELPER_2(xssubdp
, 0x00, 0x05, 0, PPC2_VSX
)
7254 GEN_VSX_HELPER_2(xsmuldp
, 0x00, 0x06, 0, PPC2_VSX
)
7255 GEN_VSX_HELPER_2(xsdivdp
, 0x00, 0x07, 0, PPC2_VSX
)
7256 GEN_VSX_HELPER_2(xsredp
, 0x14, 0x05, 0, PPC2_VSX
)
7257 GEN_VSX_HELPER_2(xssqrtdp
, 0x16, 0x04, 0, PPC2_VSX
)
7258 GEN_VSX_HELPER_2(xsrsqrtedp
, 0x14, 0x04, 0, PPC2_VSX
)
7259 GEN_VSX_HELPER_2(xstdivdp
, 0x14, 0x07, 0, PPC2_VSX
)
7260 GEN_VSX_HELPER_2(xstsqrtdp
, 0x14, 0x06, 0, PPC2_VSX
)
7261 GEN_VSX_HELPER_2(xsmaddadp
, 0x04, 0x04, 0, PPC2_VSX
)
7262 GEN_VSX_HELPER_2(xsmaddmdp
, 0x04, 0x05, 0, PPC2_VSX
)
7263 GEN_VSX_HELPER_2(xsmsubadp
, 0x04, 0x06, 0, PPC2_VSX
)
7264 GEN_VSX_HELPER_2(xsmsubmdp
, 0x04, 0x07, 0, PPC2_VSX
)
7265 GEN_VSX_HELPER_2(xsnmaddadp
, 0x04, 0x14, 0, PPC2_VSX
)
7266 GEN_VSX_HELPER_2(xsnmaddmdp
, 0x04, 0x15, 0, PPC2_VSX
)
7267 GEN_VSX_HELPER_2(xsnmsubadp
, 0x04, 0x16, 0, PPC2_VSX
)
7268 GEN_VSX_HELPER_2(xsnmsubmdp
, 0x04, 0x17, 0, PPC2_VSX
)
7269 GEN_VSX_HELPER_2(xscmpodp
, 0x0C, 0x05, 0, PPC2_VSX
)
7270 GEN_VSX_HELPER_2(xscmpudp
, 0x0C, 0x04, 0, PPC2_VSX
)
7271 GEN_VSX_HELPER_2(xsmaxdp
, 0x00, 0x14, 0, PPC2_VSX
)
7272 GEN_VSX_HELPER_2(xsmindp
, 0x00, 0x15, 0, PPC2_VSX
)
7273 GEN_VSX_HELPER_2(xscvdpsp
, 0x12, 0x10, 0, PPC2_VSX
)
7274 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn
, 0x16, 0x10, 0, PPC2_VSX207
)
7275 GEN_VSX_HELPER_2(xscvspdp
, 0x12, 0x14, 0, PPC2_VSX
)
7276 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn
, 0x16, 0x14, 0, PPC2_VSX207
)
7277 GEN_VSX_HELPER_2(xscvdpsxds
, 0x10, 0x15, 0, PPC2_VSX
)
7278 GEN_VSX_HELPER_2(xscvdpsxws
, 0x10, 0x05, 0, PPC2_VSX
)
7279 GEN_VSX_HELPER_2(xscvdpuxds
, 0x10, 0x14, 0, PPC2_VSX
)
7280 GEN_VSX_HELPER_2(xscvdpuxws
, 0x10, 0x04, 0, PPC2_VSX
)
7281 GEN_VSX_HELPER_2(xscvsxddp
, 0x10, 0x17, 0, PPC2_VSX
)
7282 GEN_VSX_HELPER_2(xscvuxddp
, 0x10, 0x16, 0, PPC2_VSX
)
7283 GEN_VSX_HELPER_2(xsrdpi
, 0x12, 0x04, 0, PPC2_VSX
)
7284 GEN_VSX_HELPER_2(xsrdpic
, 0x16, 0x06, 0, PPC2_VSX
)
7285 GEN_VSX_HELPER_2(xsrdpim
, 0x12, 0x07, 0, PPC2_VSX
)
7286 GEN_VSX_HELPER_2(xsrdpip
, 0x12, 0x06, 0, PPC2_VSX
)
7287 GEN_VSX_HELPER_2(xsrdpiz
, 0x12, 0x05, 0, PPC2_VSX
)
7288 GEN_VSX_HELPER_XT_XB_ENV(xsrsp
, 0x12, 0x11, 0, PPC2_VSX207
)
7290 GEN_VSX_HELPER_2(xsaddsp
, 0x00, 0x00, 0, PPC2_VSX207
)
7291 GEN_VSX_HELPER_2(xssubsp
, 0x00, 0x01, 0, PPC2_VSX207
)
7292 GEN_VSX_HELPER_2(xsmulsp
, 0x00, 0x02, 0, PPC2_VSX207
)
7293 GEN_VSX_HELPER_2(xsdivsp
, 0x00, 0x03, 0, PPC2_VSX207
)
7294 GEN_VSX_HELPER_2(xsresp
, 0x14, 0x01, 0, PPC2_VSX207
)
7295 GEN_VSX_HELPER_2(xssqrtsp
, 0x16, 0x00, 0, PPC2_VSX207
)
7296 GEN_VSX_HELPER_2(xsrsqrtesp
, 0x14, 0x00, 0, PPC2_VSX207
)
7297 GEN_VSX_HELPER_2(xsmaddasp
, 0x04, 0x00, 0, PPC2_VSX207
)
7298 GEN_VSX_HELPER_2(xsmaddmsp
, 0x04, 0x01, 0, PPC2_VSX207
)
7299 GEN_VSX_HELPER_2(xsmsubasp
, 0x04, 0x02, 0, PPC2_VSX207
)
7300 GEN_VSX_HELPER_2(xsmsubmsp
, 0x04, 0x03, 0, PPC2_VSX207
)
7301 GEN_VSX_HELPER_2(xsnmaddasp
, 0x04, 0x10, 0, PPC2_VSX207
)
7302 GEN_VSX_HELPER_2(xsnmaddmsp
, 0x04, 0x11, 0, PPC2_VSX207
)
7303 GEN_VSX_HELPER_2(xsnmsubasp
, 0x04, 0x12, 0, PPC2_VSX207
)
7304 GEN_VSX_HELPER_2(xsnmsubmsp
, 0x04, 0x13, 0, PPC2_VSX207
)
7305 GEN_VSX_HELPER_2(xscvsxdsp
, 0x10, 0x13, 0, PPC2_VSX207
)
7306 GEN_VSX_HELPER_2(xscvuxdsp
, 0x10, 0x12, 0, PPC2_VSX207
)
7308 GEN_VSX_HELPER_2(xvadddp
, 0x00, 0x0C, 0, PPC2_VSX
)
7309 GEN_VSX_HELPER_2(xvsubdp
, 0x00, 0x0D, 0, PPC2_VSX
)
7310 GEN_VSX_HELPER_2(xvmuldp
, 0x00, 0x0E, 0, PPC2_VSX
)
7311 GEN_VSX_HELPER_2(xvdivdp
, 0x00, 0x0F, 0, PPC2_VSX
)
7312 GEN_VSX_HELPER_2(xvredp
, 0x14, 0x0D, 0, PPC2_VSX
)
7313 GEN_VSX_HELPER_2(xvsqrtdp
, 0x16, 0x0C, 0, PPC2_VSX
)
7314 GEN_VSX_HELPER_2(xvrsqrtedp
, 0x14, 0x0C, 0, PPC2_VSX
)
7315 GEN_VSX_HELPER_2(xvtdivdp
, 0x14, 0x0F, 0, PPC2_VSX
)
7316 GEN_VSX_HELPER_2(xvtsqrtdp
, 0x14, 0x0E, 0, PPC2_VSX
)
7317 GEN_VSX_HELPER_2(xvmaddadp
, 0x04, 0x0C, 0, PPC2_VSX
)
7318 GEN_VSX_HELPER_2(xvmaddmdp
, 0x04, 0x0D, 0, PPC2_VSX
)
7319 GEN_VSX_HELPER_2(xvmsubadp
, 0x04, 0x0E, 0, PPC2_VSX
)
7320 GEN_VSX_HELPER_2(xvmsubmdp
, 0x04, 0x0F, 0, PPC2_VSX
)
7321 GEN_VSX_HELPER_2(xvnmaddadp
, 0x04, 0x1C, 0, PPC2_VSX
)
7322 GEN_VSX_HELPER_2(xvnmaddmdp
, 0x04, 0x1D, 0, PPC2_VSX
)
7323 GEN_VSX_HELPER_2(xvnmsubadp
, 0x04, 0x1E, 0, PPC2_VSX
)
7324 GEN_VSX_HELPER_2(xvnmsubmdp
, 0x04, 0x1F, 0, PPC2_VSX
)
7325 GEN_VSX_HELPER_2(xvmaxdp
, 0x00, 0x1C, 0, PPC2_VSX
)
7326 GEN_VSX_HELPER_2(xvmindp
, 0x00, 0x1D, 0, PPC2_VSX
)
7327 GEN_VSX_HELPER_2(xvcmpeqdp
, 0x0C, 0x0C, 0, PPC2_VSX
)
7328 GEN_VSX_HELPER_2(xvcmpgtdp
, 0x0C, 0x0D, 0, PPC2_VSX
)
7329 GEN_VSX_HELPER_2(xvcmpgedp
, 0x0C, 0x0E, 0, PPC2_VSX
)
7330 GEN_VSX_HELPER_2(xvcvdpsp
, 0x12, 0x18, 0, PPC2_VSX
)
7331 GEN_VSX_HELPER_2(xvcvdpsxds
, 0x10, 0x1D, 0, PPC2_VSX
)
7332 GEN_VSX_HELPER_2(xvcvdpsxws
, 0x10, 0x0D, 0, PPC2_VSX
)
7333 GEN_VSX_HELPER_2(xvcvdpuxds
, 0x10, 0x1C, 0, PPC2_VSX
)
7334 GEN_VSX_HELPER_2(xvcvdpuxws
, 0x10, 0x0C, 0, PPC2_VSX
)
7335 GEN_VSX_HELPER_2(xvcvsxddp
, 0x10, 0x1F, 0, PPC2_VSX
)
7336 GEN_VSX_HELPER_2(xvcvuxddp
, 0x10, 0x1E, 0, PPC2_VSX
)
7337 GEN_VSX_HELPER_2(xvcvsxwdp
, 0x10, 0x0F, 0, PPC2_VSX
)
7338 GEN_VSX_HELPER_2(xvcvuxwdp
, 0x10, 0x0E, 0, PPC2_VSX
)
7339 GEN_VSX_HELPER_2(xvrdpi
, 0x12, 0x0C, 0, PPC2_VSX
)
7340 GEN_VSX_HELPER_2(xvrdpic
, 0x16, 0x0E, 0, PPC2_VSX
)
7341 GEN_VSX_HELPER_2(xvrdpim
, 0x12, 0x0F, 0, PPC2_VSX
)
7342 GEN_VSX_HELPER_2(xvrdpip
, 0x12, 0x0E, 0, PPC2_VSX
)
7343 GEN_VSX_HELPER_2(xvrdpiz
, 0x12, 0x0D, 0, PPC2_VSX
)
7345 GEN_VSX_HELPER_2(xvaddsp
, 0x00, 0x08, 0, PPC2_VSX
)
7346 GEN_VSX_HELPER_2(xvsubsp
, 0x00, 0x09, 0, PPC2_VSX
)
7347 GEN_VSX_HELPER_2(xvmulsp
, 0x00, 0x0A, 0, PPC2_VSX
)
7348 GEN_VSX_HELPER_2(xvdivsp
, 0x00, 0x0B, 0, PPC2_VSX
)
7349 GEN_VSX_HELPER_2(xvresp
, 0x14, 0x09, 0, PPC2_VSX
)
7350 GEN_VSX_HELPER_2(xvsqrtsp
, 0x16, 0x08, 0, PPC2_VSX
)
7351 GEN_VSX_HELPER_2(xvrsqrtesp
, 0x14, 0x08, 0, PPC2_VSX
)
7352 GEN_VSX_HELPER_2(xvtdivsp
, 0x14, 0x0B, 0, PPC2_VSX
)
7353 GEN_VSX_HELPER_2(xvtsqrtsp
, 0x14, 0x0A, 0, PPC2_VSX
)
7354 GEN_VSX_HELPER_2(xvmaddasp
, 0x04, 0x08, 0, PPC2_VSX
)
7355 GEN_VSX_HELPER_2(xvmaddmsp
, 0x04, 0x09, 0, PPC2_VSX
)
7356 GEN_VSX_HELPER_2(xvmsubasp
, 0x04, 0x0A, 0, PPC2_VSX
)
7357 GEN_VSX_HELPER_2(xvmsubmsp
, 0x04, 0x0B, 0, PPC2_VSX
)
7358 GEN_VSX_HELPER_2(xvnmaddasp
, 0x04, 0x18, 0, PPC2_VSX
)
7359 GEN_VSX_HELPER_2(xvnmaddmsp
, 0x04, 0x19, 0, PPC2_VSX
)
7360 GEN_VSX_HELPER_2(xvnmsubasp
, 0x04, 0x1A, 0, PPC2_VSX
)
7361 GEN_VSX_HELPER_2(xvnmsubmsp
, 0x04, 0x1B, 0, PPC2_VSX
)
7362 GEN_VSX_HELPER_2(xvmaxsp
, 0x00, 0x18, 0, PPC2_VSX
)
7363 GEN_VSX_HELPER_2(xvminsp
, 0x00, 0x19, 0, PPC2_VSX
)
7364 GEN_VSX_HELPER_2(xvcmpeqsp
, 0x0C, 0x08, 0, PPC2_VSX
)
7365 GEN_VSX_HELPER_2(xvcmpgtsp
, 0x0C, 0x09, 0, PPC2_VSX
)
7366 GEN_VSX_HELPER_2(xvcmpgesp
, 0x0C, 0x0A, 0, PPC2_VSX
)
7367 GEN_VSX_HELPER_2(xvcvspdp
, 0x12, 0x1C, 0, PPC2_VSX
)
7368 GEN_VSX_HELPER_2(xvcvspsxds
, 0x10, 0x19, 0, PPC2_VSX
)
7369 GEN_VSX_HELPER_2(xvcvspsxws
, 0x10, 0x09, 0, PPC2_VSX
)
7370 GEN_VSX_HELPER_2(xvcvspuxds
, 0x10, 0x18, 0, PPC2_VSX
)
7371 GEN_VSX_HELPER_2(xvcvspuxws
, 0x10, 0x08, 0, PPC2_VSX
)
7372 GEN_VSX_HELPER_2(xvcvsxdsp
, 0x10, 0x1B, 0, PPC2_VSX
)
7373 GEN_VSX_HELPER_2(xvcvuxdsp
, 0x10, 0x1A, 0, PPC2_VSX
)
7374 GEN_VSX_HELPER_2(xvcvsxwsp
, 0x10, 0x0B, 0, PPC2_VSX
)
7375 GEN_VSX_HELPER_2(xvcvuxwsp
, 0x10, 0x0A, 0, PPC2_VSX
)
7376 GEN_VSX_HELPER_2(xvrspi
, 0x12, 0x08, 0, PPC2_VSX
)
7377 GEN_VSX_HELPER_2(xvrspic
, 0x16, 0x0A, 0, PPC2_VSX
)
7378 GEN_VSX_HELPER_2(xvrspim
, 0x12, 0x0B, 0, PPC2_VSX
)
7379 GEN_VSX_HELPER_2(xvrspip
, 0x12, 0x0A, 0, PPC2_VSX
)
7380 GEN_VSX_HELPER_2(xvrspiz
, 0x12, 0x09, 0, PPC2_VSX
)
7382 #define VSX_LOGICAL(name, tcg_op) \
7383 static void glue(gen_, name)(DisasContext * ctx) \
7385 if (unlikely(!ctx->vsx_enabled)) { \
7386 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7389 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
7390 cpu_vsrh(xB(ctx->opcode))); \
7391 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
7392 cpu_vsrl(xB(ctx->opcode))); \
7395 VSX_LOGICAL(xxland
, tcg_gen_and_i64
)
7396 VSX_LOGICAL(xxlandc
, tcg_gen_andc_i64
)
7397 VSX_LOGICAL(xxlor
, tcg_gen_or_i64
)
7398 VSX_LOGICAL(xxlxor
, tcg_gen_xor_i64
)
7399 VSX_LOGICAL(xxlnor
, tcg_gen_nor_i64
)
7400 VSX_LOGICAL(xxleqv
, tcg_gen_eqv_i64
)
7401 VSX_LOGICAL(xxlnand
, tcg_gen_nand_i64
)
7402 VSX_LOGICAL(xxlorc
, tcg_gen_orc_i64
)
7404 #define VSX_XXMRG(name, high) \
7405 static void glue(gen_, name)(DisasContext * ctx) \
7407 TCGv_i64 a0, a1, b0, b1; \
7408 if (unlikely(!ctx->vsx_enabled)) { \
7409 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7412 a0 = tcg_temp_new_i64(); \
7413 a1 = tcg_temp_new_i64(); \
7414 b0 = tcg_temp_new_i64(); \
7415 b1 = tcg_temp_new_i64(); \
7417 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
7418 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
7419 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
7420 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
7422 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
7423 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
7424 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
7425 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
7427 tcg_gen_shri_i64(a0, a0, 32); \
7428 tcg_gen_shri_i64(b0, b0, 32); \
7429 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
7431 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
7433 tcg_temp_free_i64(a0); \
7434 tcg_temp_free_i64(a1); \
7435 tcg_temp_free_i64(b0); \
7436 tcg_temp_free_i64(b1); \
7439 VSX_XXMRG(xxmrghw
, 1)
7440 VSX_XXMRG(xxmrglw
, 0)
7442 static void gen_xxsel(DisasContext
* ctx
)
7445 if (unlikely(!ctx
->vsx_enabled
)) {
7446 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
7449 a
= tcg_temp_new_i64();
7450 b
= tcg_temp_new_i64();
7451 c
= tcg_temp_new_i64();
7453 tcg_gen_mov_i64(a
, cpu_vsrh(xA(ctx
->opcode
)));
7454 tcg_gen_mov_i64(b
, cpu_vsrh(xB(ctx
->opcode
)));
7455 tcg_gen_mov_i64(c
, cpu_vsrh(xC(ctx
->opcode
)));
7457 tcg_gen_and_i64(b
, b
, c
);
7458 tcg_gen_andc_i64(a
, a
, c
);
7459 tcg_gen_or_i64(cpu_vsrh(xT(ctx
->opcode
)), a
, b
);
7461 tcg_gen_mov_i64(a
, cpu_vsrl(xA(ctx
->opcode
)));
7462 tcg_gen_mov_i64(b
, cpu_vsrl(xB(ctx
->opcode
)));
7463 tcg_gen_mov_i64(c
, cpu_vsrl(xC(ctx
->opcode
)));
7465 tcg_gen_and_i64(b
, b
, c
);
7466 tcg_gen_andc_i64(a
, a
, c
);
7467 tcg_gen_or_i64(cpu_vsrl(xT(ctx
->opcode
)), a
, b
);
7469 tcg_temp_free_i64(a
);
7470 tcg_temp_free_i64(b
);
7471 tcg_temp_free_i64(c
);
7474 static void gen_xxspltw(DisasContext
*ctx
)
7477 TCGv_i64 vsr
= (UIM(ctx
->opcode
) & 2) ?
7478 cpu_vsrl(xB(ctx
->opcode
)) :
7479 cpu_vsrh(xB(ctx
->opcode
));
7481 if (unlikely(!ctx
->vsx_enabled
)) {
7482 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
7486 b
= tcg_temp_new_i64();
7487 b2
= tcg_temp_new_i64();
7489 if (UIM(ctx
->opcode
) & 1) {
7490 tcg_gen_ext32u_i64(b
, vsr
);
7492 tcg_gen_shri_i64(b
, vsr
, 32);
7495 tcg_gen_shli_i64(b2
, b
, 32);
7496 tcg_gen_or_i64(cpu_vsrh(xT(ctx
->opcode
)), b
, b2
);
7497 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), cpu_vsrh(xT(ctx
->opcode
)));
7499 tcg_temp_free_i64(b
);
7500 tcg_temp_free_i64(b2
);
7503 static void gen_xxsldwi(DisasContext
*ctx
)
7506 if (unlikely(!ctx
->vsx_enabled
)) {
7507 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
7510 xth
= tcg_temp_new_i64();
7511 xtl
= tcg_temp_new_i64();
7513 switch (SHW(ctx
->opcode
)) {
7515 tcg_gen_mov_i64(xth
, cpu_vsrh(xA(ctx
->opcode
)));
7516 tcg_gen_mov_i64(xtl
, cpu_vsrl(xA(ctx
->opcode
)));
7520 TCGv_i64 t0
= tcg_temp_new_i64();
7521 tcg_gen_mov_i64(xth
, cpu_vsrh(xA(ctx
->opcode
)));
7522 tcg_gen_shli_i64(xth
, xth
, 32);
7523 tcg_gen_mov_i64(t0
, cpu_vsrl(xA(ctx
->opcode
)));
7524 tcg_gen_shri_i64(t0
, t0
, 32);
7525 tcg_gen_or_i64(xth
, xth
, t0
);
7526 tcg_gen_mov_i64(xtl
, cpu_vsrl(xA(ctx
->opcode
)));
7527 tcg_gen_shli_i64(xtl
, xtl
, 32);
7528 tcg_gen_mov_i64(t0
, cpu_vsrh(xB(ctx
->opcode
)));
7529 tcg_gen_shri_i64(t0
, t0
, 32);
7530 tcg_gen_or_i64(xtl
, xtl
, t0
);
7531 tcg_temp_free_i64(t0
);
7535 tcg_gen_mov_i64(xth
, cpu_vsrl(xA(ctx
->opcode
)));
7536 tcg_gen_mov_i64(xtl
, cpu_vsrh(xB(ctx
->opcode
)));
7540 TCGv_i64 t0
= tcg_temp_new_i64();
7541 tcg_gen_mov_i64(xth
, cpu_vsrl(xA(ctx
->opcode
)));
7542 tcg_gen_shli_i64(xth
, xth
, 32);
7543 tcg_gen_mov_i64(t0
, cpu_vsrh(xB(ctx
->opcode
)));
7544 tcg_gen_shri_i64(t0
, t0
, 32);
7545 tcg_gen_or_i64(xth
, xth
, t0
);
7546 tcg_gen_mov_i64(xtl
, cpu_vsrh(xB(ctx
->opcode
)));
7547 tcg_gen_shli_i64(xtl
, xtl
, 32);
7548 tcg_gen_mov_i64(t0
, cpu_vsrl(xB(ctx
->opcode
)));
7549 tcg_gen_shri_i64(t0
, t0
, 32);
7550 tcg_gen_or_i64(xtl
, xtl
, t0
);
7551 tcg_temp_free_i64(t0
);
7556 tcg_gen_mov_i64(cpu_vsrh(xT(ctx
->opcode
)), xth
);
7557 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), xtl
);
7559 tcg_temp_free_i64(xth
);
7560 tcg_temp_free_i64(xtl
);
7563 /*** Decimal Floating Point ***/
7565 static inline TCGv_ptr
gen_fprp_ptr(int reg
)
7567 TCGv_ptr r
= tcg_temp_new_ptr();
7568 tcg_gen_addi_ptr(r
, cpu_env
, offsetof(CPUPPCState
, fpr
[reg
]));
7572 #define GEN_DFP_T_A_B_Rc(name) \
7573 static void gen_##name(DisasContext *ctx) \
7575 TCGv_ptr rd, ra, rb; \
7576 if (unlikely(!ctx->fpu_enabled)) { \
7577 gen_exception(ctx, POWERPC_EXCP_FPU); \
7580 gen_update_nip(ctx, ctx->nip - 4); \
7581 rd = gen_fprp_ptr(rD(ctx->opcode)); \
7582 ra = gen_fprp_ptr(rA(ctx->opcode)); \
7583 rb = gen_fprp_ptr(rB(ctx->opcode)); \
7584 gen_helper_##name(cpu_env, rd, ra, rb); \
7585 if (unlikely(Rc(ctx->opcode) != 0)) { \
7586 gen_set_cr1_from_fpscr(ctx); \
7588 tcg_temp_free_ptr(rd); \
7589 tcg_temp_free_ptr(ra); \
7590 tcg_temp_free_ptr(rb); \
7593 #define GEN_DFP_BF_A_B(name) \
7594 static void gen_##name(DisasContext *ctx) \
7597 if (unlikely(!ctx->fpu_enabled)) { \
7598 gen_exception(ctx, POWERPC_EXCP_FPU); \
7601 gen_update_nip(ctx, ctx->nip - 4); \
7602 ra = gen_fprp_ptr(rA(ctx->opcode)); \
7603 rb = gen_fprp_ptr(rB(ctx->opcode)); \
7604 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7606 tcg_temp_free_ptr(ra); \
7607 tcg_temp_free_ptr(rb); \
7610 #define GEN_DFP_BF_A_DCM(name) \
7611 static void gen_##name(DisasContext *ctx) \
7615 if (unlikely(!ctx->fpu_enabled)) { \
7616 gen_exception(ctx, POWERPC_EXCP_FPU); \
7619 gen_update_nip(ctx, ctx->nip - 4); \
7620 ra = gen_fprp_ptr(rA(ctx->opcode)); \
7621 dcm = tcg_const_i32(DCM(ctx->opcode)); \
7622 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7623 cpu_env, ra, dcm); \
7624 tcg_temp_free_ptr(ra); \
7625 tcg_temp_free_i32(dcm); \
7628 #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
7629 static void gen_##name(DisasContext *ctx) \
7632 TCGv_i32 u32_1, u32_2; \
7633 if (unlikely(!ctx->fpu_enabled)) { \
7634 gen_exception(ctx, POWERPC_EXCP_FPU); \
7637 gen_update_nip(ctx, ctx->nip - 4); \
7638 rt = gen_fprp_ptr(rD(ctx->opcode)); \
7639 rb = gen_fprp_ptr(rB(ctx->opcode)); \
7640 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
7641 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
7642 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
7643 if (unlikely(Rc(ctx->opcode) != 0)) { \
7644 gen_set_cr1_from_fpscr(ctx); \
7646 tcg_temp_free_ptr(rt); \
7647 tcg_temp_free_ptr(rb); \
7648 tcg_temp_free_i32(u32_1); \
7649 tcg_temp_free_i32(u32_2); \
7652 #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
7653 static void gen_##name(DisasContext *ctx) \
7655 TCGv_ptr rt, ra, rb; \
7657 if (unlikely(!ctx->fpu_enabled)) { \
7658 gen_exception(ctx, POWERPC_EXCP_FPU); \
7661 gen_update_nip(ctx, ctx->nip - 4); \
7662 rt = gen_fprp_ptr(rD(ctx->opcode)); \
7663 ra = gen_fprp_ptr(rA(ctx->opcode)); \
7664 rb = gen_fprp_ptr(rB(ctx->opcode)); \
7665 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
7666 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
7667 if (unlikely(Rc(ctx->opcode) != 0)) { \
7668 gen_set_cr1_from_fpscr(ctx); \
7670 tcg_temp_free_ptr(rt); \
7671 tcg_temp_free_ptr(rb); \
7672 tcg_temp_free_ptr(ra); \
7673 tcg_temp_free_i32(i32); \
7676 #define GEN_DFP_T_B_Rc(name) \
7677 static void gen_##name(DisasContext *ctx) \
7680 if (unlikely(!ctx->fpu_enabled)) { \
7681 gen_exception(ctx, POWERPC_EXCP_FPU); \
7684 gen_update_nip(ctx, ctx->nip - 4); \
7685 rt = gen_fprp_ptr(rD(ctx->opcode)); \
7686 rb = gen_fprp_ptr(rB(ctx->opcode)); \
7687 gen_helper_##name(cpu_env, rt, rb); \
7688 if (unlikely(Rc(ctx->opcode) != 0)) { \
7689 gen_set_cr1_from_fpscr(ctx); \
7691 tcg_temp_free_ptr(rt); \
7692 tcg_temp_free_ptr(rb); \
7695 #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
7696 static void gen_##name(DisasContext *ctx) \
7700 if (unlikely(!ctx->fpu_enabled)) { \
7701 gen_exception(ctx, POWERPC_EXCP_FPU); \
7704 gen_update_nip(ctx, ctx->nip - 4); \
7705 rt = gen_fprp_ptr(rD(ctx->opcode)); \
7706 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
7707 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
7708 gen_helper_##name(cpu_env, rt, rs, i32); \
7709 if (unlikely(Rc(ctx->opcode) != 0)) { \
7710 gen_set_cr1_from_fpscr(ctx); \
7712 tcg_temp_free_ptr(rt); \
7713 tcg_temp_free_ptr(rs); \
7714 tcg_temp_free_i32(i32); \
7717 GEN_DFP_T_A_B_Rc(dadd
)
7718 GEN_DFP_T_A_B_Rc(daddq
)
7719 GEN_DFP_T_A_B_Rc(dsub
)
7720 GEN_DFP_T_A_B_Rc(dsubq
)
7721 GEN_DFP_T_A_B_Rc(dmul
)
7722 GEN_DFP_T_A_B_Rc(dmulq
)
7723 GEN_DFP_T_A_B_Rc(ddiv
)
7724 GEN_DFP_T_A_B_Rc(ddivq
)
7725 GEN_DFP_BF_A_B(dcmpu
)
7726 GEN_DFP_BF_A_B(dcmpuq
)
7727 GEN_DFP_BF_A_B(dcmpo
)
7728 GEN_DFP_BF_A_B(dcmpoq
)
7729 GEN_DFP_BF_A_DCM(dtstdc
)
7730 GEN_DFP_BF_A_DCM(dtstdcq
)
7731 GEN_DFP_BF_A_DCM(dtstdg
)
7732 GEN_DFP_BF_A_DCM(dtstdgq
)
7733 GEN_DFP_BF_A_B(dtstex
)
7734 GEN_DFP_BF_A_B(dtstexq
)
7735 GEN_DFP_BF_A_B(dtstsf
)
7736 GEN_DFP_BF_A_B(dtstsfq
)
7737 GEN_DFP_T_B_U32_U32_Rc(dquai
, SIMM5
, RMC
)
7738 GEN_DFP_T_B_U32_U32_Rc(dquaiq
, SIMM5
, RMC
)
7739 GEN_DFP_T_A_B_I32_Rc(dqua
, RMC
)
7740 GEN_DFP_T_A_B_I32_Rc(dquaq
, RMC
)
7741 GEN_DFP_T_A_B_I32_Rc(drrnd
, RMC
)
7742 GEN_DFP_T_A_B_I32_Rc(drrndq
, RMC
)
7743 GEN_DFP_T_B_U32_U32_Rc(drintx
, FPW
, RMC
)
7744 GEN_DFP_T_B_U32_U32_Rc(drintxq
, FPW
, RMC
)
7745 GEN_DFP_T_B_U32_U32_Rc(drintn
, FPW
, RMC
)
7746 GEN_DFP_T_B_U32_U32_Rc(drintnq
, FPW
, RMC
)
7747 GEN_DFP_T_B_Rc(dctdp
)
7748 GEN_DFP_T_B_Rc(dctqpq
)
7749 GEN_DFP_T_B_Rc(drsp
)
7750 GEN_DFP_T_B_Rc(drdpq
)
7751 GEN_DFP_T_B_Rc(dcffix
)
7752 GEN_DFP_T_B_Rc(dcffixq
)
7753 GEN_DFP_T_B_Rc(dctfix
)
7754 GEN_DFP_T_B_Rc(dctfixq
)
7755 GEN_DFP_T_FPR_I32_Rc(ddedpd
, rB
, SP
)
7756 GEN_DFP_T_FPR_I32_Rc(ddedpdq
, rB
, SP
)
7757 GEN_DFP_T_FPR_I32_Rc(denbcd
, rB
, SP
)
7758 GEN_DFP_T_FPR_I32_Rc(denbcdq
, rB
, SP
)
7759 GEN_DFP_T_B_Rc(dxex
)
7760 GEN_DFP_T_B_Rc(dxexq
)
7761 GEN_DFP_T_A_B_Rc(diex
)
7762 GEN_DFP_T_A_B_Rc(diexq
)
7763 GEN_DFP_T_FPR_I32_Rc(dscli
, rA
, DCM
)
7764 GEN_DFP_T_FPR_I32_Rc(dscliq
, rA
, DCM
)
7765 GEN_DFP_T_FPR_I32_Rc(dscri
, rA
, DCM
)
7766 GEN_DFP_T_FPR_I32_Rc(dscriq
, rA
, DCM
)
7768 /*** SPE extension ***/
7769 /* Register moves */
7771 static inline void gen_evmra(DisasContext
*ctx
)
7774 if (unlikely(!ctx
->spe_enabled
)) {
7775 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7779 TCGv_i64 tmp
= tcg_temp_new_i64();
7781 /* tmp := rA_lo + rA_hi << 32 */
7782 tcg_gen_concat_tl_i64(tmp
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
7784 /* spe_acc := tmp */
7785 tcg_gen_st_i64(tmp
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
7786 tcg_temp_free_i64(tmp
);
7789 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
7790 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
7793 static inline void gen_load_gpr64(TCGv_i64 t
, int reg
)
7795 tcg_gen_concat_tl_i64(t
, cpu_gpr
[reg
], cpu_gprh
[reg
]);
7798 static inline void gen_store_gpr64(int reg
, TCGv_i64 t
)
7800 tcg_gen_extr_i64_tl(cpu_gpr
[reg
], cpu_gprh
[reg
], t
);
7803 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
7804 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7806 if (Rc(ctx->opcode)) \
7812 /* Handler for undefined SPE opcodes */
7813 static inline void gen_speundef(DisasContext
*ctx
)
7815 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
7819 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
7820 static inline void gen_##name(DisasContext *ctx) \
7822 if (unlikely(!ctx->spe_enabled)) { \
7823 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7826 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7827 cpu_gpr[rB(ctx->opcode)]); \
7828 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7829 cpu_gprh[rB(ctx->opcode)]); \
7832 GEN_SPEOP_LOGIC2(evand
, tcg_gen_and_tl
);
7833 GEN_SPEOP_LOGIC2(evandc
, tcg_gen_andc_tl
);
7834 GEN_SPEOP_LOGIC2(evxor
, tcg_gen_xor_tl
);
7835 GEN_SPEOP_LOGIC2(evor
, tcg_gen_or_tl
);
7836 GEN_SPEOP_LOGIC2(evnor
, tcg_gen_nor_tl
);
7837 GEN_SPEOP_LOGIC2(eveqv
, tcg_gen_eqv_tl
);
7838 GEN_SPEOP_LOGIC2(evorc
, tcg_gen_orc_tl
);
7839 GEN_SPEOP_LOGIC2(evnand
, tcg_gen_nand_tl
);
7841 /* SPE logic immediate */
7842 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
7843 static inline void gen_##name(DisasContext *ctx) \
7846 if (unlikely(!ctx->spe_enabled)) { \
7847 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7850 t0 = tcg_temp_new_i32(); \
7852 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7853 tcg_opi(t0, t0, rB(ctx->opcode)); \
7854 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
7856 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
7857 tcg_opi(t0, t0, rB(ctx->opcode)); \
7858 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
7860 tcg_temp_free_i32(t0); \
7862 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi
, tcg_gen_shli_i32
);
7863 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu
, tcg_gen_shri_i32
);
7864 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis
, tcg_gen_sari_i32
);
7865 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi
, tcg_gen_rotli_i32
);
7867 /* SPE arithmetic */
7868 #define GEN_SPEOP_ARITH1(name, tcg_op) \
7869 static inline void gen_##name(DisasContext *ctx) \
7872 if (unlikely(!ctx->spe_enabled)) { \
7873 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7876 t0 = tcg_temp_new_i32(); \
7878 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7880 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
7882 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
7884 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
7886 tcg_temp_free_i32(t0); \
7889 static inline void gen_op_evabs(TCGv_i32 ret
, TCGv_i32 arg1
)
7891 TCGLabel
*l1
= gen_new_label();
7892 TCGLabel
*l2
= gen_new_label();
7894 tcg_gen_brcondi_i32(TCG_COND_GE
, arg1
, 0, l1
);
7895 tcg_gen_neg_i32(ret
, arg1
);
7898 tcg_gen_mov_i32(ret
, arg1
);
7901 GEN_SPEOP_ARITH1(evabs
, gen_op_evabs
);
7902 GEN_SPEOP_ARITH1(evneg
, tcg_gen_neg_i32
);
7903 GEN_SPEOP_ARITH1(evextsb
, tcg_gen_ext8s_i32
);
7904 GEN_SPEOP_ARITH1(evextsh
, tcg_gen_ext16s_i32
);
7905 static inline void gen_op_evrndw(TCGv_i32 ret
, TCGv_i32 arg1
)
7907 tcg_gen_addi_i32(ret
, arg1
, 0x8000);
7908 tcg_gen_ext16u_i32(ret
, ret
);
7910 GEN_SPEOP_ARITH1(evrndw
, gen_op_evrndw
);
7911 GEN_SPEOP_ARITH1(evcntlsw
, gen_helper_cntlsw32
);
7912 GEN_SPEOP_ARITH1(evcntlzw
, gen_helper_cntlzw32
);
7914 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7915 static inline void gen_##name(DisasContext *ctx) \
7918 if (unlikely(!ctx->spe_enabled)) { \
7919 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7922 t0 = tcg_temp_new_i32(); \
7923 t1 = tcg_temp_new_i32(); \
7925 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7926 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7927 tcg_op(t0, t0, t1); \
7928 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
7930 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
7931 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
7932 tcg_op(t0, t0, t1); \
7933 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
7935 tcg_temp_free_i32(t0); \
7936 tcg_temp_free_i32(t1); \
7939 static inline void gen_op_evsrwu(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
7941 TCGLabel
*l1
= gen_new_label();
7942 TCGLabel
*l2
= gen_new_label();
7943 TCGv_i32 t0
= tcg_temp_local_new_i32();
7945 /* No error here: 6 bits are used */
7946 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
7947 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
7948 tcg_gen_shr_i32(ret
, arg1
, t0
);
7951 tcg_gen_movi_i32(ret
, 0);
7953 tcg_temp_free_i32(t0
);
7955 GEN_SPEOP_ARITH2(evsrwu
, gen_op_evsrwu
);
7956 static inline void gen_op_evsrws(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
7958 TCGLabel
*l1
= gen_new_label();
7959 TCGLabel
*l2
= gen_new_label();
7960 TCGv_i32 t0
= tcg_temp_local_new_i32();
7962 /* No error here: 6 bits are used */
7963 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
7964 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
7965 tcg_gen_sar_i32(ret
, arg1
, t0
);
7968 tcg_gen_movi_i32(ret
, 0);
7970 tcg_temp_free_i32(t0
);
7972 GEN_SPEOP_ARITH2(evsrws
, gen_op_evsrws
);
7973 static inline void gen_op_evslw(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
7975 TCGLabel
*l1
= gen_new_label();
7976 TCGLabel
*l2
= gen_new_label();
7977 TCGv_i32 t0
= tcg_temp_local_new_i32();
7979 /* No error here: 6 bits are used */
7980 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
7981 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
7982 tcg_gen_shl_i32(ret
, arg1
, t0
);
7985 tcg_gen_movi_i32(ret
, 0);
7987 tcg_temp_free_i32(t0
);
7989 GEN_SPEOP_ARITH2(evslw
, gen_op_evslw
);
7990 static inline void gen_op_evrlw(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
7992 TCGv_i32 t0
= tcg_temp_new_i32();
7993 tcg_gen_andi_i32(t0
, arg2
, 0x1F);
7994 tcg_gen_rotl_i32(ret
, arg1
, t0
);
7995 tcg_temp_free_i32(t0
);
7997 GEN_SPEOP_ARITH2(evrlw
, gen_op_evrlw
);
7998 static inline void gen_evmergehi(DisasContext
*ctx
)
8000 if (unlikely(!ctx
->spe_enabled
)) {
8001 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8004 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
8005 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
8007 GEN_SPEOP_ARITH2(evaddw
, tcg_gen_add_i32
);
8008 static inline void gen_op_evsubf(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
8010 tcg_gen_sub_i32(ret
, arg2
, arg1
);
8012 GEN_SPEOP_ARITH2(evsubfw
, gen_op_evsubf
);
8014 /* SPE arithmetic immediate */
8015 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8016 static inline void gen_##name(DisasContext *ctx) \
8019 if (unlikely(!ctx->spe_enabled)) { \
8020 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8023 t0 = tcg_temp_new_i32(); \
8025 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8026 tcg_op(t0, t0, rA(ctx->opcode)); \
8027 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8029 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8030 tcg_op(t0, t0, rA(ctx->opcode)); \
8031 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8033 tcg_temp_free_i32(t0); \
8035 GEN_SPEOP_ARITH_IMM2(evaddiw
, tcg_gen_addi_i32
);
8036 GEN_SPEOP_ARITH_IMM2(evsubifw
, tcg_gen_subi_i32
);
8038 /* SPE comparison */
8039 #define GEN_SPEOP_COMP(name, tcg_cond) \
8040 static inline void gen_##name(DisasContext *ctx) \
8042 if (unlikely(!ctx->spe_enabled)) { \
8043 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8046 TCGLabel *l1 = gen_new_label(); \
8047 TCGLabel *l2 = gen_new_label(); \
8048 TCGLabel *l3 = gen_new_label(); \
8049 TCGLabel *l4 = gen_new_label(); \
8051 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8052 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8053 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8054 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8056 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8057 cpu_gpr[rB(ctx->opcode)], l1); \
8058 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8060 gen_set_label(l1); \
8061 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8062 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8063 gen_set_label(l2); \
8064 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8065 cpu_gprh[rB(ctx->opcode)], l3); \
8066 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8067 ~(CRF_CH | CRF_CH_AND_CL)); \
8069 gen_set_label(l3); \
8070 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8071 CRF_CH | CRF_CH_OR_CL); \
8072 gen_set_label(l4); \
8074 GEN_SPEOP_COMP(evcmpgtu
, TCG_COND_GTU
);
8075 GEN_SPEOP_COMP(evcmpgts
, TCG_COND_GT
);
8076 GEN_SPEOP_COMP(evcmpltu
, TCG_COND_LTU
);
8077 GEN_SPEOP_COMP(evcmplts
, TCG_COND_LT
);
8078 GEN_SPEOP_COMP(evcmpeq
, TCG_COND_EQ
);
8081 static inline void gen_brinc(DisasContext
*ctx
)
8083 /* Note: brinc is usable even if SPE is disabled */
8084 gen_helper_brinc(cpu_gpr
[rD(ctx
->opcode
)],
8085 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
8087 static inline void gen_evmergelo(DisasContext
*ctx
)
8089 if (unlikely(!ctx
->spe_enabled
)) {
8090 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8093 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8094 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
8096 static inline void gen_evmergehilo(DisasContext
*ctx
)
8098 if (unlikely(!ctx
->spe_enabled
)) {
8099 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8102 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
8103 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
8105 static inline void gen_evmergelohi(DisasContext
*ctx
)
8107 if (unlikely(!ctx
->spe_enabled
)) {
8108 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8111 if (rD(ctx
->opcode
) == rA(ctx
->opcode
)) {
8112 TCGv tmp
= tcg_temp_new();
8113 tcg_gen_mov_tl(tmp
, cpu_gpr
[rA(ctx
->opcode
)]);
8114 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
8115 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], tmp
);
8118 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
8119 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8122 static inline void gen_evsplati(DisasContext
*ctx
)
8124 uint64_t imm
= ((int32_t)(rA(ctx
->opcode
) << 27)) >> 27;
8126 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], imm
);
8127 tcg_gen_movi_tl(cpu_gprh
[rD(ctx
->opcode
)], imm
);
8129 static inline void gen_evsplatfi(DisasContext
*ctx
)
8131 uint64_t imm
= rA(ctx
->opcode
) << 27;
8133 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], imm
);
8134 tcg_gen_movi_tl(cpu_gprh
[rD(ctx
->opcode
)], imm
);
8137 static inline void gen_evsel(DisasContext
*ctx
)
8139 TCGLabel
*l1
= gen_new_label();
8140 TCGLabel
*l2
= gen_new_label();
8141 TCGLabel
*l3
= gen_new_label();
8142 TCGLabel
*l4
= gen_new_label();
8143 TCGv_i32 t0
= tcg_temp_local_new_i32();
8145 tcg_gen_andi_i32(t0
, cpu_crf
[ctx
->opcode
& 0x07], 1 << 3);
8146 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l1
);
8147 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
8150 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
8152 tcg_gen_andi_i32(t0
, cpu_crf
[ctx
->opcode
& 0x07], 1 << 2);
8153 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l3
);
8154 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8157 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
8159 tcg_temp_free_i32(t0
);
8162 static void gen_evsel0(DisasContext
*ctx
)
8167 static void gen_evsel1(DisasContext
*ctx
)
8172 static void gen_evsel2(DisasContext
*ctx
)
8177 static void gen_evsel3(DisasContext
*ctx
)
8184 static inline void gen_evmwumi(DisasContext
*ctx
)
8188 if (unlikely(!ctx
->spe_enabled
)) {
8189 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8193 t0
= tcg_temp_new_i64();
8194 t1
= tcg_temp_new_i64();
8196 /* t0 := rA; t1 := rB */
8197 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
8198 tcg_gen_ext32u_i64(t0
, t0
);
8199 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
8200 tcg_gen_ext32u_i64(t1
, t1
);
8202 tcg_gen_mul_i64(t0
, t0
, t1
); /* t0 := rA * rB */
8204 gen_store_gpr64(rD(ctx
->opcode
), t0
); /* rD := t0 */
8206 tcg_temp_free_i64(t0
);
8207 tcg_temp_free_i64(t1
);
8210 static inline void gen_evmwumia(DisasContext
*ctx
)
8214 if (unlikely(!ctx
->spe_enabled
)) {
8215 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8219 gen_evmwumi(ctx
); /* rD := rA * rB */
8221 tmp
= tcg_temp_new_i64();
8224 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
8225 tcg_gen_st_i64(tmp
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
8226 tcg_temp_free_i64(tmp
);
8229 static inline void gen_evmwumiaa(DisasContext
*ctx
)
8234 if (unlikely(!ctx
->spe_enabled
)) {
8235 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8239 gen_evmwumi(ctx
); /* rD := rA * rB */
8241 acc
= tcg_temp_new_i64();
8242 tmp
= tcg_temp_new_i64();
8245 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
8248 tcg_gen_ld_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
8250 /* acc := tmp + acc */
8251 tcg_gen_add_i64(acc
, acc
, tmp
);
8254 tcg_gen_st_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
8257 gen_store_gpr64(rD(ctx
->opcode
), acc
);
8259 tcg_temp_free_i64(acc
);
8260 tcg_temp_free_i64(tmp
);
8263 static inline void gen_evmwsmi(DisasContext
*ctx
)
8267 if (unlikely(!ctx
->spe_enabled
)) {
8268 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8272 t0
= tcg_temp_new_i64();
8273 t1
= tcg_temp_new_i64();
8275 /* t0 := rA; t1 := rB */
8276 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
8277 tcg_gen_ext32s_i64(t0
, t0
);
8278 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
8279 tcg_gen_ext32s_i64(t1
, t1
);
8281 tcg_gen_mul_i64(t0
, t0
, t1
); /* t0 := rA * rB */
8283 gen_store_gpr64(rD(ctx
->opcode
), t0
); /* rD := t0 */
8285 tcg_temp_free_i64(t0
);
8286 tcg_temp_free_i64(t1
);
8289 static inline void gen_evmwsmia(DisasContext
*ctx
)
8293 gen_evmwsmi(ctx
); /* rD := rA * rB */
8295 tmp
= tcg_temp_new_i64();
8298 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
8299 tcg_gen_st_i64(tmp
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
8301 tcg_temp_free_i64(tmp
);
8304 static inline void gen_evmwsmiaa(DisasContext
*ctx
)
8306 TCGv_i64 acc
= tcg_temp_new_i64();
8307 TCGv_i64 tmp
= tcg_temp_new_i64();
8309 gen_evmwsmi(ctx
); /* rD := rA * rB */
8311 acc
= tcg_temp_new_i64();
8312 tmp
= tcg_temp_new_i64();
8315 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
8318 tcg_gen_ld_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
8320 /* acc := tmp + acc */
8321 tcg_gen_add_i64(acc
, acc
, tmp
);
8324 tcg_gen_st_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
8327 gen_store_gpr64(rD(ctx
->opcode
), acc
);
8329 tcg_temp_free_i64(acc
);
8330 tcg_temp_free_i64(tmp
);
8333 GEN_SPE(evaddw
, speundef
, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
8334 GEN_SPE(evaddiw
, speundef
, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
8335 GEN_SPE(evsubfw
, speundef
, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
8336 GEN_SPE(evsubifw
, speundef
, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
8337 GEN_SPE(evabs
, evneg
, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
); ////
8338 GEN_SPE(evextsb
, evextsh
, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
); ////
8339 GEN_SPE(evrndw
, evcntlzw
, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
); ////
8340 GEN_SPE(evcntlsw
, brinc
, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE
); //
8341 GEN_SPE(evmra
, speundef
, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE
);
8342 GEN_SPE(speundef
, evand
, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
); ////
8343 GEN_SPE(evandc
, speundef
, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
8344 GEN_SPE(evxor
, evor
, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
8345 GEN_SPE(evnor
, eveqv
, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
8346 GEN_SPE(evmwumi
, evmwsmi
, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
8347 GEN_SPE(evmwumia
, evmwsmia
, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
8348 GEN_SPE(evmwumiaa
, evmwsmiaa
, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE
);
8349 GEN_SPE(speundef
, evorc
, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
); ////
8350 GEN_SPE(evnand
, speundef
, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
8351 GEN_SPE(evsrwu
, evsrws
, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
8352 GEN_SPE(evsrwiu
, evsrwis
, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE
);
8353 GEN_SPE(evslw
, speundef
, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
8354 GEN_SPE(evslwi
, speundef
, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
8355 GEN_SPE(evrlw
, evsplati
, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE
); //
8356 GEN_SPE(evrlwi
, evsplatfi
, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE
);
8357 GEN_SPE(evmergehi
, evmergelo
, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
8358 GEN_SPE(evmergehilo
, evmergelohi
, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
8359 GEN_SPE(evcmpgtu
, evcmpgts
, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE
); ////
8360 GEN_SPE(evcmpltu
, evcmplts
, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE
); ////
8361 GEN_SPE(evcmpeq
, speundef
, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE
); ////
8363 /* SPE load and stores */
8364 static inline void gen_addr_spe_imm_index(DisasContext
*ctx
, TCGv EA
, int sh
)
8366 target_ulong uimm
= rB(ctx
->opcode
);
8368 if (rA(ctx
->opcode
) == 0) {
8369 tcg_gen_movi_tl(EA
, uimm
<< sh
);
8371 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], uimm
<< sh
);
8372 if (NARROW_MODE(ctx
)) {
8373 tcg_gen_ext32u_tl(EA
, EA
);
8378 static inline void gen_op_evldd(DisasContext
*ctx
, TCGv addr
)
8380 TCGv_i64 t0
= tcg_temp_new_i64();
8381 gen_qemu_ld64(ctx
, t0
, addr
);
8382 gen_store_gpr64(rD(ctx
->opcode
), t0
);
8383 tcg_temp_free_i64(t0
);
8386 static inline void gen_op_evldw(DisasContext
*ctx
, TCGv addr
)
8388 gen_qemu_ld32u(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
8389 gen_addr_add(ctx
, addr
, addr
, 4);
8390 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
8393 static inline void gen_op_evldh(DisasContext
*ctx
, TCGv addr
)
8395 TCGv t0
= tcg_temp_new();
8396 gen_qemu_ld16u(ctx
, t0
, addr
);
8397 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
8398 gen_addr_add(ctx
, addr
, addr
, 2);
8399 gen_qemu_ld16u(ctx
, t0
, addr
);
8400 tcg_gen_or_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
8401 gen_addr_add(ctx
, addr
, addr
, 2);
8402 gen_qemu_ld16u(ctx
, t0
, addr
);
8403 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
8404 gen_addr_add(ctx
, addr
, addr
, 2);
8405 gen_qemu_ld16u(ctx
, t0
, addr
);
8406 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
8410 static inline void gen_op_evlhhesplat(DisasContext
*ctx
, TCGv addr
)
8412 TCGv t0
= tcg_temp_new();
8413 gen_qemu_ld16u(ctx
, t0
, addr
);
8414 tcg_gen_shli_tl(t0
, t0
, 16);
8415 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
8416 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
8420 static inline void gen_op_evlhhousplat(DisasContext
*ctx
, TCGv addr
)
8422 TCGv t0
= tcg_temp_new();
8423 gen_qemu_ld16u(ctx
, t0
, addr
);
8424 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
8425 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
8429 static inline void gen_op_evlhhossplat(DisasContext
*ctx
, TCGv addr
)
8431 TCGv t0
= tcg_temp_new();
8432 gen_qemu_ld16s(ctx
, t0
, addr
);
8433 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
8434 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
8438 static inline void gen_op_evlwhe(DisasContext
*ctx
, TCGv addr
)
8440 TCGv t0
= tcg_temp_new();
8441 gen_qemu_ld16u(ctx
, t0
, addr
);
8442 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
8443 gen_addr_add(ctx
, addr
, addr
, 2);
8444 gen_qemu_ld16u(ctx
, t0
, addr
);
8445 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 16);
8449 static inline void gen_op_evlwhou(DisasContext
*ctx
, TCGv addr
)
8451 gen_qemu_ld16u(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
8452 gen_addr_add(ctx
, addr
, addr
, 2);
8453 gen_qemu_ld16u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
8456 static inline void gen_op_evlwhos(DisasContext
*ctx
, TCGv addr
)
8458 gen_qemu_ld16s(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
8459 gen_addr_add(ctx
, addr
, addr
, 2);
8460 gen_qemu_ld16s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
8463 static inline void gen_op_evlwwsplat(DisasContext
*ctx
, TCGv addr
)
8465 TCGv t0
= tcg_temp_new();
8466 gen_qemu_ld32u(ctx
, t0
, addr
);
8467 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
8468 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
8472 static inline void gen_op_evlwhsplat(DisasContext
*ctx
, TCGv addr
)
8474 TCGv t0
= tcg_temp_new();
8475 gen_qemu_ld16u(ctx
, t0
, addr
);
8476 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
8477 tcg_gen_or_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
8478 gen_addr_add(ctx
, addr
, addr
, 2);
8479 gen_qemu_ld16u(ctx
, t0
, addr
);
8480 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 16);
8481 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
8485 static inline void gen_op_evstdd(DisasContext
*ctx
, TCGv addr
)
8487 TCGv_i64 t0
= tcg_temp_new_i64();
8488 gen_load_gpr64(t0
, rS(ctx
->opcode
));
8489 gen_qemu_st64(ctx
, t0
, addr
);
8490 tcg_temp_free_i64(t0
);
8493 static inline void gen_op_evstdw(DisasContext
*ctx
, TCGv addr
)
8495 gen_qemu_st32(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
8496 gen_addr_add(ctx
, addr
, addr
, 4);
8497 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
8500 static inline void gen_op_evstdh(DisasContext
*ctx
, TCGv addr
)
8502 TCGv t0
= tcg_temp_new();
8503 tcg_gen_shri_tl(t0
, cpu_gprh
[rS(ctx
->opcode
)], 16);
8504 gen_qemu_st16(ctx
, t0
, addr
);
8505 gen_addr_add(ctx
, addr
, addr
, 2);
8506 gen_qemu_st16(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
8507 gen_addr_add(ctx
, addr
, addr
, 2);
8508 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 16);
8509 gen_qemu_st16(ctx
, t0
, addr
);
8511 gen_addr_add(ctx
, addr
, addr
, 2);
8512 gen_qemu_st16(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
8515 static inline void gen_op_evstwhe(DisasContext
*ctx
, TCGv addr
)
8517 TCGv t0
= tcg_temp_new();
8518 tcg_gen_shri_tl(t0
, cpu_gprh
[rS(ctx
->opcode
)], 16);
8519 gen_qemu_st16(ctx
, t0
, addr
);
8520 gen_addr_add(ctx
, addr
, addr
, 2);
8521 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 16);
8522 gen_qemu_st16(ctx
, t0
, addr
);
8526 static inline void gen_op_evstwho(DisasContext
*ctx
, TCGv addr
)
8528 gen_qemu_st16(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
8529 gen_addr_add(ctx
, addr
, addr
, 2);
8530 gen_qemu_st16(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
8533 static inline void gen_op_evstwwe(DisasContext
*ctx
, TCGv addr
)
8535 gen_qemu_st32(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
8538 static inline void gen_op_evstwwo(DisasContext
*ctx
, TCGv addr
)
8540 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
8543 #define GEN_SPEOP_LDST(name, opc2, sh) \
8544 static void glue(gen_, name)(DisasContext *ctx) \
8547 if (unlikely(!ctx->spe_enabled)) { \
8548 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8551 gen_set_access_type(ctx, ACCESS_INT); \
8552 t0 = tcg_temp_new(); \
8553 if (Rc(ctx->opcode)) { \
8554 gen_addr_spe_imm_index(ctx, t0, sh); \
8556 gen_addr_reg_index(ctx, t0); \
8558 gen_op_##name(ctx, t0); \
8559 tcg_temp_free(t0); \
8562 GEN_SPEOP_LDST(evldd
, 0x00, 3);
8563 GEN_SPEOP_LDST(evldw
, 0x01, 3);
8564 GEN_SPEOP_LDST(evldh
, 0x02, 3);
8565 GEN_SPEOP_LDST(evlhhesplat
, 0x04, 1);
8566 GEN_SPEOP_LDST(evlhhousplat
, 0x06, 1);
8567 GEN_SPEOP_LDST(evlhhossplat
, 0x07, 1);
8568 GEN_SPEOP_LDST(evlwhe
, 0x08, 2);
8569 GEN_SPEOP_LDST(evlwhou
, 0x0A, 2);
8570 GEN_SPEOP_LDST(evlwhos
, 0x0B, 2);
8571 GEN_SPEOP_LDST(evlwwsplat
, 0x0C, 2);
8572 GEN_SPEOP_LDST(evlwhsplat
, 0x0E, 2);
8574 GEN_SPEOP_LDST(evstdd
, 0x10, 3);
8575 GEN_SPEOP_LDST(evstdw
, 0x11, 3);
8576 GEN_SPEOP_LDST(evstdh
, 0x12, 3);
8577 GEN_SPEOP_LDST(evstwhe
, 0x18, 2);
8578 GEN_SPEOP_LDST(evstwho
, 0x1A, 2);
8579 GEN_SPEOP_LDST(evstwwe
, 0x1C, 2);
8580 GEN_SPEOP_LDST(evstwwo
, 0x1E, 2);
8582 /* Multiply and add - TODO */
8584 GEN_SPE(speundef
, evmhessf
, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);//
8585 GEN_SPE(speundef
, evmhossf
, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8586 GEN_SPE(evmheumi
, evmhesmi
, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
8587 GEN_SPE(speundef
, evmhesmf
, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8588 GEN_SPE(evmhoumi
, evmhosmi
, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
8589 GEN_SPE(speundef
, evmhosmf
, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8590 GEN_SPE(speundef
, evmhessfa
, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8591 GEN_SPE(speundef
, evmhossfa
, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8592 GEN_SPE(evmheumia
, evmhesmia
, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
8593 GEN_SPE(speundef
, evmhesmfa
, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8594 GEN_SPE(evmhoumia
, evmhosmia
, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
8595 GEN_SPE(speundef
, evmhosmfa
, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8597 GEN_SPE(speundef
, evmwhssf
, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8598 GEN_SPE(evmwlumi
, speundef
, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
8599 GEN_SPE(evmwhumi
, evmwhsmi
, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
8600 GEN_SPE(speundef
, evmwhsmf
, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8601 GEN_SPE(speundef
, evmwssf
, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8602 GEN_SPE(speundef
, evmwsmf
, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8603 GEN_SPE(speundef
, evmwhssfa
, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8604 GEN_SPE(evmwlumia
, speundef
, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
8605 GEN_SPE(evmwhumia
, evmwhsmia
, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
8606 GEN_SPE(speundef
, evmwhsmfa
, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8607 GEN_SPE(speundef
, evmwssfa
, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8608 GEN_SPE(speundef
, evmwsmfa
, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8610 GEN_SPE(evadduiaaw
, evaddsiaaw
, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
8611 GEN_SPE(evsubfusiaaw
, evsubfssiaaw
, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
8612 GEN_SPE(evaddumiaaw
, evaddsmiaaw
, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
8613 GEN_SPE(evsubfumiaaw
, evsubfsmiaaw
, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
8614 GEN_SPE(evdivws
, evdivwu
, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE
);
8616 GEN_SPE(evmheusiaaw
, evmhessiaaw
, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
8617 GEN_SPE(speundef
, evmhessfaaw
, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8618 GEN_SPE(evmhousiaaw
, evmhossiaaw
, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
8619 GEN_SPE(speundef
, evmhossfaaw
, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8620 GEN_SPE(evmheumiaaw
, evmhesmiaaw
, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
8621 GEN_SPE(speundef
, evmhesmfaaw
, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8622 GEN_SPE(evmhoumiaaw
, evmhosmiaaw
, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
8623 GEN_SPE(speundef
, evmhosmfaaw
, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8624 GEN_SPE(evmhegumiaa
, evmhegsmiaa
, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
8625 GEN_SPE(speundef
, evmhegsmfaa
, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8626 GEN_SPE(evmhogumiaa
, evmhogsmiaa
, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
8627 GEN_SPE(speundef
, evmhogsmfaa
, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8629 GEN_SPE(evmwlusiaaw
, evmwlssiaaw
, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE
);
8630 GEN_SPE(evmwlumiaaw
, evmwlsmiaaw
, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE
);
8631 GEN_SPE(speundef
, evmwssfaa
, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8632 GEN_SPE(speundef
, evmwsmfaa
, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8634 GEN_SPE(evmheusianw
, evmhessianw
, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
8635 GEN_SPE(speundef
, evmhessfanw
, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8636 GEN_SPE(evmhousianw
, evmhossianw
, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
8637 GEN_SPE(speundef
, evmhossfanw
, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8638 GEN_SPE(evmheumianw
, evmhesmianw
, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
8639 GEN_SPE(speundef
, evmhesmfanw
, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8640 GEN_SPE(evmhoumianw
, evmhosmianw
, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
8641 GEN_SPE(speundef
, evmhosmfanw
, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8642 GEN_SPE(evmhegumian
, evmhegsmian
, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
8643 GEN_SPE(speundef
, evmhegsmfan
, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8644 GEN_SPE(evmhigumian
, evmhigsmian
, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
8645 GEN_SPE(speundef
, evmhogsmfan
, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8647 GEN_SPE(evmwlusianw
, evmwlssianw
, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE
);
8648 GEN_SPE(evmwlumianw
, evmwlsmianw
, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE
);
8649 GEN_SPE(speundef
, evmwssfan
, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8650 GEN_SPE(evmwumian
, evmwsmian
, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE
);
8651 GEN_SPE(speundef
, evmwsmfan
, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8654 /*** SPE floating-point extension ***/
8655 #define GEN_SPEFPUOP_CONV_32_32(name) \
8656 static inline void gen_##name(DisasContext *ctx) \
8658 TCGv_i32 t0 = tcg_temp_new_i32(); \
8659 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8660 gen_helper_##name(t0, cpu_env, t0); \
8661 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8662 tcg_temp_free_i32(t0); \
8664 #define GEN_SPEFPUOP_CONV_32_64(name) \
8665 static inline void gen_##name(DisasContext *ctx) \
8667 TCGv_i64 t0 = tcg_temp_new_i64(); \
8668 TCGv_i32 t1 = tcg_temp_new_i32(); \
8669 gen_load_gpr64(t0, rB(ctx->opcode)); \
8670 gen_helper_##name(t1, cpu_env, t0); \
8671 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
8672 tcg_temp_free_i64(t0); \
8673 tcg_temp_free_i32(t1); \
8675 #define GEN_SPEFPUOP_CONV_64_32(name) \
8676 static inline void gen_##name(DisasContext *ctx) \
8678 TCGv_i64 t0 = tcg_temp_new_i64(); \
8679 TCGv_i32 t1 = tcg_temp_new_i32(); \
8680 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8681 gen_helper_##name(t0, cpu_env, t1); \
8682 gen_store_gpr64(rD(ctx->opcode), t0); \
8683 tcg_temp_free_i64(t0); \
8684 tcg_temp_free_i32(t1); \
8686 #define GEN_SPEFPUOP_CONV_64_64(name) \
8687 static inline void gen_##name(DisasContext *ctx) \
8689 TCGv_i64 t0 = tcg_temp_new_i64(); \
8690 gen_load_gpr64(t0, rB(ctx->opcode)); \
8691 gen_helper_##name(t0, cpu_env, t0); \
8692 gen_store_gpr64(rD(ctx->opcode), t0); \
8693 tcg_temp_free_i64(t0); \
8695 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8696 static inline void gen_##name(DisasContext *ctx) \
8699 if (unlikely(!ctx->spe_enabled)) { \
8700 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8703 t0 = tcg_temp_new_i32(); \
8704 t1 = tcg_temp_new_i32(); \
8705 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8706 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8707 gen_helper_##name(t0, cpu_env, t0, t1); \
8708 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8710 tcg_temp_free_i32(t0); \
8711 tcg_temp_free_i32(t1); \
8713 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8714 static inline void gen_##name(DisasContext *ctx) \
8717 if (unlikely(!ctx->spe_enabled)) { \
8718 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8721 t0 = tcg_temp_new_i64(); \
8722 t1 = tcg_temp_new_i64(); \
8723 gen_load_gpr64(t0, rA(ctx->opcode)); \
8724 gen_load_gpr64(t1, rB(ctx->opcode)); \
8725 gen_helper_##name(t0, cpu_env, t0, t1); \
8726 gen_store_gpr64(rD(ctx->opcode), t0); \
8727 tcg_temp_free_i64(t0); \
8728 tcg_temp_free_i64(t1); \
8730 #define GEN_SPEFPUOP_COMP_32(name) \
8731 static inline void gen_##name(DisasContext *ctx) \
8734 if (unlikely(!ctx->spe_enabled)) { \
8735 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8738 t0 = tcg_temp_new_i32(); \
8739 t1 = tcg_temp_new_i32(); \
8741 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8742 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8743 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8745 tcg_temp_free_i32(t0); \
8746 tcg_temp_free_i32(t1); \
8748 #define GEN_SPEFPUOP_COMP_64(name) \
8749 static inline void gen_##name(DisasContext *ctx) \
8752 if (unlikely(!ctx->spe_enabled)) { \
8753 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8756 t0 = tcg_temp_new_i64(); \
8757 t1 = tcg_temp_new_i64(); \
8758 gen_load_gpr64(t0, rA(ctx->opcode)); \
8759 gen_load_gpr64(t1, rB(ctx->opcode)); \
8760 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8761 tcg_temp_free_i64(t0); \
8762 tcg_temp_free_i64(t1); \
8765 /* Single precision floating-point vectors operations */
8767 GEN_SPEFPUOP_ARITH2_64_64(evfsadd
);
8768 GEN_SPEFPUOP_ARITH2_64_64(evfssub
);
8769 GEN_SPEFPUOP_ARITH2_64_64(evfsmul
);
8770 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv
);
8771 static inline void gen_evfsabs(DisasContext
*ctx
)
8773 if (unlikely(!ctx
->spe_enabled
)) {
8774 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8777 tcg_gen_andi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
8779 tcg_gen_andi_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
8782 static inline void gen_evfsnabs(DisasContext
*ctx
)
8784 if (unlikely(!ctx
->spe_enabled
)) {
8785 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8788 tcg_gen_ori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
8790 tcg_gen_ori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
8793 static inline void gen_evfsneg(DisasContext
*ctx
)
8795 if (unlikely(!ctx
->spe_enabled
)) {
8796 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8799 tcg_gen_xori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
8801 tcg_gen_xori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
8806 GEN_SPEFPUOP_CONV_64_64(evfscfui
);
8807 GEN_SPEFPUOP_CONV_64_64(evfscfsi
);
8808 GEN_SPEFPUOP_CONV_64_64(evfscfuf
);
8809 GEN_SPEFPUOP_CONV_64_64(evfscfsf
);
8810 GEN_SPEFPUOP_CONV_64_64(evfsctui
);
8811 GEN_SPEFPUOP_CONV_64_64(evfsctsi
);
8812 GEN_SPEFPUOP_CONV_64_64(evfsctuf
);
8813 GEN_SPEFPUOP_CONV_64_64(evfsctsf
);
8814 GEN_SPEFPUOP_CONV_64_64(evfsctuiz
);
8815 GEN_SPEFPUOP_CONV_64_64(evfsctsiz
);
8818 GEN_SPEFPUOP_COMP_64(evfscmpgt
);
8819 GEN_SPEFPUOP_COMP_64(evfscmplt
);
8820 GEN_SPEFPUOP_COMP_64(evfscmpeq
);
8821 GEN_SPEFPUOP_COMP_64(evfststgt
);
8822 GEN_SPEFPUOP_COMP_64(evfststlt
);
8823 GEN_SPEFPUOP_COMP_64(evfststeq
);
8825 /* Opcodes definitions */
8826 GEN_SPE(evfsadd
, evfssub
, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
8827 GEN_SPE(evfsabs
, evfsnabs
, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
); //
8828 GEN_SPE(evfsneg
, speundef
, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8829 GEN_SPE(evfsmul
, evfsdiv
, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
8830 GEN_SPE(evfscmpgt
, evfscmplt
, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
8831 GEN_SPE(evfscmpeq
, speundef
, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8832 GEN_SPE(evfscfui
, evfscfsi
, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8833 GEN_SPE(evfscfuf
, evfscfsf
, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8834 GEN_SPE(evfsctui
, evfsctsi
, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8835 GEN_SPE(evfsctuf
, evfsctsf
, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8836 GEN_SPE(evfsctuiz
, speundef
, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8837 GEN_SPE(evfsctsiz
, speundef
, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8838 GEN_SPE(evfststgt
, evfststlt
, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
8839 GEN_SPE(evfststeq
, speundef
, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8841 /* Single precision floating-point operations */
8843 GEN_SPEFPUOP_ARITH2_32_32(efsadd
);
8844 GEN_SPEFPUOP_ARITH2_32_32(efssub
);
8845 GEN_SPEFPUOP_ARITH2_32_32(efsmul
);
8846 GEN_SPEFPUOP_ARITH2_32_32(efsdiv
);
8847 static inline void gen_efsabs(DisasContext
*ctx
)
8849 if (unlikely(!ctx
->spe_enabled
)) {
8850 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8853 tcg_gen_andi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], (target_long
)~0x80000000LL
);
8855 static inline void gen_efsnabs(DisasContext
*ctx
)
8857 if (unlikely(!ctx
->spe_enabled
)) {
8858 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8861 tcg_gen_ori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
8863 static inline void gen_efsneg(DisasContext
*ctx
)
8865 if (unlikely(!ctx
->spe_enabled
)) {
8866 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8869 tcg_gen_xori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
8873 GEN_SPEFPUOP_CONV_32_32(efscfui
);
8874 GEN_SPEFPUOP_CONV_32_32(efscfsi
);
8875 GEN_SPEFPUOP_CONV_32_32(efscfuf
);
8876 GEN_SPEFPUOP_CONV_32_32(efscfsf
);
8877 GEN_SPEFPUOP_CONV_32_32(efsctui
);
8878 GEN_SPEFPUOP_CONV_32_32(efsctsi
);
8879 GEN_SPEFPUOP_CONV_32_32(efsctuf
);
8880 GEN_SPEFPUOP_CONV_32_32(efsctsf
);
8881 GEN_SPEFPUOP_CONV_32_32(efsctuiz
);
8882 GEN_SPEFPUOP_CONV_32_32(efsctsiz
);
8883 GEN_SPEFPUOP_CONV_32_64(efscfd
);
8886 GEN_SPEFPUOP_COMP_32(efscmpgt
);
8887 GEN_SPEFPUOP_COMP_32(efscmplt
);
8888 GEN_SPEFPUOP_COMP_32(efscmpeq
);
8889 GEN_SPEFPUOP_COMP_32(efststgt
);
8890 GEN_SPEFPUOP_COMP_32(efststlt
);
8891 GEN_SPEFPUOP_COMP_32(efststeq
);
8893 /* Opcodes definitions */
8894 GEN_SPE(efsadd
, efssub
, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
8895 GEN_SPE(efsabs
, efsnabs
, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
); //
8896 GEN_SPE(efsneg
, speundef
, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8897 GEN_SPE(efsmul
, efsdiv
, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
8898 GEN_SPE(efscmpgt
, efscmplt
, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
8899 GEN_SPE(efscmpeq
, efscfd
, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE
); //
8900 GEN_SPE(efscfui
, efscfsi
, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8901 GEN_SPE(efscfuf
, efscfsf
, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8902 GEN_SPE(efsctui
, efsctsi
, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8903 GEN_SPE(efsctuf
, efsctsf
, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8904 GEN_SPE(efsctuiz
, speundef
, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8905 GEN_SPE(efsctsiz
, speundef
, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8906 GEN_SPE(efststgt
, efststlt
, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
8907 GEN_SPE(efststeq
, speundef
, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8909 /* Double precision floating-point operations */
8911 GEN_SPEFPUOP_ARITH2_64_64(efdadd
);
8912 GEN_SPEFPUOP_ARITH2_64_64(efdsub
);
8913 GEN_SPEFPUOP_ARITH2_64_64(efdmul
);
8914 GEN_SPEFPUOP_ARITH2_64_64(efddiv
);
8915 static inline void gen_efdabs(DisasContext
*ctx
)
8917 if (unlikely(!ctx
->spe_enabled
)) {
8918 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8921 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8922 tcg_gen_andi_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
8925 static inline void gen_efdnabs(DisasContext
*ctx
)
8927 if (unlikely(!ctx
->spe_enabled
)) {
8928 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8931 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8932 tcg_gen_ori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
8935 static inline void gen_efdneg(DisasContext
*ctx
)
8937 if (unlikely(!ctx
->spe_enabled
)) {
8938 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8941 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8942 tcg_gen_xori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
8947 GEN_SPEFPUOP_CONV_64_32(efdcfui
);
8948 GEN_SPEFPUOP_CONV_64_32(efdcfsi
);
8949 GEN_SPEFPUOP_CONV_64_32(efdcfuf
);
8950 GEN_SPEFPUOP_CONV_64_32(efdcfsf
);
8951 GEN_SPEFPUOP_CONV_32_64(efdctui
);
8952 GEN_SPEFPUOP_CONV_32_64(efdctsi
);
8953 GEN_SPEFPUOP_CONV_32_64(efdctuf
);
8954 GEN_SPEFPUOP_CONV_32_64(efdctsf
);
8955 GEN_SPEFPUOP_CONV_32_64(efdctuiz
);
8956 GEN_SPEFPUOP_CONV_32_64(efdctsiz
);
8957 GEN_SPEFPUOP_CONV_64_32(efdcfs
);
8958 GEN_SPEFPUOP_CONV_64_64(efdcfuid
);
8959 GEN_SPEFPUOP_CONV_64_64(efdcfsid
);
8960 GEN_SPEFPUOP_CONV_64_64(efdctuidz
);
8961 GEN_SPEFPUOP_CONV_64_64(efdctsidz
);
8964 GEN_SPEFPUOP_COMP_64(efdcmpgt
);
8965 GEN_SPEFPUOP_COMP_64(efdcmplt
);
8966 GEN_SPEFPUOP_COMP_64(efdcmpeq
);
8967 GEN_SPEFPUOP_COMP_64(efdtstgt
);
8968 GEN_SPEFPUOP_COMP_64(efdtstlt
);
8969 GEN_SPEFPUOP_COMP_64(efdtsteq
);
8971 /* Opcodes definitions */
8972 GEN_SPE(efdadd
, efdsub
, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
); //
8973 GEN_SPE(efdcfuid
, efdcfsid
, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8974 GEN_SPE(efdabs
, efdnabs
, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE
); //
8975 GEN_SPE(efdneg
, speundef
, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
8976 GEN_SPE(efdmul
, efddiv
, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
); //
8977 GEN_SPE(efdctuidz
, efdctsidz
, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8978 GEN_SPE(efdcmpgt
, efdcmplt
, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
); //
8979 GEN_SPE(efdcmpeq
, efdcfs
, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE
); //
8980 GEN_SPE(efdcfui
, efdcfsi
, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8981 GEN_SPE(efdcfuf
, efdcfsf
, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8982 GEN_SPE(efdctui
, efdctsi
, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8983 GEN_SPE(efdctuf
, efdctsf
, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8984 GEN_SPE(efdctuiz
, speundef
, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
8985 GEN_SPE(efdctsiz
, speundef
, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
8986 GEN_SPE(efdtstgt
, efdtstlt
, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
); //
8987 GEN_SPE(efdtsteq
, speundef
, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
8989 static void gen_tbegin(DisasContext
*ctx
)
8991 if (unlikely(!ctx
->tm_enabled
)) {
8992 gen_exception_err(ctx
, POWERPC_EXCP_FU
, FSCR_IC_TM
);
8995 gen_helper_tbegin(cpu_env
);
8998 #define GEN_TM_NOOP(name) \
8999 static inline void gen_##name(DisasContext *ctx) \
9001 if (unlikely(!ctx->tm_enabled)) { \
9002 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9005 /* Because tbegin always fails in QEMU, these user \
9006 * space instructions all have a simple implementation: \
9008 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9009 * = 0b0 || 0b00 || 0b0 \
9011 tcg_gen_movi_i32(cpu_crf[0], 0); \
9015 GEN_TM_NOOP(tabort
);
9016 GEN_TM_NOOP(tabortwc
);
9017 GEN_TM_NOOP(tabortwci
);
9018 GEN_TM_NOOP(tabortdc
);
9019 GEN_TM_NOOP(tabortdci
);
9022 static void gen_tcheck(DisasContext
*ctx
)
9024 if (unlikely(!ctx
->tm_enabled
)) {
9025 gen_exception_err(ctx
, POWERPC_EXCP_FU
, FSCR_IC_TM
);
9028 /* Because tbegin always fails, the tcheck implementation
9031 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
9032 * = 0b1 || 0b00 || 0b0
9034 tcg_gen_movi_i32(cpu_crf
[crfD(ctx
->opcode
)], 0x8);
9037 #if defined(CONFIG_USER_ONLY)
9038 #define GEN_TM_PRIV_NOOP(name) \
9039 static inline void gen_##name(DisasContext *ctx) \
9041 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9046 #define GEN_TM_PRIV_NOOP(name) \
9047 static inline void gen_##name(DisasContext *ctx) \
9050 if (unlikely(!ctx->tm_enabled)) { \
9051 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9054 /* Because tbegin always fails, the implementation is \
9057 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9058 * = 0b0 || 0b00 | 0b0 \
9060 tcg_gen_movi_i32(cpu_crf[0], 0); \
9065 GEN_TM_PRIV_NOOP(treclaim
);
9066 GEN_TM_PRIV_NOOP(trechkpt
);
9068 static opcode_t opcodes
[] = {
9069 GEN_HANDLER(invalid
, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE
),
9070 GEN_HANDLER(cmp
, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER
),
9071 GEN_HANDLER(cmpi
, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
9072 GEN_HANDLER(cmpl
, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER
),
9073 GEN_HANDLER(cmpli
, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
9074 #if defined(TARGET_PPC64)
9075 GEN_HANDLER_E(cmpeqb
, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE
, PPC2_ISA300
),
9077 GEN_HANDLER_E(cmpb
, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE
, PPC2_ISA205
),
9078 GEN_HANDLER_E(cmprb
, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE
, PPC2_ISA300
),
9079 GEN_HANDLER(isel
, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL
),
9080 GEN_HANDLER(addi
, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9081 GEN_HANDLER(addic
, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9082 GEN_HANDLER2(addic_
, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9083 GEN_HANDLER(addis
, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9084 GEN_HANDLER_E(addpcis
, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA300
),
9085 GEN_HANDLER(mulhw
, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER
),
9086 GEN_HANDLER(mulhwu
, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER
),
9087 GEN_HANDLER(mullw
, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER
),
9088 GEN_HANDLER(mullwo
, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER
),
9089 GEN_HANDLER(mulli
, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9090 #if defined(TARGET_PPC64)
9091 GEN_HANDLER(mulld
, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B
),
9093 GEN_HANDLER(neg
, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER
),
9094 GEN_HANDLER(nego
, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER
),
9095 GEN_HANDLER(subfic
, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9096 GEN_HANDLER2(andi_
, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9097 GEN_HANDLER2(andis_
, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9098 GEN_HANDLER(cntlzw
, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER
),
9099 GEN_HANDLER_E(cnttzw
, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE
, PPC2_ISA300
),
9100 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER
),
9101 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER
),
9102 GEN_HANDLER(ori
, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9103 GEN_HANDLER(oris
, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9104 GEN_HANDLER(xori
, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9105 GEN_HANDLER(xoris
, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9106 GEN_HANDLER(popcntb
, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB
),
9107 GEN_HANDLER(popcntw
, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD
),
9108 GEN_HANDLER_E(prtyw
, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE
, PPC2_ISA205
),
9109 #if defined(TARGET_PPC64)
9110 GEN_HANDLER(popcntd
, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD
),
9111 GEN_HANDLER(cntlzd
, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B
),
9112 GEN_HANDLER_E(cnttzd
, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE
, PPC2_ISA300
),
9113 GEN_HANDLER_E(prtyd
, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE
, PPC2_ISA205
),
9114 GEN_HANDLER_E(bpermd
, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE
, PPC2_PERM_ISA206
),
9116 GEN_HANDLER(rlwimi
, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9117 GEN_HANDLER(rlwinm
, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9118 GEN_HANDLER(rlwnm
, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9119 GEN_HANDLER(slw
, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER
),
9120 GEN_HANDLER(sraw
, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER
),
9121 GEN_HANDLER(srawi
, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER
),
9122 GEN_HANDLER(srw
, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER
),
9123 #if defined(TARGET_PPC64)
9124 GEN_HANDLER(sld
, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B
),
9125 GEN_HANDLER(srad
, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B
),
9126 GEN_HANDLER2(sradi0
, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B
),
9127 GEN_HANDLER2(sradi1
, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B
),
9128 GEN_HANDLER(srd
, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B
),
9130 #if defined(TARGET_PPC64)
9131 GEN_HANDLER(ld
, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B
),
9132 GEN_HANDLER(lq
, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX
),
9133 GEN_HANDLER(std
, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B
),
9135 GEN_HANDLER(lmw
, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9136 GEN_HANDLER(stmw
, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9137 GEN_HANDLER(lswi
, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING
),
9138 GEN_HANDLER(lswx
, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING
),
9139 GEN_HANDLER(stswi
, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING
),
9140 GEN_HANDLER(stswx
, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING
),
9141 GEN_HANDLER(eieio
, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO
),
9142 GEN_HANDLER(isync
, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM
),
9143 GEN_HANDLER_E(lbarx
, 0x1F, 0x14, 0x01, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
9144 GEN_HANDLER_E(lharx
, 0x1F, 0x14, 0x03, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
9145 GEN_HANDLER(lwarx
, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES
),
9146 GEN_HANDLER_E(stbcx_
, 0x1F, 0x16, 0x15, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
9147 GEN_HANDLER_E(sthcx_
, 0x1F, 0x16, 0x16, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
9148 GEN_HANDLER2(stwcx_
, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES
),
9149 #if defined(TARGET_PPC64)
9150 GEN_HANDLER(ldarx
, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B
),
9151 GEN_HANDLER_E(lqarx
, 0x1F, 0x14, 0x08, 0, PPC_NONE
, PPC2_LSQ_ISA207
),
9152 GEN_HANDLER2(stdcx_
, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B
),
9153 GEN_HANDLER_E(stqcx_
, 0x1F, 0x16, 0x05, 0, PPC_NONE
, PPC2_LSQ_ISA207
),
9155 GEN_HANDLER(sync
, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC
),
9156 GEN_HANDLER(wait
, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT
),
9157 GEN_HANDLER(b
, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
9158 GEN_HANDLER(bc
, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
9159 GEN_HANDLER(bcctr
, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW
),
9160 GEN_HANDLER(bclr
, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW
),
9161 GEN_HANDLER_E(bctar
, 0x13, 0x10, 0x11, 0, PPC_NONE
, PPC2_BCTAR_ISA207
),
9162 GEN_HANDLER(mcrf
, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER
),
9163 GEN_HANDLER(rfi
, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW
),
9164 #if defined(TARGET_PPC64)
9165 GEN_HANDLER(rfid
, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B
),
9166 GEN_HANDLER_E(doze
, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
9167 GEN_HANDLER_E(nap
, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
9168 GEN_HANDLER_E(sleep
, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
9169 GEN_HANDLER_E(rvwinkle
, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
9170 GEN_HANDLER(hrfid
, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H
),
9172 GEN_HANDLER(sc
, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW
),
9173 GEN_HANDLER(tw
, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW
),
9174 GEN_HANDLER(twi
, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
9175 #if defined(TARGET_PPC64)
9176 GEN_HANDLER(td
, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B
),
9177 GEN_HANDLER(tdi
, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B
),
9179 GEN_HANDLER(mcrxr
, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC
),
9180 GEN_HANDLER(mfcr
, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC
),
9181 GEN_HANDLER(mfmsr
, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC
),
9182 GEN_HANDLER(mfspr
, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC
),
9183 GEN_HANDLER(mftb
, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB
),
9184 GEN_HANDLER(mtcrf
, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC
),
9185 #if defined(TARGET_PPC64)
9186 GEN_HANDLER(mtmsrd
, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B
),
9187 GEN_HANDLER_E(setb
, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE
, PPC2_ISA300
),
9189 GEN_HANDLER(mtmsr
, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC
),
9190 GEN_HANDLER(mtspr
, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC
),
9191 GEN_HANDLER(dcbf
, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE
),
9192 GEN_HANDLER(dcbi
, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE
),
9193 GEN_HANDLER(dcbst
, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE
),
9194 GEN_HANDLER(dcbt
, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE
),
9195 GEN_HANDLER(dcbtst
, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE
),
9196 GEN_HANDLER_E(dcbtls
, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE
, PPC2_BOOKE206
),
9197 GEN_HANDLER(dcbz
, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ
),
9198 GEN_HANDLER(dst
, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC
),
9199 GEN_HANDLER(dstst
, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC
),
9200 GEN_HANDLER(dss
, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC
),
9201 GEN_HANDLER(icbi
, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI
),
9202 GEN_HANDLER(dcba
, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA
),
9203 GEN_HANDLER(mfsr
, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT
),
9204 GEN_HANDLER(mfsrin
, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT
),
9205 GEN_HANDLER(mtsr
, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT
),
9206 GEN_HANDLER(mtsrin
, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT
),
9207 #if defined(TARGET_PPC64)
9208 GEN_HANDLER2(mfsr_64b
, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B
),
9209 GEN_HANDLER2(mfsrin_64b
, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9211 GEN_HANDLER2(mtsr_64b
, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B
),
9212 GEN_HANDLER2(mtsrin_64b
, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9214 GEN_HANDLER2(slbmte
, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B
),
9215 GEN_HANDLER2(slbmfee
, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B
),
9216 GEN_HANDLER2(slbmfev
, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B
),
9217 GEN_HANDLER2(slbfee_
, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B
),
9219 GEN_HANDLER(tlbia
, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA
),
9220 /* XXX Those instructions will need to be handled differently for
9221 * different ISA versions */
9222 GEN_HANDLER(tlbiel
, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE
),
9223 GEN_HANDLER(tlbie
, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE
),
9224 GEN_HANDLER(tlbsync
, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC
),
9225 #if defined(TARGET_PPC64)
9226 GEN_HANDLER(slbia
, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI
),
9227 GEN_HANDLER(slbie
, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI
),
9229 GEN_HANDLER(eciwx
, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN
),
9230 GEN_HANDLER(ecowx
, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN
),
9231 GEN_HANDLER(abs
, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR
),
9232 GEN_HANDLER(abso
, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR
),
9233 GEN_HANDLER(clcs
, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR
),
9234 GEN_HANDLER(div
, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR
),
9235 GEN_HANDLER(divo
, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR
),
9236 GEN_HANDLER(divs
, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR
),
9237 GEN_HANDLER(divso
, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR
),
9238 GEN_HANDLER(doz
, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR
),
9239 GEN_HANDLER(dozo
, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR
),
9240 GEN_HANDLER(dozi
, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
9241 GEN_HANDLER(lscbx
, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR
),
9242 GEN_HANDLER(maskg
, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR
),
9243 GEN_HANDLER(maskir
, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR
),
9244 GEN_HANDLER(mul
, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR
),
9245 GEN_HANDLER(mulo
, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR
),
9246 GEN_HANDLER(nabs
, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR
),
9247 GEN_HANDLER(nabso
, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR
),
9248 GEN_HANDLER(rlmi
, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
9249 GEN_HANDLER(rrib
, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR
),
9250 GEN_HANDLER(sle
, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR
),
9251 GEN_HANDLER(sleq
, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR
),
9252 GEN_HANDLER(sliq
, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR
),
9253 GEN_HANDLER(slliq
, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR
),
9254 GEN_HANDLER(sllq
, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR
),
9255 GEN_HANDLER(slq
, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR
),
9256 GEN_HANDLER(sraiq
, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR
),
9257 GEN_HANDLER(sraq
, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR
),
9258 GEN_HANDLER(sre
, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR
),
9259 GEN_HANDLER(srea
, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR
),
9260 GEN_HANDLER(sreq
, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR
),
9261 GEN_HANDLER(sriq
, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR
),
9262 GEN_HANDLER(srliq
, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR
),
9263 GEN_HANDLER(srlq
, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR
),
9264 GEN_HANDLER(srq
, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR
),
9265 GEN_HANDLER(dsa
, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC
),
9266 GEN_HANDLER(esa
, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC
),
9267 GEN_HANDLER(mfrom
, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC
),
9268 GEN_HANDLER2(tlbld_6xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB
),
9269 GEN_HANDLER2(tlbli_6xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB
),
9270 GEN_HANDLER2(tlbld_74xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB
),
9271 GEN_HANDLER2(tlbli_74xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB
),
9272 GEN_HANDLER(clf
, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER
),
9273 GEN_HANDLER(cli
, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER
),
9274 GEN_HANDLER(dclst
, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER
),
9275 GEN_HANDLER(mfsri
, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER
),
9276 GEN_HANDLER(rac
, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER
),
9277 GEN_HANDLER(rfsvc
, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER
),
9278 GEN_HANDLER(lfq
, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
9279 GEN_HANDLER(lfqu
, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
9280 GEN_HANDLER(lfqux
, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2
),
9281 GEN_HANDLER(lfqx
, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2
),
9282 GEN_HANDLER(stfq
, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
9283 GEN_HANDLER(stfqu
, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
9284 GEN_HANDLER(stfqux
, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2
),
9285 GEN_HANDLER(stfqx
, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2
),
9286 GEN_HANDLER(mfapidi
, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI
),
9287 GEN_HANDLER(tlbiva
, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA
),
9288 GEN_HANDLER(mfdcr
, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR
),
9289 GEN_HANDLER(mtdcr
, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR
),
9290 GEN_HANDLER(mfdcrx
, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX
),
9291 GEN_HANDLER(mtdcrx
, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX
),
9292 GEN_HANDLER(mfdcrux
, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX
),
9293 GEN_HANDLER(mtdcrux
, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX
),
9294 GEN_HANDLER(dccci
, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON
),
9295 GEN_HANDLER(dcread
, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON
),
9296 GEN_HANDLER2(icbt_40x
, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT
),
9297 GEN_HANDLER(iccci
, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON
),
9298 GEN_HANDLER(icread
, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON
),
9299 GEN_HANDLER2(rfci_40x
, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP
),
9300 GEN_HANDLER_E(rfci
, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE
, PPC2_BOOKE206
),
9301 GEN_HANDLER(rfdi
, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI
),
9302 GEN_HANDLER(rfmci
, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI
),
9303 GEN_HANDLER2(tlbre_40x
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB
),
9304 GEN_HANDLER2(tlbsx_40x
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB
),
9305 GEN_HANDLER2(tlbwe_40x
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB
),
9306 GEN_HANDLER2(tlbre_440
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE
),
9307 GEN_HANDLER2(tlbsx_440
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE
),
9308 GEN_HANDLER2(tlbwe_440
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE
),
9309 GEN_HANDLER2_E(tlbre_booke206
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
9310 PPC_NONE
, PPC2_BOOKE206
),
9311 GEN_HANDLER2_E(tlbsx_booke206
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
9312 PPC_NONE
, PPC2_BOOKE206
),
9313 GEN_HANDLER2_E(tlbwe_booke206
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
9314 PPC_NONE
, PPC2_BOOKE206
),
9315 GEN_HANDLER2_E(tlbivax_booke206
, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
9316 PPC_NONE
, PPC2_BOOKE206
),
9317 GEN_HANDLER2_E(tlbilx_booke206
, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
9318 PPC_NONE
, PPC2_BOOKE206
),
9319 GEN_HANDLER2_E(msgsnd
, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
9320 PPC_NONE
, PPC2_PRCNTL
),
9321 GEN_HANDLER2_E(msgclr
, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
9322 PPC_NONE
, PPC2_PRCNTL
),
9323 GEN_HANDLER(wrtee
, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE
),
9324 GEN_HANDLER(wrteei
, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE
),
9325 GEN_HANDLER(dlmzb
, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC
),
9326 GEN_HANDLER_E(mbar
, 0x1F, 0x16, 0x1a, 0x001FF801,
9327 PPC_BOOKE
, PPC2_BOOKE206
),
9328 GEN_HANDLER(msync_4xx
, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE
),
9329 GEN_HANDLER2_E(icbt_440
, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
9330 PPC_BOOKE
, PPC2_BOOKE206
),
9331 GEN_HANDLER(lvsl
, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC
),
9332 GEN_HANDLER(lvsr
, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC
),
9333 GEN_HANDLER(mfvscr
, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC
),
9334 GEN_HANDLER(mtvscr
, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC
),
9335 GEN_HANDLER(vmladduhm
, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC
),
9336 #if defined(TARGET_PPC64)
9337 GEN_HANDLER_E(maddhd_maddhdu
, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE
,
9339 GEN_HANDLER_E(maddld
, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA300
),
9341 GEN_HANDLER2(evsel0
, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE
),
9342 GEN_HANDLER2(evsel1
, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE
),
9343 GEN_HANDLER2(evsel2
, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE
),
9344 GEN_HANDLER2(evsel3
, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE
),
9346 #undef GEN_INT_ARITH_ADD
9347 #undef GEN_INT_ARITH_ADD_CONST
9348 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
9349 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
9350 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
9351 add_ca, compute_ca, compute_ov) \
9352 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
9353 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
9354 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
9355 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
9356 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
9357 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
9358 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
9359 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
9360 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
9361 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
9362 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
9364 #undef GEN_INT_ARITH_DIVW
9365 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
9366 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
9367 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0),
9368 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1),
9369 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0),
9370 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1),
9371 GEN_HANDLER_E(divwe
, 0x1F, 0x0B, 0x0D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
9372 GEN_HANDLER_E(divweo
, 0x1F, 0x0B, 0x1D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
9373 GEN_HANDLER_E(divweu
, 0x1F, 0x0B, 0x0C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
9374 GEN_HANDLER_E(divweuo
, 0x1F, 0x0B, 0x1C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
9375 GEN_HANDLER_E(modsw
, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE
, PPC2_ISA300
),
9376 GEN_HANDLER_E(moduw
, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE
, PPC2_ISA300
),
9378 #if defined(TARGET_PPC64)
9379 #undef GEN_INT_ARITH_DIVD
9380 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
9381 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
9382 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0),
9383 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1),
9384 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0),
9385 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1),
9387 GEN_HANDLER_E(divdeu
, 0x1F, 0x09, 0x0C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
9388 GEN_HANDLER_E(divdeuo
, 0x1F, 0x09, 0x1C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
9389 GEN_HANDLER_E(divde
, 0x1F, 0x09, 0x0D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
9390 GEN_HANDLER_E(divdeo
, 0x1F, 0x09, 0x1D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
9391 GEN_HANDLER_E(modsd
, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE
, PPC2_ISA300
),
9392 GEN_HANDLER_E(modud
, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE
, PPC2_ISA300
),
9394 #undef GEN_INT_ARITH_MUL_HELPER
9395 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
9396 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
9397 GEN_INT_ARITH_MUL_HELPER(mulhdu
, 0x00),
9398 GEN_INT_ARITH_MUL_HELPER(mulhd
, 0x02),
9399 GEN_INT_ARITH_MUL_HELPER(mulldo
, 0x17),
9402 #undef GEN_INT_ARITH_SUBF
9403 #undef GEN_INT_ARITH_SUBF_CONST
9404 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
9405 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
9406 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
9407 add_ca, compute_ca, compute_ov) \
9408 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
9409 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
9410 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
9411 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
9412 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
9413 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
9414 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
9415 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
9416 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
9417 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
9418 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
9422 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
9423 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
9424 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
9425 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
9426 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
),
9427 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
),
9428 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
),
9429 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
),
9430 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
),
9431 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
),
9432 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
),
9433 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
),
9434 #if defined(TARGET_PPC64)
9435 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
),
9438 #if defined(TARGET_PPC64)
9441 #define GEN_PPC64_R2(name, opc1, opc2) \
9442 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
9443 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
9445 #define GEN_PPC64_R4(name, opc1, opc2) \
9446 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
9447 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
9449 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
9451 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
9453 GEN_PPC64_R4(rldicl
, 0x1E, 0x00),
9454 GEN_PPC64_R4(rldicr
, 0x1E, 0x02),
9455 GEN_PPC64_R4(rldic
, 0x1E, 0x04),
9456 GEN_PPC64_R2(rldcl
, 0x1E, 0x08),
9457 GEN_PPC64_R2(rldcr
, 0x1E, 0x09),
9458 GEN_PPC64_R4(rldimi
, 0x1E, 0x06),
9466 #define GEN_LD(name, ldop, opc, type) \
9467 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9468 #define GEN_LDU(name, ldop, opc, type) \
9469 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9470 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
9471 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
9472 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
9473 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
9474 #define GEN_LDS(name, ldop, op, type) \
9475 GEN_LD(name, ldop, op | 0x20, type) \
9476 GEN_LDU(name, ldop, op | 0x21, type) \
9477 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
9478 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
9480 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
)
9481 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
)
9482 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
)
9483 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
)
9484 #if defined(TARGET_PPC64)
9485 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
)
9486 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
)
9487 GEN_LDUX(ld
, ld64
, 0x15, 0x01, PPC_64B
)
9488 GEN_LDX(ld
, ld64
, 0x15, 0x00, PPC_64B
)
9489 GEN_LDX_E(ldbr
, ld64ur
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
, CHK_NONE
)
9491 /* HV/P7 and later only */
9492 GEN_LDX_HVRM(ldcix
, ld64
, 0x15, 0x1b, PPC_CILDST
)
9493 GEN_LDX_HVRM(lwzcix
, ld32u
, 0x15, 0x18, PPC_CILDST
)
9494 GEN_LDX_HVRM(lhzcix
, ld16u
, 0x15, 0x19, PPC_CILDST
)
9495 GEN_LDX_HVRM(lbzcix
, ld8u
, 0x15, 0x1a, PPC_CILDST
)
9497 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
)
9498 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
)
9505 #define GEN_ST(name, stop, opc, type) \
9506 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9507 #define GEN_STU(name, stop, opc, type) \
9508 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
9509 #define GEN_STUX(name, stop, opc2, opc3, type) \
9510 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
9511 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
9512 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
9513 #define GEN_STS(name, stop, op, type) \
9514 GEN_ST(name, stop, op | 0x20, type) \
9515 GEN_STU(name, stop, op | 0x21, type) \
9516 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
9517 GEN_STX(name, stop, 0x17, op | 0x00, type)
9519 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
)
9520 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
)
9521 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
)
9522 #if defined(TARGET_PPC64)
9523 GEN_STUX(std
, st64
, 0x15, 0x05, PPC_64B
)
9524 GEN_STX(std
, st64
, 0x15, 0x04, PPC_64B
)
9525 GEN_STX_E(stdbr
, st64r
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
, CHK_NONE
)
9526 GEN_STX_HVRM(stdcix
, st64
, 0x15, 0x1f, PPC_CILDST
)
9527 GEN_STX_HVRM(stwcix
, st32
, 0x15, 0x1c, PPC_CILDST
)
9528 GEN_STX_HVRM(sthcix
, st16
, 0x15, 0x1d, PPC_CILDST
)
9529 GEN_STX_HVRM(stbcix
, st8
, 0x15, 0x1e, PPC_CILDST
)
9531 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
)
9532 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
)
9535 #define GEN_CRLOGIC(name, tcg_op, opc) \
9536 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
9537 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08),
9538 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04),
9539 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09),
9540 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07),
9541 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01),
9542 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E),
9543 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D),
9544 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06),
9546 #undef GEN_MAC_HANDLER
9547 #define GEN_MAC_HANDLER(name, opc2, opc3) \
9548 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
9549 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05),
9550 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15),
9551 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07),
9552 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17),
9553 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06),
9554 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16),
9555 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04),
9556 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14),
9557 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01),
9558 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11),
9559 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03),
9560 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13),
9561 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02),
9562 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12),
9563 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00),
9564 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10),
9565 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D),
9566 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D),
9567 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F),
9568 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F),
9569 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C),
9570 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C),
9571 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E),
9572 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E),
9573 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05),
9574 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15),
9575 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07),
9576 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17),
9577 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01),
9578 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11),
9579 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03),
9580 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13),
9581 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D),
9582 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D),
9583 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F),
9584 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F),
9585 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05),
9586 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04),
9587 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01),
9588 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00),
9589 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D),
9590 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C),
9592 #include "translate/fp-ops.c"
9598 #define GEN_VR_LDX(name, opc2, opc3) \
9599 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9600 #define GEN_VR_STX(name, opc2, opc3) \
9601 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9602 #define GEN_VR_LVE(name, opc2, opc3) \
9603 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9604 #define GEN_VR_STVE(name, opc2, opc3) \
9605 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9606 GEN_VR_LDX(lvx
, 0x07, 0x03),
9607 GEN_VR_LDX(lvxl
, 0x07, 0x0B),
9608 GEN_VR_LVE(bx
, 0x07, 0x00),
9609 GEN_VR_LVE(hx
, 0x07, 0x01),
9610 GEN_VR_LVE(wx
, 0x07, 0x02),
9611 GEN_VR_STX(svx
, 0x07, 0x07),
9612 GEN_VR_STX(svxl
, 0x07, 0x0F),
9613 GEN_VR_STVE(bx
, 0x07, 0x04),
9614 GEN_VR_STVE(hx
, 0x07, 0x05),
9615 GEN_VR_STVE(wx
, 0x07, 0x06),
9617 #undef GEN_VX_LOGICAL
9618 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
9619 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9621 #undef GEN_VX_LOGICAL_207
9622 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
9623 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
9625 GEN_VX_LOGICAL(vand
, tcg_gen_and_i64
, 2, 16),
9626 GEN_VX_LOGICAL(vandc
, tcg_gen_andc_i64
, 2, 17),
9627 GEN_VX_LOGICAL(vor
, tcg_gen_or_i64
, 2, 18),
9628 GEN_VX_LOGICAL(vxor
, tcg_gen_xor_i64
, 2, 19),
9629 GEN_VX_LOGICAL(vnor
, tcg_gen_nor_i64
, 2, 20),
9630 GEN_VX_LOGICAL_207(veqv
, tcg_gen_eqv_i64
, 2, 26),
9631 GEN_VX_LOGICAL_207(vnand
, tcg_gen_nand_i64
, 2, 22),
9632 GEN_VX_LOGICAL_207(vorc
, tcg_gen_orc_i64
, 2, 21),
9635 #define GEN_VXFORM(name, opc2, opc3) \
9636 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9638 #undef GEN_VXFORM_207
9639 #define GEN_VXFORM_207(name, opc2, opc3) \
9640 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
9642 #undef GEN_VXFORM_DUAL
9643 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
9644 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
9646 #undef GEN_VXRFORM_DUAL
9647 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
9648 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
9649 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
9651 GEN_VXFORM(vaddubm
, 0, 0),
9652 GEN_VXFORM(vadduhm
, 0, 1),
9653 GEN_VXFORM(vadduwm
, 0, 2),
9654 GEN_VXFORM_207(vaddudm
, 0, 3),
9655 GEN_VXFORM_DUAL(vsububm
, bcdadd
, 0, 16, PPC_ALTIVEC
, PPC_NONE
),
9656 GEN_VXFORM_DUAL(vsubuhm
, bcdsub
, 0, 17, PPC_ALTIVEC
, PPC_NONE
),
9657 GEN_VXFORM(vsubuwm
, 0, 18),
9658 GEN_VXFORM_207(vsubudm
, 0, 19),
9659 GEN_VXFORM(vmaxub
, 1, 0),
9660 GEN_VXFORM(vmaxuh
, 1, 1),
9661 GEN_VXFORM(vmaxuw
, 1, 2),
9662 GEN_VXFORM_207(vmaxud
, 1, 3),
9663 GEN_VXFORM(vmaxsb
, 1, 4),
9664 GEN_VXFORM(vmaxsh
, 1, 5),
9665 GEN_VXFORM(vmaxsw
, 1, 6),
9666 GEN_VXFORM_207(vmaxsd
, 1, 7),
9667 GEN_VXFORM(vminub
, 1, 8),
9668 GEN_VXFORM(vminuh
, 1, 9),
9669 GEN_VXFORM(vminuw
, 1, 10),
9670 GEN_VXFORM_207(vminud
, 1, 11),
9671 GEN_VXFORM(vminsb
, 1, 12),
9672 GEN_VXFORM(vminsh
, 1, 13),
9673 GEN_VXFORM(vminsw
, 1, 14),
9674 GEN_VXFORM_207(vminsd
, 1, 15),
9675 GEN_VXFORM(vavgub
, 1, 16),
9676 GEN_VXFORM(vavguh
, 1, 17),
9677 GEN_VXFORM(vavguw
, 1, 18),
9678 GEN_VXFORM(vavgsb
, 1, 20),
9679 GEN_VXFORM(vavgsh
, 1, 21),
9680 GEN_VXFORM(vavgsw
, 1, 22),
9681 GEN_VXFORM(vmrghb
, 6, 0),
9682 GEN_VXFORM(vmrghh
, 6, 1),
9683 GEN_VXFORM(vmrghw
, 6, 2),
9684 GEN_VXFORM(vmrglb
, 6, 4),
9685 GEN_VXFORM(vmrglh
, 6, 5),
9686 GEN_VXFORM(vmrglw
, 6, 6),
9687 GEN_VXFORM_207(vmrgew
, 6, 30),
9688 GEN_VXFORM_207(vmrgow
, 6, 26),
9689 GEN_VXFORM(vmuloub
, 4, 0),
9690 GEN_VXFORM(vmulouh
, 4, 1),
9691 GEN_VXFORM_DUAL(vmulouw
, vmuluwm
, 4, 2, PPC_ALTIVEC
, PPC_NONE
),
9692 GEN_VXFORM(vmulosb
, 4, 4),
9693 GEN_VXFORM(vmulosh
, 4, 5),
9694 GEN_VXFORM_207(vmulosw
, 4, 6),
9695 GEN_VXFORM(vmuleub
, 4, 8),
9696 GEN_VXFORM(vmuleuh
, 4, 9),
9697 GEN_VXFORM_207(vmuleuw
, 4, 10),
9698 GEN_VXFORM(vmulesb
, 4, 12),
9699 GEN_VXFORM(vmulesh
, 4, 13),
9700 GEN_VXFORM_207(vmulesw
, 4, 14),
9701 GEN_VXFORM(vslb
, 2, 4),
9702 GEN_VXFORM(vslh
, 2, 5),
9703 GEN_VXFORM(vslw
, 2, 6),
9704 GEN_VXFORM_207(vsld
, 2, 23),
9705 GEN_VXFORM(vsrb
, 2, 8),
9706 GEN_VXFORM(vsrh
, 2, 9),
9707 GEN_VXFORM(vsrw
, 2, 10),
9708 GEN_VXFORM_207(vsrd
, 2, 27),
9709 GEN_VXFORM(vsrab
, 2, 12),
9710 GEN_VXFORM(vsrah
, 2, 13),
9711 GEN_VXFORM(vsraw
, 2, 14),
9712 GEN_VXFORM_207(vsrad
, 2, 15),
9713 GEN_VXFORM(vslo
, 6, 16),
9714 GEN_VXFORM(vsro
, 6, 17),
9715 GEN_VXFORM(vaddcuw
, 0, 6),
9716 GEN_VXFORM(vsubcuw
, 0, 22),
9717 GEN_VXFORM(vaddubs
, 0, 8),
9718 GEN_VXFORM(vadduhs
, 0, 9),
9719 GEN_VXFORM(vadduws
, 0, 10),
9720 GEN_VXFORM(vaddsbs
, 0, 12),
9721 GEN_VXFORM(vaddshs
, 0, 13),
9722 GEN_VXFORM(vaddsws
, 0, 14),
9723 GEN_VXFORM_DUAL(vsububs
, bcdadd
, 0, 24, PPC_ALTIVEC
, PPC_NONE
),
9724 GEN_VXFORM_DUAL(vsubuhs
, bcdsub
, 0, 25, PPC_ALTIVEC
, PPC_NONE
),
9725 GEN_VXFORM(vsubuws
, 0, 26),
9726 GEN_VXFORM(vsubsbs
, 0, 28),
9727 GEN_VXFORM(vsubshs
, 0, 29),
9728 GEN_VXFORM(vsubsws
, 0, 30),
9729 GEN_VXFORM_207(vadduqm
, 0, 4),
9730 GEN_VXFORM_207(vaddcuq
, 0, 5),
9731 GEN_VXFORM_DUAL(vaddeuqm
, vaddecuq
, 30, 0xFF, PPC_NONE
, PPC2_ALTIVEC_207
),
9732 GEN_VXFORM_207(vsubuqm
, 0, 20),
9733 GEN_VXFORM_207(vsubcuq
, 0, 21),
9734 GEN_VXFORM_DUAL(vsubeuqm
, vsubecuq
, 31, 0xFF, PPC_NONE
, PPC2_ALTIVEC_207
),
9735 GEN_VXFORM(vrlb
, 2, 0),
9736 GEN_VXFORM(vrlh
, 2, 1),
9737 GEN_VXFORM(vrlw
, 2, 2),
9738 GEN_VXFORM_207(vrld
, 2, 3),
9739 GEN_VXFORM(vsl
, 2, 7),
9740 GEN_VXFORM(vsr
, 2, 11),
9741 GEN_VXFORM(vpkuhum
, 7, 0),
9742 GEN_VXFORM(vpkuwum
, 7, 1),
9743 GEN_VXFORM_207(vpkudum
, 7, 17),
9744 GEN_VXFORM(vpkuhus
, 7, 2),
9745 GEN_VXFORM(vpkuwus
, 7, 3),
9746 GEN_VXFORM_207(vpkudus
, 7, 19),
9747 GEN_VXFORM(vpkshus
, 7, 4),
9748 GEN_VXFORM(vpkswus
, 7, 5),
9749 GEN_VXFORM_207(vpksdus
, 7, 21),
9750 GEN_VXFORM(vpkshss
, 7, 6),
9751 GEN_VXFORM(vpkswss
, 7, 7),
9752 GEN_VXFORM_207(vpksdss
, 7, 23),
9753 GEN_VXFORM(vpkpx
, 7, 12),
9754 GEN_VXFORM(vsum4ubs
, 4, 24),
9755 GEN_VXFORM(vsum4sbs
, 4, 28),
9756 GEN_VXFORM(vsum4shs
, 4, 25),
9757 GEN_VXFORM(vsum2sws
, 4, 26),
9758 GEN_VXFORM(vsumsws
, 4, 30),
9759 GEN_VXFORM(vaddfp
, 5, 0),
9760 GEN_VXFORM(vsubfp
, 5, 1),
9761 GEN_VXFORM(vmaxfp
, 5, 16),
9762 GEN_VXFORM(vminfp
, 5, 17),
9766 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9767 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9768 #define GEN_VXRFORM(name, opc2, opc3) \
9769 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9770 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9771 GEN_VXRFORM(vcmpequb
, 3, 0)
9772 GEN_VXRFORM(vcmpequh
, 3, 1)
9773 GEN_VXRFORM(vcmpequw
, 3, 2)
9774 GEN_VXRFORM(vcmpgtsb
, 3, 12)
9775 GEN_VXRFORM(vcmpgtsh
, 3, 13)
9776 GEN_VXRFORM(vcmpgtsw
, 3, 14)
9777 GEN_VXRFORM(vcmpgtub
, 3, 8)
9778 GEN_VXRFORM(vcmpgtuh
, 3, 9)
9779 GEN_VXRFORM(vcmpgtuw
, 3, 10)
9780 GEN_VXRFORM_DUAL(vcmpeqfp
, vcmpequd
, 3, 3, PPC_ALTIVEC
, PPC_NONE
)
9781 GEN_VXRFORM(vcmpgefp
, 3, 7)
9782 GEN_VXRFORM_DUAL(vcmpgtfp
, vcmpgtud
, 3, 11, PPC_ALTIVEC
, PPC_NONE
)
9783 GEN_VXRFORM_DUAL(vcmpbfp
, vcmpgtsd
, 3, 15, PPC_ALTIVEC
, PPC_NONE
)
9785 #undef GEN_VXFORM_SIMM
9786 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
9787 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9788 GEN_VXFORM_SIMM(vspltisb
, 6, 12),
9789 GEN_VXFORM_SIMM(vspltish
, 6, 13),
9790 GEN_VXFORM_SIMM(vspltisw
, 6, 14),
9792 #undef GEN_VXFORM_NOA
9793 #define GEN_VXFORM_NOA(name, opc2, opc3) \
9794 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9795 GEN_VXFORM_NOA(vupkhsb
, 7, 8),
9796 GEN_VXFORM_NOA(vupkhsh
, 7, 9),
9797 GEN_VXFORM_207(vupkhsw
, 7, 25),
9798 GEN_VXFORM_NOA(vupklsb
, 7, 10),
9799 GEN_VXFORM_NOA(vupklsh
, 7, 11),
9800 GEN_VXFORM_207(vupklsw
, 7, 27),
9801 GEN_VXFORM_NOA(vupkhpx
, 7, 13),
9802 GEN_VXFORM_NOA(vupklpx
, 7, 15),
9803 GEN_VXFORM_NOA(vrefp
, 5, 4),
9804 GEN_VXFORM_NOA(vrsqrtefp
, 5, 5),
9805 GEN_VXFORM_NOA(vexptefp
, 5, 6),
9806 GEN_VXFORM_NOA(vlogefp
, 5, 7),
9807 GEN_VXFORM_NOA(vrfim
, 5, 11),
9808 GEN_VXFORM_NOA(vrfin
, 5, 8),
9809 GEN_VXFORM_NOA(vrfip
, 5, 10),
9810 GEN_VXFORM_NOA(vrfiz
, 5, 9),
9812 #undef GEN_VXFORM_UIMM
9813 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
9814 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9815 GEN_VXFORM_UIMM(vspltb
, 6, 8),
9816 GEN_VXFORM_UIMM(vsplth
, 6, 9),
9817 GEN_VXFORM_UIMM(vspltw
, 6, 10),
9818 GEN_VXFORM_UIMM(vcfux
, 5, 12),
9819 GEN_VXFORM_UIMM(vcfsx
, 5, 13),
9820 GEN_VXFORM_UIMM(vctuxs
, 5, 14),
9821 GEN_VXFORM_UIMM(vctsxs
, 5, 15),
9823 #undef GEN_VAFORM_PAIRED
9824 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9825 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9826 GEN_VAFORM_PAIRED(vmhaddshs
, vmhraddshs
, 16),
9827 GEN_VAFORM_PAIRED(vmsumubm
, vmsummbm
, 18),
9828 GEN_VAFORM_PAIRED(vmsumuhm
, vmsumuhs
, 19),
9829 GEN_VAFORM_PAIRED(vmsumshm
, vmsumshs
, 20),
9830 GEN_VAFORM_PAIRED(vsel
, vperm
, 21),
9831 GEN_VAFORM_PAIRED(vmaddfp
, vnmsubfp
, 23),
9833 GEN_VXFORM_DUAL(vclzb
, vpopcntb
, 1, 28, PPC_NONE
, PPC2_ALTIVEC_207
),
9834 GEN_VXFORM_DUAL(vclzh
, vpopcnth
, 1, 29, PPC_NONE
, PPC2_ALTIVEC_207
),
9835 GEN_VXFORM_DUAL(vclzw
, vpopcntw
, 1, 30, PPC_NONE
, PPC2_ALTIVEC_207
),
9836 GEN_VXFORM_DUAL(vclzd
, vpopcntd
, 1, 31, PPC_NONE
, PPC2_ALTIVEC_207
),
9838 GEN_VXFORM_207(vbpermq
, 6, 21),
9839 GEN_VXFORM_207(vgbbd
, 6, 20),
9840 GEN_VXFORM_207(vpmsumb
, 4, 16),
9841 GEN_VXFORM_207(vpmsumh
, 4, 17),
9842 GEN_VXFORM_207(vpmsumw
, 4, 18),
9843 GEN_VXFORM_207(vpmsumd
, 4, 19),
9845 GEN_VXFORM_207(vsbox
, 4, 23),
9847 GEN_VXFORM_DUAL(vcipher
, vcipherlast
, 4, 20, PPC_NONE
, PPC2_ALTIVEC_207
),
9848 GEN_VXFORM_DUAL(vncipher
, vncipherlast
, 4, 21, PPC_NONE
, PPC2_ALTIVEC_207
),
9850 GEN_VXFORM_207(vshasigmaw
, 1, 26),
9851 GEN_VXFORM_207(vshasigmad
, 1, 27),
9853 GEN_VXFORM_DUAL(vsldoi
, vpermxor
, 22, 0xFF, PPC_ALTIVEC
, PPC_NONE
),
9855 GEN_HANDLER_E(lxsdx
, 0x1F, 0x0C, 0x12, 0, PPC_NONE
, PPC2_VSX
),
9856 GEN_HANDLER_E(lxsiwax
, 0x1F, 0x0C, 0x02, 0, PPC_NONE
, PPC2_VSX207
),
9857 GEN_HANDLER_E(lxsiwzx
, 0x1F, 0x0C, 0x00, 0, PPC_NONE
, PPC2_VSX207
),
9858 GEN_HANDLER_E(lxsspx
, 0x1F, 0x0C, 0x10, 0, PPC_NONE
, PPC2_VSX207
),
9859 GEN_HANDLER_E(lxvd2x
, 0x1F, 0x0C, 0x1A, 0, PPC_NONE
, PPC2_VSX
),
9860 GEN_HANDLER_E(lxvdsx
, 0x1F, 0x0C, 0x0A, 0, PPC_NONE
, PPC2_VSX
),
9861 GEN_HANDLER_E(lxvw4x
, 0x1F, 0x0C, 0x18, 0, PPC_NONE
, PPC2_VSX
),
9863 GEN_HANDLER_E(stxsdx
, 0x1F, 0xC, 0x16, 0, PPC_NONE
, PPC2_VSX
),
9864 GEN_HANDLER_E(stxsiwx
, 0x1F, 0xC, 0x04, 0, PPC_NONE
, PPC2_VSX207
),
9865 GEN_HANDLER_E(stxsspx
, 0x1F, 0xC, 0x14, 0, PPC_NONE
, PPC2_VSX207
),
9866 GEN_HANDLER_E(stxvd2x
, 0x1F, 0xC, 0x1E, 0, PPC_NONE
, PPC2_VSX
),
9867 GEN_HANDLER_E(stxvw4x
, 0x1F, 0xC, 0x1C, 0, PPC_NONE
, PPC2_VSX
),
9869 GEN_HANDLER_E(mfvsrwz
, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
9870 GEN_HANDLER_E(mtvsrwa
, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
9871 GEN_HANDLER_E(mtvsrwz
, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
9872 #if defined(TARGET_PPC64)
9873 GEN_HANDLER_E(mfvsrd
, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
9874 GEN_HANDLER_E(mtvsrd
, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
9878 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
9879 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
9880 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
9883 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
9884 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
9885 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
9886 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
9887 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
9890 #define GEN_XX2IFORM(name, opc2, opc3, fl2) \
9891 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \
9892 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \
9893 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \
9894 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
9896 #undef GEN_XX3_RC_FORM
9897 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
9898 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
9899 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
9900 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
9901 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
9902 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
9903 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
9904 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
9905 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
9907 #undef GEN_XX3FORM_DM
9908 #define GEN_XX3FORM_DM(name, opc2, opc3) \
9909 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
9910 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
9911 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
9912 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
9913 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
9914 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
9915 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
9916 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
9917 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
9918 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
9919 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
9920 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
9921 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
9922 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
9923 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
9924 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
9926 GEN_XX2FORM(xsabsdp
, 0x12, 0x15, PPC2_VSX
),
9927 GEN_XX2FORM(xsnabsdp
, 0x12, 0x16, PPC2_VSX
),
9928 GEN_XX2FORM(xsnegdp
, 0x12, 0x17, PPC2_VSX
),
9929 GEN_XX3FORM(xscpsgndp
, 0x00, 0x16, PPC2_VSX
),
9931 GEN_XX2FORM(xvabsdp
, 0x12, 0x1D, PPC2_VSX
),
9932 GEN_XX2FORM(xvnabsdp
, 0x12, 0x1E, PPC2_VSX
),
9933 GEN_XX2FORM(xvnegdp
, 0x12, 0x1F, PPC2_VSX
),
9934 GEN_XX3FORM(xvcpsgndp
, 0x00, 0x1E, PPC2_VSX
),
9935 GEN_XX2FORM(xvabssp
, 0x12, 0x19, PPC2_VSX
),
9936 GEN_XX2FORM(xvnabssp
, 0x12, 0x1A, PPC2_VSX
),
9937 GEN_XX2FORM(xvnegsp
, 0x12, 0x1B, PPC2_VSX
),
9938 GEN_XX3FORM(xvcpsgnsp
, 0x00, 0x1A, PPC2_VSX
),
9940 GEN_XX3FORM(xsadddp
, 0x00, 0x04, PPC2_VSX
),
9941 GEN_XX3FORM(xssubdp
, 0x00, 0x05, PPC2_VSX
),
9942 GEN_XX3FORM(xsmuldp
, 0x00, 0x06, PPC2_VSX
),
9943 GEN_XX3FORM(xsdivdp
, 0x00, 0x07, PPC2_VSX
),
9944 GEN_XX2FORM(xsredp
, 0x14, 0x05, PPC2_VSX
),
9945 GEN_XX2FORM(xssqrtdp
, 0x16, 0x04, PPC2_VSX
),
9946 GEN_XX2FORM(xsrsqrtedp
, 0x14, 0x04, PPC2_VSX
),
9947 GEN_XX3FORM(xstdivdp
, 0x14, 0x07, PPC2_VSX
),
9948 GEN_XX2FORM(xstsqrtdp
, 0x14, 0x06, PPC2_VSX
),
9949 GEN_XX3FORM(xsmaddadp
, 0x04, 0x04, PPC2_VSX
),
9950 GEN_XX3FORM(xsmaddmdp
, 0x04, 0x05, PPC2_VSX
),
9951 GEN_XX3FORM(xsmsubadp
, 0x04, 0x06, PPC2_VSX
),
9952 GEN_XX3FORM(xsmsubmdp
, 0x04, 0x07, PPC2_VSX
),
9953 GEN_XX3FORM(xsnmaddadp
, 0x04, 0x14, PPC2_VSX
),
9954 GEN_XX3FORM(xsnmaddmdp
, 0x04, 0x15, PPC2_VSX
),
9955 GEN_XX3FORM(xsnmsubadp
, 0x04, 0x16, PPC2_VSX
),
9956 GEN_XX3FORM(xsnmsubmdp
, 0x04, 0x17, PPC2_VSX
),
9957 GEN_XX2IFORM(xscmpodp
, 0x0C, 0x05, PPC2_VSX
),
9958 GEN_XX2IFORM(xscmpudp
, 0x0C, 0x04, PPC2_VSX
),
9959 GEN_XX3FORM(xsmaxdp
, 0x00, 0x14, PPC2_VSX
),
9960 GEN_XX3FORM(xsmindp
, 0x00, 0x15, PPC2_VSX
),
9961 GEN_XX2FORM(xscvdpsp
, 0x12, 0x10, PPC2_VSX
),
9962 GEN_XX2FORM(xscvdpspn
, 0x16, 0x10, PPC2_VSX207
),
9963 GEN_XX2FORM(xscvspdp
, 0x12, 0x14, PPC2_VSX
),
9964 GEN_XX2FORM(xscvspdpn
, 0x16, 0x14, PPC2_VSX207
),
9965 GEN_XX2FORM(xscvdpsxds
, 0x10, 0x15, PPC2_VSX
),
9966 GEN_XX2FORM(xscvdpsxws
, 0x10, 0x05, PPC2_VSX
),
9967 GEN_XX2FORM(xscvdpuxds
, 0x10, 0x14, PPC2_VSX
),
9968 GEN_XX2FORM(xscvdpuxws
, 0x10, 0x04, PPC2_VSX
),
9969 GEN_XX2FORM(xscvsxddp
, 0x10, 0x17, PPC2_VSX
),
9970 GEN_XX2FORM(xscvuxddp
, 0x10, 0x16, PPC2_VSX
),
9971 GEN_XX2FORM(xsrdpi
, 0x12, 0x04, PPC2_VSX
),
9972 GEN_XX2FORM(xsrdpic
, 0x16, 0x06, PPC2_VSX
),
9973 GEN_XX2FORM(xsrdpim
, 0x12, 0x07, PPC2_VSX
),
9974 GEN_XX2FORM(xsrdpip
, 0x12, 0x06, PPC2_VSX
),
9975 GEN_XX2FORM(xsrdpiz
, 0x12, 0x05, PPC2_VSX
),
9977 GEN_XX3FORM(xsaddsp
, 0x00, 0x00, PPC2_VSX207
),
9978 GEN_XX3FORM(xssubsp
, 0x00, 0x01, PPC2_VSX207
),
9979 GEN_XX3FORM(xsmulsp
, 0x00, 0x02, PPC2_VSX207
),
9980 GEN_XX3FORM(xsdivsp
, 0x00, 0x03, PPC2_VSX207
),
9981 GEN_XX2FORM(xsresp
, 0x14, 0x01, PPC2_VSX207
),
9982 GEN_XX2FORM(xsrsp
, 0x12, 0x11, PPC2_VSX207
),
9983 GEN_XX2FORM(xssqrtsp
, 0x16, 0x00, PPC2_VSX207
),
9984 GEN_XX2FORM(xsrsqrtesp
, 0x14, 0x00, PPC2_VSX207
),
9985 GEN_XX3FORM(xsmaddasp
, 0x04, 0x00, PPC2_VSX207
),
9986 GEN_XX3FORM(xsmaddmsp
, 0x04, 0x01, PPC2_VSX207
),
9987 GEN_XX3FORM(xsmsubasp
, 0x04, 0x02, PPC2_VSX207
),
9988 GEN_XX3FORM(xsmsubmsp
, 0x04, 0x03, PPC2_VSX207
),
9989 GEN_XX3FORM(xsnmaddasp
, 0x04, 0x10, PPC2_VSX207
),
9990 GEN_XX3FORM(xsnmaddmsp
, 0x04, 0x11, PPC2_VSX207
),
9991 GEN_XX3FORM(xsnmsubasp
, 0x04, 0x12, PPC2_VSX207
),
9992 GEN_XX3FORM(xsnmsubmsp
, 0x04, 0x13, PPC2_VSX207
),
9993 GEN_XX2FORM(xscvsxdsp
, 0x10, 0x13, PPC2_VSX207
),
9994 GEN_XX2FORM(xscvuxdsp
, 0x10, 0x12, PPC2_VSX207
),
9996 GEN_XX3FORM(xvadddp
, 0x00, 0x0C, PPC2_VSX
),
9997 GEN_XX3FORM(xvsubdp
, 0x00, 0x0D, PPC2_VSX
),
9998 GEN_XX3FORM(xvmuldp
, 0x00, 0x0E, PPC2_VSX
),
9999 GEN_XX3FORM(xvdivdp
, 0x00, 0x0F, PPC2_VSX
),
10000 GEN_XX2FORM(xvredp
, 0x14, 0x0D, PPC2_VSX
),
10001 GEN_XX2FORM(xvsqrtdp
, 0x16, 0x0C, PPC2_VSX
),
10002 GEN_XX2FORM(xvrsqrtedp
, 0x14, 0x0C, PPC2_VSX
),
10003 GEN_XX3FORM(xvtdivdp
, 0x14, 0x0F, PPC2_VSX
),
10004 GEN_XX2FORM(xvtsqrtdp
, 0x14, 0x0E, PPC2_VSX
),
10005 GEN_XX3FORM(xvmaddadp
, 0x04, 0x0C, PPC2_VSX
),
10006 GEN_XX3FORM(xvmaddmdp
, 0x04, 0x0D, PPC2_VSX
),
10007 GEN_XX3FORM(xvmsubadp
, 0x04, 0x0E, PPC2_VSX
),
10008 GEN_XX3FORM(xvmsubmdp
, 0x04, 0x0F, PPC2_VSX
),
10009 GEN_XX3FORM(xvnmaddadp
, 0x04, 0x1C, PPC2_VSX
),
10010 GEN_XX3FORM(xvnmaddmdp
, 0x04, 0x1D, PPC2_VSX
),
10011 GEN_XX3FORM(xvnmsubadp
, 0x04, 0x1E, PPC2_VSX
),
10012 GEN_XX3FORM(xvnmsubmdp
, 0x04, 0x1F, PPC2_VSX
),
10013 GEN_XX3FORM(xvmaxdp
, 0x00, 0x1C, PPC2_VSX
),
10014 GEN_XX3FORM(xvmindp
, 0x00, 0x1D, PPC2_VSX
),
10015 GEN_XX3_RC_FORM(xvcmpeqdp
, 0x0C, 0x0C, PPC2_VSX
),
10016 GEN_XX3_RC_FORM(xvcmpgtdp
, 0x0C, 0x0D, PPC2_VSX
),
10017 GEN_XX3_RC_FORM(xvcmpgedp
, 0x0C, 0x0E, PPC2_VSX
),
10018 GEN_XX2FORM(xvcvdpsp
, 0x12, 0x18, PPC2_VSX
),
10019 GEN_XX2FORM(xvcvdpsxds
, 0x10, 0x1D, PPC2_VSX
),
10020 GEN_XX2FORM(xvcvdpsxws
, 0x10, 0x0D, PPC2_VSX
),
10021 GEN_XX2FORM(xvcvdpuxds
, 0x10, 0x1C, PPC2_VSX
),
10022 GEN_XX2FORM(xvcvdpuxws
, 0x10, 0x0C, PPC2_VSX
),
10023 GEN_XX2FORM(xvcvsxddp
, 0x10, 0x1F, PPC2_VSX
),
10024 GEN_XX2FORM(xvcvuxddp
, 0x10, 0x1E, PPC2_VSX
),
10025 GEN_XX2FORM(xvcvsxwdp
, 0x10, 0x0F, PPC2_VSX
),
10026 GEN_XX2FORM(xvcvuxwdp
, 0x10, 0x0E, PPC2_VSX
),
10027 GEN_XX2FORM(xvrdpi
, 0x12, 0x0C, PPC2_VSX
),
10028 GEN_XX2FORM(xvrdpic
, 0x16, 0x0E, PPC2_VSX
),
10029 GEN_XX2FORM(xvrdpim
, 0x12, 0x0F, PPC2_VSX
),
10030 GEN_XX2FORM(xvrdpip
, 0x12, 0x0E, PPC2_VSX
),
10031 GEN_XX2FORM(xvrdpiz
, 0x12, 0x0D, PPC2_VSX
),
10033 GEN_XX3FORM(xvaddsp
, 0x00, 0x08, PPC2_VSX
),
10034 GEN_XX3FORM(xvsubsp
, 0x00, 0x09, PPC2_VSX
),
10035 GEN_XX3FORM(xvmulsp
, 0x00, 0x0A, PPC2_VSX
),
10036 GEN_XX3FORM(xvdivsp
, 0x00, 0x0B, PPC2_VSX
),
10037 GEN_XX2FORM(xvresp
, 0x14, 0x09, PPC2_VSX
),
10038 GEN_XX2FORM(xvsqrtsp
, 0x16, 0x08, PPC2_VSX
),
10039 GEN_XX2FORM(xvrsqrtesp
, 0x14, 0x08, PPC2_VSX
),
10040 GEN_XX3FORM(xvtdivsp
, 0x14, 0x0B, PPC2_VSX
),
10041 GEN_XX2FORM(xvtsqrtsp
, 0x14, 0x0A, PPC2_VSX
),
10042 GEN_XX3FORM(xvmaddasp
, 0x04, 0x08, PPC2_VSX
),
10043 GEN_XX3FORM(xvmaddmsp
, 0x04, 0x09, PPC2_VSX
),
10044 GEN_XX3FORM(xvmsubasp
, 0x04, 0x0A, PPC2_VSX
),
10045 GEN_XX3FORM(xvmsubmsp
, 0x04, 0x0B, PPC2_VSX
),
10046 GEN_XX3FORM(xvnmaddasp
, 0x04, 0x18, PPC2_VSX
),
10047 GEN_XX3FORM(xvnmaddmsp
, 0x04, 0x19, PPC2_VSX
),
10048 GEN_XX3FORM(xvnmsubasp
, 0x04, 0x1A, PPC2_VSX
),
10049 GEN_XX3FORM(xvnmsubmsp
, 0x04, 0x1B, PPC2_VSX
),
10050 GEN_XX3FORM(xvmaxsp
, 0x00, 0x18, PPC2_VSX
),
10051 GEN_XX3FORM(xvminsp
, 0x00, 0x19, PPC2_VSX
),
10052 GEN_XX3_RC_FORM(xvcmpeqsp
, 0x0C, 0x08, PPC2_VSX
),
10053 GEN_XX3_RC_FORM(xvcmpgtsp
, 0x0C, 0x09, PPC2_VSX
),
10054 GEN_XX3_RC_FORM(xvcmpgesp
, 0x0C, 0x0A, PPC2_VSX
),
10055 GEN_XX2FORM(xvcvspdp
, 0x12, 0x1C, PPC2_VSX
),
10056 GEN_XX2FORM(xvcvspsxds
, 0x10, 0x19, PPC2_VSX
),
10057 GEN_XX2FORM(xvcvspsxws
, 0x10, 0x09, PPC2_VSX
),
10058 GEN_XX2FORM(xvcvspuxds
, 0x10, 0x18, PPC2_VSX
),
10059 GEN_XX2FORM(xvcvspuxws
, 0x10, 0x08, PPC2_VSX
),
10060 GEN_XX2FORM(xvcvsxdsp
, 0x10, 0x1B, PPC2_VSX
),
10061 GEN_XX2FORM(xvcvuxdsp
, 0x10, 0x1A, PPC2_VSX
),
10062 GEN_XX2FORM(xvcvsxwsp
, 0x10, 0x0B, PPC2_VSX
),
10063 GEN_XX2FORM(xvcvuxwsp
, 0x10, 0x0A, PPC2_VSX
),
10064 GEN_XX2FORM(xvrspi
, 0x12, 0x08, PPC2_VSX
),
10065 GEN_XX2FORM(xvrspic
, 0x16, 0x0A, PPC2_VSX
),
10066 GEN_XX2FORM(xvrspim
, 0x12, 0x0B, PPC2_VSX
),
10067 GEN_XX2FORM(xvrspip
, 0x12, 0x0A, PPC2_VSX
),
10068 GEN_XX2FORM(xvrspiz
, 0x12, 0x09, PPC2_VSX
),
10071 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10072 GEN_XX3FORM(name, opc2, opc3, fl2)
10074 VSX_LOGICAL(xxland
, 0x8, 0x10, PPC2_VSX
),
10075 VSX_LOGICAL(xxlandc
, 0x8, 0x11, PPC2_VSX
),
10076 VSX_LOGICAL(xxlor
, 0x8, 0x12, PPC2_VSX
),
10077 VSX_LOGICAL(xxlxor
, 0x8, 0x13, PPC2_VSX
),
10078 VSX_LOGICAL(xxlnor
, 0x8, 0x14, PPC2_VSX
),
10079 VSX_LOGICAL(xxleqv
, 0x8, 0x17, PPC2_VSX207
),
10080 VSX_LOGICAL(xxlnand
, 0x8, 0x16, PPC2_VSX207
),
10081 VSX_LOGICAL(xxlorc
, 0x8, 0x15, PPC2_VSX207
),
10082 GEN_XX3FORM(xxmrghw
, 0x08, 0x02, PPC2_VSX
),
10083 GEN_XX3FORM(xxmrglw
, 0x08, 0x06, PPC2_VSX
),
10084 GEN_XX2FORM(xxspltw
, 0x08, 0x0A, PPC2_VSX
),
10085 GEN_XX3FORM_DM(xxsldwi
, 0x08, 0x00),
10087 #define GEN_XXSEL_ROW(opc3) \
10088 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10089 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10090 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10091 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10092 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10093 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10094 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10095 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10097 GEN_XXSEL_ROW(0x00)
10098 GEN_XXSEL_ROW(0x01)
10099 GEN_XXSEL_ROW(0x02)
10100 GEN_XXSEL_ROW(0x03)
10101 GEN_XXSEL_ROW(0x04)
10102 GEN_XXSEL_ROW(0x05)
10103 GEN_XXSEL_ROW(0x06)
10104 GEN_XXSEL_ROW(0x07)
10105 GEN_XXSEL_ROW(0x08)
10106 GEN_XXSEL_ROW(0x09)
10107 GEN_XXSEL_ROW(0x0A)
10108 GEN_XXSEL_ROW(0x0B)
10109 GEN_XXSEL_ROW(0x0C)
10110 GEN_XXSEL_ROW(0x0D)
10111 GEN_XXSEL_ROW(0x0E)
10112 GEN_XXSEL_ROW(0x0F)
10113 GEN_XXSEL_ROW(0x10)
10114 GEN_XXSEL_ROW(0x11)
10115 GEN_XXSEL_ROW(0x12)
10116 GEN_XXSEL_ROW(0x13)
10117 GEN_XXSEL_ROW(0x14)
10118 GEN_XXSEL_ROW(0x15)
10119 GEN_XXSEL_ROW(0x16)
10120 GEN_XXSEL_ROW(0x17)
10121 GEN_XXSEL_ROW(0x18)
10122 GEN_XXSEL_ROW(0x19)
10123 GEN_XXSEL_ROW(0x1A)
10124 GEN_XXSEL_ROW(0x1B)
10125 GEN_XXSEL_ROW(0x1C)
10126 GEN_XXSEL_ROW(0x1D)
10127 GEN_XXSEL_ROW(0x1E)
10128 GEN_XXSEL_ROW(0x1F)
10130 GEN_XX3FORM_DM(xxpermdi
, 0x08, 0x01),
10132 #undef GEN_DFP_T_A_B_Rc
10133 #undef GEN_DFP_BF_A_B
10134 #undef GEN_DFP_BF_A_DCM
10135 #undef GEN_DFP_T_B_U32_U32_Rc
10136 #undef GEN_DFP_T_A_B_I32_Rc
10137 #undef GEN_DFP_T_B_Rc
10138 #undef GEN_DFP_T_FPR_I32_Rc
10140 #define _GEN_DFP_LONG(name, op1, op2, mask) \
10141 GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
10143 #define _GEN_DFP_LONGx2(name, op1, op2, mask) \
10144 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10145 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10147 #define _GEN_DFP_LONGx4(name, op1, op2, mask) \
10148 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10149 GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10150 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10151 GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10153 #define _GEN_DFP_QUAD(name, op1, op2, mask) \
10154 GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
10156 #define _GEN_DFP_QUADx2(name, op1, op2, mask) \
10157 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10158 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10160 #define _GEN_DFP_QUADx4(name, op1, op2, mask) \
10161 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10162 GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10163 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10164 GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10166 #define GEN_DFP_T_A_B_Rc(name, op1, op2) \
10167 _GEN_DFP_LONG(name, op1, op2, 0x00000000)
10169 #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
10170 _GEN_DFP_QUAD(name, op1, op2, 0x00210800)
10172 #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
10173 _GEN_DFP_QUAD(name, op1, op2, 0x00200800)
10175 #define GEN_DFP_T_B_Rc(name, op1, op2) \
10176 _GEN_DFP_LONG(name, op1, op2, 0x001F0000)
10178 #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
10179 _GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
10181 #define GEN_DFP_Tp_B_Rc(name, op1, op2) \
10182 _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
10184 #define GEN_DFP_T_Bp_Rc(name, op1, op2) \
10185 _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
10187 #define GEN_DFP_BF_A_B(name, op1, op2) \
10188 _GEN_DFP_LONG(name, op1, op2, 0x00000001)
10190 #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
10191 _GEN_DFP_QUAD(name, op1, op2, 0x00610801)
10193 #define GEN_DFP_BF_A_Bp(name, op1, op2) \
10194 _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
10196 #define GEN_DFP_BF_A_DCM(name, op1, op2) \
10197 _GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
10199 #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
10200 _GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
10202 #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
10203 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
10205 #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
10206 _GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
10208 #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
10209 _GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
10211 #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
10212 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
10214 #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
10215 _GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
10217 #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
10218 _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
10220 #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
10221 _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
10223 #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
10224 _GEN_DFP_LONG(name, op1, op2, 0x00070000)
10226 #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
10227 _GEN_DFP_QUAD(name, op1, op2, 0x00270800)
10229 #define GEN_DFP_S_T_B_Rc(name, op1, op2) \
10230 _GEN_DFP_LONG(name, op1, op2, 0x000F0000)
10232 #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
10233 _GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
10235 #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
10236 _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
10238 #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
10239 _GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
10241 GEN_DFP_T_A_B_Rc(dadd
, 0x02, 0x00),
10242 GEN_DFP_Tp_Ap_Bp_Rc(daddq
, 0x02, 0x00),
10243 GEN_DFP_T_A_B_Rc(dsub
, 0x02, 0x10),
10244 GEN_DFP_Tp_Ap_Bp_Rc(dsubq
, 0x02, 0x10),
10245 GEN_DFP_T_A_B_Rc(dmul
, 0x02, 0x01),
10246 GEN_DFP_Tp_Ap_Bp_Rc(dmulq
, 0x02, 0x01),
10247 GEN_DFP_T_A_B_Rc(ddiv
, 0x02, 0x11),
10248 GEN_DFP_Tp_Ap_Bp_Rc(ddivq
, 0x02, 0x11),
10249 GEN_DFP_BF_A_B(dcmpu
, 0x02, 0x14),
10250 GEN_DFP_BF_Ap_Bp(dcmpuq
, 0x02, 0x14),
10251 GEN_DFP_BF_A_B(dcmpo
, 0x02, 0x04),
10252 GEN_DFP_BF_Ap_Bp(dcmpoq
, 0x02, 0x04),
10253 GEN_DFP_BF_A_DCM(dtstdc
, 0x02, 0x06),
10254 GEN_DFP_BF_Ap_DCM(dtstdcq
, 0x02, 0x06),
10255 GEN_DFP_BF_A_DCM(dtstdg
, 0x02, 0x07),
10256 GEN_DFP_BF_Ap_DCM(dtstdgq
, 0x02, 0x07),
10257 GEN_DFP_BF_A_B(dtstex
, 0x02, 0x05),
10258 GEN_DFP_BF_Ap_Bp(dtstexq
, 0x02, 0x05),
10259 GEN_DFP_BF_A_B(dtstsf
, 0x02, 0x15),
10260 GEN_DFP_BF_A_Bp(dtstsfq
, 0x02, 0x15),
10261 GEN_DFP_TE_T_B_RMC_Rc(dquai
, 0x03, 0x02),
10262 GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq
, 0x03, 0x02),
10263 GEN_DFP_T_A_B_RMC_Rc(dqua
, 0x03, 0x00),
10264 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq
, 0x03, 0x00),
10265 GEN_DFP_T_A_B_RMC_Rc(drrnd
, 0x03, 0x01),
10266 GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq
, 0x03, 0x01),
10267 GEN_DFP_R_T_B_RMC_Rc(drintx
, 0x03, 0x03),
10268 GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq
, 0x03, 0x03),
10269 GEN_DFP_R_T_B_RMC_Rc(drintn
, 0x03, 0x07),
10270 GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq
, 0x03, 0x07),
10271 GEN_DFP_T_B_Rc(dctdp
, 0x02, 0x08),
10272 GEN_DFP_Tp_B_Rc(dctqpq
, 0x02, 0x08),
10273 GEN_DFP_T_B_Rc(drsp
, 0x02, 0x18),
10274 GEN_DFP_Tp_Bp_Rc(drdpq
, 0x02, 0x18),
10275 GEN_DFP_T_B_Rc(dcffix
, 0x02, 0x19),
10276 GEN_DFP_Tp_B_Rc(dcffixq
, 0x02, 0x19),
10277 GEN_DFP_T_B_Rc(dctfix
, 0x02, 0x09),
10278 GEN_DFP_T_Bp_Rc(dctfixq
, 0x02, 0x09),
10279 GEN_DFP_SP_T_B_Rc(ddedpd
, 0x02, 0x0a),
10280 GEN_DFP_SP_Tp_Bp_Rc(ddedpdq
, 0x02, 0x0a),
10281 GEN_DFP_S_T_B_Rc(denbcd
, 0x02, 0x1a),
10282 GEN_DFP_S_Tp_Bp_Rc(denbcdq
, 0x02, 0x1a),
10283 GEN_DFP_T_B_Rc(dxex
, 0x02, 0x0b),
10284 GEN_DFP_T_Bp_Rc(dxexq
, 0x02, 0x0b),
10285 GEN_DFP_T_A_B_Rc(diex
, 0x02, 0x1b),
10286 GEN_DFP_Tp_A_Bp_Rc(diexq
, 0x02, 0x1b),
10287 GEN_DFP_T_A_SH_Rc(dscli
, 0x02, 0x02),
10288 GEN_DFP_Tp_Ap_SH_Rc(dscliq
, 0x02, 0x02),
10289 GEN_DFP_T_A_SH_Rc(dscri
, 0x02, 0x03),
10290 GEN_DFP_Tp_Ap_SH_Rc(dscriq
, 0x02, 0x03),
10293 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
10294 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
10295 GEN_SPE(evaddw
, speundef
, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
10296 GEN_SPE(evaddiw
, speundef
, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
10297 GEN_SPE(evsubfw
, speundef
, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
10298 GEN_SPE(evsubifw
, speundef
, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
10299 GEN_SPE(evabs
, evneg
, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
),
10300 GEN_SPE(evextsb
, evextsh
, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
),
10301 GEN_SPE(evrndw
, evcntlzw
, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
),
10302 GEN_SPE(evcntlsw
, brinc
, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE
),
10303 GEN_SPE(evmra
, speundef
, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE
),
10304 GEN_SPE(speundef
, evand
, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
),
10305 GEN_SPE(evandc
, speundef
, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
10306 GEN_SPE(evxor
, evor
, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
10307 GEN_SPE(evnor
, eveqv
, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
10308 GEN_SPE(evmwumi
, evmwsmi
, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE
),
10309 GEN_SPE(evmwumia
, evmwsmia
, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE
),
10310 GEN_SPE(evmwumiaa
, evmwsmiaa
, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE
),
10311 GEN_SPE(speundef
, evorc
, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
),
10312 GEN_SPE(evnand
, speundef
, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
10313 GEN_SPE(evsrwu
, evsrws
, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
10314 GEN_SPE(evsrwiu
, evsrwis
, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
10315 GEN_SPE(evslw
, speundef
, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
10316 GEN_SPE(evslwi
, speundef
, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
10317 GEN_SPE(evrlw
, evsplati
, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE
),
10318 GEN_SPE(evrlwi
, evsplatfi
, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE
),
10319 GEN_SPE(evmergehi
, evmergelo
, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
10320 GEN_SPE(evmergehilo
, evmergelohi
, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
10321 GEN_SPE(evcmpgtu
, evcmpgts
, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE
),
10322 GEN_SPE(evcmpltu
, evcmplts
, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE
),
10323 GEN_SPE(evcmpeq
, speundef
, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE
),
10325 GEN_SPE(evfsadd
, evfssub
, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
10326 GEN_SPE(evfsabs
, evfsnabs
, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
),
10327 GEN_SPE(evfsneg
, speundef
, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
),
10328 GEN_SPE(evfsmul
, evfsdiv
, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
10329 GEN_SPE(evfscmpgt
, evfscmplt
, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
10330 GEN_SPE(evfscmpeq
, speundef
, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
10331 GEN_SPE(evfscfui
, evfscfsi
, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
10332 GEN_SPE(evfscfuf
, evfscfsf
, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
10333 GEN_SPE(evfsctui
, evfsctsi
, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
10334 GEN_SPE(evfsctuf
, evfsctsf
, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
10335 GEN_SPE(evfsctuiz
, speundef
, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
10336 GEN_SPE(evfsctsiz
, speundef
, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
10337 GEN_SPE(evfststgt
, evfststlt
, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
10338 GEN_SPE(evfststeq
, speundef
, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
10340 GEN_SPE(efsadd
, efssub
, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
10341 GEN_SPE(efsabs
, efsnabs
, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
),
10342 GEN_SPE(efsneg
, speundef
, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
),
10343 GEN_SPE(efsmul
, efsdiv
, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
10344 GEN_SPE(efscmpgt
, efscmplt
, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
10345 GEN_SPE(efscmpeq
, efscfd
, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE
),
10346 GEN_SPE(efscfui
, efscfsi
, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
10347 GEN_SPE(efscfuf
, efscfsf
, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
10348 GEN_SPE(efsctui
, efsctsi
, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
10349 GEN_SPE(efsctuf
, efsctsf
, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
10350 GEN_SPE(efsctuiz
, speundef
, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
10351 GEN_SPE(efsctsiz
, speundef
, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
10352 GEN_SPE(efststgt
, efststlt
, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
10353 GEN_SPE(efststeq
, speundef
, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
10355 GEN_SPE(efdadd
, efdsub
, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
),
10356 GEN_SPE(efdcfuid
, efdcfsid
, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
10357 GEN_SPE(efdabs
, efdnabs
, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE
),
10358 GEN_SPE(efdneg
, speundef
, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
10359 GEN_SPE(efdmul
, efddiv
, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
),
10360 GEN_SPE(efdctuidz
, efdctsidz
, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
10361 GEN_SPE(efdcmpgt
, efdcmplt
, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
),
10362 GEN_SPE(efdcmpeq
, efdcfs
, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE
),
10363 GEN_SPE(efdcfui
, efdcfsi
, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
10364 GEN_SPE(efdcfuf
, efdcfsf
, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
10365 GEN_SPE(efdctui
, efdctsi
, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
10366 GEN_SPE(efdctuf
, efdctsf
, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
10367 GEN_SPE(efdctuiz
, speundef
, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
10368 GEN_SPE(efdctsiz
, speundef
, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
10369 GEN_SPE(efdtstgt
, efdtstlt
, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
),
10370 GEN_SPE(efdtsteq
, speundef
, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
10372 #undef GEN_SPEOP_LDST
10373 #define GEN_SPEOP_LDST(name, opc2, sh) \
10374 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
10375 GEN_SPEOP_LDST(evldd
, 0x00, 3),
10376 GEN_SPEOP_LDST(evldw
, 0x01, 3),
10377 GEN_SPEOP_LDST(evldh
, 0x02, 3),
10378 GEN_SPEOP_LDST(evlhhesplat
, 0x04, 1),
10379 GEN_SPEOP_LDST(evlhhousplat
, 0x06, 1),
10380 GEN_SPEOP_LDST(evlhhossplat
, 0x07, 1),
10381 GEN_SPEOP_LDST(evlwhe
, 0x08, 2),
10382 GEN_SPEOP_LDST(evlwhou
, 0x0A, 2),
10383 GEN_SPEOP_LDST(evlwhos
, 0x0B, 2),
10384 GEN_SPEOP_LDST(evlwwsplat
, 0x0C, 2),
10385 GEN_SPEOP_LDST(evlwhsplat
, 0x0E, 2),
10387 GEN_SPEOP_LDST(evstdd
, 0x10, 3),
10388 GEN_SPEOP_LDST(evstdw
, 0x11, 3),
10389 GEN_SPEOP_LDST(evstdh
, 0x12, 3),
10390 GEN_SPEOP_LDST(evstwhe
, 0x18, 2),
10391 GEN_SPEOP_LDST(evstwho
, 0x1A, 2),
10392 GEN_SPEOP_LDST(evstwwe
, 0x1C, 2),
10393 GEN_SPEOP_LDST(evstwwo
, 0x1E, 2),
10395 GEN_HANDLER2_E(tbegin
, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
10396 PPC_NONE
, PPC2_TM
),
10397 GEN_HANDLER2_E(tend
, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
10398 PPC_NONE
, PPC2_TM
),
10399 GEN_HANDLER2_E(tabort
, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
10400 PPC_NONE
, PPC2_TM
),
10401 GEN_HANDLER2_E(tabortwc
, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
10402 PPC_NONE
, PPC2_TM
),
10403 GEN_HANDLER2_E(tabortwci
, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
10404 PPC_NONE
, PPC2_TM
),
10405 GEN_HANDLER2_E(tabortdc
, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
10406 PPC_NONE
, PPC2_TM
),
10407 GEN_HANDLER2_E(tabortdci
, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
10408 PPC_NONE
, PPC2_TM
),
10409 GEN_HANDLER2_E(tsr
, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
10410 PPC_NONE
, PPC2_TM
),
10411 GEN_HANDLER2_E(tcheck
, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
10412 PPC_NONE
, PPC2_TM
),
10413 GEN_HANDLER2_E(treclaim
, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
10414 PPC_NONE
, PPC2_TM
),
10415 GEN_HANDLER2_E(trechkpt
, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
10416 PPC_NONE
, PPC2_TM
),
10419 #include "helper_regs.h"
10420 #include "translate_init.c"
10422 /*****************************************************************************/
10423 /* Misc PowerPC helpers */
10424 void ppc_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
10430 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
10431 CPUPPCState
*env
= &cpu
->env
;
10434 cpu_fprintf(f
, "NIP " TARGET_FMT_lx
" LR " TARGET_FMT_lx
" CTR "
10435 TARGET_FMT_lx
" XER " TARGET_FMT_lx
" CPU#%d\n",
10436 env
->nip
, env
->lr
, env
->ctr
, cpu_read_xer(env
),
10438 cpu_fprintf(f
, "MSR " TARGET_FMT_lx
" HID0 " TARGET_FMT_lx
" HF "
10439 TARGET_FMT_lx
" iidx %d didx %d\n",
10440 env
->msr
, env
->spr
[SPR_HID0
],
10441 env
->hflags
, env
->immu_idx
, env
->dmmu_idx
);
10442 #if !defined(NO_TIMER_DUMP)
10443 cpu_fprintf(f
, "TB %08" PRIu32
" %08" PRIu64
10444 #if !defined(CONFIG_USER_ONLY)
10448 cpu_ppc_load_tbu(env
), cpu_ppc_load_tbl(env
)
10449 #if !defined(CONFIG_USER_ONLY)
10450 , cpu_ppc_load_decr(env
)
10454 for (i
= 0; i
< 32; i
++) {
10455 if ((i
& (RGPL
- 1)) == 0)
10456 cpu_fprintf(f
, "GPR%02d", i
);
10457 cpu_fprintf(f
, " %016" PRIx64
, ppc_dump_gpr(env
, i
));
10458 if ((i
& (RGPL
- 1)) == (RGPL
- 1))
10459 cpu_fprintf(f
, "\n");
10461 cpu_fprintf(f
, "CR ");
10462 for (i
= 0; i
< 8; i
++)
10463 cpu_fprintf(f
, "%01x", env
->crf
[i
]);
10464 cpu_fprintf(f
, " [");
10465 for (i
= 0; i
< 8; i
++) {
10467 if (env
->crf
[i
] & 0x08)
10469 else if (env
->crf
[i
] & 0x04)
10471 else if (env
->crf
[i
] & 0x02)
10473 cpu_fprintf(f
, " %c%c", a
, env
->crf
[i
] & 0x01 ? 'O' : ' ');
10475 cpu_fprintf(f
, " ] RES " TARGET_FMT_lx
"\n",
10476 env
->reserve_addr
);
10477 for (i
= 0; i
< 32; i
++) {
10478 if ((i
& (RFPL
- 1)) == 0)
10479 cpu_fprintf(f
, "FPR%02d", i
);
10480 cpu_fprintf(f
, " %016" PRIx64
, *((uint64_t *)&env
->fpr
[i
]));
10481 if ((i
& (RFPL
- 1)) == (RFPL
- 1))
10482 cpu_fprintf(f
, "\n");
10484 cpu_fprintf(f
, "FPSCR " TARGET_FMT_lx
"\n", env
->fpscr
);
10485 #if !defined(CONFIG_USER_ONLY)
10486 cpu_fprintf(f
, " SRR0 " TARGET_FMT_lx
" SRR1 " TARGET_FMT_lx
10487 " PVR " TARGET_FMT_lx
" VRSAVE " TARGET_FMT_lx
"\n",
10488 env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
],
10489 env
->spr
[SPR_PVR
], env
->spr
[SPR_VRSAVE
]);
10491 cpu_fprintf(f
, "SPRG0 " TARGET_FMT_lx
" SPRG1 " TARGET_FMT_lx
10492 " SPRG2 " TARGET_FMT_lx
" SPRG3 " TARGET_FMT_lx
"\n",
10493 env
->spr
[SPR_SPRG0
], env
->spr
[SPR_SPRG1
],
10494 env
->spr
[SPR_SPRG2
], env
->spr
[SPR_SPRG3
]);
10496 cpu_fprintf(f
, "SPRG4 " TARGET_FMT_lx
" SPRG5 " TARGET_FMT_lx
10497 " SPRG6 " TARGET_FMT_lx
" SPRG7 " TARGET_FMT_lx
"\n",
10498 env
->spr
[SPR_SPRG4
], env
->spr
[SPR_SPRG5
],
10499 env
->spr
[SPR_SPRG6
], env
->spr
[SPR_SPRG7
]);
10501 #if defined(TARGET_PPC64)
10502 if (env
->excp_model
== POWERPC_EXCP_POWER7
||
10503 env
->excp_model
== POWERPC_EXCP_POWER8
) {
10504 cpu_fprintf(f
, "HSRR0 " TARGET_FMT_lx
" HSRR1 " TARGET_FMT_lx
"\n",
10505 env
->spr
[SPR_HSRR0
], env
->spr
[SPR_HSRR1
]);
10508 if (env
->excp_model
== POWERPC_EXCP_BOOKE
) {
10509 cpu_fprintf(f
, "CSRR0 " TARGET_FMT_lx
" CSRR1 " TARGET_FMT_lx
10510 " MCSRR0 " TARGET_FMT_lx
" MCSRR1 " TARGET_FMT_lx
"\n",
10511 env
->spr
[SPR_BOOKE_CSRR0
], env
->spr
[SPR_BOOKE_CSRR1
],
10512 env
->spr
[SPR_BOOKE_MCSRR0
], env
->spr
[SPR_BOOKE_MCSRR1
]);
10514 cpu_fprintf(f
, " TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
10515 " ESR " TARGET_FMT_lx
" DEAR " TARGET_FMT_lx
"\n",
10516 env
->spr
[SPR_BOOKE_TCR
], env
->spr
[SPR_BOOKE_TSR
],
10517 env
->spr
[SPR_BOOKE_ESR
], env
->spr
[SPR_BOOKE_DEAR
]);
10519 cpu_fprintf(f
, " PIR " TARGET_FMT_lx
" DECAR " TARGET_FMT_lx
10520 " IVPR " TARGET_FMT_lx
" EPCR " TARGET_FMT_lx
"\n",
10521 env
->spr
[SPR_BOOKE_PIR
], env
->spr
[SPR_BOOKE_DECAR
],
10522 env
->spr
[SPR_BOOKE_IVPR
], env
->spr
[SPR_BOOKE_EPCR
]);
10524 cpu_fprintf(f
, " MCSR " TARGET_FMT_lx
" SPRG8 " TARGET_FMT_lx
10525 " EPR " TARGET_FMT_lx
"\n",
10526 env
->spr
[SPR_BOOKE_MCSR
], env
->spr
[SPR_BOOKE_SPRG8
],
10527 env
->spr
[SPR_BOOKE_EPR
]);
10530 cpu_fprintf(f
, " MCAR " TARGET_FMT_lx
" PID1 " TARGET_FMT_lx
10531 " PID2 " TARGET_FMT_lx
" SVR " TARGET_FMT_lx
"\n",
10532 env
->spr
[SPR_Exxx_MCAR
], env
->spr
[SPR_BOOKE_PID1
],
10533 env
->spr
[SPR_BOOKE_PID2
], env
->spr
[SPR_E500_SVR
]);
10536 * IVORs are left out as they are large and do not change often --
10537 * they can be read with "p $ivor0", "p $ivor1", etc.
10541 #if defined(TARGET_PPC64)
10542 if (env
->flags
& POWERPC_FLAG_CFAR
) {
10543 cpu_fprintf(f
, " CFAR " TARGET_FMT_lx
"\n", env
->cfar
);
10547 switch (env
->mmu_model
) {
10548 case POWERPC_MMU_32B
:
10549 case POWERPC_MMU_601
:
10550 case POWERPC_MMU_SOFT_6xx
:
10551 case POWERPC_MMU_SOFT_74xx
:
10552 #if defined(TARGET_PPC64)
10553 case POWERPC_MMU_64B
:
10554 case POWERPC_MMU_2_03
:
10555 case POWERPC_MMU_2_06
:
10556 case POWERPC_MMU_2_06a
:
10557 case POWERPC_MMU_2_07
:
10558 case POWERPC_MMU_2_07a
:
10560 cpu_fprintf(f
, " SDR1 " TARGET_FMT_lx
" DAR " TARGET_FMT_lx
10561 " DSISR " TARGET_FMT_lx
"\n", env
->spr
[SPR_SDR1
],
10562 env
->spr
[SPR_DAR
], env
->spr
[SPR_DSISR
]);
10564 case POWERPC_MMU_BOOKE206
:
10565 cpu_fprintf(f
, " MAS0 " TARGET_FMT_lx
" MAS1 " TARGET_FMT_lx
10566 " MAS2 " TARGET_FMT_lx
" MAS3 " TARGET_FMT_lx
"\n",
10567 env
->spr
[SPR_BOOKE_MAS0
], env
->spr
[SPR_BOOKE_MAS1
],
10568 env
->spr
[SPR_BOOKE_MAS2
], env
->spr
[SPR_BOOKE_MAS3
]);
10570 cpu_fprintf(f
, " MAS4 " TARGET_FMT_lx
" MAS6 " TARGET_FMT_lx
10571 " MAS7 " TARGET_FMT_lx
" PID " TARGET_FMT_lx
"\n",
10572 env
->spr
[SPR_BOOKE_MAS4
], env
->spr
[SPR_BOOKE_MAS6
],
10573 env
->spr
[SPR_BOOKE_MAS7
], env
->spr
[SPR_BOOKE_PID
]);
10575 cpu_fprintf(f
, "MMUCFG " TARGET_FMT_lx
" TLB0CFG " TARGET_FMT_lx
10576 " TLB1CFG " TARGET_FMT_lx
"\n",
10577 env
->spr
[SPR_MMUCFG
], env
->spr
[SPR_BOOKE_TLB0CFG
],
10578 env
->spr
[SPR_BOOKE_TLB1CFG
]);
10589 void ppc_cpu_dump_statistics(CPUState
*cs
, FILE*f
,
10590 fprintf_function cpu_fprintf
, int flags
)
10592 #if defined(DO_PPC_STATISTICS)
10593 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
10594 opc_handler_t
**t1
, **t2
, **t3
, *handler
;
10597 t1
= cpu
->env
.opcodes
;
10598 for (op1
= 0; op1
< 64; op1
++) {
10600 if (is_indirect_opcode(handler
)) {
10601 t2
= ind_table(handler
);
10602 for (op2
= 0; op2
< 32; op2
++) {
10604 if (is_indirect_opcode(handler
)) {
10605 t3
= ind_table(handler
);
10606 for (op3
= 0; op3
< 32; op3
++) {
10608 if (handler
->count
== 0)
10610 cpu_fprintf(f
, "%02x %02x %02x (%02x %04d) %16s: "
10611 "%016" PRIx64
" %" PRId64
"\n",
10612 op1
, op2
, op3
, op1
, (op3
<< 5) | op2
,
10614 handler
->count
, handler
->count
);
10617 if (handler
->count
== 0)
10619 cpu_fprintf(f
, "%02x %02x (%02x %04d) %16s: "
10620 "%016" PRIx64
" %" PRId64
"\n",
10621 op1
, op2
, op1
, op2
, handler
->oname
,
10622 handler
->count
, handler
->count
);
10626 if (handler
->count
== 0)
10628 cpu_fprintf(f
, "%02x (%02x ) %16s: %016" PRIx64
10630 op1
, op1
, handler
->oname
,
10631 handler
->count
, handler
->count
);
10637 /*****************************************************************************/
10638 void gen_intermediate_code(CPUPPCState
*env
, struct TranslationBlock
*tb
)
10640 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
10641 CPUState
*cs
= CPU(cpu
);
10642 DisasContext ctx
, *ctxp
= &ctx
;
10643 opc_handler_t
**table
, *handler
;
10644 target_ulong pc_start
;
10649 ctx
.nip
= pc_start
;
10651 ctx
.exception
= POWERPC_EXCP_NONE
;
10652 ctx
.spr_cb
= env
->spr_cb
;
10654 ctx
.mem_idx
= env
->dmmu_idx
;
10656 #if !defined(CONFIG_USER_ONLY)
10657 ctx
.hv
= msr_hv
|| !env
->has_hv_mode
;
10659 ctx
.insns_flags
= env
->insns_flags
;
10660 ctx
.insns_flags2
= env
->insns_flags2
;
10661 ctx
.access_type
= -1;
10662 ctx
.le_mode
= !!(env
->hflags
& (1 << MSR_LE
));
10663 ctx
.default_tcg_memop_mask
= ctx
.le_mode
? MO_LE
: MO_BE
;
10664 #if defined(TARGET_PPC64)
10665 ctx
.sf_mode
= msr_is_64bit(env
, env
->msr
);
10666 ctx
.has_cfar
= !!(env
->flags
& POWERPC_FLAG_CFAR
);
10668 if (env
->mmu_model
== POWERPC_MMU_32B
||
10669 env
->mmu_model
== POWERPC_MMU_601
||
10670 (env
->mmu_model
& POWERPC_MMU_64B
))
10671 ctx
.lazy_tlb_flush
= true;
10673 ctx
.fpu_enabled
= !!msr_fp
;
10674 if ((env
->flags
& POWERPC_FLAG_SPE
) && msr_spe
)
10675 ctx
.spe_enabled
= !!msr_spe
;
10677 ctx
.spe_enabled
= false;
10678 if ((env
->flags
& POWERPC_FLAG_VRE
) && msr_vr
)
10679 ctx
.altivec_enabled
= !!msr_vr
;
10681 ctx
.altivec_enabled
= false;
10682 if ((env
->flags
& POWERPC_FLAG_VSX
) && msr_vsx
) {
10683 ctx
.vsx_enabled
= !!msr_vsx
;
10685 ctx
.vsx_enabled
= false;
10687 #if defined(TARGET_PPC64)
10688 if ((env
->flags
& POWERPC_FLAG_TM
) && msr_tm
) {
10689 ctx
.tm_enabled
= !!msr_tm
;
10691 ctx
.tm_enabled
= false;
10694 if ((env
->flags
& POWERPC_FLAG_SE
) && msr_se
)
10695 ctx
.singlestep_enabled
= CPU_SINGLE_STEP
;
10697 ctx
.singlestep_enabled
= 0;
10698 if ((env
->flags
& POWERPC_FLAG_BE
) && msr_be
)
10699 ctx
.singlestep_enabled
|= CPU_BRANCH_STEP
;
10700 if (unlikely(cs
->singlestep_enabled
)) {
10701 ctx
.singlestep_enabled
|= GDBSTUB_SINGLE_STEP
;
10703 #if defined (DO_SINGLE_STEP) && 0
10704 /* Single step trace mode */
10708 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
10709 if (max_insns
== 0) {
10710 max_insns
= CF_COUNT_MASK
;
10712 if (max_insns
> TCG_MAX_INSNS
) {
10713 max_insns
= TCG_MAX_INSNS
;
10717 tcg_clear_temp_count();
10718 /* Set env in case of segfault during code fetch */
10719 while (ctx
.exception
== POWERPC_EXCP_NONE
&& !tcg_op_buf_full()) {
10720 tcg_gen_insn_start(ctx
.nip
);
10723 if (unlikely(cpu_breakpoint_test(cs
, ctx
.nip
, BP_ANY
))) {
10724 gen_debug_exception(ctxp
);
10725 /* The address covered by the breakpoint must be included in
10726 [tb->pc, tb->pc + tb->size) in order to for it to be
10727 properly cleared -- thus we increment the PC here so that
10728 the logic setting tb->size below does the right thing. */
10733 LOG_DISAS("----------------\n");
10734 LOG_DISAS("nip=" TARGET_FMT_lx
" super=%d ir=%d\n",
10735 ctx
.nip
, ctx
.mem_idx
, (int)msr_ir
);
10736 if (num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
))
10738 if (unlikely(need_byteswap(&ctx
))) {
10739 ctx
.opcode
= bswap32(cpu_ldl_code(env
, ctx
.nip
));
10741 ctx
.opcode
= cpu_ldl_code(env
, ctx
.nip
);
10743 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
10744 ctx
.opcode
, opc1(ctx
.opcode
), opc2(ctx
.opcode
),
10745 opc3(ctx
.opcode
), opc4(ctx
.opcode
),
10746 ctx
.le_mode
? "little" : "big");
10748 table
= env
->opcodes
;
10749 handler
= table
[opc1(ctx
.opcode
)];
10750 if (is_indirect_opcode(handler
)) {
10751 table
= ind_table(handler
);
10752 handler
= table
[opc2(ctx
.opcode
)];
10753 if (is_indirect_opcode(handler
)) {
10754 table
= ind_table(handler
);
10755 handler
= table
[opc3(ctx
.opcode
)];
10756 if (is_indirect_opcode(handler
)) {
10757 table
= ind_table(handler
);
10758 handler
= table
[opc4(ctx
.opcode
)];
10762 /* Is opcode *REALLY* valid ? */
10763 if (unlikely(handler
->handler
== &gen_invalid
)) {
10764 qemu_log_mask(LOG_GUEST_ERROR
, "invalid/unsupported opcode: "
10765 "%02x - %02x - %02x - %02x (%08x) "
10766 TARGET_FMT_lx
" %d\n",
10767 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
10768 opc3(ctx
.opcode
), opc4(ctx
.opcode
),
10769 ctx
.opcode
, ctx
.nip
- 4, (int)msr_ir
);
10773 if (unlikely(handler
->type
& (PPC_SPE
| PPC_SPE_SINGLE
| PPC_SPE_DOUBLE
) && Rc(ctx
.opcode
))) {
10774 inval
= handler
->inval2
;
10776 inval
= handler
->inval1
;
10779 if (unlikely((ctx
.opcode
& inval
) != 0)) {
10780 qemu_log_mask(LOG_GUEST_ERROR
, "invalid bits: %08x for opcode: "
10781 "%02x - %02x - %02x - %02x (%08x) "
10782 TARGET_FMT_lx
"\n", ctx
.opcode
& inval
,
10783 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
10784 opc3(ctx
.opcode
), opc4(ctx
.opcode
),
10785 ctx
.opcode
, ctx
.nip
- 4);
10786 gen_inval_exception(ctxp
, POWERPC_EXCP_INVAL_INVAL
);
10790 (*(handler
->handler
))(&ctx
);
10791 #if defined(DO_PPC_STATISTICS)
10794 /* Check trace mode exceptions */
10795 if (unlikely(ctx
.singlestep_enabled
& CPU_SINGLE_STEP
&&
10796 (ctx
.nip
<= 0x100 || ctx
.nip
> 0xF00) &&
10797 ctx
.exception
!= POWERPC_SYSCALL
&&
10798 ctx
.exception
!= POWERPC_EXCP_TRAP
&&
10799 ctx
.exception
!= POWERPC_EXCP_BRANCH
)) {
10800 gen_exception(ctxp
, POWERPC_EXCP_TRACE
);
10801 } else if (unlikely(((ctx
.nip
& (TARGET_PAGE_SIZE
- 1)) == 0) ||
10802 (cs
->singlestep_enabled
) ||
10804 num_insns
>= max_insns
)) {
10805 /* if we reach a page boundary or are single stepping, stop
10810 if (tcg_check_temp_count()) {
10811 fprintf(stderr
, "Opcode %02x %02x %02x %02x (%08x) leaked "
10812 "temporaries\n", opc1(ctx
.opcode
), opc2(ctx
.opcode
),
10813 opc3(ctx
.opcode
), opc4(ctx
.opcode
), ctx
.opcode
);
10817 if (tb
->cflags
& CF_LAST_IO
)
10819 if (ctx
.exception
== POWERPC_EXCP_NONE
) {
10820 gen_goto_tb(&ctx
, 0, ctx
.nip
);
10821 } else if (ctx
.exception
!= POWERPC_EXCP_BRANCH
) {
10822 if (unlikely(cs
->singlestep_enabled
)) {
10823 gen_debug_exception(ctxp
);
10825 /* Generate the return instruction */
10826 tcg_gen_exit_tb(0);
10828 gen_tb_end(tb
, num_insns
);
10830 tb
->size
= ctx
.nip
- pc_start
;
10831 tb
->icount
= num_insns
;
10833 #if defined(DEBUG_DISAS)
10834 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)
10835 && qemu_log_in_addr_range(pc_start
)) {
10837 flags
= env
->bfd_mach
;
10838 flags
|= ctx
.le_mode
<< 16;
10839 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
10840 log_target_disas(cs
, pc_start
, ctx
.nip
- pc_start
, flags
);
10846 void restore_state_to_opc(CPUPPCState
*env
, TranslationBlock
*tb
,
10847 target_ulong
*data
)
10849 env
->nip
= data
[0];