4 * Copyright (c) 2009 Ulrich Hecht
5 * Copyright (c) 2010 Alexander Graf
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 /* #define DEBUG_INLINE_BRANCHES */
22 #define S390X_DEBUG_DISAS
23 /* #define S390X_DEBUG_DISAS_VERBOSE */
25 #ifdef S390X_DEBUG_DISAS_VERBOSE
26 # define LOG_DISAS(...) qemu_log(__VA_ARGS__)
28 # define LOG_DISAS(...) do { } while (0)
32 #include "disas/disas.h"
35 #include "qemu/host-utils.h"
37 /* global register indexes */
38 static TCGv_ptr cpu_env
;
40 #include "exec/gen-icount.h"
46 /* Information that (most) every instruction needs to manipulate. */
47 typedef struct DisasContext DisasContext
;
48 typedef struct DisasInsn DisasInsn
;
49 typedef struct DisasFields DisasFields
;
52 struct TranslationBlock
*tb
;
53 const DisasInsn
*insn
;
57 bool singlestep_enabled
;
61 /* Information carried about a condition to be evaluated. */
68 struct { TCGv_i64 a
, b
; } s64
;
69 struct { TCGv_i32 a
, b
; } s32
;
75 static void gen_op_calc_cc(DisasContext
*s
);
77 #ifdef DEBUG_INLINE_BRANCHES
78 static uint64_t inline_branch_hit
[CC_OP_MAX
];
79 static uint64_t inline_branch_miss
[CC_OP_MAX
];
82 static inline void debug_insn(uint64_t insn
)
84 LOG_DISAS("insn: 0x%" PRIx64
"\n", insn
);
87 static inline uint64_t pc_to_link_info(DisasContext
*s
, uint64_t pc
)
89 if (!(s
->tb
->flags
& FLAG_MASK_64
)) {
90 if (s
->tb
->flags
& FLAG_MASK_32
) {
91 return pc
| 0x80000000;
97 void cpu_dump_state(CPUS390XState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
102 if (env
->cc_op
> 3) {
103 cpu_fprintf(f
, "PSW=mask %016" PRIx64
" addr %016" PRIx64
" cc %15s\n",
104 env
->psw
.mask
, env
->psw
.addr
, cc_name(env
->cc_op
));
106 cpu_fprintf(f
, "PSW=mask %016" PRIx64
" addr %016" PRIx64
" cc %02x\n",
107 env
->psw
.mask
, env
->psw
.addr
, env
->cc_op
);
110 for (i
= 0; i
< 16; i
++) {
111 cpu_fprintf(f
, "R%02d=%016" PRIx64
, i
, env
->regs
[i
]);
113 cpu_fprintf(f
, "\n");
119 for (i
= 0; i
< 16; i
++) {
120 cpu_fprintf(f
, "F%02d=%016" PRIx64
, i
, env
->fregs
[i
].ll
);
122 cpu_fprintf(f
, "\n");
128 #ifndef CONFIG_USER_ONLY
129 for (i
= 0; i
< 16; i
++) {
130 cpu_fprintf(f
, "C%02d=%016" PRIx64
, i
, env
->cregs
[i
]);
132 cpu_fprintf(f
, "\n");
139 #ifdef DEBUG_INLINE_BRANCHES
140 for (i
= 0; i
< CC_OP_MAX
; i
++) {
141 cpu_fprintf(f
, " %15s = %10ld\t%10ld\n", cc_name(i
),
142 inline_branch_miss
[i
], inline_branch_hit
[i
]);
146 cpu_fprintf(f
, "\n");
149 static TCGv_i64 psw_addr
;
150 static TCGv_i64 psw_mask
;
152 static TCGv_i32 cc_op
;
153 static TCGv_i64 cc_src
;
154 static TCGv_i64 cc_dst
;
155 static TCGv_i64 cc_vr
;
157 static char cpu_reg_names
[32][4];
158 static TCGv_i64 regs
[16];
159 static TCGv_i64 fregs
[16];
161 static uint8_t gen_opc_cc_op
[OPC_BUF_SIZE
];
163 void s390x_translate_init(void)
167 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
168 psw_addr
= tcg_global_mem_new_i64(TCG_AREG0
,
169 offsetof(CPUS390XState
, psw
.addr
),
171 psw_mask
= tcg_global_mem_new_i64(TCG_AREG0
,
172 offsetof(CPUS390XState
, psw
.mask
),
175 cc_op
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUS390XState
, cc_op
),
177 cc_src
= tcg_global_mem_new_i64(TCG_AREG0
, offsetof(CPUS390XState
, cc_src
),
179 cc_dst
= tcg_global_mem_new_i64(TCG_AREG0
, offsetof(CPUS390XState
, cc_dst
),
181 cc_vr
= tcg_global_mem_new_i64(TCG_AREG0
, offsetof(CPUS390XState
, cc_vr
),
184 for (i
= 0; i
< 16; i
++) {
185 snprintf(cpu_reg_names
[i
], sizeof(cpu_reg_names
[0]), "r%d", i
);
186 regs
[i
] = tcg_global_mem_new(TCG_AREG0
,
187 offsetof(CPUS390XState
, regs
[i
]),
191 for (i
= 0; i
< 16; i
++) {
192 snprintf(cpu_reg_names
[i
+ 16], sizeof(cpu_reg_names
[0]), "f%d", i
);
193 fregs
[i
] = tcg_global_mem_new(TCG_AREG0
,
194 offsetof(CPUS390XState
, fregs
[i
].d
),
195 cpu_reg_names
[i
+ 16]);
198 /* register helpers */
203 static inline TCGv_i64
load_reg(int reg
)
205 TCGv_i64 r
= tcg_temp_new_i64();
206 tcg_gen_mov_i64(r
, regs
[reg
]);
210 static inline TCGv_i64
load_freg(int reg
)
212 TCGv_i64 r
= tcg_temp_new_i64();
213 tcg_gen_mov_i64(r
, fregs
[reg
]);
217 static inline TCGv_i32
load_freg32(int reg
)
219 TCGv_i32 r
= tcg_temp_new_i32();
220 #if HOST_LONG_BITS == 32
221 tcg_gen_mov_i32(r
, TCGV_HIGH(fregs
[reg
]));
223 tcg_gen_shri_i64(MAKE_TCGV_I64(GET_TCGV_I32(r
)), fregs
[reg
], 32);
228 static inline TCGv_i64
load_freg32_i64(int reg
)
230 TCGv_i64 r
= tcg_temp_new_i64();
231 tcg_gen_shri_i64(r
, fregs
[reg
], 32);
235 static inline TCGv_i32
load_reg32(int reg
)
237 TCGv_i32 r
= tcg_temp_new_i32();
238 tcg_gen_trunc_i64_i32(r
, regs
[reg
]);
242 static inline TCGv_i64
load_reg32_i64(int reg
)
244 TCGv_i64 r
= tcg_temp_new_i64();
245 tcg_gen_ext32s_i64(r
, regs
[reg
]);
249 static inline void store_reg(int reg
, TCGv_i64 v
)
251 tcg_gen_mov_i64(regs
[reg
], v
);
254 static inline void store_freg(int reg
, TCGv_i64 v
)
256 tcg_gen_mov_i64(fregs
[reg
], v
);
259 static inline void store_reg32(int reg
, TCGv_i32 v
)
261 /* 32 bit register writes keep the upper half */
262 #if HOST_LONG_BITS == 32
263 tcg_gen_mov_i32(TCGV_LOW(regs
[reg
]), v
);
265 tcg_gen_deposit_i64(regs
[reg
], regs
[reg
],
266 MAKE_TCGV_I64(GET_TCGV_I32(v
)), 0, 32);
270 static inline void store_reg32_i64(int reg
, TCGv_i64 v
)
272 /* 32 bit register writes keep the upper half */
273 tcg_gen_deposit_i64(regs
[reg
], regs
[reg
], v
, 0, 32);
276 static inline void store_reg32h_i64(int reg
, TCGv_i64 v
)
278 tcg_gen_deposit_i64(regs
[reg
], regs
[reg
], v
, 32, 32);
281 static inline void store_freg32(int reg
, TCGv_i32 v
)
283 /* 32 bit register writes keep the lower half */
284 #if HOST_LONG_BITS == 32
285 tcg_gen_mov_i32(TCGV_HIGH(fregs
[reg
]), v
);
287 tcg_gen_deposit_i64(fregs
[reg
], fregs
[reg
],
288 MAKE_TCGV_I64(GET_TCGV_I32(v
)), 32, 32);
292 static inline void store_freg32_i64(int reg
, TCGv_i64 v
)
294 tcg_gen_deposit_i64(fregs
[reg
], fregs
[reg
], v
, 32, 32);
297 static inline void return_low128(TCGv_i64 dest
)
299 tcg_gen_ld_i64(dest
, cpu_env
, offsetof(CPUS390XState
, retxl
));
302 static inline void update_psw_addr(DisasContext
*s
)
305 tcg_gen_movi_i64(psw_addr
, s
->pc
);
308 static inline void potential_page_fault(DisasContext
*s
)
310 #ifndef CONFIG_USER_ONLY
316 static inline uint64_t ld_code2(CPUS390XState
*env
, uint64_t pc
)
318 return (uint64_t)cpu_lduw_code(env
, pc
);
321 static inline uint64_t ld_code4(CPUS390XState
*env
, uint64_t pc
)
323 return (uint64_t)(uint32_t)cpu_ldl_code(env
, pc
);
326 static inline uint64_t ld_code6(CPUS390XState
*env
, uint64_t pc
)
328 return (ld_code2(env
, pc
) << 32) | ld_code4(env
, pc
+ 2);
331 static inline int get_mem_index(DisasContext
*s
)
333 switch (s
->tb
->flags
& FLAG_MASK_ASC
) {
334 case PSW_ASC_PRIMARY
>> 32:
336 case PSW_ASC_SECONDARY
>> 32:
338 case PSW_ASC_HOME
>> 32:
346 static void gen_exception(int excp
)
348 TCGv_i32 tmp
= tcg_const_i32(excp
);
349 gen_helper_exception(cpu_env
, tmp
);
350 tcg_temp_free_i32(tmp
);
353 static void gen_program_exception(DisasContext
*s
, int code
)
357 /* Remember what pgm exeption this was. */
358 tmp
= tcg_const_i32(code
);
359 tcg_gen_st_i32(tmp
, cpu_env
, offsetof(CPUS390XState
, int_pgm_code
));
360 tcg_temp_free_i32(tmp
);
362 tmp
= tcg_const_i32(s
->next_pc
- s
->pc
);
363 tcg_gen_st_i32(tmp
, cpu_env
, offsetof(CPUS390XState
, int_pgm_ilen
));
364 tcg_temp_free_i32(tmp
);
366 /* Advance past instruction. */
373 /* Trigger exception. */
374 gen_exception(EXCP_PGM
);
377 s
->is_jmp
= DISAS_EXCP
;
380 static inline void gen_illegal_opcode(DisasContext
*s
)
382 gen_program_exception(s
, PGM_SPECIFICATION
);
385 static inline void check_privileged(DisasContext
*s
)
387 if (s
->tb
->flags
& (PSW_MASK_PSTATE
>> 32)) {
388 gen_program_exception(s
, PGM_PRIVILEGED
);
392 static TCGv_i64
get_address(DisasContext
*s
, int x2
, int b2
, int d2
)
396 /* 31-bitify the immediate part; register contents are dealt with below */
397 if (!(s
->tb
->flags
& FLAG_MASK_64
)) {
403 tmp
= tcg_const_i64(d2
);
404 tcg_gen_add_i64(tmp
, tmp
, regs
[x2
]);
409 tcg_gen_add_i64(tmp
, tmp
, regs
[b2
]);
413 tmp
= tcg_const_i64(d2
);
414 tcg_gen_add_i64(tmp
, tmp
, regs
[b2
]);
419 tmp
= tcg_const_i64(d2
);
422 /* 31-bit mode mask if there are values loaded from registers */
423 if (!(s
->tb
->flags
& FLAG_MASK_64
) && (x2
|| b2
)) {
424 tcg_gen_andi_i64(tmp
, tmp
, 0x7fffffffUL
);
430 static void gen_op_movi_cc(DisasContext
*s
, uint32_t val
)
432 s
->cc_op
= CC_OP_CONST0
+ val
;
435 static void gen_op_update1_cc_i64(DisasContext
*s
, enum cc_op op
, TCGv_i64 dst
)
437 tcg_gen_discard_i64(cc_src
);
438 tcg_gen_mov_i64(cc_dst
, dst
);
439 tcg_gen_discard_i64(cc_vr
);
443 static void gen_op_update1_cc_i32(DisasContext
*s
, enum cc_op op
, TCGv_i32 dst
)
445 tcg_gen_discard_i64(cc_src
);
446 tcg_gen_extu_i32_i64(cc_dst
, dst
);
447 tcg_gen_discard_i64(cc_vr
);
451 static void gen_op_update2_cc_i64(DisasContext
*s
, enum cc_op op
, TCGv_i64 src
,
454 tcg_gen_mov_i64(cc_src
, src
);
455 tcg_gen_mov_i64(cc_dst
, dst
);
456 tcg_gen_discard_i64(cc_vr
);
460 static void gen_op_update2_cc_i32(DisasContext
*s
, enum cc_op op
, TCGv_i32 src
,
463 tcg_gen_extu_i32_i64(cc_src
, src
);
464 tcg_gen_extu_i32_i64(cc_dst
, dst
);
465 tcg_gen_discard_i64(cc_vr
);
469 static void gen_op_update3_cc_i64(DisasContext
*s
, enum cc_op op
, TCGv_i64 src
,
470 TCGv_i64 dst
, TCGv_i64 vr
)
472 tcg_gen_mov_i64(cc_src
, src
);
473 tcg_gen_mov_i64(cc_dst
, dst
);
474 tcg_gen_mov_i64(cc_vr
, vr
);
478 static inline void set_cc_nz_u32(DisasContext
*s
, TCGv_i32 val
)
480 gen_op_update1_cc_i32(s
, CC_OP_NZ
, val
);
483 static inline void set_cc_nz_u64(DisasContext
*s
, TCGv_i64 val
)
485 gen_op_update1_cc_i64(s
, CC_OP_NZ
, val
);
488 static inline void gen_set_cc_nz_f32(DisasContext
*s
, TCGv_i64 val
)
490 gen_op_update1_cc_i64(s
, CC_OP_NZ_F32
, val
);
493 static inline void gen_set_cc_nz_f64(DisasContext
*s
, TCGv_i64 val
)
495 gen_op_update1_cc_i64(s
, CC_OP_NZ_F64
, val
);
498 static inline void gen_set_cc_nz_f128(DisasContext
*s
, TCGv_i64 vh
, TCGv_i64 vl
)
500 gen_op_update2_cc_i64(s
, CC_OP_NZ_F128
, vh
, vl
);
503 static inline void cmp_32(DisasContext
*s
, TCGv_i32 v1
, TCGv_i32 v2
,
506 gen_op_update2_cc_i32(s
, cond
, v1
, v2
);
509 static inline void cmp_64(DisasContext
*s
, TCGv_i64 v1
, TCGv_i64 v2
,
512 gen_op_update2_cc_i64(s
, cond
, v1
, v2
);
515 static inline void cmp_s32(DisasContext
*s
, TCGv_i32 v1
, TCGv_i32 v2
)
517 cmp_32(s
, v1
, v2
, CC_OP_LTGT_32
);
520 static inline void cmp_u32(DisasContext
*s
, TCGv_i32 v1
, TCGv_i32 v2
)
522 cmp_32(s
, v1
, v2
, CC_OP_LTUGTU_32
);
525 static inline void cmp_s32c(DisasContext
*s
, TCGv_i32 v1
, int32_t v2
)
527 /* XXX optimize for the constant? put it in s? */
528 TCGv_i32 tmp
= tcg_const_i32(v2
);
529 cmp_32(s
, v1
, tmp
, CC_OP_LTGT_32
);
530 tcg_temp_free_i32(tmp
);
533 static inline void cmp_u32c(DisasContext
*s
, TCGv_i32 v1
, uint32_t v2
)
535 TCGv_i32 tmp
= tcg_const_i32(v2
);
536 cmp_32(s
, v1
, tmp
, CC_OP_LTUGTU_32
);
537 tcg_temp_free_i32(tmp
);
540 static inline void cmp_s64(DisasContext
*s
, TCGv_i64 v1
, TCGv_i64 v2
)
542 cmp_64(s
, v1
, v2
, CC_OP_LTGT_64
);
545 static inline void cmp_u64(DisasContext
*s
, TCGv_i64 v1
, TCGv_i64 v2
)
547 cmp_64(s
, v1
, v2
, CC_OP_LTUGTU_64
);
550 static inline void cmp_s64c(DisasContext
*s
, TCGv_i64 v1
, int64_t v2
)
552 TCGv_i64 tmp
= tcg_const_i64(v2
);
554 tcg_temp_free_i64(tmp
);
557 static inline void cmp_u64c(DisasContext
*s
, TCGv_i64 v1
, uint64_t v2
)
559 TCGv_i64 tmp
= tcg_const_i64(v2
);
561 tcg_temp_free_i64(tmp
);
564 static inline void set_cc_s32(DisasContext
*s
, TCGv_i32 val
)
566 gen_op_update1_cc_i32(s
, CC_OP_LTGT0_32
, val
);
569 static inline void set_cc_s64(DisasContext
*s
, TCGv_i64 val
)
571 gen_op_update1_cc_i64(s
, CC_OP_LTGT0_64
, val
);
574 /* CC value is in env->cc_op */
575 static inline void set_cc_static(DisasContext
*s
)
577 tcg_gen_discard_i64(cc_src
);
578 tcg_gen_discard_i64(cc_dst
);
579 tcg_gen_discard_i64(cc_vr
);
580 s
->cc_op
= CC_OP_STATIC
;
583 static inline void gen_op_set_cc_op(DisasContext
*s
)
585 if (s
->cc_op
!= CC_OP_DYNAMIC
&& s
->cc_op
!= CC_OP_STATIC
) {
586 tcg_gen_movi_i32(cc_op
, s
->cc_op
);
590 static inline void gen_update_cc_op(DisasContext
*s
)
595 /* calculates cc into cc_op */
596 static void gen_op_calc_cc(DisasContext
*s
)
598 TCGv_i32 local_cc_op
= tcg_const_i32(s
->cc_op
);
599 TCGv_i64 dummy
= tcg_const_i64(0);
606 /* s->cc_op is the cc value */
607 tcg_gen_movi_i32(cc_op
, s
->cc_op
- CC_OP_CONST0
);
610 /* env->cc_op already is the cc value */
625 gen_helper_calc_cc(cc_op
, cpu_env
, local_cc_op
, dummy
, cc_dst
, dummy
);
630 case CC_OP_LTUGTU_32
:
631 case CC_OP_LTUGTU_64
:
638 gen_helper_calc_cc(cc_op
, cpu_env
, local_cc_op
, cc_src
, cc_dst
, dummy
);
653 gen_helper_calc_cc(cc_op
, cpu_env
, local_cc_op
, cc_src
, cc_dst
, cc_vr
);
656 /* unknown operation - assume 3 arguments and cc_op in env */
657 gen_helper_calc_cc(cc_op
, cpu_env
, cc_op
, cc_src
, cc_dst
, cc_vr
);
663 tcg_temp_free_i32(local_cc_op
);
664 tcg_temp_free_i64(dummy
);
666 /* We now have cc in cc_op as constant */
670 static inline void decode_rr(DisasContext
*s
, uint64_t insn
, int *r1
, int *r2
)
674 *r1
= (insn
>> 4) & 0xf;
678 static inline TCGv_i64
decode_rx(DisasContext
*s
, uint64_t insn
, int *r1
,
679 int *x2
, int *b2
, int *d2
)
683 *r1
= (insn
>> 20) & 0xf;
684 *x2
= (insn
>> 16) & 0xf;
685 *b2
= (insn
>> 12) & 0xf;
688 return get_address(s
, *x2
, *b2
, *d2
);
691 static inline void decode_rs(DisasContext
*s
, uint64_t insn
, int *r1
, int *r3
,
696 *r1
= (insn
>> 20) & 0xf;
698 *r3
= (insn
>> 16) & 0xf;
699 *b2
= (insn
>> 12) & 0xf;
703 static inline TCGv_i64
decode_si(DisasContext
*s
, uint64_t insn
, int *i2
,
708 *i2
= (insn
>> 16) & 0xff;
709 *b1
= (insn
>> 12) & 0xf;
712 return get_address(s
, 0, *b1
, *d1
);
715 static int use_goto_tb(DisasContext
*s
, uint64_t dest
)
717 /* NOTE: we handle the case where the TB spans two pages here */
718 return (((dest
& TARGET_PAGE_MASK
) == (s
->tb
->pc
& TARGET_PAGE_MASK
)
719 || (dest
& TARGET_PAGE_MASK
) == ((s
->pc
- 1) & TARGET_PAGE_MASK
))
720 && !s
->singlestep_enabled
721 && !(s
->tb
->cflags
& CF_LAST_IO
));
724 static inline void gen_goto_tb(DisasContext
*s
, int tb_num
, target_ulong pc
)
728 if (use_goto_tb(s
, pc
)) {
729 tcg_gen_goto_tb(tb_num
);
730 tcg_gen_movi_i64(psw_addr
, pc
);
731 tcg_gen_exit_tb((tcg_target_long
)s
->tb
+ tb_num
);
733 /* jump to another page: currently not optimized */
734 tcg_gen_movi_i64(psw_addr
, pc
);
739 static inline void account_noninline_branch(DisasContext
*s
, int cc_op
)
741 #ifdef DEBUG_INLINE_BRANCHES
742 inline_branch_miss
[cc_op
]++;
746 static inline void account_inline_branch(DisasContext
*s
, int cc_op
)
748 #ifdef DEBUG_INLINE_BRANCHES
749 inline_branch_hit
[cc_op
]++;
753 /* Table of mask values to comparison codes, given a comparison as input.
754 For a true comparison CC=3 will never be set, but we treat this
755 conservatively for possible use when CC=3 indicates overflow. */
756 static const TCGCond ltgt_cond
[16] = {
757 TCG_COND_NEVER
, TCG_COND_NEVER
, /* | | | x */
758 TCG_COND_GT
, TCG_COND_NEVER
, /* | | GT | x */
759 TCG_COND_LT
, TCG_COND_NEVER
, /* | LT | | x */
760 TCG_COND_NE
, TCG_COND_NEVER
, /* | LT | GT | x */
761 TCG_COND_EQ
, TCG_COND_NEVER
, /* EQ | | | x */
762 TCG_COND_GE
, TCG_COND_NEVER
, /* EQ | | GT | x */
763 TCG_COND_LE
, TCG_COND_NEVER
, /* EQ | LT | | x */
764 TCG_COND_ALWAYS
, TCG_COND_ALWAYS
, /* EQ | LT | GT | x */
767 /* Table of mask values to comparison codes, given a logic op as input.
768 For such, only CC=0 and CC=1 should be possible. */
769 static const TCGCond nz_cond
[16] = {
771 TCG_COND_NEVER
, TCG_COND_NEVER
, TCG_COND_NEVER
, TCG_COND_NEVER
,
773 TCG_COND_NE
, TCG_COND_NE
, TCG_COND_NE
, TCG_COND_NE
,
775 TCG_COND_EQ
, TCG_COND_EQ
, TCG_COND_EQ
, TCG_COND_EQ
,
776 /* EQ | NE | x | x */
777 TCG_COND_ALWAYS
, TCG_COND_ALWAYS
, TCG_COND_ALWAYS
, TCG_COND_ALWAYS
,
780 /* Interpret MASK in terms of S->CC_OP, and fill in C with all the
781 details required to generate a TCG comparison. */
782 static void disas_jcc(DisasContext
*s
, DisasCompare
*c
, uint32_t mask
)
785 enum cc_op old_cc_op
= s
->cc_op
;
787 if (mask
== 15 || mask
== 0) {
788 c
->cond
= (mask
? TCG_COND_ALWAYS
: TCG_COND_NEVER
);
791 c
->g1
= c
->g2
= true;
796 /* Find the TCG condition for the mask + cc op. */
802 cond
= ltgt_cond
[mask
];
803 if (cond
== TCG_COND_NEVER
) {
806 account_inline_branch(s
, old_cc_op
);
809 case CC_OP_LTUGTU_32
:
810 case CC_OP_LTUGTU_64
:
811 cond
= tcg_unsigned_cond(ltgt_cond
[mask
]);
812 if (cond
== TCG_COND_NEVER
) {
815 account_inline_branch(s
, old_cc_op
);
819 cond
= nz_cond
[mask
];
820 if (cond
== TCG_COND_NEVER
) {
823 account_inline_branch(s
, old_cc_op
);
838 account_inline_branch(s
, old_cc_op
);
853 account_inline_branch(s
, old_cc_op
);
857 switch (mask
& 0xa) {
858 case 8: /* src == 0 -> no one bit found */
861 case 2: /* src != 0 -> one bit found */
867 account_inline_branch(s
, old_cc_op
);
872 /* Calculate cc value. */
877 /* Jump based on CC. We'll load up the real cond below;
878 the assignment here merely avoids a compiler warning. */
879 account_noninline_branch(s
, old_cc_op
);
880 old_cc_op
= CC_OP_STATIC
;
881 cond
= TCG_COND_NEVER
;
885 /* Load up the arguments of the comparison. */
887 c
->g1
= c
->g2
= false;
891 c
->u
.s32
.a
= tcg_temp_new_i32();
892 tcg_gen_trunc_i64_i32(c
->u
.s32
.a
, cc_dst
);
893 c
->u
.s32
.b
= tcg_const_i32(0);
896 case CC_OP_LTUGTU_32
:
898 c
->u
.s32
.a
= tcg_temp_new_i32();
899 tcg_gen_trunc_i64_i32(c
->u
.s32
.a
, cc_src
);
900 c
->u
.s32
.b
= tcg_temp_new_i32();
901 tcg_gen_trunc_i64_i32(c
->u
.s32
.b
, cc_dst
);
908 c
->u
.s64
.b
= tcg_const_i64(0);
912 case CC_OP_LTUGTU_64
:
915 c
->g1
= c
->g2
= true;
921 c
->u
.s64
.a
= tcg_temp_new_i64();
922 c
->u
.s64
.b
= tcg_const_i64(0);
923 tcg_gen_and_i64(c
->u
.s64
.a
, cc_src
, cc_dst
);
931 case 0x8 | 0x4 | 0x2: /* cc != 3 */
933 c
->u
.s32
.b
= tcg_const_i32(3);
935 case 0x8 | 0x4 | 0x1: /* cc != 2 */
937 c
->u
.s32
.b
= tcg_const_i32(2);
939 case 0x8 | 0x2 | 0x1: /* cc != 1 */
941 c
->u
.s32
.b
= tcg_const_i32(1);
943 case 0x8 | 0x2: /* cc == 0 ||Â cc == 2 => (cc & 1) == 0 */
946 c
->u
.s32
.a
= tcg_temp_new_i32();
947 c
->u
.s32
.b
= tcg_const_i32(0);
948 tcg_gen_andi_i32(c
->u
.s32
.a
, cc_op
, 1);
950 case 0x8 | 0x4: /* cc < 2 */
952 c
->u
.s32
.b
= tcg_const_i32(2);
954 case 0x8: /* cc == 0 */
956 c
->u
.s32
.b
= tcg_const_i32(0);
958 case 0x4 | 0x2 | 0x1: /* cc != 0 */
960 c
->u
.s32
.b
= tcg_const_i32(0);
962 case 0x4 | 0x1: /* cc == 1 ||Â cc == 3 => (cc & 1) != 0 */
965 c
->u
.s32
.a
= tcg_temp_new_i32();
966 c
->u
.s32
.b
= tcg_const_i32(0);
967 tcg_gen_andi_i32(c
->u
.s32
.a
, cc_op
, 1);
969 case 0x4: /* cc == 1 */
971 c
->u
.s32
.b
= tcg_const_i32(1);
973 case 0x2 | 0x1: /* cc > 1 */
975 c
->u
.s32
.b
= tcg_const_i32(1);
977 case 0x2: /* cc == 2 */
979 c
->u
.s32
.b
= tcg_const_i32(2);
981 case 0x1: /* cc == 3 */
983 c
->u
.s32
.b
= tcg_const_i32(3);
986 /* CC is masked by something else: (8 >> cc) & mask. */
989 c
->u
.s32
.a
= tcg_const_i32(8);
990 c
->u
.s32
.b
= tcg_const_i32(0);
991 tcg_gen_shr_i32(c
->u
.s32
.a
, c
->u
.s32
.a
, cc_op
);
992 tcg_gen_andi_i32(c
->u
.s32
.a
, c
->u
.s32
.a
, mask
);
1003 static void free_compare(DisasCompare
*c
)
1007 tcg_temp_free_i64(c
->u
.s64
.a
);
1009 tcg_temp_free_i32(c
->u
.s32
.a
);
1014 tcg_temp_free_i64(c
->u
.s64
.b
);
1016 tcg_temp_free_i32(c
->u
.s32
.b
);
1021 static void disas_b2(CPUS390XState
*env
, DisasContext
*s
, int op
,
1024 TCGv_i64 tmp
, tmp2
, tmp3
;
1025 TCGv_i32 tmp32_1
, tmp32_2
, tmp32_3
;
1027 #ifndef CONFIG_USER_ONLY
1031 r1
= (insn
>> 4) & 0xf;
1034 LOG_DISAS("disas_b2: op 0x%x r1 %d r2 %d\n", op
, r1
, r2
);
1037 case 0x22: /* IPM R1 [RRE] */
1038 tmp32_1
= tcg_const_i32(r1
);
1040 gen_helper_ipm(cpu_env
, cc_op
, tmp32_1
);
1041 tcg_temp_free_i32(tmp32_1
);
1043 case 0x41: /* CKSM R1,R2 [RRE] */
1044 tmp32_1
= tcg_const_i32(r1
);
1045 tmp32_2
= tcg_const_i32(r2
);
1046 potential_page_fault(s
);
1047 gen_helper_cksm(cpu_env
, tmp32_1
, tmp32_2
);
1048 tcg_temp_free_i32(tmp32_1
);
1049 tcg_temp_free_i32(tmp32_2
);
1050 gen_op_movi_cc(s
, 0);
1052 case 0x4e: /* SAR R1,R2 [RRE] */
1053 tmp32_1
= load_reg32(r2
);
1054 tcg_gen_st_i32(tmp32_1
, cpu_env
, offsetof(CPUS390XState
, aregs
[r1
]));
1055 tcg_temp_free_i32(tmp32_1
);
1057 case 0x4f: /* EAR R1,R2 [RRE] */
1058 tmp32_1
= tcg_temp_new_i32();
1059 tcg_gen_ld_i32(tmp32_1
, cpu_env
, offsetof(CPUS390XState
, aregs
[r2
]));
1060 store_reg32(r1
, tmp32_1
);
1061 tcg_temp_free_i32(tmp32_1
);
1063 case 0x54: /* MVPG R1,R2 [RRE] */
1065 tmp2
= load_reg(r1
);
1066 tmp3
= load_reg(r2
);
1067 potential_page_fault(s
);
1068 gen_helper_mvpg(cpu_env
, tmp
, tmp2
, tmp3
);
1069 tcg_temp_free_i64(tmp
);
1070 tcg_temp_free_i64(tmp2
);
1071 tcg_temp_free_i64(tmp3
);
1072 /* XXX check CCO bit and set CC accordingly */
1073 gen_op_movi_cc(s
, 0);
1075 case 0x55: /* MVST R1,R2 [RRE] */
1076 tmp32_1
= load_reg32(0);
1077 tmp32_2
= tcg_const_i32(r1
);
1078 tmp32_3
= tcg_const_i32(r2
);
1079 potential_page_fault(s
);
1080 gen_helper_mvst(cpu_env
, tmp32_1
, tmp32_2
, tmp32_3
);
1081 tcg_temp_free_i32(tmp32_1
);
1082 tcg_temp_free_i32(tmp32_2
);
1083 tcg_temp_free_i32(tmp32_3
);
1084 gen_op_movi_cc(s
, 1);
1086 case 0x5d: /* CLST R1,R2 [RRE] */
1087 tmp32_1
= load_reg32(0);
1088 tmp32_2
= tcg_const_i32(r1
);
1089 tmp32_3
= tcg_const_i32(r2
);
1090 potential_page_fault(s
);
1091 gen_helper_clst(cc_op
, cpu_env
, tmp32_1
, tmp32_2
, tmp32_3
);
1093 tcg_temp_free_i32(tmp32_1
);
1094 tcg_temp_free_i32(tmp32_2
);
1095 tcg_temp_free_i32(tmp32_3
);
1097 case 0x5e: /* SRST R1,R2 [RRE] */
1098 tmp32_1
= load_reg32(0);
1099 tmp32_2
= tcg_const_i32(r1
);
1100 tmp32_3
= tcg_const_i32(r2
);
1101 potential_page_fault(s
);
1102 gen_helper_srst(cc_op
, cpu_env
, tmp32_1
, tmp32_2
, tmp32_3
);
1104 tcg_temp_free_i32(tmp32_1
);
1105 tcg_temp_free_i32(tmp32_2
);
1106 tcg_temp_free_i32(tmp32_3
);
1109 #ifndef CONFIG_USER_ONLY
1110 case 0x02: /* STIDP D2(B2) [S] */
1112 check_privileged(s
);
1113 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1114 tmp
= get_address(s
, 0, b2
, d2
);
1115 potential_page_fault(s
);
1116 gen_helper_stidp(cpu_env
, tmp
);
1117 tcg_temp_free_i64(tmp
);
1119 case 0x04: /* SCK D2(B2) [S] */
1121 check_privileged(s
);
1122 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1123 tmp
= get_address(s
, 0, b2
, d2
);
1124 potential_page_fault(s
);
1125 gen_helper_sck(cc_op
, tmp
);
1127 tcg_temp_free_i64(tmp
);
1129 case 0x05: /* STCK D2(B2) [S] */
1131 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1132 tmp
= get_address(s
, 0, b2
, d2
);
1133 potential_page_fault(s
);
1134 gen_helper_stck(cc_op
, cpu_env
, tmp
);
1136 tcg_temp_free_i64(tmp
);
1138 case 0x06: /* SCKC D2(B2) [S] */
1139 /* Set Clock Comparator */
1140 check_privileged(s
);
1141 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1142 tmp
= get_address(s
, 0, b2
, d2
);
1143 potential_page_fault(s
);
1144 gen_helper_sckc(cpu_env
, tmp
);
1145 tcg_temp_free_i64(tmp
);
1147 case 0x07: /* STCKC D2(B2) [S] */
1148 /* Store Clock Comparator */
1149 check_privileged(s
);
1150 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1151 tmp
= get_address(s
, 0, b2
, d2
);
1152 potential_page_fault(s
);
1153 gen_helper_stckc(cpu_env
, tmp
);
1154 tcg_temp_free_i64(tmp
);
1156 case 0x08: /* SPT D2(B2) [S] */
1158 check_privileged(s
);
1159 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1160 tmp
= get_address(s
, 0, b2
, d2
);
1161 potential_page_fault(s
);
1162 gen_helper_spt(cpu_env
, tmp
);
1163 tcg_temp_free_i64(tmp
);
1165 case 0x09: /* STPT D2(B2) [S] */
1166 /* Store CPU Timer */
1167 check_privileged(s
);
1168 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1169 tmp
= get_address(s
, 0, b2
, d2
);
1170 potential_page_fault(s
);
1171 gen_helper_stpt(cpu_env
, tmp
);
1172 tcg_temp_free_i64(tmp
);
1174 case 0x0a: /* SPKA D2(B2) [S] */
1175 /* Set PSW Key from Address */
1176 check_privileged(s
);
1177 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1178 tmp
= get_address(s
, 0, b2
, d2
);
1179 tmp2
= tcg_temp_new_i64();
1180 tcg_gen_andi_i64(tmp2
, psw_mask
, ~PSW_MASK_KEY
);
1181 tcg_gen_shli_i64(tmp
, tmp
, PSW_SHIFT_KEY
- 4);
1182 tcg_gen_or_i64(psw_mask
, tmp2
, tmp
);
1183 tcg_temp_free_i64(tmp2
);
1184 tcg_temp_free_i64(tmp
);
1186 case 0x0d: /* PTLB [S] */
1188 check_privileged(s
);
1189 gen_helper_ptlb(cpu_env
);
1191 case 0x10: /* SPX D2(B2) [S] */
1192 /* Set Prefix Register */
1193 check_privileged(s
);
1194 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1195 tmp
= get_address(s
, 0, b2
, d2
);
1196 potential_page_fault(s
);
1197 gen_helper_spx(cpu_env
, tmp
);
1198 tcg_temp_free_i64(tmp
);
1200 case 0x11: /* STPX D2(B2) [S] */
1202 check_privileged(s
);
1203 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1204 tmp
= get_address(s
, 0, b2
, d2
);
1205 tmp2
= tcg_temp_new_i64();
1206 tcg_gen_ld_i64(tmp2
, cpu_env
, offsetof(CPUS390XState
, psa
));
1207 tcg_gen_qemu_st32(tmp2
, tmp
, get_mem_index(s
));
1208 tcg_temp_free_i64(tmp
);
1209 tcg_temp_free_i64(tmp2
);
1211 case 0x12: /* STAP D2(B2) [S] */
1212 /* Store CPU Address */
1213 check_privileged(s
);
1214 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1215 tmp
= get_address(s
, 0, b2
, d2
);
1216 tmp2
= tcg_temp_new_i64();
1217 tmp32_1
= tcg_temp_new_i32();
1218 tcg_gen_ld_i32(tmp32_1
, cpu_env
, offsetof(CPUS390XState
, cpu_num
));
1219 tcg_gen_extu_i32_i64(tmp2
, tmp32_1
);
1220 tcg_gen_qemu_st32(tmp2
, tmp
, get_mem_index(s
));
1221 tcg_temp_free_i64(tmp
);
1222 tcg_temp_free_i64(tmp2
);
1223 tcg_temp_free_i32(tmp32_1
);
1225 case 0x21: /* IPTE R1,R2 [RRE] */
1226 /* Invalidate PTE */
1227 check_privileged(s
);
1228 r1
= (insn
>> 4) & 0xf;
1231 tmp2
= load_reg(r2
);
1232 gen_helper_ipte(cpu_env
, tmp
, tmp2
);
1233 tcg_temp_free_i64(tmp
);
1234 tcg_temp_free_i64(tmp2
);
1236 case 0x29: /* ISKE R1,R2 [RRE] */
1237 /* Insert Storage Key Extended */
1238 check_privileged(s
);
1239 r1
= (insn
>> 4) & 0xf;
1242 tmp2
= tcg_temp_new_i64();
1243 gen_helper_iske(tmp2
, cpu_env
, tmp
);
1244 store_reg(r1
, tmp2
);
1245 tcg_temp_free_i64(tmp
);
1246 tcg_temp_free_i64(tmp2
);
1248 case 0x2a: /* RRBE R1,R2 [RRE] */
1249 /* Set Storage Key Extended */
1250 check_privileged(s
);
1251 r1
= (insn
>> 4) & 0xf;
1253 tmp32_1
= load_reg32(r1
);
1255 gen_helper_rrbe(cc_op
, cpu_env
, tmp32_1
, tmp
);
1257 tcg_temp_free_i32(tmp32_1
);
1258 tcg_temp_free_i64(tmp
);
1260 case 0x2b: /* SSKE R1,R2 [RRE] */
1261 /* Set Storage Key Extended */
1262 check_privileged(s
);
1263 r1
= (insn
>> 4) & 0xf;
1265 tmp32_1
= load_reg32(r1
);
1267 gen_helper_sske(cpu_env
, tmp32_1
, tmp
);
1268 tcg_temp_free_i32(tmp32_1
);
1269 tcg_temp_free_i64(tmp
);
1271 case 0x34: /* STCH ? */
1272 /* Store Subchannel */
1273 check_privileged(s
);
1274 gen_op_movi_cc(s
, 3);
1276 case 0x46: /* STURA R1,R2 [RRE] */
1277 /* Store Using Real Address */
1278 check_privileged(s
);
1279 r1
= (insn
>> 4) & 0xf;
1281 tmp32_1
= load_reg32(r1
);
1283 potential_page_fault(s
);
1284 gen_helper_stura(cpu_env
, tmp
, tmp32_1
);
1285 tcg_temp_free_i32(tmp32_1
);
1286 tcg_temp_free_i64(tmp
);
1288 case 0x50: /* CSP R1,R2 [RRE] */
1289 /* Compare And Swap And Purge */
1290 check_privileged(s
);
1291 r1
= (insn
>> 4) & 0xf;
1293 tmp32_1
= tcg_const_i32(r1
);
1294 tmp32_2
= tcg_const_i32(r2
);
1295 gen_helper_csp(cc_op
, cpu_env
, tmp32_1
, tmp32_2
);
1297 tcg_temp_free_i32(tmp32_1
);
1298 tcg_temp_free_i32(tmp32_2
);
1300 case 0x5f: /* CHSC ? */
1301 /* Channel Subsystem Call */
1302 check_privileged(s
);
1303 gen_op_movi_cc(s
, 3);
1305 case 0x78: /* STCKE D2(B2) [S] */
1306 /* Store Clock Extended */
1307 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1308 tmp
= get_address(s
, 0, b2
, d2
);
1309 potential_page_fault(s
);
1310 gen_helper_stcke(cc_op
, cpu_env
, tmp
);
1312 tcg_temp_free_i64(tmp
);
1314 case 0x79: /* SACF D2(B2) [S] */
1315 /* Set Address Space Control Fast */
1316 check_privileged(s
);
1317 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1318 tmp
= get_address(s
, 0, b2
, d2
);
1319 potential_page_fault(s
);
1320 gen_helper_sacf(cpu_env
, tmp
);
1321 tcg_temp_free_i64(tmp
);
1322 /* addressing mode has changed, so end the block */
1325 s
->is_jmp
= DISAS_JUMP
;
1327 case 0x7d: /* STSI D2,(B2) [S] */
1328 check_privileged(s
);
1329 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1330 tmp
= get_address(s
, 0, b2
, d2
);
1331 tmp32_1
= load_reg32(0);
1332 tmp32_2
= load_reg32(1);
1333 potential_page_fault(s
);
1334 gen_helper_stsi(cc_op
, cpu_env
, tmp
, tmp32_1
, tmp32_2
);
1336 tcg_temp_free_i64(tmp
);
1337 tcg_temp_free_i32(tmp32_1
);
1338 tcg_temp_free_i32(tmp32_2
);
1340 case 0xb1: /* STFL D2(B2) [S] */
1341 /* Store Facility List (CPU features) at 200 */
1342 check_privileged(s
);
1343 tmp2
= tcg_const_i64(0xc0000000);
1344 tmp
= tcg_const_i64(200);
1345 tcg_gen_qemu_st32(tmp2
, tmp
, get_mem_index(s
));
1346 tcg_temp_free_i64(tmp2
);
1347 tcg_temp_free_i64(tmp
);
1349 case 0xb2: /* LPSWE D2(B2) [S] */
1350 /* Load PSW Extended */
1351 check_privileged(s
);
1352 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1353 tmp
= get_address(s
, 0, b2
, d2
);
1354 tmp2
= tcg_temp_new_i64();
1355 tmp3
= tcg_temp_new_i64();
1356 tcg_gen_qemu_ld64(tmp2
, tmp
, get_mem_index(s
));
1357 tcg_gen_addi_i64(tmp
, tmp
, 8);
1358 tcg_gen_qemu_ld64(tmp3
, tmp
, get_mem_index(s
));
1359 gen_helper_load_psw(cpu_env
, tmp2
, tmp3
);
1360 /* we need to keep cc_op intact */
1361 s
->is_jmp
= DISAS_JUMP
;
1362 tcg_temp_free_i64(tmp
);
1363 tcg_temp_free_i64(tmp2
);
1364 tcg_temp_free_i64(tmp3
);
1366 case 0x20: /* SERVC R1,R2 [RRE] */
1367 /* SCLP Service call (PV hypercall) */
1368 check_privileged(s
);
1369 potential_page_fault(s
);
1370 tmp32_1
= load_reg32(r2
);
1372 gen_helper_servc(cc_op
, cpu_env
, tmp32_1
, tmp
);
1374 tcg_temp_free_i32(tmp32_1
);
1375 tcg_temp_free_i64(tmp
);
1379 LOG_DISAS("illegal b2 operation 0x%x\n", op
);
1380 gen_illegal_opcode(s
);
1385 static void disas_s390_insn(CPUS390XState
*env
, DisasContext
*s
)
1391 opc
= cpu_ldub_code(env
, s
->pc
);
1392 LOG_DISAS("opc 0x%x\n", opc
);
1396 insn
= ld_code4(env
, s
->pc
);
1397 op
= (insn
>> 16) & 0xff;
1398 disas_b2(env
, s
, op
, insn
);
1401 qemu_log_mask(LOG_UNIMP
, "unimplemented opcode 0x%x\n", opc
);
1402 gen_illegal_opcode(s
);
1407 /* ====================================================================== */
1408 /* Define the insn format enumeration. */
1409 #define F0(N) FMT_##N,
1410 #define F1(N, X1) F0(N)
1411 #define F2(N, X1, X2) F0(N)
1412 #define F3(N, X1, X2, X3) F0(N)
1413 #define F4(N, X1, X2, X3, X4) F0(N)
1414 #define F5(N, X1, X2, X3, X4, X5) F0(N)
1417 #include "insn-format.def"
1427 /* Define a structure to hold the decoded fields. We'll store each inside
1428 an array indexed by an enum. In order to conserve memory, we'll arrange
1429 for fields that do not exist at the same time to overlap, thus the "C"
1430 for compact. For checking purposes there is an "O" for original index
1431 as well that will be applied to availability bitmaps. */
1433 enum DisasFieldIndexO
{
1456 enum DisasFieldIndexC
{
1487 struct DisasFields
{
1490 unsigned presentC
:16;
1491 unsigned int presentO
;
1495 /* This is the way fields are to be accessed out of DisasFields. */
1496 #define have_field(S, F) have_field1((S), FLD_O_##F)
1497 #define get_field(S, F) get_field1((S), FLD_O_##F, FLD_C_##F)
1499 static bool have_field1(const DisasFields
*f
, enum DisasFieldIndexO c
)
1501 return (f
->presentO
>> c
) & 1;
1504 static int get_field1(const DisasFields
*f
, enum DisasFieldIndexO o
,
1505 enum DisasFieldIndexC c
)
1507 assert(have_field1(f
, o
));
1511 /* Describe the layout of each field in each format. */
1512 typedef struct DisasField
{
1514 unsigned int size
:8;
1515 unsigned int type
:2;
1516 unsigned int indexC
:6;
1517 enum DisasFieldIndexO indexO
:8;
1520 typedef struct DisasFormatInfo
{
1521 DisasField op
[NUM_C_FIELD
];
1524 #define R(N, B) { B, 4, 0, FLD_C_r##N, FLD_O_r##N }
1525 #define M(N, B) { B, 4, 0, FLD_C_m##N, FLD_O_m##N }
1526 #define BD(N, BB, BD) { BB, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1527 { BD, 12, 0, FLD_C_d##N, FLD_O_d##N }
1528 #define BXD(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1529 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
1530 { 20, 12, 0, FLD_C_d##N, FLD_O_d##N }
1531 #define BDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1532 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
1533 #define BXDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1534 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
1535 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
1536 #define I(N, B, S) { B, S, 1, FLD_C_i##N, FLD_O_i##N }
1537 #define L(N, B, S) { B, S, 0, FLD_C_l##N, FLD_O_l##N }
1539 #define F0(N) { { } },
1540 #define F1(N, X1) { { X1 } },
1541 #define F2(N, X1, X2) { { X1, X2 } },
1542 #define F3(N, X1, X2, X3) { { X1, X2, X3 } },
1543 #define F4(N, X1, X2, X3, X4) { { X1, X2, X3, X4 } },
1544 #define F5(N, X1, X2, X3, X4, X5) { { X1, X2, X3, X4, X5 } },
1546 static const DisasFormatInfo format_info
[] = {
1547 #include "insn-format.def"
1565 /* Generally, we'll extract operands into this structures, operate upon
1566 them, and store them back. See the "in1", "in2", "prep", "wout" sets
1567 of routines below for more details. */
1569 bool g_out
, g_out2
, g_in1
, g_in2
;
1570 TCGv_i64 out
, out2
, in1
, in2
;
1574 /* Return values from translate_one, indicating the state of the TB. */
1576 /* Continue the TB. */
1578 /* We have emitted one or more goto_tb. No fixup required. */
1580 /* We are not using a goto_tb (for whatever reason), but have updated
1581 the PC (for whatever reason), so there's no need to do it again on
1584 /* We are exiting the TB, but have neither emitted a goto_tb, nor
1585 updated the PC for the next instruction to be executed. */
1587 /* We are ending the TB with a noreturn function call, e.g. longjmp.
1588 No following code will be executed. */
1592 typedef enum DisasFacility
{
1593 FAC_Z
, /* zarch (default) */
1594 FAC_CASS
, /* compare and swap and store */
1595 FAC_CASS2
, /* compare and swap and store 2*/
1596 FAC_DFP
, /* decimal floating point */
1597 FAC_DFPR
, /* decimal floating point rounding */
1598 FAC_DO
, /* distinct operands */
1599 FAC_EE
, /* execute extensions */
1600 FAC_EI
, /* extended immediate */
1601 FAC_FPE
, /* floating point extension */
1602 FAC_FPSSH
, /* floating point support sign handling */
1603 FAC_FPRGR
, /* FPR-GR transfer */
1604 FAC_GIE
, /* general instructions extension */
1605 FAC_HFP_MA
, /* HFP multiply-and-add/subtract */
1606 FAC_HW
, /* high-word */
1607 FAC_IEEEE_SIM
, /* IEEE exception sumilation */
1608 FAC_LOC
, /* load/store on condition */
1609 FAC_LD
, /* long displacement */
1610 FAC_PC
, /* population count */
1611 FAC_SCF
, /* store clock fast */
1612 FAC_SFLE
, /* store facility list extended */
1618 DisasFacility fac
:6;
1622 void (*help_in1
)(DisasContext
*, DisasFields
*, DisasOps
*);
1623 void (*help_in2
)(DisasContext
*, DisasFields
*, DisasOps
*);
1624 void (*help_prep
)(DisasContext
*, DisasFields
*, DisasOps
*);
1625 void (*help_wout
)(DisasContext
*, DisasFields
*, DisasOps
*);
1626 void (*help_cout
)(DisasContext
*, DisasOps
*);
1627 ExitStatus (*help_op
)(DisasContext
*, DisasOps
*);
1632 /* ====================================================================== */
1633 /* Miscelaneous helpers, used by several operations. */
1635 static void help_l2_shift(DisasContext
*s
, DisasFields
*f
,
1636 DisasOps
*o
, int mask
)
1638 int b2
= get_field(f
, b2
);
1639 int d2
= get_field(f
, d2
);
1642 o
->in2
= tcg_const_i64(d2
& mask
);
1644 o
->in2
= get_address(s
, 0, b2
, d2
);
1645 tcg_gen_andi_i64(o
->in2
, o
->in2
, mask
);
1649 static ExitStatus
help_goto_direct(DisasContext
*s
, uint64_t dest
)
1651 if (dest
== s
->next_pc
) {
1654 if (use_goto_tb(s
, dest
)) {
1655 gen_update_cc_op(s
);
1657 tcg_gen_movi_i64(psw_addr
, dest
);
1658 tcg_gen_exit_tb((tcg_target_long
)s
->tb
);
1659 return EXIT_GOTO_TB
;
1661 tcg_gen_movi_i64(psw_addr
, dest
);
1662 return EXIT_PC_UPDATED
;
1666 static ExitStatus
help_branch(DisasContext
*s
, DisasCompare
*c
,
1667 bool is_imm
, int imm
, TCGv_i64 cdest
)
1670 uint64_t dest
= s
->pc
+ 2 * imm
;
1673 /* Take care of the special cases first. */
1674 if (c
->cond
== TCG_COND_NEVER
) {
1679 if (dest
== s
->next_pc
) {
1680 /* Branch to next. */
1684 if (c
->cond
== TCG_COND_ALWAYS
) {
1685 ret
= help_goto_direct(s
, dest
);
1689 if (TCGV_IS_UNUSED_I64(cdest
)) {
1690 /* E.g. bcr %r0 -> no branch. */
1694 if (c
->cond
== TCG_COND_ALWAYS
) {
1695 tcg_gen_mov_i64(psw_addr
, cdest
);
1696 ret
= EXIT_PC_UPDATED
;
1701 if (use_goto_tb(s
, s
->next_pc
)) {
1702 if (is_imm
&& use_goto_tb(s
, dest
)) {
1703 /* Both exits can use goto_tb. */
1704 gen_update_cc_op(s
);
1706 lab
= gen_new_label();
1708 tcg_gen_brcond_i64(c
->cond
, c
->u
.s64
.a
, c
->u
.s64
.b
, lab
);
1710 tcg_gen_brcond_i32(c
->cond
, c
->u
.s32
.a
, c
->u
.s32
.b
, lab
);
1713 /* Branch not taken. */
1715 tcg_gen_movi_i64(psw_addr
, s
->next_pc
);
1716 tcg_gen_exit_tb((tcg_target_long
)s
->tb
+ 0);
1721 tcg_gen_movi_i64(psw_addr
, dest
);
1722 tcg_gen_exit_tb((tcg_target_long
)s
->tb
+ 1);
1726 /* Fallthru can use goto_tb, but taken branch cannot. */
1727 /* Store taken branch destination before the brcond. This
1728 avoids having to allocate a new local temp to hold it.
1729 We'll overwrite this in the not taken case anyway. */
1731 tcg_gen_mov_i64(psw_addr
, cdest
);
1734 lab
= gen_new_label();
1736 tcg_gen_brcond_i64(c
->cond
, c
->u
.s64
.a
, c
->u
.s64
.b
, lab
);
1738 tcg_gen_brcond_i32(c
->cond
, c
->u
.s32
.a
, c
->u
.s32
.b
, lab
);
1741 /* Branch not taken. */
1742 gen_update_cc_op(s
);
1744 tcg_gen_movi_i64(psw_addr
, s
->next_pc
);
1745 tcg_gen_exit_tb((tcg_target_long
)s
->tb
+ 0);
1749 tcg_gen_movi_i64(psw_addr
, dest
);
1751 ret
= EXIT_PC_UPDATED
;
1754 /* Fallthru cannot use goto_tb. This by itself is vanishingly rare.
1755 Most commonly we're single-stepping or some other condition that
1756 disables all use of goto_tb. Just update the PC and exit. */
1758 TCGv_i64 next
= tcg_const_i64(s
->next_pc
);
1760 cdest
= tcg_const_i64(dest
);
1764 tcg_gen_movcond_i64(c
->cond
, psw_addr
, c
->u
.s64
.a
, c
->u
.s64
.b
,
1767 TCGv_i32 t0
= tcg_temp_new_i32();
1768 TCGv_i64 t1
= tcg_temp_new_i64();
1769 TCGv_i64 z
= tcg_const_i64(0);
1770 tcg_gen_setcond_i32(c
->cond
, t0
, c
->u
.s32
.a
, c
->u
.s32
.b
);
1771 tcg_gen_extu_i32_i64(t1
, t0
);
1772 tcg_temp_free_i32(t0
);
1773 tcg_gen_movcond_i64(TCG_COND_NE
, psw_addr
, t1
, z
, cdest
, next
);
1774 tcg_temp_free_i64(t1
);
1775 tcg_temp_free_i64(z
);
1779 tcg_temp_free_i64(cdest
);
1781 tcg_temp_free_i64(next
);
1783 ret
= EXIT_PC_UPDATED
;
1791 /* ====================================================================== */
1792 /* The operations. These perform the bulk of the work for any insn,
1793 usually after the operands have been loaded and output initialized. */
1795 static ExitStatus
op_abs(DisasContext
*s
, DisasOps
*o
)
1797 gen_helper_abs_i64(o
->out
, o
->in2
);
1801 static ExitStatus
op_absf32(DisasContext
*s
, DisasOps
*o
)
1803 tcg_gen_andi_i64(o
->out
, o
->in2
, 0x7fffffffull
);
1807 static ExitStatus
op_absf64(DisasContext
*s
, DisasOps
*o
)
1809 tcg_gen_andi_i64(o
->out
, o
->in2
, 0x7fffffffffffffffull
);
1813 static ExitStatus
op_absf128(DisasContext
*s
, DisasOps
*o
)
1815 tcg_gen_andi_i64(o
->out
, o
->in1
, 0x7fffffffffffffffull
);
1816 tcg_gen_mov_i64(o
->out2
, o
->in2
);
1820 static ExitStatus
op_add(DisasContext
*s
, DisasOps
*o
)
1822 tcg_gen_add_i64(o
->out
, o
->in1
, o
->in2
);
1826 static ExitStatus
op_addc(DisasContext
*s
, DisasOps
*o
)
1830 tcg_gen_add_i64(o
->out
, o
->in1
, o
->in2
);
1832 /* XXX possible optimization point */
1834 cc
= tcg_temp_new_i64();
1835 tcg_gen_extu_i32_i64(cc
, cc_op
);
1836 tcg_gen_shri_i64(cc
, cc
, 1);
1838 tcg_gen_add_i64(o
->out
, o
->out
, cc
);
1839 tcg_temp_free_i64(cc
);
1843 static ExitStatus
op_aeb(DisasContext
*s
, DisasOps
*o
)
1845 gen_helper_aeb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
1849 static ExitStatus
op_adb(DisasContext
*s
, DisasOps
*o
)
1851 gen_helper_adb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
1855 static ExitStatus
op_axb(DisasContext
*s
, DisasOps
*o
)
1857 gen_helper_axb(o
->out
, cpu_env
, o
->out
, o
->out2
, o
->in1
, o
->in2
);
1858 return_low128(o
->out2
);
1862 static ExitStatus
op_and(DisasContext
*s
, DisasOps
*o
)
1864 tcg_gen_and_i64(o
->out
, o
->in1
, o
->in2
);
1868 static ExitStatus
op_andi(DisasContext
*s
, DisasOps
*o
)
1870 int shift
= s
->insn
->data
& 0xff;
1871 int size
= s
->insn
->data
>> 8;
1872 uint64_t mask
= ((1ull << size
) - 1) << shift
;
1875 tcg_gen_shli_i64(o
->in2
, o
->in2
, shift
);
1876 tcg_gen_ori_i64(o
->in2
, o
->in2
, ~mask
);
1877 tcg_gen_and_i64(o
->out
, o
->in1
, o
->in2
);
1879 /* Produce the CC from only the bits manipulated. */
1880 tcg_gen_andi_i64(cc_dst
, o
->out
, mask
);
1881 set_cc_nz_u64(s
, cc_dst
);
1885 static ExitStatus
op_bas(DisasContext
*s
, DisasOps
*o
)
1887 tcg_gen_movi_i64(o
->out
, pc_to_link_info(s
, s
->next_pc
));
1888 if (!TCGV_IS_UNUSED_I64(o
->in2
)) {
1889 tcg_gen_mov_i64(psw_addr
, o
->in2
);
1890 return EXIT_PC_UPDATED
;
1896 static ExitStatus
op_basi(DisasContext
*s
, DisasOps
*o
)
1898 tcg_gen_movi_i64(o
->out
, pc_to_link_info(s
, s
->next_pc
));
1899 return help_goto_direct(s
, s
->pc
+ 2 * get_field(s
->fields
, i2
));
1902 static ExitStatus
op_bc(DisasContext
*s
, DisasOps
*o
)
1904 int m1
= get_field(s
->fields
, m1
);
1905 bool is_imm
= have_field(s
->fields
, i2
);
1906 int imm
= is_imm
? get_field(s
->fields
, i2
) : 0;
1909 disas_jcc(s
, &c
, m1
);
1910 return help_branch(s
, &c
, is_imm
, imm
, o
->in2
);
1913 static ExitStatus
op_bct32(DisasContext
*s
, DisasOps
*o
)
1915 int r1
= get_field(s
->fields
, r1
);
1916 bool is_imm
= have_field(s
->fields
, i2
);
1917 int imm
= is_imm
? get_field(s
->fields
, i2
) : 0;
1921 c
.cond
= TCG_COND_NE
;
1926 t
= tcg_temp_new_i64();
1927 tcg_gen_subi_i64(t
, regs
[r1
], 1);
1928 store_reg32_i64(r1
, t
);
1929 c
.u
.s32
.a
= tcg_temp_new_i32();
1930 c
.u
.s32
.b
= tcg_const_i32(0);
1931 tcg_gen_trunc_i64_i32(c
.u
.s32
.a
, t
);
1932 tcg_temp_free_i64(t
);
1934 return help_branch(s
, &c
, is_imm
, imm
, o
->in2
);
1937 static ExitStatus
op_bct64(DisasContext
*s
, DisasOps
*o
)
1939 int r1
= get_field(s
->fields
, r1
);
1940 bool is_imm
= have_field(s
->fields
, i2
);
1941 int imm
= is_imm
? get_field(s
->fields
, i2
) : 0;
1944 c
.cond
= TCG_COND_NE
;
1949 tcg_gen_subi_i64(regs
[r1
], regs
[r1
], 1);
1950 c
.u
.s64
.a
= regs
[r1
];
1951 c
.u
.s64
.b
= tcg_const_i64(0);
1953 return help_branch(s
, &c
, is_imm
, imm
, o
->in2
);
1956 static ExitStatus
op_ceb(DisasContext
*s
, DisasOps
*o
)
1958 gen_helper_ceb(cc_op
, cpu_env
, o
->in1
, o
->in2
);
1963 static ExitStatus
op_cdb(DisasContext
*s
, DisasOps
*o
)
1965 gen_helper_cdb(cc_op
, cpu_env
, o
->in1
, o
->in2
);
1970 static ExitStatus
op_cxb(DisasContext
*s
, DisasOps
*o
)
1972 gen_helper_cxb(cc_op
, cpu_env
, o
->out
, o
->out2
, o
->in1
, o
->in2
);
1977 static ExitStatus
op_cfeb(DisasContext
*s
, DisasOps
*o
)
1979 TCGv_i32 m3
= tcg_const_i32(get_field(s
->fields
, m3
));
1980 gen_helper_cfeb(o
->out
, cpu_env
, o
->in2
, m3
);
1981 tcg_temp_free_i32(m3
);
1982 gen_set_cc_nz_f32(s
, o
->in2
);
1986 static ExitStatus
op_cfdb(DisasContext
*s
, DisasOps
*o
)
1988 TCGv_i32 m3
= tcg_const_i32(get_field(s
->fields
, m3
));
1989 gen_helper_cfdb(o
->out
, cpu_env
, o
->in2
, m3
);
1990 tcg_temp_free_i32(m3
);
1991 gen_set_cc_nz_f64(s
, o
->in2
);
1995 static ExitStatus
op_cfxb(DisasContext
*s
, DisasOps
*o
)
1997 TCGv_i32 m3
= tcg_const_i32(get_field(s
->fields
, m3
));
1998 gen_helper_cfxb(o
->out
, cpu_env
, o
->in1
, o
->in2
, m3
);
1999 tcg_temp_free_i32(m3
);
2000 gen_set_cc_nz_f128(s
, o
->in1
, o
->in2
);
2004 static ExitStatus
op_cgeb(DisasContext
*s
, DisasOps
*o
)
2006 TCGv_i32 m3
= tcg_const_i32(get_field(s
->fields
, m3
));
2007 gen_helper_cgeb(o
->out
, cpu_env
, o
->in2
, m3
);
2008 tcg_temp_free_i32(m3
);
2009 gen_set_cc_nz_f32(s
, o
->in2
);
2013 static ExitStatus
op_cgdb(DisasContext
*s
, DisasOps
*o
)
2015 TCGv_i32 m3
= tcg_const_i32(get_field(s
->fields
, m3
));
2016 gen_helper_cgdb(o
->out
, cpu_env
, o
->in2
, m3
);
2017 tcg_temp_free_i32(m3
);
2018 gen_set_cc_nz_f64(s
, o
->in2
);
2022 static ExitStatus
op_cgxb(DisasContext
*s
, DisasOps
*o
)
2024 TCGv_i32 m3
= tcg_const_i32(get_field(s
->fields
, m3
));
2025 gen_helper_cgxb(o
->out
, cpu_env
, o
->in1
, o
->in2
, m3
);
2026 tcg_temp_free_i32(m3
);
2027 gen_set_cc_nz_f128(s
, o
->in1
, o
->in2
);
2031 static ExitStatus
op_cegb(DisasContext
*s
, DisasOps
*o
)
2033 TCGv_i32 m3
= tcg_const_i32(get_field(s
->fields
, m3
));
2034 gen_helper_cegb(o
->out
, cpu_env
, o
->in2
, m3
);
2035 tcg_temp_free_i32(m3
);
2039 static ExitStatus
op_cdgb(DisasContext
*s
, DisasOps
*o
)
2041 TCGv_i32 m3
= tcg_const_i32(get_field(s
->fields
, m3
));
2042 gen_helper_cdgb(o
->out
, cpu_env
, o
->in2
, m3
);
2043 tcg_temp_free_i32(m3
);
2047 static ExitStatus
op_cxgb(DisasContext
*s
, DisasOps
*o
)
2049 TCGv_i32 m3
= tcg_const_i32(get_field(s
->fields
, m3
));
2050 gen_helper_cxgb(o
->out
, cpu_env
, o
->in2
, m3
);
2051 tcg_temp_free_i32(m3
);
2052 return_low128(o
->out2
);
2056 static ExitStatus
op_clc(DisasContext
*s
, DisasOps
*o
)
2058 int l
= get_field(s
->fields
, l1
);
2063 tcg_gen_qemu_ld8u(cc_src
, o
->addr1
, get_mem_index(s
));
2064 tcg_gen_qemu_ld8u(cc_dst
, o
->in2
, get_mem_index(s
));
2067 tcg_gen_qemu_ld16u(cc_src
, o
->addr1
, get_mem_index(s
));
2068 tcg_gen_qemu_ld16u(cc_dst
, o
->in2
, get_mem_index(s
));
2071 tcg_gen_qemu_ld32u(cc_src
, o
->addr1
, get_mem_index(s
));
2072 tcg_gen_qemu_ld32u(cc_dst
, o
->in2
, get_mem_index(s
));
2075 tcg_gen_qemu_ld64(cc_src
, o
->addr1
, get_mem_index(s
));
2076 tcg_gen_qemu_ld64(cc_dst
, o
->in2
, get_mem_index(s
));
2079 potential_page_fault(s
);
2080 vl
= tcg_const_i32(l
);
2081 gen_helper_clc(cc_op
, cpu_env
, vl
, o
->addr1
, o
->in2
);
2082 tcg_temp_free_i32(vl
);
2086 gen_op_update2_cc_i64(s
, CC_OP_LTUGTU_64
, cc_src
, cc_dst
);
2090 static ExitStatus
op_clcle(DisasContext
*s
, DisasOps
*o
)
2092 TCGv_i32 r1
= tcg_const_i32(get_field(s
->fields
, r1
));
2093 TCGv_i32 r3
= tcg_const_i32(get_field(s
->fields
, r3
));
2094 potential_page_fault(s
);
2095 gen_helper_clcle(cc_op
, cpu_env
, r1
, o
->in2
, r3
);
2096 tcg_temp_free_i32(r1
);
2097 tcg_temp_free_i32(r3
);
2102 static ExitStatus
op_clm(DisasContext
*s
, DisasOps
*o
)
2104 TCGv_i32 m3
= tcg_const_i32(get_field(s
->fields
, m3
));
2105 TCGv_i32 t1
= tcg_temp_new_i32();
2106 tcg_gen_trunc_i64_i32(t1
, o
->in1
);
2107 potential_page_fault(s
);
2108 gen_helper_clm(cc_op
, cpu_env
, t1
, m3
, o
->in2
);
2110 tcg_temp_free_i32(t1
);
2111 tcg_temp_free_i32(m3
);
2115 static ExitStatus
op_cs(DisasContext
*s
, DisasOps
*o
)
2117 int r3
= get_field(s
->fields
, r3
);
2118 potential_page_fault(s
);
2119 gen_helper_cs(o
->out
, cpu_env
, o
->in1
, o
->in2
, regs
[r3
]);
2124 static ExitStatus
op_csg(DisasContext
*s
, DisasOps
*o
)
2126 int r3
= get_field(s
->fields
, r3
);
2127 potential_page_fault(s
);
2128 gen_helper_csg(o
->out
, cpu_env
, o
->in1
, o
->in2
, regs
[r3
]);
2133 static ExitStatus
op_cds(DisasContext
*s
, DisasOps
*o
)
2135 int r3
= get_field(s
->fields
, r3
);
2136 TCGv_i64 in3
= tcg_temp_new_i64();
2137 tcg_gen_deposit_i64(in3
, regs
[r3
+ 1], regs
[r3
], 32, 32);
2138 potential_page_fault(s
);
2139 gen_helper_csg(o
->out
, cpu_env
, o
->in1
, o
->in2
, in3
);
2140 tcg_temp_free_i64(in3
);
2145 static ExitStatus
op_cdsg(DisasContext
*s
, DisasOps
*o
)
2147 TCGv_i32 r1
= tcg_const_i32(get_field(s
->fields
, r1
));
2148 TCGv_i32 r3
= tcg_const_i32(get_field(s
->fields
, r3
));
2149 potential_page_fault(s
);
2150 /* XXX rewrite in tcg */
2151 gen_helper_cdsg(cc_op
, cpu_env
, r1
, o
->in2
, r3
);
2156 static ExitStatus
op_cvd(DisasContext
*s
, DisasOps
*o
)
2158 TCGv_i64 t1
= tcg_temp_new_i64();
2159 TCGv_i32 t2
= tcg_temp_new_i32();
2160 tcg_gen_trunc_i64_i32(t2
, o
->in1
);
2161 gen_helper_cvd(t1
, t2
);
2162 tcg_temp_free_i32(t2
);
2163 tcg_gen_qemu_st64(t1
, o
->in2
, get_mem_index(s
));
2164 tcg_temp_free_i64(t1
);
2168 #ifndef CONFIG_USER_ONLY
2169 static ExitStatus
op_diag(DisasContext
*s
, DisasOps
*o
)
2173 check_privileged(s
);
2174 potential_page_fault(s
);
2176 /* We pretend the format is RX_a so that D2 is the field we want. */
2177 tmp
= tcg_const_i32(get_field(s
->fields
, d2
) & 0xfff);
2178 gen_helper_diag(regs
[2], cpu_env
, tmp
, regs
[2], regs
[1]);
2179 tcg_temp_free_i32(tmp
);
2184 static ExitStatus
op_divs32(DisasContext
*s
, DisasOps
*o
)
2186 gen_helper_divs32(o
->out2
, cpu_env
, o
->in1
, o
->in2
);
2187 return_low128(o
->out
);
2191 static ExitStatus
op_divu32(DisasContext
*s
, DisasOps
*o
)
2193 gen_helper_divu32(o
->out2
, cpu_env
, o
->in1
, o
->in2
);
2194 return_low128(o
->out
);
2198 static ExitStatus
op_divs64(DisasContext
*s
, DisasOps
*o
)
2200 gen_helper_divs64(o
->out2
, cpu_env
, o
->in1
, o
->in2
);
2201 return_low128(o
->out
);
2205 static ExitStatus
op_divu64(DisasContext
*s
, DisasOps
*o
)
2207 gen_helper_divu64(o
->out2
, cpu_env
, o
->out
, o
->out2
, o
->in2
);
2208 return_low128(o
->out
);
2212 static ExitStatus
op_deb(DisasContext
*s
, DisasOps
*o
)
2214 gen_helper_deb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
2218 static ExitStatus
op_ddb(DisasContext
*s
, DisasOps
*o
)
2220 gen_helper_ddb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
2224 static ExitStatus
op_dxb(DisasContext
*s
, DisasOps
*o
)
2226 gen_helper_dxb(o
->out
, cpu_env
, o
->out
, o
->out2
, o
->in1
, o
->in2
);
2227 return_low128(o
->out2
);
2231 static ExitStatus
op_efpc(DisasContext
*s
, DisasOps
*o
)
2233 tcg_gen_ld32u_i64(o
->out
, cpu_env
, offsetof(CPUS390XState
, fpc
));
2237 static ExitStatus
op_ex(DisasContext
*s
, DisasOps
*o
)
2239 /* ??? Perhaps a better way to implement EXECUTE is to set a bit in
2240 tb->flags, (ab)use the tb->cs_base field as the address of
2241 the template in memory, and grab 8 bits of tb->flags/cflags for
2242 the contents of the register. We would then recognize all this
2243 in gen_intermediate_code_internal, generating code for exactly
2244 one instruction. This new TB then gets executed normally.
2246 On the other hand, this seems to be mostly used for modifying
2247 MVC inside of memcpy, which needs a helper call anyway. So
2248 perhaps this doesn't bear thinking about any further. */
2255 tmp
= tcg_const_i64(s
->next_pc
);
2256 gen_helper_ex(cc_op
, cpu_env
, cc_op
, o
->in1
, o
->in2
, tmp
);
2257 tcg_temp_free_i64(tmp
);
2263 static ExitStatus
op_flogr(DisasContext
*s
, DisasOps
*o
)
2265 /* We'll use the original input for cc computation, since we get to
2266 compare that against 0, which ought to be better than comparing
2267 the real output against 64. It also lets cc_dst be a convenient
2268 temporary during our computation. */
2269 gen_op_update1_cc_i64(s
, CC_OP_FLOGR
, o
->in2
);
2271 /* R1 = IN ? CLZ(IN) : 64. */
2272 gen_helper_clz(o
->out
, o
->in2
);
2274 /* R1+1 = IN & ~(found bit). Note that we may attempt to shift this
2275 value by 64, which is undefined. But since the shift is 64 iff the
2276 input is zero, we still get the correct result after and'ing. */
2277 tcg_gen_movi_i64(o
->out2
, 0x8000000000000000ull
);
2278 tcg_gen_shr_i64(o
->out2
, o
->out2
, o
->out
);
2279 tcg_gen_andc_i64(o
->out2
, cc_dst
, o
->out2
);
2283 static ExitStatus
op_icm(DisasContext
*s
, DisasOps
*o
)
2285 int m3
= get_field(s
->fields
, m3
);
2286 int pos
, len
, base
= s
->insn
->data
;
2287 TCGv_i64 tmp
= tcg_temp_new_i64();
2292 /* Effectively a 32-bit load. */
2293 tcg_gen_qemu_ld32u(tmp
, o
->in2
, get_mem_index(s
));
2300 /* Effectively a 16-bit load. */
2301 tcg_gen_qemu_ld16u(tmp
, o
->in2
, get_mem_index(s
));
2309 /* Effectively an 8-bit load. */
2310 tcg_gen_qemu_ld8u(tmp
, o
->in2
, get_mem_index(s
));
2315 pos
= base
+ ctz32(m3
) * 8;
2316 tcg_gen_deposit_i64(o
->out
, o
->out
, tmp
, pos
, len
);
2317 ccm
= ((1ull << len
) - 1) << pos
;
2321 /* This is going to be a sequence of loads and inserts. */
2322 pos
= base
+ 32 - 8;
2326 tcg_gen_qemu_ld8u(tmp
, o
->in2
, get_mem_index(s
));
2327 tcg_gen_addi_i64(o
->in2
, o
->in2
, 1);
2328 tcg_gen_deposit_i64(o
->out
, o
->out
, tmp
, pos
, 8);
2331 m3
= (m3
<< 1) & 0xf;
2337 tcg_gen_movi_i64(tmp
, ccm
);
2338 gen_op_update2_cc_i64(s
, CC_OP_ICM
, tmp
, o
->out
);
2339 tcg_temp_free_i64(tmp
);
2343 static ExitStatus
op_insi(DisasContext
*s
, DisasOps
*o
)
2345 int shift
= s
->insn
->data
& 0xff;
2346 int size
= s
->insn
->data
>> 8;
2347 tcg_gen_deposit_i64(o
->out
, o
->in1
, o
->in2
, shift
, size
);
2351 static ExitStatus
op_ldeb(DisasContext
*s
, DisasOps
*o
)
2353 gen_helper_ldeb(o
->out
, cpu_env
, o
->in2
);
2357 static ExitStatus
op_ledb(DisasContext
*s
, DisasOps
*o
)
2359 gen_helper_ledb(o
->out
, cpu_env
, o
->in2
);
2363 static ExitStatus
op_ldxb(DisasContext
*s
, DisasOps
*o
)
2365 gen_helper_ldxb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
2369 static ExitStatus
op_lexb(DisasContext
*s
, DisasOps
*o
)
2371 gen_helper_lexb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
2375 static ExitStatus
op_lxdb(DisasContext
*s
, DisasOps
*o
)
2377 gen_helper_lxdb(o
->out
, cpu_env
, o
->in2
);
2378 return_low128(o
->out2
);
2382 static ExitStatus
op_lxeb(DisasContext
*s
, DisasOps
*o
)
2384 gen_helper_lxeb(o
->out
, cpu_env
, o
->in2
);
2385 return_low128(o
->out2
);
2389 static ExitStatus
op_llgt(DisasContext
*s
, DisasOps
*o
)
2391 tcg_gen_andi_i64(o
->out
, o
->in2
, 0x7fffffff);
2395 static ExitStatus
op_ld8s(DisasContext
*s
, DisasOps
*o
)
2397 tcg_gen_qemu_ld8s(o
->out
, o
->in2
, get_mem_index(s
));
2401 static ExitStatus
op_ld8u(DisasContext
*s
, DisasOps
*o
)
2403 tcg_gen_qemu_ld8u(o
->out
, o
->in2
, get_mem_index(s
));
2407 static ExitStatus
op_ld16s(DisasContext
*s
, DisasOps
*o
)
2409 tcg_gen_qemu_ld16s(o
->out
, o
->in2
, get_mem_index(s
));
2413 static ExitStatus
op_ld16u(DisasContext
*s
, DisasOps
*o
)
2415 tcg_gen_qemu_ld16u(o
->out
, o
->in2
, get_mem_index(s
));
2419 static ExitStatus
op_ld32s(DisasContext
*s
, DisasOps
*o
)
2421 tcg_gen_qemu_ld32s(o
->out
, o
->in2
, get_mem_index(s
));
2425 static ExitStatus
op_ld32u(DisasContext
*s
, DisasOps
*o
)
2427 tcg_gen_qemu_ld32u(o
->out
, o
->in2
, get_mem_index(s
));
2431 static ExitStatus
op_ld64(DisasContext
*s
, DisasOps
*o
)
2433 tcg_gen_qemu_ld64(o
->out
, o
->in2
, get_mem_index(s
));
2437 #ifndef CONFIG_USER_ONLY
2438 static ExitStatus
op_lctl(DisasContext
*s
, DisasOps
*o
)
2440 TCGv_i32 r1
= tcg_const_i32(get_field(s
->fields
, r1
));
2441 TCGv_i32 r3
= tcg_const_i32(get_field(s
->fields
, r3
));
2442 check_privileged(s
);
2443 potential_page_fault(s
);
2444 gen_helper_lctl(cpu_env
, r1
, o
->in2
, r3
);
2445 tcg_temp_free_i32(r1
);
2446 tcg_temp_free_i32(r3
);
2450 static ExitStatus
op_lctlg(DisasContext
*s
, DisasOps
*o
)
2452 TCGv_i32 r1
= tcg_const_i32(get_field(s
->fields
, r1
));
2453 TCGv_i32 r3
= tcg_const_i32(get_field(s
->fields
, r3
));
2454 check_privileged(s
);
2455 potential_page_fault(s
);
2456 gen_helper_lctlg(cpu_env
, r1
, o
->in2
, r3
);
2457 tcg_temp_free_i32(r1
);
2458 tcg_temp_free_i32(r3
);
2461 static ExitStatus
op_lra(DisasContext
*s
, DisasOps
*o
)
2463 check_privileged(s
);
2464 potential_page_fault(s
);
2465 gen_helper_lra(o
->out
, cpu_env
, o
->in2
);
2470 static ExitStatus
op_lpsw(DisasContext
*s
, DisasOps
*o
)
2474 check_privileged(s
);
2476 t1
= tcg_temp_new_i64();
2477 t2
= tcg_temp_new_i64();
2478 tcg_gen_qemu_ld32u(t1
, o
->in2
, get_mem_index(s
));
2479 tcg_gen_addi_i64(o
->in2
, o
->in2
, 4);
2480 tcg_gen_qemu_ld32u(t2
, o
->in2
, get_mem_index(s
));
2481 /* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */
2482 tcg_gen_shli_i64(t1
, t1
, 32);
2483 gen_helper_load_psw(cpu_env
, t1
, t2
);
2484 tcg_temp_free_i64(t1
);
2485 tcg_temp_free_i64(t2
);
2486 return EXIT_NORETURN
;
2490 static ExitStatus
op_lam(DisasContext
*s
, DisasOps
*o
)
2492 TCGv_i32 r1
= tcg_const_i32(get_field(s
->fields
, r1
));
2493 TCGv_i32 r3
= tcg_const_i32(get_field(s
->fields
, r3
));
2494 potential_page_fault(s
);
2495 gen_helper_lam(cpu_env
, r1
, o
->in2
, r3
);
2496 tcg_temp_free_i32(r1
);
2497 tcg_temp_free_i32(r3
);
2501 static ExitStatus
op_lm32(DisasContext
*s
, DisasOps
*o
)
2503 int r1
= get_field(s
->fields
, r1
);
2504 int r3
= get_field(s
->fields
, r3
);
2505 TCGv_i64 t
= tcg_temp_new_i64();
2506 TCGv_i64 t4
= tcg_const_i64(4);
2509 tcg_gen_qemu_ld32u(t
, o
->in2
, get_mem_index(s
));
2510 store_reg32_i64(r1
, t
);
2514 tcg_gen_add_i64(o
->in2
, o
->in2
, t4
);
2518 tcg_temp_free_i64(t
);
2519 tcg_temp_free_i64(t4
);
2523 static ExitStatus
op_lmh(DisasContext
*s
, DisasOps
*o
)
2525 int r1
= get_field(s
->fields
, r1
);
2526 int r3
= get_field(s
->fields
, r3
);
2527 TCGv_i64 t
= tcg_temp_new_i64();
2528 TCGv_i64 t4
= tcg_const_i64(4);
2531 tcg_gen_qemu_ld32u(t
, o
->in2
, get_mem_index(s
));
2532 store_reg32h_i64(r1
, t
);
2536 tcg_gen_add_i64(o
->in2
, o
->in2
, t4
);
2540 tcg_temp_free_i64(t
);
2541 tcg_temp_free_i64(t4
);
2545 static ExitStatus
op_lm64(DisasContext
*s
, DisasOps
*o
)
2547 int r1
= get_field(s
->fields
, r1
);
2548 int r3
= get_field(s
->fields
, r3
);
2549 TCGv_i64 t8
= tcg_const_i64(8);
2552 tcg_gen_qemu_ld64(regs
[r1
], o
->in2
, get_mem_index(s
));
2556 tcg_gen_add_i64(o
->in2
, o
->in2
, t8
);
2560 tcg_temp_free_i64(t8
);
2564 static ExitStatus
op_mov2(DisasContext
*s
, DisasOps
*o
)
2567 o
->g_out
= o
->g_in2
;
2568 TCGV_UNUSED_I64(o
->in2
);
2573 static ExitStatus
op_movx(DisasContext
*s
, DisasOps
*o
)
2577 o
->g_out
= o
->g_in1
;
2578 o
->g_out2
= o
->g_in2
;
2579 TCGV_UNUSED_I64(o
->in1
);
2580 TCGV_UNUSED_I64(o
->in2
);
2581 o
->g_in1
= o
->g_in2
= false;
2585 static ExitStatus
op_mvc(DisasContext
*s
, DisasOps
*o
)
2587 TCGv_i32 l
= tcg_const_i32(get_field(s
->fields
, l1
));
2588 potential_page_fault(s
);
2589 gen_helper_mvc(cpu_env
, l
, o
->addr1
, o
->in2
);
2590 tcg_temp_free_i32(l
);
2594 static ExitStatus
op_mvcl(DisasContext
*s
, DisasOps
*o
)
2596 TCGv_i32 r1
= tcg_const_i32(get_field(s
->fields
, r1
));
2597 TCGv_i32 r2
= tcg_const_i32(get_field(s
->fields
, r2
));
2598 potential_page_fault(s
);
2599 gen_helper_mvcl(cc_op
, cpu_env
, r1
, r2
);
2600 tcg_temp_free_i32(r1
);
2601 tcg_temp_free_i32(r2
);
2606 static ExitStatus
op_mvcle(DisasContext
*s
, DisasOps
*o
)
2608 TCGv_i32 r1
= tcg_const_i32(get_field(s
->fields
, r1
));
2609 TCGv_i32 r3
= tcg_const_i32(get_field(s
->fields
, r3
));
2610 potential_page_fault(s
);
2611 gen_helper_mvcle(cc_op
, cpu_env
, r1
, o
->in2
, r3
);
2612 tcg_temp_free_i32(r1
);
2613 tcg_temp_free_i32(r3
);
2618 #ifndef CONFIG_USER_ONLY
2619 static ExitStatus
op_mvcp(DisasContext
*s
, DisasOps
*o
)
2621 int r1
= get_field(s
->fields
, l1
);
2622 check_privileged(s
);
2623 potential_page_fault(s
);
2624 gen_helper_mvcp(cc_op
, cpu_env
, regs
[r1
], o
->addr1
, o
->in2
);
2629 static ExitStatus
op_mvcs(DisasContext
*s
, DisasOps
*o
)
2631 int r1
= get_field(s
->fields
, l1
);
2632 check_privileged(s
);
2633 potential_page_fault(s
);
2634 gen_helper_mvcs(cc_op
, cpu_env
, regs
[r1
], o
->addr1
, o
->in2
);
2640 static ExitStatus
op_mul(DisasContext
*s
, DisasOps
*o
)
2642 tcg_gen_mul_i64(o
->out
, o
->in1
, o
->in2
);
2646 static ExitStatus
op_mul128(DisasContext
*s
, DisasOps
*o
)
2648 gen_helper_mul128(o
->out
, cpu_env
, o
->in1
, o
->in2
);
2649 return_low128(o
->out2
);
2653 static ExitStatus
op_meeb(DisasContext
*s
, DisasOps
*o
)
2655 gen_helper_meeb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
2659 static ExitStatus
op_mdeb(DisasContext
*s
, DisasOps
*o
)
2661 gen_helper_mdeb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
2665 static ExitStatus
op_mdb(DisasContext
*s
, DisasOps
*o
)
2667 gen_helper_mdb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
2671 static ExitStatus
op_mxb(DisasContext
*s
, DisasOps
*o
)
2673 gen_helper_mxb(o
->out
, cpu_env
, o
->out
, o
->out2
, o
->in1
, o
->in2
);
2674 return_low128(o
->out2
);
2678 static ExitStatus
op_mxdb(DisasContext
*s
, DisasOps
*o
)
2680 gen_helper_mxdb(o
->out
, cpu_env
, o
->out
, o
->out2
, o
->in2
);
2681 return_low128(o
->out2
);
2685 static ExitStatus
op_maeb(DisasContext
*s
, DisasOps
*o
)
2687 TCGv_i64 r3
= load_freg32_i64(get_field(s
->fields
, r3
));
2688 gen_helper_maeb(o
->out
, cpu_env
, o
->in1
, o
->in2
, r3
);
2689 tcg_temp_free_i64(r3
);
2693 static ExitStatus
op_madb(DisasContext
*s
, DisasOps
*o
)
2695 int r3
= get_field(s
->fields
, r3
);
2696 gen_helper_madb(o
->out
, cpu_env
, o
->in1
, o
->in2
, fregs
[r3
]);
2700 static ExitStatus
op_mseb(DisasContext
*s
, DisasOps
*o
)
2702 TCGv_i64 r3
= load_freg32_i64(get_field(s
->fields
, r3
));
2703 gen_helper_mseb(o
->out
, cpu_env
, o
->in1
, o
->in2
, r3
);
2704 tcg_temp_free_i64(r3
);
2708 static ExitStatus
op_msdb(DisasContext
*s
, DisasOps
*o
)
2710 int r3
= get_field(s
->fields
, r3
);
2711 gen_helper_msdb(o
->out
, cpu_env
, o
->in1
, o
->in2
, fregs
[r3
]);
2715 static ExitStatus
op_nabs(DisasContext
*s
, DisasOps
*o
)
2717 gen_helper_nabs_i64(o
->out
, o
->in2
);
2721 static ExitStatus
op_nabsf32(DisasContext
*s
, DisasOps
*o
)
2723 tcg_gen_ori_i64(o
->out
, o
->in2
, 0x80000000ull
);
2727 static ExitStatus
op_nabsf64(DisasContext
*s
, DisasOps
*o
)
2729 tcg_gen_ori_i64(o
->out
, o
->in2
, 0x8000000000000000ull
);
2733 static ExitStatus
op_nabsf128(DisasContext
*s
, DisasOps
*o
)
2735 tcg_gen_ori_i64(o
->out
, o
->in1
, 0x8000000000000000ull
);
2736 tcg_gen_mov_i64(o
->out2
, o
->in2
);
2740 static ExitStatus
op_nc(DisasContext
*s
, DisasOps
*o
)
2742 TCGv_i32 l
= tcg_const_i32(get_field(s
->fields
, l1
));
2743 potential_page_fault(s
);
2744 gen_helper_nc(cc_op
, cpu_env
, l
, o
->addr1
, o
->in2
);
2745 tcg_temp_free_i32(l
);
2750 static ExitStatus
op_neg(DisasContext
*s
, DisasOps
*o
)
2752 tcg_gen_neg_i64(o
->out
, o
->in2
);
2756 static ExitStatus
op_negf32(DisasContext
*s
, DisasOps
*o
)
2758 tcg_gen_xori_i64(o
->out
, o
->in2
, 0x80000000ull
);
2762 static ExitStatus
op_negf64(DisasContext
*s
, DisasOps
*o
)
2764 tcg_gen_xori_i64(o
->out
, o
->in2
, 0x8000000000000000ull
);
2768 static ExitStatus
op_negf128(DisasContext
*s
, DisasOps
*o
)
2770 tcg_gen_xori_i64(o
->out
, o
->in1
, 0x8000000000000000ull
);
2771 tcg_gen_mov_i64(o
->out2
, o
->in2
);
2775 static ExitStatus
op_oc(DisasContext
*s
, DisasOps
*o
)
2777 TCGv_i32 l
= tcg_const_i32(get_field(s
->fields
, l1
));
2778 potential_page_fault(s
);
2779 gen_helper_oc(cc_op
, cpu_env
, l
, o
->addr1
, o
->in2
);
2780 tcg_temp_free_i32(l
);
2785 static ExitStatus
op_or(DisasContext
*s
, DisasOps
*o
)
2787 tcg_gen_or_i64(o
->out
, o
->in1
, o
->in2
);
2791 static ExitStatus
op_ori(DisasContext
*s
, DisasOps
*o
)
2793 int shift
= s
->insn
->data
& 0xff;
2794 int size
= s
->insn
->data
>> 8;
2795 uint64_t mask
= ((1ull << size
) - 1) << shift
;
2798 tcg_gen_shli_i64(o
->in2
, o
->in2
, shift
);
2799 tcg_gen_or_i64(o
->out
, o
->in1
, o
->in2
);
2801 /* Produce the CC from only the bits manipulated. */
2802 tcg_gen_andi_i64(cc_dst
, o
->out
, mask
);
2803 set_cc_nz_u64(s
, cc_dst
);
2807 static ExitStatus
op_rev16(DisasContext
*s
, DisasOps
*o
)
2809 tcg_gen_bswap16_i64(o
->out
, o
->in2
);
2813 static ExitStatus
op_rev32(DisasContext
*s
, DisasOps
*o
)
2815 tcg_gen_bswap32_i64(o
->out
, o
->in2
);
2819 static ExitStatus
op_rev64(DisasContext
*s
, DisasOps
*o
)
2821 tcg_gen_bswap64_i64(o
->out
, o
->in2
);
2825 static ExitStatus
op_rll32(DisasContext
*s
, DisasOps
*o
)
2827 TCGv_i32 t1
= tcg_temp_new_i32();
2828 TCGv_i32 t2
= tcg_temp_new_i32();
2829 TCGv_i32 to
= tcg_temp_new_i32();
2830 tcg_gen_trunc_i64_i32(t1
, o
->in1
);
2831 tcg_gen_trunc_i64_i32(t2
, o
->in2
);
2832 tcg_gen_rotl_i32(to
, t1
, t2
);
2833 tcg_gen_extu_i32_i64(o
->out
, to
);
2834 tcg_temp_free_i32(t1
);
2835 tcg_temp_free_i32(t2
);
2836 tcg_temp_free_i32(to
);
2840 static ExitStatus
op_rll64(DisasContext
*s
, DisasOps
*o
)
2842 tcg_gen_rotl_i64(o
->out
, o
->in1
, o
->in2
);
2846 static ExitStatus
op_seb(DisasContext
*s
, DisasOps
*o
)
2848 gen_helper_seb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
2852 static ExitStatus
op_sdb(DisasContext
*s
, DisasOps
*o
)
2854 gen_helper_sdb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
2858 static ExitStatus
op_sxb(DisasContext
*s
, DisasOps
*o
)
2860 gen_helper_sxb(o
->out
, cpu_env
, o
->out
, o
->out2
, o
->in1
, o
->in2
);
2861 return_low128(o
->out2
);
2865 static ExitStatus
op_sqeb(DisasContext
*s
, DisasOps
*o
)
2867 gen_helper_sqeb(o
->out
, cpu_env
, o
->in2
);
2871 static ExitStatus
op_sqdb(DisasContext
*s
, DisasOps
*o
)
2873 gen_helper_sqdb(o
->out
, cpu_env
, o
->in2
);
2877 static ExitStatus
op_sqxb(DisasContext
*s
, DisasOps
*o
)
2879 gen_helper_sqxb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
2880 return_low128(o
->out2
);
2884 #ifndef CONFIG_USER_ONLY
2885 static ExitStatus
op_sigp(DisasContext
*s
, DisasOps
*o
)
2887 TCGv_i32 r1
= tcg_const_i32(get_field(s
->fields
, r1
));
2888 check_privileged(s
);
2889 potential_page_fault(s
);
2890 gen_helper_sigp(cc_op
, cpu_env
, o
->in2
, r1
, o
->in1
);
2891 tcg_temp_free_i32(r1
);
2896 static ExitStatus
op_sla(DisasContext
*s
, DisasOps
*o
)
2898 uint64_t sign
= 1ull << s
->insn
->data
;
2899 enum cc_op cco
= s
->insn
->data
== 31 ? CC_OP_SLA_32
: CC_OP_SLA_64
;
2900 gen_op_update2_cc_i64(s
, cco
, o
->in1
, o
->in2
);
2901 tcg_gen_shl_i64(o
->out
, o
->in1
, o
->in2
);
2902 /* The arithmetic left shift is curious in that it does not affect
2903 the sign bit. Copy that over from the source unchanged. */
2904 tcg_gen_andi_i64(o
->out
, o
->out
, ~sign
);
2905 tcg_gen_andi_i64(o
->in1
, o
->in1
, sign
);
2906 tcg_gen_or_i64(o
->out
, o
->out
, o
->in1
);
2910 static ExitStatus
op_sll(DisasContext
*s
, DisasOps
*o
)
2912 tcg_gen_shl_i64(o
->out
, o
->in1
, o
->in2
);
2916 static ExitStatus
op_sra(DisasContext
*s
, DisasOps
*o
)
2918 tcg_gen_sar_i64(o
->out
, o
->in1
, o
->in2
);
2922 static ExitStatus
op_srl(DisasContext
*s
, DisasOps
*o
)
2924 tcg_gen_shr_i64(o
->out
, o
->in1
, o
->in2
);
2928 static ExitStatus
op_sfpc(DisasContext
*s
, DisasOps
*o
)
2930 gen_helper_sfpc(cpu_env
, o
->in2
);
2934 #ifndef CONFIG_USER_ONLY
2935 static ExitStatus
op_ssm(DisasContext
*s
, DisasOps
*o
)
2937 check_privileged(s
);
2938 tcg_gen_deposit_i64(psw_mask
, psw_mask
, o
->in2
, 56, 8);
2942 static ExitStatus
op_stctg(DisasContext
*s
, DisasOps
*o
)
2944 TCGv_i32 r1
= tcg_const_i32(get_field(s
->fields
, r1
));
2945 TCGv_i32 r3
= tcg_const_i32(get_field(s
->fields
, r3
));
2946 check_privileged(s
);
2947 potential_page_fault(s
);
2948 gen_helper_stctg(cpu_env
, r1
, o
->in2
, r3
);
2949 tcg_temp_free_i32(r1
);
2950 tcg_temp_free_i32(r3
);
2954 static ExitStatus
op_stctl(DisasContext
*s
, DisasOps
*o
)
2956 TCGv_i32 r1
= tcg_const_i32(get_field(s
->fields
, r1
));
2957 TCGv_i32 r3
= tcg_const_i32(get_field(s
->fields
, r3
));
2958 check_privileged(s
);
2959 potential_page_fault(s
);
2960 gen_helper_stctl(cpu_env
, r1
, o
->in2
, r3
);
2961 tcg_temp_free_i32(r1
);
2962 tcg_temp_free_i32(r3
);
2966 static ExitStatus
op_stnosm(DisasContext
*s
, DisasOps
*o
)
2968 uint64_t i2
= get_field(s
->fields
, i2
);
2971 check_privileged(s
);
2973 /* It is important to do what the instruction name says: STORE THEN.
2974 If we let the output hook perform the store then if we fault and
2975 restart, we'll have the wrong SYSTEM MASK in place. */
2976 t
= tcg_temp_new_i64();
2977 tcg_gen_shri_i64(t
, psw_mask
, 56);
2978 tcg_gen_qemu_st8(t
, o
->addr1
, get_mem_index(s
));
2979 tcg_temp_free_i64(t
);
2981 if (s
->fields
->op
== 0xac) {
2982 tcg_gen_andi_i64(psw_mask
, psw_mask
,
2983 (i2
<< 56) | 0x00ffffffffffffffull
);
2985 tcg_gen_ori_i64(psw_mask
, psw_mask
, i2
<< 56);
2991 static ExitStatus
op_st8(DisasContext
*s
, DisasOps
*o
)
2993 tcg_gen_qemu_st8(o
->in1
, o
->in2
, get_mem_index(s
));
2997 static ExitStatus
op_st16(DisasContext
*s
, DisasOps
*o
)
2999 tcg_gen_qemu_st16(o
->in1
, o
->in2
, get_mem_index(s
));
3003 static ExitStatus
op_st32(DisasContext
*s
, DisasOps
*o
)
3005 tcg_gen_qemu_st32(o
->in1
, o
->in2
, get_mem_index(s
));
3009 static ExitStatus
op_st64(DisasContext
*s
, DisasOps
*o
)
3011 tcg_gen_qemu_st64(o
->in1
, o
->in2
, get_mem_index(s
));
3015 static ExitStatus
op_stam(DisasContext
*s
, DisasOps
*o
)
3017 TCGv_i32 r1
= tcg_const_i32(get_field(s
->fields
, r1
));
3018 TCGv_i32 r3
= tcg_const_i32(get_field(s
->fields
, r3
));
3019 potential_page_fault(s
);
3020 gen_helper_stam(cpu_env
, r1
, o
->in2
, r3
);
3021 tcg_temp_free_i32(r1
);
3022 tcg_temp_free_i32(r3
);
3026 static ExitStatus
op_stcm(DisasContext
*s
, DisasOps
*o
)
3028 int m3
= get_field(s
->fields
, m3
);
3029 int pos
, base
= s
->insn
->data
;
3030 TCGv_i64 tmp
= tcg_temp_new_i64();
3032 pos
= base
+ ctz32(m3
) * 8;
3035 /* Effectively a 32-bit store. */
3036 tcg_gen_shri_i64(tmp
, o
->in1
, pos
);
3037 tcg_gen_qemu_st32(tmp
, o
->in2
, get_mem_index(s
));
3043 /* Effectively a 16-bit store. */
3044 tcg_gen_shri_i64(tmp
, o
->in1
, pos
);
3045 tcg_gen_qemu_st16(tmp
, o
->in2
, get_mem_index(s
));
3052 /* Effectively an 8-bit store. */
3053 tcg_gen_shri_i64(tmp
, o
->in1
, pos
);
3054 tcg_gen_qemu_st8(tmp
, o
->in2
, get_mem_index(s
));
3058 /* This is going to be a sequence of shifts and stores. */
3059 pos
= base
+ 32 - 8;
3062 tcg_gen_shri_i64(tmp
, o
->in1
, pos
);
3063 tcg_gen_qemu_st8(tmp
, o
->in2
, get_mem_index(s
));
3064 tcg_gen_addi_i64(o
->in2
, o
->in2
, 1);
3066 m3
= (m3
<< 1) & 0xf;
3071 tcg_temp_free_i64(tmp
);
3075 static ExitStatus
op_stm(DisasContext
*s
, DisasOps
*o
)
3077 int r1
= get_field(s
->fields
, r1
);
3078 int r3
= get_field(s
->fields
, r3
);
3079 int size
= s
->insn
->data
;
3080 TCGv_i64 tsize
= tcg_const_i64(size
);
3084 tcg_gen_qemu_st64(regs
[r1
], o
->in2
, get_mem_index(s
));
3086 tcg_gen_qemu_st32(regs
[r1
], o
->in2
, get_mem_index(s
));
3091 tcg_gen_add_i64(o
->in2
, o
->in2
, tsize
);
3095 tcg_temp_free_i64(tsize
);
3099 static ExitStatus
op_stmh(DisasContext
*s
, DisasOps
*o
)
3101 int r1
= get_field(s
->fields
, r1
);
3102 int r3
= get_field(s
->fields
, r3
);
3103 TCGv_i64 t
= tcg_temp_new_i64();
3104 TCGv_i64 t4
= tcg_const_i64(4);
3105 TCGv_i64 t32
= tcg_const_i64(32);
3108 tcg_gen_shl_i64(t
, regs
[r1
], t32
);
3109 tcg_gen_qemu_st32(t
, o
->in2
, get_mem_index(s
));
3113 tcg_gen_add_i64(o
->in2
, o
->in2
, t4
);
3117 tcg_temp_free_i64(t
);
3118 tcg_temp_free_i64(t4
);
3119 tcg_temp_free_i64(t32
);
3123 static ExitStatus
op_sub(DisasContext
*s
, DisasOps
*o
)
3125 tcg_gen_sub_i64(o
->out
, o
->in1
, o
->in2
);
3129 static ExitStatus
op_subb(DisasContext
*s
, DisasOps
*o
)
3134 tcg_gen_not_i64(o
->in2
, o
->in2
);
3135 tcg_gen_add_i64(o
->out
, o
->in1
, o
->in2
);
3137 /* XXX possible optimization point */
3139 cc
= tcg_temp_new_i64();
3140 tcg_gen_extu_i32_i64(cc
, cc_op
);
3141 tcg_gen_shri_i64(cc
, cc
, 1);
3142 tcg_gen_add_i64(o
->out
, o
->out
, cc
);
3143 tcg_temp_free_i64(cc
);
3147 static ExitStatus
op_svc(DisasContext
*s
, DisasOps
*o
)
3154 t
= tcg_const_i32(get_field(s
->fields
, i1
) & 0xff);
3155 tcg_gen_st_i32(t
, cpu_env
, offsetof(CPUS390XState
, int_svc_code
));
3156 tcg_temp_free_i32(t
);
3158 t
= tcg_const_i32(s
->next_pc
- s
->pc
);
3159 tcg_gen_st_i32(t
, cpu_env
, offsetof(CPUS390XState
, int_svc_ilen
));
3160 tcg_temp_free_i32(t
);
3162 gen_exception(EXCP_SVC
);
3163 return EXIT_NORETURN
;
3166 static ExitStatus
op_tceb(DisasContext
*s
, DisasOps
*o
)
3168 gen_helper_tceb(cc_op
, o
->in1
, o
->in2
);
3173 static ExitStatus
op_tcdb(DisasContext
*s
, DisasOps
*o
)
3175 gen_helper_tcdb(cc_op
, o
->in1
, o
->in2
);
3180 static ExitStatus
op_tcxb(DisasContext
*s
, DisasOps
*o
)
3182 gen_helper_tcxb(cc_op
, o
->out
, o
->out2
, o
->in2
);
3187 #ifndef CONFIG_USER_ONLY
3188 static ExitStatus
op_tprot(DisasContext
*s
, DisasOps
*o
)
3190 potential_page_fault(s
);
3191 gen_helper_tprot(cc_op
, o
->addr1
, o
->in2
);
3197 static ExitStatus
op_tr(DisasContext
*s
, DisasOps
*o
)
3199 TCGv_i32 l
= tcg_const_i32(get_field(s
->fields
, l1
));
3200 potential_page_fault(s
);
3201 gen_helper_tr(cpu_env
, l
, o
->addr1
, o
->in2
);
3202 tcg_temp_free_i32(l
);
3207 static ExitStatus
op_unpk(DisasContext
*s
, DisasOps
*o
)
3209 TCGv_i32 l
= tcg_const_i32(get_field(s
->fields
, l1
));
3210 potential_page_fault(s
);
3211 gen_helper_unpk(cpu_env
, l
, o
->addr1
, o
->in2
);
3212 tcg_temp_free_i32(l
);
3216 static ExitStatus
op_xc(DisasContext
*s
, DisasOps
*o
)
3218 TCGv_i32 l
= tcg_const_i32(get_field(s
->fields
, l1
));
3219 potential_page_fault(s
);
3220 gen_helper_xc(cc_op
, cpu_env
, l
, o
->addr1
, o
->in2
);
3221 tcg_temp_free_i32(l
);
3226 static ExitStatus
op_xor(DisasContext
*s
, DisasOps
*o
)
3228 tcg_gen_xor_i64(o
->out
, o
->in1
, o
->in2
);
3232 static ExitStatus
op_xori(DisasContext
*s
, DisasOps
*o
)
3234 int shift
= s
->insn
->data
& 0xff;
3235 int size
= s
->insn
->data
>> 8;
3236 uint64_t mask
= ((1ull << size
) - 1) << shift
;
3239 tcg_gen_shli_i64(o
->in2
, o
->in2
, shift
);
3240 tcg_gen_xor_i64(o
->out
, o
->in1
, o
->in2
);
3242 /* Produce the CC from only the bits manipulated. */
3243 tcg_gen_andi_i64(cc_dst
, o
->out
, mask
);
3244 set_cc_nz_u64(s
, cc_dst
);
3248 static ExitStatus
op_zero(DisasContext
*s
, DisasOps
*o
)
3250 o
->out
= tcg_const_i64(0);
3254 static ExitStatus
op_zero2(DisasContext
*s
, DisasOps
*o
)
3256 o
->out
= tcg_const_i64(0);
3262 /* ====================================================================== */
3263 /* The "Cc OUTput" generators. Given the generated output (and in some cases
3264 the original inputs), update the various cc data structures in order to
3265 be able to compute the new condition code. */
3267 static void cout_abs32(DisasContext
*s
, DisasOps
*o
)
3269 gen_op_update1_cc_i64(s
, CC_OP_ABS_32
, o
->out
);
3272 static void cout_abs64(DisasContext
*s
, DisasOps
*o
)
3274 gen_op_update1_cc_i64(s
, CC_OP_ABS_64
, o
->out
);
3277 static void cout_adds32(DisasContext
*s
, DisasOps
*o
)
3279 gen_op_update3_cc_i64(s
, CC_OP_ADD_32
, o
->in1
, o
->in2
, o
->out
);
3282 static void cout_adds64(DisasContext
*s
, DisasOps
*o
)
3284 gen_op_update3_cc_i64(s
, CC_OP_ADD_64
, o
->in1
, o
->in2
, o
->out
);
3287 static void cout_addu32(DisasContext
*s
, DisasOps
*o
)
3289 gen_op_update3_cc_i64(s
, CC_OP_ADDU_32
, o
->in1
, o
->in2
, o
->out
);
3292 static void cout_addu64(DisasContext
*s
, DisasOps
*o
)
3294 gen_op_update3_cc_i64(s
, CC_OP_ADDU_64
, o
->in1
, o
->in2
, o
->out
);
3297 static void cout_addc32(DisasContext
*s
, DisasOps
*o
)
3299 gen_op_update3_cc_i64(s
, CC_OP_ADDC_32
, o
->in1
, o
->in2
, o
->out
);
3302 static void cout_addc64(DisasContext
*s
, DisasOps
*o
)
3304 gen_op_update3_cc_i64(s
, CC_OP_ADDC_64
, o
->in1
, o
->in2
, o
->out
);
3307 static void cout_cmps32(DisasContext
*s
, DisasOps
*o
)
3309 gen_op_update2_cc_i64(s
, CC_OP_LTGT_32
, o
->in1
, o
->in2
);
3312 static void cout_cmps64(DisasContext
*s
, DisasOps
*o
)
3314 gen_op_update2_cc_i64(s
, CC_OP_LTGT_64
, o
->in1
, o
->in2
);
3317 static void cout_cmpu32(DisasContext
*s
, DisasOps
*o
)
3319 gen_op_update2_cc_i64(s
, CC_OP_LTUGTU_32
, o
->in1
, o
->in2
);
3322 static void cout_cmpu64(DisasContext
*s
, DisasOps
*o
)
3324 gen_op_update2_cc_i64(s
, CC_OP_LTUGTU_64
, o
->in1
, o
->in2
);
3327 static void cout_f32(DisasContext
*s
, DisasOps
*o
)
3329 gen_op_update1_cc_i64(s
, CC_OP_NZ_F32
, o
->out
);
3332 static void cout_f64(DisasContext
*s
, DisasOps
*o
)
3334 gen_op_update1_cc_i64(s
, CC_OP_NZ_F64
, o
->out
);
3337 static void cout_f128(DisasContext
*s
, DisasOps
*o
)
3339 gen_op_update2_cc_i64(s
, CC_OP_NZ_F128
, o
->out
, o
->out2
);
3342 static void cout_nabs32(DisasContext
*s
, DisasOps
*o
)
3344 gen_op_update1_cc_i64(s
, CC_OP_NABS_32
, o
->out
);
3347 static void cout_nabs64(DisasContext
*s
, DisasOps
*o
)
3349 gen_op_update1_cc_i64(s
, CC_OP_NABS_64
, o
->out
);
3352 static void cout_neg32(DisasContext
*s
, DisasOps
*o
)
3354 gen_op_update1_cc_i64(s
, CC_OP_COMP_32
, o
->out
);
3357 static void cout_neg64(DisasContext
*s
, DisasOps
*o
)
3359 gen_op_update1_cc_i64(s
, CC_OP_COMP_64
, o
->out
);
3362 static void cout_nz32(DisasContext
*s
, DisasOps
*o
)
3364 tcg_gen_ext32u_i64(cc_dst
, o
->out
);
3365 gen_op_update1_cc_i64(s
, CC_OP_NZ
, cc_dst
);
3368 static void cout_nz64(DisasContext
*s
, DisasOps
*o
)
3370 gen_op_update1_cc_i64(s
, CC_OP_NZ
, o
->out
);
3373 static void cout_s32(DisasContext
*s
, DisasOps
*o
)
3375 gen_op_update1_cc_i64(s
, CC_OP_LTGT0_32
, o
->out
);
3378 static void cout_s64(DisasContext
*s
, DisasOps
*o
)
3380 gen_op_update1_cc_i64(s
, CC_OP_LTGT0_64
, o
->out
);
3383 static void cout_subs32(DisasContext
*s
, DisasOps
*o
)
3385 gen_op_update3_cc_i64(s
, CC_OP_SUB_32
, o
->in1
, o
->in2
, o
->out
);
3388 static void cout_subs64(DisasContext
*s
, DisasOps
*o
)
3390 gen_op_update3_cc_i64(s
, CC_OP_SUB_64
, o
->in1
, o
->in2
, o
->out
);
3393 static void cout_subu32(DisasContext
*s
, DisasOps
*o
)
3395 gen_op_update3_cc_i64(s
, CC_OP_SUBU_32
, o
->in1
, o
->in2
, o
->out
);
3398 static void cout_subu64(DisasContext
*s
, DisasOps
*o
)
3400 gen_op_update3_cc_i64(s
, CC_OP_SUBU_64
, o
->in1
, o
->in2
, o
->out
);
3403 static void cout_subb32(DisasContext
*s
, DisasOps
*o
)
3405 gen_op_update3_cc_i64(s
, CC_OP_SUBB_32
, o
->in1
, o
->in2
, o
->out
);
3408 static void cout_subb64(DisasContext
*s
, DisasOps
*o
)
3410 gen_op_update3_cc_i64(s
, CC_OP_SUBB_64
, o
->in1
, o
->in2
, o
->out
);
3413 static void cout_tm32(DisasContext
*s
, DisasOps
*o
)
3415 gen_op_update2_cc_i64(s
, CC_OP_TM_32
, o
->in1
, o
->in2
);
3418 static void cout_tm64(DisasContext
*s
, DisasOps
*o
)
3420 gen_op_update2_cc_i64(s
, CC_OP_TM_64
, o
->in1
, o
->in2
);
3423 /* ====================================================================== */
3424 /* The "PREPeration" generators. These initialize the DisasOps.OUT fields
3425 with the TCG register to which we will write. Used in combination with
3426 the "wout" generators, in some cases we need a new temporary, and in
3427 some cases we can write to a TCG global. */
3429 static void prep_new(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3431 o
->out
= tcg_temp_new_i64();
3434 static void prep_new_P(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3436 o
->out
= tcg_temp_new_i64();
3437 o
->out2
= tcg_temp_new_i64();
3440 static void prep_r1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3442 o
->out
= regs
[get_field(f
, r1
)];
3446 static void prep_r1_P(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3448 /* ??? Specification exception: r1 must be even. */
3449 int r1
= get_field(f
, r1
);
3451 o
->out2
= regs
[(r1
+ 1) & 15];
3452 o
->g_out
= o
->g_out2
= true;
3455 static void prep_f1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3457 o
->out
= fregs
[get_field(f
, r1
)];
3461 static void prep_x1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3463 /* ??? Specification exception: r1 must be < 14. */
3464 int r1
= get_field(f
, r1
);
3466 o
->out2
= fregs
[(r1
+ 2) & 15];
3467 o
->g_out
= o
->g_out2
= true;
3470 /* ====================================================================== */
3471 /* The "Write OUTput" generators. These generally perform some non-trivial
3472 copy of data to TCG globals, or to main memory. The trivial cases are
3473 generally handled by having a "prep" generator install the TCG global
3474 as the destination of the operation. */
3476 static void wout_r1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3478 store_reg(get_field(f
, r1
), o
->out
);
3481 static void wout_r1_8(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3483 int r1
= get_field(f
, r1
);
3484 tcg_gen_deposit_i64(regs
[r1
], regs
[r1
], o
->out
, 0, 8);
3487 static void wout_r1_16(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3489 int r1
= get_field(f
, r1
);
3490 tcg_gen_deposit_i64(regs
[r1
], regs
[r1
], o
->out
, 0, 16);
3493 static void wout_r1_32(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3495 store_reg32_i64(get_field(f
, r1
), o
->out
);
3498 static void wout_r1_P32(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3500 /* ??? Specification exception: r1 must be even. */
3501 int r1
= get_field(f
, r1
);
3502 store_reg32_i64(r1
, o
->out
);
3503 store_reg32_i64((r1
+ 1) & 15, o
->out2
);
3506 static void wout_r1_D32(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3508 /* ??? Specification exception: r1 must be even. */
3509 int r1
= get_field(f
, r1
);
3510 store_reg32_i64((r1
+ 1) & 15, o
->out
);
3511 tcg_gen_shri_i64(o
->out
, o
->out
, 32);
3512 store_reg32_i64(r1
, o
->out
);
3515 static void wout_e1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3517 store_freg32_i64(get_field(f
, r1
), o
->out
);
3520 static void wout_f1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3522 store_freg(get_field(f
, r1
), o
->out
);
3525 static void wout_x1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3527 /* ??? Specification exception: r1 must be < 14. */
3528 int f1
= get_field(s
->fields
, r1
);
3529 store_freg(f1
, o
->out
);
3530 store_freg((f1
+ 2) & 15, o
->out2
);
3533 static void wout_cond_r1r2_32(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3535 if (get_field(f
, r1
) != get_field(f
, r2
)) {
3536 store_reg32_i64(get_field(f
, r1
), o
->out
);
3540 static void wout_cond_e1e2(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3542 if (get_field(f
, r1
) != get_field(f
, r2
)) {
3543 store_freg32_i64(get_field(f
, r1
), o
->out
);
3547 static void wout_m1_8(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3549 tcg_gen_qemu_st8(o
->out
, o
->addr1
, get_mem_index(s
));
3552 static void wout_m1_16(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3554 tcg_gen_qemu_st16(o
->out
, o
->addr1
, get_mem_index(s
));
3557 static void wout_m1_32(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3559 tcg_gen_qemu_st32(o
->out
, o
->addr1
, get_mem_index(s
));
3562 static void wout_m1_64(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3564 tcg_gen_qemu_st64(o
->out
, o
->addr1
, get_mem_index(s
));
3567 static void wout_m2_32(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3569 tcg_gen_qemu_st32(o
->out
, o
->in2
, get_mem_index(s
));
3572 /* ====================================================================== */
3573 /* The "INput 1" generators. These load the first operand to an insn. */
3575 static void in1_r1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3577 o
->in1
= load_reg(get_field(f
, r1
));
3580 static void in1_r1_o(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3582 o
->in1
= regs
[get_field(f
, r1
)];
3586 static void in1_r1_32s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3588 o
->in1
= tcg_temp_new_i64();
3589 tcg_gen_ext32s_i64(o
->in1
, regs
[get_field(f
, r1
)]);
3592 static void in1_r1_32u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3594 o
->in1
= tcg_temp_new_i64();
3595 tcg_gen_ext32u_i64(o
->in1
, regs
[get_field(f
, r1
)]);
3598 static void in1_r1_sr32(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3600 o
->in1
= tcg_temp_new_i64();
3601 tcg_gen_shri_i64(o
->in1
, regs
[get_field(f
, r1
)], 32);
3604 static void in1_r1p1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3606 /* ??? Specification exception: r1 must be even. */
3607 int r1
= get_field(f
, r1
);
3608 o
->in1
= load_reg((r1
+ 1) & 15);
3611 static void in1_r1p1_32s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3613 /* ??? Specification exception: r1 must be even. */
3614 int r1
= get_field(f
, r1
);
3615 o
->in1
= tcg_temp_new_i64();
3616 tcg_gen_ext32s_i64(o
->in1
, regs
[(r1
+ 1) & 15]);
3619 static void in1_r1p1_32u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3621 /* ??? Specification exception: r1 must be even. */
3622 int r1
= get_field(f
, r1
);
3623 o
->in1
= tcg_temp_new_i64();
3624 tcg_gen_ext32u_i64(o
->in1
, regs
[(r1
+ 1) & 15]);
3627 static void in1_r1_D32(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3629 /* ??? Specification exception: r1 must be even. */
3630 int r1
= get_field(f
, r1
);
3631 o
->in1
= tcg_temp_new_i64();
3632 tcg_gen_concat32_i64(o
->in1
, regs
[r1
+ 1], regs
[r1
]);
3635 static void in1_r2(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3637 o
->in1
= load_reg(get_field(f
, r2
));
3640 static void in1_r3(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3642 o
->in1
= load_reg(get_field(f
, r3
));
3645 static void in1_r3_o(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3647 o
->in1
= regs
[get_field(f
, r3
)];
3651 static void in1_r3_32s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3653 o
->in1
= tcg_temp_new_i64();
3654 tcg_gen_ext32s_i64(o
->in1
, regs
[get_field(f
, r3
)]);
3657 static void in1_r3_32u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3659 o
->in1
= tcg_temp_new_i64();
3660 tcg_gen_ext32u_i64(o
->in1
, regs
[get_field(f
, r3
)]);
3663 static void in1_e1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3665 o
->in1
= load_freg32_i64(get_field(f
, r1
));
3668 static void in1_f1_o(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3670 o
->in1
= fregs
[get_field(f
, r1
)];
3674 static void in1_x1_o(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3676 /* ??? Specification exception: r1 must be < 14. */
3677 int r1
= get_field(f
, r1
);
3679 o
->out2
= fregs
[(r1
+ 2) & 15];
3680 o
->g_out
= o
->g_out2
= true;
3683 static void in1_la1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3685 o
->addr1
= get_address(s
, 0, get_field(f
, b1
), get_field(f
, d1
));
3688 static void in1_la2(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3690 int x2
= have_field(f
, x2
) ? get_field(f
, x2
) : 0;
3691 o
->addr1
= get_address(s
, x2
, get_field(f
, b2
), get_field(f
, d2
));
3694 static void in1_m1_8u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3697 o
->in1
= tcg_temp_new_i64();
3698 tcg_gen_qemu_ld8u(o
->in1
, o
->addr1
, get_mem_index(s
));
3701 static void in1_m1_16s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3704 o
->in1
= tcg_temp_new_i64();
3705 tcg_gen_qemu_ld16s(o
->in1
, o
->addr1
, get_mem_index(s
));
3708 static void in1_m1_16u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3711 o
->in1
= tcg_temp_new_i64();
3712 tcg_gen_qemu_ld16u(o
->in1
, o
->addr1
, get_mem_index(s
));
3715 static void in1_m1_32s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3718 o
->in1
= tcg_temp_new_i64();
3719 tcg_gen_qemu_ld32s(o
->in1
, o
->addr1
, get_mem_index(s
));
3722 static void in1_m1_32u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3725 o
->in1
= tcg_temp_new_i64();
3726 tcg_gen_qemu_ld32u(o
->in1
, o
->addr1
, get_mem_index(s
));
3729 static void in1_m1_64(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3732 o
->in1
= tcg_temp_new_i64();
3733 tcg_gen_qemu_ld64(o
->in1
, o
->addr1
, get_mem_index(s
));
3736 /* ====================================================================== */
3737 /* The "INput 2" generators. These load the second operand to an insn. */
3739 static void in2_r1_o(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3741 o
->in2
= regs
[get_field(f
, r1
)];
3745 static void in2_r1_16u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3747 o
->in2
= tcg_temp_new_i64();
3748 tcg_gen_ext16u_i64(o
->in2
, regs
[get_field(f
, r1
)]);
3751 static void in2_r1_32u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3753 o
->in2
= tcg_temp_new_i64();
3754 tcg_gen_ext32u_i64(o
->in2
, regs
[get_field(f
, r1
)]);
3757 static void in2_r2(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3759 o
->in2
= load_reg(get_field(f
, r2
));
3762 static void in2_r2_o(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3764 o
->in2
= regs
[get_field(f
, r2
)];
3768 static void in2_r2_nz(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3770 int r2
= get_field(f
, r2
);
3772 o
->in2
= load_reg(r2
);
3776 static void in2_r2_8s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3778 o
->in2
= tcg_temp_new_i64();
3779 tcg_gen_ext8s_i64(o
->in2
, regs
[get_field(f
, r2
)]);
3782 static void in2_r2_8u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3784 o
->in2
= tcg_temp_new_i64();
3785 tcg_gen_ext8u_i64(o
->in2
, regs
[get_field(f
, r2
)]);
3788 static void in2_r2_16s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3790 o
->in2
= tcg_temp_new_i64();
3791 tcg_gen_ext16s_i64(o
->in2
, regs
[get_field(f
, r2
)]);
3794 static void in2_r2_16u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3796 o
->in2
= tcg_temp_new_i64();
3797 tcg_gen_ext16u_i64(o
->in2
, regs
[get_field(f
, r2
)]);
3800 static void in2_r3(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3802 o
->in2
= load_reg(get_field(f
, r3
));
3805 static void in2_r2_32s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3807 o
->in2
= tcg_temp_new_i64();
3808 tcg_gen_ext32s_i64(o
->in2
, regs
[get_field(f
, r2
)]);
3811 static void in2_r2_32u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3813 o
->in2
= tcg_temp_new_i64();
3814 tcg_gen_ext32u_i64(o
->in2
, regs
[get_field(f
, r2
)]);
3817 static void in2_e2(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3819 o
->in2
= load_freg32_i64(get_field(f
, r2
));
3822 static void in2_f2_o(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3824 o
->in2
= fregs
[get_field(f
, r2
)];
3828 static void in2_x2_o(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3830 /* ??? Specification exception: r1 must be < 14. */
3831 int r2
= get_field(f
, r2
);
3833 o
->in2
= fregs
[(r2
+ 2) & 15];
3834 o
->g_in1
= o
->g_in2
= true;
3837 static void in2_a2(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3839 int x2
= have_field(f
, x2
) ? get_field(f
, x2
) : 0;
3840 o
->in2
= get_address(s
, x2
, get_field(f
, b2
), get_field(f
, d2
));
3843 static void in2_ri2(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3845 o
->in2
= tcg_const_i64(s
->pc
+ (int64_t)get_field(f
, i2
) * 2);
3848 static void in2_sh32(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3850 help_l2_shift(s
, f
, o
, 31);
3853 static void in2_sh64(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3855 help_l2_shift(s
, f
, o
, 63);
3858 static void in2_m2_8u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3861 tcg_gen_qemu_ld8u(o
->in2
, o
->in2
, get_mem_index(s
));
3864 static void in2_m2_16s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3867 tcg_gen_qemu_ld16s(o
->in2
, o
->in2
, get_mem_index(s
));
3870 static void in2_m2_16u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3873 tcg_gen_qemu_ld16u(o
->in2
, o
->in2
, get_mem_index(s
));
3876 static void in2_m2_32s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3879 tcg_gen_qemu_ld32s(o
->in2
, o
->in2
, get_mem_index(s
));
3882 static void in2_m2_32u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3885 tcg_gen_qemu_ld32u(o
->in2
, o
->in2
, get_mem_index(s
));
3888 static void in2_m2_64(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3891 tcg_gen_qemu_ld64(o
->in2
, o
->in2
, get_mem_index(s
));
3894 static void in2_mri2_16u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3897 tcg_gen_qemu_ld16u(o
->in2
, o
->in2
, get_mem_index(s
));
3900 static void in2_mri2_32s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3903 tcg_gen_qemu_ld32s(o
->in2
, o
->in2
, get_mem_index(s
));
3906 static void in2_mri2_32u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3909 tcg_gen_qemu_ld32u(o
->in2
, o
->in2
, get_mem_index(s
));
3912 static void in2_mri2_64(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3915 tcg_gen_qemu_ld64(o
->in2
, o
->in2
, get_mem_index(s
));
3918 static void in2_i2(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3920 o
->in2
= tcg_const_i64(get_field(f
, i2
));
3923 static void in2_i2_8u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3925 o
->in2
= tcg_const_i64((uint8_t)get_field(f
, i2
));
3928 static void in2_i2_16u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3930 o
->in2
= tcg_const_i64((uint16_t)get_field(f
, i2
));
3933 static void in2_i2_32u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3935 o
->in2
= tcg_const_i64((uint32_t)get_field(f
, i2
));
3938 static void in2_i2_16u_shl(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3940 uint64_t i2
= (uint16_t)get_field(f
, i2
);
3941 o
->in2
= tcg_const_i64(i2
<< s
->insn
->data
);
3944 static void in2_i2_32u_shl(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3946 uint64_t i2
= (uint32_t)get_field(f
, i2
);
3947 o
->in2
= tcg_const_i64(i2
<< s
->insn
->data
);
3950 /* ====================================================================== */
3952 /* Find opc within the table of insns. This is formulated as a switch
3953 statement so that (1) we get compile-time notice of cut-paste errors
3954 for duplicated opcodes, and (2) the compiler generates the binary
3955 search tree, rather than us having to post-process the table. */
3957 #define C(OPC, NM, FT, FC, I1, I2, P, W, OP, CC) \
3958 D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, 0)
3960 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) insn_ ## NM,
3962 enum DisasInsnEnum
{
3963 #include "insn-data.def"
3967 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) { \
3972 .help_in1 = in1_##I1, \
3973 .help_in2 = in2_##I2, \
3974 .help_prep = prep_##P, \
3975 .help_wout = wout_##W, \
3976 .help_cout = cout_##CC, \
3977 .help_op = op_##OP, \
3981 /* Allow 0 to be used for NULL in the table below. */
3989 static const DisasInsn insn_info
[] = {
3990 #include "insn-data.def"
3994 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) \
3995 case OPC: return &insn_info[insn_ ## NM];
3997 static const DisasInsn
*lookup_opc(uint16_t opc
)
4000 #include "insn-data.def"
4009 /* Extract a field from the insn. The INSN should be left-aligned in
4010 the uint64_t so that we can more easily utilize the big-bit-endian
4011 definitions we extract from the Principals of Operation. */
4013 static void extract_field(DisasFields
*o
, const DisasField
*f
, uint64_t insn
)
4021 /* Zero extract the field from the insn. */
4022 r
= (insn
<< f
->beg
) >> (64 - f
->size
);
4024 /* Sign-extend, or un-swap the field as necessary. */
4026 case 0: /* unsigned */
4028 case 1: /* signed */
4029 assert(f
->size
<= 32);
4030 m
= 1u << (f
->size
- 1);
4033 case 2: /* dl+dh split, signed 20 bit. */
4034 r
= ((int8_t)r
<< 12) | (r
>> 8);
4040 /* Validate that the "compressed" encoding we selected above is valid.
4041 I.e. we havn't make two different original fields overlap. */
4042 assert(((o
->presentC
>> f
->indexC
) & 1) == 0);
4043 o
->presentC
|= 1 << f
->indexC
;
4044 o
->presentO
|= 1 << f
->indexO
;
4046 o
->c
[f
->indexC
] = r
;
4049 /* Lookup the insn at the current PC, extracting the operands into O and
4050 returning the info struct for the insn. Returns NULL for invalid insn. */
4052 static const DisasInsn
*extract_insn(CPUS390XState
*env
, DisasContext
*s
,
4055 uint64_t insn
, pc
= s
->pc
;
4057 const DisasInsn
*info
;
4059 insn
= ld_code2(env
, pc
);
4060 op
= (insn
>> 8) & 0xff;
4061 ilen
= get_ilen(op
);
4062 s
->next_pc
= s
->pc
+ ilen
;
4069 insn
= ld_code4(env
, pc
) << 32;
4072 insn
= (insn
<< 48) | (ld_code4(env
, pc
+ 2) << 16);
4078 /* We can't actually determine the insn format until we've looked up
4079 the full insn opcode. Which we can't do without locating the
4080 secondary opcode. Assume by default that OP2 is at bit 40; for
4081 those smaller insns that don't actually have a secondary opcode
4082 this will correctly result in OP2 = 0. */
4088 case 0xb2: /* S, RRF, RRE */
4089 case 0xb3: /* RRE, RRD, RRF */
4090 case 0xb9: /* RRE, RRF */
4091 case 0xe5: /* SSE, SIL */
4092 op2
= (insn
<< 8) >> 56;
4096 case 0xc0: /* RIL */
4097 case 0xc2: /* RIL */
4098 case 0xc4: /* RIL */
4099 case 0xc6: /* RIL */
4100 case 0xc8: /* SSF */
4101 case 0xcc: /* RIL */
4102 op2
= (insn
<< 12) >> 60;
4104 case 0xd0 ... 0xdf: /* SS */
4110 case 0xee ... 0xf3: /* SS */
4111 case 0xf8 ... 0xfd: /* SS */
4115 op2
= (insn
<< 40) >> 56;
4119 memset(f
, 0, sizeof(*f
));
4123 /* Lookup the instruction. */
4124 info
= lookup_opc(op
<< 8 | op2
);
4126 /* If we found it, extract the operands. */
4128 DisasFormat fmt
= info
->fmt
;
4131 for (i
= 0; i
< NUM_C_FIELD
; ++i
) {
4132 extract_field(f
, &format_info
[fmt
].op
[i
], insn
);
4138 static ExitStatus
translate_one(CPUS390XState
*env
, DisasContext
*s
)
4140 const DisasInsn
*insn
;
4141 ExitStatus ret
= NO_EXIT
;
4145 insn
= extract_insn(env
, s
, &f
);
4147 /* If not found, try the old interpreter. This includes ILLOPC. */
4149 disas_s390_insn(env
, s
);
4150 switch (s
->is_jmp
) {
4158 ret
= EXIT_PC_UPDATED
;
4161 ret
= EXIT_NORETURN
;
4171 /* Set up the strutures we use to communicate with the helpers. */
4174 o
.g_out
= o
.g_out2
= o
.g_in1
= o
.g_in2
= false;
4175 TCGV_UNUSED_I64(o
.out
);
4176 TCGV_UNUSED_I64(o
.out2
);
4177 TCGV_UNUSED_I64(o
.in1
);
4178 TCGV_UNUSED_I64(o
.in2
);
4179 TCGV_UNUSED_I64(o
.addr1
);
4181 /* Implement the instruction. */
4182 if (insn
->help_in1
) {
4183 insn
->help_in1(s
, &f
, &o
);
4185 if (insn
->help_in2
) {
4186 insn
->help_in2(s
, &f
, &o
);
4188 if (insn
->help_prep
) {
4189 insn
->help_prep(s
, &f
, &o
);
4191 if (insn
->help_op
) {
4192 ret
= insn
->help_op(s
, &o
);
4194 if (insn
->help_wout
) {
4195 insn
->help_wout(s
, &f
, &o
);
4197 if (insn
->help_cout
) {
4198 insn
->help_cout(s
, &o
);
4201 /* Free any temporaries created by the helpers. */
4202 if (!TCGV_IS_UNUSED_I64(o
.out
) && !o
.g_out
) {
4203 tcg_temp_free_i64(o
.out
);
4205 if (!TCGV_IS_UNUSED_I64(o
.out2
) && !o
.g_out2
) {
4206 tcg_temp_free_i64(o
.out2
);
4208 if (!TCGV_IS_UNUSED_I64(o
.in1
) && !o
.g_in1
) {
4209 tcg_temp_free_i64(o
.in1
);
4211 if (!TCGV_IS_UNUSED_I64(o
.in2
) && !o
.g_in2
) {
4212 tcg_temp_free_i64(o
.in2
);
4214 if (!TCGV_IS_UNUSED_I64(o
.addr1
)) {
4215 tcg_temp_free_i64(o
.addr1
);
4218 /* Advance to the next instruction. */
4223 static inline void gen_intermediate_code_internal(CPUS390XState
*env
,
4224 TranslationBlock
*tb
,
4228 target_ulong pc_start
;
4229 uint64_t next_page_start
;
4230 uint16_t *gen_opc_end
;
4232 int num_insns
, max_insns
;
4240 if (!(tb
->flags
& FLAG_MASK_64
)) {
4241 pc_start
&= 0x7fffffff;
4246 dc
.cc_op
= CC_OP_DYNAMIC
;
4247 do_debug
= dc
.singlestep_enabled
= env
->singlestep_enabled
;
4248 dc
.is_jmp
= DISAS_NEXT
;
4250 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
4252 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
4255 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
4256 if (max_insns
== 0) {
4257 max_insns
= CF_COUNT_MASK
;
4264 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
4268 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
4271 tcg_ctx
.gen_opc_pc
[lj
] = dc
.pc
;
4272 gen_opc_cc_op
[lj
] = dc
.cc_op
;
4273 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
4274 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
4276 if (++num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
4280 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
4281 tcg_gen_debug_insn_start(dc
.pc
);
4285 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
4286 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
4287 if (bp
->pc
== dc
.pc
) {
4288 status
= EXIT_PC_STALE
;
4294 if (status
== NO_EXIT
) {
4295 status
= translate_one(env
, &dc
);
4298 /* If we reach a page boundary, are single stepping,
4299 or exhaust instruction count, stop generation. */
4300 if (status
== NO_EXIT
4301 && (dc
.pc
>= next_page_start
4302 || tcg_ctx
.gen_opc_ptr
>= gen_opc_end
4303 || num_insns
>= max_insns
4305 || env
->singlestep_enabled
)) {
4306 status
= EXIT_PC_STALE
;
4308 } while (status
== NO_EXIT
);
4310 if (tb
->cflags
& CF_LAST_IO
) {
4319 update_psw_addr(&dc
);
4321 case EXIT_PC_UPDATED
:
4322 if (singlestep
&& dc
.cc_op
!= CC_OP_DYNAMIC
) {
4323 gen_op_calc_cc(&dc
);
4325 /* Next TB starts off with CC_OP_DYNAMIC,
4326 so make sure the cc op type is in env */
4327 gen_op_set_cc_op(&dc
);
4330 gen_exception(EXCP_DEBUG
);
4332 /* Generate the return instruction */
4340 gen_icount_end(tb
, num_insns
);
4341 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
4343 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
4346 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
4349 tb
->size
= dc
.pc
- pc_start
;
4350 tb
->icount
= num_insns
;
4353 #if defined(S390X_DEBUG_DISAS)
4354 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
4355 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
4356 log_target_disas(env
, pc_start
, dc
.pc
- pc_start
, 1);
4362 void gen_intermediate_code (CPUS390XState
*env
, struct TranslationBlock
*tb
)
4364 gen_intermediate_code_internal(env
, tb
, 0);
4367 void gen_intermediate_code_pc (CPUS390XState
*env
, struct TranslationBlock
*tb
)
4369 gen_intermediate_code_internal(env
, tb
, 1);
4372 void restore_state_to_opc(CPUS390XState
*env
, TranslationBlock
*tb
, int pc_pos
)
4375 env
->psw
.addr
= tcg_ctx
.gen_opc_pc
[pc_pos
];
4376 cc_op
= gen_opc_cc_op
[pc_pos
];
4377 if ((cc_op
!= CC_OP_DYNAMIC
) && (cc_op
!= CC_OP_STATIC
)) {