4 * Copyright (c) 2009 Ulrich Hecht
5 * Copyright (c) 2010 Alexander Graf
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
26 /* #define DEBUG_ILLEGAL_INSTRUCTIONS */
27 /* #define DEBUG_INLINE_BRANCHES */
28 #define S390X_DEBUG_DISAS
29 /* #define S390X_DEBUG_DISAS_VERBOSE */
31 #ifdef S390X_DEBUG_DISAS_VERBOSE
32 # define LOG_DISAS(...) qemu_log(__VA_ARGS__)
34 # define LOG_DISAS(...) do { } while (0)
43 /* global register indexes */
44 static TCGv_ptr cpu_env
;
46 #include "gen-icount.h"
51 typedef struct DisasContext DisasContext
;
56 struct TranslationBlock
*tb
;
61 static void gen_op_calc_cc(DisasContext
*s
);
63 #ifdef DEBUG_INLINE_BRANCHES
64 static uint64_t inline_branch_hit
[CC_OP_MAX
];
65 static uint64_t inline_branch_miss
[CC_OP_MAX
];
68 static inline void debug_insn(uint64_t insn
)
70 LOG_DISAS("insn: 0x%" PRIx64
"\n", insn
);
73 static inline uint64_t pc_to_link_info(DisasContext
*s
, uint64_t pc
)
75 if (!(s
->tb
->flags
& FLAG_MASK_64
)) {
76 if (s
->tb
->flags
& FLAG_MASK_32
) {
77 return pc
| 0x80000000;
83 void cpu_dump_state(CPUState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
88 for (i
= 0; i
< 16; i
++) {
89 cpu_fprintf(f
, "R%02d=%016" PRIx64
, i
, env
->regs
[i
]);
97 for (i
= 0; i
< 16; i
++) {
98 cpu_fprintf(f
, "F%02d=%016" PRIx64
, i
, *(uint64_t *)&env
->fregs
[i
]);
100 cpu_fprintf(f
, "\n");
106 cpu_fprintf(f
, "\n");
108 #ifndef CONFIG_USER_ONLY
109 for (i
= 0; i
< 16; i
++) {
110 cpu_fprintf(f
, "C%02d=%016" PRIx64
, i
, env
->cregs
[i
]);
112 cpu_fprintf(f
, "\n");
119 cpu_fprintf(f
, "\n");
121 if (env
->cc_op
> 3) {
122 cpu_fprintf(f
, "PSW=mask %016" PRIx64
" addr %016" PRIx64
" cc %15s\n",
123 env
->psw
.mask
, env
->psw
.addr
, cc_name(env
->cc_op
));
125 cpu_fprintf(f
, "PSW=mask %016" PRIx64
" addr %016" PRIx64
" cc %02x\n",
126 env
->psw
.mask
, env
->psw
.addr
, env
->cc_op
);
129 #ifdef DEBUG_INLINE_BRANCHES
130 for (i
= 0; i
< CC_OP_MAX
; i
++) {
131 cpu_fprintf(f
, " %15s = %10ld\t%10ld\n", cc_name(i
),
132 inline_branch_miss
[i
], inline_branch_hit
[i
]);
137 static TCGv_i64 psw_addr
;
138 static TCGv_i64 psw_mask
;
140 static TCGv_i32 cc_op
;
141 static TCGv_i64 cc_src
;
142 static TCGv_i64 cc_dst
;
143 static TCGv_i64 cc_vr
;
145 static char cpu_reg_names
[10*3 + 6*4];
146 static TCGv_i64 regs
[16];
148 static uint8_t gen_opc_cc_op
[OPC_BUF_SIZE
];
150 void s390x_translate_init(void)
153 size_t cpu_reg_names_size
= sizeof(cpu_reg_names
);
156 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
157 psw_addr
= tcg_global_mem_new_i64(TCG_AREG0
, offsetof(CPUState
, psw
.addr
),
159 psw_mask
= tcg_global_mem_new_i64(TCG_AREG0
, offsetof(CPUState
, psw
.mask
),
162 cc_op
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUState
, cc_op
),
164 cc_src
= tcg_global_mem_new_i64(TCG_AREG0
, offsetof(CPUState
, cc_src
),
166 cc_dst
= tcg_global_mem_new_i64(TCG_AREG0
, offsetof(CPUState
, cc_dst
),
168 cc_vr
= tcg_global_mem_new_i64(TCG_AREG0
, offsetof(CPUState
, cc_vr
),
172 for (i
= 0; i
< 16; i
++) {
173 snprintf(p
, cpu_reg_names_size
, "r%d", i
);
174 regs
[i
] = tcg_global_mem_new(TCG_AREG0
,
175 offsetof(CPUState
, regs
[i
]), p
);
176 p
+= (i
< 10) ? 3 : 4;
177 cpu_reg_names_size
-= (i
< 10) ? 3 : 4;
181 static inline TCGv_i64
load_reg(int reg
)
183 TCGv_i64 r
= tcg_temp_new_i64();
184 tcg_gen_mov_i64(r
, regs
[reg
]);
188 static inline TCGv_i64
load_freg(int reg
)
190 TCGv_i64 r
= tcg_temp_new_i64();
191 tcg_gen_ld_i64(r
, cpu_env
, offsetof(CPUState
, fregs
[reg
].d
));
195 static inline TCGv_i32
load_freg32(int reg
)
197 TCGv_i32 r
= tcg_temp_new_i32();
198 tcg_gen_ld_i32(r
, cpu_env
, offsetof(CPUState
, fregs
[reg
].l
.upper
));
202 static inline TCGv_i32
load_reg32(int reg
)
204 TCGv_i32 r
= tcg_temp_new_i32();
205 tcg_gen_trunc_i64_i32(r
, regs
[reg
]);
209 static inline TCGv_i64
load_reg32_i64(int reg
)
211 TCGv_i64 r
= tcg_temp_new_i64();
212 tcg_gen_ext32s_i64(r
, regs
[reg
]);
216 static inline void store_reg(int reg
, TCGv_i64 v
)
218 tcg_gen_mov_i64(regs
[reg
], v
);
221 static inline void store_freg(int reg
, TCGv_i64 v
)
223 tcg_gen_st_i64(v
, cpu_env
, offsetof(CPUState
, fregs
[reg
].d
));
226 static inline void store_reg32(int reg
, TCGv_i32 v
)
228 #if HOST_LONG_BITS == 32
229 tcg_gen_mov_i32(TCGV_LOW(regs
[reg
]), v
);
231 TCGv_i64 tmp
= tcg_temp_new_i64();
232 tcg_gen_extu_i32_i64(tmp
, v
);
233 /* 32 bit register writes keep the upper half */
234 tcg_gen_deposit_i64(regs
[reg
], regs
[reg
], tmp
, 0, 32);
235 tcg_temp_free_i64(tmp
);
239 static inline void store_reg32_i64(int reg
, TCGv_i64 v
)
241 /* 32 bit register writes keep the upper half */
242 #if HOST_LONG_BITS == 32
243 tcg_gen_mov_i32(TCGV_LOW(regs
[reg
]), TCGV_LOW(v
));
245 tcg_gen_deposit_i64(regs
[reg
], regs
[reg
], v
, 0, 32);
249 static inline void store_reg16(int reg
, TCGv_i32 v
)
251 TCGv_i64 tmp
= tcg_temp_new_i64();
252 tcg_gen_extu_i32_i64(tmp
, v
);
253 /* 16 bit register writes keep the upper bytes */
254 tcg_gen_deposit_i64(regs
[reg
], regs
[reg
], tmp
, 0, 16);
255 tcg_temp_free_i64(tmp
);
258 static inline void store_reg8(int reg
, TCGv_i64 v
)
260 /* 8 bit register writes keep the upper bytes */
261 tcg_gen_deposit_i64(regs
[reg
], regs
[reg
], v
, 0, 8);
264 static inline void store_freg32(int reg
, TCGv_i32 v
)
266 tcg_gen_st_i32(v
, cpu_env
, offsetof(CPUState
, fregs
[reg
].l
.upper
));
269 static inline void update_psw_addr(DisasContext
*s
)
272 tcg_gen_movi_i64(psw_addr
, s
->pc
);
275 static inline void potential_page_fault(DisasContext
*s
)
277 #ifndef CONFIG_USER_ONLY
283 static inline uint64_t ld_code2(uint64_t pc
)
285 return (uint64_t)lduw_code(pc
);
288 static inline uint64_t ld_code4(uint64_t pc
)
290 return (uint64_t)ldl_code(pc
);
293 static inline uint64_t ld_code6(uint64_t pc
)
296 opc
= (uint64_t)lduw_code(pc
) << 32;
297 opc
|= (uint64_t)(uint32_t)ldl_code(pc
+2);
301 static inline int get_mem_index(DisasContext
*s
)
303 switch (s
->tb
->flags
& FLAG_MASK_ASC
) {
304 case PSW_ASC_PRIMARY
>> 32:
306 case PSW_ASC_SECONDARY
>> 32:
308 case PSW_ASC_HOME
>> 32:
316 static inline void gen_debug(DisasContext
*s
)
318 TCGv_i32 tmp
= tcg_const_i32(EXCP_DEBUG
);
321 gen_helper_exception(tmp
);
322 tcg_temp_free_i32(tmp
);
323 s
->is_jmp
= DISAS_EXCP
;
326 #ifdef CONFIG_USER_ONLY
328 static void gen_illegal_opcode(DisasContext
*s
, int ilc
)
330 TCGv_i32 tmp
= tcg_const_i32(EXCP_SPEC
);
333 gen_helper_exception(tmp
);
334 tcg_temp_free_i32(tmp
);
335 s
->is_jmp
= DISAS_EXCP
;
338 #else /* CONFIG_USER_ONLY */
340 static void debug_print_inst(DisasContext
*s
, int ilc
)
342 #ifdef DEBUG_ILLEGAL_INSTRUCTIONS
347 inst
= ld_code2(s
->pc
);
350 inst
= ld_code4(s
->pc
);
353 inst
= ld_code6(s
->pc
);
357 fprintf(stderr
, "Illegal instruction [%d at %016" PRIx64
"]: 0x%016"
358 PRIx64
"\n", ilc
, s
->pc
, inst
);
362 static void gen_program_exception(DisasContext
*s
, int ilc
, int code
)
366 debug_print_inst(s
, ilc
);
368 /* remember what pgm exeption this was */
369 tmp
= tcg_const_i32(code
);
370 tcg_gen_st_i32(tmp
, cpu_env
, offsetof(CPUState
, int_pgm_code
));
371 tcg_temp_free_i32(tmp
);
373 tmp
= tcg_const_i32(ilc
);
374 tcg_gen_st_i32(tmp
, cpu_env
, offsetof(CPUState
, int_pgm_ilc
));
375 tcg_temp_free_i32(tmp
);
377 /* advance past instruction */
384 /* trigger exception */
385 tmp
= tcg_const_i32(EXCP_PGM
);
386 gen_helper_exception(tmp
);
387 tcg_temp_free_i32(tmp
);
390 s
->is_jmp
= DISAS_EXCP
;
394 static void gen_illegal_opcode(DisasContext
*s
, int ilc
)
396 gen_program_exception(s
, ilc
, PGM_SPECIFICATION
);
399 static void gen_privileged_exception(DisasContext
*s
, int ilc
)
401 gen_program_exception(s
, ilc
, PGM_PRIVILEGED
);
404 static void check_privileged(DisasContext
*s
, int ilc
)
406 if (s
->tb
->flags
& (PSW_MASK_PSTATE
>> 32)) {
407 gen_privileged_exception(s
, ilc
);
411 #endif /* CONFIG_USER_ONLY */
413 static TCGv_i64
get_address(DisasContext
*s
, int x2
, int b2
, int d2
)
417 /* 31-bitify the immediate part; register contents are dealt with below */
418 if (!(s
->tb
->flags
& FLAG_MASK_64
)) {
424 tmp
= tcg_const_i64(d2
);
425 tcg_gen_add_i64(tmp
, tmp
, regs
[x2
]);
430 tcg_gen_add_i64(tmp
, tmp
, regs
[b2
]);
434 tmp
= tcg_const_i64(d2
);
435 tcg_gen_add_i64(tmp
, tmp
, regs
[b2
]);
440 tmp
= tcg_const_i64(d2
);
443 /* 31-bit mode mask if there are values loaded from registers */
444 if (!(s
->tb
->flags
& FLAG_MASK_64
) && (x2
|| b2
)) {
445 tcg_gen_andi_i64(tmp
, tmp
, 0x7fffffffUL
);
451 static void gen_op_movi_cc(DisasContext
*s
, uint32_t val
)
453 s
->cc_op
= CC_OP_CONST0
+ val
;
456 static void gen_op_update1_cc_i64(DisasContext
*s
, enum cc_op op
, TCGv_i64 dst
)
458 tcg_gen_discard_i64(cc_src
);
459 tcg_gen_mov_i64(cc_dst
, dst
);
460 tcg_gen_discard_i64(cc_vr
);
464 static void gen_op_update1_cc_i32(DisasContext
*s
, enum cc_op op
, TCGv_i32 dst
)
466 tcg_gen_discard_i64(cc_src
);
467 tcg_gen_extu_i32_i64(cc_dst
, dst
);
468 tcg_gen_discard_i64(cc_vr
);
472 static void gen_op_update2_cc_i64(DisasContext
*s
, enum cc_op op
, TCGv_i64 src
,
475 tcg_gen_mov_i64(cc_src
, src
);
476 tcg_gen_mov_i64(cc_dst
, dst
);
477 tcg_gen_discard_i64(cc_vr
);
481 static void gen_op_update2_cc_i32(DisasContext
*s
, enum cc_op op
, TCGv_i32 src
,
484 tcg_gen_extu_i32_i64(cc_src
, src
);
485 tcg_gen_extu_i32_i64(cc_dst
, dst
);
486 tcg_gen_discard_i64(cc_vr
);
490 static void gen_op_update3_cc_i64(DisasContext
*s
, enum cc_op op
, TCGv_i64 src
,
491 TCGv_i64 dst
, TCGv_i64 vr
)
493 tcg_gen_mov_i64(cc_src
, src
);
494 tcg_gen_mov_i64(cc_dst
, dst
);
495 tcg_gen_mov_i64(cc_vr
, vr
);
499 static void gen_op_update3_cc_i32(DisasContext
*s
, enum cc_op op
, TCGv_i32 src
,
500 TCGv_i32 dst
, TCGv_i32 vr
)
502 tcg_gen_extu_i32_i64(cc_src
, src
);
503 tcg_gen_extu_i32_i64(cc_dst
, dst
);
504 tcg_gen_extu_i32_i64(cc_vr
, vr
);
508 static inline void set_cc_nz_u32(DisasContext
*s
, TCGv_i32 val
)
510 gen_op_update1_cc_i32(s
, CC_OP_NZ
, val
);
513 static inline void set_cc_nz_u64(DisasContext
*s
, TCGv_i64 val
)
515 gen_op_update1_cc_i64(s
, CC_OP_NZ
, val
);
518 static inline void cmp_32(DisasContext
*s
, TCGv_i32 v1
, TCGv_i32 v2
,
521 gen_op_update2_cc_i32(s
, cond
, v1
, v2
);
524 static inline void cmp_64(DisasContext
*s
, TCGv_i64 v1
, TCGv_i64 v2
,
527 gen_op_update2_cc_i64(s
, cond
, v1
, v2
);
530 static inline void cmp_s32(DisasContext
*s
, TCGv_i32 v1
, TCGv_i32 v2
)
532 cmp_32(s
, v1
, v2
, CC_OP_LTGT_32
);
535 static inline void cmp_u32(DisasContext
*s
, TCGv_i32 v1
, TCGv_i32 v2
)
537 cmp_32(s
, v1
, v2
, CC_OP_LTUGTU_32
);
540 static inline void cmp_s32c(DisasContext
*s
, TCGv_i32 v1
, int32_t v2
)
542 /* XXX optimize for the constant? put it in s? */
543 TCGv_i32 tmp
= tcg_const_i32(v2
);
544 cmp_32(s
, v1
, tmp
, CC_OP_LTGT_32
);
545 tcg_temp_free_i32(tmp
);
548 static inline void cmp_u32c(DisasContext
*s
, TCGv_i32 v1
, uint32_t v2
)
550 TCGv_i32 tmp
= tcg_const_i32(v2
);
551 cmp_32(s
, v1
, tmp
, CC_OP_LTUGTU_32
);
552 tcg_temp_free_i32(tmp
);
555 static inline void cmp_s64(DisasContext
*s
, TCGv_i64 v1
, TCGv_i64 v2
)
557 cmp_64(s
, v1
, v2
, CC_OP_LTGT_64
);
560 static inline void cmp_u64(DisasContext
*s
, TCGv_i64 v1
, TCGv_i64 v2
)
562 cmp_64(s
, v1
, v2
, CC_OP_LTUGTU_64
);
565 static inline void cmp_s64c(DisasContext
*s
, TCGv_i64 v1
, int64_t v2
)
567 TCGv_i64 tmp
= tcg_const_i64(v2
);
569 tcg_temp_free_i64(tmp
);
572 static inline void cmp_u64c(DisasContext
*s
, TCGv_i64 v1
, uint64_t v2
)
574 TCGv_i64 tmp
= tcg_const_i64(v2
);
576 tcg_temp_free_i64(tmp
);
579 static inline void set_cc_s32(DisasContext
*s
, TCGv_i32 val
)
581 gen_op_update1_cc_i32(s
, CC_OP_LTGT0_32
, val
);
584 static inline void set_cc_s64(DisasContext
*s
, TCGv_i64 val
)
586 gen_op_update1_cc_i64(s
, CC_OP_LTGT0_64
, val
);
589 static void set_cc_add64(DisasContext
*s
, TCGv_i64 v1
, TCGv_i64 v2
, TCGv_i64 vr
)
591 gen_op_update3_cc_i64(s
, CC_OP_ADD_64
, v1
, v2
, vr
);
594 static void set_cc_addu64(DisasContext
*s
, TCGv_i64 v1
, TCGv_i64 v2
,
597 gen_op_update3_cc_i64(s
, CC_OP_ADDU_64
, v1
, v2
, vr
);
600 static void set_cc_sub64(DisasContext
*s
, TCGv_i64 v1
, TCGv_i64 v2
, TCGv_i64 vr
)
602 gen_op_update3_cc_i64(s
, CC_OP_SUB_64
, v1
, v2
, vr
);
605 static void set_cc_subu64(DisasContext
*s
, TCGv_i64 v1
, TCGv_i64 v2
,
608 gen_op_update3_cc_i64(s
, CC_OP_SUBU_64
, v1
, v2
, vr
);
611 static void set_cc_abs64(DisasContext
*s
, TCGv_i64 v1
)
613 gen_op_update1_cc_i64(s
, CC_OP_ABS_64
, v1
);
616 static void set_cc_nabs64(DisasContext
*s
, TCGv_i64 v1
)
618 gen_op_update1_cc_i64(s
, CC_OP_NABS_64
, v1
);
621 static void set_cc_add32(DisasContext
*s
, TCGv_i32 v1
, TCGv_i32 v2
, TCGv_i32 vr
)
623 gen_op_update3_cc_i32(s
, CC_OP_ADD_32
, v1
, v2
, vr
);
626 static void set_cc_addu32(DisasContext
*s
, TCGv_i32 v1
, TCGv_i32 v2
,
629 gen_op_update3_cc_i32(s
, CC_OP_ADDU_32
, v1
, v2
, vr
);
632 static void set_cc_sub32(DisasContext
*s
, TCGv_i32 v1
, TCGv_i32 v2
, TCGv_i32 vr
)
634 gen_op_update3_cc_i32(s
, CC_OP_SUB_32
, v1
, v2
, vr
);
637 static void set_cc_subu32(DisasContext
*s
, TCGv_i32 v1
, TCGv_i32 v2
,
640 gen_op_update3_cc_i32(s
, CC_OP_SUBU_32
, v1
, v2
, vr
);
643 static void set_cc_abs32(DisasContext
*s
, TCGv_i32 v1
)
645 gen_op_update1_cc_i32(s
, CC_OP_ABS_32
, v1
);
648 static void set_cc_nabs32(DisasContext
*s
, TCGv_i32 v1
)
650 gen_op_update1_cc_i32(s
, CC_OP_NABS_32
, v1
);
653 static void set_cc_comp32(DisasContext
*s
, TCGv_i32 v1
)
655 gen_op_update1_cc_i32(s
, CC_OP_COMP_32
, v1
);
658 static void set_cc_comp64(DisasContext
*s
, TCGv_i64 v1
)
660 gen_op_update1_cc_i64(s
, CC_OP_COMP_64
, v1
);
663 static void set_cc_icm(DisasContext
*s
, TCGv_i32 v1
, TCGv_i32 v2
)
665 gen_op_update2_cc_i32(s
, CC_OP_ICM
, v1
, v2
);
668 static void set_cc_cmp_f32_i64(DisasContext
*s
, TCGv_i32 v1
, TCGv_i64 v2
)
670 tcg_gen_extu_i32_i64(cc_src
, v1
);
671 tcg_gen_mov_i64(cc_dst
, v2
);
672 tcg_gen_discard_i64(cc_vr
);
673 s
->cc_op
= CC_OP_LTGT_F32
;
676 static void set_cc_nz_f32(DisasContext
*s
, TCGv_i32 v1
)
678 gen_op_update1_cc_i32(s
, CC_OP_NZ_F32
, v1
);
681 static inline void set_cc_nz_f64(DisasContext
*s
, TCGv_i64 v1
)
683 gen_op_update1_cc_i64(s
, CC_OP_NZ_F64
, v1
);
686 /* CC value is in env->cc_op */
687 static inline void set_cc_static(DisasContext
*s
)
689 tcg_gen_discard_i64(cc_src
);
690 tcg_gen_discard_i64(cc_dst
);
691 tcg_gen_discard_i64(cc_vr
);
692 s
->cc_op
= CC_OP_STATIC
;
695 static inline void gen_op_set_cc_op(DisasContext
*s
)
697 if (s
->cc_op
!= CC_OP_DYNAMIC
&& s
->cc_op
!= CC_OP_STATIC
) {
698 tcg_gen_movi_i32(cc_op
, s
->cc_op
);
702 static inline void gen_update_cc_op(DisasContext
*s
)
707 /* calculates cc into cc_op */
708 static void gen_op_calc_cc(DisasContext
*s
)
710 TCGv_i32 local_cc_op
= tcg_const_i32(s
->cc_op
);
711 TCGv_i64 dummy
= tcg_const_i64(0);
718 /* s->cc_op is the cc value */
719 tcg_gen_movi_i32(cc_op
, s
->cc_op
- CC_OP_CONST0
);
722 /* env->cc_op already is the cc value */
736 gen_helper_calc_cc(cc_op
, local_cc_op
, dummy
, cc_dst
, dummy
);
741 case CC_OP_LTUGTU_32
:
742 case CC_OP_LTUGTU_64
:
749 gen_helper_calc_cc(cc_op
, local_cc_op
, cc_src
, cc_dst
, dummy
);
760 gen_helper_calc_cc(cc_op
, local_cc_op
, cc_src
, cc_dst
, cc_vr
);
763 /* unknown operation - assume 3 arguments and cc_op in env */
764 gen_helper_calc_cc(cc_op
, cc_op
, cc_src
, cc_dst
, cc_vr
);
770 tcg_temp_free_i32(local_cc_op
);
772 /* We now have cc in cc_op as constant */
776 static inline void decode_rr(DisasContext
*s
, uint64_t insn
, int *r1
, int *r2
)
780 *r1
= (insn
>> 4) & 0xf;
784 static inline TCGv_i64
decode_rx(DisasContext
*s
, uint64_t insn
, int *r1
,
785 int *x2
, int *b2
, int *d2
)
789 *r1
= (insn
>> 20) & 0xf;
790 *x2
= (insn
>> 16) & 0xf;
791 *b2
= (insn
>> 12) & 0xf;
794 return get_address(s
, *x2
, *b2
, *d2
);
797 static inline void decode_rs(DisasContext
*s
, uint64_t insn
, int *r1
, int *r3
,
802 *r1
= (insn
>> 20) & 0xf;
804 *r3
= (insn
>> 16) & 0xf;
805 *b2
= (insn
>> 12) & 0xf;
809 static inline TCGv_i64
decode_si(DisasContext
*s
, uint64_t insn
, int *i2
,
814 *i2
= (insn
>> 16) & 0xff;
815 *b1
= (insn
>> 12) & 0xf;
818 return get_address(s
, 0, *b1
, *d1
);
821 static inline void gen_goto_tb(DisasContext
*s
, int tb_num
, target_ulong pc
)
823 TranslationBlock
*tb
;
828 /* NOTE: we handle the case where the TB spans two pages here */
829 if ((pc
& TARGET_PAGE_MASK
) == (tb
->pc
& TARGET_PAGE_MASK
) ||
830 (pc
& TARGET_PAGE_MASK
) == ((s
->pc
- 1) & TARGET_PAGE_MASK
)) {
831 /* jump to same page: we can use a direct jump */
832 tcg_gen_goto_tb(tb_num
);
833 tcg_gen_movi_i64(psw_addr
, pc
);
834 tcg_gen_exit_tb((long)tb
+ tb_num
);
836 /* jump to another page: currently not optimized */
837 tcg_gen_movi_i64(psw_addr
, pc
);
842 static inline void account_noninline_branch(DisasContext
*s
, int cc_op
)
844 #ifdef DEBUG_INLINE_BRANCHES
845 inline_branch_miss
[cc_op
]++;
849 static inline void account_inline_branch(DisasContext
*s
)
851 #ifdef DEBUG_INLINE_BRANCHES
852 inline_branch_hit
[s
->cc_op
]++;
856 static void gen_jcc(DisasContext
*s
, uint32_t mask
, int skip
)
858 TCGv_i32 tmp
, tmp2
, r
;
864 tmp
= tcg_temp_new_i32();
865 tcg_gen_trunc_i64_i32(tmp
, cc_dst
);
867 case 0x8 | 0x4: /* dst <= 0 */
868 tcg_gen_brcondi_i32(TCG_COND_GT
, tmp
, 0, skip
);
870 case 0x8 | 0x2: /* dst >= 0 */
871 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, skip
);
873 case 0x8: /* dst == 0 */
874 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, skip
);
876 case 0x7: /* dst != 0 */
877 case 0x6: /* dst != 0 */
878 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, skip
);
880 case 0x4: /* dst < 0 */
881 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, skip
);
883 case 0x2: /* dst > 0 */
884 tcg_gen_brcondi_i32(TCG_COND_LE
, tmp
, 0, skip
);
887 tcg_temp_free_i32(tmp
);
890 account_inline_branch(s
);
891 tcg_temp_free_i32(tmp
);
895 case 0x8 | 0x4: /* dst <= 0 */
896 tcg_gen_brcondi_i64(TCG_COND_GT
, cc_dst
, 0, skip
);
898 case 0x8 | 0x2: /* dst >= 0 */
899 tcg_gen_brcondi_i64(TCG_COND_LT
, cc_dst
, 0, skip
);
901 case 0x8: /* dst == 0 */
902 tcg_gen_brcondi_i64(TCG_COND_NE
, cc_dst
, 0, skip
);
904 case 0x7: /* dst != 0 */
905 case 0x6: /* dst != 0 */
906 tcg_gen_brcondi_i64(TCG_COND_EQ
, cc_dst
, 0, skip
);
908 case 0x4: /* dst < 0 */
909 tcg_gen_brcondi_i64(TCG_COND_GE
, cc_dst
, 0, skip
);
911 case 0x2: /* dst > 0 */
912 tcg_gen_brcondi_i64(TCG_COND_LE
, cc_dst
, 0, skip
);
917 account_inline_branch(s
);
920 tmp
= tcg_temp_new_i32();
921 tmp2
= tcg_temp_new_i32();
922 tcg_gen_trunc_i64_i32(tmp
, cc_src
);
923 tcg_gen_trunc_i64_i32(tmp2
, cc_dst
);
925 case 0x8 | 0x4: /* src <= dst */
926 tcg_gen_brcond_i32(TCG_COND_GT
, tmp
, tmp2
, skip
);
928 case 0x8 | 0x2: /* src >= dst */
929 tcg_gen_brcond_i32(TCG_COND_LT
, tmp
, tmp2
, skip
);
931 case 0x8: /* src == dst */
932 tcg_gen_brcond_i32(TCG_COND_NE
, tmp
, tmp2
, skip
);
934 case 0x7: /* src != dst */
935 case 0x6: /* src != dst */
936 tcg_gen_brcond_i32(TCG_COND_EQ
, tmp
, tmp2
, skip
);
938 case 0x4: /* src < dst */
939 tcg_gen_brcond_i32(TCG_COND_GE
, tmp
, tmp2
, skip
);
941 case 0x2: /* src > dst */
942 tcg_gen_brcond_i32(TCG_COND_LE
, tmp
, tmp2
, skip
);
945 tcg_temp_free_i32(tmp
);
946 tcg_temp_free_i32(tmp2
);
949 account_inline_branch(s
);
950 tcg_temp_free_i32(tmp
);
951 tcg_temp_free_i32(tmp2
);
955 case 0x8 | 0x4: /* src <= dst */
956 tcg_gen_brcond_i64(TCG_COND_GT
, cc_src
, cc_dst
, skip
);
958 case 0x8 | 0x2: /* src >= dst */
959 tcg_gen_brcond_i64(TCG_COND_LT
, cc_src
, cc_dst
, skip
);
961 case 0x8: /* src == dst */
962 tcg_gen_brcond_i64(TCG_COND_NE
, cc_src
, cc_dst
, skip
);
964 case 0x7: /* src != dst */
965 case 0x6: /* src != dst */
966 tcg_gen_brcond_i64(TCG_COND_EQ
, cc_src
, cc_dst
, skip
);
968 case 0x4: /* src < dst */
969 tcg_gen_brcond_i64(TCG_COND_GE
, cc_src
, cc_dst
, skip
);
971 case 0x2: /* src > dst */
972 tcg_gen_brcond_i64(TCG_COND_LE
, cc_src
, cc_dst
, skip
);
977 account_inline_branch(s
);
979 case CC_OP_LTUGTU_32
:
980 tmp
= tcg_temp_new_i32();
981 tmp2
= tcg_temp_new_i32();
982 tcg_gen_trunc_i64_i32(tmp
, cc_src
);
983 tcg_gen_trunc_i64_i32(tmp2
, cc_dst
);
985 case 0x8 | 0x4: /* src <= dst */
986 tcg_gen_brcond_i32(TCG_COND_GTU
, tmp
, tmp2
, skip
);
988 case 0x8 | 0x2: /* src >= dst */
989 tcg_gen_brcond_i32(TCG_COND_LTU
, tmp
, tmp2
, skip
);
991 case 0x8: /* src == dst */
992 tcg_gen_brcond_i32(TCG_COND_NE
, tmp
, tmp2
, skip
);
994 case 0x7: /* src != dst */
995 case 0x6: /* src != dst */
996 tcg_gen_brcond_i32(TCG_COND_EQ
, tmp
, tmp2
, skip
);
998 case 0x4: /* src < dst */
999 tcg_gen_brcond_i32(TCG_COND_GEU
, tmp
, tmp2
, skip
);
1001 case 0x2: /* src > dst */
1002 tcg_gen_brcond_i32(TCG_COND_LEU
, tmp
, tmp2
, skip
);
1005 tcg_temp_free_i32(tmp
);
1006 tcg_temp_free_i32(tmp2
);
1009 account_inline_branch(s
);
1010 tcg_temp_free_i32(tmp
);
1011 tcg_temp_free_i32(tmp2
);
1013 case CC_OP_LTUGTU_64
:
1015 case 0x8 | 0x4: /* src <= dst */
1016 tcg_gen_brcond_i64(TCG_COND_GTU
, cc_src
, cc_dst
, skip
);
1018 case 0x8 | 0x2: /* src >= dst */
1019 tcg_gen_brcond_i64(TCG_COND_LTU
, cc_src
, cc_dst
, skip
);
1021 case 0x8: /* src == dst */
1022 tcg_gen_brcond_i64(TCG_COND_NE
, cc_src
, cc_dst
, skip
);
1024 case 0x7: /* src != dst */
1025 case 0x6: /* src != dst */
1026 tcg_gen_brcond_i64(TCG_COND_EQ
, cc_src
, cc_dst
, skip
);
1028 case 0x4: /* src < dst */
1029 tcg_gen_brcond_i64(TCG_COND_GEU
, cc_src
, cc_dst
, skip
);
1031 case 0x2: /* src > dst */
1032 tcg_gen_brcond_i64(TCG_COND_LEU
, cc_src
, cc_dst
, skip
);
1037 account_inline_branch(s
);
1041 /* dst == 0 || dst != 0 */
1043 case 0x8 | 0x4 | 0x2:
1044 case 0x8 | 0x4 | 0x2 | 0x1:
1045 case 0x8 | 0x4 | 0x1:
1050 case 0x8 | 0x2 | 0x1:
1052 tcg_gen_brcondi_i64(TCG_COND_NE
, cc_dst
, 0, skip
);
1057 case 0x4 | 0x2 | 0x1:
1059 tcg_gen_brcondi_i64(TCG_COND_EQ
, cc_dst
, 0, skip
);
1064 account_inline_branch(s
);
1067 tmp
= tcg_temp_new_i32();
1068 tmp2
= tcg_temp_new_i32();
1070 tcg_gen_trunc_i64_i32(tmp
, cc_src
);
1071 tcg_gen_trunc_i64_i32(tmp2
, cc_dst
);
1072 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
1074 case 0x8: /* val & mask == 0 */
1075 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, skip
);
1077 case 0x4 | 0x2 | 0x1: /* val & mask != 0 */
1078 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, skip
);
1081 tcg_temp_free_i32(tmp
);
1082 tcg_temp_free_i32(tmp2
);
1085 tcg_temp_free_i32(tmp
);
1086 tcg_temp_free_i32(tmp2
);
1087 account_inline_branch(s
);
1090 tmp64
= tcg_temp_new_i64();
1092 tcg_gen_and_i64(tmp64
, cc_src
, cc_dst
);
1094 case 0x8: /* val & mask == 0 */
1095 tcg_gen_brcondi_i64(TCG_COND_NE
, tmp64
, 0, skip
);
1097 case 0x4 | 0x2 | 0x1: /* val & mask != 0 */
1098 tcg_gen_brcondi_i64(TCG_COND_EQ
, tmp64
, 0, skip
);
1101 tcg_temp_free_i64(tmp64
);
1104 tcg_temp_free_i64(tmp64
);
1105 account_inline_branch(s
);
1109 case 0x8: /* val == 0 */
1110 tcg_gen_brcondi_i64(TCG_COND_NE
, cc_dst
, 0, skip
);
1112 case 0x4 | 0x2 | 0x1: /* val != 0 */
1113 case 0x4 | 0x2: /* val != 0 */
1114 tcg_gen_brcondi_i64(TCG_COND_EQ
, cc_dst
, 0, skip
);
1119 account_inline_branch(s
);
1122 old_cc_op
= s
->cc_op
;
1123 goto do_dynamic_nocccalc
;
1127 old_cc_op
= s
->cc_op
;
1128 /* calculate cc value */
1131 do_dynamic_nocccalc
:
1132 /* jump based on cc */
1133 account_noninline_branch(s
, old_cc_op
);
1136 case 0x8 | 0x4 | 0x2 | 0x1:
1139 case 0x8 | 0x4 | 0x2: /* cc != 3 */
1140 tcg_gen_brcondi_i32(TCG_COND_EQ
, cc_op
, 3, skip
);
1142 case 0x8 | 0x4 | 0x1: /* cc != 2 */
1143 tcg_gen_brcondi_i32(TCG_COND_EQ
, cc_op
, 2, skip
);
1145 case 0x8 | 0x2 | 0x1: /* cc != 1 */
1146 tcg_gen_brcondi_i32(TCG_COND_EQ
, cc_op
, 1, skip
);
1148 case 0x8 | 0x2: /* cc == 0 ||Â cc == 2 */
1149 tmp
= tcg_temp_new_i32();
1150 tcg_gen_andi_i32(tmp
, cc_op
, 1);
1151 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, skip
);
1152 tcg_temp_free_i32(tmp
);
1154 case 0x8 | 0x4: /* cc < 2 */
1155 tcg_gen_brcondi_i32(TCG_COND_GEU
, cc_op
, 2, skip
);
1157 case 0x8: /* cc == 0 */
1158 tcg_gen_brcondi_i32(TCG_COND_NE
, cc_op
, 0, skip
);
1160 case 0x4 | 0x2 | 0x1: /* cc != 0 */
1161 tcg_gen_brcondi_i32(TCG_COND_EQ
, cc_op
, 0, skip
);
1163 case 0x4 | 0x1: /* cc == 1 ||Â cc == 3 */
1164 tmp
= tcg_temp_new_i32();
1165 tcg_gen_andi_i32(tmp
, cc_op
, 1);
1166 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, skip
);
1167 tcg_temp_free_i32(tmp
);
1169 case 0x4: /* cc == 1 */
1170 tcg_gen_brcondi_i32(TCG_COND_NE
, cc_op
, 1, skip
);
1172 case 0x2 | 0x1: /* cc > 1 */
1173 tcg_gen_brcondi_i32(TCG_COND_LEU
, cc_op
, 1, skip
);
1175 case 0x2: /* cc == 2 */
1176 tcg_gen_brcondi_i32(TCG_COND_NE
, cc_op
, 2, skip
);
1178 case 0x1: /* cc == 3 */
1179 tcg_gen_brcondi_i32(TCG_COND_NE
, cc_op
, 3, skip
);
1181 default: /* cc is masked by something else */
1182 tmp
= tcg_const_i32(3);
1184 tcg_gen_sub_i32(tmp
, tmp
, cc_op
);
1185 tmp2
= tcg_const_i32(1);
1187 tcg_gen_shl_i32(tmp2
, tmp2
, tmp
);
1188 r
= tcg_const_i32(mask
);
1189 /* mask & (1 << (3 - cc)) */
1190 tcg_gen_and_i32(r
, r
, tmp2
);
1191 tcg_temp_free_i32(tmp
);
1192 tcg_temp_free_i32(tmp2
);
1194 tcg_gen_brcondi_i32(TCG_COND_EQ
, r
, 0, skip
);
1195 tcg_temp_free_i32(r
);
1202 static void gen_bcr(DisasContext
*s
, uint32_t mask
, TCGv_i64 target
,
1209 tcg_gen_mov_i64(psw_addr
, target
);
1211 } else if (mask
== 0) {
1212 /* ignore cc and never match */
1213 gen_goto_tb(s
, 0, offset
+ 2);
1215 TCGv_i64 new_addr
= tcg_temp_local_new_i64();
1217 tcg_gen_mov_i64(new_addr
, target
);
1218 skip
= gen_new_label();
1219 gen_jcc(s
, mask
, skip
);
1220 tcg_gen_mov_i64(psw_addr
, new_addr
);
1221 tcg_temp_free_i64(new_addr
);
1223 gen_set_label(skip
);
1224 tcg_temp_free_i64(new_addr
);
1225 gen_goto_tb(s
, 1, offset
+ 2);
1229 static void gen_brc(uint32_t mask
, DisasContext
*s
, int32_t offset
)
1235 gen_goto_tb(s
, 0, s
->pc
+ offset
);
1236 } else if (mask
== 0) {
1237 /* ignore cc and never match */
1238 gen_goto_tb(s
, 0, s
->pc
+ 4);
1240 skip
= gen_new_label();
1241 gen_jcc(s
, mask
, skip
);
1242 gen_goto_tb(s
, 0, s
->pc
+ offset
);
1243 gen_set_label(skip
);
1244 gen_goto_tb(s
, 1, s
->pc
+ 4);
1246 s
->is_jmp
= DISAS_TB_JUMP
;
1249 static void gen_op_mvc(DisasContext
*s
, int l
, TCGv_i64 s1
, TCGv_i64 s2
)
1253 int l_memset
= gen_new_label();
1254 int l_out
= gen_new_label();
1255 TCGv_i64 dest
= tcg_temp_local_new_i64();
1256 TCGv_i64 src
= tcg_temp_local_new_i64();
1259 /* Find out if we should use the inline version of mvc */
1274 /* Fall back to helper */
1275 vl
= tcg_const_i32(l
);
1276 potential_page_fault(s
);
1277 gen_helper_mvc(vl
, s1
, s2
);
1278 tcg_temp_free_i32(vl
);
1282 tcg_gen_mov_i64(dest
, s1
);
1283 tcg_gen_mov_i64(src
, s2
);
1285 if (!(s
->tb
->flags
& FLAG_MASK_64
)) {
1286 /* XXX what if we overflow while moving? */
1287 tcg_gen_andi_i64(dest
, dest
, 0x7fffffffUL
);
1288 tcg_gen_andi_i64(src
, src
, 0x7fffffffUL
);
1291 tmp
= tcg_temp_new_i64();
1292 tcg_gen_addi_i64(tmp
, src
, 1);
1293 tcg_gen_brcond_i64(TCG_COND_EQ
, dest
, tmp
, l_memset
);
1294 tcg_temp_free_i64(tmp
);
1298 tmp
= tcg_temp_new_i64();
1300 tcg_gen_qemu_ld8u(tmp
, src
, get_mem_index(s
));
1301 tcg_gen_qemu_st8(tmp
, dest
, get_mem_index(s
));
1303 tcg_temp_free_i64(tmp
);
1306 tmp
= tcg_temp_new_i64();
1308 tcg_gen_qemu_ld16u(tmp
, src
, get_mem_index(s
));
1309 tcg_gen_qemu_st16(tmp
, dest
, get_mem_index(s
));
1311 tcg_temp_free_i64(tmp
);
1314 tmp
= tcg_temp_new_i64();
1316 tcg_gen_qemu_ld32u(tmp
, src
, get_mem_index(s
));
1317 tcg_gen_qemu_st32(tmp
, dest
, get_mem_index(s
));
1319 tcg_temp_free_i64(tmp
);
1322 tmp
= tcg_temp_new_i64();
1323 tmp2
= tcg_temp_new_i64();
1325 tcg_gen_qemu_ld32u(tmp
, src
, get_mem_index(s
));
1326 tcg_gen_addi_i64(src
, src
, 4);
1327 tcg_gen_qemu_ld8u(tmp2
, src
, get_mem_index(s
));
1328 tcg_gen_qemu_st32(tmp
, dest
, get_mem_index(s
));
1329 tcg_gen_addi_i64(dest
, dest
, 4);
1330 tcg_gen_qemu_st8(tmp2
, dest
, get_mem_index(s
));
1332 tcg_temp_free_i64(tmp
);
1333 tcg_temp_free_i64(tmp2
);
1336 tmp
= tcg_temp_new_i64();
1338 tcg_gen_qemu_ld64(tmp
, src
, get_mem_index(s
));
1339 tcg_gen_qemu_st64(tmp
, dest
, get_mem_index(s
));
1341 tcg_temp_free_i64(tmp
);
1344 /* The inline version can become too big for too uneven numbers, only
1345 use it on known good lengths */
1346 tmp
= tcg_temp_new_i64();
1347 tmp2
= tcg_const_i64(8);
1348 for (i
= 0; (i
+ 7) <= l
; i
+= 8) {
1349 tcg_gen_qemu_ld64(tmp
, src
, get_mem_index(s
));
1350 tcg_gen_qemu_st64(tmp
, dest
, get_mem_index(s
));
1352 tcg_gen_add_i64(src
, src
, tmp2
);
1353 tcg_gen_add_i64(dest
, dest
, tmp2
);
1356 tcg_temp_free_i64(tmp2
);
1357 tmp2
= tcg_const_i64(1);
1359 for (; i
<= l
; i
++) {
1360 tcg_gen_qemu_ld8u(tmp
, src
, get_mem_index(s
));
1361 tcg_gen_qemu_st8(tmp
, dest
, get_mem_index(s
));
1363 tcg_gen_add_i64(src
, src
, tmp2
);
1364 tcg_gen_add_i64(dest
, dest
, tmp2
);
1367 tcg_temp_free_i64(tmp2
);
1368 tcg_temp_free_i64(tmp
);
1374 gen_set_label(l_memset
);
1375 /* memset case (dest == (src + 1)) */
1377 tmp
= tcg_temp_new_i64();
1378 tmp2
= tcg_temp_new_i64();
1379 /* fill tmp with the byte */
1380 tcg_gen_qemu_ld8u(tmp
, src
, get_mem_index(s
));
1381 tcg_gen_shli_i64(tmp2
, tmp
, 8);
1382 tcg_gen_or_i64(tmp
, tmp
, tmp2
);
1383 tcg_gen_shli_i64(tmp2
, tmp
, 16);
1384 tcg_gen_or_i64(tmp
, tmp
, tmp2
);
1385 tcg_gen_shli_i64(tmp2
, tmp
, 32);
1386 tcg_gen_or_i64(tmp
, tmp
, tmp2
);
1387 tcg_temp_free_i64(tmp2
);
1389 tmp2
= tcg_const_i64(8);
1391 for (i
= 0; (i
+ 7) <= l
; i
+= 8) {
1392 tcg_gen_qemu_st64(tmp
, dest
, get_mem_index(s
));
1393 tcg_gen_addi_i64(dest
, dest
, 8);
1396 tcg_temp_free_i64(tmp2
);
1397 tmp2
= tcg_const_i64(1);
1399 for (; i
<= l
; i
++) {
1400 tcg_gen_qemu_st8(tmp
, dest
, get_mem_index(s
));
1401 tcg_gen_addi_i64(dest
, dest
, 1);
1404 tcg_temp_free_i64(tmp2
);
1405 tcg_temp_free_i64(tmp
);
1407 gen_set_label(l_out
);
1409 tcg_temp_free(dest
);
1413 static void gen_op_clc(DisasContext
*s
, int l
, TCGv_i64 s1
, TCGv_i64 s2
)
1419 /* check for simple 32bit or 64bit match */
1422 tmp
= tcg_temp_new_i64();
1423 tmp2
= tcg_temp_new_i64();
1425 tcg_gen_qemu_ld8u(tmp
, s1
, get_mem_index(s
));
1426 tcg_gen_qemu_ld8u(tmp2
, s2
, get_mem_index(s
));
1427 cmp_u64(s
, tmp
, tmp2
);
1429 tcg_temp_free_i64(tmp
);
1430 tcg_temp_free_i64(tmp2
);
1433 tmp
= tcg_temp_new_i64();
1434 tmp2
= tcg_temp_new_i64();
1436 tcg_gen_qemu_ld16u(tmp
, s1
, get_mem_index(s
));
1437 tcg_gen_qemu_ld16u(tmp2
, s2
, get_mem_index(s
));
1438 cmp_u64(s
, tmp
, tmp2
);
1440 tcg_temp_free_i64(tmp
);
1441 tcg_temp_free_i64(tmp2
);
1444 tmp
= tcg_temp_new_i64();
1445 tmp2
= tcg_temp_new_i64();
1447 tcg_gen_qemu_ld32u(tmp
, s1
, get_mem_index(s
));
1448 tcg_gen_qemu_ld32u(tmp2
, s2
, get_mem_index(s
));
1449 cmp_u64(s
, tmp
, tmp2
);
1451 tcg_temp_free_i64(tmp
);
1452 tcg_temp_free_i64(tmp2
);
1455 tmp
= tcg_temp_new_i64();
1456 tmp2
= tcg_temp_new_i64();
1458 tcg_gen_qemu_ld64(tmp
, s1
, get_mem_index(s
));
1459 tcg_gen_qemu_ld64(tmp2
, s2
, get_mem_index(s
));
1460 cmp_u64(s
, tmp
, tmp2
);
1462 tcg_temp_free_i64(tmp
);
1463 tcg_temp_free_i64(tmp2
);
1467 potential_page_fault(s
);
1468 vl
= tcg_const_i32(l
);
1469 gen_helper_clc(cc_op
, vl
, s1
, s2
);
1470 tcg_temp_free_i32(vl
);
1474 static void disas_e3(DisasContext
* s
, int op
, int r1
, int x2
, int b2
, int d2
)
1476 TCGv_i64 addr
, tmp
, tmp2
, tmp3
, tmp4
;
1477 TCGv_i32 tmp32_1
, tmp32_2
, tmp32_3
;
1479 LOG_DISAS("disas_e3: op 0x%x r1 %d x2 %d b2 %d d2 %d\n",
1480 op
, r1
, x2
, b2
, d2
);
1481 addr
= get_address(s
, x2
, b2
, d2
);
1483 case 0x2: /* LTG R1,D2(X2,B2) [RXY] */
1484 case 0x4: /* lg r1,d2(x2,b2) */
1485 tcg_gen_qemu_ld64(regs
[r1
], addr
, get_mem_index(s
));
1487 set_cc_s64(s
, regs
[r1
]);
1490 case 0x12: /* LT R1,D2(X2,B2) [RXY] */
1491 tmp2
= tcg_temp_new_i64();
1492 tmp32_1
= tcg_temp_new_i32();
1493 tcg_gen_qemu_ld32s(tmp2
, addr
, get_mem_index(s
));
1494 tcg_gen_trunc_i64_i32(tmp32_1
, tmp2
);
1495 store_reg32(r1
, tmp32_1
);
1496 set_cc_s32(s
, tmp32_1
);
1497 tcg_temp_free_i64(tmp2
);
1498 tcg_temp_free_i32(tmp32_1
);
1500 case 0xc: /* MSG R1,D2(X2,B2) [RXY] */
1501 case 0x1c: /* MSGF R1,D2(X2,B2) [RXY] */
1502 tmp2
= tcg_temp_new_i64();
1504 tcg_gen_qemu_ld64(tmp2
, addr
, get_mem_index(s
));
1506 tcg_gen_qemu_ld32s(tmp2
, addr
, get_mem_index(s
));
1508 tcg_gen_mul_i64(regs
[r1
], regs
[r1
], tmp2
);
1509 tcg_temp_free_i64(tmp2
);
1511 case 0xd: /* DSG R1,D2(X2,B2) [RXY] */
1512 case 0x1d: /* DSGF R1,D2(X2,B2) [RXY] */
1513 tmp2
= tcg_temp_new_i64();
1515 tcg_gen_qemu_ld32s(tmp2
, addr
, get_mem_index(s
));
1517 tcg_gen_qemu_ld64(tmp2
, addr
, get_mem_index(s
));
1519 tmp4
= load_reg(r1
+ 1);
1520 tmp3
= tcg_temp_new_i64();
1521 tcg_gen_div_i64(tmp3
, tmp4
, tmp2
);
1522 store_reg(r1
+ 1, tmp3
);
1523 tcg_gen_rem_i64(tmp3
, tmp4
, tmp2
);
1524 store_reg(r1
, tmp3
);
1525 tcg_temp_free_i64(tmp2
);
1526 tcg_temp_free_i64(tmp3
);
1527 tcg_temp_free_i64(tmp4
);
1529 case 0x8: /* AG R1,D2(X2,B2) [RXY] */
1530 case 0xa: /* ALG R1,D2(X2,B2) [RXY] */
1531 case 0x18: /* AGF R1,D2(X2,B2) [RXY] */
1532 case 0x1a: /* ALGF R1,D2(X2,B2) [RXY] */
1534 tmp2
= tcg_temp_new_i64();
1535 tcg_gen_qemu_ld32u(tmp2
, addr
, get_mem_index(s
));
1536 } else if (op
== 0x18) {
1537 tmp2
= tcg_temp_new_i64();
1538 tcg_gen_qemu_ld32s(tmp2
, addr
, get_mem_index(s
));
1540 tmp2
= tcg_temp_new_i64();
1541 tcg_gen_qemu_ld64(tmp2
, addr
, get_mem_index(s
));
1543 tmp4
= load_reg(r1
);
1544 tmp3
= tcg_temp_new_i64();
1545 tcg_gen_add_i64(tmp3
, tmp4
, tmp2
);
1546 store_reg(r1
, tmp3
);
1550 set_cc_add64(s
, tmp4
, tmp2
, tmp3
);
1554 set_cc_addu64(s
, tmp4
, tmp2
, tmp3
);
1559 tcg_temp_free_i64(tmp2
);
1560 tcg_temp_free_i64(tmp3
);
1561 tcg_temp_free_i64(tmp4
);
1563 case 0x9: /* SG R1,D2(X2,B2) [RXY] */
1564 case 0xb: /* SLG R1,D2(X2,B2) [RXY] */
1565 case 0x19: /* SGF R1,D2(X2,B2) [RXY] */
1566 case 0x1b: /* SLGF R1,D2(X2,B2) [RXY] */
1567 tmp2
= tcg_temp_new_i64();
1569 tcg_gen_qemu_ld32s(tmp2
, addr
, get_mem_index(s
));
1570 } else if (op
== 0x1b) {
1571 tcg_gen_qemu_ld32u(tmp2
, addr
, get_mem_index(s
));
1573 tcg_gen_qemu_ld64(tmp2
, addr
, get_mem_index(s
));
1575 tmp4
= load_reg(r1
);
1576 tmp3
= tcg_temp_new_i64();
1577 tcg_gen_sub_i64(tmp3
, tmp4
, tmp2
);
1578 store_reg(r1
, tmp3
);
1582 set_cc_sub64(s
, tmp4
, tmp2
, tmp3
);
1586 set_cc_subu64(s
, tmp4
, tmp2
, tmp3
);
1591 tcg_temp_free_i64(tmp2
);
1592 tcg_temp_free_i64(tmp3
);
1593 tcg_temp_free_i64(tmp4
);
1595 case 0xf: /* LRVG R1,D2(X2,B2) [RXE] */
1596 tmp2
= tcg_temp_new_i64();
1597 tcg_gen_qemu_ld64(tmp2
, addr
, get_mem_index(s
));
1598 tcg_gen_bswap64_i64(tmp2
, tmp2
);
1599 store_reg(r1
, tmp2
);
1600 tcg_temp_free_i64(tmp2
);
1602 case 0x14: /* LGF R1,D2(X2,B2) [RXY] */
1603 case 0x16: /* LLGF R1,D2(X2,B2) [RXY] */
1604 tmp2
= tcg_temp_new_i64();
1605 tcg_gen_qemu_ld32u(tmp2
, addr
, get_mem_index(s
));
1607 tcg_gen_ext32s_i64(tmp2
, tmp2
);
1609 store_reg(r1
, tmp2
);
1610 tcg_temp_free_i64(tmp2
);
1612 case 0x15: /* LGH R1,D2(X2,B2) [RXY] */
1613 tmp2
= tcg_temp_new_i64();
1614 tcg_gen_qemu_ld16s(tmp2
, addr
, get_mem_index(s
));
1615 store_reg(r1
, tmp2
);
1616 tcg_temp_free_i64(tmp2
);
1618 case 0x17: /* LLGT R1,D2(X2,B2) [RXY] */
1619 tmp2
= tcg_temp_new_i64();
1620 tcg_gen_qemu_ld32u(tmp2
, addr
, get_mem_index(s
));
1621 tcg_gen_andi_i64(tmp2
, tmp2
, 0x7fffffffULL
);
1622 store_reg(r1
, tmp2
);
1623 tcg_temp_free_i64(tmp2
);
1625 case 0x1e: /* LRV R1,D2(X2,B2) [RXY] */
1626 tmp2
= tcg_temp_new_i64();
1627 tmp32_1
= tcg_temp_new_i32();
1628 tcg_gen_qemu_ld32u(tmp2
, addr
, get_mem_index(s
));
1629 tcg_gen_trunc_i64_i32(tmp32_1
, tmp2
);
1630 tcg_temp_free_i64(tmp2
);
1631 tcg_gen_bswap32_i32(tmp32_1
, tmp32_1
);
1632 store_reg32(r1
, tmp32_1
);
1633 tcg_temp_free_i32(tmp32_1
);
1635 case 0x1f: /* LRVH R1,D2(X2,B2) [RXY] */
1636 tmp2
= tcg_temp_new_i64();
1637 tmp32_1
= tcg_temp_new_i32();
1638 tcg_gen_qemu_ld16u(tmp2
, addr
, get_mem_index(s
));
1639 tcg_gen_trunc_i64_i32(tmp32_1
, tmp2
);
1640 tcg_temp_free_i64(tmp2
);
1641 tcg_gen_bswap16_i32(tmp32_1
, tmp32_1
);
1642 store_reg16(r1
, tmp32_1
);
1643 tcg_temp_free_i32(tmp32_1
);
1645 case 0x20: /* CG R1,D2(X2,B2) [RXY] */
1646 case 0x21: /* CLG R1,D2(X2,B2) */
1647 case 0x30: /* CGF R1,D2(X2,B2) [RXY] */
1648 case 0x31: /* CLGF R1,D2(X2,B2) [RXY] */
1649 tmp2
= tcg_temp_new_i64();
1653 tcg_gen_qemu_ld64(tmp2
, addr
, get_mem_index(s
));
1656 tcg_gen_qemu_ld32s(tmp2
, addr
, get_mem_index(s
));
1659 tcg_gen_qemu_ld32u(tmp2
, addr
, get_mem_index(s
));
1667 cmp_s64(s
, regs
[r1
], tmp2
);
1671 cmp_u64(s
, regs
[r1
], tmp2
);
1676 tcg_temp_free_i64(tmp2
);
1678 case 0x24: /* stg r1, d2(x2,b2) */
1679 tcg_gen_qemu_st64(regs
[r1
], addr
, get_mem_index(s
));
1681 case 0x3e: /* STRV R1,D2(X2,B2) [RXY] */
1682 tmp32_1
= load_reg32(r1
);
1683 tmp2
= tcg_temp_new_i64();
1684 tcg_gen_bswap32_i32(tmp32_1
, tmp32_1
);
1685 tcg_gen_extu_i32_i64(tmp2
, tmp32_1
);
1686 tcg_temp_free_i32(tmp32_1
);
1687 tcg_gen_qemu_st32(tmp2
, addr
, get_mem_index(s
));
1688 tcg_temp_free_i64(tmp2
);
1690 case 0x50: /* STY R1,D2(X2,B2) [RXY] */
1691 tmp32_1
= load_reg32(r1
);
1692 tmp2
= tcg_temp_new_i64();
1693 tcg_gen_extu_i32_i64(tmp2
, tmp32_1
);
1694 tcg_temp_free_i32(tmp32_1
);
1695 tcg_gen_qemu_st32(tmp2
, addr
, get_mem_index(s
));
1696 tcg_temp_free_i64(tmp2
);
1698 case 0x57: /* XY R1,D2(X2,B2) [RXY] */
1699 tmp32_1
= load_reg32(r1
);
1700 tmp32_2
= tcg_temp_new_i32();
1701 tmp2
= tcg_temp_new_i64();
1702 tcg_gen_qemu_ld32u(tmp2
, addr
, get_mem_index(s
));
1703 tcg_gen_trunc_i64_i32(tmp32_2
, tmp2
);
1704 tcg_temp_free_i64(tmp2
);
1705 tcg_gen_xor_i32(tmp32_2
, tmp32_1
, tmp32_2
);
1706 store_reg32(r1
, tmp32_2
);
1707 set_cc_nz_u32(s
, tmp32_2
);
1708 tcg_temp_free_i32(tmp32_1
);
1709 tcg_temp_free_i32(tmp32_2
);
1711 case 0x58: /* LY R1,D2(X2,B2) [RXY] */
1712 tmp3
= tcg_temp_new_i64();
1713 tcg_gen_qemu_ld32u(tmp3
, addr
, get_mem_index(s
));
1714 store_reg32_i64(r1
, tmp3
);
1715 tcg_temp_free_i64(tmp3
);
1717 case 0x5a: /* AY R1,D2(X2,B2) [RXY] */
1718 case 0x5b: /* SY R1,D2(X2,B2) [RXY] */
1719 tmp32_1
= load_reg32(r1
);
1720 tmp32_2
= tcg_temp_new_i32();
1721 tmp32_3
= tcg_temp_new_i32();
1722 tmp2
= tcg_temp_new_i64();
1723 tcg_gen_qemu_ld32s(tmp2
, addr
, get_mem_index(s
));
1724 tcg_gen_trunc_i64_i32(tmp32_2
, tmp2
);
1725 tcg_temp_free_i64(tmp2
);
1728 tcg_gen_add_i32(tmp32_3
, tmp32_1
, tmp32_2
);
1731 tcg_gen_sub_i32(tmp32_3
, tmp32_1
, tmp32_2
);
1736 store_reg32(r1
, tmp32_3
);
1739 set_cc_add32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
1742 set_cc_sub32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
1747 tcg_temp_free_i32(tmp32_1
);
1748 tcg_temp_free_i32(tmp32_2
);
1749 tcg_temp_free_i32(tmp32_3
);
1751 case 0x71: /* LAY R1,D2(X2,B2) [RXY] */
1752 store_reg(r1
, addr
);
1754 case 0x72: /* STCY R1,D2(X2,B2) [RXY] */
1755 tmp32_1
= load_reg32(r1
);
1756 tmp2
= tcg_temp_new_i64();
1757 tcg_gen_ext_i32_i64(tmp2
, tmp32_1
);
1758 tcg_gen_qemu_st8(tmp2
, addr
, get_mem_index(s
));
1759 tcg_temp_free_i32(tmp32_1
);
1760 tcg_temp_free_i64(tmp2
);
1762 case 0x73: /* ICY R1,D2(X2,B2) [RXY] */
1763 tmp3
= tcg_temp_new_i64();
1764 tcg_gen_qemu_ld8u(tmp3
, addr
, get_mem_index(s
));
1765 store_reg8(r1
, tmp3
);
1766 tcg_temp_free_i64(tmp3
);
1768 case 0x76: /* LB R1,D2(X2,B2) [RXY] */
1769 case 0x77: /* LGB R1,D2(X2,B2) [RXY] */
1770 tmp2
= tcg_temp_new_i64();
1771 tcg_gen_qemu_ld8s(tmp2
, addr
, get_mem_index(s
));
1774 tcg_gen_ext8s_i64(tmp2
, tmp2
);
1775 store_reg32_i64(r1
, tmp2
);
1778 tcg_gen_ext8s_i64(tmp2
, tmp2
);
1779 store_reg(r1
, tmp2
);
1784 tcg_temp_free_i64(tmp2
);
1786 case 0x78: /* LHY R1,D2(X2,B2) [RXY] */
1787 tmp2
= tcg_temp_new_i64();
1788 tcg_gen_qemu_ld16s(tmp2
, addr
, get_mem_index(s
));
1789 store_reg32_i64(r1
, tmp2
);
1790 tcg_temp_free_i64(tmp2
);
1792 case 0x80: /* NG R1,D2(X2,B2) [RXY] */
1793 case 0x81: /* OG R1,D2(X2,B2) [RXY] */
1794 case 0x82: /* XG R1,D2(X2,B2) [RXY] */
1795 tmp3
= tcg_temp_new_i64();
1796 tcg_gen_qemu_ld64(tmp3
, addr
, get_mem_index(s
));
1799 tcg_gen_and_i64(regs
[r1
], regs
[r1
], tmp3
);
1802 tcg_gen_or_i64(regs
[r1
], regs
[r1
], tmp3
);
1805 tcg_gen_xor_i64(regs
[r1
], regs
[r1
], tmp3
);
1810 set_cc_nz_u64(s
, regs
[r1
]);
1811 tcg_temp_free_i64(tmp3
);
1813 case 0x86: /* MLG R1,D2(X2,B2) [RXY] */
1814 tmp2
= tcg_temp_new_i64();
1815 tmp32_1
= tcg_const_i32(r1
);
1816 tcg_gen_qemu_ld64(tmp2
, addr
, get_mem_index(s
));
1817 gen_helper_mlg(tmp32_1
, tmp2
);
1818 tcg_temp_free_i64(tmp2
);
1819 tcg_temp_free_i32(tmp32_1
);
1821 case 0x87: /* DLG R1,D2(X2,B2) [RXY] */
1822 tmp2
= tcg_temp_new_i64();
1823 tmp32_1
= tcg_const_i32(r1
);
1824 tcg_gen_qemu_ld64(tmp2
, addr
, get_mem_index(s
));
1825 gen_helper_dlg(tmp32_1
, tmp2
);
1826 tcg_temp_free_i64(tmp2
);
1827 tcg_temp_free_i32(tmp32_1
);
1829 case 0x88: /* ALCG R1,D2(X2,B2) [RXY] */
1830 tmp2
= tcg_temp_new_i64();
1831 tmp3
= tcg_temp_new_i64();
1832 tcg_gen_qemu_ld64(tmp2
, addr
, get_mem_index(s
));
1833 /* XXX possible optimization point */
1835 tcg_gen_extu_i32_i64(tmp3
, cc_op
);
1836 tcg_gen_shri_i64(tmp3
, tmp3
, 1);
1837 tcg_gen_andi_i64(tmp3
, tmp3
, 1);
1838 tcg_gen_add_i64(tmp3
, tmp2
, tmp3
);
1839 tcg_gen_add_i64(tmp3
, regs
[r1
], tmp3
);
1840 store_reg(r1
, tmp3
);
1841 set_cc_addu64(s
, regs
[r1
], tmp2
, tmp3
);
1842 tcg_temp_free_i64(tmp2
);
1843 tcg_temp_free_i64(tmp3
);
1845 case 0x89: /* SLBG R1,D2(X2,B2) [RXY] */
1846 tmp2
= tcg_temp_new_i64();
1847 tmp32_1
= tcg_const_i32(r1
);
1848 tcg_gen_qemu_ld64(tmp2
, addr
, get_mem_index(s
));
1849 /* XXX possible optimization point */
1851 gen_helper_slbg(cc_op
, cc_op
, tmp32_1
, regs
[r1
], tmp2
);
1853 tcg_temp_free_i64(tmp2
);
1854 tcg_temp_free_i32(tmp32_1
);
1856 case 0x90: /* LLGC R1,D2(X2,B2) [RXY] */
1857 tcg_gen_qemu_ld8u(regs
[r1
], addr
, get_mem_index(s
));
1859 case 0x91: /* LLGH R1,D2(X2,B2) [RXY] */
1860 tcg_gen_qemu_ld16u(regs
[r1
], addr
, get_mem_index(s
));
1862 case 0x94: /* LLC R1,D2(X2,B2) [RXY] */
1863 tmp2
= tcg_temp_new_i64();
1864 tcg_gen_qemu_ld8u(tmp2
, addr
, get_mem_index(s
));
1865 store_reg32_i64(r1
, tmp2
);
1866 tcg_temp_free_i64(tmp2
);
1868 case 0x95: /* LLH R1,D2(X2,B2) [RXY] */
1869 tmp2
= tcg_temp_new_i64();
1870 tcg_gen_qemu_ld16u(tmp2
, addr
, get_mem_index(s
));
1871 store_reg32_i64(r1
, tmp2
);
1872 tcg_temp_free_i64(tmp2
);
1874 case 0x96: /* ML R1,D2(X2,B2) [RXY] */
1875 tmp2
= tcg_temp_new_i64();
1876 tmp3
= load_reg((r1
+ 1) & 15);
1877 tcg_gen_ext32u_i64(tmp3
, tmp3
);
1878 tcg_gen_qemu_ld32u(tmp2
, addr
, get_mem_index(s
));
1879 tcg_gen_mul_i64(tmp2
, tmp2
, tmp3
);
1880 store_reg32_i64((r1
+ 1) & 15, tmp2
);
1881 tcg_gen_shri_i64(tmp2
, tmp2
, 32);
1882 store_reg32_i64(r1
, tmp2
);
1883 tcg_temp_free_i64(tmp2
);
1884 tcg_temp_free_i64(tmp3
);
1886 case 0x97: /* DL R1,D2(X2,B2) [RXY] */
1887 /* reg(r1) = reg(r1, r1+1) % ld32(addr) */
1888 /* reg(r1+1) = reg(r1, r1+1) / ld32(addr) */
1890 tmp2
= tcg_temp_new_i64();
1891 tcg_gen_qemu_ld32u(tmp2
, addr
, get_mem_index(s
));
1892 tmp3
= load_reg((r1
+ 1) & 15);
1893 tcg_gen_ext32u_i64(tmp2
, tmp2
);
1894 tcg_gen_ext32u_i64(tmp3
, tmp3
);
1895 tcg_gen_shli_i64(tmp
, tmp
, 32);
1896 tcg_gen_or_i64(tmp
, tmp
, tmp3
);
1898 tcg_gen_rem_i64(tmp3
, tmp
, tmp2
);
1899 tcg_gen_div_i64(tmp
, tmp
, tmp2
);
1900 store_reg32_i64((r1
+ 1) & 15, tmp
);
1901 store_reg32_i64(r1
, tmp3
);
1902 tcg_temp_free_i64(tmp
);
1903 tcg_temp_free_i64(tmp2
);
1904 tcg_temp_free_i64(tmp3
);
1906 case 0x98: /* ALC R1,D2(X2,B2) [RXY] */
1907 tmp2
= tcg_temp_new_i64();
1908 tmp32_1
= load_reg32(r1
);
1909 tmp32_2
= tcg_temp_new_i32();
1910 tmp32_3
= tcg_temp_new_i32();
1911 tcg_gen_qemu_ld32u(tmp2
, addr
, get_mem_index(s
));
1912 tcg_gen_trunc_i64_i32(tmp32_2
, tmp2
);
1913 /* XXX possible optimization point */
1915 gen_helper_addc_u32(tmp32_3
, cc_op
, tmp32_1
, tmp32_2
);
1916 set_cc_addu32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
1917 store_reg32(r1
, tmp32_3
);
1918 tcg_temp_free_i64(tmp2
);
1919 tcg_temp_free_i32(tmp32_1
);
1920 tcg_temp_free_i32(tmp32_2
);
1921 tcg_temp_free_i32(tmp32_3
);
1923 case 0x99: /* SLB R1,D2(X2,B2) [RXY] */
1924 tmp2
= tcg_temp_new_i64();
1925 tmp32_1
= tcg_const_i32(r1
);
1926 tmp32_2
= tcg_temp_new_i32();
1927 tcg_gen_qemu_ld32u(tmp2
, addr
, get_mem_index(s
));
1928 tcg_gen_trunc_i64_i32(tmp32_2
, tmp2
);
1929 /* XXX possible optimization point */
1931 gen_helper_slb(cc_op
, cc_op
, tmp32_1
, tmp32_2
);
1933 tcg_temp_free_i64(tmp2
);
1934 tcg_temp_free_i32(tmp32_1
);
1935 tcg_temp_free_i32(tmp32_2
);
1938 LOG_DISAS("illegal e3 operation 0x%x\n", op
);
1939 gen_illegal_opcode(s
, 3);
1942 tcg_temp_free_i64(addr
);
1945 #ifndef CONFIG_USER_ONLY
1946 static void disas_e5(DisasContext
* s
, uint64_t insn
)
1949 int op
= (insn
>> 32) & 0xff;
1951 tmp
= get_address(s
, 0, (insn
>> 28) & 0xf, (insn
>> 16) & 0xfff);
1952 tmp2
= get_address(s
, 0, (insn
>> 12) & 0xf, insn
& 0xfff);
1954 LOG_DISAS("disas_e5: insn %" PRIx64
"\n", insn
);
1956 case 0x01: /* TPROT D1(B1),D2(B2) [SSE] */
1957 /* Test Protection */
1958 potential_page_fault(s
);
1959 gen_helper_tprot(cc_op
, tmp
, tmp2
);
1963 LOG_DISAS("illegal e5 operation 0x%x\n", op
);
1964 gen_illegal_opcode(s
, 3);
1968 tcg_temp_free_i64(tmp
);
1969 tcg_temp_free_i64(tmp2
);
1973 static void disas_eb(DisasContext
*s
, int op
, int r1
, int r3
, int b2
, int d2
)
1975 TCGv_i64 tmp
, tmp2
, tmp3
, tmp4
;
1976 TCGv_i32 tmp32_1
, tmp32_2
;
1980 LOG_DISAS("disas_eb: op 0x%x r1 %d r3 %d b2 %d d2 0x%x\n",
1981 op
, r1
, r3
, b2
, d2
);
1983 case 0xc: /* SRLG R1,R3,D2(B2) [RSY] */
1984 case 0xd: /* SLLG R1,R3,D2(B2) [RSY] */
1985 case 0xa: /* SRAG R1,R3,D2(B2) [RSY] */
1986 case 0xb: /* SLAG R1,R3,D2(B2) [RSY] */
1987 case 0x1c: /* RLLG R1,R3,D2(B2) [RSY] */
1989 tmp
= get_address(s
, 0, b2
, d2
);
1990 tcg_gen_andi_i64(tmp
, tmp
, 0x3f);
1992 tmp
= tcg_const_i64(d2
& 0x3f);
1996 tcg_gen_shr_i64(regs
[r1
], regs
[r3
], tmp
);
1999 tcg_gen_shl_i64(regs
[r1
], regs
[r3
], tmp
);
2002 tcg_gen_sar_i64(regs
[r1
], regs
[r3
], tmp
);
2005 tmp2
= tcg_temp_new_i64();
2006 tmp3
= tcg_temp_new_i64();
2007 gen_op_update2_cc_i64(s
, CC_OP_SLAG
, regs
[r3
], tmp
);
2008 tcg_gen_shl_i64(tmp2
, regs
[r3
], tmp
);
2009 /* override sign bit with source sign */
2010 tcg_gen_andi_i64(tmp2
, tmp2
, ~0x8000000000000000ULL
);
2011 tcg_gen_andi_i64(tmp3
, regs
[r3
], 0x8000000000000000ULL
);
2012 tcg_gen_or_i64(regs
[r1
], tmp2
, tmp3
);
2013 tcg_temp_free_i64(tmp2
);
2014 tcg_temp_free_i64(tmp3
);
2017 tcg_gen_rotl_i64(regs
[r1
], regs
[r3
], tmp
);
2024 set_cc_s64(s
, regs
[r1
]);
2026 tcg_temp_free_i64(tmp
);
2028 case 0x1d: /* RLL R1,R3,D2(B2) [RSY] */
2030 tmp
= get_address(s
, 0, b2
, d2
);
2031 tcg_gen_andi_i64(tmp
, tmp
, 0x3f);
2033 tmp
= tcg_const_i64(d2
& 0x3f);
2035 tmp32_1
= tcg_temp_new_i32();
2036 tmp32_2
= load_reg32(r3
);
2037 tcg_gen_trunc_i64_i32(tmp32_1
, tmp
);
2040 tcg_gen_rotl_i32(tmp32_1
, tmp32_2
, tmp32_1
);
2046 store_reg32(r1
, tmp32_1
);
2047 tcg_temp_free_i64(tmp
);
2048 tcg_temp_free_i32(tmp32_1
);
2049 tcg_temp_free_i32(tmp32_2
);
2051 case 0x4: /* LMG R1,R3,D2(B2) [RSE] */
2052 case 0x24: /* STMG R1,R3,D2(B2) [RSE] */
2055 case 0x26: /* STMH R1,R3,D2(B2) [RSE] */
2056 case 0x96: /* LMH R1,R3,D2(B2) [RSE] */
2059 /* Apparently, unrolling lmg/stmg of any size gains performance -
2060 even for very long ones... */
2061 tmp
= get_address(s
, 0, b2
, d2
);
2062 tmp3
= tcg_const_i64(stm_len
);
2063 tmp4
= tcg_const_i64(op
== 0x26 ? 32 : 4);
2064 for (i
= r1
;; i
= (i
+ 1) % 16) {
2067 tcg_gen_qemu_ld64(regs
[i
], tmp
, get_mem_index(s
));
2070 tmp2
= tcg_temp_new_i64();
2071 #if HOST_LONG_BITS == 32
2072 tcg_gen_qemu_ld32u(tmp2
, tmp
, get_mem_index(s
));
2073 tcg_gen_trunc_i64_i32(TCGV_HIGH(regs
[i
]), tmp2
);
2075 tcg_gen_qemu_ld32u(tmp2
, tmp
, get_mem_index(s
));
2076 tcg_gen_shl_i64(tmp2
, tmp2
, tmp4
);
2077 tcg_gen_ext32u_i64(regs
[i
], regs
[i
]);
2078 tcg_gen_or_i64(regs
[i
], regs
[i
], tmp2
);
2080 tcg_temp_free_i64(tmp2
);
2083 tcg_gen_qemu_st64(regs
[i
], tmp
, get_mem_index(s
));
2086 tmp2
= tcg_temp_new_i64();
2087 tcg_gen_shr_i64(tmp2
, regs
[i
], tmp4
);
2088 tcg_gen_qemu_st32(tmp2
, tmp
, get_mem_index(s
));
2089 tcg_temp_free_i64(tmp2
);
2097 tcg_gen_add_i64(tmp
, tmp
, tmp3
);
2099 tcg_temp_free_i64(tmp
);
2100 tcg_temp_free_i64(tmp3
);
2101 tcg_temp_free_i64(tmp4
);
2103 case 0x2c: /* STCMH R1,M3,D2(B2) [RSY] */
2104 tmp
= get_address(s
, 0, b2
, d2
);
2105 tmp32_1
= tcg_const_i32(r1
);
2106 tmp32_2
= tcg_const_i32(r3
);
2107 potential_page_fault(s
);
2108 gen_helper_stcmh(tmp32_1
, tmp
, tmp32_2
);
2109 tcg_temp_free_i64(tmp
);
2110 tcg_temp_free_i32(tmp32_1
);
2111 tcg_temp_free_i32(tmp32_2
);
2113 #ifndef CONFIG_USER_ONLY
2114 case 0x2f: /* LCTLG R1,R3,D2(B2) [RSE] */
2116 check_privileged(s
, ilc
);
2117 tmp
= get_address(s
, 0, b2
, d2
);
2118 tmp32_1
= tcg_const_i32(r1
);
2119 tmp32_2
= tcg_const_i32(r3
);
2120 potential_page_fault(s
);
2121 gen_helper_lctlg(tmp32_1
, tmp
, tmp32_2
);
2122 tcg_temp_free_i64(tmp
);
2123 tcg_temp_free_i32(tmp32_1
);
2124 tcg_temp_free_i32(tmp32_2
);
2126 case 0x25: /* STCTG R1,R3,D2(B2) [RSE] */
2128 check_privileged(s
, ilc
);
2129 tmp
= get_address(s
, 0, b2
, d2
);
2130 tmp32_1
= tcg_const_i32(r1
);
2131 tmp32_2
= tcg_const_i32(r3
);
2132 potential_page_fault(s
);
2133 gen_helper_stctg(tmp32_1
, tmp
, tmp32_2
);
2134 tcg_temp_free_i64(tmp
);
2135 tcg_temp_free_i32(tmp32_1
);
2136 tcg_temp_free_i32(tmp32_2
);
2139 case 0x30: /* CSG R1,R3,D2(B2) [RSY] */
2140 tmp
= get_address(s
, 0, b2
, d2
);
2141 tmp32_1
= tcg_const_i32(r1
);
2142 tmp32_2
= tcg_const_i32(r3
);
2143 potential_page_fault(s
);
2144 /* XXX rewrite in tcg */
2145 gen_helper_csg(cc_op
, tmp32_1
, tmp
, tmp32_2
);
2147 tcg_temp_free_i64(tmp
);
2148 tcg_temp_free_i32(tmp32_1
);
2149 tcg_temp_free_i32(tmp32_2
);
2151 case 0x3e: /* CDSG R1,R3,D2(B2) [RSY] */
2152 tmp
= get_address(s
, 0, b2
, d2
);
2153 tmp32_1
= tcg_const_i32(r1
);
2154 tmp32_2
= tcg_const_i32(r3
);
2155 potential_page_fault(s
);
2156 /* XXX rewrite in tcg */
2157 gen_helper_cdsg(cc_op
, tmp32_1
, tmp
, tmp32_2
);
2159 tcg_temp_free_i64(tmp
);
2160 tcg_temp_free_i32(tmp32_1
);
2161 tcg_temp_free_i32(tmp32_2
);
2163 case 0x51: /* TMY D1(B1),I2 [SIY] */
2164 tmp
= get_address(s
, 0, b2
, d2
); /* SIY -> this is the destination */
2165 tmp2
= tcg_const_i64((r1
<< 4) | r3
);
2166 tcg_gen_qemu_ld8u(tmp
, tmp
, get_mem_index(s
));
2167 /* yes, this is a 32 bit operation with 64 bit tcg registers, because
2168 that incurs less conversions */
2169 cmp_64(s
, tmp
, tmp2
, CC_OP_TM_32
);
2170 tcg_temp_free_i64(tmp
);
2171 tcg_temp_free_i64(tmp2
);
2173 case 0x52: /* MVIY D1(B1),I2 [SIY] */
2174 tmp
= get_address(s
, 0, b2
, d2
); /* SIY -> this is the destination */
2175 tmp2
= tcg_const_i64((r1
<< 4) | r3
);
2176 tcg_gen_qemu_st8(tmp2
, tmp
, get_mem_index(s
));
2177 tcg_temp_free_i64(tmp
);
2178 tcg_temp_free_i64(tmp2
);
2180 case 0x55: /* CLIY D1(B1),I2 [SIY] */
2181 tmp3
= get_address(s
, 0, b2
, d2
); /* SIY -> this is the 1st operand */
2182 tmp
= tcg_temp_new_i64();
2183 tmp32_1
= tcg_temp_new_i32();
2184 tcg_gen_qemu_ld8u(tmp
, tmp3
, get_mem_index(s
));
2185 tcg_gen_trunc_i64_i32(tmp32_1
, tmp
);
2186 cmp_u32c(s
, tmp32_1
, (r1
<< 4) | r3
);
2187 tcg_temp_free_i64(tmp
);
2188 tcg_temp_free_i64(tmp3
);
2189 tcg_temp_free_i32(tmp32_1
);
2191 case 0x80: /* ICMH R1,M3,D2(B2) [RSY] */
2192 tmp
= get_address(s
, 0, b2
, d2
);
2193 tmp32_1
= tcg_const_i32(r1
);
2194 tmp32_2
= tcg_const_i32(r3
);
2195 potential_page_fault(s
);
2196 /* XXX split CC calculation out */
2197 gen_helper_icmh(cc_op
, tmp32_1
, tmp
, tmp32_2
);
2199 tcg_temp_free_i64(tmp
);
2200 tcg_temp_free_i32(tmp32_1
);
2201 tcg_temp_free_i32(tmp32_2
);
2204 LOG_DISAS("illegal eb operation 0x%x\n", op
);
2205 gen_illegal_opcode(s
, ilc
);
2210 static void disas_ed(DisasContext
*s
, int op
, int r1
, int x2
, int b2
, int d2
,
2213 TCGv_i32 tmp_r1
, tmp32
;
2215 addr
= get_address(s
, x2
, b2
, d2
);
2216 tmp_r1
= tcg_const_i32(r1
);
2218 case 0x5: /* LXDB R1,D2(X2,B2) [RXE] */
2219 potential_page_fault(s
);
2220 gen_helper_lxdb(tmp_r1
, addr
);
2222 case 0x9: /* CEB R1,D2(X2,B2) [RXE] */
2223 tmp
= tcg_temp_new_i64();
2224 tmp32
= load_freg32(r1
);
2225 tcg_gen_qemu_ld32u(tmp
, addr
, get_mem_index(s
));
2226 set_cc_cmp_f32_i64(s
, tmp32
, tmp
);
2227 tcg_temp_free_i64(tmp
);
2228 tcg_temp_free_i32(tmp32
);
2230 case 0xa: /* AEB R1,D2(X2,B2) [RXE] */
2231 tmp
= tcg_temp_new_i64();
2232 tmp32
= tcg_temp_new_i32();
2233 tcg_gen_qemu_ld32u(tmp
, addr
, get_mem_index(s
));
2234 tcg_gen_trunc_i64_i32(tmp32
, tmp
);
2235 gen_helper_aeb(tmp_r1
, tmp32
);
2236 tcg_temp_free_i64(tmp
);
2237 tcg_temp_free_i32(tmp32
);
2239 tmp32
= load_freg32(r1
);
2240 set_cc_nz_f32(s
, tmp32
);
2241 tcg_temp_free_i32(tmp32
);
2243 case 0xb: /* SEB R1,D2(X2,B2) [RXE] */
2244 tmp
= tcg_temp_new_i64();
2245 tmp32
= tcg_temp_new_i32();
2246 tcg_gen_qemu_ld32u(tmp
, addr
, get_mem_index(s
));
2247 tcg_gen_trunc_i64_i32(tmp32
, tmp
);
2248 gen_helper_seb(tmp_r1
, tmp32
);
2249 tcg_temp_free_i64(tmp
);
2250 tcg_temp_free_i32(tmp32
);
2252 tmp32
= load_freg32(r1
);
2253 set_cc_nz_f32(s
, tmp32
);
2254 tcg_temp_free_i32(tmp32
);
2256 case 0xd: /* DEB R1,D2(X2,B2) [RXE] */
2257 tmp
= tcg_temp_new_i64();
2258 tmp32
= tcg_temp_new_i32();
2259 tcg_gen_qemu_ld32u(tmp
, addr
, get_mem_index(s
));
2260 tcg_gen_trunc_i64_i32(tmp32
, tmp
);
2261 gen_helper_deb(tmp_r1
, tmp32
);
2262 tcg_temp_free_i64(tmp
);
2263 tcg_temp_free_i32(tmp32
);
2265 case 0x10: /* TCEB R1,D2(X2,B2) [RXE] */
2266 potential_page_fault(s
);
2267 gen_helper_tceb(cc_op
, tmp_r1
, addr
);
2270 case 0x11: /* TCDB R1,D2(X2,B2) [RXE] */
2271 potential_page_fault(s
);
2272 gen_helper_tcdb(cc_op
, tmp_r1
, addr
);
2275 case 0x12: /* TCXB R1,D2(X2,B2) [RXE] */
2276 potential_page_fault(s
);
2277 gen_helper_tcxb(cc_op
, tmp_r1
, addr
);
2280 case 0x17: /* MEEB R1,D2(X2,B2) [RXE] */
2281 tmp
= tcg_temp_new_i64();
2282 tmp32
= tcg_temp_new_i32();
2283 tcg_gen_qemu_ld32u(tmp
, addr
, get_mem_index(s
));
2284 tcg_gen_trunc_i64_i32(tmp32
, tmp
);
2285 gen_helper_meeb(tmp_r1
, tmp32
);
2286 tcg_temp_free_i64(tmp
);
2287 tcg_temp_free_i32(tmp32
);
2289 case 0x19: /* CDB R1,D2(X2,B2) [RXE] */
2290 potential_page_fault(s
);
2291 gen_helper_cdb(cc_op
, tmp_r1
, addr
);
2294 case 0x1a: /* ADB R1,D2(X2,B2) [RXE] */
2295 potential_page_fault(s
);
2296 gen_helper_adb(cc_op
, tmp_r1
, addr
);
2299 case 0x1b: /* SDB R1,D2(X2,B2) [RXE] */
2300 potential_page_fault(s
);
2301 gen_helper_sdb(cc_op
, tmp_r1
, addr
);
2304 case 0x1c: /* MDB R1,D2(X2,B2) [RXE] */
2305 potential_page_fault(s
);
2306 gen_helper_mdb(tmp_r1
, addr
);
2308 case 0x1d: /* DDB R1,D2(X2,B2) [RXE] */
2309 potential_page_fault(s
);
2310 gen_helper_ddb(tmp_r1
, addr
);
2312 case 0x1e: /* MADB R1,R3,D2(X2,B2) [RXF] */
2313 /* for RXF insns, r1 is R3 and r1b is R1 */
2314 tmp32
= tcg_const_i32(r1b
);
2315 potential_page_fault(s
);
2316 gen_helper_madb(tmp32
, addr
, tmp_r1
);
2317 tcg_temp_free_i32(tmp32
);
2320 LOG_DISAS("illegal ed operation 0x%x\n", op
);
2321 gen_illegal_opcode(s
, 3);
2324 tcg_temp_free_i32(tmp_r1
);
2325 tcg_temp_free_i64(addr
);
2328 static void disas_a5(DisasContext
*s
, int op
, int r1
, int i2
)
2332 LOG_DISAS("disas_a5: op 0x%x r1 %d i2 0x%x\n", op
, r1
, i2
);
2334 case 0x0: /* IIHH R1,I2 [RI] */
2335 tmp
= tcg_const_i64(i2
);
2336 tcg_gen_deposit_i64(regs
[r1
], regs
[r1
], tmp
, 48, 16);
2338 case 0x1: /* IIHL R1,I2 [RI] */
2339 tmp
= tcg_const_i64(i2
);
2340 tcg_gen_deposit_i64(regs
[r1
], regs
[r1
], tmp
, 32, 16);
2342 case 0x2: /* IILH R1,I2 [RI] */
2343 tmp
= tcg_const_i64(i2
);
2344 tcg_gen_deposit_i64(regs
[r1
], regs
[r1
], tmp
, 16, 16);
2346 case 0x3: /* IILL R1,I2 [RI] */
2347 tmp
= tcg_const_i64(i2
);
2348 tcg_gen_deposit_i64(regs
[r1
], regs
[r1
], tmp
, 0, 16);
2350 case 0x4: /* NIHH R1,I2 [RI] */
2351 case 0x8: /* OIHH R1,I2 [RI] */
2353 tmp32
= tcg_temp_new_i32();
2356 tmp2
= tcg_const_i64((((uint64_t)i2
) << 48)
2357 | 0x0000ffffffffffffULL
);
2358 tcg_gen_and_i64(tmp
, tmp
, tmp2
);
2361 tmp2
= tcg_const_i64(((uint64_t)i2
) << 48);
2362 tcg_gen_or_i64(tmp
, tmp
, tmp2
);
2368 tcg_gen_shri_i64(tmp2
, tmp
, 48);
2369 tcg_gen_trunc_i64_i32(tmp32
, tmp2
);
2370 set_cc_nz_u32(s
, tmp32
);
2371 tcg_temp_free_i64(tmp2
);
2372 tcg_temp_free_i32(tmp32
);
2374 case 0x5: /* NIHL R1,I2 [RI] */
2375 case 0x9: /* OIHL R1,I2 [RI] */
2377 tmp32
= tcg_temp_new_i32();
2380 tmp2
= tcg_const_i64((((uint64_t)i2
) << 32)
2381 | 0xffff0000ffffffffULL
);
2382 tcg_gen_and_i64(tmp
, tmp
, tmp2
);
2385 tmp2
= tcg_const_i64(((uint64_t)i2
) << 32);
2386 tcg_gen_or_i64(tmp
, tmp
, tmp2
);
2392 tcg_gen_shri_i64(tmp2
, tmp
, 32);
2393 tcg_gen_trunc_i64_i32(tmp32
, tmp2
);
2394 tcg_gen_andi_i32(tmp32
, tmp32
, 0xffff);
2395 set_cc_nz_u32(s
, tmp32
);
2396 tcg_temp_free_i64(tmp2
);
2397 tcg_temp_free_i32(tmp32
);
2399 case 0x6: /* NILH R1,I2 [RI] */
2400 case 0xa: /* OILH R1,I2 [RI] */
2402 tmp32
= tcg_temp_new_i32();
2405 tmp2
= tcg_const_i64((((uint64_t)i2
) << 16)
2406 | 0xffffffff0000ffffULL
);
2407 tcg_gen_and_i64(tmp
, tmp
, tmp2
);
2410 tmp2
= tcg_const_i64(((uint64_t)i2
) << 16);
2411 tcg_gen_or_i64(tmp
, tmp
, tmp2
);
2417 tcg_gen_shri_i64(tmp
, tmp
, 16);
2418 tcg_gen_trunc_i64_i32(tmp32
, tmp
);
2419 tcg_gen_andi_i32(tmp32
, tmp32
, 0xffff);
2420 set_cc_nz_u32(s
, tmp32
);
2421 tcg_temp_free_i64(tmp2
);
2422 tcg_temp_free_i32(tmp32
);
2424 case 0x7: /* NILL R1,I2 [RI] */
2425 case 0xb: /* OILL R1,I2 [RI] */
2427 tmp32
= tcg_temp_new_i32();
2430 tmp2
= tcg_const_i64(i2
| 0xffffffffffff0000ULL
);
2431 tcg_gen_and_i64(tmp
, tmp
, tmp2
);
2434 tmp2
= tcg_const_i64(i2
);
2435 tcg_gen_or_i64(tmp
, tmp
, tmp2
);
2441 tcg_gen_trunc_i64_i32(tmp32
, tmp
);
2442 tcg_gen_andi_i32(tmp32
, tmp32
, 0xffff);
2443 set_cc_nz_u32(s
, tmp32
); /* signedness should not matter here */
2444 tcg_temp_free_i64(tmp2
);
2445 tcg_temp_free_i32(tmp32
);
2447 case 0xc: /* LLIHH R1,I2 [RI] */
2448 tmp
= tcg_const_i64( ((uint64_t)i2
) << 48 );
2451 case 0xd: /* LLIHL R1,I2 [RI] */
2452 tmp
= tcg_const_i64( ((uint64_t)i2
) << 32 );
2455 case 0xe: /* LLILH R1,I2 [RI] */
2456 tmp
= tcg_const_i64( ((uint64_t)i2
) << 16 );
2459 case 0xf: /* LLILL R1,I2 [RI] */
2460 tmp
= tcg_const_i64(i2
);
2464 LOG_DISAS("illegal a5 operation 0x%x\n", op
);
2465 gen_illegal_opcode(s
, 2);
2468 tcg_temp_free_i64(tmp
);
2471 static void disas_a7(DisasContext
*s
, int op
, int r1
, int i2
)
2474 TCGv_i32 tmp32_1
, tmp32_2
, tmp32_3
;
2477 LOG_DISAS("disas_a7: op 0x%x r1 %d i2 0x%x\n", op
, r1
, i2
);
2479 case 0x0: /* TMLH or TMH R1,I2 [RI] */
2480 case 0x1: /* TMLL or TML R1,I2 [RI] */
2481 case 0x2: /* TMHH R1,I2 [RI] */
2482 case 0x3: /* TMHL R1,I2 [RI] */
2484 tmp2
= tcg_const_i64((uint16_t)i2
);
2487 tcg_gen_shri_i64(tmp
, tmp
, 16);
2492 tcg_gen_shri_i64(tmp
, tmp
, 48);
2495 tcg_gen_shri_i64(tmp
, tmp
, 32);
2498 tcg_gen_andi_i64(tmp
, tmp
, 0xffff);
2499 cmp_64(s
, tmp
, tmp2
, CC_OP_TM_64
);
2500 tcg_temp_free_i64(tmp
);
2501 tcg_temp_free_i64(tmp2
);
2503 case 0x4: /* brc m1, i2 */
2504 gen_brc(r1
, s
, i2
* 2LL);
2506 case 0x5: /* BRAS R1,I2 [RI] */
2507 tmp
= tcg_const_i64(pc_to_link_info(s
, s
->pc
+ 4));
2509 tcg_temp_free_i64(tmp
);
2510 gen_goto_tb(s
, 0, s
->pc
+ i2
* 2LL);
2511 s
->is_jmp
= DISAS_TB_JUMP
;
2513 case 0x6: /* BRCT R1,I2 [RI] */
2514 tmp32_1
= load_reg32(r1
);
2515 tcg_gen_subi_i32(tmp32_1
, tmp32_1
, 1);
2516 store_reg32(r1
, tmp32_1
);
2517 gen_update_cc_op(s
);
2518 l1
= gen_new_label();
2519 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp32_1
, 0, l1
);
2520 gen_goto_tb(s
, 0, s
->pc
+ (i2
* 2LL));
2522 gen_goto_tb(s
, 1, s
->pc
+ 4);
2523 s
->is_jmp
= DISAS_TB_JUMP
;
2524 tcg_temp_free_i32(tmp32_1
);
2526 case 0x7: /* BRCTG R1,I2 [RI] */
2528 tcg_gen_subi_i64(tmp
, tmp
, 1);
2530 gen_update_cc_op(s
);
2531 l1
= gen_new_label();
2532 tcg_gen_brcondi_i64(TCG_COND_EQ
, tmp
, 0, l1
);
2533 gen_goto_tb(s
, 0, s
->pc
+ (i2
* 2LL));
2535 gen_goto_tb(s
, 1, s
->pc
+ 4);
2536 s
->is_jmp
= DISAS_TB_JUMP
;
2537 tcg_temp_free_i64(tmp
);
2539 case 0x8: /* lhi r1, i2 */
2540 tmp32_1
= tcg_const_i32(i2
);
2541 store_reg32(r1
, tmp32_1
);
2542 tcg_temp_free_i32(tmp32_1
);
2544 case 0x9: /* lghi r1, i2 */
2545 tmp
= tcg_const_i64(i2
);
2547 tcg_temp_free_i64(tmp
);
2549 case 0xa: /* AHI R1,I2 [RI] */
2550 tmp32_1
= load_reg32(r1
);
2551 tmp32_2
= tcg_temp_new_i32();
2552 tmp32_3
= tcg_const_i32(i2
);
2555 tcg_gen_subi_i32(tmp32_2
, tmp32_1
, -i2
);
2557 tcg_gen_add_i32(tmp32_2
, tmp32_1
, tmp32_3
);
2560 store_reg32(r1
, tmp32_2
);
2561 set_cc_add32(s
, tmp32_1
, tmp32_3
, tmp32_2
);
2562 tcg_temp_free_i32(tmp32_1
);
2563 tcg_temp_free_i32(tmp32_2
);
2564 tcg_temp_free_i32(tmp32_3
);
2566 case 0xb: /* aghi r1, i2 */
2568 tmp2
= tcg_const_i64(i2
);
2571 tcg_gen_subi_i64(regs
[r1
], tmp
, -i2
);
2573 tcg_gen_add_i64(regs
[r1
], tmp
, tmp2
);
2575 set_cc_add64(s
, tmp
, tmp2
, regs
[r1
]);
2576 tcg_temp_free_i64(tmp
);
2577 tcg_temp_free_i64(tmp2
);
2579 case 0xc: /* MHI R1,I2 [RI] */
2580 tmp32_1
= load_reg32(r1
);
2581 tcg_gen_muli_i32(tmp32_1
, tmp32_1
, i2
);
2582 store_reg32(r1
, tmp32_1
);
2583 tcg_temp_free_i32(tmp32_1
);
2585 case 0xd: /* MGHI R1,I2 [RI] */
2587 tcg_gen_muli_i64(tmp
, tmp
, i2
);
2589 tcg_temp_free_i64(tmp
);
2591 case 0xe: /* CHI R1,I2 [RI] */
2592 tmp32_1
= load_reg32(r1
);
2593 cmp_s32c(s
, tmp32_1
, i2
);
2594 tcg_temp_free_i32(tmp32_1
);
2596 case 0xf: /* CGHI R1,I2 [RI] */
2598 cmp_s64c(s
, tmp
, i2
);
2599 tcg_temp_free_i64(tmp
);
2602 LOG_DISAS("illegal a7 operation 0x%x\n", op
);
2603 gen_illegal_opcode(s
, 2);
2608 static void disas_b2(DisasContext
*s
, int op
, uint32_t insn
)
2610 TCGv_i64 tmp
, tmp2
, tmp3
;
2611 TCGv_i32 tmp32_1
, tmp32_2
, tmp32_3
;
2614 #ifndef CONFIG_USER_ONLY
2618 r1
= (insn
>> 4) & 0xf;
2621 LOG_DISAS("disas_b2: op 0x%x r1 %d r2 %d\n", op
, r1
, r2
);
2624 case 0x22: /* IPM R1 [RRE] */
2625 tmp32_1
= tcg_const_i32(r1
);
2627 gen_helper_ipm(cc_op
, tmp32_1
);
2628 tcg_temp_free_i32(tmp32_1
);
2630 case 0x41: /* CKSM R1,R2 [RRE] */
2631 tmp32_1
= tcg_const_i32(r1
);
2632 tmp32_2
= tcg_const_i32(r2
);
2633 potential_page_fault(s
);
2634 gen_helper_cksm(tmp32_1
, tmp32_2
);
2635 tcg_temp_free_i32(tmp32_1
);
2636 tcg_temp_free_i32(tmp32_2
);
2637 gen_op_movi_cc(s
, 0);
2639 case 0x4e: /* SAR R1,R2 [RRE] */
2640 tmp32_1
= load_reg32(r2
);
2641 tcg_gen_st_i32(tmp32_1
, cpu_env
, offsetof(CPUState
, aregs
[r1
]));
2642 tcg_temp_free_i32(tmp32_1
);
2644 case 0x4f: /* EAR R1,R2 [RRE] */
2645 tmp32_1
= tcg_temp_new_i32();
2646 tcg_gen_ld_i32(tmp32_1
, cpu_env
, offsetof(CPUState
, aregs
[r2
]));
2647 store_reg32(r1
, tmp32_1
);
2648 tcg_temp_free_i32(tmp32_1
);
2650 case 0x52: /* MSR R1,R2 [RRE] */
2651 tmp32_1
= load_reg32(r1
);
2652 tmp32_2
= load_reg32(r2
);
2653 tcg_gen_mul_i32(tmp32_1
, tmp32_1
, tmp32_2
);
2654 store_reg32(r1
, tmp32_1
);
2655 tcg_temp_free_i32(tmp32_1
);
2656 tcg_temp_free_i32(tmp32_2
);
2658 case 0x54: /* MVPG R1,R2 [RRE] */
2660 tmp2
= load_reg(r1
);
2661 tmp3
= load_reg(r2
);
2662 potential_page_fault(s
);
2663 gen_helper_mvpg(tmp
, tmp2
, tmp3
);
2664 tcg_temp_free_i64(tmp
);
2665 tcg_temp_free_i64(tmp2
);
2666 tcg_temp_free_i64(tmp3
);
2667 /* XXX check CCO bit and set CC accordingly */
2668 gen_op_movi_cc(s
, 0);
2670 case 0x55: /* MVST R1,R2 [RRE] */
2671 tmp32_1
= load_reg32(0);
2672 tmp32_2
= tcg_const_i32(r1
);
2673 tmp32_3
= tcg_const_i32(r2
);
2674 potential_page_fault(s
);
2675 gen_helper_mvst(tmp32_1
, tmp32_2
, tmp32_3
);
2676 tcg_temp_free_i32(tmp32_1
);
2677 tcg_temp_free_i32(tmp32_2
);
2678 tcg_temp_free_i32(tmp32_3
);
2679 gen_op_movi_cc(s
, 1);
2681 case 0x5d: /* CLST R1,R2 [RRE] */
2682 tmp32_1
= load_reg32(0);
2683 tmp32_2
= tcg_const_i32(r1
);
2684 tmp32_3
= tcg_const_i32(r2
);
2685 potential_page_fault(s
);
2686 gen_helper_clst(cc_op
, tmp32_1
, tmp32_2
, tmp32_3
);
2688 tcg_temp_free_i32(tmp32_1
);
2689 tcg_temp_free_i32(tmp32_2
);
2690 tcg_temp_free_i32(tmp32_3
);
2692 case 0x5e: /* SRST R1,R2 [RRE] */
2693 tmp32_1
= load_reg32(0);
2694 tmp32_2
= tcg_const_i32(r1
);
2695 tmp32_3
= tcg_const_i32(r2
);
2696 potential_page_fault(s
);
2697 gen_helper_srst(cc_op
, tmp32_1
, tmp32_2
, tmp32_3
);
2699 tcg_temp_free_i32(tmp32_1
);
2700 tcg_temp_free_i32(tmp32_2
);
2701 tcg_temp_free_i32(tmp32_3
);
2704 #ifndef CONFIG_USER_ONLY
2705 case 0x02: /* STIDP D2(B2) [S] */
2707 check_privileged(s
, ilc
);
2708 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2709 tmp
= get_address(s
, 0, b2
, d2
);
2710 potential_page_fault(s
);
2711 gen_helper_stidp(tmp
);
2712 tcg_temp_free_i64(tmp
);
2714 case 0x04: /* SCK D2(B2) [S] */
2716 check_privileged(s
, ilc
);
2717 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2718 tmp
= get_address(s
, 0, b2
, d2
);
2719 potential_page_fault(s
);
2720 gen_helper_sck(cc_op
, tmp
);
2722 tcg_temp_free_i64(tmp
);
2724 case 0x05: /* STCK D2(B2) [S] */
2726 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2727 tmp
= get_address(s
, 0, b2
, d2
);
2728 potential_page_fault(s
);
2729 gen_helper_stck(cc_op
, tmp
);
2731 tcg_temp_free_i64(tmp
);
2733 case 0x06: /* SCKC D2(B2) [S] */
2734 /* Set Clock Comparator */
2735 check_privileged(s
, ilc
);
2736 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2737 tmp
= get_address(s
, 0, b2
, d2
);
2738 potential_page_fault(s
);
2739 gen_helper_sckc(tmp
);
2740 tcg_temp_free_i64(tmp
);
2742 case 0x07: /* STCKC D2(B2) [S] */
2743 /* Store Clock Comparator */
2744 check_privileged(s
, ilc
);
2745 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2746 tmp
= get_address(s
, 0, b2
, d2
);
2747 potential_page_fault(s
);
2748 gen_helper_stckc(tmp
);
2749 tcg_temp_free_i64(tmp
);
2751 case 0x08: /* SPT D2(B2) [S] */
2753 check_privileged(s
, ilc
);
2754 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2755 tmp
= get_address(s
, 0, b2
, d2
);
2756 potential_page_fault(s
);
2757 gen_helper_spt(tmp
);
2758 tcg_temp_free_i64(tmp
);
2760 case 0x09: /* STPT D2(B2) [S] */
2761 /* Store CPU Timer */
2762 check_privileged(s
, ilc
);
2763 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2764 tmp
= get_address(s
, 0, b2
, d2
);
2765 potential_page_fault(s
);
2766 gen_helper_stpt(tmp
);
2767 tcg_temp_free_i64(tmp
);
2769 case 0x0a: /* SPKA D2(B2) [S] */
2770 /* Set PSW Key from Address */
2771 check_privileged(s
, ilc
);
2772 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2773 tmp
= get_address(s
, 0, b2
, d2
);
2774 tmp2
= tcg_temp_new_i64();
2775 tcg_gen_andi_i64(tmp2
, psw_mask
, ~PSW_MASK_KEY
);
2776 tcg_gen_shli_i64(tmp
, tmp
, PSW_SHIFT_KEY
- 4);
2777 tcg_gen_or_i64(psw_mask
, tmp2
, tmp
);
2778 tcg_temp_free_i64(tmp2
);
2779 tcg_temp_free_i64(tmp
);
2781 case 0x0d: /* PTLB [S] */
2783 check_privileged(s
, ilc
);
2786 case 0x10: /* SPX D2(B2) [S] */
2787 /* Set Prefix Register */
2788 check_privileged(s
, ilc
);
2789 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2790 tmp
= get_address(s
, 0, b2
, d2
);
2791 potential_page_fault(s
);
2792 gen_helper_spx(tmp
);
2793 tcg_temp_free_i64(tmp
);
2795 case 0x11: /* STPX D2(B2) [S] */
2797 check_privileged(s
, ilc
);
2798 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2799 tmp
= get_address(s
, 0, b2
, d2
);
2800 tmp2
= tcg_temp_new_i64();
2801 tcg_gen_ld_i64(tmp2
, cpu_env
, offsetof(CPUState
, psa
));
2802 tcg_gen_qemu_st32(tmp2
, tmp
, get_mem_index(s
));
2803 tcg_temp_free_i64(tmp
);
2804 tcg_temp_free_i64(tmp2
);
2806 case 0x12: /* STAP D2(B2) [S] */
2807 /* Store CPU Address */
2808 check_privileged(s
, ilc
);
2809 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2810 tmp
= get_address(s
, 0, b2
, d2
);
2811 tmp2
= tcg_temp_new_i64();
2812 tmp32_1
= tcg_temp_new_i32();
2813 tcg_gen_ld_i32(tmp32_1
, cpu_env
, offsetof(CPUState
, cpu_num
));
2814 tcg_gen_extu_i32_i64(tmp2
, tmp32_1
);
2815 tcg_gen_qemu_st32(tmp2
, tmp
, get_mem_index(s
));
2816 tcg_temp_free_i64(tmp
);
2817 tcg_temp_free_i64(tmp2
);
2818 tcg_temp_free_i32(tmp32_1
);
2820 case 0x21: /* IPTE R1,R2 [RRE] */
2821 /* Invalidate PTE */
2822 check_privileged(s
, ilc
);
2823 r1
= (insn
>> 4) & 0xf;
2826 tmp2
= load_reg(r2
);
2827 gen_helper_ipte(tmp
, tmp2
);
2828 tcg_temp_free_i64(tmp
);
2829 tcg_temp_free_i64(tmp2
);
2831 case 0x29: /* ISKE R1,R2 [RRE] */
2832 /* Insert Storage Key Extended */
2833 check_privileged(s
, ilc
);
2834 r1
= (insn
>> 4) & 0xf;
2837 tmp2
= tcg_temp_new_i64();
2838 gen_helper_iske(tmp2
, tmp
);
2839 store_reg(r1
, tmp2
);
2840 tcg_temp_free_i64(tmp
);
2841 tcg_temp_free_i64(tmp2
);
2843 case 0x2a: /* RRBE R1,R2 [RRE] */
2844 /* Set Storage Key Extended */
2845 check_privileged(s
, ilc
);
2846 r1
= (insn
>> 4) & 0xf;
2848 tmp32_1
= load_reg32(r1
);
2850 gen_helper_rrbe(cc_op
, tmp32_1
, tmp
);
2852 tcg_temp_free_i32(tmp32_1
);
2853 tcg_temp_free_i64(tmp
);
2855 case 0x2b: /* SSKE R1,R2 [RRE] */
2856 /* Set Storage Key Extended */
2857 check_privileged(s
, ilc
);
2858 r1
= (insn
>> 4) & 0xf;
2860 tmp32_1
= load_reg32(r1
);
2862 gen_helper_sske(tmp32_1
, tmp
);
2863 tcg_temp_free_i32(tmp32_1
);
2864 tcg_temp_free_i64(tmp
);
2866 case 0x34: /* STCH ? */
2867 /* Store Subchannel */
2868 check_privileged(s
, ilc
);
2869 gen_op_movi_cc(s
, 3);
2871 case 0x46: /* STURA R1,R2 [RRE] */
2872 /* Store Using Real Address */
2873 check_privileged(s
, ilc
);
2874 r1
= (insn
>> 4) & 0xf;
2876 tmp32_1
= load_reg32(r1
);
2878 potential_page_fault(s
);
2879 gen_helper_stura(tmp
, tmp32_1
);
2880 tcg_temp_free_i32(tmp32_1
);
2881 tcg_temp_free_i64(tmp
);
2883 case 0x50: /* CSP R1,R2 [RRE] */
2884 /* Compare And Swap And Purge */
2885 check_privileged(s
, ilc
);
2886 r1
= (insn
>> 4) & 0xf;
2888 tmp32_1
= tcg_const_i32(r1
);
2889 tmp32_2
= tcg_const_i32(r2
);
2890 gen_helper_csp(cc_op
, tmp32_1
, tmp32_2
);
2892 tcg_temp_free_i32(tmp32_1
);
2893 tcg_temp_free_i32(tmp32_2
);
2895 case 0x5f: /* CHSC ? */
2896 /* Channel Subsystem Call */
2897 check_privileged(s
, ilc
);
2898 gen_op_movi_cc(s
, 3);
2900 case 0x78: /* STCKE D2(B2) [S] */
2901 /* Store Clock Extended */
2902 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2903 tmp
= get_address(s
, 0, b2
, d2
);
2904 potential_page_fault(s
);
2905 gen_helper_stcke(cc_op
, tmp
);
2907 tcg_temp_free_i64(tmp
);
2909 case 0x79: /* SACF D2(B2) [S] */
2910 /* Store Clock Extended */
2911 check_privileged(s
, ilc
);
2912 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2913 tmp
= get_address(s
, 0, b2
, d2
);
2914 potential_page_fault(s
);
2915 gen_helper_sacf(tmp
);
2916 tcg_temp_free_i64(tmp
);
2917 /* addressing mode has changed, so end the block */
2920 s
->is_jmp
= DISAS_EXCP
;
2922 case 0x7d: /* STSI D2,(B2) [S] */
2923 check_privileged(s
, ilc
);
2924 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2925 tmp
= get_address(s
, 0, b2
, d2
);
2926 tmp32_1
= load_reg32(0);
2927 tmp32_2
= load_reg32(1);
2928 potential_page_fault(s
);
2929 gen_helper_stsi(cc_op
, tmp
, tmp32_1
, tmp32_2
);
2931 tcg_temp_free_i64(tmp
);
2932 tcg_temp_free_i32(tmp32_1
);
2933 tcg_temp_free_i32(tmp32_2
);
2935 case 0x9d: /* LFPC D2(B2) [S] */
2936 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2937 tmp
= get_address(s
, 0, b2
, d2
);
2938 tmp2
= tcg_temp_new_i64();
2939 tmp32_1
= tcg_temp_new_i32();
2940 tcg_gen_qemu_ld32u(tmp2
, tmp
, get_mem_index(s
));
2941 tcg_gen_trunc_i64_i32(tmp32_1
, tmp2
);
2942 tcg_gen_st_i32(tmp32_1
, cpu_env
, offsetof(CPUState
, fpc
));
2943 tcg_temp_free_i64(tmp
);
2944 tcg_temp_free_i64(tmp2
);
2945 tcg_temp_free_i32(tmp32_1
);
2947 case 0xb1: /* STFL D2(B2) [S] */
2948 /* Store Facility List (CPU features) at 200 */
2949 check_privileged(s
, ilc
);
2950 tmp2
= tcg_const_i64(0xc0000000);
2951 tmp
= tcg_const_i64(200);
2952 tcg_gen_qemu_st32(tmp2
, tmp
, get_mem_index(s
));
2953 tcg_temp_free_i64(tmp2
);
2954 tcg_temp_free_i64(tmp
);
2956 case 0xb2: /* LPSWE D2(B2) [S] */
2957 /* Load PSW Extended */
2958 check_privileged(s
, ilc
);
2959 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2960 tmp
= get_address(s
, 0, b2
, d2
);
2961 tmp2
= tcg_temp_new_i64();
2962 tmp3
= tcg_temp_new_i64();
2963 tcg_gen_qemu_ld64(tmp2
, tmp
, get_mem_index(s
));
2964 tcg_gen_addi_i64(tmp
, tmp
, 8);
2965 tcg_gen_qemu_ld64(tmp3
, tmp
, get_mem_index(s
));
2966 gen_helper_load_psw(tmp2
, tmp3
);
2967 /* we need to keep cc_op intact */
2968 s
->is_jmp
= DISAS_JUMP
;
2969 tcg_temp_free_i64(tmp
);
2970 tcg_temp_free_i64(tmp2
);
2971 tcg_temp_free_i64(tmp3
);
2973 case 0x20: /* SERVC R1,R2 [RRE] */
2974 /* SCLP Service call (PV hypercall) */
2975 check_privileged(s
, ilc
);
2976 potential_page_fault(s
);
2977 tmp32_1
= load_reg32(r2
);
2979 gen_helper_servc(cc_op
, tmp32_1
, tmp
);
2981 tcg_temp_free_i32(tmp32_1
);
2982 tcg_temp_free_i64(tmp
);
2986 LOG_DISAS("illegal b2 operation 0x%x\n", op
);
2987 gen_illegal_opcode(s
, ilc
);
2992 static void disas_b3(DisasContext
*s
, int op
, int m3
, int r1
, int r2
)
2995 TCGv_i32 tmp32_1
, tmp32_2
, tmp32_3
;
2996 LOG_DISAS("disas_b3: op 0x%x m3 0x%x r1 %d r2 %d\n", op
, m3
, r1
, r2
);
2997 #define FP_HELPER(i) \
2998 tmp32_1 = tcg_const_i32(r1); \
2999 tmp32_2 = tcg_const_i32(r2); \
3000 gen_helper_ ## i (tmp32_1, tmp32_2); \
3001 tcg_temp_free_i32(tmp32_1); \
3002 tcg_temp_free_i32(tmp32_2);
3004 #define FP_HELPER_CC(i) \
3005 tmp32_1 = tcg_const_i32(r1); \
3006 tmp32_2 = tcg_const_i32(r2); \
3007 gen_helper_ ## i (cc_op, tmp32_1, tmp32_2); \
3009 tcg_temp_free_i32(tmp32_1); \
3010 tcg_temp_free_i32(tmp32_2);
3013 case 0x0: /* LPEBR R1,R2 [RRE] */
3014 FP_HELPER_CC(lpebr
);
3016 case 0x2: /* LTEBR R1,R2 [RRE] */
3017 FP_HELPER_CC(ltebr
);
3019 case 0x3: /* LCEBR R1,R2 [RRE] */
3020 FP_HELPER_CC(lcebr
);
3022 case 0x4: /* LDEBR R1,R2 [RRE] */
3025 case 0x5: /* LXDBR R1,R2 [RRE] */
3028 case 0x9: /* CEBR R1,R2 [RRE] */
3031 case 0xa: /* AEBR R1,R2 [RRE] */
3034 case 0xb: /* SEBR R1,R2 [RRE] */
3037 case 0xd: /* DEBR R1,R2 [RRE] */
3040 case 0x10: /* LPDBR R1,R2 [RRE] */
3041 FP_HELPER_CC(lpdbr
);
3043 case 0x12: /* LTDBR R1,R2 [RRE] */
3044 FP_HELPER_CC(ltdbr
);
3046 case 0x13: /* LCDBR R1,R2 [RRE] */
3047 FP_HELPER_CC(lcdbr
);
3049 case 0x15: /* SQBDR R1,R2 [RRE] */
3052 case 0x17: /* MEEBR R1,R2 [RRE] */
3055 case 0x19: /* CDBR R1,R2 [RRE] */
3058 case 0x1a: /* ADBR R1,R2 [RRE] */
3061 case 0x1b: /* SDBR R1,R2 [RRE] */
3064 case 0x1c: /* MDBR R1,R2 [RRE] */
3067 case 0x1d: /* DDBR R1,R2 [RRE] */
3070 case 0xe: /* MAEBR R1,R3,R2 [RRF] */
3071 case 0x1e: /* MADBR R1,R3,R2 [RRF] */
3072 case 0x1f: /* MSDBR R1,R3,R2 [RRF] */
3073 /* for RRF insns, m3 is R1, r1 is R3, and r2 is R2 */
3074 tmp32_1
= tcg_const_i32(m3
);
3075 tmp32_2
= tcg_const_i32(r2
);
3076 tmp32_3
= tcg_const_i32(r1
);
3079 gen_helper_maebr(tmp32_1
, tmp32_3
, tmp32_2
);
3082 gen_helper_madbr(tmp32_1
, tmp32_3
, tmp32_2
);
3085 gen_helper_msdbr(tmp32_1
, tmp32_3
, tmp32_2
);
3090 tcg_temp_free_i32(tmp32_1
);
3091 tcg_temp_free_i32(tmp32_2
);
3092 tcg_temp_free_i32(tmp32_3
);
3094 case 0x40: /* LPXBR R1,R2 [RRE] */
3095 FP_HELPER_CC(lpxbr
);
3097 case 0x42: /* LTXBR R1,R2 [RRE] */
3098 FP_HELPER_CC(ltxbr
);
3100 case 0x43: /* LCXBR R1,R2 [RRE] */
3101 FP_HELPER_CC(lcxbr
);
3103 case 0x44: /* LEDBR R1,R2 [RRE] */
3106 case 0x45: /* LDXBR R1,R2 [RRE] */
3109 case 0x46: /* LEXBR R1,R2 [RRE] */
3112 case 0x49: /* CXBR R1,R2 [RRE] */
3115 case 0x4a: /* AXBR R1,R2 [RRE] */
3118 case 0x4b: /* SXBR R1,R2 [RRE] */
3121 case 0x4c: /* MXBR R1,R2 [RRE] */
3124 case 0x4d: /* DXBR R1,R2 [RRE] */
3127 case 0x65: /* LXR R1,R2 [RRE] */
3128 tmp
= load_freg(r2
);
3129 store_freg(r1
, tmp
);
3130 tcg_temp_free_i64(tmp
);
3131 tmp
= load_freg(r2
+ 2);
3132 store_freg(r1
+ 2, tmp
);
3133 tcg_temp_free_i64(tmp
);
3135 case 0x74: /* LZER R1 [RRE] */
3136 tmp32_1
= tcg_const_i32(r1
);
3137 gen_helper_lzer(tmp32_1
);
3138 tcg_temp_free_i32(tmp32_1
);
3140 case 0x75: /* LZDR R1 [RRE] */
3141 tmp32_1
= tcg_const_i32(r1
);
3142 gen_helper_lzdr(tmp32_1
);
3143 tcg_temp_free_i32(tmp32_1
);
3145 case 0x76: /* LZXR R1 [RRE] */
3146 tmp32_1
= tcg_const_i32(r1
);
3147 gen_helper_lzxr(tmp32_1
);
3148 tcg_temp_free_i32(tmp32_1
);
3150 case 0x84: /* SFPC R1 [RRE] */
3151 tmp32_1
= load_reg32(r1
);
3152 tcg_gen_st_i32(tmp32_1
, cpu_env
, offsetof(CPUState
, fpc
));
3153 tcg_temp_free_i32(tmp32_1
);
3155 case 0x8c: /* EFPC R1 [RRE] */
3156 tmp32_1
= tcg_temp_new_i32();
3157 tcg_gen_ld_i32(tmp32_1
, cpu_env
, offsetof(CPUState
, fpc
));
3158 store_reg32(r1
, tmp32_1
);
3159 tcg_temp_free_i32(tmp32_1
);
3161 case 0x94: /* CEFBR R1,R2 [RRE] */
3162 case 0x95: /* CDFBR R1,R2 [RRE] */
3163 case 0x96: /* CXFBR R1,R2 [RRE] */
3164 tmp32_1
= tcg_const_i32(r1
);
3165 tmp32_2
= load_reg32(r2
);
3168 gen_helper_cefbr(tmp32_1
, tmp32_2
);
3171 gen_helper_cdfbr(tmp32_1
, tmp32_2
);
3174 gen_helper_cxfbr(tmp32_1
, tmp32_2
);
3179 tcg_temp_free_i32(tmp32_1
);
3180 tcg_temp_free_i32(tmp32_2
);
3182 case 0x98: /* CFEBR R1,R2 [RRE] */
3183 case 0x99: /* CFDBR R1,R2 [RRE] */
3184 case 0x9a: /* CFXBR R1,R2 [RRE] */
3185 tmp32_1
= tcg_const_i32(r1
);
3186 tmp32_2
= tcg_const_i32(r2
);
3187 tmp32_3
= tcg_const_i32(m3
);
3190 gen_helper_cfebr(cc_op
, tmp32_1
, tmp32_2
, tmp32_3
);
3193 gen_helper_cfdbr(cc_op
, tmp32_1
, tmp32_2
, tmp32_3
);
3196 gen_helper_cfxbr(cc_op
, tmp32_1
, tmp32_2
, tmp32_3
);
3202 tcg_temp_free_i32(tmp32_1
);
3203 tcg_temp_free_i32(tmp32_2
);
3204 tcg_temp_free_i32(tmp32_3
);
3206 case 0xa4: /* CEGBR R1,R2 [RRE] */
3207 case 0xa5: /* CDGBR R1,R2 [RRE] */
3208 tmp32_1
= tcg_const_i32(r1
);
3212 gen_helper_cegbr(tmp32_1
, tmp
);
3215 gen_helper_cdgbr(tmp32_1
, tmp
);
3220 tcg_temp_free_i32(tmp32_1
);
3221 tcg_temp_free_i64(tmp
);
3223 case 0xa6: /* CXGBR R1,R2 [RRE] */
3224 tmp32_1
= tcg_const_i32(r1
);
3226 gen_helper_cxgbr(tmp32_1
, tmp
);
3227 tcg_temp_free_i32(tmp32_1
);
3228 tcg_temp_free_i64(tmp
);
3230 case 0xa8: /* CGEBR R1,R2 [RRE] */
3231 tmp32_1
= tcg_const_i32(r1
);
3232 tmp32_2
= tcg_const_i32(r2
);
3233 tmp32_3
= tcg_const_i32(m3
);
3234 gen_helper_cgebr(cc_op
, tmp32_1
, tmp32_2
, tmp32_3
);
3236 tcg_temp_free_i32(tmp32_1
);
3237 tcg_temp_free_i32(tmp32_2
);
3238 tcg_temp_free_i32(tmp32_3
);
3240 case 0xa9: /* CGDBR R1,R2 [RRE] */
3241 tmp32_1
= tcg_const_i32(r1
);
3242 tmp32_2
= tcg_const_i32(r2
);
3243 tmp32_3
= tcg_const_i32(m3
);
3244 gen_helper_cgdbr(cc_op
, tmp32_1
, tmp32_2
, tmp32_3
);
3246 tcg_temp_free_i32(tmp32_1
);
3247 tcg_temp_free_i32(tmp32_2
);
3248 tcg_temp_free_i32(tmp32_3
);
3250 case 0xaa: /* CGXBR R1,R2 [RRE] */
3251 tmp32_1
= tcg_const_i32(r1
);
3252 tmp32_2
= tcg_const_i32(r2
);
3253 tmp32_3
= tcg_const_i32(m3
);
3254 gen_helper_cgxbr(cc_op
, tmp32_1
, tmp32_2
, tmp32_3
);
3256 tcg_temp_free_i32(tmp32_1
);
3257 tcg_temp_free_i32(tmp32_2
);
3258 tcg_temp_free_i32(tmp32_3
);
3261 LOG_DISAS("illegal b3 operation 0x%x\n", op
);
3262 gen_illegal_opcode(s
, 2);
3270 static void disas_b9(DisasContext
*s
, int op
, int r1
, int r2
)
3272 TCGv_i64 tmp
, tmp2
, tmp3
;
3273 TCGv_i32 tmp32_1
, tmp32_2
, tmp32_3
;
3275 LOG_DISAS("disas_b9: op 0x%x r1 %d r2 %d\n", op
, r1
, r2
);
3277 case 0x0: /* LPGR R1,R2 [RRE] */
3278 case 0x1: /* LNGR R1,R2 [RRE] */
3279 case 0x2: /* LTGR R1,R2 [RRE] */
3280 case 0x3: /* LCGR R1,R2 [RRE] */
3281 case 0x10: /* LPGFR R1,R2 [RRE] */
3282 case 0x11: /* LNFGR R1,R2 [RRE] */
3283 case 0x12: /* LTGFR R1,R2 [RRE] */
3284 case 0x13: /* LCGFR R1,R2 [RRE] */
3286 tmp
= load_reg32_i64(r2
);
3291 case 0x0: /* LP?GR */
3292 set_cc_abs64(s
, tmp
);
3293 gen_helper_abs_i64(tmp
, tmp
);
3296 case 0x1: /* LN?GR */
3297 set_cc_nabs64(s
, tmp
);
3298 gen_helper_nabs_i64(tmp
, tmp
);
3301 case 0x2: /* LT?GR */
3307 case 0x3: /* LC?GR */
3308 tcg_gen_neg_i64(regs
[r1
], tmp
);
3309 set_cc_comp64(s
, regs
[r1
]);
3312 tcg_temp_free_i64(tmp
);
3314 case 0x4: /* LGR R1,R2 [RRE] */
3315 store_reg(r1
, regs
[r2
]);
3317 case 0x6: /* LGBR R1,R2 [RRE] */
3318 tmp2
= load_reg(r2
);
3319 tcg_gen_ext8s_i64(tmp2
, tmp2
);
3320 store_reg(r1
, tmp2
);
3321 tcg_temp_free_i64(tmp2
);
3323 case 0x8: /* AGR R1,R2 [RRE] */
3324 case 0xa: /* ALGR R1,R2 [RRE] */
3326 tmp2
= load_reg(r2
);
3327 tmp3
= tcg_temp_new_i64();
3328 tcg_gen_add_i64(tmp3
, tmp
, tmp2
);
3329 store_reg(r1
, tmp3
);
3332 set_cc_add64(s
, tmp
, tmp2
, tmp3
);
3335 set_cc_addu64(s
, tmp
, tmp2
, tmp3
);
3340 tcg_temp_free_i64(tmp
);
3341 tcg_temp_free_i64(tmp2
);
3342 tcg_temp_free_i64(tmp3
);
3344 case 0x9: /* SGR R1,R2 [RRE] */
3345 case 0xb: /* SLGR R1,R2 [RRE] */
3346 case 0x1b: /* SLGFR R1,R2 [RRE] */
3347 case 0x19: /* SGFR R1,R2 [RRE] */
3351 tmp32_1
= load_reg32(r2
);
3352 tmp2
= tcg_temp_new_i64();
3353 tcg_gen_extu_i32_i64(tmp2
, tmp32_1
);
3354 tcg_temp_free_i32(tmp32_1
);
3357 tmp32_1
= load_reg32(r2
);
3358 tmp2
= tcg_temp_new_i64();
3359 tcg_gen_ext_i32_i64(tmp2
, tmp32_1
);
3360 tcg_temp_free_i32(tmp32_1
);
3363 tmp2
= load_reg(r2
);
3366 tmp3
= tcg_temp_new_i64();
3367 tcg_gen_sub_i64(tmp3
, tmp
, tmp2
);
3368 store_reg(r1
, tmp3
);
3372 set_cc_sub64(s
, tmp
, tmp2
, tmp3
);
3376 set_cc_subu64(s
, tmp
, tmp2
, tmp3
);
3381 tcg_temp_free_i64(tmp
);
3382 tcg_temp_free_i64(tmp2
);
3383 tcg_temp_free_i64(tmp3
);
3385 case 0xc: /* MSGR R1,R2 [RRE] */
3386 case 0x1c: /* MSGFR R1,R2 [RRE] */
3388 tmp2
= load_reg(r2
);
3390 tcg_gen_ext32s_i64(tmp2
, tmp2
);
3392 tcg_gen_mul_i64(tmp
, tmp
, tmp2
);
3394 tcg_temp_free_i64(tmp
);
3395 tcg_temp_free_i64(tmp2
);
3397 case 0xd: /* DSGR R1,R2 [RRE] */
3398 case 0x1d: /* DSGFR R1,R2 [RRE] */
3399 tmp
= load_reg(r1
+ 1);
3401 tmp2
= load_reg(r2
);
3403 tmp32_1
= load_reg32(r2
);
3404 tmp2
= tcg_temp_new_i64();
3405 tcg_gen_ext_i32_i64(tmp2
, tmp32_1
);
3406 tcg_temp_free_i32(tmp32_1
);
3408 tmp3
= tcg_temp_new_i64();
3409 tcg_gen_div_i64(tmp3
, tmp
, tmp2
);
3410 store_reg(r1
+ 1, tmp3
);
3411 tcg_gen_rem_i64(tmp3
, tmp
, tmp2
);
3412 store_reg(r1
, tmp3
);
3413 tcg_temp_free_i64(tmp
);
3414 tcg_temp_free_i64(tmp2
);
3415 tcg_temp_free_i64(tmp3
);
3417 case 0x14: /* LGFR R1,R2 [RRE] */
3418 tmp32_1
= load_reg32(r2
);
3419 tmp
= tcg_temp_new_i64();
3420 tcg_gen_ext_i32_i64(tmp
, tmp32_1
);
3422 tcg_temp_free_i32(tmp32_1
);
3423 tcg_temp_free_i64(tmp
);
3425 case 0x16: /* LLGFR R1,R2 [RRE] */
3426 tmp32_1
= load_reg32(r2
);
3427 tmp
= tcg_temp_new_i64();
3428 tcg_gen_extu_i32_i64(tmp
, tmp32_1
);
3430 tcg_temp_free_i32(tmp32_1
);
3431 tcg_temp_free_i64(tmp
);
3433 case 0x17: /* LLGTR R1,R2 [RRE] */
3434 tmp32_1
= load_reg32(r2
);
3435 tmp
= tcg_temp_new_i64();
3436 tcg_gen_andi_i32(tmp32_1
, tmp32_1
, 0x7fffffffUL
);
3437 tcg_gen_extu_i32_i64(tmp
, tmp32_1
);
3439 tcg_temp_free_i32(tmp32_1
);
3440 tcg_temp_free_i64(tmp
);
3442 case 0x18: /* AGFR R1,R2 [RRE] */
3443 case 0x1a: /* ALGFR R1,R2 [RRE] */
3444 tmp32_1
= load_reg32(r2
);
3445 tmp2
= tcg_temp_new_i64();
3447 tcg_gen_ext_i32_i64(tmp2
, tmp32_1
);
3449 tcg_gen_extu_i32_i64(tmp2
, tmp32_1
);
3451 tcg_temp_free_i32(tmp32_1
);
3453 tmp3
= tcg_temp_new_i64();
3454 tcg_gen_add_i64(tmp3
, tmp
, tmp2
);
3455 store_reg(r1
, tmp3
);
3457 set_cc_add64(s
, tmp
, tmp2
, tmp3
);
3459 set_cc_addu64(s
, tmp
, tmp2
, tmp3
);
3461 tcg_temp_free_i64(tmp
);
3462 tcg_temp_free_i64(tmp2
);
3463 tcg_temp_free_i64(tmp3
);
3465 case 0x1f: /* LRVR R1,R2 [RRE] */
3466 tmp32_1
= load_reg32(r2
);
3467 tcg_gen_bswap32_i32(tmp32_1
, tmp32_1
);
3468 store_reg32(r1
, tmp32_1
);
3469 tcg_temp_free_i32(tmp32_1
);
3471 case 0x20: /* CGR R1,R2 [RRE] */
3472 case 0x30: /* CGFR R1,R2 [RRE] */
3473 tmp2
= load_reg(r2
);
3475 tcg_gen_ext32s_i64(tmp2
, tmp2
);
3478 cmp_s64(s
, tmp
, tmp2
);
3479 tcg_temp_free_i64(tmp
);
3480 tcg_temp_free_i64(tmp2
);
3482 case 0x21: /* CLGR R1,R2 [RRE] */
3483 case 0x31: /* CLGFR R1,R2 [RRE] */
3484 tmp2
= load_reg(r2
);
3486 tcg_gen_ext32u_i64(tmp2
, tmp2
);
3489 cmp_u64(s
, tmp
, tmp2
);
3490 tcg_temp_free_i64(tmp
);
3491 tcg_temp_free_i64(tmp2
);
3493 case 0x26: /* LBR R1,R2 [RRE] */
3494 tmp32_1
= load_reg32(r2
);
3495 tcg_gen_ext8s_i32(tmp32_1
, tmp32_1
);
3496 store_reg32(r1
, tmp32_1
);
3497 tcg_temp_free_i32(tmp32_1
);
3499 case 0x27: /* LHR R1,R2 [RRE] */
3500 tmp32_1
= load_reg32(r2
);
3501 tcg_gen_ext16s_i32(tmp32_1
, tmp32_1
);
3502 store_reg32(r1
, tmp32_1
);
3503 tcg_temp_free_i32(tmp32_1
);
3505 case 0x80: /* NGR R1,R2 [RRE] */
3506 case 0x81: /* OGR R1,R2 [RRE] */
3507 case 0x82: /* XGR R1,R2 [RRE] */
3509 tmp2
= load_reg(r2
);
3512 tcg_gen_and_i64(tmp
, tmp
, tmp2
);
3515 tcg_gen_or_i64(tmp
, tmp
, tmp2
);
3518 tcg_gen_xor_i64(tmp
, tmp
, tmp2
);
3524 set_cc_nz_u64(s
, tmp
);
3525 tcg_temp_free_i64(tmp
);
3526 tcg_temp_free_i64(tmp2
);
3528 case 0x83: /* FLOGR R1,R2 [RRE] */
3530 tmp32_1
= tcg_const_i32(r1
);
3531 gen_helper_flogr(cc_op
, tmp32_1
, tmp
);
3533 tcg_temp_free_i64(tmp
);
3534 tcg_temp_free_i32(tmp32_1
);
3536 case 0x84: /* LLGCR R1,R2 [RRE] */
3538 tcg_gen_andi_i64(tmp
, tmp
, 0xff);
3540 tcg_temp_free_i64(tmp
);
3542 case 0x85: /* LLGHR R1,R2 [RRE] */
3544 tcg_gen_andi_i64(tmp
, tmp
, 0xffff);
3546 tcg_temp_free_i64(tmp
);
3548 case 0x87: /* DLGR R1,R2 [RRE] */
3549 tmp32_1
= tcg_const_i32(r1
);
3551 gen_helper_dlg(tmp32_1
, tmp
);
3552 tcg_temp_free_i64(tmp
);
3553 tcg_temp_free_i32(tmp32_1
);
3555 case 0x88: /* ALCGR R1,R2 [RRE] */
3557 tmp2
= load_reg(r2
);
3558 tmp3
= tcg_temp_new_i64();
3560 tcg_gen_extu_i32_i64(tmp3
, cc_op
);
3561 tcg_gen_shri_i64(tmp3
, tmp3
, 1);
3562 tcg_gen_andi_i64(tmp3
, tmp3
, 1);
3563 tcg_gen_add_i64(tmp3
, tmp2
, tmp3
);
3564 tcg_gen_add_i64(tmp3
, tmp
, tmp3
);
3565 store_reg(r1
, tmp3
);
3566 set_cc_addu64(s
, tmp
, tmp2
, tmp3
);
3567 tcg_temp_free_i64(tmp
);
3568 tcg_temp_free_i64(tmp2
);
3569 tcg_temp_free_i64(tmp3
);
3571 case 0x89: /* SLBGR R1,R2 [RRE] */
3573 tmp2
= load_reg(r2
);
3574 tmp32_1
= tcg_const_i32(r1
);
3576 gen_helper_slbg(cc_op
, cc_op
, tmp32_1
, tmp
, tmp2
);
3578 tcg_temp_free_i64(tmp
);
3579 tcg_temp_free_i64(tmp2
);
3580 tcg_temp_free_i32(tmp32_1
);
3582 case 0x94: /* LLCR R1,R2 [RRE] */
3583 tmp32_1
= load_reg32(r2
);
3584 tcg_gen_andi_i32(tmp32_1
, tmp32_1
, 0xff);
3585 store_reg32(r1
, tmp32_1
);
3586 tcg_temp_free_i32(tmp32_1
);
3588 case 0x95: /* LLHR R1,R2 [RRE] */
3589 tmp32_1
= load_reg32(r2
);
3590 tcg_gen_andi_i32(tmp32_1
, tmp32_1
, 0xffff);
3591 store_reg32(r1
, tmp32_1
);
3592 tcg_temp_free_i32(tmp32_1
);
3594 case 0x96: /* MLR R1,R2 [RRE] */
3595 /* reg(r1, r1+1) = reg(r1+1) * reg(r2) */
3596 tmp2
= load_reg(r2
);
3597 tmp3
= load_reg((r1
+ 1) & 15);
3598 tcg_gen_ext32u_i64(tmp2
, tmp2
);
3599 tcg_gen_ext32u_i64(tmp3
, tmp3
);
3600 tcg_gen_mul_i64(tmp2
, tmp2
, tmp3
);
3601 store_reg32_i64((r1
+ 1) & 15, tmp2
);
3602 tcg_gen_shri_i64(tmp2
, tmp2
, 32);
3603 store_reg32_i64(r1
, tmp2
);
3604 tcg_temp_free_i64(tmp2
);
3605 tcg_temp_free_i64(tmp3
);
3607 case 0x97: /* DLR R1,R2 [RRE] */
3608 /* reg(r1) = reg(r1, r1+1) % reg(r2) */
3609 /* reg(r1+1) = reg(r1, r1+1) / reg(r2) */
3611 tmp2
= load_reg(r2
);
3612 tmp3
= load_reg((r1
+ 1) & 15);
3613 tcg_gen_ext32u_i64(tmp2
, tmp2
);
3614 tcg_gen_ext32u_i64(tmp3
, tmp3
);
3615 tcg_gen_shli_i64(tmp
, tmp
, 32);
3616 tcg_gen_or_i64(tmp
, tmp
, tmp3
);
3618 tcg_gen_rem_i64(tmp3
, tmp
, tmp2
);
3619 tcg_gen_div_i64(tmp
, tmp
, tmp2
);
3620 store_reg32_i64((r1
+ 1) & 15, tmp
);
3621 store_reg32_i64(r1
, tmp3
);
3622 tcg_temp_free_i64(tmp
);
3623 tcg_temp_free_i64(tmp2
);
3624 tcg_temp_free_i64(tmp3
);
3626 case 0x98: /* ALCR R1,R2 [RRE] */
3627 tmp32_1
= load_reg32(r1
);
3628 tmp32_2
= load_reg32(r2
);
3629 tmp32_3
= tcg_temp_new_i32();
3630 /* XXX possible optimization point */
3632 gen_helper_addc_u32(tmp32_3
, cc_op
, tmp32_1
, tmp32_2
);
3633 set_cc_addu32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
3634 store_reg32(r1
, tmp32_3
);
3635 tcg_temp_free_i32(tmp32_1
);
3636 tcg_temp_free_i32(tmp32_2
);
3637 tcg_temp_free_i32(tmp32_3
);
3639 case 0x99: /* SLBR R1,R2 [RRE] */
3640 tmp32_1
= load_reg32(r2
);
3641 tmp32_2
= tcg_const_i32(r1
);
3643 gen_helper_slb(cc_op
, cc_op
, tmp32_2
, tmp32_1
);
3645 tcg_temp_free_i32(tmp32_1
);
3646 tcg_temp_free_i32(tmp32_2
);
3649 LOG_DISAS("illegal b9 operation 0x%x\n", op
);
3650 gen_illegal_opcode(s
, 2);
3655 static void disas_c0(DisasContext
*s
, int op
, int r1
, int i2
)
3658 TCGv_i32 tmp32_1
, tmp32_2
;
3659 uint64_t target
= s
->pc
+ i2
* 2LL;
3662 LOG_DISAS("disas_c0: op 0x%x r1 %d i2 %d\n", op
, r1
, i2
);
3665 case 0: /* larl r1, i2 */
3666 tmp
= tcg_const_i64(target
);
3668 tcg_temp_free_i64(tmp
);
3670 case 0x1: /* LGFI R1,I2 [RIL] */
3671 tmp
= tcg_const_i64((int64_t)i2
);
3673 tcg_temp_free_i64(tmp
);
3675 case 0x4: /* BRCL M1,I2 [RIL] */
3676 /* m1 & (1 << (3 - cc)) */
3677 tmp32_1
= tcg_const_i32(3);
3678 tmp32_2
= tcg_const_i32(1);
3680 tcg_gen_sub_i32(tmp32_1
, tmp32_1
, cc_op
);
3681 tcg_gen_shl_i32(tmp32_2
, tmp32_2
, tmp32_1
);
3682 tcg_temp_free_i32(tmp32_1
);
3683 tmp32_1
= tcg_const_i32(r1
); /* m1 == r1 */
3684 tcg_gen_and_i32(tmp32_1
, tmp32_1
, tmp32_2
);
3685 l1
= gen_new_label();
3686 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp32_1
, 0, l1
);
3687 gen_goto_tb(s
, 0, target
);
3689 gen_goto_tb(s
, 1, s
->pc
+ 6);
3690 s
->is_jmp
= DISAS_TB_JUMP
;
3691 tcg_temp_free_i32(tmp32_1
);
3692 tcg_temp_free_i32(tmp32_2
);
3694 case 0x5: /* brasl r1, i2 */
3695 tmp
= tcg_const_i64(pc_to_link_info(s
, s
->pc
+ 6));
3697 tcg_temp_free_i64(tmp
);
3698 gen_goto_tb(s
, 0, target
);
3699 s
->is_jmp
= DISAS_TB_JUMP
;
3701 case 0x7: /* XILF R1,I2 [RIL] */
3702 case 0xb: /* NILF R1,I2 [RIL] */
3703 case 0xd: /* OILF R1,I2 [RIL] */
3704 tmp32_1
= load_reg32(r1
);
3707 tcg_gen_xori_i32(tmp32_1
, tmp32_1
, (uint32_t)i2
);
3710 tcg_gen_andi_i32(tmp32_1
, tmp32_1
, (uint32_t)i2
);
3713 tcg_gen_ori_i32(tmp32_1
, tmp32_1
, (uint32_t)i2
);
3718 store_reg32(r1
, tmp32_1
);
3719 set_cc_nz_u32(s
, tmp32_1
);
3720 tcg_temp_free_i32(tmp32_1
);
3722 case 0x9: /* IILF R1,I2 [RIL] */
3723 tmp32_1
= tcg_const_i32((uint32_t)i2
);
3724 store_reg32(r1
, tmp32_1
);
3725 tcg_temp_free_i32(tmp32_1
);
3727 case 0xa: /* NIHF R1,I2 [RIL] */
3729 tmp32_1
= tcg_temp_new_i32();
3730 tcg_gen_andi_i64(tmp
, tmp
, (((uint64_t)((uint32_t)i2
)) << 32)
3733 tcg_gen_shri_i64(tmp
, tmp
, 32);
3734 tcg_gen_trunc_i64_i32(tmp32_1
, tmp
);
3735 set_cc_nz_u32(s
, tmp32_1
);
3736 tcg_temp_free_i64(tmp
);
3737 tcg_temp_free_i32(tmp32_1
);
3739 case 0xe: /* LLIHF R1,I2 [RIL] */
3740 tmp
= tcg_const_i64(((uint64_t)(uint32_t)i2
) << 32);
3742 tcg_temp_free_i64(tmp
);
3744 case 0xf: /* LLILF R1,I2 [RIL] */
3745 tmp
= tcg_const_i64((uint32_t)i2
);
3747 tcg_temp_free_i64(tmp
);
3750 LOG_DISAS("illegal c0 operation 0x%x\n", op
);
3751 gen_illegal_opcode(s
, 3);
3756 static void disas_c2(DisasContext
*s
, int op
, int r1
, int i2
)
3758 TCGv_i64 tmp
, tmp2
, tmp3
;
3759 TCGv_i32 tmp32_1
, tmp32_2
, tmp32_3
;
3762 case 0x4: /* SLGFI R1,I2 [RIL] */
3763 case 0xa: /* ALGFI R1,I2 [RIL] */
3765 tmp2
= tcg_const_i64((uint64_t)(uint32_t)i2
);
3766 tmp3
= tcg_temp_new_i64();
3769 tcg_gen_sub_i64(tmp3
, tmp
, tmp2
);
3770 set_cc_subu64(s
, tmp
, tmp2
, tmp3
);
3773 tcg_gen_add_i64(tmp3
, tmp
, tmp2
);
3774 set_cc_addu64(s
, tmp
, tmp2
, tmp3
);
3779 store_reg(r1
, tmp3
);
3780 tcg_temp_free_i64(tmp
);
3781 tcg_temp_free_i64(tmp2
);
3782 tcg_temp_free_i64(tmp3
);
3784 case 0x5: /* SLFI R1,I2 [RIL] */
3785 case 0xb: /* ALFI R1,I2 [RIL] */
3786 tmp32_1
= load_reg32(r1
);
3787 tmp32_2
= tcg_const_i32(i2
);
3788 tmp32_3
= tcg_temp_new_i32();
3791 tcg_gen_sub_i32(tmp32_3
, tmp32_1
, tmp32_2
);
3792 set_cc_subu32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
3795 tcg_gen_add_i32(tmp32_3
, tmp32_1
, tmp32_2
);
3796 set_cc_addu32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
3801 store_reg32(r1
, tmp32_3
);
3802 tcg_temp_free_i32(tmp32_1
);
3803 tcg_temp_free_i32(tmp32_2
);
3804 tcg_temp_free_i32(tmp32_3
);
3806 case 0xc: /* CGFI R1,I2 [RIL] */
3808 cmp_s64c(s
, tmp
, (int64_t)i2
);
3809 tcg_temp_free_i64(tmp
);
3811 case 0xe: /* CLGFI R1,I2 [RIL] */
3813 cmp_u64c(s
, tmp
, (uint64_t)(uint32_t)i2
);
3814 tcg_temp_free_i64(tmp
);
3816 case 0xd: /* CFI R1,I2 [RIL] */
3817 tmp32_1
= load_reg32(r1
);
3818 cmp_s32c(s
, tmp32_1
, i2
);
3819 tcg_temp_free_i32(tmp32_1
);
3821 case 0xf: /* CLFI R1,I2 [RIL] */
3822 tmp32_1
= load_reg32(r1
);
3823 cmp_u32c(s
, tmp32_1
, i2
);
3824 tcg_temp_free_i32(tmp32_1
);
3827 LOG_DISAS("illegal c2 operation 0x%x\n", op
);
3828 gen_illegal_opcode(s
, 3);
3833 static void gen_and_or_xor_i32(int opc
, TCGv_i32 tmp
, TCGv_i32 tmp2
)
3835 switch (opc
& 0xf) {
3837 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
3840 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
3843 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
3850 static void disas_s390_insn(DisasContext
*s
)
3852 TCGv_i64 tmp
, tmp2
, tmp3
, tmp4
;
3853 TCGv_i32 tmp32_1
, tmp32_2
, tmp32_3
, tmp32_4
;
3856 int op
, r1
, r2
, r3
, d1
, d2
, x2
, b1
, b2
, i
, i2
, r1b
;
3861 opc
= ldub_code(s
->pc
);
3862 LOG_DISAS("opc 0x%x\n", opc
);
3867 #ifndef CONFIG_USER_ONLY
3868 case 0x01: /* SAM */
3869 insn
= ld_code2(s
->pc
);
3870 /* set addressing mode, but we only do 64bit anyways */
3873 case 0x6: /* BCTR R1,R2 [RR] */
3874 insn
= ld_code2(s
->pc
);
3875 decode_rr(s
, insn
, &r1
, &r2
);
3876 tmp32_1
= load_reg32(r1
);
3877 tcg_gen_subi_i32(tmp32_1
, tmp32_1
, 1);
3878 store_reg32(r1
, tmp32_1
);
3881 gen_update_cc_op(s
);
3882 l1
= gen_new_label();
3883 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp32_1
, 0, l1
);
3885 /* not taking the branch, jump to after the instruction */
3886 gen_goto_tb(s
, 0, s
->pc
+ 2);
3889 /* take the branch, move R2 into psw.addr */
3890 tmp32_1
= load_reg32(r2
);
3891 tmp
= tcg_temp_new_i64();
3892 tcg_gen_extu_i32_i64(tmp
, tmp32_1
);
3893 tcg_gen_mov_i64(psw_addr
, tmp
);
3894 s
->is_jmp
= DISAS_JUMP
;
3895 tcg_temp_free_i32(tmp32_1
);
3896 tcg_temp_free_i64(tmp
);
3899 case 0x7: /* BCR M1,R2 [RR] */
3900 insn
= ld_code2(s
->pc
);
3901 decode_rr(s
, insn
, &r1
, &r2
);
3904 gen_bcr(s
, r1
, tmp
, s
->pc
);
3905 tcg_temp_free_i64(tmp
);
3906 s
->is_jmp
= DISAS_TB_JUMP
;
3908 /* XXX: "serialization and checkpoint-synchronization function"? */
3911 case 0xa: /* SVC I [RR] */
3912 insn
= ld_code2(s
->pc
);
3917 tmp32_1
= tcg_const_i32(i
);
3918 tmp32_2
= tcg_const_i32(ilc
* 2);
3919 tmp32_3
= tcg_const_i32(EXCP_SVC
);
3920 tcg_gen_st_i32(tmp32_1
, cpu_env
, offsetof(CPUState
, int_svc_code
));
3921 tcg_gen_st_i32(tmp32_2
, cpu_env
, offsetof(CPUState
, int_svc_ilc
));
3922 gen_helper_exception(tmp32_3
);
3923 s
->is_jmp
= DISAS_EXCP
;
3924 tcg_temp_free_i32(tmp32_1
);
3925 tcg_temp_free_i32(tmp32_2
);
3926 tcg_temp_free_i32(tmp32_3
);
3928 case 0xd: /* BASR R1,R2 [RR] */
3929 insn
= ld_code2(s
->pc
);
3930 decode_rr(s
, insn
, &r1
, &r2
);
3931 tmp
= tcg_const_i64(pc_to_link_info(s
, s
->pc
+ 2));
3934 tmp2
= load_reg(r2
);
3935 tcg_gen_mov_i64(psw_addr
, tmp2
);
3936 tcg_temp_free_i64(tmp2
);
3937 s
->is_jmp
= DISAS_JUMP
;
3939 tcg_temp_free_i64(tmp
);
3941 case 0xe: /* MVCL R1,R2 [RR] */
3942 insn
= ld_code2(s
->pc
);
3943 decode_rr(s
, insn
, &r1
, &r2
);
3944 tmp32_1
= tcg_const_i32(r1
);
3945 tmp32_2
= tcg_const_i32(r2
);
3946 potential_page_fault(s
);
3947 gen_helper_mvcl(cc_op
, tmp32_1
, tmp32_2
);
3949 tcg_temp_free_i32(tmp32_1
);
3950 tcg_temp_free_i32(tmp32_2
);
3952 case 0x10: /* LPR R1,R2 [RR] */
3953 insn
= ld_code2(s
->pc
);
3954 decode_rr(s
, insn
, &r1
, &r2
);
3955 tmp32_1
= load_reg32(r2
);
3956 set_cc_abs32(s
, tmp32_1
);
3957 gen_helper_abs_i32(tmp32_1
, tmp32_1
);
3958 store_reg32(r1
, tmp32_1
);
3959 tcg_temp_free_i32(tmp32_1
);
3961 case 0x11: /* LNR R1,R2 [RR] */
3962 insn
= ld_code2(s
->pc
);
3963 decode_rr(s
, insn
, &r1
, &r2
);
3964 tmp32_1
= load_reg32(r2
);
3965 set_cc_nabs32(s
, tmp32_1
);
3966 gen_helper_nabs_i32(tmp32_1
, tmp32_1
);
3967 store_reg32(r1
, tmp32_1
);
3968 tcg_temp_free_i32(tmp32_1
);
3970 case 0x12: /* LTR R1,R2 [RR] */
3971 insn
= ld_code2(s
->pc
);
3972 decode_rr(s
, insn
, &r1
, &r2
);
3973 tmp32_1
= load_reg32(r2
);
3975 store_reg32(r1
, tmp32_1
);
3977 set_cc_s32(s
, tmp32_1
);
3978 tcg_temp_free_i32(tmp32_1
);
3980 case 0x13: /* LCR R1,R2 [RR] */
3981 insn
= ld_code2(s
->pc
);
3982 decode_rr(s
, insn
, &r1
, &r2
);
3983 tmp32_1
= load_reg32(r2
);
3984 tcg_gen_neg_i32(tmp32_1
, tmp32_1
);
3985 store_reg32(r1
, tmp32_1
);
3986 set_cc_comp32(s
, tmp32_1
);
3987 tcg_temp_free_i32(tmp32_1
);
3989 case 0x14: /* NR R1,R2 [RR] */
3990 case 0x16: /* OR R1,R2 [RR] */
3991 case 0x17: /* XR R1,R2 [RR] */
3992 insn
= ld_code2(s
->pc
);
3993 decode_rr(s
, insn
, &r1
, &r2
);
3994 tmp32_2
= load_reg32(r2
);
3995 tmp32_1
= load_reg32(r1
);
3996 gen_and_or_xor_i32(opc
, tmp32_1
, tmp32_2
);
3997 store_reg32(r1
, tmp32_1
);
3998 set_cc_nz_u32(s
, tmp32_1
);
3999 tcg_temp_free_i32(tmp32_1
);
4000 tcg_temp_free_i32(tmp32_2
);
4002 case 0x18: /* LR R1,R2 [RR] */
4003 insn
= ld_code2(s
->pc
);
4004 decode_rr(s
, insn
, &r1
, &r2
);
4005 tmp32_1
= load_reg32(r2
);
4006 store_reg32(r1
, tmp32_1
);
4007 tcg_temp_free_i32(tmp32_1
);
4009 case 0x15: /* CLR R1,R2 [RR] */
4010 case 0x19: /* CR R1,R2 [RR] */
4011 insn
= ld_code2(s
->pc
);
4012 decode_rr(s
, insn
, &r1
, &r2
);
4013 tmp32_1
= load_reg32(r1
);
4014 tmp32_2
= load_reg32(r2
);
4016 cmp_u32(s
, tmp32_1
, tmp32_2
);
4018 cmp_s32(s
, tmp32_1
, tmp32_2
);
4020 tcg_temp_free_i32(tmp32_1
);
4021 tcg_temp_free_i32(tmp32_2
);
4023 case 0x1a: /* AR R1,R2 [RR] */
4024 case 0x1e: /* ALR R1,R2 [RR] */
4025 insn
= ld_code2(s
->pc
);
4026 decode_rr(s
, insn
, &r1
, &r2
);
4027 tmp32_1
= load_reg32(r1
);
4028 tmp32_2
= load_reg32(r2
);
4029 tmp32_3
= tcg_temp_new_i32();
4030 tcg_gen_add_i32(tmp32_3
, tmp32_1
, tmp32_2
);
4031 store_reg32(r1
, tmp32_3
);
4033 set_cc_add32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
4035 set_cc_addu32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
4037 tcg_temp_free_i32(tmp32_1
);
4038 tcg_temp_free_i32(tmp32_2
);
4039 tcg_temp_free_i32(tmp32_3
);
4041 case 0x1b: /* SR R1,R2 [RR] */
4042 case 0x1f: /* SLR R1,R2 [RR] */
4043 insn
= ld_code2(s
->pc
);
4044 decode_rr(s
, insn
, &r1
, &r2
);
4045 tmp32_1
= load_reg32(r1
);
4046 tmp32_2
= load_reg32(r2
);
4047 tmp32_3
= tcg_temp_new_i32();
4048 tcg_gen_sub_i32(tmp32_3
, tmp32_1
, tmp32_2
);
4049 store_reg32(r1
, tmp32_3
);
4051 set_cc_sub32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
4053 set_cc_subu32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
4055 tcg_temp_free_i32(tmp32_1
);
4056 tcg_temp_free_i32(tmp32_2
);
4057 tcg_temp_free_i32(tmp32_3
);
4059 case 0x1c: /* MR R1,R2 [RR] */
4060 /* reg(r1, r1+1) = reg(r1+1) * reg(r2) */
4061 insn
= ld_code2(s
->pc
);
4062 decode_rr(s
, insn
, &r1
, &r2
);
4063 tmp2
= load_reg(r2
);
4064 tmp3
= load_reg((r1
+ 1) & 15);
4065 tcg_gen_ext32s_i64(tmp2
, tmp2
);
4066 tcg_gen_ext32s_i64(tmp3
, tmp3
);
4067 tcg_gen_mul_i64(tmp2
, tmp2
, tmp3
);
4068 store_reg32_i64((r1
+ 1) & 15, tmp2
);
4069 tcg_gen_shri_i64(tmp2
, tmp2
, 32);
4070 store_reg32_i64(r1
, tmp2
);
4071 tcg_temp_free_i64(tmp2
);
4072 tcg_temp_free_i64(tmp3
);
4074 case 0x1d: /* DR R1,R2 [RR] */
4075 insn
= ld_code2(s
->pc
);
4076 decode_rr(s
, insn
, &r1
, &r2
);
4077 tmp32_1
= load_reg32(r1
);
4078 tmp32_2
= load_reg32(r1
+ 1);
4079 tmp32_3
= load_reg32(r2
);
4081 tmp
= tcg_temp_new_i64(); /* dividend */
4082 tmp2
= tcg_temp_new_i64(); /* divisor */
4083 tmp3
= tcg_temp_new_i64();
4085 /* dividend is r(r1 << 32) | r(r1 + 1) */
4086 tcg_gen_extu_i32_i64(tmp
, tmp32_1
);
4087 tcg_gen_extu_i32_i64(tmp2
, tmp32_2
);
4088 tcg_gen_shli_i64(tmp
, tmp
, 32);
4089 tcg_gen_or_i64(tmp
, tmp
, tmp2
);
4091 /* divisor is r(r2) */
4092 tcg_gen_ext_i32_i64(tmp2
, tmp32_3
);
4094 tcg_gen_div_i64(tmp3
, tmp
, tmp2
);
4095 tcg_gen_rem_i64(tmp
, tmp
, tmp2
);
4097 tcg_gen_trunc_i64_i32(tmp32_1
, tmp
);
4098 tcg_gen_trunc_i64_i32(tmp32_2
, tmp3
);
4100 store_reg32(r1
, tmp32_1
); /* remainder */
4101 store_reg32(r1
+ 1, tmp32_2
); /* quotient */
4102 tcg_temp_free_i32(tmp32_1
);
4103 tcg_temp_free_i32(tmp32_2
);
4104 tcg_temp_free_i32(tmp32_3
);
4105 tcg_temp_free_i64(tmp
);
4106 tcg_temp_free_i64(tmp2
);
4107 tcg_temp_free_i64(tmp3
);
4109 case 0x28: /* LDR R1,R2 [RR] */
4110 insn
= ld_code2(s
->pc
);
4111 decode_rr(s
, insn
, &r1
, &r2
);
4112 tmp
= load_freg(r2
);
4113 store_freg(r1
, tmp
);
4114 tcg_temp_free_i64(tmp
);
4116 case 0x38: /* LER R1,R2 [RR] */
4117 insn
= ld_code2(s
->pc
);
4118 decode_rr(s
, insn
, &r1
, &r2
);
4119 tmp32_1
= load_freg32(r2
);
4120 store_freg32(r1
, tmp32_1
);
4121 tcg_temp_free_i32(tmp32_1
);
4123 case 0x40: /* STH R1,D2(X2,B2) [RX] */
4124 insn
= ld_code4(s
->pc
);
4125 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4126 tmp2
= load_reg(r1
);
4127 tcg_gen_qemu_st16(tmp2
, tmp
, get_mem_index(s
));
4128 tcg_temp_free_i64(tmp
);
4129 tcg_temp_free_i64(tmp2
);
4132 insn
= ld_code4(s
->pc
);
4133 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4134 store_reg(r1
, tmp
); /* FIXME: 31/24-bit addressing */
4135 tcg_temp_free_i64(tmp
);
4137 case 0x42: /* STC R1,D2(X2,B2) [RX] */
4138 insn
= ld_code4(s
->pc
);
4139 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4140 tmp2
= load_reg(r1
);
4141 tcg_gen_qemu_st8(tmp2
, tmp
, get_mem_index(s
));
4142 tcg_temp_free_i64(tmp
);
4143 tcg_temp_free_i64(tmp2
);
4145 case 0x43: /* IC R1,D2(X2,B2) [RX] */
4146 insn
= ld_code4(s
->pc
);
4147 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4148 tmp2
= tcg_temp_new_i64();
4149 tcg_gen_qemu_ld8u(tmp2
, tmp
, get_mem_index(s
));
4150 store_reg8(r1
, tmp2
);
4151 tcg_temp_free_i64(tmp
);
4152 tcg_temp_free_i64(tmp2
);
4154 case 0x44: /* EX R1,D2(X2,B2) [RX] */
4155 insn
= ld_code4(s
->pc
);
4156 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4157 tmp2
= load_reg(r1
);
4158 tmp3
= tcg_const_i64(s
->pc
+ 4);
4161 gen_helper_ex(cc_op
, cc_op
, tmp2
, tmp
, tmp3
);
4163 tcg_temp_free_i64(tmp
);
4164 tcg_temp_free_i64(tmp2
);
4165 tcg_temp_free_i64(tmp3
);
4167 case 0x46: /* BCT R1,D2(X2,B2) [RX] */
4168 insn
= ld_code4(s
->pc
);
4169 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4170 tcg_temp_free_i64(tmp
);
4172 tmp32_1
= load_reg32(r1
);
4173 tcg_gen_subi_i32(tmp32_1
, tmp32_1
, 1);
4174 store_reg32(r1
, tmp32_1
);
4176 gen_update_cc_op(s
);
4177 l1
= gen_new_label();
4178 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp32_1
, 0, l1
);
4180 /* not taking the branch, jump to after the instruction */
4181 gen_goto_tb(s
, 0, s
->pc
+ 4);
4184 /* take the branch, move R2 into psw.addr */
4185 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4186 tcg_gen_mov_i64(psw_addr
, tmp
);
4187 s
->is_jmp
= DISAS_JUMP
;
4188 tcg_temp_free_i32(tmp32_1
);
4189 tcg_temp_free_i64(tmp
);
4191 case 0x47: /* BC M1,D2(X2,B2) [RX] */
4192 insn
= ld_code4(s
->pc
);
4193 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4194 gen_bcr(s
, r1
, tmp
, s
->pc
+ 4);
4195 tcg_temp_free_i64(tmp
);
4196 s
->is_jmp
= DISAS_TB_JUMP
;
4198 case 0x48: /* LH R1,D2(X2,B2) [RX] */
4199 insn
= ld_code4(s
->pc
);
4200 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4201 tmp2
= tcg_temp_new_i64();
4202 tcg_gen_qemu_ld16s(tmp2
, tmp
, get_mem_index(s
));
4203 store_reg32_i64(r1
, tmp2
);
4204 tcg_temp_free_i64(tmp
);
4205 tcg_temp_free_i64(tmp2
);
4207 case 0x49: /* CH R1,D2(X2,B2) [RX] */
4208 insn
= ld_code4(s
->pc
);
4209 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4210 tmp32_1
= load_reg32(r1
);
4211 tmp32_2
= tcg_temp_new_i32();
4212 tmp2
= tcg_temp_new_i64();
4213 tcg_gen_qemu_ld16s(tmp2
, tmp
, get_mem_index(s
));
4214 tcg_gen_trunc_i64_i32(tmp32_2
, tmp2
);
4215 cmp_s32(s
, tmp32_1
, tmp32_2
);
4216 tcg_temp_free_i32(tmp32_1
);
4217 tcg_temp_free_i32(tmp32_2
);
4218 tcg_temp_free_i64(tmp
);
4219 tcg_temp_free_i64(tmp2
);
4221 case 0x4a: /* AH R1,D2(X2,B2) [RX] */
4222 case 0x4b: /* SH R1,D2(X2,B2) [RX] */
4223 case 0x4c: /* MH R1,D2(X2,B2) [RX] */
4224 insn
= ld_code4(s
->pc
);
4225 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4226 tmp2
= tcg_temp_new_i64();
4227 tmp32_1
= load_reg32(r1
);
4228 tmp32_2
= tcg_temp_new_i32();
4229 tmp32_3
= tcg_temp_new_i32();
4231 tcg_gen_qemu_ld16s(tmp2
, tmp
, get_mem_index(s
));
4232 tcg_gen_trunc_i64_i32(tmp32_2
, tmp2
);
4235 tcg_gen_add_i32(tmp32_3
, tmp32_1
, tmp32_2
);
4236 set_cc_add32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
4239 tcg_gen_sub_i32(tmp32_3
, tmp32_1
, tmp32_2
);
4240 set_cc_sub32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
4243 tcg_gen_mul_i32(tmp32_3
, tmp32_1
, tmp32_2
);
4248 store_reg32(r1
, tmp32_3
);
4250 tcg_temp_free_i32(tmp32_1
);
4251 tcg_temp_free_i32(tmp32_2
);
4252 tcg_temp_free_i32(tmp32_3
);
4253 tcg_temp_free_i64(tmp
);
4254 tcg_temp_free_i64(tmp2
);
4256 case 0x4d: /* BAS R1,D2(X2,B2) [RX] */
4257 insn
= ld_code4(s
->pc
);
4258 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4259 tmp2
= tcg_const_i64(pc_to_link_info(s
, s
->pc
+ 4));
4260 store_reg(r1
, tmp2
);
4261 tcg_gen_mov_i64(psw_addr
, tmp
);
4262 tcg_temp_free_i64(tmp
);
4263 tcg_temp_free_i64(tmp2
);
4264 s
->is_jmp
= DISAS_JUMP
;
4266 case 0x4e: /* CVD R1,D2(X2,B2) [RX] */
4267 insn
= ld_code4(s
->pc
);
4268 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4269 tmp2
= tcg_temp_new_i64();
4270 tmp32_1
= tcg_temp_new_i32();
4271 tcg_gen_trunc_i64_i32(tmp32_1
, regs
[r1
]);
4272 gen_helper_cvd(tmp2
, tmp32_1
);
4273 tcg_gen_qemu_st64(tmp2
, tmp
, get_mem_index(s
));
4274 tcg_temp_free_i64(tmp
);
4275 tcg_temp_free_i64(tmp2
);
4276 tcg_temp_free_i32(tmp32_1
);
4278 case 0x50: /* st r1, d2(x2, b2) */
4279 insn
= ld_code4(s
->pc
);
4280 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4281 tmp2
= load_reg(r1
);
4282 tcg_gen_qemu_st32(tmp2
, tmp
, get_mem_index(s
));
4283 tcg_temp_free_i64(tmp
);
4284 tcg_temp_free_i64(tmp2
);
4286 case 0x55: /* CL R1,D2(X2,B2) [RX] */
4287 insn
= ld_code4(s
->pc
);
4288 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4289 tmp2
= tcg_temp_new_i64();
4290 tmp32_1
= tcg_temp_new_i32();
4291 tmp32_2
= load_reg32(r1
);
4292 tcg_gen_qemu_ld32u(tmp2
, tmp
, get_mem_index(s
));
4293 tcg_gen_trunc_i64_i32(tmp32_1
, tmp2
);
4294 cmp_u32(s
, tmp32_2
, tmp32_1
);
4295 tcg_temp_free_i64(tmp
);
4296 tcg_temp_free_i64(tmp2
);
4297 tcg_temp_free_i32(tmp32_1
);
4298 tcg_temp_free_i32(tmp32_2
);
4300 case 0x54: /* N R1,D2(X2,B2) [RX] */
4301 case 0x56: /* O R1,D2(X2,B2) [RX] */
4302 case 0x57: /* X R1,D2(X2,B2) [RX] */
4303 insn
= ld_code4(s
->pc
);
4304 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4305 tmp2
= tcg_temp_new_i64();
4306 tmp32_1
= load_reg32(r1
);
4307 tmp32_2
= tcg_temp_new_i32();
4308 tcg_gen_qemu_ld32u(tmp2
, tmp
, get_mem_index(s
));
4309 tcg_gen_trunc_i64_i32(tmp32_2
, tmp2
);
4310 gen_and_or_xor_i32(opc
, tmp32_1
, tmp32_2
);
4311 store_reg32(r1
, tmp32_1
);
4312 set_cc_nz_u32(s
, tmp32_1
);
4313 tcg_temp_free_i64(tmp
);
4314 tcg_temp_free_i64(tmp2
);
4315 tcg_temp_free_i32(tmp32_1
);
4316 tcg_temp_free_i32(tmp32_2
);
4318 case 0x58: /* l r1, d2(x2, b2) */
4319 insn
= ld_code4(s
->pc
);
4320 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4321 tmp2
= tcg_temp_new_i64();
4322 tmp32_1
= tcg_temp_new_i32();
4323 tcg_gen_qemu_ld32u(tmp2
, tmp
, get_mem_index(s
));
4324 tcg_gen_trunc_i64_i32(tmp32_1
, tmp2
);
4325 store_reg32(r1
, tmp32_1
);
4326 tcg_temp_free_i64(tmp
);
4327 tcg_temp_free_i64(tmp2
);
4328 tcg_temp_free_i32(tmp32_1
);
4330 case 0x59: /* C R1,D2(X2,B2) [RX] */
4331 insn
= ld_code4(s
->pc
);
4332 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4333 tmp2
= tcg_temp_new_i64();
4334 tmp32_1
= tcg_temp_new_i32();
4335 tmp32_2
= load_reg32(r1
);
4336 tcg_gen_qemu_ld32s(tmp2
, tmp
, get_mem_index(s
));
4337 tcg_gen_trunc_i64_i32(tmp32_1
, tmp2
);
4338 cmp_s32(s
, tmp32_2
, tmp32_1
);
4339 tcg_temp_free_i64(tmp
);
4340 tcg_temp_free_i64(tmp2
);
4341 tcg_temp_free_i32(tmp32_1
);
4342 tcg_temp_free_i32(tmp32_2
);
4344 case 0x5a: /* A R1,D2(X2,B2) [RX] */
4345 case 0x5b: /* S R1,D2(X2,B2) [RX] */
4346 case 0x5e: /* AL R1,D2(X2,B2) [RX] */
4347 case 0x5f: /* SL R1,D2(X2,B2) [RX] */
4348 insn
= ld_code4(s
->pc
);
4349 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4350 tmp32_1
= load_reg32(r1
);
4351 tmp32_2
= tcg_temp_new_i32();
4352 tmp32_3
= tcg_temp_new_i32();
4353 tcg_gen_qemu_ld32s(tmp
, tmp
, get_mem_index(s
));
4354 tcg_gen_trunc_i64_i32(tmp32_2
, tmp
);
4358 tcg_gen_add_i32(tmp32_3
, tmp32_1
, tmp32_2
);
4362 tcg_gen_sub_i32(tmp32_3
, tmp32_1
, tmp32_2
);
4367 store_reg32(r1
, tmp32_3
);
4370 set_cc_add32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
4373 set_cc_addu32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
4376 set_cc_sub32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
4379 set_cc_subu32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
4384 tcg_temp_free_i64(tmp
);
4385 tcg_temp_free_i32(tmp32_1
);
4386 tcg_temp_free_i32(tmp32_2
);
4387 tcg_temp_free_i32(tmp32_3
);
4389 case 0x5c: /* M R1,D2(X2,B2) [RX] */
4390 /* reg(r1, r1+1) = reg(r1+1) * *(s32*)addr */
4391 insn
= ld_code4(s
->pc
);
4392 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4393 tmp2
= tcg_temp_new_i64();
4394 tcg_gen_qemu_ld32s(tmp2
, tmp
, get_mem_index(s
));
4395 tmp3
= load_reg((r1
+ 1) & 15);
4396 tcg_gen_ext32s_i64(tmp2
, tmp2
);
4397 tcg_gen_ext32s_i64(tmp3
, tmp3
);
4398 tcg_gen_mul_i64(tmp2
, tmp2
, tmp3
);
4399 store_reg32_i64((r1
+ 1) & 15, tmp2
);
4400 tcg_gen_shri_i64(tmp2
, tmp2
, 32);
4401 store_reg32_i64(r1
, tmp2
);
4402 tcg_temp_free_i64(tmp
);
4403 tcg_temp_free_i64(tmp2
);
4404 tcg_temp_free_i64(tmp3
);
4406 case 0x5d: /* D R1,D2(X2,B2) [RX] */
4407 insn
= ld_code4(s
->pc
);
4408 tmp3
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4409 tmp32_1
= load_reg32(r1
);
4410 tmp32_2
= load_reg32(r1
+ 1);
4412 tmp
= tcg_temp_new_i64();
4413 tmp2
= tcg_temp_new_i64();
4415 /* dividend is r(r1 << 32) | r(r1 + 1) */
4416 tcg_gen_extu_i32_i64(tmp
, tmp32_1
);
4417 tcg_gen_extu_i32_i64(tmp2
, tmp32_2
);
4418 tcg_gen_shli_i64(tmp
, tmp
, 32);
4419 tcg_gen_or_i64(tmp
, tmp
, tmp2
);
4421 /* divisor is in memory */
4422 tcg_gen_qemu_ld32s(tmp2
, tmp3
, get_mem_index(s
));
4424 /* XXX divisor == 0 -> FixP divide exception */
4426 tcg_gen_div_i64(tmp3
, tmp
, tmp2
);
4427 tcg_gen_rem_i64(tmp
, tmp
, tmp2
);
4429 tcg_gen_trunc_i64_i32(tmp32_1
, tmp
);
4430 tcg_gen_trunc_i64_i32(tmp32_2
, tmp3
);
4432 store_reg32(r1
, tmp32_1
); /* remainder */
4433 store_reg32(r1
+ 1, tmp32_2
); /* quotient */
4434 tcg_temp_free_i32(tmp32_1
);
4435 tcg_temp_free_i32(tmp32_2
);
4436 tcg_temp_free_i64(tmp
);
4437 tcg_temp_free_i64(tmp2
);
4438 tcg_temp_free_i64(tmp3
);
4440 case 0x60: /* STD R1,D2(X2,B2) [RX] */
4441 insn
= ld_code4(s
->pc
);
4442 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4443 tmp2
= load_freg(r1
);
4444 tcg_gen_qemu_st64(tmp2
, tmp
, get_mem_index(s
));
4445 tcg_temp_free_i64(tmp
);
4446 tcg_temp_free_i64(tmp2
);
4448 case 0x68: /* LD R1,D2(X2,B2) [RX] */
4449 insn
= ld_code4(s
->pc
);
4450 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4451 tmp2
= tcg_temp_new_i64();
4452 tcg_gen_qemu_ld64(tmp2
, tmp
, get_mem_index(s
));
4453 store_freg(r1
, tmp2
);
4454 tcg_temp_free_i64(tmp
);
4455 tcg_temp_free_i64(tmp2
);
4457 case 0x70: /* STE R1,D2(X2,B2) [RX] */
4458 insn
= ld_code4(s
->pc
);
4459 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4460 tmp2
= tcg_temp_new_i64();
4461 tmp32_1
= load_freg32(r1
);
4462 tcg_gen_extu_i32_i64(tmp2
, tmp32_1
);
4463 tcg_gen_qemu_st32(tmp2
, tmp
, get_mem_index(s
));
4464 tcg_temp_free_i64(tmp
);
4465 tcg_temp_free_i64(tmp2
);
4466 tcg_temp_free_i32(tmp32_1
);
4468 case 0x71: /* MS R1,D2(X2,B2) [RX] */
4469 insn
= ld_code4(s
->pc
);
4470 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4471 tmp2
= tcg_temp_new_i64();
4472 tmp32_1
= load_reg32(r1
);
4473 tmp32_2
= tcg_temp_new_i32();
4474 tcg_gen_qemu_ld32s(tmp2
, tmp
, get_mem_index(s
));
4475 tcg_gen_trunc_i64_i32(tmp32_2
, tmp2
);
4476 tcg_gen_mul_i32(tmp32_1
, tmp32_1
, tmp32_2
);
4477 store_reg32(r1
, tmp32_1
);
4478 tcg_temp_free_i64(tmp
);
4479 tcg_temp_free_i64(tmp2
);
4480 tcg_temp_free_i32(tmp32_1
);
4481 tcg_temp_free_i32(tmp32_2
);
4483 case 0x78: /* LE R1,D2(X2,B2) [RX] */
4484 insn
= ld_code4(s
->pc
);
4485 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4486 tmp2
= tcg_temp_new_i64();
4487 tmp32_1
= tcg_temp_new_i32();
4488 tcg_gen_qemu_ld32u(tmp2
, tmp
, get_mem_index(s
));
4489 tcg_gen_trunc_i64_i32(tmp32_1
, tmp2
);
4490 store_freg32(r1
, tmp32_1
);
4491 tcg_temp_free_i64(tmp
);
4492 tcg_temp_free_i64(tmp2
);
4493 tcg_temp_free_i32(tmp32_1
);
4495 #ifndef CONFIG_USER_ONLY
4496 case 0x80: /* SSM D2(B2) [S] */
4497 /* Set System Mask */
4498 check_privileged(s
, ilc
);
4499 insn
= ld_code4(s
->pc
);
4500 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4501 tmp
= get_address(s
, 0, b2
, d2
);
4502 tmp2
= tcg_temp_new_i64();
4503 tmp3
= tcg_temp_new_i64();
4504 tcg_gen_andi_i64(tmp3
, psw_mask
, ~0xff00000000000000ULL
);
4505 tcg_gen_qemu_ld8u(tmp2
, tmp
, get_mem_index(s
));
4506 tcg_gen_shli_i64(tmp2
, tmp2
, 56);
4507 tcg_gen_or_i64(psw_mask
, tmp3
, tmp2
);
4508 tcg_temp_free_i64(tmp
);
4509 tcg_temp_free_i64(tmp2
);
4510 tcg_temp_free_i64(tmp3
);
4512 case 0x82: /* LPSW D2(B2) [S] */
4514 check_privileged(s
, ilc
);
4515 insn
= ld_code4(s
->pc
);
4516 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4517 tmp
= get_address(s
, 0, b2
, d2
);
4518 tmp2
= tcg_temp_new_i64();
4519 tmp3
= tcg_temp_new_i64();
4520 tcg_gen_qemu_ld32u(tmp2
, tmp
, get_mem_index(s
));
4521 tcg_gen_addi_i64(tmp
, tmp
, 4);
4522 tcg_gen_qemu_ld32u(tmp3
, tmp
, get_mem_index(s
));
4523 gen_helper_load_psw(tmp2
, tmp3
);
4524 tcg_temp_free_i64(tmp
);
4525 tcg_temp_free_i64(tmp2
);
4526 tcg_temp_free_i64(tmp3
);
4527 /* we need to keep cc_op intact */
4528 s
->is_jmp
= DISAS_JUMP
;
4530 case 0x83: /* DIAG R1,R3,D2 [RS] */
4531 /* Diagnose call (KVM hypercall) */
4532 check_privileged(s
, ilc
);
4533 potential_page_fault(s
);
4534 insn
= ld_code4(s
->pc
);
4535 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4536 tmp32_1
= tcg_const_i32(insn
& 0xfff);
4539 gen_helper_diag(tmp2
, tmp32_1
, tmp2
, tmp3
);
4541 tcg_temp_free_i32(tmp32_1
);
4542 tcg_temp_free_i64(tmp2
);
4543 tcg_temp_free_i64(tmp3
);
4546 case 0x88: /* SRL R1,D2(B2) [RS] */
4547 case 0x89: /* SLL R1,D2(B2) [RS] */
4548 case 0x8a: /* SRA R1,D2(B2) [RS] */
4549 insn
= ld_code4(s
->pc
);
4550 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4551 tmp
= get_address(s
, 0, b2
, d2
);
4552 tmp32_1
= load_reg32(r1
);
4553 tmp32_2
= tcg_temp_new_i32();
4554 tcg_gen_trunc_i64_i32(tmp32_2
, tmp
);
4555 tcg_gen_andi_i32(tmp32_2
, tmp32_2
, 0x3f);
4558 tcg_gen_shr_i32(tmp32_1
, tmp32_1
, tmp32_2
);
4561 tcg_gen_shl_i32(tmp32_1
, tmp32_1
, tmp32_2
);
4564 tcg_gen_sar_i32(tmp32_1
, tmp32_1
, tmp32_2
);
4565 set_cc_s32(s
, tmp32_1
);
4570 store_reg32(r1
, tmp32_1
);
4571 tcg_temp_free_i64(tmp
);
4572 tcg_temp_free_i32(tmp32_1
);
4573 tcg_temp_free_i32(tmp32_2
);
4575 case 0x8c: /* SRDL R1,D2(B2) [RS] */
4576 case 0x8d: /* SLDL R1,D2(B2) [RS] */
4577 case 0x8e: /* SRDA R1,D2(B2) [RS] */
4578 insn
= ld_code4(s
->pc
);
4579 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4580 tmp
= get_address(s
, 0, b2
, d2
); /* shift */
4581 tmp2
= tcg_temp_new_i64();
4582 tmp32_1
= load_reg32(r1
);
4583 tmp32_2
= load_reg32(r1
+ 1);
4584 tcg_gen_concat_i32_i64(tmp2
, tmp32_2
, tmp32_1
); /* operand */
4587 tcg_gen_shr_i64(tmp2
, tmp2
, tmp
);
4590 tcg_gen_shl_i64(tmp2
, tmp2
, tmp
);
4593 tcg_gen_sar_i64(tmp2
, tmp2
, tmp
);
4594 set_cc_s64(s
, tmp2
);
4597 tcg_gen_shri_i64(tmp
, tmp2
, 32);
4598 tcg_gen_trunc_i64_i32(tmp32_1
, tmp
);
4599 store_reg32(r1
, tmp32_1
);
4600 tcg_gen_trunc_i64_i32(tmp32_2
, tmp2
);
4601 store_reg32(r1
+ 1, tmp32_2
);
4602 tcg_temp_free_i64(tmp
);
4603 tcg_temp_free_i64(tmp2
);
4605 case 0x98: /* LM R1,R3,D2(B2) [RS] */
4606 case 0x90: /* STM R1,R3,D2(B2) [RS] */
4607 insn
= ld_code4(s
->pc
);
4608 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4610 tmp
= get_address(s
, 0, b2
, d2
);
4611 tmp2
= tcg_temp_new_i64();
4612 tmp3
= tcg_const_i64(4);
4613 tmp4
= tcg_const_i64(0xffffffff00000000ULL
);
4614 for (i
= r1
;; i
= (i
+ 1) % 16) {
4616 tcg_gen_qemu_ld32u(tmp2
, tmp
, get_mem_index(s
));
4617 tcg_gen_and_i64(regs
[i
], regs
[i
], tmp4
);
4618 tcg_gen_or_i64(regs
[i
], regs
[i
], tmp2
);
4620 tcg_gen_qemu_st32(regs
[i
], tmp
, get_mem_index(s
));
4625 tcg_gen_add_i64(tmp
, tmp
, tmp3
);
4627 tcg_temp_free_i64(tmp
);
4628 tcg_temp_free_i64(tmp2
);
4629 tcg_temp_free_i64(tmp3
);
4630 tcg_temp_free_i64(tmp4
);
4632 case 0x91: /* TM D1(B1),I2 [SI] */
4633 insn
= ld_code4(s
->pc
);
4634 tmp
= decode_si(s
, insn
, &i2
, &b1
, &d1
);
4635 tmp2
= tcg_const_i64(i2
);
4636 tcg_gen_qemu_ld8u(tmp
, tmp
, get_mem_index(s
));
4637 cmp_64(s
, tmp
, tmp2
, CC_OP_TM_32
);
4638 tcg_temp_free_i64(tmp
);
4639 tcg_temp_free_i64(tmp2
);
4641 case 0x92: /* MVI D1(B1),I2 [SI] */
4642 insn
= ld_code4(s
->pc
);
4643 tmp
= decode_si(s
, insn
, &i2
, &b1
, &d1
);
4644 tmp2
= tcg_const_i64(i2
);
4645 tcg_gen_qemu_st8(tmp2
, tmp
, get_mem_index(s
));
4646 tcg_temp_free_i64(tmp
);
4647 tcg_temp_free_i64(tmp2
);
4649 case 0x94: /* NI D1(B1),I2 [SI] */
4650 case 0x96: /* OI D1(B1),I2 [SI] */
4651 case 0x97: /* XI D1(B1),I2 [SI] */
4652 insn
= ld_code4(s
->pc
);
4653 tmp
= decode_si(s
, insn
, &i2
, &b1
, &d1
);
4654 tmp2
= tcg_temp_new_i64();
4655 tcg_gen_qemu_ld8u(tmp2
, tmp
, get_mem_index(s
));
4658 tcg_gen_andi_i64(tmp2
, tmp2
, i2
);
4661 tcg_gen_ori_i64(tmp2
, tmp2
, i2
);
4664 tcg_gen_xori_i64(tmp2
, tmp2
, i2
);
4669 tcg_gen_qemu_st8(tmp2
, tmp
, get_mem_index(s
));
4670 set_cc_nz_u64(s
, tmp2
);
4671 tcg_temp_free_i64(tmp
);
4672 tcg_temp_free_i64(tmp2
);
4674 case 0x95: /* CLI D1(B1),I2 [SI] */
4675 insn
= ld_code4(s
->pc
);
4676 tmp
= decode_si(s
, insn
, &i2
, &b1
, &d1
);
4677 tmp2
= tcg_temp_new_i64();
4678 tcg_gen_qemu_ld8u(tmp2
, tmp
, get_mem_index(s
));
4679 cmp_u64c(s
, tmp2
, i2
);
4680 tcg_temp_free_i64(tmp
);
4681 tcg_temp_free_i64(tmp2
);
4683 case 0x9a: /* LAM R1,R3,D2(B2) [RS] */
4684 insn
= ld_code4(s
->pc
);
4685 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4686 tmp
= get_address(s
, 0, b2
, d2
);
4687 tmp32_1
= tcg_const_i32(r1
);
4688 tmp32_2
= tcg_const_i32(r3
);
4689 potential_page_fault(s
);
4690 gen_helper_lam(tmp32_1
, tmp
, tmp32_2
);
4691 tcg_temp_free_i64(tmp
);
4692 tcg_temp_free_i32(tmp32_1
);
4693 tcg_temp_free_i32(tmp32_2
);
4695 case 0x9b: /* STAM R1,R3,D2(B2) [RS] */
4696 insn
= ld_code4(s
->pc
);
4697 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4698 tmp
= get_address(s
, 0, b2
, d2
);
4699 tmp32_1
= tcg_const_i32(r1
);
4700 tmp32_2
= tcg_const_i32(r3
);
4701 potential_page_fault(s
);
4702 gen_helper_stam(tmp32_1
, tmp
, tmp32_2
);
4703 tcg_temp_free_i64(tmp
);
4704 tcg_temp_free_i32(tmp32_1
);
4705 tcg_temp_free_i32(tmp32_2
);
4708 insn
= ld_code4(s
->pc
);
4709 r1
= (insn
>> 20) & 0xf;
4710 op
= (insn
>> 16) & 0xf;
4712 disas_a5(s
, op
, r1
, i2
);
4715 insn
= ld_code4(s
->pc
);
4716 r1
= (insn
>> 20) & 0xf;
4717 op
= (insn
>> 16) & 0xf;
4719 disas_a7(s
, op
, r1
, i2
);
4721 case 0xa8: /* MVCLE R1,R3,D2(B2) [RS] */
4722 insn
= ld_code4(s
->pc
);
4723 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4724 tmp
= get_address(s
, 0, b2
, d2
);
4725 tmp32_1
= tcg_const_i32(r1
);
4726 tmp32_2
= tcg_const_i32(r3
);
4727 potential_page_fault(s
);
4728 gen_helper_mvcle(cc_op
, tmp32_1
, tmp
, tmp32_2
);
4730 tcg_temp_free_i64(tmp
);
4731 tcg_temp_free_i32(tmp32_1
);
4732 tcg_temp_free_i32(tmp32_2
);
4734 case 0xa9: /* CLCLE R1,R3,D2(B2) [RS] */
4735 insn
= ld_code4(s
->pc
);
4736 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4737 tmp
= get_address(s
, 0, b2
, d2
);
4738 tmp32_1
= tcg_const_i32(r1
);
4739 tmp32_2
= tcg_const_i32(r3
);
4740 potential_page_fault(s
);
4741 gen_helper_clcle(cc_op
, tmp32_1
, tmp
, tmp32_2
);
4743 tcg_temp_free_i64(tmp
);
4744 tcg_temp_free_i32(tmp32_1
);
4745 tcg_temp_free_i32(tmp32_2
);
4747 #ifndef CONFIG_USER_ONLY
4748 case 0xac: /* STNSM D1(B1),I2 [SI] */
4749 case 0xad: /* STOSM D1(B1),I2 [SI] */
4750 check_privileged(s
, ilc
);
4751 insn
= ld_code4(s
->pc
);
4752 tmp
= decode_si(s
, insn
, &i2
, &b1
, &d1
);
4753 tmp2
= tcg_temp_new_i64();
4754 tcg_gen_shri_i64(tmp2
, psw_mask
, 56);
4755 tcg_gen_qemu_st8(tmp2
, tmp
, get_mem_index(s
));
4757 tcg_gen_andi_i64(psw_mask
, psw_mask
,
4758 ((uint64_t)i2
<< 56) | 0x00ffffffffffffffULL
);
4760 tcg_gen_ori_i64(psw_mask
, psw_mask
, (uint64_t)i2
<< 56);
4762 tcg_temp_free_i64(tmp
);
4763 tcg_temp_free_i64(tmp2
);
4765 case 0xae: /* SIGP R1,R3,D2(B2) [RS] */
4766 check_privileged(s
, ilc
);
4767 insn
= ld_code4(s
->pc
);
4768 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4769 tmp
= get_address(s
, 0, b2
, d2
);
4770 tmp2
= load_reg(r3
);
4771 tmp32_1
= tcg_const_i32(r1
);
4772 potential_page_fault(s
);
4773 gen_helper_sigp(cc_op
, tmp
, tmp32_1
, tmp2
);
4775 tcg_temp_free_i64(tmp
);
4776 tcg_temp_free_i64(tmp2
);
4777 tcg_temp_free_i32(tmp32_1
);
4779 case 0xb1: /* LRA R1,D2(X2, B2) [RX] */
4780 check_privileged(s
, ilc
);
4781 insn
= ld_code4(s
->pc
);
4782 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4783 tmp32_1
= tcg_const_i32(r1
);
4784 potential_page_fault(s
);
4785 gen_helper_lra(cc_op
, tmp
, tmp32_1
);
4787 tcg_temp_free_i64(tmp
);
4788 tcg_temp_free_i32(tmp32_1
);
4792 insn
= ld_code4(s
->pc
);
4793 op
= (insn
>> 16) & 0xff;
4795 case 0x9c: /* STFPC D2(B2) [S] */
4797 b2
= (insn
>> 12) & 0xf;
4798 tmp32_1
= tcg_temp_new_i32();
4799 tmp
= tcg_temp_new_i64();
4800 tmp2
= get_address(s
, 0, b2
, d2
);
4801 tcg_gen_ld_i32(tmp32_1
, cpu_env
, offsetof(CPUState
, fpc
));
4802 tcg_gen_extu_i32_i64(tmp
, tmp32_1
);
4803 tcg_gen_qemu_st32(tmp
, tmp2
, get_mem_index(s
));
4804 tcg_temp_free_i32(tmp32_1
);
4805 tcg_temp_free_i64(tmp
);
4806 tcg_temp_free_i64(tmp2
);
4809 disas_b2(s
, op
, insn
);
4814 insn
= ld_code4(s
->pc
);
4815 op
= (insn
>> 16) & 0xff;
4816 r3
= (insn
>> 12) & 0xf; /* aka m3 */
4817 r1
= (insn
>> 4) & 0xf;
4819 disas_b3(s
, op
, r3
, r1
, r2
);
4821 #ifndef CONFIG_USER_ONLY
4822 case 0xb6: /* STCTL R1,R3,D2(B2) [RS] */
4824 check_privileged(s
, ilc
);
4825 insn
= ld_code4(s
->pc
);
4826 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4827 tmp
= get_address(s
, 0, b2
, d2
);
4828 tmp32_1
= tcg_const_i32(r1
);
4829 tmp32_2
= tcg_const_i32(r3
);
4830 potential_page_fault(s
);
4831 gen_helper_stctl(tmp32_1
, tmp
, tmp32_2
);
4832 tcg_temp_free_i64(tmp
);
4833 tcg_temp_free_i32(tmp32_1
);
4834 tcg_temp_free_i32(tmp32_2
);
4836 case 0xb7: /* LCTL R1,R3,D2(B2) [RS] */
4838 check_privileged(s
, ilc
);
4839 insn
= ld_code4(s
->pc
);
4840 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4841 tmp
= get_address(s
, 0, b2
, d2
);
4842 tmp32_1
= tcg_const_i32(r1
);
4843 tmp32_2
= tcg_const_i32(r3
);
4844 potential_page_fault(s
);
4845 gen_helper_lctl(tmp32_1
, tmp
, tmp32_2
);
4846 tcg_temp_free_i64(tmp
);
4847 tcg_temp_free_i32(tmp32_1
);
4848 tcg_temp_free_i32(tmp32_2
);
4852 insn
= ld_code4(s
->pc
);
4853 r1
= (insn
>> 4) & 0xf;
4855 op
= (insn
>> 16) & 0xff;
4856 disas_b9(s
, op
, r1
, r2
);
4858 case 0xba: /* CS R1,R3,D2(B2) [RS] */
4859 insn
= ld_code4(s
->pc
);
4860 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4861 tmp
= get_address(s
, 0, b2
, d2
);
4862 tmp32_1
= tcg_const_i32(r1
);
4863 tmp32_2
= tcg_const_i32(r3
);
4864 potential_page_fault(s
);
4865 gen_helper_cs(cc_op
, tmp32_1
, tmp
, tmp32_2
);
4867 tcg_temp_free_i64(tmp
);
4868 tcg_temp_free_i32(tmp32_1
);
4869 tcg_temp_free_i32(tmp32_2
);
4871 case 0xbd: /* CLM R1,M3,D2(B2) [RS] */
4872 insn
= ld_code4(s
->pc
);
4873 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4874 tmp
= get_address(s
, 0, b2
, d2
);
4875 tmp32_1
= load_reg32(r1
);
4876 tmp32_2
= tcg_const_i32(r3
);
4877 potential_page_fault(s
);
4878 gen_helper_clm(cc_op
, tmp32_1
, tmp32_2
, tmp
);
4880 tcg_temp_free_i64(tmp
);
4881 tcg_temp_free_i32(tmp32_1
);
4882 tcg_temp_free_i32(tmp32_2
);
4884 case 0xbe: /* STCM R1,M3,D2(B2) [RS] */
4885 insn
= ld_code4(s
->pc
);
4886 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4887 tmp
= get_address(s
, 0, b2
, d2
);
4888 tmp32_1
= load_reg32(r1
);
4889 tmp32_2
= tcg_const_i32(r3
);
4890 potential_page_fault(s
);
4891 gen_helper_stcm(tmp32_1
, tmp32_2
, tmp
);
4892 tcg_temp_free_i64(tmp
);
4893 tcg_temp_free_i32(tmp32_1
);
4894 tcg_temp_free_i32(tmp32_2
);
4896 case 0xbf: /* ICM R1,M3,D2(B2) [RS] */
4897 insn
= ld_code4(s
->pc
);
4898 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4900 /* effectively a 32-bit load */
4901 tmp
= get_address(s
, 0, b2
, d2
);
4902 tmp32_1
= tcg_temp_new_i32();
4903 tmp32_2
= tcg_const_i32(r3
);
4904 tcg_gen_qemu_ld32u(tmp
, tmp
, get_mem_index(s
));
4905 store_reg32_i64(r1
, tmp
);
4906 tcg_gen_trunc_i64_i32(tmp32_1
, tmp
);
4907 set_cc_icm(s
, tmp32_2
, tmp32_1
);
4908 tcg_temp_free_i64(tmp
);
4909 tcg_temp_free_i32(tmp32_1
);
4910 tcg_temp_free_i32(tmp32_2
);
4912 uint32_t mask
= 0x00ffffffUL
;
4913 uint32_t shift
= 24;
4915 tmp
= get_address(s
, 0, b2
, d2
);
4916 tmp2
= tcg_temp_new_i64();
4917 tmp32_1
= load_reg32(r1
);
4918 tmp32_2
= tcg_temp_new_i32();
4919 tmp32_3
= tcg_const_i32(r3
);
4920 tmp32_4
= tcg_const_i32(0);
4923 tcg_gen_qemu_ld8u(tmp2
, tmp
, get_mem_index(s
));
4924 tcg_gen_trunc_i64_i32(tmp32_2
, tmp2
);
4926 tcg_gen_shli_i32(tmp32_2
, tmp32_2
, shift
);
4928 tcg_gen_andi_i32(tmp32_1
, tmp32_1
, mask
);
4929 tcg_gen_or_i32(tmp32_1
, tmp32_1
, tmp32_2
);
4930 tcg_gen_or_i32(tmp32_4
, tmp32_4
, tmp32_2
);
4931 tcg_gen_addi_i64(tmp
, tmp
, 1);
4933 m3
= (m3
<< 1) & 0xf;
4934 mask
= (mask
>> 8) | 0xff000000UL
;
4937 store_reg32(r1
, tmp32_1
);
4938 set_cc_icm(s
, tmp32_3
, tmp32_4
);
4939 tcg_temp_free_i64(tmp
);
4940 tcg_temp_free_i64(tmp2
);
4941 tcg_temp_free_i32(tmp32_1
);
4942 tcg_temp_free_i32(tmp32_2
);
4943 tcg_temp_free_i32(tmp32_3
);
4944 tcg_temp_free_i32(tmp32_4
);
4946 /* i.e. env->cc = 0 */
4947 gen_op_movi_cc(s
, 0);
4952 insn
= ld_code6(s
->pc
);
4953 r1
= (insn
>> 36) & 0xf;
4954 op
= (insn
>> 32) & 0xf;
4958 disas_c0(s
, op
, r1
, i2
);
4961 disas_c2(s
, op
, r1
, i2
);
4967 case 0xd2: /* MVC D1(L,B1),D2(B2) [SS] */
4968 case 0xd4: /* NC D1(L,B1),D2(B2) [SS] */
4969 case 0xd5: /* CLC D1(L,B1),D2(B2) [SS] */
4970 case 0xd6: /* OC D1(L,B1),D2(B2) [SS] */
4971 case 0xd7: /* XC D1(L,B1),D2(B2) [SS] */
4972 case 0xdc: /* TR D1(L,B1),D2(B2) [SS] */
4973 case 0xf3: /* UNPK D1(L1,B1),D2(L2,B2) [SS] */
4974 insn
= ld_code6(s
->pc
);
4975 vl
= tcg_const_i32((insn
>> 32) & 0xff);
4976 b1
= (insn
>> 28) & 0xf;
4977 b2
= (insn
>> 12) & 0xf;
4978 d1
= (insn
>> 16) & 0xfff;
4980 tmp
= get_address(s
, 0, b1
, d1
);
4981 tmp2
= get_address(s
, 0, b2
, d2
);
4984 gen_op_mvc(s
, (insn
>> 32) & 0xff, tmp
, tmp2
);
4987 potential_page_fault(s
);
4988 gen_helper_nc(cc_op
, vl
, tmp
, tmp2
);
4992 gen_op_clc(s
, (insn
>> 32) & 0xff, tmp
, tmp2
);
4995 potential_page_fault(s
);
4996 gen_helper_oc(cc_op
, vl
, tmp
, tmp2
);
5000 potential_page_fault(s
);
5001 gen_helper_xc(cc_op
, vl
, tmp
, tmp2
);
5005 potential_page_fault(s
);
5006 gen_helper_tr(vl
, tmp
, tmp2
);
5010 potential_page_fault(s
);
5011 gen_helper_unpk(vl
, tmp
, tmp2
);
5016 tcg_temp_free_i64(tmp
);
5017 tcg_temp_free_i64(tmp2
);
5019 #ifndef CONFIG_USER_ONLY
5020 case 0xda: /* MVCP D1(R1,B1),D2(B2),R3 [SS] */
5021 case 0xdb: /* MVCS D1(R1,B1),D2(B2),R3 [SS] */
5022 check_privileged(s
, ilc
);
5023 potential_page_fault(s
);
5024 insn
= ld_code6(s
->pc
);
5025 r1
= (insn
>> 36) & 0xf;
5026 r3
= (insn
>> 32) & 0xf;
5027 b1
= (insn
>> 28) & 0xf;
5028 d1
= (insn
>> 16) & 0xfff;
5029 b2
= (insn
>> 12) & 0xf;
5033 tmp2
= get_address(s
, 0, b1
, d1
);
5034 tmp3
= get_address(s
, 0, b2
, d2
);
5036 gen_helper_mvcp(cc_op
, tmp
, tmp2
, tmp3
);
5038 gen_helper_mvcs(cc_op
, tmp
, tmp2
, tmp3
);
5041 tcg_temp_free_i64(tmp
);
5042 tcg_temp_free_i64(tmp2
);
5043 tcg_temp_free_i64(tmp3
);
5047 insn
= ld_code6(s
->pc
);
5050 r1
= (insn
>> 36) & 0xf;
5051 x2
= (insn
>> 32) & 0xf;
5052 b2
= (insn
>> 28) & 0xf;
5053 d2
= ((int)((((insn
>> 16) & 0xfff)
5054 | ((insn
<< 4) & 0xff000)) << 12)) >> 12;
5055 disas_e3(s
, op
, r1
, x2
, b2
, d2
);
5057 #ifndef CONFIG_USER_ONLY
5059 /* Test Protection */
5060 check_privileged(s
, ilc
);
5061 insn
= ld_code6(s
->pc
);
5067 insn
= ld_code6(s
->pc
);
5070 r1
= (insn
>> 36) & 0xf;
5071 r3
= (insn
>> 32) & 0xf;
5072 b2
= (insn
>> 28) & 0xf;
5073 d2
= ((int)((((insn
>> 16) & 0xfff)
5074 | ((insn
<< 4) & 0xff000)) << 12)) >> 12;
5075 disas_eb(s
, op
, r1
, r3
, b2
, d2
);
5078 insn
= ld_code6(s
->pc
);
5081 r1
= (insn
>> 36) & 0xf;
5082 x2
= (insn
>> 32) & 0xf;
5083 b2
= (insn
>> 28) & 0xf;
5084 d2
= (short)((insn
>> 16) & 0xfff);
5085 r1b
= (insn
>> 12) & 0xf;
5086 disas_ed(s
, op
, r1
, x2
, b2
, d2
, r1b
);
5089 LOG_DISAS("unimplemented opcode 0x%x\n", opc
);
5090 gen_illegal_opcode(s
, ilc
);
5094 /* Instruction length is encoded in the opcode */
5098 static inline void gen_intermediate_code_internal(CPUState
*env
,
5099 TranslationBlock
*tb
,
5103 target_ulong pc_start
;
5104 uint64_t next_page_start
;
5105 uint16_t *gen_opc_end
;
5107 int num_insns
, max_insns
;
5113 if (!(tb
->flags
& FLAG_MASK_64
)) {
5114 pc_start
&= 0x7fffffff;
5118 dc
.is_jmp
= DISAS_NEXT
;
5120 dc
.cc_op
= CC_OP_DYNAMIC
;
5122 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
5124 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
5127 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
5128 if (max_insns
== 0) {
5129 max_insns
= CF_COUNT_MASK
;
5135 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
5136 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
5137 if (bp
->pc
== dc
.pc
) {
5144 j
= gen_opc_ptr
- gen_opc_buf
;
5148 gen_opc_instr_start
[lj
++] = 0;
5151 gen_opc_pc
[lj
] = dc
.pc
;
5152 gen_opc_cc_op
[lj
] = dc
.cc_op
;
5153 gen_opc_instr_start
[lj
] = 1;
5154 gen_opc_icount
[lj
] = num_insns
;
5156 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
5159 #if defined(S390X_DEBUG_DISAS_VERBOSE)
5160 LOG_DISAS("pc " TARGET_FMT_lx
"\n",
5163 disas_s390_insn(&dc
);
5166 if (env
->singlestep_enabled
) {
5169 } while (!dc
.is_jmp
&& gen_opc_ptr
< gen_opc_end
&& dc
.pc
< next_page_start
5170 && num_insns
< max_insns
&& !env
->singlestep_enabled
5174 update_psw_addr(&dc
);
5177 if (singlestep
&& dc
.cc_op
!= CC_OP_DYNAMIC
) {
5178 gen_op_calc_cc(&dc
);
5180 /* next TB starts off with CC_OP_DYNAMIC, so make sure the cc op type
5182 gen_op_set_cc_op(&dc
);
5185 if (tb
->cflags
& CF_LAST_IO
) {
5188 /* Generate the return instruction */
5189 if (dc
.is_jmp
!= DISAS_TB_JUMP
) {
5192 gen_icount_end(tb
, num_insns
);
5193 *gen_opc_ptr
= INDEX_op_end
;
5195 j
= gen_opc_ptr
- gen_opc_buf
;
5198 gen_opc_instr_start
[lj
++] = 0;
5201 tb
->size
= dc
.pc
- pc_start
;
5202 tb
->icount
= num_insns
;
5204 #if defined(S390X_DEBUG_DISAS)
5205 log_cpu_state_mask(CPU_LOG_TB_CPU
, env
, 0);
5206 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
5207 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
5208 log_target_disas(pc_start
, dc
.pc
- pc_start
, 1);
5214 void gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
5216 gen_intermediate_code_internal(env
, tb
, 0);
5219 void gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
5221 gen_intermediate_code_internal(env
, tb
, 1);
5224 void restore_state_to_opc(CPUState
*env
, TranslationBlock
*tb
, int pc_pos
)
5227 env
->psw
.addr
= gen_opc_pc
[pc_pos
];
5228 cc_op
= gen_opc_cc_op
[pc_pos
];
5229 if ((cc_op
!= CC_OP_DYNAMIC
) && (cc_op
!= CC_OP_STATIC
)) {