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git.proxmox.com Git - qemu.git/blob - target-sh4/op_helper.c
525b0609ccd8478f4ff7bc471d82220cd5ce6bac
4 * Copyright (c) 2005 Samuel Tardieu
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 static void cpu_restore_state_from_retaddr(void *retaddr
)
30 pc
= (unsigned long) retaddr
;
33 /* the PC is inside the translated code. It means that we have
34 a virtual CPU fault */
35 cpu_restore_state(tb
, env
, pc
, NULL
);
40 #ifndef CONFIG_USER_ONLY
42 #define MMUSUFFIX _mmu
45 #include "softmmu_template.h"
48 #include "softmmu_template.h"
51 #include "softmmu_template.h"
54 #include "softmmu_template.h"
56 void tlb_fill(target_ulong addr
, int is_write
, int mmu_idx
, void *retaddr
)
61 /* XXX: hack to restore env in all cases, even if not called from
65 ret
= cpu_sh4_handle_mmu_fault(env
, addr
, is_write
, mmu_idx
, 1);
67 /* now we have a real cpu fault */
68 cpu_restore_state_from_retaddr(retaddr
);
76 void helper_ldtlb(void)
78 #ifdef CONFIG_USER_ONLY
80 cpu_abort(env
, "Unhandled ldtlb");
86 void helper_raise_illegal_instruction(void)
88 env
->exception_index
= 0x180;
92 void helper_raise_slot_illegal_instruction(void)
94 env
->exception_index
= 0x1a0;
98 void helper_raise_fpu_disable(void)
100 env
->exception_index
= 0x800;
104 void helper_raise_slot_fpu_disable(void)
106 env
->exception_index
= 0x820;
110 void helper_debug(void)
112 env
->exception_index
= EXCP_DEBUG
;
116 void helper_sleep(uint32_t next_pc
)
119 env
->exception_index
= EXCP_HLT
;
124 void helper_trapa(uint32_t tra
)
127 env
->exception_index
= 0x160;
131 void helper_movcal(uint32_t address
, uint32_t value
)
133 if (cpu_sh4_is_cached (env
, address
))
135 memory_content
*r
= malloc (sizeof(memory_content
));
136 r
->address
= address
;
140 *(env
->movcal_backup_tail
) = r
;
141 env
->movcal_backup_tail
= &(r
->next
);
145 void helper_discard_movcal_backup(void)
147 memory_content
*current
= env
->movcal_backup
;
151 memory_content
*next
= current
->next
;
153 env
->movcal_backup
= current
= next
;
155 env
->movcal_backup_tail
= &(env
->movcal_backup
);
159 void helper_ocbi(uint32_t address
)
161 memory_content
**current
= &(env
->movcal_backup
);
164 uint32_t a
= (*current
)->address
;
165 if ((a
& ~0x1F) == (address
& ~0x1F))
167 memory_content
*next
= (*current
)->next
;
168 stl(a
, (*current
)->value
);
172 env
->movcal_backup_tail
= current
;
182 uint32_t helper_addc(uint32_t arg0
, uint32_t arg1
)
188 arg1
= tmp1
+ (env
->sr
& 1);
198 uint32_t helper_addv(uint32_t arg0
, uint32_t arg1
)
200 uint32_t dest
, src
, ans
;
202 if ((int32_t) arg1
>= 0)
206 if ((int32_t) arg0
>= 0)
212 if ((int32_t) arg1
>= 0)
217 if (src
== 0 || src
== 2) {
227 #define T (env->sr & SR_T)
228 #define Q (env->sr & SR_Q ? 1 : 0)
229 #define M (env->sr & SR_M ? 1 : 0)
230 #define SETT env->sr |= SR_T
231 #define CLRT env->sr &= ~SR_T
232 #define SETQ env->sr |= SR_Q
233 #define CLRQ env->sr &= ~SR_Q
234 #define SETM env->sr |= SR_M
235 #define CLRM env->sr &= ~SR_M
237 uint32_t helper_div1(uint32_t arg0
, uint32_t arg1
)
240 uint8_t old_q
, tmp1
= 0xff;
242 //printf("div1 arg0=0x%08x arg1=0x%08x M=%d Q=%d T=%d\n", arg0, arg1, M, Q, T);
244 if ((0x80000000 & arg1
) != 0)
341 //printf("Output: arg1=0x%08x M=%d Q=%d T=%d\n", arg1, M, Q, T);
345 void helper_macl(uint32_t arg0
, uint32_t arg1
)
349 res
= ((uint64_t) env
->mach
<< 32) | env
->macl
;
350 res
+= (int64_t) (int32_t) arg0
*(int64_t) (int32_t) arg1
;
351 env
->mach
= (res
>> 32) & 0xffffffff;
352 env
->macl
= res
& 0xffffffff;
353 if (env
->sr
& SR_S
) {
355 env
->mach
|= 0xffff0000;
357 env
->mach
&= 0x00007fff;
361 void helper_macw(uint32_t arg0
, uint32_t arg1
)
365 res
= ((uint64_t) env
->mach
<< 32) | env
->macl
;
366 res
+= (int64_t) (int16_t) arg0
*(int64_t) (int16_t) arg1
;
367 env
->mach
= (res
>> 32) & 0xffffffff;
368 env
->macl
= res
& 0xffffffff;
369 if (env
->sr
& SR_S
) {
370 if (res
< -0x80000000) {
372 env
->macl
= 0x80000000;
373 } else if (res
> 0x000000007fffffff) {
375 env
->macl
= 0x7fffffff;
380 uint32_t helper_negc(uint32_t arg
)
385 arg
= temp
- (env
->sr
& SR_T
);
395 uint32_t helper_subc(uint32_t arg0
, uint32_t arg1
)
401 arg1
= tmp1
- (env
->sr
& SR_T
);
411 uint32_t helper_subv(uint32_t arg0
, uint32_t arg1
)
413 int32_t dest
, src
, ans
;
415 if ((int32_t) arg1
>= 0)
419 if ((int32_t) arg0
>= 0)
425 if ((int32_t) arg1
>= 0)
440 static inline void set_t(void)
445 static inline void clr_t(void)
450 void helper_ld_fpscr(uint32_t val
)
452 env
->fpscr
= val
& FPSCR_MASK
;
453 if ((val
& FPSCR_RM_MASK
) == FPSCR_RM_ZERO
) {
454 set_float_rounding_mode(float_round_to_zero
, &env
->fp_status
);
456 set_float_rounding_mode(float_round_nearest_even
, &env
->fp_status
);
458 set_flush_to_zero((val
& FPSCR_DN
) != 0, &env
->fp_status
);
461 static void update_fpscr(void *retaddr
)
463 int xcpt
, cause
, enable
;
465 xcpt
= get_float_exception_flags(&env
->fp_status
);
467 /* Clear the flag entries */
468 env
->fpscr
&= ~FPSCR_FLAG_MASK
;
470 if (unlikely(xcpt
)) {
471 if (xcpt
& float_flag_invalid
) {
472 env
->fpscr
|= FPSCR_FLAG_V
;
474 if (xcpt
& float_flag_divbyzero
) {
475 env
->fpscr
|= FPSCR_FLAG_Z
;
477 if (xcpt
& float_flag_overflow
) {
478 env
->fpscr
|= FPSCR_FLAG_O
;
480 if (xcpt
& float_flag_underflow
) {
481 env
->fpscr
|= FPSCR_FLAG_U
;
483 if (xcpt
& float_flag_inexact
) {
484 env
->fpscr
|= FPSCR_FLAG_I
;
487 /* Accumulate in cause entries */
488 env
->fpscr
|= (env
->fpscr
& FPSCR_FLAG_MASK
)
489 << (FPSCR_CAUSE_SHIFT
- FPSCR_FLAG_SHIFT
);
491 /* Generate an exception if enabled */
492 cause
= (env
->fpscr
& FPSCR_CAUSE_MASK
) >> FPSCR_CAUSE_SHIFT
;
493 enable
= (env
->fpscr
& FPSCR_ENABLE_MASK
) >> FPSCR_ENABLE_SHIFT
;
494 if (cause
& enable
) {
495 cpu_restore_state_from_retaddr(retaddr
);
496 env
->exception_index
= 0x120;
502 uint32_t helper_fabs_FT(uint32_t t0
)
506 f
.f
= float32_abs(f
.f
);
510 uint64_t helper_fabs_DT(uint64_t t0
)
514 d
.d
= float64_abs(d
.d
);
518 uint32_t helper_fadd_FT(uint32_t t0
, uint32_t t1
)
523 set_float_exception_flags(0, &env
->fp_status
);
524 f0
.f
= float32_add(f0
.f
, f1
.f
, &env
->fp_status
);
525 update_fpscr(GETPC());
529 uint64_t helper_fadd_DT(uint64_t t0
, uint64_t t1
)
534 set_float_exception_flags(0, &env
->fp_status
);
535 d0
.d
= float64_add(d0
.d
, d1
.d
, &env
->fp_status
);
536 update_fpscr(GETPC());
540 void helper_fcmp_eq_FT(uint32_t t0
, uint32_t t1
)
547 set_float_exception_flags(0, &env
->fp_status
);
548 relation
= float32_compare(f0
.f
, f1
.f
, &env
->fp_status
);
549 if (unlikely(relation
== float_relation_unordered
)) {
550 update_fpscr(GETPC());
551 } else if (relation
== float_relation_equal
) {
558 void helper_fcmp_eq_DT(uint64_t t0
, uint64_t t1
)
565 set_float_exception_flags(0, &env
->fp_status
);
566 relation
= float64_compare(d0
.d
, d1
.d
, &env
->fp_status
);
567 if (unlikely(relation
== float_relation_unordered
)) {
568 update_fpscr(GETPC());
569 } else if (relation
== float_relation_equal
) {
576 void helper_fcmp_gt_FT(uint32_t t0
, uint32_t t1
)
583 set_float_exception_flags(0, &env
->fp_status
);
584 relation
= float32_compare(f0
.f
, f1
.f
, &env
->fp_status
);
585 if (unlikely(relation
== float_relation_unordered
)) {
586 update_fpscr(GETPC());
587 } else if (relation
== float_relation_greater
) {
594 void helper_fcmp_gt_DT(uint64_t t0
, uint64_t t1
)
601 set_float_exception_flags(0, &env
->fp_status
);
602 relation
= float64_compare(d0
.d
, d1
.d
, &env
->fp_status
);
603 if (unlikely(relation
== float_relation_unordered
)) {
604 update_fpscr(GETPC());
605 } else if (relation
== float_relation_greater
) {
612 uint64_t helper_fcnvsd_FT_DT(uint32_t t0
)
617 set_float_exception_flags(0, &env
->fp_status
);
618 d
.d
= float32_to_float64(f
.f
, &env
->fp_status
);
619 update_fpscr(GETPC());
623 uint32_t helper_fcnvds_DT_FT(uint64_t t0
)
628 set_float_exception_flags(0, &env
->fp_status
);
629 f
.f
= float64_to_float32(d
.d
, &env
->fp_status
);
630 update_fpscr(GETPC());
634 uint32_t helper_fdiv_FT(uint32_t t0
, uint32_t t1
)
639 set_float_exception_flags(0, &env
->fp_status
);
640 f0
.f
= float32_div(f0
.f
, f1
.f
, &env
->fp_status
);
641 update_fpscr(GETPC());
645 uint64_t helper_fdiv_DT(uint64_t t0
, uint64_t t1
)
650 set_float_exception_flags(0, &env
->fp_status
);
651 d0
.d
= float64_div(d0
.d
, d1
.d
, &env
->fp_status
);
652 update_fpscr(GETPC());
656 uint32_t helper_float_FT(uint32_t t0
)
660 set_float_exception_flags(0, &env
->fp_status
);
661 f
.f
= int32_to_float32(t0
, &env
->fp_status
);
662 update_fpscr(GETPC());
667 uint64_t helper_float_DT(uint32_t t0
)
670 set_float_exception_flags(0, &env
->fp_status
);
671 d
.d
= int32_to_float64(t0
, &env
->fp_status
);
672 update_fpscr(GETPC());
676 uint32_t helper_fmac_FT(uint32_t t0
, uint32_t t1
, uint32_t t2
)
678 CPU_FloatU f0
, f1
, f2
;
682 set_float_exception_flags(0, &env
->fp_status
);
683 f0
.f
= float32_mul(f0
.f
, f1
.f
, &env
->fp_status
);
684 f0
.f
= float32_add(f0
.f
, f2
.f
, &env
->fp_status
);
685 update_fpscr(GETPC());
690 uint32_t helper_fmul_FT(uint32_t t0
, uint32_t t1
)
695 set_float_exception_flags(0, &env
->fp_status
);
696 f0
.f
= float32_mul(f0
.f
, f1
.f
, &env
->fp_status
);
697 update_fpscr(GETPC());
701 uint64_t helper_fmul_DT(uint64_t t0
, uint64_t t1
)
706 set_float_exception_flags(0, &env
->fp_status
);
707 d0
.d
= float64_mul(d0
.d
, d1
.d
, &env
->fp_status
);
708 update_fpscr(GETPC());
713 uint32_t helper_fneg_T(uint32_t t0
)
717 f
.f
= float32_chs(f
.f
);
721 uint32_t helper_fsqrt_FT(uint32_t t0
)
725 set_float_exception_flags(0, &env
->fp_status
);
726 f
.f
= float32_sqrt(f
.f
, &env
->fp_status
);
727 update_fpscr(GETPC());
731 uint64_t helper_fsqrt_DT(uint64_t t0
)
735 set_float_exception_flags(0, &env
->fp_status
);
736 d
.d
= float64_sqrt(d
.d
, &env
->fp_status
);
737 update_fpscr(GETPC());
741 uint32_t helper_fsub_FT(uint32_t t0
, uint32_t t1
)
746 set_float_exception_flags(0, &env
->fp_status
);
747 f0
.f
= float32_sub(f0
.f
, f1
.f
, &env
->fp_status
);
748 update_fpscr(GETPC());
752 uint64_t helper_fsub_DT(uint64_t t0
, uint64_t t1
)
758 set_float_exception_flags(0, &env
->fp_status
);
759 d0
.d
= float64_sub(d0
.d
, d1
.d
, &env
->fp_status
);
760 update_fpscr(GETPC());
764 uint32_t helper_ftrc_FT(uint32_t t0
)
769 set_float_exception_flags(0, &env
->fp_status
);
770 ret
= float32_to_int32_round_to_zero(f
.f
, &env
->fp_status
);
771 update_fpscr(GETPC());
775 uint32_t helper_ftrc_DT(uint64_t t0
)
780 set_float_exception_flags(0, &env
->fp_status
);
781 ret
= float64_to_int32_round_to_zero(d
.d
, &env
->fp_status
);
782 update_fpscr(GETPC());
786 void helper_fipr(uint32_t m
, uint32_t n
)
791 bank
= (env
->sr
& FPSCR_FR
) ? 16 : 0;
793 set_float_exception_flags(0, &env
->fp_status
);
795 for (i
= 0 ; i
< 4 ; i
++) {
796 p
= float32_mul(env
->fregs
[bank
+ m
+ i
],
797 env
->fregs
[bank
+ n
+ i
],
799 r
= float32_add(r
, p
, &env
->fp_status
);
801 update_fpscr(GETPC());
803 env
->fregs
[bank
+ n
+ 3] = r
;
806 void helper_ftrv(uint32_t n
)
808 int bank_matrix
, bank_vector
;
813 bank_matrix
= (env
->sr
& FPSCR_FR
) ? 0 : 16;
814 bank_vector
= (env
->sr
& FPSCR_FR
) ? 16 : 0;
815 set_float_exception_flags(0, &env
->fp_status
);
816 for (i
= 0 ; i
< 4 ; i
++) {
818 for (j
= 0 ; j
< 4 ; j
++) {
819 p
= float32_mul(env
->fregs
[bank_matrix
+ 4 * j
+ i
],
820 env
->fregs
[bank_vector
+ j
],
822 r
[i
] = float32_add(r
[i
], p
, &env
->fp_status
);
825 update_fpscr(GETPC());
827 for (i
= 0 ; i
< 4 ; i
++) {
828 env
->fregs
[bank_vector
+ i
] = r
[i
];