4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
26 #include "qemu-common.h"
29 //#define DEBUG_FEATURES
32 #define DPRINTF_MMU(fmt, ...) \
33 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
35 #define DPRINTF_MMU(fmt, ...) do {} while (0)
38 static int cpu_sparc_find_by_name(sparc_def_t
*cpu_def
, const char *cpu_model
);
40 /* Sparc MMU emulation */
42 #if defined(CONFIG_USER_ONLY)
44 int cpu_sparc_handle_mmu_fault(CPUState
*env1
, target_ulong address
, int rw
,
45 int mmu_idx
, int is_softmmu
)
48 env1
->exception_index
= TT_TFAULT
;
50 env1
->exception_index
= TT_DFAULT
;
56 #ifndef TARGET_SPARC64
58 * Sparc V8 Reference MMU (SRMMU)
60 static const int access_table
[8][8] = {
61 { 0, 0, 0, 0, 8, 0, 12, 12 },
62 { 0, 0, 0, 0, 8, 0, 0, 0 },
63 { 8, 8, 0, 0, 0, 8, 12, 12 },
64 { 8, 8, 0, 0, 0, 8, 0, 0 },
65 { 8, 0, 8, 0, 8, 8, 12, 12 },
66 { 8, 0, 8, 0, 8, 0, 8, 0 },
67 { 8, 8, 8, 0, 8, 8, 12, 12 },
68 { 8, 8, 8, 0, 8, 8, 8, 0 }
71 static const int perm_table
[2][8] = {
74 PAGE_READ
| PAGE_WRITE
,
75 PAGE_READ
| PAGE_EXEC
,
76 PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
,
78 PAGE_READ
| PAGE_WRITE
,
79 PAGE_READ
| PAGE_EXEC
,
80 PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
84 PAGE_READ
| PAGE_WRITE
,
85 PAGE_READ
| PAGE_EXEC
,
86 PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
,
94 static int get_physical_address(CPUState
*env
, target_phys_addr_t
*physical
,
95 int *prot
, int *access_index
,
96 target_ulong address
, int rw
, int mmu_idx
,
97 target_ulong
*page_size
)
100 target_phys_addr_t pde_ptr
;
102 int error_code
= 0, is_dirty
, is_user
;
103 unsigned long page_offset
;
105 is_user
= mmu_idx
== MMU_USER_IDX
;
107 if ((env
->mmuregs
[0] & MMU_E
) == 0) { /* MMU disabled */
108 *page_size
= TARGET_PAGE_SIZE
;
109 // Boot mode: instruction fetches are taken from PROM
110 if (rw
== 2 && (env
->mmuregs
[0] & env
->def
->mmu_bm
)) {
111 *physical
= env
->prom_addr
| (address
& 0x7ffffULL
);
112 *prot
= PAGE_READ
| PAGE_EXEC
;
116 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
120 *access_index
= ((rw
& 1) << 2) | (rw
& 2) | (is_user
? 0 : 1);
121 *physical
= 0xffffffffffff0000ULL
;
123 /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
124 /* Context base + context number */
125 pde_ptr
= (env
->mmuregs
[1] << 4) + (env
->mmuregs
[2] << 2);
126 pde
= ldl_phys(pde_ptr
);
129 switch (pde
& PTE_ENTRYTYPE_MASK
) {
131 case 0: /* Invalid */
133 case 2: /* L0 PTE, maybe should not happen? */
134 case 3: /* Reserved */
137 pde_ptr
= ((address
>> 22) & ~3) + ((pde
& ~3) << 4);
138 pde
= ldl_phys(pde_ptr
);
140 switch (pde
& PTE_ENTRYTYPE_MASK
) {
142 case 0: /* Invalid */
143 return (1 << 8) | (1 << 2);
144 case 3: /* Reserved */
145 return (1 << 8) | (4 << 2);
147 pde_ptr
= ((address
& 0xfc0000) >> 16) + ((pde
& ~3) << 4);
148 pde
= ldl_phys(pde_ptr
);
150 switch (pde
& PTE_ENTRYTYPE_MASK
) {
152 case 0: /* Invalid */
153 return (2 << 8) | (1 << 2);
154 case 3: /* Reserved */
155 return (2 << 8) | (4 << 2);
157 pde_ptr
= ((address
& 0x3f000) >> 10) + ((pde
& ~3) << 4);
158 pde
= ldl_phys(pde_ptr
);
160 switch (pde
& PTE_ENTRYTYPE_MASK
) {
162 case 0: /* Invalid */
163 return (3 << 8) | (1 << 2);
164 case 1: /* PDE, should not happen */
165 case 3: /* Reserved */
166 return (3 << 8) | (4 << 2);
168 page_offset
= (address
& TARGET_PAGE_MASK
) &
169 (TARGET_PAGE_SIZE
- 1);
171 *page_size
= TARGET_PAGE_SIZE
;
174 page_offset
= address
& 0x3ffff;
175 *page_size
= 0x40000;
179 page_offset
= address
& 0xffffff;
180 *page_size
= 0x1000000;
185 access_perms
= (pde
& PTE_ACCESS_MASK
) >> PTE_ACCESS_SHIFT
;
186 error_code
= access_table
[*access_index
][access_perms
];
187 if (error_code
&& !((env
->mmuregs
[0] & MMU_NF
) && is_user
))
190 /* update page modified and dirty bits */
191 is_dirty
= (rw
& 1) && !(pde
& PG_MODIFIED_MASK
);
192 if (!(pde
& PG_ACCESSED_MASK
) || is_dirty
) {
193 pde
|= PG_ACCESSED_MASK
;
195 pde
|= PG_MODIFIED_MASK
;
196 stl_phys_notdirty(pde_ptr
, pde
);
199 /* the page can be put in the TLB */
200 *prot
= perm_table
[is_user
][access_perms
];
201 if (!(pde
& PG_MODIFIED_MASK
)) {
202 /* only set write access if already dirty... otherwise wait
204 *prot
&= ~PAGE_WRITE
;
207 /* Even if large ptes, we map only one 4KB page in the cache to
208 avoid filling it too fast */
209 *physical
= ((target_phys_addr_t
)(pde
& PTE_ADDR_MASK
) << 4) + page_offset
;
213 /* Perform address translation */
214 int cpu_sparc_handle_mmu_fault (CPUState
*env
, target_ulong address
, int rw
,
215 int mmu_idx
, int is_softmmu
)
217 target_phys_addr_t paddr
;
219 target_ulong page_size
;
220 int error_code
= 0, prot
, access_index
;
222 error_code
= get_physical_address(env
, &paddr
, &prot
, &access_index
,
223 address
, rw
, mmu_idx
, &page_size
);
224 if (error_code
== 0) {
225 vaddr
= address
& TARGET_PAGE_MASK
;
226 paddr
&= TARGET_PAGE_MASK
;
228 printf("Translate at " TARGET_FMT_lx
" -> " TARGET_FMT_plx
", vaddr "
229 TARGET_FMT_lx
"\n", address
, paddr
, vaddr
);
231 tlb_set_page(env
, vaddr
, paddr
, prot
, mmu_idx
, page_size
);
235 if (env
->mmuregs
[3]) /* Fault status register */
236 env
->mmuregs
[3] = 1; /* overflow (not read before another fault) */
237 env
->mmuregs
[3] |= (access_index
<< 5) | error_code
| 2;
238 env
->mmuregs
[4] = address
; /* Fault address register */
240 if ((env
->mmuregs
[0] & MMU_NF
) || env
->psret
== 0) {
241 // No fault mode: if a mapping is available, just override
242 // permissions. If no mapping is available, redirect accesses to
243 // neverland. Fake/overridden mappings will be flushed when
244 // switching to normal mode.
245 vaddr
= address
& TARGET_PAGE_MASK
;
246 prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
247 tlb_set_page(env
, vaddr
, paddr
, prot
, mmu_idx
, TARGET_PAGE_SIZE
);
251 env
->exception_index
= TT_TFAULT
;
253 env
->exception_index
= TT_DFAULT
;
258 target_ulong
mmu_probe(CPUState
*env
, target_ulong address
, int mmulev
)
260 target_phys_addr_t pde_ptr
;
263 /* Context base + context number */
264 pde_ptr
= (target_phys_addr_t
)(env
->mmuregs
[1] << 4) +
265 (env
->mmuregs
[2] << 2);
266 pde
= ldl_phys(pde_ptr
);
268 switch (pde
& PTE_ENTRYTYPE_MASK
) {
270 case 0: /* Invalid */
271 case 2: /* PTE, maybe should not happen? */
272 case 3: /* Reserved */
277 pde_ptr
= ((address
>> 22) & ~3) + ((pde
& ~3) << 4);
278 pde
= ldl_phys(pde_ptr
);
280 switch (pde
& PTE_ENTRYTYPE_MASK
) {
282 case 0: /* Invalid */
283 case 3: /* Reserved */
290 pde_ptr
= ((address
& 0xfc0000) >> 16) + ((pde
& ~3) << 4);
291 pde
= ldl_phys(pde_ptr
);
293 switch (pde
& PTE_ENTRYTYPE_MASK
) {
295 case 0: /* Invalid */
296 case 3: /* Reserved */
303 pde_ptr
= ((address
& 0x3f000) >> 10) + ((pde
& ~3) << 4);
304 pde
= ldl_phys(pde_ptr
);
306 switch (pde
& PTE_ENTRYTYPE_MASK
) {
308 case 0: /* Invalid */
309 case 1: /* PDE, should not happen */
310 case 3: /* Reserved */
321 void dump_mmu(FILE *f
, fprintf_function cpu_fprintf
, CPUState
*env
)
323 target_ulong va
, va1
, va2
;
324 unsigned int n
, m
, o
;
325 target_phys_addr_t pde_ptr
, pa
;
328 pde_ptr
= (env
->mmuregs
[1] << 4) + (env
->mmuregs
[2] << 2);
329 pde
= ldl_phys(pde_ptr
);
330 (*cpu_fprintf
)(f
, "Root ptr: " TARGET_FMT_plx
", ctx: %d\n",
331 (target_phys_addr_t
)env
->mmuregs
[1] << 4, env
->mmuregs
[2]);
332 for (n
= 0, va
= 0; n
< 256; n
++, va
+= 16 * 1024 * 1024) {
333 pde
= mmu_probe(env
, va
, 2);
335 pa
= cpu_get_phys_page_debug(env
, va
);
336 (*cpu_fprintf
)(f
, "VA: " TARGET_FMT_lx
", PA: " TARGET_FMT_plx
337 " PDE: " TARGET_FMT_lx
"\n", va
, pa
, pde
);
338 for (m
= 0, va1
= va
; m
< 64; m
++, va1
+= 256 * 1024) {
339 pde
= mmu_probe(env
, va1
, 1);
341 pa
= cpu_get_phys_page_debug(env
, va1
);
342 (*cpu_fprintf
)(f
, " VA: " TARGET_FMT_lx
", PA: "
343 TARGET_FMT_plx
" PDE: " TARGET_FMT_lx
"\n",
345 for (o
= 0, va2
= va1
; o
< 64; o
++, va2
+= 4 * 1024) {
346 pde
= mmu_probe(env
, va2
, 0);
348 pa
= cpu_get_phys_page_debug(env
, va2
);
349 (*cpu_fprintf
)(f
, " VA: " TARGET_FMT_lx
", PA: "
350 TARGET_FMT_plx
" PTE: "
361 #else /* !TARGET_SPARC64 */
363 // 41 bit physical address space
364 static inline target_phys_addr_t
ultrasparc_truncate_physical(uint64_t x
)
366 return x
& 0x1ffffffffffULL
;
370 * UltraSparc IIi I/DMMUs
373 // Returns true if TTE tag is valid and matches virtual address value in context
374 // requires virtual address mask value calculated from TTE entry size
375 static inline int ultrasparc_tag_match(SparcTLBEntry
*tlb
,
376 uint64_t address
, uint64_t context
,
377 target_phys_addr_t
*physical
)
381 switch ((tlb
->tte
>> 61) & 3) {
384 mask
= 0xffffffffffffe000ULL
;
387 mask
= 0xffffffffffff0000ULL
;
390 mask
= 0xfffffffffff80000ULL
;
393 mask
= 0xffffffffffc00000ULL
;
397 // valid, context match, virtual address match?
398 if (TTE_IS_VALID(tlb
->tte
) &&
399 (TTE_IS_GLOBAL(tlb
->tte
) || tlb_compare_context(tlb
, context
))
400 && compare_masked(address
, tlb
->tag
, mask
))
402 // decode physical address
403 *physical
= ((tlb
->tte
& mask
) | (address
& ~mask
)) & 0x1ffffffe000ULL
;
410 static int get_physical_address_data(CPUState
*env
,
411 target_phys_addr_t
*physical
, int *prot
,
412 target_ulong address
, int rw
, int mmu_idx
)
417 int is_user
= (mmu_idx
== MMU_USER_IDX
||
418 mmu_idx
== MMU_USER_SECONDARY_IDX
);
420 if ((env
->lsu
& DMMU_E
) == 0) { /* DMMU disabled */
421 *physical
= ultrasparc_truncate_physical(address
);
422 *prot
= PAGE_READ
| PAGE_WRITE
;
429 context
= env
->dmmu
.mmu_primary_context
& 0x1fff;
431 case MMU_USER_SECONDARY_IDX
:
432 case MMU_KERNEL_SECONDARY_IDX
:
433 context
= env
->dmmu
.mmu_secondary_context
& 0x1fff;
435 case MMU_NUCLEUS_IDX
:
441 for (i
= 0; i
< 64; i
++) {
442 // ctx match, vaddr match, valid?
443 if (ultrasparc_tag_match(&env
->dtlb
[i
], address
, context
, physical
)) {
445 uint8_t fault_type
= 0;
448 if ((env
->dtlb
[i
].tte
& 0x4) && is_user
) {
449 fault_type
|= 1; /* privilege violation */
450 env
->exception_index
= TT_DFAULT
;
452 DPRINTF_MMU("DFAULT at %" PRIx64
" context %" PRIx64
453 " mmu_idx=%d tl=%d\n",
454 address
, context
, mmu_idx
, env
->tl
);
455 } else if (!(env
->dtlb
[i
].tte
& 0x2) && (rw
== 1)) {
456 env
->exception_index
= TT_DPROT
;
458 DPRINTF_MMU("DPROT at %" PRIx64
" context %" PRIx64
459 " mmu_idx=%d tl=%d\n",
460 address
, context
, mmu_idx
, env
->tl
);
463 if (env
->dtlb
[i
].tte
& 0x2)
466 TTE_SET_USED(env
->dtlb
[i
].tte
);
471 if (env
->dmmu
.sfsr
& 1) /* Fault status register */
472 env
->dmmu
.sfsr
= 2; /* overflow (not read before
475 env
->dmmu
.sfsr
|= (is_user
<< 3) | ((rw
== 1) << 2) | 1;
477 env
->dmmu
.sfsr
|= (fault_type
<< 7);
479 env
->dmmu
.sfar
= address
; /* Fault address register */
481 env
->dmmu
.tag_access
= (address
& ~0x1fffULL
) | context
;
487 DPRINTF_MMU("DMISS at %" PRIx64
" context %" PRIx64
"\n",
490 env
->dmmu
.tag_access
= (address
& ~0x1fffULL
) | context
;
491 env
->exception_index
= TT_DMISS
;
495 static int get_physical_address_code(CPUState
*env
,
496 target_phys_addr_t
*physical
, int *prot
,
497 target_ulong address
, int mmu_idx
)
502 int is_user
= (mmu_idx
== MMU_USER_IDX
||
503 mmu_idx
== MMU_USER_SECONDARY_IDX
);
505 if ((env
->lsu
& IMMU_E
) == 0 || (env
->pstate
& PS_RED
) != 0) {
507 *physical
= ultrasparc_truncate_physical(address
);
513 /* PRIMARY context */
514 context
= env
->dmmu
.mmu_primary_context
& 0x1fff;
516 /* NUCLEUS context */
520 for (i
= 0; i
< 64; i
++) {
521 // ctx match, vaddr match, valid?
522 if (ultrasparc_tag_match(&env
->itlb
[i
],
523 address
, context
, physical
)) {
525 if ((env
->itlb
[i
].tte
& 0x4) && is_user
) {
526 if (env
->immu
.sfsr
) /* Fault status register */
527 env
->immu
.sfsr
= 2; /* overflow (not read before
529 env
->immu
.sfsr
|= (is_user
<< 3) | 1;
530 env
->exception_index
= TT_TFAULT
;
532 env
->immu
.tag_access
= (address
& ~0x1fffULL
) | context
;
534 DPRINTF_MMU("TFAULT at %" PRIx64
" context %" PRIx64
"\n",
540 TTE_SET_USED(env
->itlb
[i
].tte
);
545 DPRINTF_MMU("TMISS at %" PRIx64
" context %" PRIx64
"\n",
548 /* Context is stored in DMMU (dmmuregs[1]) also for IMMU */
549 env
->immu
.tag_access
= (address
& ~0x1fffULL
) | context
;
550 env
->exception_index
= TT_TMISS
;
554 static int get_physical_address(CPUState
*env
, target_phys_addr_t
*physical
,
555 int *prot
, int *access_index
,
556 target_ulong address
, int rw
, int mmu_idx
,
557 target_ulong
*page_size
)
559 /* ??? We treat everything as a small page, then explicitly flush
560 everything when an entry is evicted. */
561 *page_size
= TARGET_PAGE_SIZE
;
563 #if defined (DEBUG_MMU)
564 /* safety net to catch wrong softmmu index use from dynamic code */
565 if (env
->tl
> 0 && mmu_idx
!= MMU_NUCLEUS_IDX
) {
566 DPRINTF_MMU("get_physical_address %s tl=%d mmu_idx=%d"
567 " primary context=%" PRIx64
568 " secondary context=%" PRIx64
571 (rw
== 2 ? "CODE" : "DATA"),
573 env
->dmmu
.mmu_primary_context
,
574 env
->dmmu
.mmu_secondary_context
,
580 return get_physical_address_code(env
, physical
, prot
, address
,
583 return get_physical_address_data(env
, physical
, prot
, address
, rw
,
587 /* Perform address translation */
588 int cpu_sparc_handle_mmu_fault (CPUState
*env
, target_ulong address
, int rw
,
589 int mmu_idx
, int is_softmmu
)
591 target_ulong virt_addr
, vaddr
;
592 target_phys_addr_t paddr
;
593 target_ulong page_size
;
594 int error_code
= 0, prot
, access_index
;
596 error_code
= get_physical_address(env
, &paddr
, &prot
, &access_index
,
597 address
, rw
, mmu_idx
, &page_size
);
598 if (error_code
== 0) {
599 virt_addr
= address
& TARGET_PAGE_MASK
;
600 vaddr
= virt_addr
+ ((address
& TARGET_PAGE_MASK
) &
601 (TARGET_PAGE_SIZE
- 1));
603 DPRINTF_MMU("Translate at %" PRIx64
" -> %" PRIx64
","
607 " primary context=%" PRIx64
608 " secondary context=%" PRIx64
610 address
, paddr
, vaddr
, mmu_idx
, env
->tl
,
611 env
->dmmu
.mmu_primary_context
,
612 env
->dmmu
.mmu_secondary_context
);
614 tlb_set_page(env
, vaddr
, paddr
, prot
, mmu_idx
, page_size
);
621 void dump_mmu(FILE *f
, fprintf_function cpu_fprintf
, CPUState
*env
)
626 (*cpu_fprintf
)(f
, "MMU contexts: Primary: %" PRId64
", Secondary: %"
628 env
->dmmu
.mmu_primary_context
,
629 env
->dmmu
.mmu_secondary_context
);
630 if ((env
->lsu
& DMMU_E
) == 0) {
631 (*cpu_fprintf
)(f
, "DMMU disabled\n");
633 (*cpu_fprintf
)(f
, "DMMU dump\n");
634 for (i
= 0; i
< 64; i
++) {
635 switch ((env
->dtlb
[i
].tte
>> 61) & 3) {
650 if ((env
->dtlb
[i
].tte
& 0x8000000000000000ULL
) != 0) {
651 (*cpu_fprintf
)(f
, "[%02u] VA: %" PRIx64
", PA: %" PRIx64
652 ", %s, %s, %s, %s, ctx %" PRId64
" %s\n",
654 env
->dtlb
[i
].tag
& (uint64_t)~0x1fffULL
,
655 env
->dtlb
[i
].tte
& (uint64_t)0x1ffffffe000ULL
,
657 env
->dtlb
[i
].tte
& 0x4? "priv": "user",
658 env
->dtlb
[i
].tte
& 0x2? "RW": "RO",
659 env
->dtlb
[i
].tte
& 0x40? "locked": "unlocked",
660 env
->dtlb
[i
].tag
& (uint64_t)0x1fffULL
,
661 TTE_IS_GLOBAL(env
->dtlb
[i
].tte
)?
666 if ((env
->lsu
& IMMU_E
) == 0) {
667 (*cpu_fprintf
)(f
, "IMMU disabled\n");
669 (*cpu_fprintf
)(f
, "IMMU dump\n");
670 for (i
= 0; i
< 64; i
++) {
671 switch ((env
->itlb
[i
].tte
>> 61) & 3) {
686 if ((env
->itlb
[i
].tte
& 0x8000000000000000ULL
) != 0) {
687 (*cpu_fprintf
)(f
, "[%02u] VA: %" PRIx64
", PA: %" PRIx64
688 ", %s, %s, %s, ctx %" PRId64
" %s\n",
690 env
->itlb
[i
].tag
& (uint64_t)~0x1fffULL
,
691 env
->itlb
[i
].tte
& (uint64_t)0x1ffffffe000ULL
,
693 env
->itlb
[i
].tte
& 0x4? "priv": "user",
694 env
->itlb
[i
].tte
& 0x40? "locked": "unlocked",
695 env
->itlb
[i
].tag
& (uint64_t)0x1fffULL
,
696 TTE_IS_GLOBAL(env
->itlb
[i
].tte
)?
703 #endif /* TARGET_SPARC64 */
704 #endif /* !CONFIG_USER_ONLY */
707 #if !defined(CONFIG_USER_ONLY)
708 target_phys_addr_t
cpu_get_phys_page_nofault(CPUState
*env
, target_ulong addr
,
711 target_phys_addr_t phys_addr
;
712 target_ulong page_size
;
713 int prot
, access_index
;
715 if (get_physical_address(env
, &phys_addr
, &prot
, &access_index
, addr
, 2,
716 mmu_idx
, &page_size
) != 0)
717 if (get_physical_address(env
, &phys_addr
, &prot
, &access_index
, addr
,
718 0, mmu_idx
, &page_size
) != 0)
720 if (cpu_get_physical_page_desc(phys_addr
) == IO_MEM_UNASSIGNED
)
725 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
727 return cpu_get_phys_page_nofault(env
, addr
, cpu_mmu_index(env
));
731 #ifdef TARGET_SPARC64
733 static const char * const excp_names
[0x80] = {
734 [TT_TFAULT
] = "Instruction Access Fault",
735 [TT_TMISS
] = "Instruction Access MMU Miss",
736 [TT_CODE_ACCESS
] = "Instruction Access Error",
737 [TT_ILL_INSN
] = "Illegal Instruction",
738 [TT_PRIV_INSN
] = "Privileged Instruction",
739 [TT_NFPU_INSN
] = "FPU Disabled",
740 [TT_FP_EXCP
] = "FPU Exception",
741 [TT_TOVF
] = "Tag Overflow",
742 [TT_CLRWIN
] = "Clean Windows",
743 [TT_DIV_ZERO
] = "Division By Zero",
744 [TT_DFAULT
] = "Data Access Fault",
745 [TT_DMISS
] = "Data Access MMU Miss",
746 [TT_DATA_ACCESS
] = "Data Access Error",
747 [TT_DPROT
] = "Data Protection Error",
748 [TT_UNALIGNED
] = "Unaligned Memory Access",
749 [TT_PRIV_ACT
] = "Privileged Action",
750 [TT_EXTINT
| 0x1] = "External Interrupt 1",
751 [TT_EXTINT
| 0x2] = "External Interrupt 2",
752 [TT_EXTINT
| 0x3] = "External Interrupt 3",
753 [TT_EXTINT
| 0x4] = "External Interrupt 4",
754 [TT_EXTINT
| 0x5] = "External Interrupt 5",
755 [TT_EXTINT
| 0x6] = "External Interrupt 6",
756 [TT_EXTINT
| 0x7] = "External Interrupt 7",
757 [TT_EXTINT
| 0x8] = "External Interrupt 8",
758 [TT_EXTINT
| 0x9] = "External Interrupt 9",
759 [TT_EXTINT
| 0xa] = "External Interrupt 10",
760 [TT_EXTINT
| 0xb] = "External Interrupt 11",
761 [TT_EXTINT
| 0xc] = "External Interrupt 12",
762 [TT_EXTINT
| 0xd] = "External Interrupt 13",
763 [TT_EXTINT
| 0xe] = "External Interrupt 14",
764 [TT_EXTINT
| 0xf] = "External Interrupt 15",
768 void do_interrupt(CPUState
*env
)
770 int intno
= env
->exception_index
;
774 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
778 if (intno
< 0 || intno
>= 0x180) {
780 } else if (intno
>= 0x100) {
781 name
= "Trap Instruction";
782 } else if (intno
>= 0xc0) {
783 name
= "Window Fill";
784 } else if (intno
>= 0x80) {
785 name
= "Window Spill";
787 name
= excp_names
[intno
];
793 qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64
" npc=%016" PRIx64
794 " SP=%016" PRIx64
"\n",
797 env
->npc
, env
->regwptr
[6]);
798 log_cpu_state(env
, 0);
805 ptr
= (uint8_t *)env
->pc
;
806 for (i
= 0; i
< 16; i
++) {
807 qemu_log(" %02x", ldub(ptr
+ i
));
815 #if !defined(CONFIG_USER_ONLY)
816 if (env
->tl
>= env
->maxtl
) {
817 cpu_abort(env
, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
818 " Error state", env
->exception_index
, env
->tl
, env
->maxtl
);
822 if (env
->tl
< env
->maxtl
- 1) {
825 env
->pstate
|= PS_RED
;
826 if (env
->tl
< env
->maxtl
) {
830 tsptr
= cpu_tsptr(env
);
832 tsptr
->tstate
= (cpu_get_ccr(env
) << 32) |
833 ((env
->asi
& 0xff) << 24) | ((env
->pstate
& 0xf3f) << 8) |
835 tsptr
->tpc
= env
->pc
;
836 tsptr
->tnpc
= env
->npc
;
841 cpu_change_pstate(env
, PS_PEF
| PS_PRIV
| PS_IG
);
845 case TT_TMISS
... TT_TMISS
+ 3:
846 case TT_DMISS
... TT_DMISS
+ 3:
847 case TT_DPROT
... TT_DPROT
+ 3:
848 cpu_change_pstate(env
, PS_PEF
| PS_PRIV
| PS_MG
);
851 cpu_change_pstate(env
, PS_PEF
| PS_PRIV
| PS_AG
);
855 if (intno
== TT_CLRWIN
) {
856 cpu_set_cwp(env
, cpu_cwp_dec(env
, env
->cwp
- 1));
857 } else if ((intno
& 0x1c0) == TT_SPILL
) {
858 cpu_set_cwp(env
, cpu_cwp_dec(env
, env
->cwp
- env
->cansave
- 2));
859 } else if ((intno
& 0x1c0) == TT_FILL
) {
860 cpu_set_cwp(env
, cpu_cwp_inc(env
, env
->cwp
+ 1));
862 env
->tbr
&= ~0x7fffULL
;
863 env
->tbr
|= ((env
->tl
> 1) ? 1 << 14 : 0) | (intno
<< 5);
865 env
->npc
= env
->pc
+ 4;
866 env
->exception_index
= -1;
870 static const char * const excp_names
[0x80] = {
871 [TT_TFAULT
] = "Instruction Access Fault",
872 [TT_ILL_INSN
] = "Illegal Instruction",
873 [TT_PRIV_INSN
] = "Privileged Instruction",
874 [TT_NFPU_INSN
] = "FPU Disabled",
875 [TT_WIN_OVF
] = "Window Overflow",
876 [TT_WIN_UNF
] = "Window Underflow",
877 [TT_UNALIGNED
] = "Unaligned Memory Access",
878 [TT_FP_EXCP
] = "FPU Exception",
879 [TT_DFAULT
] = "Data Access Fault",
880 [TT_TOVF
] = "Tag Overflow",
881 [TT_EXTINT
| 0x1] = "External Interrupt 1",
882 [TT_EXTINT
| 0x2] = "External Interrupt 2",
883 [TT_EXTINT
| 0x3] = "External Interrupt 3",
884 [TT_EXTINT
| 0x4] = "External Interrupt 4",
885 [TT_EXTINT
| 0x5] = "External Interrupt 5",
886 [TT_EXTINT
| 0x6] = "External Interrupt 6",
887 [TT_EXTINT
| 0x7] = "External Interrupt 7",
888 [TT_EXTINT
| 0x8] = "External Interrupt 8",
889 [TT_EXTINT
| 0x9] = "External Interrupt 9",
890 [TT_EXTINT
| 0xa] = "External Interrupt 10",
891 [TT_EXTINT
| 0xb] = "External Interrupt 11",
892 [TT_EXTINT
| 0xc] = "External Interrupt 12",
893 [TT_EXTINT
| 0xd] = "External Interrupt 13",
894 [TT_EXTINT
| 0xe] = "External Interrupt 14",
895 [TT_EXTINT
| 0xf] = "External Interrupt 15",
896 [TT_TOVF
] = "Tag Overflow",
897 [TT_CODE_ACCESS
] = "Instruction Access Error",
898 [TT_DATA_ACCESS
] = "Data Access Error",
899 [TT_DIV_ZERO
] = "Division By Zero",
900 [TT_NCP_INSN
] = "Coprocessor Disabled",
904 void do_interrupt(CPUState
*env
)
906 int cwp
, intno
= env
->exception_index
;
909 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
913 if (intno
< 0 || intno
>= 0x100) {
915 } else if (intno
>= 0x80) {
916 name
= "Trap Instruction";
918 name
= excp_names
[intno
];
924 qemu_log("%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
927 env
->npc
, env
->regwptr
[6]);
928 log_cpu_state(env
, 0);
935 ptr
= (uint8_t *)env
->pc
;
936 for (i
= 0; i
< 16; i
++) {
937 qemu_log(" %02x", ldub(ptr
+ i
));
945 #if !defined(CONFIG_USER_ONLY)
946 if (env
->psret
== 0) {
947 cpu_abort(env
, "Trap 0x%02x while interrupts disabled, Error state",
948 env
->exception_index
);
953 cwp
= cpu_cwp_dec(env
, env
->cwp
- 1);
954 cpu_set_cwp(env
, cwp
);
955 env
->regwptr
[9] = env
->pc
;
956 env
->regwptr
[10] = env
->npc
;
957 env
->psrps
= env
->psrs
;
959 env
->tbr
= (env
->tbr
& TBR_BASE_MASK
) | (intno
<< 4);
961 env
->npc
= env
->pc
+ 4;
962 env
->exception_index
= -1;
964 #if !defined(CONFIG_USER_ONLY)
965 /* IRQ acknowledgment */
966 if ((intno
& ~15) == TT_EXTINT
&& env
->qemu_irq_ack
!= NULL
) {
967 env
->qemu_irq_ack(env
->irq_manager
, intno
);
973 void cpu_reset(CPUSPARCState
*env
)
975 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
976 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
977 log_cpu_state(env
, 0);
982 #ifndef TARGET_SPARC64
985 env
->regwptr
= env
->regbase
+ (env
->cwp
* 16);
987 #if defined(CONFIG_USER_ONLY)
988 #ifdef TARGET_SPARC64
989 env
->cleanwin
= env
->nwindows
- 2;
990 env
->cansave
= env
->nwindows
- 2;
991 env
->pstate
= PS_RMO
| PS_PEF
| PS_IE
;
992 env
->asi
= 0x82; // Primary no-fault
995 #if !defined(TARGET_SPARC64)
1000 #ifdef TARGET_SPARC64
1001 env
->pstate
= PS_PRIV
|PS_RED
|PS_PEF
|PS_AG
;
1002 env
->hpstate
= cpu_has_hypervisor(env
) ? HS_PRIV
: 0;
1003 env
->tl
= env
->maxtl
;
1004 cpu_tsptr(env
)->tt
= TT_POWER_ON_RESET
;
1007 env
->mmuregs
[0] &= ~(MMU_E
| MMU_NF
);
1008 env
->mmuregs
[0] |= env
->def
->mmu_bm
;
1011 env
->npc
= env
->pc
+ 4;
1013 env
->cache_control
= 0;
1016 static int cpu_sparc_register(CPUSPARCState
*env
, const char *cpu_model
)
1018 sparc_def_t def1
, *def
= &def1
;
1020 if (cpu_sparc_find_by_name(def
, cpu_model
) < 0)
1023 env
->def
= qemu_mallocz(sizeof(*def
));
1024 memcpy(env
->def
, def
, sizeof(*def
));
1025 #if defined(CONFIG_USER_ONLY)
1026 if ((env
->def
->features
& CPU_FEATURE_FLOAT
))
1027 env
->def
->features
|= CPU_FEATURE_FLOAT128
;
1029 env
->cpu_model_str
= cpu_model
;
1030 env
->version
= def
->iu_version
;
1031 env
->fsr
= def
->fpu_version
;
1032 env
->nwindows
= def
->nwindows
;
1033 #if !defined(TARGET_SPARC64)
1034 env
->mmuregs
[0] |= def
->mmu_version
;
1035 cpu_sparc_set_id(env
, 0);
1036 env
->mxccregs
[7] |= def
->mxcc_version
;
1038 env
->mmu_version
= def
->mmu_version
;
1039 env
->maxtl
= def
->maxtl
;
1040 env
->version
|= def
->maxtl
<< 8;
1041 env
->version
|= def
->nwindows
- 1;
1046 static void cpu_sparc_close(CPUSPARCState
*env
)
1052 CPUSPARCState
*cpu_sparc_init(const char *cpu_model
)
1056 env
= qemu_mallocz(sizeof(CPUSPARCState
));
1059 gen_intermediate_code_init(env
);
1061 if (cpu_sparc_register(env
, cpu_model
) < 0) {
1062 cpu_sparc_close(env
);
1065 qemu_init_vcpu(env
);
1070 void cpu_sparc_set_id(CPUSPARCState
*env
, unsigned int cpu
)
1072 #if !defined(TARGET_SPARC64)
1073 env
->mxccregs
[7] = ((cpu
+ 8) & 0xf) << 24;
1077 static const sparc_def_t sparc_defs
[] = {
1078 #ifdef TARGET_SPARC64
1080 .name
= "Fujitsu Sparc64",
1081 .iu_version
= ((0x04ULL
<< 48) | (0x02ULL
<< 32) | (0ULL << 24)),
1082 .fpu_version
= 0x00000000,
1083 .mmu_version
= mmu_us_12
,
1086 .features
= CPU_DEFAULT_FEATURES
,
1089 .name
= "Fujitsu Sparc64 III",
1090 .iu_version
= ((0x04ULL
<< 48) | (0x03ULL
<< 32) | (0ULL << 24)),
1091 .fpu_version
= 0x00000000,
1092 .mmu_version
= mmu_us_12
,
1095 .features
= CPU_DEFAULT_FEATURES
,
1098 .name
= "Fujitsu Sparc64 IV",
1099 .iu_version
= ((0x04ULL
<< 48) | (0x04ULL
<< 32) | (0ULL << 24)),
1100 .fpu_version
= 0x00000000,
1101 .mmu_version
= mmu_us_12
,
1104 .features
= CPU_DEFAULT_FEATURES
,
1107 .name
= "Fujitsu Sparc64 V",
1108 .iu_version
= ((0x04ULL
<< 48) | (0x05ULL
<< 32) | (0x51ULL
<< 24)),
1109 .fpu_version
= 0x00000000,
1110 .mmu_version
= mmu_us_12
,
1113 .features
= CPU_DEFAULT_FEATURES
,
1116 .name
= "TI UltraSparc I",
1117 .iu_version
= ((0x17ULL
<< 48) | (0x10ULL
<< 32) | (0x40ULL
<< 24)),
1118 .fpu_version
= 0x00000000,
1119 .mmu_version
= mmu_us_12
,
1122 .features
= CPU_DEFAULT_FEATURES
,
1125 .name
= "TI UltraSparc II",
1126 .iu_version
= ((0x17ULL
<< 48) | (0x11ULL
<< 32) | (0x20ULL
<< 24)),
1127 .fpu_version
= 0x00000000,
1128 .mmu_version
= mmu_us_12
,
1131 .features
= CPU_DEFAULT_FEATURES
,
1134 .name
= "TI UltraSparc IIi",
1135 .iu_version
= ((0x17ULL
<< 48) | (0x12ULL
<< 32) | (0x91ULL
<< 24)),
1136 .fpu_version
= 0x00000000,
1137 .mmu_version
= mmu_us_12
,
1140 .features
= CPU_DEFAULT_FEATURES
,
1143 .name
= "TI UltraSparc IIe",
1144 .iu_version
= ((0x17ULL
<< 48) | (0x13ULL
<< 32) | (0x14ULL
<< 24)),
1145 .fpu_version
= 0x00000000,
1146 .mmu_version
= mmu_us_12
,
1149 .features
= CPU_DEFAULT_FEATURES
,
1152 .name
= "Sun UltraSparc III",
1153 .iu_version
= ((0x3eULL
<< 48) | (0x14ULL
<< 32) | (0x34ULL
<< 24)),
1154 .fpu_version
= 0x00000000,
1155 .mmu_version
= mmu_us_12
,
1158 .features
= CPU_DEFAULT_FEATURES
,
1161 .name
= "Sun UltraSparc III Cu",
1162 .iu_version
= ((0x3eULL
<< 48) | (0x15ULL
<< 32) | (0x41ULL
<< 24)),
1163 .fpu_version
= 0x00000000,
1164 .mmu_version
= mmu_us_3
,
1167 .features
= CPU_DEFAULT_FEATURES
,
1170 .name
= "Sun UltraSparc IIIi",
1171 .iu_version
= ((0x3eULL
<< 48) | (0x16ULL
<< 32) | (0x34ULL
<< 24)),
1172 .fpu_version
= 0x00000000,
1173 .mmu_version
= mmu_us_12
,
1176 .features
= CPU_DEFAULT_FEATURES
,
1179 .name
= "Sun UltraSparc IV",
1180 .iu_version
= ((0x3eULL
<< 48) | (0x18ULL
<< 32) | (0x31ULL
<< 24)),
1181 .fpu_version
= 0x00000000,
1182 .mmu_version
= mmu_us_4
,
1185 .features
= CPU_DEFAULT_FEATURES
,
1188 .name
= "Sun UltraSparc IV+",
1189 .iu_version
= ((0x3eULL
<< 48) | (0x19ULL
<< 32) | (0x22ULL
<< 24)),
1190 .fpu_version
= 0x00000000,
1191 .mmu_version
= mmu_us_12
,
1194 .features
= CPU_DEFAULT_FEATURES
| CPU_FEATURE_CMT
,
1197 .name
= "Sun UltraSparc IIIi+",
1198 .iu_version
= ((0x3eULL
<< 48) | (0x22ULL
<< 32) | (0ULL << 24)),
1199 .fpu_version
= 0x00000000,
1200 .mmu_version
= mmu_us_3
,
1203 .features
= CPU_DEFAULT_FEATURES
,
1206 .name
= "Sun UltraSparc T1",
1207 // defined in sparc_ifu_fdp.v and ctu.h
1208 .iu_version
= ((0x3eULL
<< 48) | (0x23ULL
<< 32) | (0x02ULL
<< 24)),
1209 .fpu_version
= 0x00000000,
1210 .mmu_version
= mmu_sun4v
,
1213 .features
= CPU_DEFAULT_FEATURES
| CPU_FEATURE_HYPV
| CPU_FEATURE_CMT
1217 .name
= "Sun UltraSparc T2",
1218 // defined in tlu_asi_ctl.v and n2_revid_cust.v
1219 .iu_version
= ((0x3eULL
<< 48) | (0x24ULL
<< 32) | (0x02ULL
<< 24)),
1220 .fpu_version
= 0x00000000,
1221 .mmu_version
= mmu_sun4v
,
1224 .features
= CPU_DEFAULT_FEATURES
| CPU_FEATURE_HYPV
| CPU_FEATURE_CMT
1228 .name
= "NEC UltraSparc I",
1229 .iu_version
= ((0x22ULL
<< 48) | (0x10ULL
<< 32) | (0x40ULL
<< 24)),
1230 .fpu_version
= 0x00000000,
1231 .mmu_version
= mmu_us_12
,
1234 .features
= CPU_DEFAULT_FEATURES
,
1238 .name
= "Fujitsu MB86900",
1239 .iu_version
= 0x00 << 24, /* Impl 0, ver 0 */
1240 .fpu_version
= 4 << 17, /* FPU version 4 (Meiko) */
1241 .mmu_version
= 0x00 << 24, /* Impl 0, ver 0 */
1242 .mmu_bm
= 0x00004000,
1243 .mmu_ctpr_mask
= 0x007ffff0,
1244 .mmu_cxr_mask
= 0x0000003f,
1245 .mmu_sfsr_mask
= 0xffffffff,
1246 .mmu_trcr_mask
= 0xffffffff,
1248 .features
= CPU_FEATURE_FLOAT
| CPU_FEATURE_FSMULD
,
1251 .name
= "Fujitsu MB86904",
1252 .iu_version
= 0x04 << 24, /* Impl 0, ver 4 */
1253 .fpu_version
= 4 << 17, /* FPU version 4 (Meiko) */
1254 .mmu_version
= 0x04 << 24, /* Impl 0, ver 4 */
1255 .mmu_bm
= 0x00004000,
1256 .mmu_ctpr_mask
= 0x00ffffc0,
1257 .mmu_cxr_mask
= 0x000000ff,
1258 .mmu_sfsr_mask
= 0x00016fff,
1259 .mmu_trcr_mask
= 0x00ffffff,
1261 .features
= CPU_DEFAULT_FEATURES
,
1264 .name
= "Fujitsu MB86907",
1265 .iu_version
= 0x05 << 24, /* Impl 0, ver 5 */
1266 .fpu_version
= 4 << 17, /* FPU version 4 (Meiko) */
1267 .mmu_version
= 0x05 << 24, /* Impl 0, ver 5 */
1268 .mmu_bm
= 0x00004000,
1269 .mmu_ctpr_mask
= 0xffffffc0,
1270 .mmu_cxr_mask
= 0x000000ff,
1271 .mmu_sfsr_mask
= 0x00016fff,
1272 .mmu_trcr_mask
= 0xffffffff,
1274 .features
= CPU_DEFAULT_FEATURES
,
1277 .name
= "LSI L64811",
1278 .iu_version
= 0x10 << 24, /* Impl 1, ver 0 */
1279 .fpu_version
= 1 << 17, /* FPU version 1 (LSI L64814) */
1280 .mmu_version
= 0x10 << 24,
1281 .mmu_bm
= 0x00004000,
1282 .mmu_ctpr_mask
= 0x007ffff0,
1283 .mmu_cxr_mask
= 0x0000003f,
1284 .mmu_sfsr_mask
= 0xffffffff,
1285 .mmu_trcr_mask
= 0xffffffff,
1287 .features
= CPU_FEATURE_FLOAT
| CPU_FEATURE_SWAP
| CPU_FEATURE_FSQRT
|
1291 .name
= "Cypress CY7C601",
1292 .iu_version
= 0x11 << 24, /* Impl 1, ver 1 */
1293 .fpu_version
= 3 << 17, /* FPU version 3 (Cypress CY7C602) */
1294 .mmu_version
= 0x10 << 24,
1295 .mmu_bm
= 0x00004000,
1296 .mmu_ctpr_mask
= 0x007ffff0,
1297 .mmu_cxr_mask
= 0x0000003f,
1298 .mmu_sfsr_mask
= 0xffffffff,
1299 .mmu_trcr_mask
= 0xffffffff,
1301 .features
= CPU_FEATURE_FLOAT
| CPU_FEATURE_SWAP
| CPU_FEATURE_FSQRT
|
1305 .name
= "Cypress CY7C611",
1306 .iu_version
= 0x13 << 24, /* Impl 1, ver 3 */
1307 .fpu_version
= 3 << 17, /* FPU version 3 (Cypress CY7C602) */
1308 .mmu_version
= 0x10 << 24,
1309 .mmu_bm
= 0x00004000,
1310 .mmu_ctpr_mask
= 0x007ffff0,
1311 .mmu_cxr_mask
= 0x0000003f,
1312 .mmu_sfsr_mask
= 0xffffffff,
1313 .mmu_trcr_mask
= 0xffffffff,
1315 .features
= CPU_FEATURE_FLOAT
| CPU_FEATURE_SWAP
| CPU_FEATURE_FSQRT
|
1319 .name
= "TI MicroSparc I",
1320 .iu_version
= 0x41000000,
1321 .fpu_version
= 4 << 17,
1322 .mmu_version
= 0x41000000,
1323 .mmu_bm
= 0x00004000,
1324 .mmu_ctpr_mask
= 0x007ffff0,
1325 .mmu_cxr_mask
= 0x0000003f,
1326 .mmu_sfsr_mask
= 0x00016fff,
1327 .mmu_trcr_mask
= 0x0000003f,
1329 .features
= CPU_FEATURE_FLOAT
| CPU_FEATURE_SWAP
| CPU_FEATURE_MUL
|
1330 CPU_FEATURE_DIV
| CPU_FEATURE_FLUSH
| CPU_FEATURE_FSQRT
|
1334 .name
= "TI MicroSparc II",
1335 .iu_version
= 0x42000000,
1336 .fpu_version
= 4 << 17,
1337 .mmu_version
= 0x02000000,
1338 .mmu_bm
= 0x00004000,
1339 .mmu_ctpr_mask
= 0x00ffffc0,
1340 .mmu_cxr_mask
= 0x000000ff,
1341 .mmu_sfsr_mask
= 0x00016fff,
1342 .mmu_trcr_mask
= 0x00ffffff,
1344 .features
= CPU_DEFAULT_FEATURES
,
1347 .name
= "TI MicroSparc IIep",
1348 .iu_version
= 0x42000000,
1349 .fpu_version
= 4 << 17,
1350 .mmu_version
= 0x04000000,
1351 .mmu_bm
= 0x00004000,
1352 .mmu_ctpr_mask
= 0x00ffffc0,
1353 .mmu_cxr_mask
= 0x000000ff,
1354 .mmu_sfsr_mask
= 0x00016bff,
1355 .mmu_trcr_mask
= 0x00ffffff,
1357 .features
= CPU_DEFAULT_FEATURES
,
1360 .name
= "TI SuperSparc 40", // STP1020NPGA
1361 .iu_version
= 0x41000000, // SuperSPARC 2.x
1362 .fpu_version
= 0 << 17,
1363 .mmu_version
= 0x00000800, // SuperSPARC 2.x, no MXCC
1364 .mmu_bm
= 0x00002000,
1365 .mmu_ctpr_mask
= 0xffffffc0,
1366 .mmu_cxr_mask
= 0x0000ffff,
1367 .mmu_sfsr_mask
= 0xffffffff,
1368 .mmu_trcr_mask
= 0xffffffff,
1370 .features
= CPU_DEFAULT_FEATURES
,
1373 .name
= "TI SuperSparc 50", // STP1020PGA
1374 .iu_version
= 0x40000000, // SuperSPARC 3.x
1375 .fpu_version
= 0 << 17,
1376 .mmu_version
= 0x01000800, // SuperSPARC 3.x, no MXCC
1377 .mmu_bm
= 0x00002000,
1378 .mmu_ctpr_mask
= 0xffffffc0,
1379 .mmu_cxr_mask
= 0x0000ffff,
1380 .mmu_sfsr_mask
= 0xffffffff,
1381 .mmu_trcr_mask
= 0xffffffff,
1383 .features
= CPU_DEFAULT_FEATURES
,
1386 .name
= "TI SuperSparc 51",
1387 .iu_version
= 0x40000000, // SuperSPARC 3.x
1388 .fpu_version
= 0 << 17,
1389 .mmu_version
= 0x01000000, // SuperSPARC 3.x, MXCC
1390 .mmu_bm
= 0x00002000,
1391 .mmu_ctpr_mask
= 0xffffffc0,
1392 .mmu_cxr_mask
= 0x0000ffff,
1393 .mmu_sfsr_mask
= 0xffffffff,
1394 .mmu_trcr_mask
= 0xffffffff,
1395 .mxcc_version
= 0x00000104,
1397 .features
= CPU_DEFAULT_FEATURES
,
1400 .name
= "TI SuperSparc 60", // STP1020APGA
1401 .iu_version
= 0x40000000, // SuperSPARC 3.x
1402 .fpu_version
= 0 << 17,
1403 .mmu_version
= 0x01000800, // SuperSPARC 3.x, no MXCC
1404 .mmu_bm
= 0x00002000,
1405 .mmu_ctpr_mask
= 0xffffffc0,
1406 .mmu_cxr_mask
= 0x0000ffff,
1407 .mmu_sfsr_mask
= 0xffffffff,
1408 .mmu_trcr_mask
= 0xffffffff,
1410 .features
= CPU_DEFAULT_FEATURES
,
1413 .name
= "TI SuperSparc 61",
1414 .iu_version
= 0x44000000, // SuperSPARC 3.x
1415 .fpu_version
= 0 << 17,
1416 .mmu_version
= 0x01000000, // SuperSPARC 3.x, MXCC
1417 .mmu_bm
= 0x00002000,
1418 .mmu_ctpr_mask
= 0xffffffc0,
1419 .mmu_cxr_mask
= 0x0000ffff,
1420 .mmu_sfsr_mask
= 0xffffffff,
1421 .mmu_trcr_mask
= 0xffffffff,
1422 .mxcc_version
= 0x00000104,
1424 .features
= CPU_DEFAULT_FEATURES
,
1427 .name
= "TI SuperSparc II",
1428 .iu_version
= 0x40000000, // SuperSPARC II 1.x
1429 .fpu_version
= 0 << 17,
1430 .mmu_version
= 0x08000000, // SuperSPARC II 1.x, MXCC
1431 .mmu_bm
= 0x00002000,
1432 .mmu_ctpr_mask
= 0xffffffc0,
1433 .mmu_cxr_mask
= 0x0000ffff,
1434 .mmu_sfsr_mask
= 0xffffffff,
1435 .mmu_trcr_mask
= 0xffffffff,
1436 .mxcc_version
= 0x00000104,
1438 .features
= CPU_DEFAULT_FEATURES
,
1441 .name
= "Ross RT625",
1442 .iu_version
= 0x1e000000,
1443 .fpu_version
= 1 << 17,
1444 .mmu_version
= 0x1e000000,
1445 .mmu_bm
= 0x00004000,
1446 .mmu_ctpr_mask
= 0x007ffff0,
1447 .mmu_cxr_mask
= 0x0000003f,
1448 .mmu_sfsr_mask
= 0xffffffff,
1449 .mmu_trcr_mask
= 0xffffffff,
1451 .features
= CPU_DEFAULT_FEATURES
,
1454 .name
= "Ross RT620",
1455 .iu_version
= 0x1f000000,
1456 .fpu_version
= 1 << 17,
1457 .mmu_version
= 0x1f000000,
1458 .mmu_bm
= 0x00004000,
1459 .mmu_ctpr_mask
= 0x007ffff0,
1460 .mmu_cxr_mask
= 0x0000003f,
1461 .mmu_sfsr_mask
= 0xffffffff,
1462 .mmu_trcr_mask
= 0xffffffff,
1464 .features
= CPU_DEFAULT_FEATURES
,
1467 .name
= "BIT B5010",
1468 .iu_version
= 0x20000000,
1469 .fpu_version
= 0 << 17, /* B5010/B5110/B5120/B5210 */
1470 .mmu_version
= 0x20000000,
1471 .mmu_bm
= 0x00004000,
1472 .mmu_ctpr_mask
= 0x007ffff0,
1473 .mmu_cxr_mask
= 0x0000003f,
1474 .mmu_sfsr_mask
= 0xffffffff,
1475 .mmu_trcr_mask
= 0xffffffff,
1477 .features
= CPU_FEATURE_FLOAT
| CPU_FEATURE_SWAP
| CPU_FEATURE_FSQRT
|
1481 .name
= "Matsushita MN10501",
1482 .iu_version
= 0x50000000,
1483 .fpu_version
= 0 << 17,
1484 .mmu_version
= 0x50000000,
1485 .mmu_bm
= 0x00004000,
1486 .mmu_ctpr_mask
= 0x007ffff0,
1487 .mmu_cxr_mask
= 0x0000003f,
1488 .mmu_sfsr_mask
= 0xffffffff,
1489 .mmu_trcr_mask
= 0xffffffff,
1491 .features
= CPU_FEATURE_FLOAT
| CPU_FEATURE_MUL
| CPU_FEATURE_FSQRT
|
1495 .name
= "Weitek W8601",
1496 .iu_version
= 0x90 << 24, /* Impl 9, ver 0 */
1497 .fpu_version
= 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
1498 .mmu_version
= 0x10 << 24,
1499 .mmu_bm
= 0x00004000,
1500 .mmu_ctpr_mask
= 0x007ffff0,
1501 .mmu_cxr_mask
= 0x0000003f,
1502 .mmu_sfsr_mask
= 0xffffffff,
1503 .mmu_trcr_mask
= 0xffffffff,
1505 .features
= CPU_DEFAULT_FEATURES
,
1509 .iu_version
= 0xf2000000,
1510 .fpu_version
= 4 << 17, /* FPU version 4 (Meiko) */
1511 .mmu_version
= 0xf2000000,
1512 .mmu_bm
= 0x00004000,
1513 .mmu_ctpr_mask
= 0x007ffff0,
1514 .mmu_cxr_mask
= 0x0000003f,
1515 .mmu_sfsr_mask
= 0xffffffff,
1516 .mmu_trcr_mask
= 0xffffffff,
1518 .features
= CPU_DEFAULT_FEATURES
| CPU_FEATURE_TA0_SHUTDOWN
,
1522 .iu_version
= 0xf3000000,
1523 .fpu_version
= 4 << 17, /* FPU version 4 (Meiko) */
1524 .mmu_version
= 0xf3000000,
1525 .mmu_bm
= 0x00000000,
1526 .mmu_ctpr_mask
= 0x007ffff0,
1527 .mmu_cxr_mask
= 0x0000003f,
1528 .mmu_sfsr_mask
= 0xffffffff,
1529 .mmu_trcr_mask
= 0xffffffff,
1531 .features
= CPU_DEFAULT_FEATURES
| CPU_FEATURE_TA0_SHUTDOWN
|
1532 CPU_FEATURE_ASR17
| CPU_FEATURE_CACHE_CTRL
,
1537 static const char * const feature_name
[] = {
1554 static void print_features(FILE *f
, fprintf_function cpu_fprintf
,
1555 uint32_t features
, const char *prefix
)
1559 for (i
= 0; i
< ARRAY_SIZE(feature_name
); i
++)
1560 if (feature_name
[i
] && (features
& (1 << i
))) {
1562 (*cpu_fprintf
)(f
, "%s", prefix
);
1563 (*cpu_fprintf
)(f
, "%s ", feature_name
[i
]);
1567 static void add_flagname_to_bitmaps(const char *flagname
, uint32_t *features
)
1571 for (i
= 0; i
< ARRAY_SIZE(feature_name
); i
++)
1572 if (feature_name
[i
] && !strcmp(flagname
, feature_name
[i
])) {
1573 *features
|= 1 << i
;
1576 fprintf(stderr
, "CPU feature %s not found\n", flagname
);
1579 static int cpu_sparc_find_by_name(sparc_def_t
*cpu_def
, const char *cpu_model
)
1582 const sparc_def_t
*def
= NULL
;
1583 char *s
= strdup(cpu_model
);
1584 char *featurestr
, *name
= strtok(s
, ",");
1585 uint32_t plus_features
= 0;
1586 uint32_t minus_features
= 0;
1587 uint64_t iu_version
;
1588 uint32_t fpu_version
, mmu_version
, nwindows
;
1590 for (i
= 0; i
< ARRAY_SIZE(sparc_defs
); i
++) {
1591 if (strcasecmp(name
, sparc_defs
[i
].name
) == 0) {
1592 def
= &sparc_defs
[i
];
1597 memcpy(cpu_def
, def
, sizeof(*def
));
1599 featurestr
= strtok(NULL
, ",");
1600 while (featurestr
) {
1603 if (featurestr
[0] == '+') {
1604 add_flagname_to_bitmaps(featurestr
+ 1, &plus_features
);
1605 } else if (featurestr
[0] == '-') {
1606 add_flagname_to_bitmaps(featurestr
+ 1, &minus_features
);
1607 } else if ((val
= strchr(featurestr
, '='))) {
1609 if (!strcmp(featurestr
, "iu_version")) {
1612 iu_version
= strtoll(val
, &err
, 0);
1613 if (!*val
|| *err
) {
1614 fprintf(stderr
, "bad numerical value %s\n", val
);
1617 cpu_def
->iu_version
= iu_version
;
1618 #ifdef DEBUG_FEATURES
1619 fprintf(stderr
, "iu_version %" PRIx64
"\n", iu_version
);
1621 } else if (!strcmp(featurestr
, "fpu_version")) {
1624 fpu_version
= strtol(val
, &err
, 0);
1625 if (!*val
|| *err
) {
1626 fprintf(stderr
, "bad numerical value %s\n", val
);
1629 cpu_def
->fpu_version
= fpu_version
;
1630 #ifdef DEBUG_FEATURES
1631 fprintf(stderr
, "fpu_version %x\n", fpu_version
);
1633 } else if (!strcmp(featurestr
, "mmu_version")) {
1636 mmu_version
= strtol(val
, &err
, 0);
1637 if (!*val
|| *err
) {
1638 fprintf(stderr
, "bad numerical value %s\n", val
);
1641 cpu_def
->mmu_version
= mmu_version
;
1642 #ifdef DEBUG_FEATURES
1643 fprintf(stderr
, "mmu_version %x\n", mmu_version
);
1645 } else if (!strcmp(featurestr
, "nwindows")) {
1648 nwindows
= strtol(val
, &err
, 0);
1649 if (!*val
|| *err
|| nwindows
> MAX_NWINDOWS
||
1650 nwindows
< MIN_NWINDOWS
) {
1651 fprintf(stderr
, "bad numerical value %s\n", val
);
1654 cpu_def
->nwindows
= nwindows
;
1655 #ifdef DEBUG_FEATURES
1656 fprintf(stderr
, "nwindows %d\n", nwindows
);
1659 fprintf(stderr
, "unrecognized feature %s\n", featurestr
);
1663 fprintf(stderr
, "feature string `%s' not in format "
1664 "(+feature|-feature|feature=xyz)\n", featurestr
);
1667 featurestr
= strtok(NULL
, ",");
1669 cpu_def
->features
|= plus_features
;
1670 cpu_def
->features
&= ~minus_features
;
1671 #ifdef DEBUG_FEATURES
1672 print_features(stderr
, fprintf
, cpu_def
->features
, NULL
);
1682 void sparc_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
1686 for (i
= 0; i
< ARRAY_SIZE(sparc_defs
); i
++) {
1687 (*cpu_fprintf
)(f
, "Sparc %16s IU " TARGET_FMT_lx
" FPU %08x MMU %08x NWINS %d ",
1689 sparc_defs
[i
].iu_version
,
1690 sparc_defs
[i
].fpu_version
,
1691 sparc_defs
[i
].mmu_version
,
1692 sparc_defs
[i
].nwindows
);
1693 print_features(f
, cpu_fprintf
, CPU_DEFAULT_FEATURES
&
1694 ~sparc_defs
[i
].features
, "-");
1695 print_features(f
, cpu_fprintf
, ~CPU_DEFAULT_FEATURES
&
1696 sparc_defs
[i
].features
, "+");
1697 (*cpu_fprintf
)(f
, "\n");
1699 (*cpu_fprintf
)(f
, "Default CPU feature flags (use '-' to remove): ");
1700 print_features(f
, cpu_fprintf
, CPU_DEFAULT_FEATURES
, NULL
);
1701 (*cpu_fprintf
)(f
, "\n");
1702 (*cpu_fprintf
)(f
, "Available CPU feature flags (use '+' to add): ");
1703 print_features(f
, cpu_fprintf
, ~CPU_DEFAULT_FEATURES
, NULL
);
1704 (*cpu_fprintf
)(f
, "\n");
1705 (*cpu_fprintf
)(f
, "Numerical features (use '=' to set): iu_version "
1706 "fpu_version mmu_version nwindows\n");
1709 static void cpu_print_cc(FILE *f
, fprintf_function cpu_fprintf
,
1712 cpu_fprintf(f
, "%c%c%c%c", cc
& PSR_NEG
? 'N' : '-',
1713 cc
& PSR_ZERO
? 'Z' : '-', cc
& PSR_OVF
? 'V' : '-',
1714 cc
& PSR_CARRY
? 'C' : '-');
1717 #ifdef TARGET_SPARC64
1718 #define REGS_PER_LINE 4
1720 #define REGS_PER_LINE 8
1723 void cpu_dump_state(CPUState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
1728 cpu_fprintf(f
, "pc: " TARGET_FMT_lx
" npc: " TARGET_FMT_lx
"\n", env
->pc
,
1730 cpu_fprintf(f
, "General Registers:\n");
1732 for (i
= 0; i
< 8; i
++) {
1733 if (i
% REGS_PER_LINE
== 0) {
1734 cpu_fprintf(f
, "%%g%d-%d:", i
, i
+ REGS_PER_LINE
- 1);
1736 cpu_fprintf(f
, " " TARGET_FMT_lx
, env
->gregs
[i
]);
1737 if (i
% REGS_PER_LINE
== REGS_PER_LINE
- 1) {
1738 cpu_fprintf(f
, "\n");
1741 cpu_fprintf(f
, "\nCurrent Register Window:\n");
1742 for (x
= 0; x
< 3; x
++) {
1743 for (i
= 0; i
< 8; i
++) {
1744 if (i
% REGS_PER_LINE
== 0) {
1745 cpu_fprintf(f
, "%%%c%d-%d: ",
1746 x
== 0 ? 'o' : (x
== 1 ? 'l' : 'i'),
1747 i
, i
+ REGS_PER_LINE
- 1);
1749 cpu_fprintf(f
, TARGET_FMT_lx
" ", env
->regwptr
[i
+ x
* 8]);
1750 if (i
% REGS_PER_LINE
== REGS_PER_LINE
- 1) {
1751 cpu_fprintf(f
, "\n");
1755 cpu_fprintf(f
, "\nFloating Point Registers:\n");
1756 for (i
= 0; i
< TARGET_FPREGS
; i
++) {
1758 cpu_fprintf(f
, "%%f%02d:", i
);
1759 cpu_fprintf(f
, " %016f", *(float *)&env
->fpr
[i
]);
1761 cpu_fprintf(f
, "\n");
1763 #ifdef TARGET_SPARC64
1764 cpu_fprintf(f
, "pstate: %08x ccr: %02x (icc: ", env
->pstate
,
1765 (unsigned)cpu_get_ccr(env
));
1766 cpu_print_cc(f
, cpu_fprintf
, cpu_get_ccr(env
) << PSR_CARRY_SHIFT
);
1767 cpu_fprintf(f
, " xcc: ");
1768 cpu_print_cc(f
, cpu_fprintf
, cpu_get_ccr(env
) << (PSR_CARRY_SHIFT
- 4));
1769 cpu_fprintf(f
, ") asi: %02x tl: %d pil: %x\n", env
->asi
, env
->tl
,
1771 cpu_fprintf(f
, "cansave: %d canrestore: %d otherwin: %d wstate: %d "
1772 "cleanwin: %d cwp: %d\n",
1773 env
->cansave
, env
->canrestore
, env
->otherwin
, env
->wstate
,
1774 env
->cleanwin
, env
->nwindows
- 1 - env
->cwp
);
1775 cpu_fprintf(f
, "fsr: " TARGET_FMT_lx
" y: " TARGET_FMT_lx
" fprs: "
1776 TARGET_FMT_lx
"\n", env
->fsr
, env
->y
, env
->fprs
);
1778 cpu_fprintf(f
, "psr: %08x (icc: ", cpu_get_psr(env
));
1779 cpu_print_cc(f
, cpu_fprintf
, cpu_get_psr(env
));
1780 cpu_fprintf(f
, " SPE: %c%c%c) wim: %08x\n", env
->psrs
? 'S' : '-',
1781 env
->psrps
? 'P' : '-', env
->psret
? 'E' : '-',
1783 cpu_fprintf(f
, "fsr: " TARGET_FMT_lx
" y: " TARGET_FMT_lx
"\n",