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Fix block load ASIs
[qemu.git] / target-sparc / op_helper.c
1 #include "exec.h"
2
3 //#define DEBUG_PCALL
4 //#define DEBUG_MMU
5 //#define DEBUG_UNALIGNED
6 //#define DEBUG_UNASSIGNED
7
8 void raise_exception(int tt)
9 {
10 env->exception_index = tt;
11 cpu_loop_exit();
12 }
13
14 void check_ieee_exceptions()
15 {
16 T0 = get_float_exception_flags(&env->fp_status);
17 if (T0)
18 {
19 /* Copy IEEE 754 flags into FSR */
20 if (T0 & float_flag_invalid)
21 env->fsr |= FSR_NVC;
22 if (T0 & float_flag_overflow)
23 env->fsr |= FSR_OFC;
24 if (T0 & float_flag_underflow)
25 env->fsr |= FSR_UFC;
26 if (T0 & float_flag_divbyzero)
27 env->fsr |= FSR_DZC;
28 if (T0 & float_flag_inexact)
29 env->fsr |= FSR_NXC;
30
31 if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23))
32 {
33 /* Unmasked exception, generate a trap */
34 env->fsr |= FSR_FTT_IEEE_EXCP;
35 raise_exception(TT_FP_EXCP);
36 }
37 else
38 {
39 /* Accumulate exceptions */
40 env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
41 }
42 }
43 }
44
45 #ifdef USE_INT_TO_FLOAT_HELPERS
46 void do_fitos(void)
47 {
48 set_float_exception_flags(0, &env->fp_status);
49 FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status);
50 check_ieee_exceptions();
51 }
52
53 void do_fitod(void)
54 {
55 DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status);
56 }
57 #endif
58
59 void do_fabss(void)
60 {
61 FT0 = float32_abs(FT1);
62 }
63
64 #ifdef TARGET_SPARC64
65 void do_fabsd(void)
66 {
67 DT0 = float64_abs(DT1);
68 }
69 #endif
70
71 void do_fsqrts(void)
72 {
73 set_float_exception_flags(0, &env->fp_status);
74 FT0 = float32_sqrt(FT1, &env->fp_status);
75 check_ieee_exceptions();
76 }
77
78 void do_fsqrtd(void)
79 {
80 set_float_exception_flags(0, &env->fp_status);
81 DT0 = float64_sqrt(DT1, &env->fp_status);
82 check_ieee_exceptions();
83 }
84
85 #define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
86 void glue(do_, name) (void) \
87 { \
88 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
89 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
90 case float_relation_unordered: \
91 T0 = (FSR_FCC1 | FSR_FCC0) << FS; \
92 if ((env->fsr & FSR_NVM) || TRAP) { \
93 env->fsr |= T0; \
94 env->fsr |= FSR_NVC; \
95 env->fsr |= FSR_FTT_IEEE_EXCP; \
96 raise_exception(TT_FP_EXCP); \
97 } else { \
98 env->fsr |= FSR_NVA; \
99 } \
100 break; \
101 case float_relation_less: \
102 T0 = FSR_FCC0 << FS; \
103 break; \
104 case float_relation_greater: \
105 T0 = FSR_FCC1 << FS; \
106 break; \
107 default: \
108 T0 = 0; \
109 break; \
110 } \
111 env->fsr |= T0; \
112 }
113
114 GEN_FCMP(fcmps, float32, FT0, FT1, 0, 0);
115 GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);
116
117 GEN_FCMP(fcmpes, float32, FT0, FT1, 0, 1);
118 GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
119
120 #ifdef TARGET_SPARC64
121 GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22, 0);
122 GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
123
124 GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24, 0);
125 GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);
126
127 GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26, 0);
128 GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);
129
130 GEN_FCMP(fcmpes_fcc1, float32, FT0, FT1, 22, 1);
131 GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);
132
133 GEN_FCMP(fcmpes_fcc2, float32, FT0, FT1, 24, 1);
134 GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
135
136 GEN_FCMP(fcmpes_fcc3, float32, FT0, FT1, 26, 1);
137 GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
138 #endif
139
140 #ifndef TARGET_SPARC64
141 #ifndef CONFIG_USER_ONLY
142 void helper_ld_asi(int asi, int size, int sign)
143 {
144 uint32_t ret = 0;
145
146 switch (asi) {
147 case 2: /* SuperSparc MXCC registers */
148 break;
149 case 3: /* MMU probe */
150 {
151 int mmulev;
152
153 mmulev = (T0 >> 8) & 15;
154 if (mmulev > 4)
155 ret = 0;
156 else {
157 ret = mmu_probe(env, T0, mmulev);
158 //bswap32s(&ret);
159 }
160 #ifdef DEBUG_MMU
161 printf("mmu_probe: 0x%08x (lev %d) -> 0x%08x\n", T0, mmulev, ret);
162 #endif
163 }
164 break;
165 case 4: /* read MMU regs */
166 {
167 int reg = (T0 >> 8) & 0xf;
168
169 ret = env->mmuregs[reg];
170 if (reg == 3) /* Fault status cleared on read */
171 env->mmuregs[reg] = 0;
172 #ifdef DEBUG_MMU
173 printf("mmu_read: reg[%d] = 0x%08x\n", reg, ret);
174 #endif
175 }
176 break;
177 case 9: /* Supervisor code access */
178 switch(size) {
179 case 1:
180 ret = ldub_code(T0);
181 break;
182 case 2:
183 ret = lduw_code(T0 & ~1);
184 break;
185 default:
186 case 4:
187 ret = ldl_code(T0 & ~3);
188 break;
189 case 8:
190 ret = ldl_code(T0 & ~3);
191 T0 = ldl_code((T0 + 4) & ~3);
192 break;
193 }
194 break;
195 case 0xa: /* User data access */
196 switch(size) {
197 case 1:
198 ret = ldub_user(T0);
199 break;
200 case 2:
201 ret = lduw_user(T0 & ~1);
202 break;
203 default:
204 case 4:
205 ret = ldl_user(T0 & ~3);
206 break;
207 case 8:
208 ret = ldl_user(T0 & ~3);
209 T0 = ldl_user((T0 + 4) & ~3);
210 break;
211 }
212 break;
213 case 0xb: /* Supervisor data access */
214 switch(size) {
215 case 1:
216 ret = ldub_kernel(T0);
217 break;
218 case 2:
219 ret = lduw_kernel(T0 & ~1);
220 break;
221 default:
222 case 4:
223 ret = ldl_kernel(T0 & ~3);
224 break;
225 case 8:
226 ret = ldl_kernel(T0 & ~3);
227 T0 = ldl_kernel((T0 + 4) & ~3);
228 break;
229 }
230 break;
231 case 0xc: /* I-cache tag */
232 case 0xd: /* I-cache data */
233 case 0xe: /* D-cache tag */
234 case 0xf: /* D-cache data */
235 break;
236 case 0x20: /* MMU passthrough */
237 switch(size) {
238 case 1:
239 ret = ldub_phys(T0);
240 break;
241 case 2:
242 ret = lduw_phys(T0 & ~1);
243 break;
244 default:
245 case 4:
246 ret = ldl_phys(T0 & ~3);
247 break;
248 case 8:
249 ret = ldl_phys(T0 & ~3);
250 T0 = ldl_phys((T0 + 4) & ~3);
251 break;
252 }
253 break;
254 case 0x2e: /* MMU passthrough, 0xexxxxxxxx */
255 case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */
256 switch(size) {
257 case 1:
258 ret = ldub_phys((target_phys_addr_t)T0
259 | ((target_phys_addr_t)(asi & 0xf) << 32));
260 break;
261 case 2:
262 ret = lduw_phys((target_phys_addr_t)(T0 & ~1)
263 | ((target_phys_addr_t)(asi & 0xf) << 32));
264 break;
265 default:
266 case 4:
267 ret = ldl_phys((target_phys_addr_t)(T0 & ~3)
268 | ((target_phys_addr_t)(asi & 0xf) << 32));
269 break;
270 case 8:
271 ret = ldl_phys((target_phys_addr_t)(T0 & ~3)
272 | ((target_phys_addr_t)(asi & 0xf) << 32));
273 T0 = ldl_phys((target_phys_addr_t)((T0 + 4) & ~3)
274 | ((target_phys_addr_t)(asi & 0xf) << 32));
275 break;
276 }
277 break;
278 case 0x21 ... 0x2d: /* MMU passthrough, unassigned */
279 default:
280 do_unassigned_access(T0, 0, 0, 1);
281 ret = 0;
282 break;
283 }
284 if (sign) {
285 switch(size) {
286 case 1:
287 T1 = (int8_t) ret;
288 break;
289 case 2:
290 T1 = (int16_t) ret;
291 break;
292 default:
293 T1 = ret;
294 break;
295 }
296 }
297 else
298 T1 = ret;
299 }
300
301 void helper_st_asi(int asi, int size)
302 {
303 switch(asi) {
304 case 2: /* SuperSparc MXCC registers */
305 break;
306 case 3: /* MMU flush */
307 {
308 int mmulev;
309
310 mmulev = (T0 >> 8) & 15;
311 #ifdef DEBUG_MMU
312 printf("mmu flush level %d\n", mmulev);
313 #endif
314 switch (mmulev) {
315 case 0: // flush page
316 tlb_flush_page(env, T0 & 0xfffff000);
317 break;
318 case 1: // flush segment (256k)
319 case 2: // flush region (16M)
320 case 3: // flush context (4G)
321 case 4: // flush entire
322 tlb_flush(env, 1);
323 break;
324 default:
325 break;
326 }
327 #ifdef DEBUG_MMU
328 dump_mmu(env);
329 #endif
330 return;
331 }
332 case 4: /* write MMU regs */
333 {
334 int reg = (T0 >> 8) & 0xf;
335 uint32_t oldreg;
336
337 oldreg = env->mmuregs[reg];
338 switch(reg) {
339 case 0:
340 env->mmuregs[reg] &= ~(MMU_E | MMU_NF | MMU_BM);
341 env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF | MMU_BM);
342 // Mappings generated during no-fault mode or MMU
343 // disabled mode are invalid in normal mode
344 if (oldreg != env->mmuregs[reg])
345 tlb_flush(env, 1);
346 break;
347 case 2:
348 env->mmuregs[reg] = T1;
349 if (oldreg != env->mmuregs[reg]) {
350 /* we flush when the MMU context changes because
351 QEMU has no MMU context support */
352 tlb_flush(env, 1);
353 }
354 break;
355 case 3:
356 case 4:
357 break;
358 default:
359 env->mmuregs[reg] = T1;
360 break;
361 }
362 #ifdef DEBUG_MMU
363 if (oldreg != env->mmuregs[reg]) {
364 printf("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
365 }
366 dump_mmu(env);
367 #endif
368 return;
369 }
370 case 0xa: /* User data access */
371 switch(size) {
372 case 1:
373 stb_user(T0, T1);
374 break;
375 case 2:
376 stw_user(T0 & ~1, T1);
377 break;
378 default:
379 case 4:
380 stl_user(T0 & ~3, T1);
381 break;
382 case 8:
383 stl_user(T0 & ~3, T1);
384 stl_user((T0 + 4) & ~3, T2);
385 break;
386 }
387 break;
388 case 0xb: /* Supervisor data access */
389 switch(size) {
390 case 1:
391 stb_kernel(T0, T1);
392 break;
393 case 2:
394 stw_kernel(T0 & ~1, T1);
395 break;
396 default:
397 case 4:
398 stl_kernel(T0 & ~3, T1);
399 break;
400 case 8:
401 stl_kernel(T0 & ~3, T1);
402 stl_kernel((T0 + 4) & ~3, T2);
403 break;
404 }
405 break;
406 case 0xc: /* I-cache tag */
407 case 0xd: /* I-cache data */
408 case 0xe: /* D-cache tag */
409 case 0xf: /* D-cache data */
410 case 0x10: /* I/D-cache flush page */
411 case 0x11: /* I/D-cache flush segment */
412 case 0x12: /* I/D-cache flush region */
413 case 0x13: /* I/D-cache flush context */
414 case 0x14: /* I/D-cache flush user */
415 break;
416 case 0x17: /* Block copy, sta access */
417 {
418 // value (T1) = src
419 // address (T0) = dst
420 // copy 32 bytes
421 unsigned int i;
422 uint32_t src = T1 & ~3, dst = T0 & ~3, temp;
423
424 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
425 temp = ldl_kernel(src);
426 stl_kernel(dst, temp);
427 }
428 }
429 return;
430 case 0x1f: /* Block fill, stda access */
431 {
432 // value (T1, T2)
433 // address (T0) = dst
434 // fill 32 bytes
435 unsigned int i;
436 uint32_t dst = T0 & 7;
437 uint64_t val;
438
439 val = (((uint64_t)T1) << 32) | T2;
440
441 for (i = 0; i < 32; i += 8, dst += 8)
442 stq_kernel(dst, val);
443 }
444 return;
445 case 0x20: /* MMU passthrough */
446 {
447 switch(size) {
448 case 1:
449 stb_phys(T0, T1);
450 break;
451 case 2:
452 stw_phys(T0 & ~1, T1);
453 break;
454 case 4:
455 default:
456 stl_phys(T0 & ~3, T1);
457 break;
458 case 8:
459 stl_phys(T0 & ~3, T1);
460 stl_phys((T0 + 4) & ~3, T2);
461 break;
462 }
463 }
464 return;
465 case 0x2e: /* MMU passthrough, 0xexxxxxxxx */
466 case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */
467 {
468 switch(size) {
469 case 1:
470 stb_phys((target_phys_addr_t)T0
471 | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
472 break;
473 case 2:
474 stw_phys((target_phys_addr_t)(T0 & ~1)
475 | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
476 break;
477 case 4:
478 default:
479 stl_phys((target_phys_addr_t)(T0 & ~3)
480 | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
481 break;
482 case 8:
483 stl_phys((target_phys_addr_t)(T0 & ~3)
484 | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
485 stl_phys((target_phys_addr_t)((T0 + 4) & ~3)
486 | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
487 break;
488 }
489 }
490 return;
491 case 0x31: /* Ross RT620 I-cache flush */
492 case 0x36: /* I-cache flash clear */
493 case 0x37: /* D-cache flash clear */
494 break;
495 case 9: /* Supervisor code access, XXX */
496 case 0x21 ... 0x2d: /* MMU passthrough, unassigned */
497 default:
498 do_unassigned_access(T0, 1, 0, 1);
499 return;
500 }
501 }
502
503 #endif /* CONFIG_USER_ONLY */
504 #else /* TARGET_SPARC64 */
505
506 #ifdef CONFIG_USER_ONLY
507 void helper_ld_asi(int asi, int size, int sign)
508 {
509 uint64_t ret = 0;
510
511 if (asi < 0x80)
512 raise_exception(TT_PRIV_ACT);
513
514 switch (asi) {
515 case 0x80: // Primary
516 case 0x82: // Primary no-fault
517 case 0x88: // Primary LE
518 case 0x8a: // Primary no-fault LE
519 {
520 switch(size) {
521 case 1:
522 ret = ldub_raw(T0);
523 break;
524 case 2:
525 ret = lduw_raw(T0 & ~1);
526 break;
527 case 4:
528 ret = ldl_raw(T0 & ~3);
529 break;
530 default:
531 case 8:
532 ret = ldq_raw(T0 & ~7);
533 break;
534 }
535 }
536 break;
537 case 0x81: // Secondary
538 case 0x83: // Secondary no-fault
539 case 0x89: // Secondary LE
540 case 0x8b: // Secondary no-fault LE
541 // XXX
542 break;
543 default:
544 break;
545 }
546
547 /* Convert from little endian */
548 switch (asi) {
549 case 0x88: // Primary LE
550 case 0x89: // Secondary LE
551 case 0x8a: // Primary no-fault LE
552 case 0x8b: // Secondary no-fault LE
553 switch(size) {
554 case 2:
555 ret = bswap16(ret);
556 break;
557 case 4:
558 ret = bswap32(ret);
559 break;
560 case 8:
561 ret = bswap64(ret);
562 break;
563 default:
564 break;
565 }
566 default:
567 break;
568 }
569
570 /* Convert to signed number */
571 if (sign) {
572 switch(size) {
573 case 1:
574 ret = (int8_t) ret;
575 break;
576 case 2:
577 ret = (int16_t) ret;
578 break;
579 case 4:
580 ret = (int32_t) ret;
581 break;
582 default:
583 break;
584 }
585 }
586 T1 = ret;
587 }
588
589 void helper_st_asi(int asi, int size)
590 {
591 if (asi < 0x80)
592 raise_exception(TT_PRIV_ACT);
593
594 /* Convert to little endian */
595 switch (asi) {
596 case 0x88: // Primary LE
597 case 0x89: // Secondary LE
598 switch(size) {
599 case 2:
600 T0 = bswap16(T0);
601 break;
602 case 4:
603 T0 = bswap32(T0);
604 break;
605 case 8:
606 T0 = bswap64(T0);
607 break;
608 default:
609 break;
610 }
611 default:
612 break;
613 }
614
615 switch(asi) {
616 case 0x80: // Primary
617 case 0x88: // Primary LE
618 {
619 switch(size) {
620 case 1:
621 stb_raw(T0, T1);
622 break;
623 case 2:
624 stw_raw(T0 & ~1, T1);
625 break;
626 case 4:
627 stl_raw(T0 & ~3, T1);
628 break;
629 case 8:
630 default:
631 stq_raw(T0 & ~7, T1);
632 break;
633 }
634 }
635 break;
636 case 0x81: // Secondary
637 case 0x89: // Secondary LE
638 // XXX
639 return;
640
641 case 0x82: // Primary no-fault, RO
642 case 0x83: // Secondary no-fault, RO
643 case 0x8a: // Primary no-fault LE, RO
644 case 0x8b: // Secondary no-fault LE, RO
645 default:
646 do_unassigned_access(T0, 1, 0, 1);
647 return;
648 }
649 }
650
651 #else /* CONFIG_USER_ONLY */
652
653 void helper_ld_asi(int asi, int size, int sign)
654 {
655 uint64_t ret = 0;
656
657 if (asi < 0x80 && (env->pstate & PS_PRIV) == 0)
658 raise_exception(TT_PRIV_ACT);
659
660 switch (asi) {
661 case 0x10: // As if user primary
662 case 0x18: // As if user primary LE
663 case 0x80: // Primary
664 case 0x82: // Primary no-fault
665 case 0x88: // Primary LE
666 case 0x8a: // Primary no-fault LE
667 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
668 switch(size) {
669 case 1:
670 ret = ldub_kernel(T0);
671 break;
672 case 2:
673 ret = lduw_kernel(T0 & ~1);
674 break;
675 case 4:
676 ret = ldl_kernel(T0 & ~3);
677 break;
678 default:
679 case 8:
680 ret = ldq_kernel(T0 & ~7);
681 break;
682 }
683 } else {
684 switch(size) {
685 case 1:
686 ret = ldub_user(T0);
687 break;
688 case 2:
689 ret = lduw_user(T0 & ~1);
690 break;
691 case 4:
692 ret = ldl_user(T0 & ~3);
693 break;
694 default:
695 case 8:
696 ret = ldq_user(T0 & ~7);
697 break;
698 }
699 }
700 break;
701 case 0x14: // Bypass
702 case 0x15: // Bypass, non-cacheable
703 case 0x1c: // Bypass LE
704 case 0x1d: // Bypass, non-cacheable LE
705 {
706 switch(size) {
707 case 1:
708 ret = ldub_phys(T0);
709 break;
710 case 2:
711 ret = lduw_phys(T0 & ~1);
712 break;
713 case 4:
714 ret = ldl_phys(T0 & ~3);
715 break;
716 default:
717 case 8:
718 ret = ldq_phys(T0 & ~7);
719 break;
720 }
721 break;
722 }
723 case 0x04: // Nucleus
724 case 0x0c: // Nucleus Little Endian (LE)
725 case 0x11: // As if user secondary
726 case 0x19: // As if user secondary LE
727 case 0x24: // Nucleus quad LDD 128 bit atomic
728 case 0x2c: // Nucleus quad LDD 128 bit atomic
729 case 0x4a: // UPA config
730 case 0x81: // Secondary
731 case 0x83: // Secondary no-fault
732 case 0x89: // Secondary LE
733 case 0x8b: // Secondary no-fault LE
734 // XXX
735 break;
736 case 0x45: // LSU
737 ret = env->lsu;
738 break;
739 case 0x50: // I-MMU regs
740 {
741 int reg = (T0 >> 3) & 0xf;
742
743 ret = env->immuregs[reg];
744 break;
745 }
746 case 0x51: // I-MMU 8k TSB pointer
747 case 0x52: // I-MMU 64k TSB pointer
748 case 0x55: // I-MMU data access
749 // XXX
750 break;
751 case 0x56: // I-MMU tag read
752 {
753 unsigned int i;
754
755 for (i = 0; i < 64; i++) {
756 // Valid, ctx match, vaddr match
757 if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 &&
758 env->itlb_tag[i] == T0) {
759 ret = env->itlb_tag[i];
760 break;
761 }
762 }
763 break;
764 }
765 case 0x58: // D-MMU regs
766 {
767 int reg = (T0 >> 3) & 0xf;
768
769 ret = env->dmmuregs[reg];
770 break;
771 }
772 case 0x5e: // D-MMU tag read
773 {
774 unsigned int i;
775
776 for (i = 0; i < 64; i++) {
777 // Valid, ctx match, vaddr match
778 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 &&
779 env->dtlb_tag[i] == T0) {
780 ret = env->dtlb_tag[i];
781 break;
782 }
783 }
784 break;
785 }
786 case 0x59: // D-MMU 8k TSB pointer
787 case 0x5a: // D-MMU 64k TSB pointer
788 case 0x5b: // D-MMU data pointer
789 case 0x5d: // D-MMU data access
790 case 0x48: // Interrupt dispatch, RO
791 case 0x49: // Interrupt data receive
792 case 0x7f: // Incoming interrupt vector, RO
793 // XXX
794 break;
795 case 0x54: // I-MMU data in, WO
796 case 0x57: // I-MMU demap, WO
797 case 0x5c: // D-MMU data in, WO
798 case 0x5f: // D-MMU demap, WO
799 case 0x77: // Interrupt vector, WO
800 default:
801 do_unassigned_access(T0, 0, 0, 1);
802 ret = 0;
803 break;
804 }
805
806 /* Convert from little endian */
807 switch (asi) {
808 case 0x0c: // Nucleus Little Endian (LE)
809 case 0x18: // As if user primary LE
810 case 0x19: // As if user secondary LE
811 case 0x1c: // Bypass LE
812 case 0x1d: // Bypass, non-cacheable LE
813 case 0x88: // Primary LE
814 case 0x89: // Secondary LE
815 case 0x8a: // Primary no-fault LE
816 case 0x8b: // Secondary no-fault LE
817 switch(size) {
818 case 2:
819 ret = bswap16(ret);
820 break;
821 case 4:
822 ret = bswap32(ret);
823 break;
824 case 8:
825 ret = bswap64(ret);
826 break;
827 default:
828 break;
829 }
830 default:
831 break;
832 }
833
834 /* Convert to signed number */
835 if (sign) {
836 switch(size) {
837 case 1:
838 ret = (int8_t) ret;
839 break;
840 case 2:
841 ret = (int16_t) ret;
842 break;
843 case 4:
844 ret = (int32_t) ret;
845 break;
846 default:
847 break;
848 }
849 }
850 T1 = ret;
851 }
852
853 void helper_st_asi(int asi, int size)
854 {
855 if (asi < 0x80 && (env->pstate & PS_PRIV) == 0)
856 raise_exception(TT_PRIV_ACT);
857
858 /* Convert to little endian */
859 switch (asi) {
860 case 0x0c: // Nucleus Little Endian (LE)
861 case 0x18: // As if user primary LE
862 case 0x19: // As if user secondary LE
863 case 0x1c: // Bypass LE
864 case 0x1d: // Bypass, non-cacheable LE
865 case 0x88: // Primary LE
866 case 0x89: // Secondary LE
867 switch(size) {
868 case 2:
869 T0 = bswap16(T0);
870 break;
871 case 4:
872 T0 = bswap32(T0);
873 break;
874 case 8:
875 T0 = bswap64(T0);
876 break;
877 default:
878 break;
879 }
880 default:
881 break;
882 }
883
884 switch(asi) {
885 case 0x10: // As if user primary
886 case 0x18: // As if user primary LE
887 case 0x80: // Primary
888 case 0x88: // Primary LE
889 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
890 switch(size) {
891 case 1:
892 stb_kernel(T0, T1);
893 break;
894 case 2:
895 stw_kernel(T0 & ~1, T1);
896 break;
897 case 4:
898 stl_kernel(T0 & ~3, T1);
899 break;
900 case 8:
901 default:
902 stq_kernel(T0 & ~7, T1);
903 break;
904 }
905 } else {
906 switch(size) {
907 case 1:
908 stb_user(T0, T1);
909 break;
910 case 2:
911 stw_user(T0 & ~1, T1);
912 break;
913 case 4:
914 stl_user(T0 & ~3, T1);
915 break;
916 case 8:
917 default:
918 stq_user(T0 & ~7, T1);
919 break;
920 }
921 }
922 break;
923 case 0x14: // Bypass
924 case 0x15: // Bypass, non-cacheable
925 case 0x1c: // Bypass LE
926 case 0x1d: // Bypass, non-cacheable LE
927 {
928 switch(size) {
929 case 1:
930 stb_phys(T0, T1);
931 break;
932 case 2:
933 stw_phys(T0 & ~1, T1);
934 break;
935 case 4:
936 stl_phys(T0 & ~3, T1);
937 break;
938 case 8:
939 default:
940 stq_phys(T0 & ~7, T1);
941 break;
942 }
943 }
944 return;
945 case 0x04: // Nucleus
946 case 0x0c: // Nucleus Little Endian (LE)
947 case 0x11: // As if user secondary
948 case 0x19: // As if user secondary LE
949 case 0x24: // Nucleus quad LDD 128 bit atomic
950 case 0x2c: // Nucleus quad LDD 128 bit atomic
951 case 0x4a: // UPA config
952 case 0x81: // Secondary
953 case 0x89: // Secondary LE
954 // XXX
955 return;
956 case 0x45: // LSU
957 {
958 uint64_t oldreg;
959
960 oldreg = env->lsu;
961 env->lsu = T1 & (DMMU_E | IMMU_E);
962 // Mappings generated during D/I MMU disabled mode are
963 // invalid in normal mode
964 if (oldreg != env->lsu) {
965 #ifdef DEBUG_MMU
966 printf("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu);
967 dump_mmu(env);
968 #endif
969 tlb_flush(env, 1);
970 }
971 return;
972 }
973 case 0x50: // I-MMU regs
974 {
975 int reg = (T0 >> 3) & 0xf;
976 uint64_t oldreg;
977
978 oldreg = env->immuregs[reg];
979 switch(reg) {
980 case 0: // RO
981 case 4:
982 return;
983 case 1: // Not in I-MMU
984 case 2:
985 case 7:
986 case 8:
987 return;
988 case 3: // SFSR
989 if ((T1 & 1) == 0)
990 T1 = 0; // Clear SFSR
991 break;
992 case 5: // TSB access
993 case 6: // Tag access
994 default:
995 break;
996 }
997 env->immuregs[reg] = T1;
998 #ifdef DEBUG_MMU
999 if (oldreg != env->immuregs[reg]) {
1000 printf("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
1001 }
1002 dump_mmu(env);
1003 #endif
1004 return;
1005 }
1006 case 0x54: // I-MMU data in
1007 {
1008 unsigned int i;
1009
1010 // Try finding an invalid entry
1011 for (i = 0; i < 64; i++) {
1012 if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
1013 env->itlb_tag[i] = env->immuregs[6];
1014 env->itlb_tte[i] = T1;
1015 return;
1016 }
1017 }
1018 // Try finding an unlocked entry
1019 for (i = 0; i < 64; i++) {
1020 if ((env->itlb_tte[i] & 0x40) == 0) {
1021 env->itlb_tag[i] = env->immuregs[6];
1022 env->itlb_tte[i] = T1;
1023 return;
1024 }
1025 }
1026 // error state?
1027 return;
1028 }
1029 case 0x55: // I-MMU data access
1030 {
1031 unsigned int i = (T0 >> 3) & 0x3f;
1032
1033 env->itlb_tag[i] = env->immuregs[6];
1034 env->itlb_tte[i] = T1;
1035 return;
1036 }
1037 case 0x57: // I-MMU demap
1038 // XXX
1039 return;
1040 case 0x58: // D-MMU regs
1041 {
1042 int reg = (T0 >> 3) & 0xf;
1043 uint64_t oldreg;
1044
1045 oldreg = env->dmmuregs[reg];
1046 switch(reg) {
1047 case 0: // RO
1048 case 4:
1049 return;
1050 case 3: // SFSR
1051 if ((T1 & 1) == 0) {
1052 T1 = 0; // Clear SFSR, Fault address
1053 env->dmmuregs[4] = 0;
1054 }
1055 env->dmmuregs[reg] = T1;
1056 break;
1057 case 1: // Primary context
1058 case 2: // Secondary context
1059 case 5: // TSB access
1060 case 6: // Tag access
1061 case 7: // Virtual Watchpoint
1062 case 8: // Physical Watchpoint
1063 default:
1064 break;
1065 }
1066 env->dmmuregs[reg] = T1;
1067 #ifdef DEBUG_MMU
1068 if (oldreg != env->dmmuregs[reg]) {
1069 printf("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
1070 }
1071 dump_mmu(env);
1072 #endif
1073 return;
1074 }
1075 case 0x5c: // D-MMU data in
1076 {
1077 unsigned int i;
1078
1079 // Try finding an invalid entry
1080 for (i = 0; i < 64; i++) {
1081 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
1082 env->dtlb_tag[i] = env->dmmuregs[6];
1083 env->dtlb_tte[i] = T1;
1084 return;
1085 }
1086 }
1087 // Try finding an unlocked entry
1088 for (i = 0; i < 64; i++) {
1089 if ((env->dtlb_tte[i] & 0x40) == 0) {
1090 env->dtlb_tag[i] = env->dmmuregs[6];
1091 env->dtlb_tte[i] = T1;
1092 return;
1093 }
1094 }
1095 // error state?
1096 return;
1097 }
1098 case 0x5d: // D-MMU data access
1099 {
1100 unsigned int i = (T0 >> 3) & 0x3f;
1101
1102 env->dtlb_tag[i] = env->dmmuregs[6];
1103 env->dtlb_tte[i] = T1;
1104 return;
1105 }
1106 case 0x5f: // D-MMU demap
1107 case 0x49: // Interrupt data receive
1108 // XXX
1109 return;
1110 case 0x51: // I-MMU 8k TSB pointer, RO
1111 case 0x52: // I-MMU 64k TSB pointer, RO
1112 case 0x56: // I-MMU tag read, RO
1113 case 0x59: // D-MMU 8k TSB pointer, RO
1114 case 0x5a: // D-MMU 64k TSB pointer, RO
1115 case 0x5b: // D-MMU data pointer, RO
1116 case 0x5e: // D-MMU tag read, RO
1117 case 0x48: // Interrupt dispatch, RO
1118 case 0x7f: // Incoming interrupt vector, RO
1119 case 0x82: // Primary no-fault, RO
1120 case 0x83: // Secondary no-fault, RO
1121 case 0x8a: // Primary no-fault LE, RO
1122 case 0x8b: // Secondary no-fault LE, RO
1123 default:
1124 do_unassigned_access(T0, 1, 0, 1);
1125 return;
1126 }
1127 }
1128 #endif /* CONFIG_USER_ONLY */
1129
1130 void helper_ldf_asi(int asi, int size, int rd)
1131 {
1132 target_ulong tmp_T0 = T0, tmp_T1 = T1;
1133 unsigned int i;
1134
1135 switch (asi) {
1136 case 0xf0: // Block load primary
1137 case 0xf1: // Block load secondary
1138 case 0xf8: // Block load primary LE
1139 case 0xf9: // Block load secondary LE
1140 if (rd & 7) {
1141 raise_exception(TT_ILL_INSN);
1142 return;
1143 }
1144 if (T0 & 0x3f) {
1145 raise_exception(TT_UNALIGNED);
1146 return;
1147 }
1148 for (i = 0; i < 16; i++) {
1149 helper_ld_asi(asi & 0x8f, 4, 0);
1150 *(uint32_t *)&env->fpr[rd++] = T1;
1151 T0 += 4;
1152 }
1153 T0 = tmp_T0;
1154 T1 = tmp_T1;
1155
1156 return;
1157 default:
1158 break;
1159 }
1160
1161 helper_ld_asi(asi, size, 0);
1162 switch(size) {
1163 default:
1164 case 4:
1165 *((uint32_t *)&FT0) = T1;
1166 break;
1167 case 8:
1168 *((int64_t *)&DT0) = T1;
1169 break;
1170 }
1171 T1 = tmp_T1;
1172 }
1173
1174 void helper_stf_asi(int asi, int size, int rd)
1175 {
1176 target_ulong tmp_T0 = T0, tmp_T1 = T1;
1177 unsigned int i;
1178
1179 switch (asi) {
1180 case 0xf0: // Block store primary
1181 case 0xf1: // Block store secondary
1182 case 0xf8: // Block store primary LE
1183 case 0xf9: // Block store secondary LE
1184 if (rd & 7) {
1185 raise_exception(TT_ILL_INSN);
1186 return;
1187 }
1188 if (T0 & 0x3f) {
1189 raise_exception(TT_UNALIGNED);
1190 return;
1191 }
1192 for (i = 0; i < 16; i++) {
1193 T1 = *(uint32_t *)&env->fpr[rd++];
1194 helper_st_asi(asi & 0x8f, 4);
1195 T0 += 4;
1196 }
1197 T0 = tmp_T0;
1198 T1 = tmp_T1;
1199
1200 return;
1201 default:
1202 break;
1203 }
1204
1205 switch(size) {
1206 default:
1207 case 4:
1208 T1 = *((uint32_t *)&FT0);
1209 break;
1210 case 8:
1211 T1 = *((int64_t *)&DT0);
1212 break;
1213 }
1214 helper_st_asi(asi, size);
1215 T1 = tmp_T1;
1216 }
1217
1218 #endif /* TARGET_SPARC64 */
1219
1220 #ifndef TARGET_SPARC64
1221 void helper_rett()
1222 {
1223 unsigned int cwp;
1224
1225 if (env->psret == 1)
1226 raise_exception(TT_ILL_INSN);
1227
1228 env->psret = 1;
1229 cwp = (env->cwp + 1) & (NWINDOWS - 1);
1230 if (env->wim & (1 << cwp)) {
1231 raise_exception(TT_WIN_UNF);
1232 }
1233 set_cwp(cwp);
1234 env->psrs = env->psrps;
1235 }
1236 #endif
1237
1238 void helper_ldfsr(void)
1239 {
1240 int rnd_mode;
1241 switch (env->fsr & FSR_RD_MASK) {
1242 case FSR_RD_NEAREST:
1243 rnd_mode = float_round_nearest_even;
1244 break;
1245 default:
1246 case FSR_RD_ZERO:
1247 rnd_mode = float_round_to_zero;
1248 break;
1249 case FSR_RD_POS:
1250 rnd_mode = float_round_up;
1251 break;
1252 case FSR_RD_NEG:
1253 rnd_mode = float_round_down;
1254 break;
1255 }
1256 set_float_rounding_mode(rnd_mode, &env->fp_status);
1257 }
1258
1259 void helper_debug()
1260 {
1261 env->exception_index = EXCP_DEBUG;
1262 cpu_loop_exit();
1263 }
1264
1265 #ifndef TARGET_SPARC64
1266 void do_wrpsr()
1267 {
1268 if ((T0 & PSR_CWP) >= NWINDOWS)
1269 raise_exception(TT_ILL_INSN);
1270 else
1271 PUT_PSR(env, T0);
1272 }
1273
1274 void do_rdpsr()
1275 {
1276 T0 = GET_PSR(env);
1277 }
1278
1279 #else
1280
1281 void do_popc()
1282 {
1283 T0 = (T1 & 0x5555555555555555ULL) + ((T1 >> 1) & 0x5555555555555555ULL);
1284 T0 = (T0 & 0x3333333333333333ULL) + ((T0 >> 2) & 0x3333333333333333ULL);
1285 T0 = (T0 & 0x0f0f0f0f0f0f0f0fULL) + ((T0 >> 4) & 0x0f0f0f0f0f0f0f0fULL);
1286 T0 = (T0 & 0x00ff00ff00ff00ffULL) + ((T0 >> 8) & 0x00ff00ff00ff00ffULL);
1287 T0 = (T0 & 0x0000ffff0000ffffULL) + ((T0 >> 16) & 0x0000ffff0000ffffULL);
1288 T0 = (T0 & 0x00000000ffffffffULL) + ((T0 >> 32) & 0x00000000ffffffffULL);
1289 }
1290
1291 static inline uint64_t *get_gregset(uint64_t pstate)
1292 {
1293 switch (pstate) {
1294 default:
1295 case 0:
1296 return env->bgregs;
1297 case PS_AG:
1298 return env->agregs;
1299 case PS_MG:
1300 return env->mgregs;
1301 case PS_IG:
1302 return env->igregs;
1303 }
1304 }
1305
1306 static inline void change_pstate(uint64_t new_pstate)
1307 {
1308 uint64_t pstate_regs, new_pstate_regs;
1309 uint64_t *src, *dst;
1310
1311 pstate_regs = env->pstate & 0xc01;
1312 new_pstate_regs = new_pstate & 0xc01;
1313 if (new_pstate_regs != pstate_regs) {
1314 // Switch global register bank
1315 src = get_gregset(new_pstate_regs);
1316 dst = get_gregset(pstate_regs);
1317 memcpy32(dst, env->gregs);
1318 memcpy32(env->gregs, src);
1319 }
1320 env->pstate = new_pstate;
1321 }
1322
1323 void do_wrpstate(void)
1324 {
1325 change_pstate(T0 & 0xf3f);
1326 }
1327
1328 void do_done(void)
1329 {
1330 env->tl--;
1331 env->pc = env->tnpc[env->tl];
1332 env->npc = env->tnpc[env->tl] + 4;
1333 PUT_CCR(env, env->tstate[env->tl] >> 32);
1334 env->asi = (env->tstate[env->tl] >> 24) & 0xff;
1335 change_pstate((env->tstate[env->tl] >> 8) & 0xf3f);
1336 PUT_CWP64(env, env->tstate[env->tl] & 0xff);
1337 }
1338
1339 void do_retry(void)
1340 {
1341 env->tl--;
1342 env->pc = env->tpc[env->tl];
1343 env->npc = env->tnpc[env->tl];
1344 PUT_CCR(env, env->tstate[env->tl] >> 32);
1345 env->asi = (env->tstate[env->tl] >> 24) & 0xff;
1346 change_pstate((env->tstate[env->tl] >> 8) & 0xf3f);
1347 PUT_CWP64(env, env->tstate[env->tl] & 0xff);
1348 }
1349 #endif
1350
1351 void set_cwp(int new_cwp)
1352 {
1353 /* put the modified wrap registers at their proper location */
1354 if (env->cwp == (NWINDOWS - 1))
1355 memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
1356 env->cwp = new_cwp;
1357 /* put the wrap registers at their temporary location */
1358 if (new_cwp == (NWINDOWS - 1))
1359 memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
1360 env->regwptr = env->regbase + (new_cwp * 16);
1361 REGWPTR = env->regwptr;
1362 }
1363
1364 void cpu_set_cwp(CPUState *env1, int new_cwp)
1365 {
1366 CPUState *saved_env;
1367 #ifdef reg_REGWPTR
1368 target_ulong *saved_regwptr;
1369 #endif
1370
1371 saved_env = env;
1372 #ifdef reg_REGWPTR
1373 saved_regwptr = REGWPTR;
1374 #endif
1375 env = env1;
1376 set_cwp(new_cwp);
1377 env = saved_env;
1378 #ifdef reg_REGWPTR
1379 REGWPTR = saved_regwptr;
1380 #endif
1381 }
1382
1383 #ifdef TARGET_SPARC64
1384 void do_interrupt(int intno)
1385 {
1386 #ifdef DEBUG_PCALL
1387 if (loglevel & CPU_LOG_INT) {
1388 static int count;
1389 fprintf(logfile, "%6d: v=%04x pc=%016" PRIx64 " npc=%016" PRIx64 " SP=%016" PRIx64 "\n",
1390 count, intno,
1391 env->pc,
1392 env->npc, env->regwptr[6]);
1393 cpu_dump_state(env, logfile, fprintf, 0);
1394 #if 0
1395 {
1396 int i;
1397 uint8_t *ptr;
1398
1399 fprintf(logfile, " code=");
1400 ptr = (uint8_t *)env->pc;
1401 for(i = 0; i < 16; i++) {
1402 fprintf(logfile, " %02x", ldub(ptr + i));
1403 }
1404 fprintf(logfile, "\n");
1405 }
1406 #endif
1407 count++;
1408 }
1409 #endif
1410 #if !defined(CONFIG_USER_ONLY)
1411 if (env->tl == MAXTL) {
1412 cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
1413 return;
1414 }
1415 #endif
1416 env->tstate[env->tl] = ((uint64_t)GET_CCR(env) << 32) | ((env->asi & 0xff) << 24) |
1417 ((env->pstate & 0xf3f) << 8) | GET_CWP64(env);
1418 env->tpc[env->tl] = env->pc;
1419 env->tnpc[env->tl] = env->npc;
1420 env->tt[env->tl] = intno;
1421 change_pstate(PS_PEF | PS_PRIV | PS_AG);
1422
1423 if (intno == TT_CLRWIN)
1424 set_cwp((env->cwp - 1) & (NWINDOWS - 1));
1425 else if ((intno & 0x1c0) == TT_SPILL)
1426 set_cwp((env->cwp - env->cansave - 2) & (NWINDOWS - 1));
1427 else if ((intno & 0x1c0) == TT_FILL)
1428 set_cwp((env->cwp + 1) & (NWINDOWS - 1));
1429 env->tbr &= ~0x7fffULL;
1430 env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
1431 if (env->tl < MAXTL - 1) {
1432 env->tl++;
1433 } else {
1434 env->pstate |= PS_RED;
1435 if (env->tl != MAXTL)
1436 env->tl++;
1437 }
1438 env->pc = env->tbr;
1439 env->npc = env->pc + 4;
1440 env->exception_index = 0;
1441 }
1442 #else
1443 void do_interrupt(int intno)
1444 {
1445 int cwp;
1446
1447 #ifdef DEBUG_PCALL
1448 if (loglevel & CPU_LOG_INT) {
1449 static int count;
1450 fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
1451 count, intno,
1452 env->pc,
1453 env->npc, env->regwptr[6]);
1454 cpu_dump_state(env, logfile, fprintf, 0);
1455 #if 0
1456 {
1457 int i;
1458 uint8_t *ptr;
1459
1460 fprintf(logfile, " code=");
1461 ptr = (uint8_t *)env->pc;
1462 for(i = 0; i < 16; i++) {
1463 fprintf(logfile, " %02x", ldub(ptr + i));
1464 }
1465 fprintf(logfile, "\n");
1466 }
1467 #endif
1468 count++;
1469 }
1470 #endif
1471 #if !defined(CONFIG_USER_ONLY)
1472 if (env->psret == 0) {
1473 cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
1474 return;
1475 }
1476 #endif
1477 env->psret = 0;
1478 cwp = (env->cwp - 1) & (NWINDOWS - 1);
1479 set_cwp(cwp);
1480 env->regwptr[9] = env->pc;
1481 env->regwptr[10] = env->npc;
1482 env->psrps = env->psrs;
1483 env->psrs = 1;
1484 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
1485 env->pc = env->tbr;
1486 env->npc = env->pc + 4;
1487 env->exception_index = 0;
1488 }
1489 #endif
1490
1491 #if !defined(CONFIG_USER_ONLY)
1492
1493 static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
1494 void *retaddr);
1495
1496 #define MMUSUFFIX _mmu
1497 #define ALIGNED_ONLY
1498 #define GETPC() (__builtin_return_address(0))
1499
1500 #define SHIFT 0
1501 #include "softmmu_template.h"
1502
1503 #define SHIFT 1
1504 #include "softmmu_template.h"
1505
1506 #define SHIFT 2
1507 #include "softmmu_template.h"
1508
1509 #define SHIFT 3
1510 #include "softmmu_template.h"
1511
1512 static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
1513 void *retaddr)
1514 {
1515 #ifdef DEBUG_UNALIGNED
1516 printf("Unaligned access to 0x%x from 0x%x\n", addr, env->pc);
1517 #endif
1518 raise_exception(TT_UNALIGNED);
1519 }
1520
1521 /* try to fill the TLB and return an exception if error. If retaddr is
1522 NULL, it means that the function was called in C code (i.e. not
1523 from generated code or from helper.c) */
1524 /* XXX: fix it to restore all registers */
1525 void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
1526 {
1527 TranslationBlock *tb;
1528 int ret;
1529 unsigned long pc;
1530 CPUState *saved_env;
1531
1532 /* XXX: hack to restore env in all cases, even if not called from
1533 generated code */
1534 saved_env = env;
1535 env = cpu_single_env;
1536
1537 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, is_user, 1);
1538 if (ret) {
1539 if (retaddr) {
1540 /* now we have a real cpu fault */
1541 pc = (unsigned long)retaddr;
1542 tb = tb_find_pc(pc);
1543 if (tb) {
1544 /* the PC is inside the translated code. It means that we have
1545 a virtual CPU fault */
1546 cpu_restore_state(tb, env, pc, (void *)T2);
1547 }
1548 }
1549 cpu_loop_exit();
1550 }
1551 env = saved_env;
1552 }
1553
1554 #endif
1555
1556 #ifndef TARGET_SPARC64
1557 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
1558 int is_asi)
1559 {
1560 CPUState *saved_env;
1561
1562 /* XXX: hack to restore env in all cases, even if not called from
1563 generated code */
1564 saved_env = env;
1565 env = cpu_single_env;
1566 if (env->mmuregs[3]) /* Fault status register */
1567 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
1568 if (is_asi)
1569 env->mmuregs[3] |= 1 << 16;
1570 if (env->psrs)
1571 env->mmuregs[3] |= 1 << 5;
1572 if (is_exec)
1573 env->mmuregs[3] |= 1 << 6;
1574 if (is_write)
1575 env->mmuregs[3] |= 1 << 7;
1576 env->mmuregs[3] |= (5 << 2) | 2;
1577 env->mmuregs[4] = addr; /* Fault address register */
1578 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
1579 #ifdef DEBUG_UNASSIGNED
1580 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
1581 "\n", addr, env->pc);
1582 #endif
1583 if (is_exec)
1584 raise_exception(TT_CODE_ACCESS);
1585 else
1586 raise_exception(TT_DATA_ACCESS);
1587 }
1588 env = saved_env;
1589 }
1590 #else
1591 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
1592 int is_asi)
1593 {
1594 #ifdef DEBUG_UNASSIGNED
1595 CPUState *saved_env;
1596
1597 /* XXX: hack to restore env in all cases, even if not called from
1598 generated code */
1599 saved_env = env;
1600 env = cpu_single_env;
1601 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx "\n",
1602 addr, env->pc);
1603 env = saved_env;
1604 #endif
1605 if (is_exec)
1606 raise_exception(TT_CODE_ACCESS);
1607 else
1608 raise_exception(TT_DATA_ACCESS);
1609 }
1610 #endif
1611
1612 #ifdef TARGET_SPARC64
1613 void do_tick_set_count(void *opaque, uint64_t count)
1614 {
1615 #if !defined(CONFIG_USER_ONLY)
1616 ptimer_set_count(opaque, -count);
1617 #endif
1618 }
1619
1620 uint64_t do_tick_get_count(void *opaque)
1621 {
1622 #if !defined(CONFIG_USER_ONLY)
1623 return -ptimer_get_count(opaque);
1624 #else
1625 return 0;
1626 #endif
1627 }
1628
1629 void do_tick_set_limit(void *opaque, uint64_t limit)
1630 {
1631 #if !defined(CONFIG_USER_ONLY)
1632 ptimer_set_limit(opaque, -limit, 0);
1633 #endif
1634 }
1635 #endif
Qemu copy for testing