]>
git.proxmox.com Git - qemu.git/blob - target-sparc/op_helper.c
2 #include "dyngen-exec.h"
5 #if !defined(CONFIG_USER_ONLY)
6 #include "softmmu_exec.h"
11 //#define DEBUG_UNALIGNED
12 //#define DEBUG_UNASSIGNED
14 //#define DEBUG_PSTATE
15 //#define DEBUG_CACHE_CONTROL
18 #define DPRINTF_MMU(fmt, ...) \
19 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
21 #define DPRINTF_MMU(fmt, ...) do {} while (0)
25 #define DPRINTF_MXCC(fmt, ...) \
26 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
28 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
32 #define DPRINTF_ASI(fmt, ...) \
33 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
37 #define DPRINTF_PSTATE(fmt, ...) \
38 do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0)
40 #define DPRINTF_PSTATE(fmt, ...) do {} while (0)
43 #ifdef DEBUG_CACHE_CONTROL
44 #define DPRINTF_CACHE_CONTROL(fmt, ...) \
45 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
47 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
52 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
54 #define AM_CHECK(env1) (1)
58 #define DT0 (env->dt0)
59 #define DT1 (env->dt1)
60 #define QT0 (env->qt0)
61 #define QT1 (env->qt1)
63 /* Leon3 cache control */
65 /* Cache control: emulate the behavior of cache control registers but without
66 any effect on the emulated */
68 #define CACHE_STATE_MASK 0x3
69 #define CACHE_DISABLED 0x0
70 #define CACHE_FROZEN 0x1
71 #define CACHE_ENABLED 0x3
73 /* Cache Control register fields */
75 #define CACHE_CTRL_IF (1 << 4) /* Instruction Cache Freeze on Interrupt */
76 #define CACHE_CTRL_DF (1 << 5) /* Data Cache Freeze on Interrupt */
77 #define CACHE_CTRL_DP (1 << 14) /* Data cache flush pending */
78 #define CACHE_CTRL_IP (1 << 15) /* Instruction cache flush pending */
79 #define CACHE_CTRL_IB (1 << 16) /* Instruction burst fetch */
80 #define CACHE_CTRL_FI (1 << 21) /* Flush Instruction cache (Write only) */
81 #define CACHE_CTRL_FD (1 << 22) /* Flush Data cache (Write only) */
82 #define CACHE_CTRL_DS (1 << 23) /* Data cache snoop enable */
84 #if !defined(CONFIG_USER_ONLY)
85 static void do_unassigned_access(target_phys_addr_t addr
, int is_write
,
86 int is_exec
, int is_asi
, int size
);
89 static void do_unassigned_access(target_ulong addr
, int is_write
, int is_exec
,
90 int is_asi
, int size
);
94 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
95 /* Calculates TSB pointer value for fault page size 8k or 64k */
96 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register
,
97 uint64_t tag_access_register
,
100 uint64_t tsb_base
= tsb_register
& ~0x1fffULL
;
101 int tsb_split
= (tsb_register
& 0x1000ULL
) ? 1 : 0;
102 int tsb_size
= tsb_register
& 0xf;
104 /* discard lower 13 bits which hold tag access context */
105 uint64_t tag_access_va
= tag_access_register
& ~0x1fffULL
;
107 /* now reorder bits */
108 uint64_t tsb_base_mask
= ~0x1fffULL
;
109 uint64_t va
= tag_access_va
;
111 /* move va bits to correct position */
112 if (page_size
== 8*1024) {
114 } else if (page_size
== 64*1024) {
119 tsb_base_mask
<<= tsb_size
;
122 /* calculate tsb_base mask and adjust va if split is in use */
124 if (page_size
== 8*1024) {
125 va
&= ~(1ULL << (13 + tsb_size
));
126 } else if (page_size
== 64*1024) {
127 va
|= (1ULL << (13 + tsb_size
));
132 return ((tsb_base
& tsb_base_mask
) | (va
& ~tsb_base_mask
)) & ~0xfULL
;
135 /* Calculates tag target register value by reordering bits
136 in tag access register */
137 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register
)
139 return ((tag_access_register
& 0x1fff) << 48) | (tag_access_register
>> 22);
142 static void replace_tlb_entry(SparcTLBEntry
*tlb
,
143 uint64_t tlb_tag
, uint64_t tlb_tte
,
146 target_ulong mask
, size
, va
, offset
;
148 /* flush page range if translation is valid */
149 if (TTE_IS_VALID(tlb
->tte
)) {
151 mask
= 0xffffffffffffe000ULL
;
152 mask
<<= 3 * ((tlb
->tte
>> 61) & 3);
155 va
= tlb
->tag
& mask
;
157 for (offset
= 0; offset
< size
; offset
+= TARGET_PAGE_SIZE
) {
158 tlb_flush_page(env1
, va
+ offset
);
166 static void demap_tlb(SparcTLBEntry
*tlb
, target_ulong demap_addr
,
167 const char *strmmu
, CPUState
*env1
)
173 int is_demap_context
= (demap_addr
>> 6) & 1;
176 switch ((demap_addr
>> 4) & 3) {
177 case 0: /* primary */
178 context
= env1
->dmmu
.mmu_primary_context
;
180 case 1: /* secondary */
181 context
= env1
->dmmu
.mmu_secondary_context
;
183 case 2: /* nucleus */
186 case 3: /* reserved */
191 for (i
= 0; i
< 64; i
++) {
192 if (TTE_IS_VALID(tlb
[i
].tte
)) {
194 if (is_demap_context
) {
195 /* will remove non-global entries matching context value */
196 if (TTE_IS_GLOBAL(tlb
[i
].tte
) ||
197 !tlb_compare_context(&tlb
[i
], context
)) {
202 will remove any entry matching VA */
203 mask
= 0xffffffffffffe000ULL
;
204 mask
<<= 3 * ((tlb
[i
].tte
>> 61) & 3);
206 if (!compare_masked(demap_addr
, tlb
[i
].tag
, mask
)) {
210 /* entry should be global or matching context value */
211 if (!TTE_IS_GLOBAL(tlb
[i
].tte
) &&
212 !tlb_compare_context(&tlb
[i
], context
)) {
217 replace_tlb_entry(&tlb
[i
], 0, 0, env1
);
219 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu
, i
);
220 dump_mmu(stdout
, fprintf
, env1
);
226 static void replace_tlb_1bit_lru(SparcTLBEntry
*tlb
,
227 uint64_t tlb_tag
, uint64_t tlb_tte
,
228 const char *strmmu
, CPUState
*env1
)
230 unsigned int i
, replace_used
;
232 /* Try replacing invalid entry */
233 for (i
= 0; i
< 64; i
++) {
234 if (!TTE_IS_VALID(tlb
[i
].tte
)) {
235 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
237 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu
, i
);
238 dump_mmu(stdout
, fprintf
, env1
);
244 /* All entries are valid, try replacing unlocked entry */
246 for (replace_used
= 0; replace_used
< 2; ++replace_used
) {
248 /* Used entries are not replaced on first pass */
250 for (i
= 0; i
< 64; i
++) {
251 if (!TTE_IS_LOCKED(tlb
[i
].tte
) && !TTE_IS_USED(tlb
[i
].tte
)) {
253 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
255 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
256 strmmu
, (replace_used
? "used" : "unused"), i
);
257 dump_mmu(stdout
, fprintf
, env1
);
263 /* Now reset used bit and search for unused entries again */
265 for (i
= 0; i
< 64; i
++) {
266 TTE_SET_UNUSED(tlb
[i
].tte
);
271 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu
);
278 static inline target_ulong
address_mask(CPUState
*env1
, target_ulong addr
)
280 #ifdef TARGET_SPARC64
281 if (AM_CHECK(env1
)) {
282 addr
&= 0xffffffffULL
;
288 /* returns true if access using this ASI is to have address translated by MMU
289 otherwise access is to raw physical address */
290 static inline int is_translating_asi(int asi
)
292 #ifdef TARGET_SPARC64
293 /* Ultrasparc IIi translating asi
294 - note this list is defined by cpu implementation
310 /* TODO: check sparc32 bits */
315 static inline target_ulong
asi_address_mask(CPUState
*env1
,
316 int asi
, target_ulong addr
)
318 if (is_translating_asi(asi
)) {
319 return address_mask(env
, addr
);
325 void helper_check_align(target_ulong addr
, uint32_t align
)
328 #ifdef DEBUG_UNALIGNED
329 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
330 "\n", addr
, env
->pc
);
332 helper_raise_exception(env
, TT_UNALIGNED
);
336 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
338 static void dump_mxcc(CPUState
*env
)
340 printf("mxccdata: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
342 env
->mxccdata
[0], env
->mxccdata
[1],
343 env
->mxccdata
[2], env
->mxccdata
[3]);
344 printf("mxccregs: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
346 " %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
348 env
->mxccregs
[0], env
->mxccregs
[1],
349 env
->mxccregs
[2], env
->mxccregs
[3],
350 env
->mxccregs
[4], env
->mxccregs
[5],
351 env
->mxccregs
[6], env
->mxccregs
[7]);
355 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
356 && defined(DEBUG_ASI)
357 static void dump_asi(const char *txt
, target_ulong addr
, int asi
, int size
,
362 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %02" PRIx64
"\n", txt
,
363 addr
, asi
, r1
& 0xff);
366 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %04" PRIx64
"\n", txt
,
367 addr
, asi
, r1
& 0xffff);
370 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %08" PRIx64
"\n", txt
,
371 addr
, asi
, r1
& 0xffffffff);
374 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %016" PRIx64
"\n", txt
,
381 #ifndef TARGET_SPARC64
382 #ifndef CONFIG_USER_ONLY
385 /* Leon3 cache control */
387 static void leon3_cache_control_int(void)
391 if (env
->cache_control
& CACHE_CTRL_IF
) {
392 /* Instruction cache state */
393 state
= env
->cache_control
& CACHE_STATE_MASK
;
394 if (state
== CACHE_ENABLED
) {
395 state
= CACHE_FROZEN
;
396 DPRINTF_CACHE_CONTROL("Instruction cache: freeze\n");
399 env
->cache_control
&= ~CACHE_STATE_MASK
;
400 env
->cache_control
|= state
;
403 if (env
->cache_control
& CACHE_CTRL_DF
) {
404 /* Data cache state */
405 state
= (env
->cache_control
>> 2) & CACHE_STATE_MASK
;
406 if (state
== CACHE_ENABLED
) {
407 state
= CACHE_FROZEN
;
408 DPRINTF_CACHE_CONTROL("Data cache: freeze\n");
411 env
->cache_control
&= ~(CACHE_STATE_MASK
<< 2);
412 env
->cache_control
|= (state
<< 2);
416 static void leon3_cache_control_st(target_ulong addr
, uint64_t val
, int size
)
418 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64
", size:%d\n",
422 DPRINTF_CACHE_CONTROL("32bits only\n");
427 case 0x00: /* Cache control */
429 /* These values must always be read as zeros */
430 val
&= ~CACHE_CTRL_FD
;
431 val
&= ~CACHE_CTRL_FI
;
432 val
&= ~CACHE_CTRL_IB
;
433 val
&= ~CACHE_CTRL_IP
;
434 val
&= ~CACHE_CTRL_DP
;
436 env
->cache_control
= val
;
438 case 0x04: /* Instruction cache configuration */
439 case 0x08: /* Data cache configuration */
443 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr
);
448 static uint64_t leon3_cache_control_ld(target_ulong addr
, int size
)
453 DPRINTF_CACHE_CONTROL("32bits only\n");
458 case 0x00: /* Cache control */
459 ret
= env
->cache_control
;
462 /* Configuration registers are read and only always keep those
465 case 0x04: /* Instruction cache configuration */
468 case 0x08: /* Data cache configuration */
472 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr
);
475 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64
", size:%d\n",
480 void leon3_irq_manager(void *irq_manager
, int intno
)
482 leon3_irq_ack(irq_manager
, intno
);
483 leon3_cache_control_int();
486 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
489 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
490 uint32_t last_addr
= addr
;
493 helper_check_align(addr
, size
- 1);
495 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
497 case 0x00: /* Leon3 Cache Control */
498 case 0x08: /* Leon3 Instruction Cache config */
499 case 0x0C: /* Leon3 Date Cache config */
500 if (env
->def
->features
& CPU_FEATURE_CACHE_CTRL
) {
501 ret
= leon3_cache_control_ld(addr
, size
);
504 case 0x01c00a00: /* MXCC control register */
506 ret
= env
->mxccregs
[3];
508 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
512 case 0x01c00a04: /* MXCC control register */
514 ret
= env
->mxccregs
[3];
516 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
520 case 0x01c00c00: /* Module reset register */
522 ret
= env
->mxccregs
[5];
523 /* should we do something here? */
525 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
529 case 0x01c00f00: /* MBus port address register */
531 ret
= env
->mxccregs
[7];
533 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
538 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr
,
542 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
543 "addr = %08x -> ret = %" PRIx64
","
544 "addr = %08x\n", asi
, size
, sign
, last_addr
, ret
, addr
);
549 case 3: /* MMU probe */
553 mmulev
= (addr
>> 8) & 15;
557 ret
= mmu_probe(env
, addr
, mmulev
);
559 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64
"\n",
563 case 4: /* read MMU regs */
565 int reg
= (addr
>> 8) & 0x1f;
567 ret
= env
->mmuregs
[reg
];
568 if (reg
== 3) { /* Fault status cleared on read */
570 } else if (reg
== 0x13) { /* Fault status read */
571 ret
= env
->mmuregs
[3];
572 } else if (reg
== 0x14) { /* Fault address read */
573 ret
= env
->mmuregs
[4];
575 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64
"\n", reg
, ret
);
578 case 5: /* Turbosparc ITLB Diagnostic */
579 case 6: /* Turbosparc DTLB Diagnostic */
580 case 7: /* Turbosparc IOTLB Diagnostic */
582 case 9: /* Supervisor code access */
585 ret
= ldub_code(addr
);
588 ret
= lduw_code(addr
);
592 ret
= ldl_code(addr
);
595 ret
= ldq_code(addr
);
599 case 0xa: /* User data access */
602 ret
= ldub_user(addr
);
605 ret
= lduw_user(addr
);
609 ret
= ldl_user(addr
);
612 ret
= ldq_user(addr
);
616 case 0xb: /* Supervisor data access */
619 ret
= ldub_kernel(addr
);
622 ret
= lduw_kernel(addr
);
626 ret
= ldl_kernel(addr
);
629 ret
= ldq_kernel(addr
);
633 case 0xc: /* I-cache tag */
634 case 0xd: /* I-cache data */
635 case 0xe: /* D-cache tag */
636 case 0xf: /* D-cache data */
638 case 0x20: /* MMU passthrough */
641 ret
= ldub_phys(addr
);
644 ret
= lduw_phys(addr
);
648 ret
= ldl_phys(addr
);
651 ret
= ldq_phys(addr
);
655 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
658 ret
= ldub_phys((target_phys_addr_t
)addr
659 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
662 ret
= lduw_phys((target_phys_addr_t
)addr
663 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
667 ret
= ldl_phys((target_phys_addr_t
)addr
668 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
671 ret
= ldq_phys((target_phys_addr_t
)addr
672 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
676 case 0x30: /* Turbosparc secondary cache diagnostic */
677 case 0x31: /* Turbosparc RAM snoop */
678 case 0x32: /* Turbosparc page table descriptor diagnostic */
679 case 0x39: /* data cache diagnostic register */
682 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
684 int reg
= (addr
>> 8) & 3;
687 case 0: /* Breakpoint Value (Addr) */
688 ret
= env
->mmubpregs
[reg
];
690 case 1: /* Breakpoint Mask */
691 ret
= env
->mmubpregs
[reg
];
693 case 2: /* Breakpoint Control */
694 ret
= env
->mmubpregs
[reg
];
696 case 3: /* Breakpoint Status */
697 ret
= env
->mmubpregs
[reg
];
698 env
->mmubpregs
[reg
] = 0ULL;
701 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64
"\n", reg
,
705 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
706 ret
= env
->mmubpctrv
;
708 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
709 ret
= env
->mmubpctrc
;
711 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
712 ret
= env
->mmubpctrs
;
714 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
715 ret
= env
->mmubpaction
;
717 case 8: /* User code access, XXX */
719 do_unassigned_access(addr
, 0, 0, asi
, size
);
739 dump_asi("read ", last_addr
, asi
, size
, ret
);
744 void helper_st_asi(target_ulong addr
, uint64_t val
, int asi
, int size
)
746 helper_check_align(addr
, size
- 1);
748 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
750 case 0x00: /* Leon3 Cache Control */
751 case 0x08: /* Leon3 Instruction Cache config */
752 case 0x0C: /* Leon3 Date Cache config */
753 if (env
->def
->features
& CPU_FEATURE_CACHE_CTRL
) {
754 leon3_cache_control_st(addr
, val
, size
);
758 case 0x01c00000: /* MXCC stream data register 0 */
760 env
->mxccdata
[0] = val
;
762 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
766 case 0x01c00008: /* MXCC stream data register 1 */
768 env
->mxccdata
[1] = val
;
770 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
774 case 0x01c00010: /* MXCC stream data register 2 */
776 env
->mxccdata
[2] = val
;
778 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
782 case 0x01c00018: /* MXCC stream data register 3 */
784 env
->mxccdata
[3] = val
;
786 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
790 case 0x01c00100: /* MXCC stream source */
792 env
->mxccregs
[0] = val
;
794 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
797 env
->mxccdata
[0] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
799 env
->mxccdata
[1] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
801 env
->mxccdata
[2] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
803 env
->mxccdata
[3] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
806 case 0x01c00200: /* MXCC stream destination */
808 env
->mxccregs
[1] = val
;
810 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
813 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 0,
815 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 8,
817 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 16,
819 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 24,
822 case 0x01c00a00: /* MXCC control register */
824 env
->mxccregs
[3] = val
;
826 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
830 case 0x01c00a04: /* MXCC control register */
832 env
->mxccregs
[3] = (env
->mxccregs
[3] & 0xffffffff00000000ULL
)
835 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
839 case 0x01c00e00: /* MXCC error register */
840 /* writing a 1 bit clears the error */
842 env
->mxccregs
[6] &= ~val
;
844 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
848 case 0x01c00f00: /* MBus port address register */
850 env
->mxccregs
[7] = val
;
852 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
857 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr
,
861 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64
"\n",
862 asi
, size
, addr
, val
);
867 case 3: /* MMU flush */
871 mmulev
= (addr
>> 8) & 15;
872 DPRINTF_MMU("mmu flush level %d\n", mmulev
);
874 case 0: /* flush page */
875 tlb_flush_page(env
, addr
& 0xfffff000);
877 case 1: /* flush segment (256k) */
878 case 2: /* flush region (16M) */
879 case 3: /* flush context (4G) */
880 case 4: /* flush entire */
887 dump_mmu(stdout
, fprintf
, env
);
891 case 4: /* write MMU regs */
893 int reg
= (addr
>> 8) & 0x1f;
896 oldreg
= env
->mmuregs
[reg
];
898 case 0: /* Control Register */
899 env
->mmuregs
[reg
] = (env
->mmuregs
[reg
] & 0xff000000) |
901 /* Mappings generated during no-fault mode or MMU
902 disabled mode are invalid in normal mode */
903 if ((oldreg
& (MMU_E
| MMU_NF
| env
->def
->mmu_bm
)) !=
904 (env
->mmuregs
[reg
] & (MMU_E
| MMU_NF
| env
->def
->mmu_bm
))) {
908 case 1: /* Context Table Pointer Register */
909 env
->mmuregs
[reg
] = val
& env
->def
->mmu_ctpr_mask
;
911 case 2: /* Context Register */
912 env
->mmuregs
[reg
] = val
& env
->def
->mmu_cxr_mask
;
913 if (oldreg
!= env
->mmuregs
[reg
]) {
914 /* we flush when the MMU context changes because
915 QEMU has no MMU context support */
919 case 3: /* Synchronous Fault Status Register with Clear */
920 case 4: /* Synchronous Fault Address Register */
922 case 0x10: /* TLB Replacement Control Register */
923 env
->mmuregs
[reg
] = val
& env
->def
->mmu_trcr_mask
;
925 case 0x13: /* Synchronous Fault Status Register with Read
927 env
->mmuregs
[3] = val
& env
->def
->mmu_sfsr_mask
;
929 case 0x14: /* Synchronous Fault Address Register */
930 env
->mmuregs
[4] = val
;
933 env
->mmuregs
[reg
] = val
;
936 if (oldreg
!= env
->mmuregs
[reg
]) {
937 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
938 reg
, oldreg
, env
->mmuregs
[reg
]);
941 dump_mmu(stdout
, fprintf
, env
);
945 case 5: /* Turbosparc ITLB Diagnostic */
946 case 6: /* Turbosparc DTLB Diagnostic */
947 case 7: /* Turbosparc IOTLB Diagnostic */
949 case 0xa: /* User data access */
966 case 0xb: /* Supervisor data access */
969 stb_kernel(addr
, val
);
972 stw_kernel(addr
, val
);
976 stl_kernel(addr
, val
);
979 stq_kernel(addr
, val
);
983 case 0xc: /* I-cache tag */
984 case 0xd: /* I-cache data */
985 case 0xe: /* D-cache tag */
986 case 0xf: /* D-cache data */
987 case 0x10: /* I/D-cache flush page */
988 case 0x11: /* I/D-cache flush segment */
989 case 0x12: /* I/D-cache flush region */
990 case 0x13: /* I/D-cache flush context */
991 case 0x14: /* I/D-cache flush user */
993 case 0x17: /* Block copy, sta access */
999 uint32_t src
= val
& ~3, dst
= addr
& ~3, temp
;
1001 for (i
= 0; i
< 32; i
+= 4, src
+= 4, dst
+= 4) {
1002 temp
= ldl_kernel(src
);
1003 stl_kernel(dst
, temp
);
1007 case 0x1f: /* Block fill, stda access */
1010 fill 32 bytes with val */
1012 uint32_t dst
= addr
& 7;
1014 for (i
= 0; i
< 32; i
+= 8, dst
+= 8) {
1015 stq_kernel(dst
, val
);
1019 case 0x20: /* MMU passthrough */
1023 stb_phys(addr
, val
);
1026 stw_phys(addr
, val
);
1030 stl_phys(addr
, val
);
1033 stq_phys(addr
, val
);
1038 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1042 stb_phys((target_phys_addr_t
)addr
1043 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
1046 stw_phys((target_phys_addr_t
)addr
1047 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
1051 stl_phys((target_phys_addr_t
)addr
1052 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
1055 stq_phys((target_phys_addr_t
)addr
1056 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
1061 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */
1062 case 0x31: /* store buffer data, Ross RT620 I-cache flush or
1063 Turbosparc snoop RAM */
1064 case 0x32: /* store buffer control or Turbosparc page table
1065 descriptor diagnostic */
1066 case 0x36: /* I-cache flash clear */
1067 case 0x37: /* D-cache flash clear */
1069 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1071 int reg
= (addr
>> 8) & 3;
1074 case 0: /* Breakpoint Value (Addr) */
1075 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
1077 case 1: /* Breakpoint Mask */
1078 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
1080 case 2: /* Breakpoint Control */
1081 env
->mmubpregs
[reg
] = (val
& 0x7fULL
);
1083 case 3: /* Breakpoint Status */
1084 env
->mmubpregs
[reg
] = (val
& 0xfULL
);
1087 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg
,
1091 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
1092 env
->mmubpctrv
= val
& 0xffffffff;
1094 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
1095 env
->mmubpctrc
= val
& 0x3;
1097 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
1098 env
->mmubpctrs
= val
& 0x3;
1100 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
1101 env
->mmubpaction
= val
& 0x1fff;
1103 case 8: /* User code access, XXX */
1104 case 9: /* Supervisor code access, XXX */
1106 do_unassigned_access(addr
, 1, 0, asi
, size
);
1110 dump_asi("write", addr
, asi
, size
, val
);
1114 #endif /* CONFIG_USER_ONLY */
1115 #else /* TARGET_SPARC64 */
1117 #ifdef CONFIG_USER_ONLY
1118 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
1121 #if defined(DEBUG_ASI)
1122 target_ulong last_addr
= addr
;
1126 helper_raise_exception(env
, TT_PRIV_ACT
);
1129 helper_check_align(addr
, size
- 1);
1130 addr
= asi_address_mask(env
, asi
, addr
);
1133 case 0x82: /* Primary no-fault */
1134 case 0x8a: /* Primary no-fault LE */
1135 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
1137 dump_asi("read ", last_addr
, asi
, size
, ret
);
1142 case 0x80: /* Primary */
1143 case 0x88: /* Primary LE */
1147 ret
= ldub_raw(addr
);
1150 ret
= lduw_raw(addr
);
1153 ret
= ldl_raw(addr
);
1157 ret
= ldq_raw(addr
);
1162 case 0x83: /* Secondary no-fault */
1163 case 0x8b: /* Secondary no-fault LE */
1164 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
1166 dump_asi("read ", last_addr
, asi
, size
, ret
);
1171 case 0x81: /* Secondary */
1172 case 0x89: /* Secondary LE */
1179 /* Convert from little endian */
1181 case 0x88: /* Primary LE */
1182 case 0x89: /* Secondary LE */
1183 case 0x8a: /* Primary no-fault LE */
1184 case 0x8b: /* Secondary no-fault LE */
1202 /* Convert to signed number */
1209 ret
= (int16_t) ret
;
1212 ret
= (int32_t) ret
;
1219 dump_asi("read ", last_addr
, asi
, size
, ret
);
1224 void helper_st_asi(target_ulong addr
, target_ulong val
, int asi
, int size
)
1227 dump_asi("write", addr
, asi
, size
, val
);
1230 helper_raise_exception(env
, TT_PRIV_ACT
);
1233 helper_check_align(addr
, size
- 1);
1234 addr
= asi_address_mask(env
, asi
, addr
);
1236 /* Convert to little endian */
1238 case 0x88: /* Primary LE */
1239 case 0x89: /* Secondary LE */
1258 case 0x80: /* Primary */
1259 case 0x88: /* Primary LE */
1278 case 0x81: /* Secondary */
1279 case 0x89: /* Secondary LE */
1283 case 0x82: /* Primary no-fault, RO */
1284 case 0x83: /* Secondary no-fault, RO */
1285 case 0x8a: /* Primary no-fault LE, RO */
1286 case 0x8b: /* Secondary no-fault LE, RO */
1288 do_unassigned_access(addr
, 1, 0, 1, size
);
1293 #else /* CONFIG_USER_ONLY */
1295 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
1298 #if defined(DEBUG_ASI)
1299 target_ulong last_addr
= addr
;
1304 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
1305 || (cpu_has_hypervisor(env
)
1306 && asi
>= 0x30 && asi
< 0x80
1307 && !(env
->hpstate
& HS_PRIV
))) {
1308 helper_raise_exception(env
, TT_PRIV_ACT
);
1311 helper_check_align(addr
, size
- 1);
1312 addr
= asi_address_mask(env
, asi
, addr
);
1314 /* process nonfaulting loads first */
1315 if ((asi
& 0xf6) == 0x82) {
1318 /* secondary space access has lowest asi bit equal to 1 */
1319 if (env
->pstate
& PS_PRIV
) {
1320 mmu_idx
= (asi
& 1) ? MMU_KERNEL_SECONDARY_IDX
: MMU_KERNEL_IDX
;
1322 mmu_idx
= (asi
& 1) ? MMU_USER_SECONDARY_IDX
: MMU_USER_IDX
;
1325 if (cpu_get_phys_page_nofault(env
, addr
, mmu_idx
) == -1ULL) {
1327 dump_asi("read ", last_addr
, asi
, size
, ret
);
1329 /* env->exception_index is set in get_physical_address_data(). */
1330 helper_raise_exception(env
, env
->exception_index
);
1333 /* convert nonfaulting load ASIs to normal load ASIs */
1338 case 0x10: /* As if user primary */
1339 case 0x11: /* As if user secondary */
1340 case 0x18: /* As if user primary LE */
1341 case 0x19: /* As if user secondary LE */
1342 case 0x80: /* Primary */
1343 case 0x81: /* Secondary */
1344 case 0x88: /* Primary LE */
1345 case 0x89: /* Secondary LE */
1346 case 0xe2: /* UA2007 Primary block init */
1347 case 0xe3: /* UA2007 Secondary block init */
1348 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
1349 if (cpu_hypervisor_mode(env
)) {
1352 ret
= ldub_hypv(addr
);
1355 ret
= lduw_hypv(addr
);
1358 ret
= ldl_hypv(addr
);
1362 ret
= ldq_hypv(addr
);
1366 /* secondary space access has lowest asi bit equal to 1 */
1370 ret
= ldub_kernel_secondary(addr
);
1373 ret
= lduw_kernel_secondary(addr
);
1376 ret
= ldl_kernel_secondary(addr
);
1380 ret
= ldq_kernel_secondary(addr
);
1386 ret
= ldub_kernel(addr
);
1389 ret
= lduw_kernel(addr
);
1392 ret
= ldl_kernel(addr
);
1396 ret
= ldq_kernel(addr
);
1402 /* secondary space access has lowest asi bit equal to 1 */
1406 ret
= ldub_user_secondary(addr
);
1409 ret
= lduw_user_secondary(addr
);
1412 ret
= ldl_user_secondary(addr
);
1416 ret
= ldq_user_secondary(addr
);
1422 ret
= ldub_user(addr
);
1425 ret
= lduw_user(addr
);
1428 ret
= ldl_user(addr
);
1432 ret
= ldq_user(addr
);
1438 case 0x14: /* Bypass */
1439 case 0x15: /* Bypass, non-cacheable */
1440 case 0x1c: /* Bypass LE */
1441 case 0x1d: /* Bypass, non-cacheable LE */
1445 ret
= ldub_phys(addr
);
1448 ret
= lduw_phys(addr
);
1451 ret
= ldl_phys(addr
);
1455 ret
= ldq_phys(addr
);
1460 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1461 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1462 Only ldda allowed */
1463 helper_raise_exception(env
, TT_ILL_INSN
);
1465 case 0x04: /* Nucleus */
1466 case 0x0c: /* Nucleus Little Endian (LE) */
1470 ret
= ldub_nucleus(addr
);
1473 ret
= lduw_nucleus(addr
);
1476 ret
= ldl_nucleus(addr
);
1480 ret
= ldq_nucleus(addr
);
1485 case 0x4a: /* UPA config */
1488 case 0x45: /* LSU */
1491 case 0x50: /* I-MMU regs */
1493 int reg
= (addr
>> 3) & 0xf;
1496 /* I-TSB Tag Target register */
1497 ret
= ultrasparc_tag_target(env
->immu
.tag_access
);
1499 ret
= env
->immuregs
[reg
];
1504 case 0x51: /* I-MMU 8k TSB pointer */
1506 /* env->immuregs[5] holds I-MMU TSB register value
1507 env->immuregs[6] holds I-MMU Tag Access register value */
1508 ret
= ultrasparc_tsb_pointer(env
->immu
.tsb
, env
->immu
.tag_access
,
1512 case 0x52: /* I-MMU 64k TSB pointer */
1514 /* env->immuregs[5] holds I-MMU TSB register value
1515 env->immuregs[6] holds I-MMU Tag Access register value */
1516 ret
= ultrasparc_tsb_pointer(env
->immu
.tsb
, env
->immu
.tag_access
,
1520 case 0x55: /* I-MMU data access */
1522 int reg
= (addr
>> 3) & 0x3f;
1524 ret
= env
->itlb
[reg
].tte
;
1527 case 0x56: /* I-MMU tag read */
1529 int reg
= (addr
>> 3) & 0x3f;
1531 ret
= env
->itlb
[reg
].tag
;
1534 case 0x58: /* D-MMU regs */
1536 int reg
= (addr
>> 3) & 0xf;
1539 /* D-TSB Tag Target register */
1540 ret
= ultrasparc_tag_target(env
->dmmu
.tag_access
);
1542 ret
= env
->dmmuregs
[reg
];
1546 case 0x59: /* D-MMU 8k TSB pointer */
1548 /* env->dmmuregs[5] holds D-MMU TSB register value
1549 env->dmmuregs[6] holds D-MMU Tag Access register value */
1550 ret
= ultrasparc_tsb_pointer(env
->dmmu
.tsb
, env
->dmmu
.tag_access
,
1554 case 0x5a: /* D-MMU 64k TSB pointer */
1556 /* env->dmmuregs[5] holds D-MMU TSB register value
1557 env->dmmuregs[6] holds D-MMU Tag Access register value */
1558 ret
= ultrasparc_tsb_pointer(env
->dmmu
.tsb
, env
->dmmu
.tag_access
,
1562 case 0x5d: /* D-MMU data access */
1564 int reg
= (addr
>> 3) & 0x3f;
1566 ret
= env
->dtlb
[reg
].tte
;
1569 case 0x5e: /* D-MMU tag read */
1571 int reg
= (addr
>> 3) & 0x3f;
1573 ret
= env
->dtlb
[reg
].tag
;
1576 case 0x46: /* D-cache data */
1577 case 0x47: /* D-cache tag access */
1578 case 0x4b: /* E-cache error enable */
1579 case 0x4c: /* E-cache asynchronous fault status */
1580 case 0x4d: /* E-cache asynchronous fault address */
1581 case 0x4e: /* E-cache tag data */
1582 case 0x66: /* I-cache instruction access */
1583 case 0x67: /* I-cache tag access */
1584 case 0x6e: /* I-cache predecode */
1585 case 0x6f: /* I-cache LRU etc. */
1586 case 0x76: /* E-cache tag */
1587 case 0x7e: /* E-cache tag */
1589 case 0x5b: /* D-MMU data pointer */
1590 case 0x48: /* Interrupt dispatch, RO */
1591 case 0x49: /* Interrupt data receive */
1592 case 0x7f: /* Incoming interrupt vector, RO */
1595 case 0x54: /* I-MMU data in, WO */
1596 case 0x57: /* I-MMU demap, WO */
1597 case 0x5c: /* D-MMU data in, WO */
1598 case 0x5f: /* D-MMU demap, WO */
1599 case 0x77: /* Interrupt vector, WO */
1601 do_unassigned_access(addr
, 0, 0, 1, size
);
1606 /* Convert from little endian */
1608 case 0x0c: /* Nucleus Little Endian (LE) */
1609 case 0x18: /* As if user primary LE */
1610 case 0x19: /* As if user secondary LE */
1611 case 0x1c: /* Bypass LE */
1612 case 0x1d: /* Bypass, non-cacheable LE */
1613 case 0x88: /* Primary LE */
1614 case 0x89: /* Secondary LE */
1632 /* Convert to signed number */
1639 ret
= (int16_t) ret
;
1642 ret
= (int32_t) ret
;
1649 dump_asi("read ", last_addr
, asi
, size
, ret
);
1654 void helper_st_asi(target_ulong addr
, target_ulong val
, int asi
, int size
)
1657 dump_asi("write", addr
, asi
, size
, val
);
1662 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
1663 || (cpu_has_hypervisor(env
)
1664 && asi
>= 0x30 && asi
< 0x80
1665 && !(env
->hpstate
& HS_PRIV
))) {
1666 helper_raise_exception(env
, TT_PRIV_ACT
);
1669 helper_check_align(addr
, size
- 1);
1670 addr
= asi_address_mask(env
, asi
, addr
);
1672 /* Convert to little endian */
1674 case 0x0c: /* Nucleus Little Endian (LE) */
1675 case 0x18: /* As if user primary LE */
1676 case 0x19: /* As if user secondary LE */
1677 case 0x1c: /* Bypass LE */
1678 case 0x1d: /* Bypass, non-cacheable LE */
1679 case 0x88: /* Primary LE */
1680 case 0x89: /* Secondary LE */
1699 case 0x10: /* As if user primary */
1700 case 0x11: /* As if user secondary */
1701 case 0x18: /* As if user primary LE */
1702 case 0x19: /* As if user secondary LE */
1703 case 0x80: /* Primary */
1704 case 0x81: /* Secondary */
1705 case 0x88: /* Primary LE */
1706 case 0x89: /* Secondary LE */
1707 case 0xe2: /* UA2007 Primary block init */
1708 case 0xe3: /* UA2007 Secondary block init */
1709 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
1710 if (cpu_hypervisor_mode(env
)) {
1713 stb_hypv(addr
, val
);
1716 stw_hypv(addr
, val
);
1719 stl_hypv(addr
, val
);
1723 stq_hypv(addr
, val
);
1727 /* secondary space access has lowest asi bit equal to 1 */
1731 stb_kernel_secondary(addr
, val
);
1734 stw_kernel_secondary(addr
, val
);
1737 stl_kernel_secondary(addr
, val
);
1741 stq_kernel_secondary(addr
, val
);
1747 stb_kernel(addr
, val
);
1750 stw_kernel(addr
, val
);
1753 stl_kernel(addr
, val
);
1757 stq_kernel(addr
, val
);
1763 /* secondary space access has lowest asi bit equal to 1 */
1767 stb_user_secondary(addr
, val
);
1770 stw_user_secondary(addr
, val
);
1773 stl_user_secondary(addr
, val
);
1777 stq_user_secondary(addr
, val
);
1783 stb_user(addr
, val
);
1786 stw_user(addr
, val
);
1789 stl_user(addr
, val
);
1793 stq_user(addr
, val
);
1799 case 0x14: /* Bypass */
1800 case 0x15: /* Bypass, non-cacheable */
1801 case 0x1c: /* Bypass LE */
1802 case 0x1d: /* Bypass, non-cacheable LE */
1806 stb_phys(addr
, val
);
1809 stw_phys(addr
, val
);
1812 stl_phys(addr
, val
);
1816 stq_phys(addr
, val
);
1821 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1822 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1823 Only ldda allowed */
1824 helper_raise_exception(env
, TT_ILL_INSN
);
1826 case 0x04: /* Nucleus */
1827 case 0x0c: /* Nucleus Little Endian (LE) */
1831 stb_nucleus(addr
, val
);
1834 stw_nucleus(addr
, val
);
1837 stl_nucleus(addr
, val
);
1841 stq_nucleus(addr
, val
);
1847 case 0x4a: /* UPA config */
1850 case 0x45: /* LSU */
1855 env
->lsu
= val
& (DMMU_E
| IMMU_E
);
1856 /* Mappings generated during D/I MMU disabled mode are
1857 invalid in normal mode */
1858 if (oldreg
!= env
->lsu
) {
1859 DPRINTF_MMU("LSU change: 0x%" PRIx64
" -> 0x%" PRIx64
"\n",
1862 dump_mmu(stdout
, fprintf
, env1
);
1868 case 0x50: /* I-MMU regs */
1870 int reg
= (addr
>> 3) & 0xf;
1873 oldreg
= env
->immuregs
[reg
];
1877 case 1: /* Not in I-MMU */
1881 if ((val
& 1) == 0) {
1882 val
= 0; /* Clear SFSR */
1884 env
->immu
.sfsr
= val
;
1888 case 5: /* TSB access */
1889 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64
" -> 0x%016"
1890 PRIx64
"\n", env
->immu
.tsb
, val
);
1891 env
->immu
.tsb
= val
;
1893 case 6: /* Tag access */
1894 env
->immu
.tag_access
= val
;
1903 if (oldreg
!= env
->immuregs
[reg
]) {
1904 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
1905 PRIx64
"\n", reg
, oldreg
, env
->immuregs
[reg
]);
1908 dump_mmu(stdout
, fprintf
, env
);
1912 case 0x54: /* I-MMU data in */
1913 replace_tlb_1bit_lru(env
->itlb
, env
->immu
.tag_access
, val
, "immu", env
);
1915 case 0x55: /* I-MMU data access */
1917 /* TODO: auto demap */
1919 unsigned int i
= (addr
>> 3) & 0x3f;
1921 replace_tlb_entry(&env
->itlb
[i
], env
->immu
.tag_access
, val
, env
);
1924 DPRINTF_MMU("immu data access replaced entry [%i]\n", i
);
1925 dump_mmu(stdout
, fprintf
, env
);
1929 case 0x57: /* I-MMU demap */
1930 demap_tlb(env
->itlb
, addr
, "immu", env
);
1932 case 0x58: /* D-MMU regs */
1934 int reg
= (addr
>> 3) & 0xf;
1937 oldreg
= env
->dmmuregs
[reg
];
1943 if ((val
& 1) == 0) {
1944 val
= 0; /* Clear SFSR, Fault address */
1947 env
->dmmu
.sfsr
= val
;
1949 case 1: /* Primary context */
1950 env
->dmmu
.mmu_primary_context
= val
;
1951 /* can be optimized to only flush MMU_USER_IDX
1952 and MMU_KERNEL_IDX entries */
1955 case 2: /* Secondary context */
1956 env
->dmmu
.mmu_secondary_context
= val
;
1957 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
1958 and MMU_KERNEL_SECONDARY_IDX entries */
1961 case 5: /* TSB access */
1962 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64
" -> 0x%016"
1963 PRIx64
"\n", env
->dmmu
.tsb
, val
);
1964 env
->dmmu
.tsb
= val
;
1966 case 6: /* Tag access */
1967 env
->dmmu
.tag_access
= val
;
1969 case 7: /* Virtual Watchpoint */
1970 case 8: /* Physical Watchpoint */
1972 env
->dmmuregs
[reg
] = val
;
1976 if (oldreg
!= env
->dmmuregs
[reg
]) {
1977 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
1978 PRIx64
"\n", reg
, oldreg
, env
->dmmuregs
[reg
]);
1981 dump_mmu(stdout
, fprintf
, env
);
1985 case 0x5c: /* D-MMU data in */
1986 replace_tlb_1bit_lru(env
->dtlb
, env
->dmmu
.tag_access
, val
, "dmmu", env
);
1988 case 0x5d: /* D-MMU data access */
1990 unsigned int i
= (addr
>> 3) & 0x3f;
1992 replace_tlb_entry(&env
->dtlb
[i
], env
->dmmu
.tag_access
, val
, env
);
1995 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i
);
1996 dump_mmu(stdout
, fprintf
, env
);
2000 case 0x5f: /* D-MMU demap */
2001 demap_tlb(env
->dtlb
, addr
, "dmmu", env
);
2003 case 0x49: /* Interrupt data receive */
2006 case 0x46: /* D-cache data */
2007 case 0x47: /* D-cache tag access */
2008 case 0x4b: /* E-cache error enable */
2009 case 0x4c: /* E-cache asynchronous fault status */
2010 case 0x4d: /* E-cache asynchronous fault address */
2011 case 0x4e: /* E-cache tag data */
2012 case 0x66: /* I-cache instruction access */
2013 case 0x67: /* I-cache tag access */
2014 case 0x6e: /* I-cache predecode */
2015 case 0x6f: /* I-cache LRU etc. */
2016 case 0x76: /* E-cache tag */
2017 case 0x7e: /* E-cache tag */
2019 case 0x51: /* I-MMU 8k TSB pointer, RO */
2020 case 0x52: /* I-MMU 64k TSB pointer, RO */
2021 case 0x56: /* I-MMU tag read, RO */
2022 case 0x59: /* D-MMU 8k TSB pointer, RO */
2023 case 0x5a: /* D-MMU 64k TSB pointer, RO */
2024 case 0x5b: /* D-MMU data pointer, RO */
2025 case 0x5e: /* D-MMU tag read, RO */
2026 case 0x48: /* Interrupt dispatch, RO */
2027 case 0x7f: /* Incoming interrupt vector, RO */
2028 case 0x82: /* Primary no-fault, RO */
2029 case 0x83: /* Secondary no-fault, RO */
2030 case 0x8a: /* Primary no-fault LE, RO */
2031 case 0x8b: /* Secondary no-fault LE, RO */
2033 do_unassigned_access(addr
, 1, 0, 1, size
);
2037 #endif /* CONFIG_USER_ONLY */
2039 void helper_ldda_asi(target_ulong addr
, int asi
, int rd
)
2041 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
2042 || (cpu_has_hypervisor(env
)
2043 && asi
>= 0x30 && asi
< 0x80
2044 && !(env
->hpstate
& HS_PRIV
))) {
2045 helper_raise_exception(env
, TT_PRIV_ACT
);
2048 addr
= asi_address_mask(env
, asi
, addr
);
2051 #if !defined(CONFIG_USER_ONLY)
2052 case 0x24: /* Nucleus quad LDD 128 bit atomic */
2053 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE */
2054 helper_check_align(addr
, 0xf);
2056 env
->gregs
[1] = ldq_nucleus(addr
+ 8);
2058 bswap64s(&env
->gregs
[1]);
2060 } else if (rd
< 8) {
2061 env
->gregs
[rd
] = ldq_nucleus(addr
);
2062 env
->gregs
[rd
+ 1] = ldq_nucleus(addr
+ 8);
2064 bswap64s(&env
->gregs
[rd
]);
2065 bswap64s(&env
->gregs
[rd
+ 1]);
2068 env
->regwptr
[rd
] = ldq_nucleus(addr
);
2069 env
->regwptr
[rd
+ 1] = ldq_nucleus(addr
+ 8);
2071 bswap64s(&env
->regwptr
[rd
]);
2072 bswap64s(&env
->regwptr
[rd
+ 1]);
2078 helper_check_align(addr
, 0x3);
2080 env
->gregs
[1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
2081 } else if (rd
< 8) {
2082 env
->gregs
[rd
] = helper_ld_asi(addr
, asi
, 4, 0);
2083 env
->gregs
[rd
+ 1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
2085 env
->regwptr
[rd
] = helper_ld_asi(addr
, asi
, 4, 0);
2086 env
->regwptr
[rd
+ 1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
2092 void helper_ldf_asi(target_ulong addr
, int asi
, int size
, int rd
)
2097 helper_check_align(addr
, 3);
2098 addr
= asi_address_mask(env
, asi
, addr
);
2101 case 0xf0: /* UA2007/JPS1 Block load primary */
2102 case 0xf1: /* UA2007/JPS1 Block load secondary */
2103 case 0xf8: /* UA2007/JPS1 Block load primary LE */
2104 case 0xf9: /* UA2007/JPS1 Block load secondary LE */
2106 helper_raise_exception(env
, TT_ILL_INSN
);
2109 helper_check_align(addr
, 0x3f);
2110 for (i
= 0; i
< 16; i
++) {
2111 *(uint32_t *)&env
->fpr
[rd
++] = helper_ld_asi(addr
, asi
& 0x8f, 4,
2117 case 0x16: /* UA2007 Block load primary, user privilege */
2118 case 0x17: /* UA2007 Block load secondary, user privilege */
2119 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2120 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2121 case 0x70: /* JPS1 Block load primary, user privilege */
2122 case 0x71: /* JPS1 Block load secondary, user privilege */
2123 case 0x78: /* JPS1 Block load primary LE, user privilege */
2124 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2126 helper_raise_exception(env
, TT_ILL_INSN
);
2129 helper_check_align(addr
, 0x3f);
2130 for (i
= 0; i
< 16; i
++) {
2131 *(uint32_t *)&env
->fpr
[rd
++] = helper_ld_asi(addr
, asi
& 0x19, 4,
2144 *((uint32_t *)&env
->fpr
[rd
]) = helper_ld_asi(addr
, asi
, size
, 0);
2147 u
.ll
= helper_ld_asi(addr
, asi
, size
, 0);
2148 *((uint32_t *)&env
->fpr
[rd
++]) = u
.l
.upper
;
2149 *((uint32_t *)&env
->fpr
[rd
++]) = u
.l
.lower
;
2152 u
.ll
= helper_ld_asi(addr
, asi
, 8, 0);
2153 *((uint32_t *)&env
->fpr
[rd
++]) = u
.l
.upper
;
2154 *((uint32_t *)&env
->fpr
[rd
++]) = u
.l
.lower
;
2155 u
.ll
= helper_ld_asi(addr
+ 8, asi
, 8, 0);
2156 *((uint32_t *)&env
->fpr
[rd
++]) = u
.l
.upper
;
2157 *((uint32_t *)&env
->fpr
[rd
++]) = u
.l
.lower
;
2162 void helper_stf_asi(target_ulong addr
, int asi
, int size
, int rd
)
2165 target_ulong val
= 0;
2168 helper_check_align(addr
, 3);
2169 addr
= asi_address_mask(env
, asi
, addr
);
2172 case 0xe0: /* UA2007/JPS1 Block commit store primary (cache flush) */
2173 case 0xe1: /* UA2007/JPS1 Block commit store secondary (cache flush) */
2174 case 0xf0: /* UA2007/JPS1 Block store primary */
2175 case 0xf1: /* UA2007/JPS1 Block store secondary */
2176 case 0xf8: /* UA2007/JPS1 Block store primary LE */
2177 case 0xf9: /* UA2007/JPS1 Block store secondary LE */
2179 helper_raise_exception(env
, TT_ILL_INSN
);
2182 helper_check_align(addr
, 0x3f);
2183 for (i
= 0; i
< 16; i
++) {
2184 val
= *(uint32_t *)&env
->fpr
[rd
++];
2185 helper_st_asi(addr
, val
, asi
& 0x8f, 4);
2190 case 0x16: /* UA2007 Block load primary, user privilege */
2191 case 0x17: /* UA2007 Block load secondary, user privilege */
2192 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2193 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2194 case 0x70: /* JPS1 Block store primary, user privilege */
2195 case 0x71: /* JPS1 Block store secondary, user privilege */
2196 case 0x78: /* JPS1 Block load primary LE, user privilege */
2197 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2199 helper_raise_exception(env
, TT_ILL_INSN
);
2202 helper_check_align(addr
, 0x3f);
2203 for (i
= 0; i
< 16; i
++) {
2204 val
= *(uint32_t *)&env
->fpr
[rd
++];
2205 helper_st_asi(addr
, val
, asi
& 0x19, 4);
2217 helper_st_asi(addr
, *(uint32_t *)&env
->fpr
[rd
], asi
, size
);
2220 u
.l
.upper
= *(uint32_t *)&env
->fpr
[rd
++];
2221 u
.l
.lower
= *(uint32_t *)&env
->fpr
[rd
++];
2222 helper_st_asi(addr
, u
.ll
, asi
, size
);
2225 u
.l
.upper
= *(uint32_t *)&env
->fpr
[rd
++];
2226 u
.l
.lower
= *(uint32_t *)&env
->fpr
[rd
++];
2227 helper_st_asi(addr
, u
.ll
, asi
, 8);
2228 u
.l
.upper
= *(uint32_t *)&env
->fpr
[rd
++];
2229 u
.l
.lower
= *(uint32_t *)&env
->fpr
[rd
++];
2230 helper_st_asi(addr
+ 8, u
.ll
, asi
, 8);
2235 target_ulong
helper_cas_asi(target_ulong addr
, target_ulong val1
,
2236 target_ulong val2
, uint32_t asi
)
2240 val2
&= 0xffffffffUL
;
2241 ret
= helper_ld_asi(addr
, asi
, 4, 0);
2242 ret
&= 0xffffffffUL
;
2244 helper_st_asi(addr
, val1
& 0xffffffffUL
, asi
, 4);
2249 target_ulong
helper_casx_asi(target_ulong addr
, target_ulong val1
,
2250 target_ulong val2
, uint32_t asi
)
2254 ret
= helper_ld_asi(addr
, asi
, 8, 0);
2256 helper_st_asi(addr
, val1
, asi
, 8);
2260 #endif /* TARGET_SPARC64 */
2262 static target_ulong
helper_udiv_common(target_ulong a
, target_ulong b
, int cc
)
2268 x0
= (a
& 0xffffffff) | ((int64_t) (env
->y
) << 32);
2269 x1
= (b
& 0xffffffff);
2272 helper_raise_exception(env
, TT_DIV_ZERO
);
2276 if (x0
> 0xffffffff) {
2283 env
->cc_src2
= overflow
;
2284 env
->cc_op
= CC_OP_DIV
;
2289 target_ulong
helper_udiv(target_ulong a
, target_ulong b
)
2291 return helper_udiv_common(a
, b
, 0);
2294 target_ulong
helper_udiv_cc(target_ulong a
, target_ulong b
)
2296 return helper_udiv_common(a
, b
, 1);
2299 static target_ulong
helper_sdiv_common(target_ulong a
, target_ulong b
, int cc
)
2305 x0
= (a
& 0xffffffff) | ((int64_t) (env
->y
) << 32);
2306 x1
= (b
& 0xffffffff);
2309 helper_raise_exception(env
, TT_DIV_ZERO
);
2313 if ((int32_t) x0
!= x0
) {
2314 x0
= x0
< 0 ? 0x80000000 : 0x7fffffff;
2320 env
->cc_src2
= overflow
;
2321 env
->cc_op
= CC_OP_DIV
;
2326 target_ulong
helper_sdiv(target_ulong a
, target_ulong b
)
2328 return helper_sdiv_common(a
, b
, 0);
2331 target_ulong
helper_sdiv_cc(target_ulong a
, target_ulong b
)
2333 return helper_sdiv_common(a
, b
, 1);
2336 void helper_stdf(target_ulong addr
, int mem_idx
)
2338 helper_check_align(addr
, 7);
2339 #if !defined(CONFIG_USER_ONLY)
2342 stfq_user(addr
, DT0
);
2344 case MMU_KERNEL_IDX
:
2345 stfq_kernel(addr
, DT0
);
2347 #ifdef TARGET_SPARC64
2349 stfq_hypv(addr
, DT0
);
2353 DPRINTF_MMU("helper_stdf: need to check MMU idx %d\n", mem_idx
);
2357 stfq_raw(address_mask(env
, addr
), DT0
);
2361 void helper_lddf(target_ulong addr
, int mem_idx
)
2363 helper_check_align(addr
, 7);
2364 #if !defined(CONFIG_USER_ONLY)
2367 DT0
= ldfq_user(addr
);
2369 case MMU_KERNEL_IDX
:
2370 DT0
= ldfq_kernel(addr
);
2372 #ifdef TARGET_SPARC64
2374 DT0
= ldfq_hypv(addr
);
2378 DPRINTF_MMU("helper_lddf: need to check MMU idx %d\n", mem_idx
);
2382 DT0
= ldfq_raw(address_mask(env
, addr
));
2386 void helper_ldqf(target_ulong addr
, int mem_idx
)
2388 /* XXX add 128 bit load */
2391 helper_check_align(addr
, 7);
2392 #if !defined(CONFIG_USER_ONLY)
2395 u
.ll
.upper
= ldq_user(addr
);
2396 u
.ll
.lower
= ldq_user(addr
+ 8);
2399 case MMU_KERNEL_IDX
:
2400 u
.ll
.upper
= ldq_kernel(addr
);
2401 u
.ll
.lower
= ldq_kernel(addr
+ 8);
2404 #ifdef TARGET_SPARC64
2406 u
.ll
.upper
= ldq_hypv(addr
);
2407 u
.ll
.lower
= ldq_hypv(addr
+ 8);
2412 DPRINTF_MMU("helper_ldqf: need to check MMU idx %d\n", mem_idx
);
2416 u
.ll
.upper
= ldq_raw(address_mask(env
, addr
));
2417 u
.ll
.lower
= ldq_raw(address_mask(env
, addr
+ 8));
2422 void helper_stqf(target_ulong addr
, int mem_idx
)
2424 /* XXX add 128 bit store */
2427 helper_check_align(addr
, 7);
2428 #if !defined(CONFIG_USER_ONLY)
2432 stq_user(addr
, u
.ll
.upper
);
2433 stq_user(addr
+ 8, u
.ll
.lower
);
2435 case MMU_KERNEL_IDX
:
2437 stq_kernel(addr
, u
.ll
.upper
);
2438 stq_kernel(addr
+ 8, u
.ll
.lower
);
2440 #ifdef TARGET_SPARC64
2443 stq_hypv(addr
, u
.ll
.upper
);
2444 stq_hypv(addr
+ 8, u
.ll
.lower
);
2448 DPRINTF_MMU("helper_stqf: need to check MMU idx %d\n", mem_idx
);
2453 stq_raw(address_mask(env
, addr
), u
.ll
.upper
);
2454 stq_raw(address_mask(env
, addr
+ 8), u
.ll
.lower
);
2458 #ifdef TARGET_SPARC64
2459 static void do_modify_softint(const char *operation
, uint32_t value
)
2461 if (env
->softint
!= value
) {
2462 env
->softint
= value
;
2463 DPRINTF_PSTATE(": %s new %08x\n", operation
, env
->softint
);
2464 #if !defined(CONFIG_USER_ONLY)
2465 if (cpu_interrupts_enabled(env
)) {
2466 cpu_check_irqs(env
);
2472 void helper_set_softint(uint64_t value
)
2474 do_modify_softint("helper_set_softint", env
->softint
| (uint32_t)value
);
2477 void helper_clear_softint(uint64_t value
)
2479 do_modify_softint("helper_clear_softint", env
->softint
& (uint32_t)~value
);
2482 void helper_write_softint(uint64_t value
)
2484 do_modify_softint("helper_write_softint", (uint32_t)value
);
2488 #if !defined(CONFIG_USER_ONLY)
2490 static void do_unaligned_access(target_ulong addr
, int is_write
, int is_user
,
2493 #define MMUSUFFIX _mmu
2494 #define ALIGNED_ONLY
2497 #include "softmmu_template.h"
2500 #include "softmmu_template.h"
2503 #include "softmmu_template.h"
2506 #include "softmmu_template.h"
2508 /* XXX: make it generic ? */
2509 static void cpu_restore_state2(void *retaddr
)
2511 TranslationBlock
*tb
;
2515 /* now we have a real cpu fault */
2516 pc
= (unsigned long)retaddr
;
2517 tb
= tb_find_pc(pc
);
2519 /* the PC is inside the translated code. It means that we have
2520 a virtual CPU fault */
2521 cpu_restore_state(tb
, env
, pc
);
2526 static void do_unaligned_access(target_ulong addr
, int is_write
, int is_user
,
2529 #ifdef DEBUG_UNALIGNED
2530 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
2531 "\n", addr
, env
->pc
);
2533 cpu_restore_state2(retaddr
);
2534 helper_raise_exception(env
, TT_UNALIGNED
);
2537 /* try to fill the TLB and return an exception if error. If retaddr is
2538 NULL, it means that the function was called in C code (i.e. not
2539 from generated code or from helper.c) */
2540 /* XXX: fix it to restore all registers */
2541 void tlb_fill(CPUState
*env1
, target_ulong addr
, int is_write
, int mmu_idx
,
2545 CPUState
*saved_env
;
2550 ret
= cpu_sparc_handle_mmu_fault(env
, addr
, is_write
, mmu_idx
);
2552 cpu_restore_state2(retaddr
);
2558 #endif /* !CONFIG_USER_ONLY */
2560 #ifndef TARGET_SPARC64
2561 #if !defined(CONFIG_USER_ONLY)
2562 static void do_unassigned_access(target_phys_addr_t addr
, int is_write
,
2563 int is_exec
, int is_asi
, int size
)
2567 #ifdef DEBUG_UNASSIGNED
2569 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2570 " asi 0x%02x from " TARGET_FMT_lx
"\n",
2571 is_exec
? "exec" : is_write
? "write" : "read", size
,
2572 size
== 1 ? "" : "s", addr
, is_asi
, env
->pc
);
2574 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2575 " from " TARGET_FMT_lx
"\n",
2576 is_exec
? "exec" : is_write
? "write" : "read", size
,
2577 size
== 1 ? "" : "s", addr
, env
->pc
);
2580 /* Don't overwrite translation and access faults */
2581 fault_type
= (env
->mmuregs
[3] & 0x1c) >> 2;
2582 if ((fault_type
> 4) || (fault_type
== 0)) {
2583 env
->mmuregs
[3] = 0; /* Fault status register */
2585 env
->mmuregs
[3] |= 1 << 16;
2588 env
->mmuregs
[3] |= 1 << 5;
2591 env
->mmuregs
[3] |= 1 << 6;
2594 env
->mmuregs
[3] |= 1 << 7;
2596 env
->mmuregs
[3] |= (5 << 2) | 2;
2597 /* SuperSPARC will never place instruction fault addresses in the FAR */
2599 env
->mmuregs
[4] = addr
; /* Fault address register */
2602 /* overflow (same type fault was not read before another fault) */
2603 if (fault_type
== ((env
->mmuregs
[3] & 0x1c)) >> 2) {
2604 env
->mmuregs
[3] |= 1;
2607 if ((env
->mmuregs
[0] & MMU_E
) && !(env
->mmuregs
[0] & MMU_NF
)) {
2609 helper_raise_exception(env
, TT_CODE_ACCESS
);
2611 helper_raise_exception(env
, TT_DATA_ACCESS
);
2615 /* flush neverland mappings created during no-fault mode,
2616 so the sequential MMU faults report proper fault types */
2617 if (env
->mmuregs
[0] & MMU_NF
) {
2623 #if defined(CONFIG_USER_ONLY)
2624 static void do_unassigned_access(target_ulong addr
, int is_write
, int is_exec
,
2625 int is_asi
, int size
)
2627 static void do_unassigned_access(target_phys_addr_t addr
, int is_write
,
2628 int is_exec
, int is_asi
, int size
)
2631 #ifdef DEBUG_UNASSIGNED
2632 printf("Unassigned mem access to " TARGET_FMT_plx
" from " TARGET_FMT_lx
2633 "\n", addr
, env
->pc
);
2637 helper_raise_exception(env
, TT_CODE_ACCESS
);
2639 helper_raise_exception(env
, TT_DATA_ACCESS
);
2644 #if !defined(CONFIG_USER_ONLY)
2645 void cpu_unassigned_access(CPUState
*env1
, target_phys_addr_t addr
,
2646 int is_write
, int is_exec
, int is_asi
, int size
)
2648 CPUState
*saved_env
;
2652 /* Ignore unassigned accesses outside of CPU context */
2654 do_unassigned_access(addr
, is_write
, is_exec
, is_asi
, size
);