]>
git.proxmox.com Git - qemu.git/blob - target-sparc/op_helper.c
2 #include "host-utils.h"
8 //#define DEBUG_UNALIGNED
9 //#define DEBUG_UNASSIGNED
12 //#define DEBUG_PSTATE
13 //#define DEBUG_CACHE_CONTROL
16 #define DPRINTF_MMU(fmt, ...) \
17 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
19 #define DPRINTF_MMU(fmt, ...) do {} while (0)
23 #define DPRINTF_MXCC(fmt, ...) \
24 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
26 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
30 #define DPRINTF_ASI(fmt, ...) \
31 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
35 #define DPRINTF_PSTATE(fmt, ...) \
36 do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0)
38 #define DPRINTF_PSTATE(fmt, ...) do {} while (0)
41 #ifdef DEBUG_CACHE_CONTROL
42 #define DPRINTF_CACHE_CONTROL(fmt, ...) \
43 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
45 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
50 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
52 #define AM_CHECK(env1) (1)
56 #define DT0 (env->dt0)
57 #define DT1 (env->dt1)
58 #define QT0 (env->qt0)
59 #define QT1 (env->qt1)
61 /* Leon3 cache control */
63 /* Cache control: emulate the behavior of cache control registers but without
64 any effect on the emulated */
66 #define CACHE_STATE_MASK 0x3
67 #define CACHE_DISABLED 0x0
68 #define CACHE_FROZEN 0x1
69 #define CACHE_ENABLED 0x3
71 /* Cache Control register fields */
73 #define CACHE_CTRL_IF (1 << 4) /* Instruction Cache Freeze on Interrupt */
74 #define CACHE_CTRL_DF (1 << 5) /* Data Cache Freeze on Interrupt */
75 #define CACHE_CTRL_DP (1 << 14) /* Data cache flush pending */
76 #define CACHE_CTRL_IP (1 << 15) /* Instruction cache flush pending */
77 #define CACHE_CTRL_IB (1 << 16) /* Instruction burst fetch */
78 #define CACHE_CTRL_FI (1 << 21) /* Flush Instruction cache (Write only) */
79 #define CACHE_CTRL_FD (1 << 22) /* Flush Data cache (Write only) */
80 #define CACHE_CTRL_DS (1 << 23) /* Data cache snoop enable */
82 #if !defined(CONFIG_USER_ONLY)
83 static void do_unassigned_access(target_phys_addr_t addr
, int is_write
,
84 int is_exec
, int is_asi
, int size
);
87 static void do_unassigned_access(target_ulong addr
, int is_write
, int is_exec
,
88 int is_asi
, int size
);
92 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
93 // Calculates TSB pointer value for fault page size 8k or 64k
94 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register
,
95 uint64_t tag_access_register
,
98 uint64_t tsb_base
= tsb_register
& ~0x1fffULL
;
99 int tsb_split
= (tsb_register
& 0x1000ULL
) ? 1 : 0;
100 int tsb_size
= tsb_register
& 0xf;
102 // discard lower 13 bits which hold tag access context
103 uint64_t tag_access_va
= tag_access_register
& ~0x1fffULL
;
106 uint64_t tsb_base_mask
= ~0x1fffULL
;
107 uint64_t va
= tag_access_va
;
109 // move va bits to correct position
110 if (page_size
== 8*1024) {
112 } else if (page_size
== 64*1024) {
117 tsb_base_mask
<<= tsb_size
;
120 // calculate tsb_base mask and adjust va if split is in use
122 if (page_size
== 8*1024) {
123 va
&= ~(1ULL << (13 + tsb_size
));
124 } else if (page_size
== 64*1024) {
125 va
|= (1ULL << (13 + tsb_size
));
130 return ((tsb_base
& tsb_base_mask
) | (va
& ~tsb_base_mask
)) & ~0xfULL
;
133 // Calculates tag target register value by reordering bits
134 // in tag access register
135 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register
)
137 return ((tag_access_register
& 0x1fff) << 48) | (tag_access_register
>> 22);
140 static void replace_tlb_entry(SparcTLBEntry
*tlb
,
141 uint64_t tlb_tag
, uint64_t tlb_tte
,
144 target_ulong mask
, size
, va
, offset
;
146 // flush page range if translation is valid
147 if (TTE_IS_VALID(tlb
->tte
)) {
149 mask
= 0xffffffffffffe000ULL
;
150 mask
<<= 3 * ((tlb
->tte
>> 61) & 3);
153 va
= tlb
->tag
& mask
;
155 for (offset
= 0; offset
< size
; offset
+= TARGET_PAGE_SIZE
) {
156 tlb_flush_page(env1
, va
+ offset
);
164 static void demap_tlb(SparcTLBEntry
*tlb
, target_ulong demap_addr
,
165 const char* strmmu
, CPUState
*env1
)
171 int is_demap_context
= (demap_addr
>> 6) & 1;
174 switch ((demap_addr
>> 4) & 3) {
176 context
= env1
->dmmu
.mmu_primary_context
;
179 context
= env1
->dmmu
.mmu_secondary_context
;
189 for (i
= 0; i
< 64; i
++) {
190 if (TTE_IS_VALID(tlb
[i
].tte
)) {
192 if (is_demap_context
) {
193 // will remove non-global entries matching context value
194 if (TTE_IS_GLOBAL(tlb
[i
].tte
) ||
195 !tlb_compare_context(&tlb
[i
], context
)) {
200 // will remove any entry matching VA
201 mask
= 0xffffffffffffe000ULL
;
202 mask
<<= 3 * ((tlb
[i
].tte
>> 61) & 3);
204 if (!compare_masked(demap_addr
, tlb
[i
].tag
, mask
)) {
208 // entry should be global or matching context value
209 if (!TTE_IS_GLOBAL(tlb
[i
].tte
) &&
210 !tlb_compare_context(&tlb
[i
], context
)) {
215 replace_tlb_entry(&tlb
[i
], 0, 0, env1
);
217 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu
, i
);
218 dump_mmu(stdout
, fprintf
, env1
);
224 static void replace_tlb_1bit_lru(SparcTLBEntry
*tlb
,
225 uint64_t tlb_tag
, uint64_t tlb_tte
,
226 const char* strmmu
, CPUState
*env1
)
228 unsigned int i
, replace_used
;
230 // Try replacing invalid entry
231 for (i
= 0; i
< 64; i
++) {
232 if (!TTE_IS_VALID(tlb
[i
].tte
)) {
233 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
235 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu
, i
);
236 dump_mmu(stdout
, fprintf
, env1
);
242 // All entries are valid, try replacing unlocked entry
244 for (replace_used
= 0; replace_used
< 2; ++replace_used
) {
246 // Used entries are not replaced on first pass
248 for (i
= 0; i
< 64; i
++) {
249 if (!TTE_IS_LOCKED(tlb
[i
].tte
) && !TTE_IS_USED(tlb
[i
].tte
)) {
251 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
253 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
254 strmmu
, (replace_used
?"used":"unused"), i
);
255 dump_mmu(stdout
, fprintf
, env1
);
261 // Now reset used bit and search for unused entries again
263 for (i
= 0; i
< 64; i
++) {
264 TTE_SET_UNUSED(tlb
[i
].tte
);
269 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu
);
276 static inline target_ulong
address_mask(CPUState
*env1
, target_ulong addr
)
278 #ifdef TARGET_SPARC64
280 addr
&= 0xffffffffULL
;
285 /* returns true if access using this ASI is to have address translated by MMU
286 otherwise access is to raw physical address */
287 static inline int is_translating_asi(int asi
)
289 #ifdef TARGET_SPARC64
290 /* Ultrasparc IIi translating asi
291 - note this list is defined by cpu implementation
307 /* TODO: check sparc32 bits */
312 static inline target_ulong
asi_address_mask(CPUState
*env1
,
313 int asi
, target_ulong addr
)
315 if (is_translating_asi(asi
)) {
316 return address_mask(env
, addr
);
322 static void raise_exception(int tt
)
324 env
->exception_index
= tt
;
328 void HELPER(raise_exception
)(int tt
)
333 void helper_shutdown(void)
335 #if !defined(CONFIG_USER_ONLY)
336 qemu_system_shutdown_request();
340 void helper_check_align(target_ulong addr
, uint32_t align
)
343 #ifdef DEBUG_UNALIGNED
344 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
345 "\n", addr
, env
->pc
);
347 raise_exception(TT_UNALIGNED
);
351 #define F_HELPER(name, p) void helper_f##name##p(void)
353 #define F_BINOP(name) \
354 float32 helper_f ## name ## s (float32 src1, float32 src2) \
356 return float32_ ## name (src1, src2, &env->fp_status); \
360 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
364 QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
373 void helper_fsmuld(float32 src1
, float32 src2
)
375 DT0
= float64_mul(float32_to_float64(src1
, &env
->fp_status
),
376 float32_to_float64(src2
, &env
->fp_status
),
380 void helper_fdmulq(void)
382 QT0
= float128_mul(float64_to_float128(DT0
, &env
->fp_status
),
383 float64_to_float128(DT1
, &env
->fp_status
),
387 float32
helper_fnegs(float32 src
)
389 return float32_chs(src
);
392 #ifdef TARGET_SPARC64
395 DT0
= float64_chs(DT1
);
400 QT0
= float128_chs(QT1
);
404 /* Integer to float conversion. */
405 float32
helper_fitos(int32_t src
)
407 return int32_to_float32(src
, &env
->fp_status
);
410 void helper_fitod(int32_t src
)
412 DT0
= int32_to_float64(src
, &env
->fp_status
);
415 void helper_fitoq(int32_t src
)
417 QT0
= int32_to_float128(src
, &env
->fp_status
);
420 #ifdef TARGET_SPARC64
421 float32
helper_fxtos(void)
423 return int64_to_float32(*((int64_t *)&DT1
), &env
->fp_status
);
428 DT0
= int64_to_float64(*((int64_t *)&DT1
), &env
->fp_status
);
433 QT0
= int64_to_float128(*((int64_t *)&DT1
), &env
->fp_status
);
438 /* floating point conversion */
439 float32
helper_fdtos(void)
441 return float64_to_float32(DT1
, &env
->fp_status
);
444 void helper_fstod(float32 src
)
446 DT0
= float32_to_float64(src
, &env
->fp_status
);
449 float32
helper_fqtos(void)
451 return float128_to_float32(QT1
, &env
->fp_status
);
454 void helper_fstoq(float32 src
)
456 QT0
= float32_to_float128(src
, &env
->fp_status
);
459 void helper_fqtod(void)
461 DT0
= float128_to_float64(QT1
, &env
->fp_status
);
464 void helper_fdtoq(void)
466 QT0
= float64_to_float128(DT1
, &env
->fp_status
);
469 /* Float to integer conversion. */
470 int32_t helper_fstoi(float32 src
)
472 return float32_to_int32_round_to_zero(src
, &env
->fp_status
);
475 int32_t helper_fdtoi(void)
477 return float64_to_int32_round_to_zero(DT1
, &env
->fp_status
);
480 int32_t helper_fqtoi(void)
482 return float128_to_int32_round_to_zero(QT1
, &env
->fp_status
);
485 #ifdef TARGET_SPARC64
486 void helper_fstox(float32 src
)
488 *((int64_t *)&DT0
) = float32_to_int64_round_to_zero(src
, &env
->fp_status
);
491 void helper_fdtox(void)
493 *((int64_t *)&DT0
) = float64_to_int64_round_to_zero(DT1
, &env
->fp_status
);
496 void helper_fqtox(void)
498 *((int64_t *)&DT0
) = float128_to_int64_round_to_zero(QT1
, &env
->fp_status
);
501 void helper_faligndata(void)
505 tmp
= (*((uint64_t *)&DT0
)) << ((env
->gsr
& 7) * 8);
506 /* on many architectures a shift of 64 does nothing */
507 if ((env
->gsr
& 7) != 0) {
508 tmp
|= (*((uint64_t *)&DT1
)) >> (64 - (env
->gsr
& 7) * 8);
510 *((uint64_t *)&DT0
) = tmp
;
513 #ifdef HOST_WORDS_BIGENDIAN
514 #define VIS_B64(n) b[7 - (n)]
515 #define VIS_W64(n) w[3 - (n)]
516 #define VIS_SW64(n) sw[3 - (n)]
517 #define VIS_L64(n) l[1 - (n)]
518 #define VIS_B32(n) b[3 - (n)]
519 #define VIS_W32(n) w[1 - (n)]
521 #define VIS_B64(n) b[n]
522 #define VIS_W64(n) w[n]
523 #define VIS_SW64(n) sw[n]
524 #define VIS_L64(n) l[n]
525 #define VIS_B32(n) b[n]
526 #define VIS_W32(n) w[n]
545 void helper_fpmerge(void)
552 // Reverse calculation order to handle overlap
553 d
.VIS_B64(7) = s
.VIS_B64(3);
554 d
.VIS_B64(6) = d
.VIS_B64(3);
555 d
.VIS_B64(5) = s
.VIS_B64(2);
556 d
.VIS_B64(4) = d
.VIS_B64(2);
557 d
.VIS_B64(3) = s
.VIS_B64(1);
558 d
.VIS_B64(2) = d
.VIS_B64(1);
559 d
.VIS_B64(1) = s
.VIS_B64(0);
560 //d.VIS_B64(0) = d.VIS_B64(0);
565 void helper_fmul8x16(void)
574 tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
575 if ((tmp & 0xff) > 0x7f) \
577 d.VIS_W64(r) = tmp >> 8;
588 void helper_fmul8x16al(void)
597 tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
598 if ((tmp & 0xff) > 0x7f) \
600 d.VIS_W64(r) = tmp >> 8;
611 void helper_fmul8x16au(void)
620 tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
621 if ((tmp & 0xff) > 0x7f) \
623 d.VIS_W64(r) = tmp >> 8;
634 void helper_fmul8sux16(void)
643 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
644 if ((tmp & 0xff) > 0x7f) \
646 d.VIS_W64(r) = tmp >> 8;
657 void helper_fmul8ulx16(void)
666 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
667 if ((tmp & 0xff) > 0x7f) \
669 d.VIS_W64(r) = tmp >> 8;
680 void helper_fmuld8sux16(void)
689 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
690 if ((tmp & 0xff) > 0x7f) \
694 // Reverse calculation order to handle overlap
702 void helper_fmuld8ulx16(void)
711 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
712 if ((tmp & 0xff) > 0x7f) \
716 // Reverse calculation order to handle overlap
724 void helper_fexpand(void)
729 s
.l
= (uint32_t)(*(uint64_t *)&DT0
& 0xffffffff);
731 d
.VIS_W64(0) = s
.VIS_B32(0) << 4;
732 d
.VIS_W64(1) = s
.VIS_B32(1) << 4;
733 d
.VIS_W64(2) = s
.VIS_B32(2) << 4;
734 d
.VIS_W64(3) = s
.VIS_B32(3) << 4;
739 #define VIS_HELPER(name, F) \
740 void name##16(void) \
747 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
748 d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
749 d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
750 d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
755 uint32_t name##16s(uint32_t src1, uint32_t src2) \
762 d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
763 d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
768 void name##32(void) \
775 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
776 d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
781 uint32_t name##32s(uint32_t src1, uint32_t src2) \
793 #define FADD(a, b) ((a) + (b))
794 #define FSUB(a, b) ((a) - (b))
795 VIS_HELPER(helper_fpadd
, FADD
)
796 VIS_HELPER(helper_fpsub
, FSUB
)
798 #define VIS_CMPHELPER(name, F) \
799 uint64_t name##16(void) \
806 d.VIS_W64(0) = F(s.VIS_W64(0), d.VIS_W64(0)) ? 1 : 0; \
807 d.VIS_W64(0) |= F(s.VIS_W64(1), d.VIS_W64(1)) ? 2 : 0; \
808 d.VIS_W64(0) |= F(s.VIS_W64(2), d.VIS_W64(2)) ? 4 : 0; \
809 d.VIS_W64(0) |= F(s.VIS_W64(3), d.VIS_W64(3)) ? 8 : 0; \
810 d.VIS_W64(1) = d.VIS_W64(2) = d.VIS_W64(3) = 0; \
815 uint64_t name##32(void) \
822 d.VIS_L64(0) = F(s.VIS_L64(0), d.VIS_L64(0)) ? 1 : 0; \
823 d.VIS_L64(0) |= F(s.VIS_L64(1), d.VIS_L64(1)) ? 2 : 0; \
829 #define FCMPGT(a, b) ((a) > (b))
830 #define FCMPEQ(a, b) ((a) == (b))
831 #define FCMPLE(a, b) ((a) <= (b))
832 #define FCMPNE(a, b) ((a) != (b))
834 VIS_CMPHELPER(helper_fcmpgt
, FCMPGT
)
835 VIS_CMPHELPER(helper_fcmpeq
, FCMPEQ
)
836 VIS_CMPHELPER(helper_fcmple
, FCMPLE
)
837 VIS_CMPHELPER(helper_fcmpne
, FCMPNE
)
840 void helper_check_ieee_exceptions(void)
844 status
= get_float_exception_flags(&env
->fp_status
);
846 /* Copy IEEE 754 flags into FSR */
847 if (status
& float_flag_invalid
)
849 if (status
& float_flag_overflow
)
851 if (status
& float_flag_underflow
)
853 if (status
& float_flag_divbyzero
)
855 if (status
& float_flag_inexact
)
858 if ((env
->fsr
& FSR_CEXC_MASK
) & ((env
->fsr
& FSR_TEM_MASK
) >> 23)) {
859 /* Unmasked exception, generate a trap */
860 env
->fsr
|= FSR_FTT_IEEE_EXCP
;
861 raise_exception(TT_FP_EXCP
);
863 /* Accumulate exceptions */
864 env
->fsr
|= (env
->fsr
& FSR_CEXC_MASK
) << 5;
869 void helper_clear_float_exceptions(void)
871 set_float_exception_flags(0, &env
->fp_status
);
874 float32
helper_fabss(float32 src
)
876 return float32_abs(src
);
879 #ifdef TARGET_SPARC64
880 void helper_fabsd(void)
882 DT0
= float64_abs(DT1
);
885 void helper_fabsq(void)
887 QT0
= float128_abs(QT1
);
891 float32
helper_fsqrts(float32 src
)
893 return float32_sqrt(src
, &env
->fp_status
);
896 void helper_fsqrtd(void)
898 DT0
= float64_sqrt(DT1
, &env
->fp_status
);
901 void helper_fsqrtq(void)
903 QT0
= float128_sqrt(QT1
, &env
->fp_status
);
906 #define GEN_FCMP(name, size, reg1, reg2, FS, E) \
907 void glue(helper_, name) (void) \
909 env->fsr &= FSR_FTT_NMASK; \
910 if (E && (glue(size, _is_any_nan)(reg1) || \
911 glue(size, _is_any_nan)(reg2)) && \
912 (env->fsr & FSR_NVM)) { \
913 env->fsr |= FSR_NVC; \
914 env->fsr |= FSR_FTT_IEEE_EXCP; \
915 raise_exception(TT_FP_EXCP); \
917 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
918 case float_relation_unordered: \
919 if ((env->fsr & FSR_NVM)) { \
920 env->fsr |= FSR_NVC; \
921 env->fsr |= FSR_FTT_IEEE_EXCP; \
922 raise_exception(TT_FP_EXCP); \
924 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
925 env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
926 env->fsr |= FSR_NVA; \
929 case float_relation_less: \
930 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
931 env->fsr |= FSR_FCC0 << FS; \
933 case float_relation_greater: \
934 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
935 env->fsr |= FSR_FCC1 << FS; \
938 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
942 #define GEN_FCMPS(name, size, FS, E) \
943 void glue(helper_, name)(float32 src1, float32 src2) \
945 env->fsr &= FSR_FTT_NMASK; \
946 if (E && (glue(size, _is_any_nan)(src1) || \
947 glue(size, _is_any_nan)(src2)) && \
948 (env->fsr & FSR_NVM)) { \
949 env->fsr |= FSR_NVC; \
950 env->fsr |= FSR_FTT_IEEE_EXCP; \
951 raise_exception(TT_FP_EXCP); \
953 switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \
954 case float_relation_unordered: \
955 if ((env->fsr & FSR_NVM)) { \
956 env->fsr |= FSR_NVC; \
957 env->fsr |= FSR_FTT_IEEE_EXCP; \
958 raise_exception(TT_FP_EXCP); \
960 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
961 env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
962 env->fsr |= FSR_NVA; \
965 case float_relation_less: \
966 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
967 env->fsr |= FSR_FCC0 << FS; \
969 case float_relation_greater: \
970 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
971 env->fsr |= FSR_FCC1 << FS; \
974 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
979 GEN_FCMPS(fcmps
, float32
, 0, 0);
980 GEN_FCMP(fcmpd
, float64
, DT0
, DT1
, 0, 0);
982 GEN_FCMPS(fcmpes
, float32
, 0, 1);
983 GEN_FCMP(fcmped
, float64
, DT0
, DT1
, 0, 1);
985 GEN_FCMP(fcmpq
, float128
, QT0
, QT1
, 0, 0);
986 GEN_FCMP(fcmpeq
, float128
, QT0
, QT1
, 0, 1);
988 static uint32_t compute_all_flags(void)
990 return env
->psr
& PSR_ICC
;
993 static uint32_t compute_C_flags(void)
995 return env
->psr
& PSR_CARRY
;
998 static inline uint32_t get_NZ_icc(int32_t dst
)
1004 } else if (dst
< 0) {
1010 #ifdef TARGET_SPARC64
1011 static uint32_t compute_all_flags_xcc(void)
1013 return env
->xcc
& PSR_ICC
;
1016 static uint32_t compute_C_flags_xcc(void)
1018 return env
->xcc
& PSR_CARRY
;
1021 static inline uint32_t get_NZ_xcc(target_long dst
)
1027 } else if (dst
< 0) {
1034 static inline uint32_t get_V_div_icc(target_ulong src2
)
1044 static uint32_t compute_all_div(void)
1048 ret
= get_NZ_icc(CC_DST
);
1049 ret
|= get_V_div_icc(CC_SRC2
);
1053 static uint32_t compute_C_div(void)
1058 static inline uint32_t get_C_add_icc(uint32_t dst
, uint32_t src1
)
1068 static inline uint32_t get_C_addx_icc(uint32_t dst
, uint32_t src1
,
1073 if (((src1
& src2
) | (~dst
& (src1
| src2
))) & (1U << 31)) {
1079 static inline uint32_t get_V_add_icc(uint32_t dst
, uint32_t src1
,
1084 if (((src1
^ src2
^ -1) & (src1
^ dst
)) & (1U << 31)) {
1090 #ifdef TARGET_SPARC64
1091 static inline uint32_t get_C_add_xcc(target_ulong dst
, target_ulong src1
)
1101 static inline uint32_t get_C_addx_xcc(target_ulong dst
, target_ulong src1
,
1106 if (((src1
& src2
) | (~dst
& (src1
| src2
))) & (1ULL << 63)) {
1112 static inline uint32_t get_V_add_xcc(target_ulong dst
, target_ulong src1
,
1117 if (((src1
^ src2
^ -1) & (src1
^ dst
)) & (1ULL << 63)) {
1123 static uint32_t compute_all_add_xcc(void)
1127 ret
= get_NZ_xcc(CC_DST
);
1128 ret
|= get_C_add_xcc(CC_DST
, CC_SRC
);
1129 ret
|= get_V_add_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1133 static uint32_t compute_C_add_xcc(void)
1135 return get_C_add_xcc(CC_DST
, CC_SRC
);
1139 static uint32_t compute_all_add(void)
1143 ret
= get_NZ_icc(CC_DST
);
1144 ret
|= get_C_add_icc(CC_DST
, CC_SRC
);
1145 ret
|= get_V_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1149 static uint32_t compute_C_add(void)
1151 return get_C_add_icc(CC_DST
, CC_SRC
);
1154 #ifdef TARGET_SPARC64
1155 static uint32_t compute_all_addx_xcc(void)
1159 ret
= get_NZ_xcc(CC_DST
);
1160 ret
|= get_C_addx_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1161 ret
|= get_V_add_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1165 static uint32_t compute_C_addx_xcc(void)
1169 ret
= get_C_addx_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1174 static uint32_t compute_all_addx(void)
1178 ret
= get_NZ_icc(CC_DST
);
1179 ret
|= get_C_addx_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1180 ret
|= get_V_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1184 static uint32_t compute_C_addx(void)
1188 ret
= get_C_addx_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1192 static inline uint32_t get_V_tag_icc(target_ulong src1
, target_ulong src2
)
1196 if ((src1
| src2
) & 0x3) {
1202 static uint32_t compute_all_tadd(void)
1206 ret
= get_NZ_icc(CC_DST
);
1207 ret
|= get_C_add_icc(CC_DST
, CC_SRC
);
1208 ret
|= get_V_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1209 ret
|= get_V_tag_icc(CC_SRC
, CC_SRC2
);
1213 static uint32_t compute_all_taddtv(void)
1217 ret
= get_NZ_icc(CC_DST
);
1218 ret
|= get_C_add_icc(CC_DST
, CC_SRC
);
1222 static inline uint32_t get_C_sub_icc(uint32_t src1
, uint32_t src2
)
1232 static inline uint32_t get_C_subx_icc(uint32_t dst
, uint32_t src1
,
1237 if (((~src1
& src2
) | (dst
& (~src1
| src2
))) & (1U << 31)) {
1243 static inline uint32_t get_V_sub_icc(uint32_t dst
, uint32_t src1
,
1248 if (((src1
^ src2
) & (src1
^ dst
)) & (1U << 31)) {
1255 #ifdef TARGET_SPARC64
1256 static inline uint32_t get_C_sub_xcc(target_ulong src1
, target_ulong src2
)
1266 static inline uint32_t get_C_subx_xcc(target_ulong dst
, target_ulong src1
,
1271 if (((~src1
& src2
) | (dst
& (~src1
| src2
))) & (1ULL << 63)) {
1277 static inline uint32_t get_V_sub_xcc(target_ulong dst
, target_ulong src1
,
1282 if (((src1
^ src2
) & (src1
^ dst
)) & (1ULL << 63)) {
1288 static uint32_t compute_all_sub_xcc(void)
1292 ret
= get_NZ_xcc(CC_DST
);
1293 ret
|= get_C_sub_xcc(CC_SRC
, CC_SRC2
);
1294 ret
|= get_V_sub_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1298 static uint32_t compute_C_sub_xcc(void)
1300 return get_C_sub_xcc(CC_SRC
, CC_SRC2
);
1304 static uint32_t compute_all_sub(void)
1308 ret
= get_NZ_icc(CC_DST
);
1309 ret
|= get_C_sub_icc(CC_SRC
, CC_SRC2
);
1310 ret
|= get_V_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1314 static uint32_t compute_C_sub(void)
1316 return get_C_sub_icc(CC_SRC
, CC_SRC2
);
1319 #ifdef TARGET_SPARC64
1320 static uint32_t compute_all_subx_xcc(void)
1324 ret
= get_NZ_xcc(CC_DST
);
1325 ret
|= get_C_subx_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1326 ret
|= get_V_sub_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1330 static uint32_t compute_C_subx_xcc(void)
1334 ret
= get_C_subx_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1339 static uint32_t compute_all_subx(void)
1343 ret
= get_NZ_icc(CC_DST
);
1344 ret
|= get_C_subx_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1345 ret
|= get_V_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1349 static uint32_t compute_C_subx(void)
1353 ret
= get_C_subx_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1357 static uint32_t compute_all_tsub(void)
1361 ret
= get_NZ_icc(CC_DST
);
1362 ret
|= get_C_sub_icc(CC_SRC
, CC_SRC2
);
1363 ret
|= get_V_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1364 ret
|= get_V_tag_icc(CC_SRC
, CC_SRC2
);
1368 static uint32_t compute_all_tsubtv(void)
1372 ret
= get_NZ_icc(CC_DST
);
1373 ret
|= get_C_sub_icc(CC_SRC
, CC_SRC2
);
1377 static uint32_t compute_all_logic(void)
1379 return get_NZ_icc(CC_DST
);
1382 static uint32_t compute_C_logic(void)
1387 #ifdef TARGET_SPARC64
1388 static uint32_t compute_all_logic_xcc(void)
1390 return get_NZ_xcc(CC_DST
);
1394 typedef struct CCTable
{
1395 uint32_t (*compute_all
)(void); /* return all the flags */
1396 uint32_t (*compute_c
)(void); /* return the C flag */
1399 static const CCTable icc_table
[CC_OP_NB
] = {
1400 /* CC_OP_DYNAMIC should never happen */
1401 [CC_OP_FLAGS
] = { compute_all_flags
, compute_C_flags
},
1402 [CC_OP_DIV
] = { compute_all_div
, compute_C_div
},
1403 [CC_OP_ADD
] = { compute_all_add
, compute_C_add
},
1404 [CC_OP_ADDX
] = { compute_all_addx
, compute_C_addx
},
1405 [CC_OP_TADD
] = { compute_all_tadd
, compute_C_add
},
1406 [CC_OP_TADDTV
] = { compute_all_taddtv
, compute_C_add
},
1407 [CC_OP_SUB
] = { compute_all_sub
, compute_C_sub
},
1408 [CC_OP_SUBX
] = { compute_all_subx
, compute_C_subx
},
1409 [CC_OP_TSUB
] = { compute_all_tsub
, compute_C_sub
},
1410 [CC_OP_TSUBTV
] = { compute_all_tsubtv
, compute_C_sub
},
1411 [CC_OP_LOGIC
] = { compute_all_logic
, compute_C_logic
},
1414 #ifdef TARGET_SPARC64
1415 static const CCTable xcc_table
[CC_OP_NB
] = {
1416 /* CC_OP_DYNAMIC should never happen */
1417 [CC_OP_FLAGS
] = { compute_all_flags_xcc
, compute_C_flags_xcc
},
1418 [CC_OP_DIV
] = { compute_all_logic_xcc
, compute_C_logic
},
1419 [CC_OP_ADD
] = { compute_all_add_xcc
, compute_C_add_xcc
},
1420 [CC_OP_ADDX
] = { compute_all_addx_xcc
, compute_C_addx_xcc
},
1421 [CC_OP_TADD
] = { compute_all_add_xcc
, compute_C_add_xcc
},
1422 [CC_OP_TADDTV
] = { compute_all_add_xcc
, compute_C_add_xcc
},
1423 [CC_OP_SUB
] = { compute_all_sub_xcc
, compute_C_sub_xcc
},
1424 [CC_OP_SUBX
] = { compute_all_subx_xcc
, compute_C_subx_xcc
},
1425 [CC_OP_TSUB
] = { compute_all_sub_xcc
, compute_C_sub_xcc
},
1426 [CC_OP_TSUBTV
] = { compute_all_sub_xcc
, compute_C_sub_xcc
},
1427 [CC_OP_LOGIC
] = { compute_all_logic_xcc
, compute_C_logic
},
1431 void helper_compute_psr(void)
1435 new_psr
= icc_table
[CC_OP
].compute_all();
1437 #ifdef TARGET_SPARC64
1438 new_psr
= xcc_table
[CC_OP
].compute_all();
1441 CC_OP
= CC_OP_FLAGS
;
1444 uint32_t helper_compute_C_icc(void)
1448 ret
= icc_table
[CC_OP
].compute_c() >> PSR_CARRY_SHIFT
;
1452 static inline void memcpy32(target_ulong
*dst
, const target_ulong
*src
)
1464 static void set_cwp(int new_cwp
)
1466 /* put the modified wrap registers at their proper location */
1467 if (env
->cwp
== env
->nwindows
- 1) {
1468 memcpy32(env
->regbase
, env
->regbase
+ env
->nwindows
* 16);
1472 /* put the wrap registers at their temporary location */
1473 if (new_cwp
== env
->nwindows
- 1) {
1474 memcpy32(env
->regbase
+ env
->nwindows
* 16, env
->regbase
);
1476 env
->regwptr
= env
->regbase
+ (new_cwp
* 16);
1479 void cpu_set_cwp(CPUState
*env1
, int new_cwp
)
1481 CPUState
*saved_env
;
1489 static target_ulong
get_psr(void)
1491 helper_compute_psr();
1493 #if !defined (TARGET_SPARC64)
1494 return env
->version
| (env
->psr
& PSR_ICC
) |
1495 (env
->psref
? PSR_EF
: 0) |
1496 (env
->psrpil
<< 8) |
1497 (env
->psrs
? PSR_S
: 0) |
1498 (env
->psrps
? PSR_PS
: 0) |
1499 (env
->psret
? PSR_ET
: 0) | env
->cwp
;
1501 return env
->psr
& PSR_ICC
;
1505 target_ulong
cpu_get_psr(CPUState
*env1
)
1507 CPUState
*saved_env
;
1517 static void put_psr(target_ulong val
)
1519 env
->psr
= val
& PSR_ICC
;
1520 #if !defined (TARGET_SPARC64)
1521 env
->psref
= (val
& PSR_EF
)? 1 : 0;
1522 env
->psrpil
= (val
& PSR_PIL
) >> 8;
1524 #if ((!defined (TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
1525 cpu_check_irqs(env
);
1527 #if !defined (TARGET_SPARC64)
1528 env
->psrs
= (val
& PSR_S
)? 1 : 0;
1529 env
->psrps
= (val
& PSR_PS
)? 1 : 0;
1530 env
->psret
= (val
& PSR_ET
)? 1 : 0;
1531 set_cwp(val
& PSR_CWP
);
1533 env
->cc_op
= CC_OP_FLAGS
;
1536 void cpu_put_psr(CPUState
*env1
, target_ulong val
)
1538 CPUState
*saved_env
;
1546 static int cwp_inc(int cwp
)
1548 if (unlikely(cwp
>= env
->nwindows
)) {
1549 cwp
-= env
->nwindows
;
1554 int cpu_cwp_inc(CPUState
*env1
, int cwp
)
1556 CPUState
*saved_env
;
1566 static int cwp_dec(int cwp
)
1568 if (unlikely(cwp
< 0)) {
1569 cwp
+= env
->nwindows
;
1574 int cpu_cwp_dec(CPUState
*env1
, int cwp
)
1576 CPUState
*saved_env
;
1586 #ifdef TARGET_SPARC64
1587 GEN_FCMPS(fcmps_fcc1
, float32
, 22, 0);
1588 GEN_FCMP(fcmpd_fcc1
, float64
, DT0
, DT1
, 22, 0);
1589 GEN_FCMP(fcmpq_fcc1
, float128
, QT0
, QT1
, 22, 0);
1591 GEN_FCMPS(fcmps_fcc2
, float32
, 24, 0);
1592 GEN_FCMP(fcmpd_fcc2
, float64
, DT0
, DT1
, 24, 0);
1593 GEN_FCMP(fcmpq_fcc2
, float128
, QT0
, QT1
, 24, 0);
1595 GEN_FCMPS(fcmps_fcc3
, float32
, 26, 0);
1596 GEN_FCMP(fcmpd_fcc3
, float64
, DT0
, DT1
, 26, 0);
1597 GEN_FCMP(fcmpq_fcc3
, float128
, QT0
, QT1
, 26, 0);
1599 GEN_FCMPS(fcmpes_fcc1
, float32
, 22, 1);
1600 GEN_FCMP(fcmped_fcc1
, float64
, DT0
, DT1
, 22, 1);
1601 GEN_FCMP(fcmpeq_fcc1
, float128
, QT0
, QT1
, 22, 1);
1603 GEN_FCMPS(fcmpes_fcc2
, float32
, 24, 1);
1604 GEN_FCMP(fcmped_fcc2
, float64
, DT0
, DT1
, 24, 1);
1605 GEN_FCMP(fcmpeq_fcc2
, float128
, QT0
, QT1
, 24, 1);
1607 GEN_FCMPS(fcmpes_fcc3
, float32
, 26, 1);
1608 GEN_FCMP(fcmped_fcc3
, float64
, DT0
, DT1
, 26, 1);
1609 GEN_FCMP(fcmpeq_fcc3
, float128
, QT0
, QT1
, 26, 1);
1613 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
1615 static void dump_mxcc(CPUState
*env
)
1617 printf("mxccdata: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
1619 env
->mxccdata
[0], env
->mxccdata
[1],
1620 env
->mxccdata
[2], env
->mxccdata
[3]);
1621 printf("mxccregs: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
1623 " %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
1625 env
->mxccregs
[0], env
->mxccregs
[1],
1626 env
->mxccregs
[2], env
->mxccregs
[3],
1627 env
->mxccregs
[4], env
->mxccregs
[5],
1628 env
->mxccregs
[6], env
->mxccregs
[7]);
1632 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
1633 && defined(DEBUG_ASI)
1634 static void dump_asi(const char *txt
, target_ulong addr
, int asi
, int size
,
1640 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %02" PRIx64
"\n", txt
,
1641 addr
, asi
, r1
& 0xff);
1644 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %04" PRIx64
"\n", txt
,
1645 addr
, asi
, r1
& 0xffff);
1648 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %08" PRIx64
"\n", txt
,
1649 addr
, asi
, r1
& 0xffffffff);
1652 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %016" PRIx64
"\n", txt
,
1659 #ifndef TARGET_SPARC64
1660 #ifndef CONFIG_USER_ONLY
1663 /* Leon3 cache control */
1665 static void leon3_cache_control_int(void)
1669 if (env
->cache_control
& CACHE_CTRL_IF
) {
1670 /* Instruction cache state */
1671 state
= env
->cache_control
& CACHE_STATE_MASK
;
1672 if (state
== CACHE_ENABLED
) {
1673 state
= CACHE_FROZEN
;
1674 DPRINTF_CACHE_CONTROL("Instruction cache: freeze\n");
1677 env
->cache_control
&= ~CACHE_STATE_MASK
;
1678 env
->cache_control
|= state
;
1681 if (env
->cache_control
& CACHE_CTRL_DF
) {
1682 /* Data cache state */
1683 state
= (env
->cache_control
>> 2) & CACHE_STATE_MASK
;
1684 if (state
== CACHE_ENABLED
) {
1685 state
= CACHE_FROZEN
;
1686 DPRINTF_CACHE_CONTROL("Data cache: freeze\n");
1689 env
->cache_control
&= ~(CACHE_STATE_MASK
<< 2);
1690 env
->cache_control
|= (state
<< 2);
1694 static void leon3_cache_control_st(target_ulong addr
, uint64_t val
, int size
)
1696 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64
", size:%d\n",
1700 DPRINTF_CACHE_CONTROL("32bits only\n");
1705 case 0x00: /* Cache control */
1707 /* These values must always be read as zeros */
1708 val
&= ~CACHE_CTRL_FD
;
1709 val
&= ~CACHE_CTRL_FI
;
1710 val
&= ~CACHE_CTRL_IB
;
1711 val
&= ~CACHE_CTRL_IP
;
1712 val
&= ~CACHE_CTRL_DP
;
1714 env
->cache_control
= val
;
1716 case 0x04: /* Instruction cache configuration */
1717 case 0x08: /* Data cache configuration */
1721 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr
);
1726 static uint64_t leon3_cache_control_ld(target_ulong addr
, int size
)
1731 DPRINTF_CACHE_CONTROL("32bits only\n");
1736 case 0x00: /* Cache control */
1737 ret
= env
->cache_control
;
1740 /* Configuration registers are read and only always keep those
1741 predefined values */
1743 case 0x04: /* Instruction cache configuration */
1746 case 0x08: /* Data cache configuration */
1750 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr
);
1753 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64
", size:%d\n",
1758 void leon3_irq_manager(void *irq_manager
, int intno
)
1760 leon3_irq_ack(irq_manager
, intno
);
1761 leon3_cache_control_int();
1764 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
1767 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
1768 uint32_t last_addr
= addr
;
1771 helper_check_align(addr
, size
- 1);
1773 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
1775 case 0x00: /* Leon3 Cache Control */
1776 case 0x08: /* Leon3 Instruction Cache config */
1777 case 0x0C: /* Leon3 Date Cache config */
1778 if (env
->def
->features
& CPU_FEATURE_CACHE_CTRL
) {
1779 ret
= leon3_cache_control_ld(addr
, size
);
1782 case 0x01c00a00: /* MXCC control register */
1784 ret
= env
->mxccregs
[3];
1786 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1789 case 0x01c00a04: /* MXCC control register */
1791 ret
= env
->mxccregs
[3];
1793 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1796 case 0x01c00c00: /* Module reset register */
1798 ret
= env
->mxccregs
[5];
1799 // should we do something here?
1801 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1804 case 0x01c00f00: /* MBus port address register */
1806 ret
= env
->mxccregs
[7];
1808 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1812 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr
,
1816 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
1817 "addr = %08x -> ret = %" PRIx64
","
1818 "addr = %08x\n", asi
, size
, sign
, last_addr
, ret
, addr
);
1823 case 3: /* MMU probe */
1827 mmulev
= (addr
>> 8) & 15;
1831 ret
= mmu_probe(env
, addr
, mmulev
);
1832 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64
"\n",
1836 case 4: /* read MMU regs */
1838 int reg
= (addr
>> 8) & 0x1f;
1840 ret
= env
->mmuregs
[reg
];
1841 if (reg
== 3) /* Fault status cleared on read */
1842 env
->mmuregs
[3] = 0;
1843 else if (reg
== 0x13) /* Fault status read */
1844 ret
= env
->mmuregs
[3];
1845 else if (reg
== 0x14) /* Fault address read */
1846 ret
= env
->mmuregs
[4];
1847 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64
"\n", reg
, ret
);
1850 case 5: // Turbosparc ITLB Diagnostic
1851 case 6: // Turbosparc DTLB Diagnostic
1852 case 7: // Turbosparc IOTLB Diagnostic
1854 case 9: /* Supervisor code access */
1857 ret
= ldub_code(addr
);
1860 ret
= lduw_code(addr
);
1864 ret
= ldl_code(addr
);
1867 ret
= ldq_code(addr
);
1871 case 0xa: /* User data access */
1874 ret
= ldub_user(addr
);
1877 ret
= lduw_user(addr
);
1881 ret
= ldl_user(addr
);
1884 ret
= ldq_user(addr
);
1888 case 0xb: /* Supervisor data access */
1891 ret
= ldub_kernel(addr
);
1894 ret
= lduw_kernel(addr
);
1898 ret
= ldl_kernel(addr
);
1901 ret
= ldq_kernel(addr
);
1905 case 0xc: /* I-cache tag */
1906 case 0xd: /* I-cache data */
1907 case 0xe: /* D-cache tag */
1908 case 0xf: /* D-cache data */
1910 case 0x20: /* MMU passthrough */
1913 ret
= ldub_phys(addr
);
1916 ret
= lduw_phys(addr
);
1920 ret
= ldl_phys(addr
);
1923 ret
= ldq_phys(addr
);
1927 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1930 ret
= ldub_phys((target_phys_addr_t
)addr
1931 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1934 ret
= lduw_phys((target_phys_addr_t
)addr
1935 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1939 ret
= ldl_phys((target_phys_addr_t
)addr
1940 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1943 ret
= ldq_phys((target_phys_addr_t
)addr
1944 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1948 case 0x30: // Turbosparc secondary cache diagnostic
1949 case 0x31: // Turbosparc RAM snoop
1950 case 0x32: // Turbosparc page table descriptor diagnostic
1951 case 0x39: /* data cache diagnostic register */
1954 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
1956 int reg
= (addr
>> 8) & 3;
1959 case 0: /* Breakpoint Value (Addr) */
1960 ret
= env
->mmubpregs
[reg
];
1962 case 1: /* Breakpoint Mask */
1963 ret
= env
->mmubpregs
[reg
];
1965 case 2: /* Breakpoint Control */
1966 ret
= env
->mmubpregs
[reg
];
1968 case 3: /* Breakpoint Status */
1969 ret
= env
->mmubpregs
[reg
];
1970 env
->mmubpregs
[reg
] = 0ULL;
1973 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64
"\n", reg
,
1977 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
1978 ret
= env
->mmubpctrv
;
1980 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
1981 ret
= env
->mmubpctrc
;
1983 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
1984 ret
= env
->mmubpctrs
;
1986 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
1987 ret
= env
->mmubpaction
;
1989 case 8: /* User code access, XXX */
1991 do_unassigned_access(addr
, 0, 0, asi
, size
);
2001 ret
= (int16_t) ret
;
2004 ret
= (int32_t) ret
;
2011 dump_asi("read ", last_addr
, asi
, size
, ret
);
2016 void helper_st_asi(target_ulong addr
, uint64_t val
, int asi
, int size
)
2018 helper_check_align(addr
, size
- 1);
2020 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
2022 case 0x00: /* Leon3 Cache Control */
2023 case 0x08: /* Leon3 Instruction Cache config */
2024 case 0x0C: /* Leon3 Date Cache config */
2025 if (env
->def
->features
& CPU_FEATURE_CACHE_CTRL
) {
2026 leon3_cache_control_st(addr
, val
, size
);
2030 case 0x01c00000: /* MXCC stream data register 0 */
2032 env
->mxccdata
[0] = val
;
2034 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
2037 case 0x01c00008: /* MXCC stream data register 1 */
2039 env
->mxccdata
[1] = val
;
2041 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
2044 case 0x01c00010: /* MXCC stream data register 2 */
2046 env
->mxccdata
[2] = val
;
2048 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
2051 case 0x01c00018: /* MXCC stream data register 3 */
2053 env
->mxccdata
[3] = val
;
2055 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
2058 case 0x01c00100: /* MXCC stream source */
2060 env
->mxccregs
[0] = val
;
2062 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
2064 env
->mxccdata
[0] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
2066 env
->mxccdata
[1] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
2068 env
->mxccdata
[2] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
2070 env
->mxccdata
[3] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
2073 case 0x01c00200: /* MXCC stream destination */
2075 env
->mxccregs
[1] = val
;
2077 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
2079 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 0,
2081 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 8,
2083 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 16,
2085 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 24,
2088 case 0x01c00a00: /* MXCC control register */
2090 env
->mxccregs
[3] = val
;
2092 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
2095 case 0x01c00a04: /* MXCC control register */
2097 env
->mxccregs
[3] = (env
->mxccregs
[3] & 0xffffffff00000000ULL
)
2100 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
2103 case 0x01c00e00: /* MXCC error register */
2104 // writing a 1 bit clears the error
2106 env
->mxccregs
[6] &= ~val
;
2108 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
2111 case 0x01c00f00: /* MBus port address register */
2113 env
->mxccregs
[7] = val
;
2115 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
2119 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr
,
2123 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64
"\n",
2124 asi
, size
, addr
, val
);
2129 case 3: /* MMU flush */
2133 mmulev
= (addr
>> 8) & 15;
2134 DPRINTF_MMU("mmu flush level %d\n", mmulev
);
2136 case 0: // flush page
2137 tlb_flush_page(env
, addr
& 0xfffff000);
2139 case 1: // flush segment (256k)
2140 case 2: // flush region (16M)
2141 case 3: // flush context (4G)
2142 case 4: // flush entire
2149 dump_mmu(stdout
, fprintf
, env
);
2153 case 4: /* write MMU regs */
2155 int reg
= (addr
>> 8) & 0x1f;
2158 oldreg
= env
->mmuregs
[reg
];
2160 case 0: // Control Register
2161 env
->mmuregs
[reg
] = (env
->mmuregs
[reg
] & 0xff000000) |
2163 // Mappings generated during no-fault mode or MMU
2164 // disabled mode are invalid in normal mode
2165 if ((oldreg
& (MMU_E
| MMU_NF
| env
->def
->mmu_bm
)) !=
2166 (env
->mmuregs
[reg
] & (MMU_E
| MMU_NF
| env
->def
->mmu_bm
)))
2169 case 1: // Context Table Pointer Register
2170 env
->mmuregs
[reg
] = val
& env
->def
->mmu_ctpr_mask
;
2172 case 2: // Context Register
2173 env
->mmuregs
[reg
] = val
& env
->def
->mmu_cxr_mask
;
2174 if (oldreg
!= env
->mmuregs
[reg
]) {
2175 /* we flush when the MMU context changes because
2176 QEMU has no MMU context support */
2180 case 3: // Synchronous Fault Status Register with Clear
2181 case 4: // Synchronous Fault Address Register
2183 case 0x10: // TLB Replacement Control Register
2184 env
->mmuregs
[reg
] = val
& env
->def
->mmu_trcr_mask
;
2186 case 0x13: // Synchronous Fault Status Register with Read and Clear
2187 env
->mmuregs
[3] = val
& env
->def
->mmu_sfsr_mask
;
2189 case 0x14: // Synchronous Fault Address Register
2190 env
->mmuregs
[4] = val
;
2193 env
->mmuregs
[reg
] = val
;
2196 if (oldreg
!= env
->mmuregs
[reg
]) {
2197 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
2198 reg
, oldreg
, env
->mmuregs
[reg
]);
2201 dump_mmu(stdout
, fprintf
, env
);
2205 case 5: // Turbosparc ITLB Diagnostic
2206 case 6: // Turbosparc DTLB Diagnostic
2207 case 7: // Turbosparc IOTLB Diagnostic
2209 case 0xa: /* User data access */
2212 stb_user(addr
, val
);
2215 stw_user(addr
, val
);
2219 stl_user(addr
, val
);
2222 stq_user(addr
, val
);
2226 case 0xb: /* Supervisor data access */
2229 stb_kernel(addr
, val
);
2232 stw_kernel(addr
, val
);
2236 stl_kernel(addr
, val
);
2239 stq_kernel(addr
, val
);
2243 case 0xc: /* I-cache tag */
2244 case 0xd: /* I-cache data */
2245 case 0xe: /* D-cache tag */
2246 case 0xf: /* D-cache data */
2247 case 0x10: /* I/D-cache flush page */
2248 case 0x11: /* I/D-cache flush segment */
2249 case 0x12: /* I/D-cache flush region */
2250 case 0x13: /* I/D-cache flush context */
2251 case 0x14: /* I/D-cache flush user */
2253 case 0x17: /* Block copy, sta access */
2259 uint32_t src
= val
& ~3, dst
= addr
& ~3, temp
;
2261 for (i
= 0; i
< 32; i
+= 4, src
+= 4, dst
+= 4) {
2262 temp
= ldl_kernel(src
);
2263 stl_kernel(dst
, temp
);
2267 case 0x1f: /* Block fill, stda access */
2270 // fill 32 bytes with val
2272 uint32_t dst
= addr
& 7;
2274 for (i
= 0; i
< 32; i
+= 8, dst
+= 8)
2275 stq_kernel(dst
, val
);
2278 case 0x20: /* MMU passthrough */
2282 stb_phys(addr
, val
);
2285 stw_phys(addr
, val
);
2289 stl_phys(addr
, val
);
2292 stq_phys(addr
, val
);
2297 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
2301 stb_phys((target_phys_addr_t
)addr
2302 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
2305 stw_phys((target_phys_addr_t
)addr
2306 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
2310 stl_phys((target_phys_addr_t
)addr
2311 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
2314 stq_phys((target_phys_addr_t
)addr
2315 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
2320 case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
2321 case 0x31: // store buffer data, Ross RT620 I-cache flush or
2322 // Turbosparc snoop RAM
2323 case 0x32: // store buffer control or Turbosparc page table
2324 // descriptor diagnostic
2325 case 0x36: /* I-cache flash clear */
2326 case 0x37: /* D-cache flash clear */
2328 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
2330 int reg
= (addr
>> 8) & 3;
2333 case 0: /* Breakpoint Value (Addr) */
2334 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
2336 case 1: /* Breakpoint Mask */
2337 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
2339 case 2: /* Breakpoint Control */
2340 env
->mmubpregs
[reg
] = (val
& 0x7fULL
);
2342 case 3: /* Breakpoint Status */
2343 env
->mmubpregs
[reg
] = (val
& 0xfULL
);
2346 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg
,
2350 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
2351 env
->mmubpctrv
= val
& 0xffffffff;
2353 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
2354 env
->mmubpctrc
= val
& 0x3;
2356 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
2357 env
->mmubpctrs
= val
& 0x3;
2359 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
2360 env
->mmubpaction
= val
& 0x1fff;
2362 case 8: /* User code access, XXX */
2363 case 9: /* Supervisor code access, XXX */
2365 do_unassigned_access(addr
, 1, 0, asi
, size
);
2369 dump_asi("write", addr
, asi
, size
, val
);
2373 #endif /* CONFIG_USER_ONLY */
2374 #else /* TARGET_SPARC64 */
2376 #ifdef CONFIG_USER_ONLY
2377 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
2380 #if defined(DEBUG_ASI)
2381 target_ulong last_addr
= addr
;
2385 raise_exception(TT_PRIV_ACT
);
2387 helper_check_align(addr
, size
- 1);
2388 addr
= asi_address_mask(env
, asi
, addr
);
2391 case 0x82: // Primary no-fault
2392 case 0x8a: // Primary no-fault LE
2393 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
2395 dump_asi("read ", last_addr
, asi
, size
, ret
);
2400 case 0x80: // Primary
2401 case 0x88: // Primary LE
2405 ret
= ldub_raw(addr
);
2408 ret
= lduw_raw(addr
);
2411 ret
= ldl_raw(addr
);
2415 ret
= ldq_raw(addr
);
2420 case 0x83: // Secondary no-fault
2421 case 0x8b: // Secondary no-fault LE
2422 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
2424 dump_asi("read ", last_addr
, asi
, size
, ret
);
2429 case 0x81: // Secondary
2430 case 0x89: // Secondary LE
2437 /* Convert from little endian */
2439 case 0x88: // Primary LE
2440 case 0x89: // Secondary LE
2441 case 0x8a: // Primary no-fault LE
2442 case 0x8b: // Secondary no-fault LE
2460 /* Convert to signed number */
2467 ret
= (int16_t) ret
;
2470 ret
= (int32_t) ret
;
2477 dump_asi("read ", last_addr
, asi
, size
, ret
);
2482 void helper_st_asi(target_ulong addr
, target_ulong val
, int asi
, int size
)
2485 dump_asi("write", addr
, asi
, size
, val
);
2488 raise_exception(TT_PRIV_ACT
);
2490 helper_check_align(addr
, size
- 1);
2491 addr
= asi_address_mask(env
, asi
, addr
);
2493 /* Convert to little endian */
2495 case 0x88: // Primary LE
2496 case 0x89: // Secondary LE
2515 case 0x80: // Primary
2516 case 0x88: // Primary LE
2535 case 0x81: // Secondary
2536 case 0x89: // Secondary LE
2540 case 0x82: // Primary no-fault, RO
2541 case 0x83: // Secondary no-fault, RO
2542 case 0x8a: // Primary no-fault LE, RO
2543 case 0x8b: // Secondary no-fault LE, RO
2545 do_unassigned_access(addr
, 1, 0, 1, size
);
2550 #else /* CONFIG_USER_ONLY */
2552 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
2555 #if defined(DEBUG_ASI)
2556 target_ulong last_addr
= addr
;
2561 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
2562 || (cpu_has_hypervisor(env
)
2563 && asi
>= 0x30 && asi
< 0x80
2564 && !(env
->hpstate
& HS_PRIV
)))
2565 raise_exception(TT_PRIV_ACT
);
2567 helper_check_align(addr
, size
- 1);
2568 addr
= asi_address_mask(env
, asi
, addr
);
2570 /* process nonfaulting loads first */
2571 if ((asi
& 0xf6) == 0x82) {
2574 /* secondary space access has lowest asi bit equal to 1 */
2575 if (env
->pstate
& PS_PRIV
) {
2576 mmu_idx
= (asi
& 1) ? MMU_KERNEL_SECONDARY_IDX
: MMU_KERNEL_IDX
;
2578 mmu_idx
= (asi
& 1) ? MMU_USER_SECONDARY_IDX
: MMU_USER_IDX
;
2581 if (cpu_get_phys_page_nofault(env
, addr
, mmu_idx
) == -1ULL) {
2583 dump_asi("read ", last_addr
, asi
, size
, ret
);
2585 /* env->exception_index is set in get_physical_address_data(). */
2586 raise_exception(env
->exception_index
);
2589 /* convert nonfaulting load ASIs to normal load ASIs */
2594 case 0x10: // As if user primary
2595 case 0x11: // As if user secondary
2596 case 0x18: // As if user primary LE
2597 case 0x19: // As if user secondary LE
2598 case 0x80: // Primary
2599 case 0x81: // Secondary
2600 case 0x88: // Primary LE
2601 case 0x89: // Secondary LE
2602 case 0xe2: // UA2007 Primary block init
2603 case 0xe3: // UA2007 Secondary block init
2604 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
2605 if (cpu_hypervisor_mode(env
)) {
2608 ret
= ldub_hypv(addr
);
2611 ret
= lduw_hypv(addr
);
2614 ret
= ldl_hypv(addr
);
2618 ret
= ldq_hypv(addr
);
2622 /* secondary space access has lowest asi bit equal to 1 */
2626 ret
= ldub_kernel_secondary(addr
);
2629 ret
= lduw_kernel_secondary(addr
);
2632 ret
= ldl_kernel_secondary(addr
);
2636 ret
= ldq_kernel_secondary(addr
);
2642 ret
= ldub_kernel(addr
);
2645 ret
= lduw_kernel(addr
);
2648 ret
= ldl_kernel(addr
);
2652 ret
= ldq_kernel(addr
);
2658 /* secondary space access has lowest asi bit equal to 1 */
2662 ret
= ldub_user_secondary(addr
);
2665 ret
= lduw_user_secondary(addr
);
2668 ret
= ldl_user_secondary(addr
);
2672 ret
= ldq_user_secondary(addr
);
2678 ret
= ldub_user(addr
);
2681 ret
= lduw_user(addr
);
2684 ret
= ldl_user(addr
);
2688 ret
= ldq_user(addr
);
2694 case 0x14: // Bypass
2695 case 0x15: // Bypass, non-cacheable
2696 case 0x1c: // Bypass LE
2697 case 0x1d: // Bypass, non-cacheable LE
2701 ret
= ldub_phys(addr
);
2704 ret
= lduw_phys(addr
);
2707 ret
= ldl_phys(addr
);
2711 ret
= ldq_phys(addr
);
2716 case 0x24: // Nucleus quad LDD 128 bit atomic
2717 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2718 // Only ldda allowed
2719 raise_exception(TT_ILL_INSN
);
2721 case 0x04: // Nucleus
2722 case 0x0c: // Nucleus Little Endian (LE)
2726 ret
= ldub_nucleus(addr
);
2729 ret
= lduw_nucleus(addr
);
2732 ret
= ldl_nucleus(addr
);
2736 ret
= ldq_nucleus(addr
);
2741 case 0x4a: // UPA config
2747 case 0x50: // I-MMU regs
2749 int reg
= (addr
>> 3) & 0xf;
2752 // I-TSB Tag Target register
2753 ret
= ultrasparc_tag_target(env
->immu
.tag_access
);
2755 ret
= env
->immuregs
[reg
];
2760 case 0x51: // I-MMU 8k TSB pointer
2762 // env->immuregs[5] holds I-MMU TSB register value
2763 // env->immuregs[6] holds I-MMU Tag Access register value
2764 ret
= ultrasparc_tsb_pointer(env
->immu
.tsb
, env
->immu
.tag_access
,
2768 case 0x52: // I-MMU 64k TSB pointer
2770 // env->immuregs[5] holds I-MMU TSB register value
2771 // env->immuregs[6] holds I-MMU Tag Access register value
2772 ret
= ultrasparc_tsb_pointer(env
->immu
.tsb
, env
->immu
.tag_access
,
2776 case 0x55: // I-MMU data access
2778 int reg
= (addr
>> 3) & 0x3f;
2780 ret
= env
->itlb
[reg
].tte
;
2783 case 0x56: // I-MMU tag read
2785 int reg
= (addr
>> 3) & 0x3f;
2787 ret
= env
->itlb
[reg
].tag
;
2790 case 0x58: // D-MMU regs
2792 int reg
= (addr
>> 3) & 0xf;
2795 // D-TSB Tag Target register
2796 ret
= ultrasparc_tag_target(env
->dmmu
.tag_access
);
2798 ret
= env
->dmmuregs
[reg
];
2802 case 0x59: // D-MMU 8k TSB pointer
2804 // env->dmmuregs[5] holds D-MMU TSB register value
2805 // env->dmmuregs[6] holds D-MMU Tag Access register value
2806 ret
= ultrasparc_tsb_pointer(env
->dmmu
.tsb
, env
->dmmu
.tag_access
,
2810 case 0x5a: // D-MMU 64k TSB pointer
2812 // env->dmmuregs[5] holds D-MMU TSB register value
2813 // env->dmmuregs[6] holds D-MMU Tag Access register value
2814 ret
= ultrasparc_tsb_pointer(env
->dmmu
.tsb
, env
->dmmu
.tag_access
,
2818 case 0x5d: // D-MMU data access
2820 int reg
= (addr
>> 3) & 0x3f;
2822 ret
= env
->dtlb
[reg
].tte
;
2825 case 0x5e: // D-MMU tag read
2827 int reg
= (addr
>> 3) & 0x3f;
2829 ret
= env
->dtlb
[reg
].tag
;
2832 case 0x46: // D-cache data
2833 case 0x47: // D-cache tag access
2834 case 0x4b: // E-cache error enable
2835 case 0x4c: // E-cache asynchronous fault status
2836 case 0x4d: // E-cache asynchronous fault address
2837 case 0x4e: // E-cache tag data
2838 case 0x66: // I-cache instruction access
2839 case 0x67: // I-cache tag access
2840 case 0x6e: // I-cache predecode
2841 case 0x6f: // I-cache LRU etc.
2842 case 0x76: // E-cache tag
2843 case 0x7e: // E-cache tag
2845 case 0x5b: // D-MMU data pointer
2846 case 0x48: // Interrupt dispatch, RO
2847 case 0x49: // Interrupt data receive
2848 case 0x7f: // Incoming interrupt vector, RO
2851 case 0x54: // I-MMU data in, WO
2852 case 0x57: // I-MMU demap, WO
2853 case 0x5c: // D-MMU data in, WO
2854 case 0x5f: // D-MMU demap, WO
2855 case 0x77: // Interrupt vector, WO
2857 do_unassigned_access(addr
, 0, 0, 1, size
);
2862 /* Convert from little endian */
2864 case 0x0c: // Nucleus Little Endian (LE)
2865 case 0x18: // As if user primary LE
2866 case 0x19: // As if user secondary LE
2867 case 0x1c: // Bypass LE
2868 case 0x1d: // Bypass, non-cacheable LE
2869 case 0x88: // Primary LE
2870 case 0x89: // Secondary LE
2888 /* Convert to signed number */
2895 ret
= (int16_t) ret
;
2898 ret
= (int32_t) ret
;
2905 dump_asi("read ", last_addr
, asi
, size
, ret
);
2910 void helper_st_asi(target_ulong addr
, target_ulong val
, int asi
, int size
)
2913 dump_asi("write", addr
, asi
, size
, val
);
2918 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
2919 || (cpu_has_hypervisor(env
)
2920 && asi
>= 0x30 && asi
< 0x80
2921 && !(env
->hpstate
& HS_PRIV
)))
2922 raise_exception(TT_PRIV_ACT
);
2924 helper_check_align(addr
, size
- 1);
2925 addr
= asi_address_mask(env
, asi
, addr
);
2927 /* Convert to little endian */
2929 case 0x0c: // Nucleus Little Endian (LE)
2930 case 0x18: // As if user primary LE
2931 case 0x19: // As if user secondary LE
2932 case 0x1c: // Bypass LE
2933 case 0x1d: // Bypass, non-cacheable LE
2934 case 0x88: // Primary LE
2935 case 0x89: // Secondary LE
2954 case 0x10: // As if user primary
2955 case 0x11: // As if user secondary
2956 case 0x18: // As if user primary LE
2957 case 0x19: // As if user secondary LE
2958 case 0x80: // Primary
2959 case 0x81: // Secondary
2960 case 0x88: // Primary LE
2961 case 0x89: // Secondary LE
2962 case 0xe2: // UA2007 Primary block init
2963 case 0xe3: // UA2007 Secondary block init
2964 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
2965 if (cpu_hypervisor_mode(env
)) {
2968 stb_hypv(addr
, val
);
2971 stw_hypv(addr
, val
);
2974 stl_hypv(addr
, val
);
2978 stq_hypv(addr
, val
);
2982 /* secondary space access has lowest asi bit equal to 1 */
2986 stb_kernel_secondary(addr
, val
);
2989 stw_kernel_secondary(addr
, val
);
2992 stl_kernel_secondary(addr
, val
);
2996 stq_kernel_secondary(addr
, val
);
3002 stb_kernel(addr
, val
);
3005 stw_kernel(addr
, val
);
3008 stl_kernel(addr
, val
);
3012 stq_kernel(addr
, val
);
3018 /* secondary space access has lowest asi bit equal to 1 */
3022 stb_user_secondary(addr
, val
);
3025 stw_user_secondary(addr
, val
);
3028 stl_user_secondary(addr
, val
);
3032 stq_user_secondary(addr
, val
);
3038 stb_user(addr
, val
);
3041 stw_user(addr
, val
);
3044 stl_user(addr
, val
);
3048 stq_user(addr
, val
);
3054 case 0x14: // Bypass
3055 case 0x15: // Bypass, non-cacheable
3056 case 0x1c: // Bypass LE
3057 case 0x1d: // Bypass, non-cacheable LE
3061 stb_phys(addr
, val
);
3064 stw_phys(addr
, val
);
3067 stl_phys(addr
, val
);
3071 stq_phys(addr
, val
);
3076 case 0x24: // Nucleus quad LDD 128 bit atomic
3077 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
3078 // Only ldda allowed
3079 raise_exception(TT_ILL_INSN
);
3081 case 0x04: // Nucleus
3082 case 0x0c: // Nucleus Little Endian (LE)
3086 stb_nucleus(addr
, val
);
3089 stw_nucleus(addr
, val
);
3092 stl_nucleus(addr
, val
);
3096 stq_nucleus(addr
, val
);
3102 case 0x4a: // UPA config
3110 env
->lsu
= val
& (DMMU_E
| IMMU_E
);
3111 // Mappings generated during D/I MMU disabled mode are
3112 // invalid in normal mode
3113 if (oldreg
!= env
->lsu
) {
3114 DPRINTF_MMU("LSU change: 0x%" PRIx64
" -> 0x%" PRIx64
"\n",
3117 dump_mmu(stdout
, fprintf
, env1
);
3123 case 0x50: // I-MMU regs
3125 int reg
= (addr
>> 3) & 0xf;
3128 oldreg
= env
->immuregs
[reg
];
3132 case 1: // Not in I-MMU
3137 val
= 0; // Clear SFSR
3138 env
->immu
.sfsr
= val
;
3142 case 5: // TSB access
3143 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64
" -> 0x%016"
3144 PRIx64
"\n", env
->immu
.tsb
, val
);
3145 env
->immu
.tsb
= val
;
3147 case 6: // Tag access
3148 env
->immu
.tag_access
= val
;
3157 if (oldreg
!= env
->immuregs
[reg
]) {
3158 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
3159 PRIx64
"\n", reg
, oldreg
, env
->immuregs
[reg
]);
3162 dump_mmu(stdout
, fprintf
, env
);
3166 case 0x54: // I-MMU data in
3167 replace_tlb_1bit_lru(env
->itlb
, env
->immu
.tag_access
, val
, "immu", env
);
3169 case 0x55: // I-MMU data access
3173 unsigned int i
= (addr
>> 3) & 0x3f;
3175 replace_tlb_entry(&env
->itlb
[i
], env
->immu
.tag_access
, val
, env
);
3178 DPRINTF_MMU("immu data access replaced entry [%i]\n", i
);
3179 dump_mmu(stdout
, fprintf
, env
);
3183 case 0x57: // I-MMU demap
3184 demap_tlb(env
->itlb
, addr
, "immu", env
);
3186 case 0x58: // D-MMU regs
3188 int reg
= (addr
>> 3) & 0xf;
3191 oldreg
= env
->dmmuregs
[reg
];
3197 if ((val
& 1) == 0) {
3198 val
= 0; // Clear SFSR, Fault address
3201 env
->dmmu
.sfsr
= val
;
3203 case 1: // Primary context
3204 env
->dmmu
.mmu_primary_context
= val
;
3205 /* can be optimized to only flush MMU_USER_IDX
3206 and MMU_KERNEL_IDX entries */
3209 case 2: // Secondary context
3210 env
->dmmu
.mmu_secondary_context
= val
;
3211 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
3212 and MMU_KERNEL_SECONDARY_IDX entries */
3215 case 5: // TSB access
3216 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64
" -> 0x%016"
3217 PRIx64
"\n", env
->dmmu
.tsb
, val
);
3218 env
->dmmu
.tsb
= val
;
3220 case 6: // Tag access
3221 env
->dmmu
.tag_access
= val
;
3223 case 7: // Virtual Watchpoint
3224 case 8: // Physical Watchpoint
3226 env
->dmmuregs
[reg
] = val
;
3230 if (oldreg
!= env
->dmmuregs
[reg
]) {
3231 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
3232 PRIx64
"\n", reg
, oldreg
, env
->dmmuregs
[reg
]);
3235 dump_mmu(stdout
, fprintf
, env
);
3239 case 0x5c: // D-MMU data in
3240 replace_tlb_1bit_lru(env
->dtlb
, env
->dmmu
.tag_access
, val
, "dmmu", env
);
3242 case 0x5d: // D-MMU data access
3244 unsigned int i
= (addr
>> 3) & 0x3f;
3246 replace_tlb_entry(&env
->dtlb
[i
], env
->dmmu
.tag_access
, val
, env
);
3249 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i
);
3250 dump_mmu(stdout
, fprintf
, env
);
3254 case 0x5f: // D-MMU demap
3255 demap_tlb(env
->dtlb
, addr
, "dmmu", env
);
3257 case 0x49: // Interrupt data receive
3260 case 0x46: // D-cache data
3261 case 0x47: // D-cache tag access
3262 case 0x4b: // E-cache error enable
3263 case 0x4c: // E-cache asynchronous fault status
3264 case 0x4d: // E-cache asynchronous fault address
3265 case 0x4e: // E-cache tag data
3266 case 0x66: // I-cache instruction access
3267 case 0x67: // I-cache tag access
3268 case 0x6e: // I-cache predecode
3269 case 0x6f: // I-cache LRU etc.
3270 case 0x76: // E-cache tag
3271 case 0x7e: // E-cache tag
3273 case 0x51: // I-MMU 8k TSB pointer, RO
3274 case 0x52: // I-MMU 64k TSB pointer, RO
3275 case 0x56: // I-MMU tag read, RO
3276 case 0x59: // D-MMU 8k TSB pointer, RO
3277 case 0x5a: // D-MMU 64k TSB pointer, RO
3278 case 0x5b: // D-MMU data pointer, RO
3279 case 0x5e: // D-MMU tag read, RO
3280 case 0x48: // Interrupt dispatch, RO
3281 case 0x7f: // Incoming interrupt vector, RO
3282 case 0x82: // Primary no-fault, RO
3283 case 0x83: // Secondary no-fault, RO
3284 case 0x8a: // Primary no-fault LE, RO
3285 case 0x8b: // Secondary no-fault LE, RO
3287 do_unassigned_access(addr
, 1, 0, 1, size
);
3291 #endif /* CONFIG_USER_ONLY */
3293 void helper_ldda_asi(target_ulong addr
, int asi
, int rd
)
3295 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
3296 || (cpu_has_hypervisor(env
)
3297 && asi
>= 0x30 && asi
< 0x80
3298 && !(env
->hpstate
& HS_PRIV
)))
3299 raise_exception(TT_PRIV_ACT
);
3301 addr
= asi_address_mask(env
, asi
, addr
);
3304 #if !defined(CONFIG_USER_ONLY)
3305 case 0x24: // Nucleus quad LDD 128 bit atomic
3306 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
3307 helper_check_align(addr
, 0xf);
3309 env
->gregs
[1] = ldq_nucleus(addr
+ 8);
3311 bswap64s(&env
->gregs
[1]);
3312 } else if (rd
< 8) {
3313 env
->gregs
[rd
] = ldq_nucleus(addr
);
3314 env
->gregs
[rd
+ 1] = ldq_nucleus(addr
+ 8);
3316 bswap64s(&env
->gregs
[rd
]);
3317 bswap64s(&env
->gregs
[rd
+ 1]);
3320 env
->regwptr
[rd
] = ldq_nucleus(addr
);
3321 env
->regwptr
[rd
+ 1] = ldq_nucleus(addr
+ 8);
3323 bswap64s(&env
->regwptr
[rd
]);
3324 bswap64s(&env
->regwptr
[rd
+ 1]);
3330 helper_check_align(addr
, 0x3);
3332 env
->gregs
[1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
3334 env
->gregs
[rd
] = helper_ld_asi(addr
, asi
, 4, 0);
3335 env
->gregs
[rd
+ 1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
3337 env
->regwptr
[rd
] = helper_ld_asi(addr
, asi
, 4, 0);
3338 env
->regwptr
[rd
+ 1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
3344 void helper_ldf_asi(target_ulong addr
, int asi
, int size
, int rd
)
3349 helper_check_align(addr
, 3);
3350 addr
= asi_address_mask(env
, asi
, addr
);
3353 case 0xf0: /* UA2007/JPS1 Block load primary */
3354 case 0xf1: /* UA2007/JPS1 Block load secondary */
3355 case 0xf8: /* UA2007/JPS1 Block load primary LE */
3356 case 0xf9: /* UA2007/JPS1 Block load secondary LE */
3358 raise_exception(TT_ILL_INSN
);
3361 helper_check_align(addr
, 0x3f);
3362 for (i
= 0; i
< 16; i
++) {
3363 *(uint32_t *)&env
->fpr
[rd
++] = helper_ld_asi(addr
, asi
& 0x8f, 4,
3369 case 0x16: /* UA2007 Block load primary, user privilege */
3370 case 0x17: /* UA2007 Block load secondary, user privilege */
3371 case 0x1e: /* UA2007 Block load primary LE, user privilege */
3372 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
3373 case 0x70: /* JPS1 Block load primary, user privilege */
3374 case 0x71: /* JPS1 Block load secondary, user privilege */
3375 case 0x78: /* JPS1 Block load primary LE, user privilege */
3376 case 0x79: /* JPS1 Block load secondary LE, user privilege */
3378 raise_exception(TT_ILL_INSN
);
3381 helper_check_align(addr
, 0x3f);
3382 for (i
= 0; i
< 16; i
++) {
3383 *(uint32_t *)&env
->fpr
[rd
++] = helper_ld_asi(addr
, asi
& 0x19, 4,
3396 *((uint32_t *)&env
->fpr
[rd
]) = helper_ld_asi(addr
, asi
, size
, 0);
3399 u
.ll
= helper_ld_asi(addr
, asi
, size
, 0);
3400 *((uint32_t *)&env
->fpr
[rd
++]) = u
.l
.upper
;
3401 *((uint32_t *)&env
->fpr
[rd
++]) = u
.l
.lower
;
3404 u
.ll
= helper_ld_asi(addr
, asi
, 8, 0);
3405 *((uint32_t *)&env
->fpr
[rd
++]) = u
.l
.upper
;
3406 *((uint32_t *)&env
->fpr
[rd
++]) = u
.l
.lower
;
3407 u
.ll
= helper_ld_asi(addr
+ 8, asi
, 8, 0);
3408 *((uint32_t *)&env
->fpr
[rd
++]) = u
.l
.upper
;
3409 *((uint32_t *)&env
->fpr
[rd
++]) = u
.l
.lower
;
3414 void helper_stf_asi(target_ulong addr
, int asi
, int size
, int rd
)
3417 target_ulong val
= 0;
3420 helper_check_align(addr
, 3);
3421 addr
= asi_address_mask(env
, asi
, addr
);
3424 case 0xe0: /* UA2007/JPS1 Block commit store primary (cache flush) */
3425 case 0xe1: /* UA2007/JPS1 Block commit store secondary (cache flush) */
3426 case 0xf0: /* UA2007/JPS1 Block store primary */
3427 case 0xf1: /* UA2007/JPS1 Block store secondary */
3428 case 0xf8: /* UA2007/JPS1 Block store primary LE */
3429 case 0xf9: /* UA2007/JPS1 Block store secondary LE */
3431 raise_exception(TT_ILL_INSN
);
3434 helper_check_align(addr
, 0x3f);
3435 for (i
= 0; i
< 16; i
++) {
3436 val
= *(uint32_t *)&env
->fpr
[rd
++];
3437 helper_st_asi(addr
, val
, asi
& 0x8f, 4);
3442 case 0x16: /* UA2007 Block load primary, user privilege */
3443 case 0x17: /* UA2007 Block load secondary, user privilege */
3444 case 0x1e: /* UA2007 Block load primary LE, user privilege */
3445 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
3446 case 0x70: /* JPS1 Block store primary, user privilege */
3447 case 0x71: /* JPS1 Block store secondary, user privilege */
3448 case 0x78: /* JPS1 Block load primary LE, user privilege */
3449 case 0x79: /* JPS1 Block load secondary LE, user privilege */
3451 raise_exception(TT_ILL_INSN
);
3454 helper_check_align(addr
, 0x3f);
3455 for (i
= 0; i
< 16; i
++) {
3456 val
= *(uint32_t *)&env
->fpr
[rd
++];
3457 helper_st_asi(addr
, val
, asi
& 0x19, 4);
3469 helper_st_asi(addr
, *(uint32_t *)&env
->fpr
[rd
], asi
, size
);
3472 u
.l
.upper
= *(uint32_t *)&env
->fpr
[rd
++];
3473 u
.l
.lower
= *(uint32_t *)&env
->fpr
[rd
++];
3474 helper_st_asi(addr
, u
.ll
, asi
, size
);
3477 u
.l
.upper
= *(uint32_t *)&env
->fpr
[rd
++];
3478 u
.l
.lower
= *(uint32_t *)&env
->fpr
[rd
++];
3479 helper_st_asi(addr
, u
.ll
, asi
, 8);
3480 u
.l
.upper
= *(uint32_t *)&env
->fpr
[rd
++];
3481 u
.l
.lower
= *(uint32_t *)&env
->fpr
[rd
++];
3482 helper_st_asi(addr
+ 8, u
.ll
, asi
, 8);
3487 target_ulong
helper_cas_asi(target_ulong addr
, target_ulong val1
,
3488 target_ulong val2
, uint32_t asi
)
3492 val2
&= 0xffffffffUL
;
3493 ret
= helper_ld_asi(addr
, asi
, 4, 0);
3494 ret
&= 0xffffffffUL
;
3496 helper_st_asi(addr
, val1
& 0xffffffffUL
, asi
, 4);
3500 target_ulong
helper_casx_asi(target_ulong addr
, target_ulong val1
,
3501 target_ulong val2
, uint32_t asi
)
3505 ret
= helper_ld_asi(addr
, asi
, 8, 0);
3507 helper_st_asi(addr
, val1
, asi
, 8);
3510 #endif /* TARGET_SPARC64 */
3512 #ifndef TARGET_SPARC64
3513 void helper_rett(void)
3517 if (env
->psret
== 1)
3518 raise_exception(TT_ILL_INSN
);
3521 cwp
= cwp_inc(env
->cwp
+ 1) ;
3522 if (env
->wim
& (1 << cwp
)) {
3523 raise_exception(TT_WIN_UNF
);
3526 env
->psrs
= env
->psrps
;
3530 static target_ulong
helper_udiv_common(target_ulong a
, target_ulong b
, int cc
)
3536 x0
= (a
& 0xffffffff) | ((int64_t) (env
->y
) << 32);
3537 x1
= (b
& 0xffffffff);
3540 raise_exception(TT_DIV_ZERO
);
3544 if (x0
> 0xffffffff) {
3551 env
->cc_src2
= overflow
;
3552 env
->cc_op
= CC_OP_DIV
;
3557 target_ulong
helper_udiv(target_ulong a
, target_ulong b
)
3559 return helper_udiv_common(a
, b
, 0);
3562 target_ulong
helper_udiv_cc(target_ulong a
, target_ulong b
)
3564 return helper_udiv_common(a
, b
, 1);
3567 static target_ulong
helper_sdiv_common(target_ulong a
, target_ulong b
, int cc
)
3573 x0
= (a
& 0xffffffff) | ((int64_t) (env
->y
) << 32);
3574 x1
= (b
& 0xffffffff);
3577 raise_exception(TT_DIV_ZERO
);
3581 if ((int32_t) x0
!= x0
) {
3582 x0
= x0
< 0 ? 0x80000000: 0x7fffffff;
3588 env
->cc_src2
= overflow
;
3589 env
->cc_op
= CC_OP_DIV
;
3594 target_ulong
helper_sdiv(target_ulong a
, target_ulong b
)
3596 return helper_sdiv_common(a
, b
, 0);
3599 target_ulong
helper_sdiv_cc(target_ulong a
, target_ulong b
)
3601 return helper_sdiv_common(a
, b
, 1);
3604 void helper_stdf(target_ulong addr
, int mem_idx
)
3606 helper_check_align(addr
, 7);
3607 #if !defined(CONFIG_USER_ONLY)
3610 stfq_user(addr
, DT0
);
3612 case MMU_KERNEL_IDX
:
3613 stfq_kernel(addr
, DT0
);
3615 #ifdef TARGET_SPARC64
3617 stfq_hypv(addr
, DT0
);
3621 DPRINTF_MMU("helper_stdf: need to check MMU idx %d\n", mem_idx
);
3625 stfq_raw(address_mask(env
, addr
), DT0
);
3629 void helper_lddf(target_ulong addr
, int mem_idx
)
3631 helper_check_align(addr
, 7);
3632 #if !defined(CONFIG_USER_ONLY)
3635 DT0
= ldfq_user(addr
);
3637 case MMU_KERNEL_IDX
:
3638 DT0
= ldfq_kernel(addr
);
3640 #ifdef TARGET_SPARC64
3642 DT0
= ldfq_hypv(addr
);
3646 DPRINTF_MMU("helper_lddf: need to check MMU idx %d\n", mem_idx
);
3650 DT0
= ldfq_raw(address_mask(env
, addr
));
3654 void helper_ldqf(target_ulong addr
, int mem_idx
)
3656 // XXX add 128 bit load
3659 helper_check_align(addr
, 7);
3660 #if !defined(CONFIG_USER_ONLY)
3663 u
.ll
.upper
= ldq_user(addr
);
3664 u
.ll
.lower
= ldq_user(addr
+ 8);
3667 case MMU_KERNEL_IDX
:
3668 u
.ll
.upper
= ldq_kernel(addr
);
3669 u
.ll
.lower
= ldq_kernel(addr
+ 8);
3672 #ifdef TARGET_SPARC64
3674 u
.ll
.upper
= ldq_hypv(addr
);
3675 u
.ll
.lower
= ldq_hypv(addr
+ 8);
3680 DPRINTF_MMU("helper_ldqf: need to check MMU idx %d\n", mem_idx
);
3684 u
.ll
.upper
= ldq_raw(address_mask(env
, addr
));
3685 u
.ll
.lower
= ldq_raw(address_mask(env
, addr
+ 8));
3690 void helper_stqf(target_ulong addr
, int mem_idx
)
3692 // XXX add 128 bit store
3695 helper_check_align(addr
, 7);
3696 #if !defined(CONFIG_USER_ONLY)
3700 stq_user(addr
, u
.ll
.upper
);
3701 stq_user(addr
+ 8, u
.ll
.lower
);
3703 case MMU_KERNEL_IDX
:
3705 stq_kernel(addr
, u
.ll
.upper
);
3706 stq_kernel(addr
+ 8, u
.ll
.lower
);
3708 #ifdef TARGET_SPARC64
3711 stq_hypv(addr
, u
.ll
.upper
);
3712 stq_hypv(addr
+ 8, u
.ll
.lower
);
3716 DPRINTF_MMU("helper_stqf: need to check MMU idx %d\n", mem_idx
);
3721 stq_raw(address_mask(env
, addr
), u
.ll
.upper
);
3722 stq_raw(address_mask(env
, addr
+ 8), u
.ll
.lower
);
3726 static inline void set_fsr(void)
3730 switch (env
->fsr
& FSR_RD_MASK
) {
3731 case FSR_RD_NEAREST
:
3732 rnd_mode
= float_round_nearest_even
;
3736 rnd_mode
= float_round_to_zero
;
3739 rnd_mode
= float_round_up
;
3742 rnd_mode
= float_round_down
;
3745 set_float_rounding_mode(rnd_mode
, &env
->fp_status
);
3748 void helper_ldfsr(uint32_t new_fsr
)
3750 env
->fsr
= (new_fsr
& FSR_LDFSR_MASK
) | (env
->fsr
& FSR_LDFSR_OLDMASK
);
3754 #ifdef TARGET_SPARC64
3755 void helper_ldxfsr(uint64_t new_fsr
)
3757 env
->fsr
= (new_fsr
& FSR_LDXFSR_MASK
) | (env
->fsr
& FSR_LDXFSR_OLDMASK
);
3762 void helper_debug(void)
3764 env
->exception_index
= EXCP_DEBUG
;
3768 #ifndef TARGET_SPARC64
3769 /* XXX: use another pointer for %iN registers to avoid slow wrapping
3771 void helper_save(void)
3775 cwp
= cwp_dec(env
->cwp
- 1);
3776 if (env
->wim
& (1 << cwp
)) {
3777 raise_exception(TT_WIN_OVF
);
3782 void helper_restore(void)
3786 cwp
= cwp_inc(env
->cwp
+ 1);
3787 if (env
->wim
& (1 << cwp
)) {
3788 raise_exception(TT_WIN_UNF
);
3793 void helper_wrpsr(target_ulong new_psr
)
3795 if ((new_psr
& PSR_CWP
) >= env
->nwindows
) {
3796 raise_exception(TT_ILL_INSN
);
3798 cpu_put_psr(env
, new_psr
);
3802 target_ulong
helper_rdpsr(void)
3808 /* XXX: use another pointer for %iN registers to avoid slow wrapping
3810 void helper_save(void)
3814 cwp
= cwp_dec(env
->cwp
- 1);
3815 if (env
->cansave
== 0) {
3816 raise_exception(TT_SPILL
| (env
->otherwin
!= 0 ?
3817 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
3818 ((env
->wstate
& 0x7) << 2)));
3820 if (env
->cleanwin
- env
->canrestore
== 0) {
3821 // XXX Clean windows without trap
3822 raise_exception(TT_CLRWIN
);
3831 void helper_restore(void)
3835 cwp
= cwp_inc(env
->cwp
+ 1);
3836 if (env
->canrestore
== 0) {
3837 raise_exception(TT_FILL
| (env
->otherwin
!= 0 ?
3838 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
3839 ((env
->wstate
& 0x7) << 2)));
3847 void helper_flushw(void)
3849 if (env
->cansave
!= env
->nwindows
- 2) {
3850 raise_exception(TT_SPILL
| (env
->otherwin
!= 0 ?
3851 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
3852 ((env
->wstate
& 0x7) << 2)));
3856 void helper_saved(void)
3859 if (env
->otherwin
== 0)
3865 void helper_restored(void)
3868 if (env
->cleanwin
< env
->nwindows
- 1)
3870 if (env
->otherwin
== 0)
3876 static target_ulong
get_ccr(void)
3882 return ((env
->xcc
>> 20) << 4) | ((psr
& PSR_ICC
) >> 20);
3885 target_ulong
cpu_get_ccr(CPUState
*env1
)
3887 CPUState
*saved_env
;
3897 static void put_ccr(target_ulong val
)
3899 target_ulong tmp
= val
;
3901 env
->xcc
= (tmp
>> 4) << 20;
3902 env
->psr
= (tmp
& 0xf) << 20;
3903 CC_OP
= CC_OP_FLAGS
;
3906 void cpu_put_ccr(CPUState
*env1
, target_ulong val
)
3908 CPUState
*saved_env
;
3916 static target_ulong
get_cwp64(void)
3918 return env
->nwindows
- 1 - env
->cwp
;
3921 target_ulong
cpu_get_cwp64(CPUState
*env1
)
3923 CPUState
*saved_env
;
3933 static void put_cwp64(int cwp
)
3935 if (unlikely(cwp
>= env
->nwindows
|| cwp
< 0)) {
3936 cwp
%= env
->nwindows
;
3938 set_cwp(env
->nwindows
- 1 - cwp
);
3941 void cpu_put_cwp64(CPUState
*env1
, int cwp
)
3943 CPUState
*saved_env
;
3951 target_ulong
helper_rdccr(void)
3956 void helper_wrccr(target_ulong new_ccr
)
3961 // CWP handling is reversed in V9, but we still use the V8 register
3963 target_ulong
helper_rdcwp(void)
3968 void helper_wrcwp(target_ulong new_cwp
)
3973 // This function uses non-native bit order
3974 #define GET_FIELD(X, FROM, TO) \
3975 ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
3977 // This function uses the order in the manuals, i.e. bit 0 is 2^0
3978 #define GET_FIELD_SP(X, FROM, TO) \
3979 GET_FIELD(X, 63 - (TO), 63 - (FROM))
3981 target_ulong
helper_array8(target_ulong pixel_addr
, target_ulong cubesize
)
3983 return (GET_FIELD_SP(pixel_addr
, 60, 63) << (17 + 2 * cubesize
)) |
3984 (GET_FIELD_SP(pixel_addr
, 39, 39 + cubesize
- 1) << (17 + cubesize
)) |
3985 (GET_FIELD_SP(pixel_addr
, 17 + cubesize
- 1, 17) << 17) |
3986 (GET_FIELD_SP(pixel_addr
, 56, 59) << 13) |
3987 (GET_FIELD_SP(pixel_addr
, 35, 38) << 9) |
3988 (GET_FIELD_SP(pixel_addr
, 13, 16) << 5) |
3989 (((pixel_addr
>> 55) & 1) << 4) |
3990 (GET_FIELD_SP(pixel_addr
, 33, 34) << 2) |
3991 GET_FIELD_SP(pixel_addr
, 11, 12);
3994 target_ulong
helper_alignaddr(target_ulong addr
, target_ulong offset
)
3998 tmp
= addr
+ offset
;
4000 env
->gsr
|= tmp
& 7ULL;
4004 target_ulong
helper_popc(target_ulong val
)
4006 return ctpop64(val
);
4009 static inline uint64_t *get_gregset(uint32_t pstate
)
4013 DPRINTF_PSTATE("ERROR in get_gregset: active pstate bits=%x%s%s%s\n",
4015 (pstate
& PS_IG
) ? " IG" : "",
4016 (pstate
& PS_MG
) ? " MG" : "",
4017 (pstate
& PS_AG
) ? " AG" : "");
4018 /* pass through to normal set of global registers */
4030 static inline void change_pstate(uint32_t new_pstate
)
4032 uint32_t pstate_regs
, new_pstate_regs
;
4033 uint64_t *src
, *dst
;
4035 if (env
->def
->features
& CPU_FEATURE_GL
) {
4036 // PS_AG is not implemented in this case
4037 new_pstate
&= ~PS_AG
;
4040 pstate_regs
= env
->pstate
& 0xc01;
4041 new_pstate_regs
= new_pstate
& 0xc01;
4043 if (new_pstate_regs
!= pstate_regs
) {
4044 DPRINTF_PSTATE("change_pstate: switching regs old=%x new=%x\n",
4045 pstate_regs
, new_pstate_regs
);
4046 // Switch global register bank
4047 src
= get_gregset(new_pstate_regs
);
4048 dst
= get_gregset(pstate_regs
);
4049 memcpy32(dst
, env
->gregs
);
4050 memcpy32(env
->gregs
, src
);
4053 DPRINTF_PSTATE("change_pstate: regs new=%x (unchanged)\n",
4056 env
->pstate
= new_pstate
;
4059 void helper_wrpstate(target_ulong new_state
)
4061 change_pstate(new_state
& 0xf3f);
4063 #if !defined(CONFIG_USER_ONLY)
4064 if (cpu_interrupts_enabled(env
)) {
4065 cpu_check_irqs(env
);
4070 void cpu_change_pstate(CPUState
*env1
, uint32_t new_pstate
)
4072 CPUState
*saved_env
;
4076 change_pstate(new_pstate
);
4080 void helper_wrpil(target_ulong new_pil
)
4082 #if !defined(CONFIG_USER_ONLY)
4083 DPRINTF_PSTATE("helper_wrpil old=%x new=%x\n",
4084 env
->psrpil
, (uint32_t)new_pil
);
4086 env
->psrpil
= new_pil
;
4088 if (cpu_interrupts_enabled(env
)) {
4089 cpu_check_irqs(env
);
4094 void helper_done(void)
4096 trap_state
* tsptr
= cpu_tsptr(env
);
4098 env
->pc
= tsptr
->tnpc
;
4099 env
->npc
= tsptr
->tnpc
+ 4;
4100 put_ccr(tsptr
->tstate
>> 32);
4101 env
->asi
= (tsptr
->tstate
>> 24) & 0xff;
4102 change_pstate((tsptr
->tstate
>> 8) & 0xf3f);
4103 put_cwp64(tsptr
->tstate
& 0xff);
4106 DPRINTF_PSTATE("... helper_done tl=%d\n", env
->tl
);
4108 #if !defined(CONFIG_USER_ONLY)
4109 if (cpu_interrupts_enabled(env
)) {
4110 cpu_check_irqs(env
);
4115 void helper_retry(void)
4117 trap_state
* tsptr
= cpu_tsptr(env
);
4119 env
->pc
= tsptr
->tpc
;
4120 env
->npc
= tsptr
->tnpc
;
4121 put_ccr(tsptr
->tstate
>> 32);
4122 env
->asi
= (tsptr
->tstate
>> 24) & 0xff;
4123 change_pstate((tsptr
->tstate
>> 8) & 0xf3f);
4124 put_cwp64(tsptr
->tstate
& 0xff);
4127 DPRINTF_PSTATE("... helper_retry tl=%d\n", env
->tl
);
4129 #if !defined(CONFIG_USER_ONLY)
4130 if (cpu_interrupts_enabled(env
)) {
4131 cpu_check_irqs(env
);
4136 static void do_modify_softint(const char* operation
, uint32_t value
)
4138 if (env
->softint
!= value
) {
4139 env
->softint
= value
;
4140 DPRINTF_PSTATE(": %s new %08x\n", operation
, env
->softint
);
4141 #if !defined(CONFIG_USER_ONLY)
4142 if (cpu_interrupts_enabled(env
)) {
4143 cpu_check_irqs(env
);
4149 void helper_set_softint(uint64_t value
)
4151 do_modify_softint("helper_set_softint", env
->softint
| (uint32_t)value
);
4154 void helper_clear_softint(uint64_t value
)
4156 do_modify_softint("helper_clear_softint", env
->softint
& (uint32_t)~value
);
4159 void helper_write_softint(uint64_t value
)
4161 do_modify_softint("helper_write_softint", (uint32_t)value
);
4165 #ifdef TARGET_SPARC64
4166 trap_state
* cpu_tsptr(CPUState
* env
)
4168 return &env
->ts
[env
->tl
& MAXTL_MASK
];
4172 #if !defined(CONFIG_USER_ONLY)
4174 static void do_unaligned_access(target_ulong addr
, int is_write
, int is_user
,
4177 #define MMUSUFFIX _mmu
4178 #define ALIGNED_ONLY
4181 #include "softmmu_template.h"
4184 #include "softmmu_template.h"
4187 #include "softmmu_template.h"
4190 #include "softmmu_template.h"
4192 /* XXX: make it generic ? */
4193 static void cpu_restore_state2(void *retaddr
)
4195 TranslationBlock
*tb
;
4199 /* now we have a real cpu fault */
4200 pc
= (unsigned long)retaddr
;
4201 tb
= tb_find_pc(pc
);
4203 /* the PC is inside the translated code. It means that we have
4204 a virtual CPU fault */
4205 cpu_restore_state(tb
, env
, pc
);
4210 static void do_unaligned_access(target_ulong addr
, int is_write
, int is_user
,
4213 #ifdef DEBUG_UNALIGNED
4214 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
4215 "\n", addr
, env
->pc
);
4217 cpu_restore_state2(retaddr
);
4218 raise_exception(TT_UNALIGNED
);
4221 /* try to fill the TLB and return an exception if error. If retaddr is
4222 NULL, it means that the function was called in C code (i.e. not
4223 from generated code or from helper.c) */
4224 /* XXX: fix it to restore all registers */
4225 void tlb_fill(target_ulong addr
, int is_write
, int mmu_idx
, void *retaddr
)
4228 CPUState
*saved_env
;
4230 /* XXX: hack to restore env in all cases, even if not called from
4233 env
= cpu_single_env
;
4235 ret
= cpu_sparc_handle_mmu_fault(env
, addr
, is_write
, mmu_idx
, 1);
4237 cpu_restore_state2(retaddr
);
4243 #endif /* !CONFIG_USER_ONLY */
4245 #ifndef TARGET_SPARC64
4246 #if !defined(CONFIG_USER_ONLY)
4247 static void do_unassigned_access(target_phys_addr_t addr
, int is_write
,
4248 int is_exec
, int is_asi
, int size
)
4250 CPUState
*saved_env
;
4253 /* XXX: hack to restore env in all cases, even if not called from
4256 env
= cpu_single_env
;
4257 #ifdef DEBUG_UNASSIGNED
4259 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
4260 " asi 0x%02x from " TARGET_FMT_lx
"\n",
4261 is_exec
? "exec" : is_write
? "write" : "read", size
,
4262 size
== 1 ? "" : "s", addr
, is_asi
, env
->pc
);
4264 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
4265 " from " TARGET_FMT_lx
"\n",
4266 is_exec
? "exec" : is_write
? "write" : "read", size
,
4267 size
== 1 ? "" : "s", addr
, env
->pc
);
4269 /* Don't overwrite translation and access faults */
4270 fault_type
= (env
->mmuregs
[3] & 0x1c) >> 2;
4271 if ((fault_type
> 4) || (fault_type
== 0)) {
4272 env
->mmuregs
[3] = 0; /* Fault status register */
4274 env
->mmuregs
[3] |= 1 << 16;
4276 env
->mmuregs
[3] |= 1 << 5;
4278 env
->mmuregs
[3] |= 1 << 6;
4280 env
->mmuregs
[3] |= 1 << 7;
4281 env
->mmuregs
[3] |= (5 << 2) | 2;
4282 /* SuperSPARC will never place instruction fault addresses in the FAR */
4284 env
->mmuregs
[4] = addr
; /* Fault address register */
4287 /* overflow (same type fault was not read before another fault) */
4288 if (fault_type
== ((env
->mmuregs
[3] & 0x1c)) >> 2) {
4289 env
->mmuregs
[3] |= 1;
4292 if ((env
->mmuregs
[0] & MMU_E
) && !(env
->mmuregs
[0] & MMU_NF
)) {
4294 raise_exception(TT_CODE_ACCESS
);
4296 raise_exception(TT_DATA_ACCESS
);
4299 /* flush neverland mappings created during no-fault mode,
4300 so the sequential MMU faults report proper fault types */
4301 if (env
->mmuregs
[0] & MMU_NF
) {
4309 #if defined(CONFIG_USER_ONLY)
4310 static void do_unassigned_access(target_ulong addr
, int is_write
, int is_exec
,
4311 int is_asi
, int size
)
4313 static void do_unassigned_access(target_phys_addr_t addr
, int is_write
,
4314 int is_exec
, int is_asi
, int size
)
4317 CPUState
*saved_env
;
4319 /* XXX: hack to restore env in all cases, even if not called from
4322 env
= cpu_single_env
;
4324 #ifdef DEBUG_UNASSIGNED
4325 printf("Unassigned mem access to " TARGET_FMT_plx
" from " TARGET_FMT_lx
4326 "\n", addr
, env
->pc
);
4330 raise_exception(TT_CODE_ACCESS
);
4332 raise_exception(TT_DATA_ACCESS
);
4339 #ifdef TARGET_SPARC64
4340 void helper_tick_set_count(void *opaque
, uint64_t count
)
4342 #if !defined(CONFIG_USER_ONLY)
4343 cpu_tick_set_count(opaque
, count
);
4347 uint64_t helper_tick_get_count(void *opaque
)
4349 #if !defined(CONFIG_USER_ONLY)
4350 return cpu_tick_get_count(opaque
);
4356 void helper_tick_set_limit(void *opaque
, uint64_t limit
)
4358 #if !defined(CONFIG_USER_ONLY)
4359 cpu_tick_set_limit(opaque
, limit
);
4364 #if !defined(CONFIG_USER_ONLY)
4365 void cpu_unassigned_access(CPUState
*env1
, target_phys_addr_t addr
,
4366 int is_write
, int is_exec
, int is_asi
, int size
)
4369 do_unassigned_access(addr
, is_write
, is_exec
, is_asi
, size
);