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Make UA200x features selectable, add MMU types
[qemu.git] / target-sparc / op_helper.c
1 #include "exec.h"
2 #include "host-utils.h"
3 #include "helper.h"
4 #if !defined(CONFIG_USER_ONLY)
5 #include "softmmu_exec.h"
6 #endif /* !defined(CONFIG_USER_ONLY) */
7
8 //#define DEBUG_MMU
9 //#define DEBUG_MXCC
10 //#define DEBUG_UNALIGNED
11 //#define DEBUG_UNASSIGNED
12 //#define DEBUG_ASI
13
14 #ifdef DEBUG_MMU
15 #define DPRINTF_MMU(fmt, args...) \
16 do { printf("MMU: " fmt , ##args); } while (0)
17 #else
18 #define DPRINTF_MMU(fmt, args...) do {} while (0)
19 #endif
20
21 #ifdef DEBUG_MXCC
22 #define DPRINTF_MXCC(fmt, args...) \
23 do { printf("MXCC: " fmt , ##args); } while (0)
24 #else
25 #define DPRINTF_MXCC(fmt, args...) do {} while (0)
26 #endif
27
28 #ifdef DEBUG_ASI
29 #define DPRINTF_ASI(fmt, args...) \
30 do { printf("ASI: " fmt , ##args); } while (0)
31 #else
32 #define DPRINTF_ASI(fmt, args...) do {} while (0)
33 #endif
34
35 #ifdef TARGET_SPARC64
36 #ifndef TARGET_ABI32
37 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
38 #else
39 #define AM_CHECK(env1) (1)
40 #endif
41 #endif
42
43 static inline void address_mask(CPUState *env1, target_ulong *addr)
44 {
45 #ifdef TARGET_SPARC64
46 if (AM_CHECK(env1))
47 *addr &= 0xffffffffULL;
48 #endif
49 }
50
51 void raise_exception(int tt)
52 {
53 env->exception_index = tt;
54 cpu_loop_exit();
55 }
56
57 void helper_trap(target_ulong nb_trap)
58 {
59 env->exception_index = TT_TRAP + (nb_trap & 0x7f);
60 cpu_loop_exit();
61 }
62
63 void helper_trapcc(target_ulong nb_trap, target_ulong do_trap)
64 {
65 if (do_trap) {
66 env->exception_index = TT_TRAP + (nb_trap & 0x7f);
67 cpu_loop_exit();
68 }
69 }
70
71 void helper_check_align(target_ulong addr, uint32_t align)
72 {
73 if (addr & align) {
74 #ifdef DEBUG_UNALIGNED
75 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
76 "\n", addr, env->pc);
77 #endif
78 raise_exception(TT_UNALIGNED);
79 }
80 }
81
82 #define F_HELPER(name, p) void helper_f##name##p(void)
83
84 #define F_BINOP(name) \
85 F_HELPER(name, s) \
86 { \
87 FT0 = float32_ ## name (FT0, FT1, &env->fp_status); \
88 } \
89 F_HELPER(name, d) \
90 { \
91 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
92 } \
93 F_HELPER(name, q) \
94 { \
95 QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
96 }
97
98 F_BINOP(add);
99 F_BINOP(sub);
100 F_BINOP(mul);
101 F_BINOP(div);
102 #undef F_BINOP
103
104 void helper_fsmuld(void)
105 {
106 DT0 = float64_mul(float32_to_float64(FT0, &env->fp_status),
107 float32_to_float64(FT1, &env->fp_status),
108 &env->fp_status);
109 }
110
111 void helper_fdmulq(void)
112 {
113 QT0 = float128_mul(float64_to_float128(DT0, &env->fp_status),
114 float64_to_float128(DT1, &env->fp_status),
115 &env->fp_status);
116 }
117
118 F_HELPER(neg, s)
119 {
120 FT0 = float32_chs(FT1);
121 }
122
123 #ifdef TARGET_SPARC64
124 F_HELPER(neg, d)
125 {
126 DT0 = float64_chs(DT1);
127 }
128
129 F_HELPER(neg, q)
130 {
131 QT0 = float128_chs(QT1);
132 }
133 #endif
134
135 /* Integer to float conversion. */
136 F_HELPER(ito, s)
137 {
138 FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status);
139 }
140
141 F_HELPER(ito, d)
142 {
143 DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status);
144 }
145
146 F_HELPER(ito, q)
147 {
148 QT0 = int32_to_float128(*((int32_t *)&FT1), &env->fp_status);
149 }
150
151 #ifdef TARGET_SPARC64
152 F_HELPER(xto, s)
153 {
154 FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
155 }
156
157 F_HELPER(xto, d)
158 {
159 DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
160 }
161
162 F_HELPER(xto, q)
163 {
164 QT0 = int64_to_float128(*((int64_t *)&DT1), &env->fp_status);
165 }
166 #endif
167 #undef F_HELPER
168
169 /* floating point conversion */
170 void helper_fdtos(void)
171 {
172 FT0 = float64_to_float32(DT1, &env->fp_status);
173 }
174
175 void helper_fstod(void)
176 {
177 DT0 = float32_to_float64(FT1, &env->fp_status);
178 }
179
180 void helper_fqtos(void)
181 {
182 FT0 = float128_to_float32(QT1, &env->fp_status);
183 }
184
185 void helper_fstoq(void)
186 {
187 QT0 = float32_to_float128(FT1, &env->fp_status);
188 }
189
190 void helper_fqtod(void)
191 {
192 DT0 = float128_to_float64(QT1, &env->fp_status);
193 }
194
195 void helper_fdtoq(void)
196 {
197 QT0 = float64_to_float128(DT1, &env->fp_status);
198 }
199
200 /* Float to integer conversion. */
201 void helper_fstoi(void)
202 {
203 *((int32_t *)&FT0) = float32_to_int32_round_to_zero(FT1, &env->fp_status);
204 }
205
206 void helper_fdtoi(void)
207 {
208 *((int32_t *)&FT0) = float64_to_int32_round_to_zero(DT1, &env->fp_status);
209 }
210
211 void helper_fqtoi(void)
212 {
213 *((int32_t *)&FT0) = float128_to_int32_round_to_zero(QT1, &env->fp_status);
214 }
215
216 #ifdef TARGET_SPARC64
217 void helper_fstox(void)
218 {
219 *((int64_t *)&DT0) = float32_to_int64_round_to_zero(FT1, &env->fp_status);
220 }
221
222 void helper_fdtox(void)
223 {
224 *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status);
225 }
226
227 void helper_fqtox(void)
228 {
229 *((int64_t *)&DT0) = float128_to_int64_round_to_zero(QT1, &env->fp_status);
230 }
231
232 void helper_faligndata(void)
233 {
234 uint64_t tmp;
235
236 tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8);
237 tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8);
238 *((uint64_t *)&DT0) = tmp;
239 }
240
241 void helper_movl_FT0_0(void)
242 {
243 *((uint32_t *)&FT0) = 0;
244 }
245
246 void helper_movl_DT0_0(void)
247 {
248 *((uint64_t *)&DT0) = 0;
249 }
250
251 void helper_movl_FT0_1(void)
252 {
253 *((uint32_t *)&FT0) = 0xffffffff;
254 }
255
256 void helper_movl_DT0_1(void)
257 {
258 *((uint64_t *)&DT0) = 0xffffffffffffffffULL;
259 }
260
261 void helper_fnot(void)
262 {
263 *(uint64_t *)&DT0 = ~*(uint64_t *)&DT1;
264 }
265
266 void helper_fnots(void)
267 {
268 *(uint32_t *)&FT0 = ~*(uint32_t *)&FT1;
269 }
270
271 void helper_fnor(void)
272 {
273 *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 | *(uint64_t *)&DT1);
274 }
275
276 void helper_fnors(void)
277 {
278 *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 | *(uint32_t *)&FT1);
279 }
280
281 void helper_for(void)
282 {
283 *(uint64_t *)&DT0 |= *(uint64_t *)&DT1;
284 }
285
286 void helper_fors(void)
287 {
288 *(uint32_t *)&FT0 |= *(uint32_t *)&FT1;
289 }
290
291 void helper_fxor(void)
292 {
293 *(uint64_t *)&DT0 ^= *(uint64_t *)&DT1;
294 }
295
296 void helper_fxors(void)
297 {
298 *(uint32_t *)&FT0 ^= *(uint32_t *)&FT1;
299 }
300
301 void helper_fand(void)
302 {
303 *(uint64_t *)&DT0 &= *(uint64_t *)&DT1;
304 }
305
306 void helper_fands(void)
307 {
308 *(uint32_t *)&FT0 &= *(uint32_t *)&FT1;
309 }
310
311 void helper_fornot(void)
312 {
313 *(uint64_t *)&DT0 = *(uint64_t *)&DT0 | ~*(uint64_t *)&DT1;
314 }
315
316 void helper_fornots(void)
317 {
318 *(uint32_t *)&FT0 = *(uint32_t *)&FT0 | ~*(uint32_t *)&FT1;
319 }
320
321 void helper_fandnot(void)
322 {
323 *(uint64_t *)&DT0 = *(uint64_t *)&DT0 & ~*(uint64_t *)&DT1;
324 }
325
326 void helper_fandnots(void)
327 {
328 *(uint32_t *)&FT0 = *(uint32_t *)&FT0 & ~*(uint32_t *)&FT1;
329 }
330
331 void helper_fnand(void)
332 {
333 *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 & *(uint64_t *)&DT1);
334 }
335
336 void helper_fnands(void)
337 {
338 *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 & *(uint32_t *)&FT1);
339 }
340
341 void helper_fxnor(void)
342 {
343 *(uint64_t *)&DT0 ^= ~*(uint64_t *)&DT1;
344 }
345
346 void helper_fxnors(void)
347 {
348 *(uint32_t *)&FT0 ^= ~*(uint32_t *)&FT1;
349 }
350
351 #ifdef WORDS_BIGENDIAN
352 #define VIS_B64(n) b[7 - (n)]
353 #define VIS_W64(n) w[3 - (n)]
354 #define VIS_SW64(n) sw[3 - (n)]
355 #define VIS_L64(n) l[1 - (n)]
356 #define VIS_B32(n) b[3 - (n)]
357 #define VIS_W32(n) w[1 - (n)]
358 #else
359 #define VIS_B64(n) b[n]
360 #define VIS_W64(n) w[n]
361 #define VIS_SW64(n) sw[n]
362 #define VIS_L64(n) l[n]
363 #define VIS_B32(n) b[n]
364 #define VIS_W32(n) w[n]
365 #endif
366
367 typedef union {
368 uint8_t b[8];
369 uint16_t w[4];
370 int16_t sw[4];
371 uint32_t l[2];
372 float64 d;
373 } vis64;
374
375 typedef union {
376 uint8_t b[4];
377 uint16_t w[2];
378 uint32_t l;
379 float32 f;
380 } vis32;
381
382 void helper_fpmerge(void)
383 {
384 vis64 s, d;
385
386 s.d = DT0;
387 d.d = DT1;
388
389 // Reverse calculation order to handle overlap
390 d.VIS_B64(7) = s.VIS_B64(3);
391 d.VIS_B64(6) = d.VIS_B64(3);
392 d.VIS_B64(5) = s.VIS_B64(2);
393 d.VIS_B64(4) = d.VIS_B64(2);
394 d.VIS_B64(3) = s.VIS_B64(1);
395 d.VIS_B64(2) = d.VIS_B64(1);
396 d.VIS_B64(1) = s.VIS_B64(0);
397 //d.VIS_B64(0) = d.VIS_B64(0);
398
399 DT0 = d.d;
400 }
401
402 void helper_fmul8x16(void)
403 {
404 vis64 s, d;
405 uint32_t tmp;
406
407 s.d = DT0;
408 d.d = DT1;
409
410 #define PMUL(r) \
411 tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
412 if ((tmp & 0xff) > 0x7f) \
413 tmp += 0x100; \
414 d.VIS_W64(r) = tmp >> 8;
415
416 PMUL(0);
417 PMUL(1);
418 PMUL(2);
419 PMUL(3);
420 #undef PMUL
421
422 DT0 = d.d;
423 }
424
425 void helper_fmul8x16al(void)
426 {
427 vis64 s, d;
428 uint32_t tmp;
429
430 s.d = DT0;
431 d.d = DT1;
432
433 #define PMUL(r) \
434 tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
435 if ((tmp & 0xff) > 0x7f) \
436 tmp += 0x100; \
437 d.VIS_W64(r) = tmp >> 8;
438
439 PMUL(0);
440 PMUL(1);
441 PMUL(2);
442 PMUL(3);
443 #undef PMUL
444
445 DT0 = d.d;
446 }
447
448 void helper_fmul8x16au(void)
449 {
450 vis64 s, d;
451 uint32_t tmp;
452
453 s.d = DT0;
454 d.d = DT1;
455
456 #define PMUL(r) \
457 tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
458 if ((tmp & 0xff) > 0x7f) \
459 tmp += 0x100; \
460 d.VIS_W64(r) = tmp >> 8;
461
462 PMUL(0);
463 PMUL(1);
464 PMUL(2);
465 PMUL(3);
466 #undef PMUL
467
468 DT0 = d.d;
469 }
470
471 void helper_fmul8sux16(void)
472 {
473 vis64 s, d;
474 uint32_t tmp;
475
476 s.d = DT0;
477 d.d = DT1;
478
479 #define PMUL(r) \
480 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
481 if ((tmp & 0xff) > 0x7f) \
482 tmp += 0x100; \
483 d.VIS_W64(r) = tmp >> 8;
484
485 PMUL(0);
486 PMUL(1);
487 PMUL(2);
488 PMUL(3);
489 #undef PMUL
490
491 DT0 = d.d;
492 }
493
494 void helper_fmul8ulx16(void)
495 {
496 vis64 s, d;
497 uint32_t tmp;
498
499 s.d = DT0;
500 d.d = DT1;
501
502 #define PMUL(r) \
503 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
504 if ((tmp & 0xff) > 0x7f) \
505 tmp += 0x100; \
506 d.VIS_W64(r) = tmp >> 8;
507
508 PMUL(0);
509 PMUL(1);
510 PMUL(2);
511 PMUL(3);
512 #undef PMUL
513
514 DT0 = d.d;
515 }
516
517 void helper_fmuld8sux16(void)
518 {
519 vis64 s, d;
520 uint32_t tmp;
521
522 s.d = DT0;
523 d.d = DT1;
524
525 #define PMUL(r) \
526 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
527 if ((tmp & 0xff) > 0x7f) \
528 tmp += 0x100; \
529 d.VIS_L64(r) = tmp;
530
531 // Reverse calculation order to handle overlap
532 PMUL(1);
533 PMUL(0);
534 #undef PMUL
535
536 DT0 = d.d;
537 }
538
539 void helper_fmuld8ulx16(void)
540 {
541 vis64 s, d;
542 uint32_t tmp;
543
544 s.d = DT0;
545 d.d = DT1;
546
547 #define PMUL(r) \
548 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
549 if ((tmp & 0xff) > 0x7f) \
550 tmp += 0x100; \
551 d.VIS_L64(r) = tmp;
552
553 // Reverse calculation order to handle overlap
554 PMUL(1);
555 PMUL(0);
556 #undef PMUL
557
558 DT0 = d.d;
559 }
560
561 void helper_fexpand(void)
562 {
563 vis32 s;
564 vis64 d;
565
566 s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff);
567 d.d = DT1;
568 d.VIS_L64(0) = s.VIS_W32(0) << 4;
569 d.VIS_L64(1) = s.VIS_W32(1) << 4;
570 d.VIS_L64(2) = s.VIS_W32(2) << 4;
571 d.VIS_L64(3) = s.VIS_W32(3) << 4;
572
573 DT0 = d.d;
574 }
575
576 #define VIS_HELPER(name, F) \
577 void name##16(void) \
578 { \
579 vis64 s, d; \
580 \
581 s.d = DT0; \
582 d.d = DT1; \
583 \
584 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
585 d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
586 d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
587 d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
588 \
589 DT0 = d.d; \
590 } \
591 \
592 void name##16s(void) \
593 { \
594 vis32 s, d; \
595 \
596 s.f = FT0; \
597 d.f = FT1; \
598 \
599 d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
600 d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
601 \
602 FT0 = d.f; \
603 } \
604 \
605 void name##32(void) \
606 { \
607 vis64 s, d; \
608 \
609 s.d = DT0; \
610 d.d = DT1; \
611 \
612 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
613 d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
614 \
615 DT0 = d.d; \
616 } \
617 \
618 void name##32s(void) \
619 { \
620 vis32 s, d; \
621 \
622 s.f = FT0; \
623 d.f = FT1; \
624 \
625 d.l = F(d.l, s.l); \
626 \
627 FT0 = d.f; \
628 }
629
630 #define FADD(a, b) ((a) + (b))
631 #define FSUB(a, b) ((a) - (b))
632 VIS_HELPER(helper_fpadd, FADD)
633 VIS_HELPER(helper_fpsub, FSUB)
634
635 #define VIS_CMPHELPER(name, F) \
636 void name##16(void) \
637 { \
638 vis64 s, d; \
639 \
640 s.d = DT0; \
641 d.d = DT1; \
642 \
643 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \
644 d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \
645 d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \
646 d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \
647 \
648 DT0 = d.d; \
649 } \
650 \
651 void name##32(void) \
652 { \
653 vis64 s, d; \
654 \
655 s.d = DT0; \
656 d.d = DT1; \
657 \
658 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \
659 d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \
660 \
661 DT0 = d.d; \
662 }
663
664 #define FCMPGT(a, b) ((a) > (b))
665 #define FCMPEQ(a, b) ((a) == (b))
666 #define FCMPLE(a, b) ((a) <= (b))
667 #define FCMPNE(a, b) ((a) != (b))
668
669 VIS_CMPHELPER(helper_fcmpgt, FCMPGT)
670 VIS_CMPHELPER(helper_fcmpeq, FCMPEQ)
671 VIS_CMPHELPER(helper_fcmple, FCMPLE)
672 VIS_CMPHELPER(helper_fcmpne, FCMPNE)
673 #endif
674
675 void helper_check_ieee_exceptions(void)
676 {
677 target_ulong status;
678
679 status = get_float_exception_flags(&env->fp_status);
680 if (status) {
681 /* Copy IEEE 754 flags into FSR */
682 if (status & float_flag_invalid)
683 env->fsr |= FSR_NVC;
684 if (status & float_flag_overflow)
685 env->fsr |= FSR_OFC;
686 if (status & float_flag_underflow)
687 env->fsr |= FSR_UFC;
688 if (status & float_flag_divbyzero)
689 env->fsr |= FSR_DZC;
690 if (status & float_flag_inexact)
691 env->fsr |= FSR_NXC;
692
693 if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
694 /* Unmasked exception, generate a trap */
695 env->fsr |= FSR_FTT_IEEE_EXCP;
696 raise_exception(TT_FP_EXCP);
697 } else {
698 /* Accumulate exceptions */
699 env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
700 }
701 }
702 }
703
704 void helper_clear_float_exceptions(void)
705 {
706 set_float_exception_flags(0, &env->fp_status);
707 }
708
709 void helper_fabss(void)
710 {
711 FT0 = float32_abs(FT1);
712 }
713
714 #ifdef TARGET_SPARC64
715 void helper_fabsd(void)
716 {
717 DT0 = float64_abs(DT1);
718 }
719
720 void helper_fabsq(void)
721 {
722 QT0 = float128_abs(QT1);
723 }
724 #endif
725
726 void helper_fsqrts(void)
727 {
728 FT0 = float32_sqrt(FT1, &env->fp_status);
729 }
730
731 void helper_fsqrtd(void)
732 {
733 DT0 = float64_sqrt(DT1, &env->fp_status);
734 }
735
736 void helper_fsqrtq(void)
737 {
738 QT0 = float128_sqrt(QT1, &env->fp_status);
739 }
740
741 #define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
742 void glue(helper_, name) (void) \
743 { \
744 target_ulong new_fsr; \
745 \
746 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
747 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
748 case float_relation_unordered: \
749 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
750 if ((env->fsr & FSR_NVM) || TRAP) { \
751 env->fsr |= new_fsr; \
752 env->fsr |= FSR_NVC; \
753 env->fsr |= FSR_FTT_IEEE_EXCP; \
754 raise_exception(TT_FP_EXCP); \
755 } else { \
756 env->fsr |= FSR_NVA; \
757 } \
758 break; \
759 case float_relation_less: \
760 new_fsr = FSR_FCC0 << FS; \
761 break; \
762 case float_relation_greater: \
763 new_fsr = FSR_FCC1 << FS; \
764 break; \
765 default: \
766 new_fsr = 0; \
767 break; \
768 } \
769 env->fsr |= new_fsr; \
770 }
771
772 GEN_FCMP(fcmps, float32, FT0, FT1, 0, 0);
773 GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);
774
775 GEN_FCMP(fcmpes, float32, FT0, FT1, 0, 1);
776 GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
777
778 GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
779 GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
780
781 #ifdef TARGET_SPARC64
782 GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22, 0);
783 GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
784 GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);
785
786 GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24, 0);
787 GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);
788 GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);
789
790 GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26, 0);
791 GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);
792 GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);
793
794 GEN_FCMP(fcmpes_fcc1, float32, FT0, FT1, 22, 1);
795 GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);
796 GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);
797
798 GEN_FCMP(fcmpes_fcc2, float32, FT0, FT1, 24, 1);
799 GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
800 GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);
801
802 GEN_FCMP(fcmpes_fcc3, float32, FT0, FT1, 26, 1);
803 GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
804 GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
805 #endif
806
807 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
808 defined(DEBUG_MXCC)
809 static void dump_mxcc(CPUState *env)
810 {
811 printf("mxccdata: %016llx %016llx %016llx %016llx\n",
812 env->mxccdata[0], env->mxccdata[1],
813 env->mxccdata[2], env->mxccdata[3]);
814 printf("mxccregs: %016llx %016llx %016llx %016llx\n"
815 " %016llx %016llx %016llx %016llx\n",
816 env->mxccregs[0], env->mxccregs[1],
817 env->mxccregs[2], env->mxccregs[3],
818 env->mxccregs[4], env->mxccregs[5],
819 env->mxccregs[6], env->mxccregs[7]);
820 }
821 #endif
822
823 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
824 && defined(DEBUG_ASI)
825 static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
826 uint64_t r1)
827 {
828 switch (size)
829 {
830 case 1:
831 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
832 addr, asi, r1 & 0xff);
833 break;
834 case 2:
835 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
836 addr, asi, r1 & 0xffff);
837 break;
838 case 4:
839 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
840 addr, asi, r1 & 0xffffffff);
841 break;
842 case 8:
843 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
844 addr, asi, r1);
845 break;
846 }
847 }
848 #endif
849
850 #ifndef TARGET_SPARC64
851 #ifndef CONFIG_USER_ONLY
852 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
853 {
854 uint64_t ret = 0;
855 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
856 uint32_t last_addr = addr;
857 #endif
858
859 helper_check_align(addr, size - 1);
860 switch (asi) {
861 case 2: /* SuperSparc MXCC registers */
862 switch (addr) {
863 case 0x01c00a00: /* MXCC control register */
864 if (size == 8)
865 ret = env->mxccregs[3];
866 else
867 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
868 size);
869 break;
870 case 0x01c00a04: /* MXCC control register */
871 if (size == 4)
872 ret = env->mxccregs[3];
873 else
874 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
875 size);
876 break;
877 case 0x01c00c00: /* Module reset register */
878 if (size == 8) {
879 ret = env->mxccregs[5];
880 // should we do something here?
881 } else
882 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
883 size);
884 break;
885 case 0x01c00f00: /* MBus port address register */
886 if (size == 8)
887 ret = env->mxccregs[7];
888 else
889 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
890 size);
891 break;
892 default:
893 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
894 size);
895 break;
896 }
897 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
898 "addr = %08x -> ret = %08x,"
899 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
900 #ifdef DEBUG_MXCC
901 dump_mxcc(env);
902 #endif
903 break;
904 case 3: /* MMU probe */
905 {
906 int mmulev;
907
908 mmulev = (addr >> 8) & 15;
909 if (mmulev > 4)
910 ret = 0;
911 else
912 ret = mmu_probe(env, addr, mmulev);
913 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
914 addr, mmulev, ret);
915 }
916 break;
917 case 4: /* read MMU regs */
918 {
919 int reg = (addr >> 8) & 0x1f;
920
921 ret = env->mmuregs[reg];
922 if (reg == 3) /* Fault status cleared on read */
923 env->mmuregs[3] = 0;
924 else if (reg == 0x13) /* Fault status read */
925 ret = env->mmuregs[3];
926 else if (reg == 0x14) /* Fault address read */
927 ret = env->mmuregs[4];
928 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
929 }
930 break;
931 case 5: // Turbosparc ITLB Diagnostic
932 case 6: // Turbosparc DTLB Diagnostic
933 case 7: // Turbosparc IOTLB Diagnostic
934 break;
935 case 9: /* Supervisor code access */
936 switch(size) {
937 case 1:
938 ret = ldub_code(addr);
939 break;
940 case 2:
941 ret = lduw_code(addr);
942 break;
943 default:
944 case 4:
945 ret = ldl_code(addr);
946 break;
947 case 8:
948 ret = ldq_code(addr);
949 break;
950 }
951 break;
952 case 0xa: /* User data access */
953 switch(size) {
954 case 1:
955 ret = ldub_user(addr);
956 break;
957 case 2:
958 ret = lduw_user(addr);
959 break;
960 default:
961 case 4:
962 ret = ldl_user(addr);
963 break;
964 case 8:
965 ret = ldq_user(addr);
966 break;
967 }
968 break;
969 case 0xb: /* Supervisor data access */
970 switch(size) {
971 case 1:
972 ret = ldub_kernel(addr);
973 break;
974 case 2:
975 ret = lduw_kernel(addr);
976 break;
977 default:
978 case 4:
979 ret = ldl_kernel(addr);
980 break;
981 case 8:
982 ret = ldq_kernel(addr);
983 break;
984 }
985 break;
986 case 0xc: /* I-cache tag */
987 case 0xd: /* I-cache data */
988 case 0xe: /* D-cache tag */
989 case 0xf: /* D-cache data */
990 break;
991 case 0x20: /* MMU passthrough */
992 switch(size) {
993 case 1:
994 ret = ldub_phys(addr);
995 break;
996 case 2:
997 ret = lduw_phys(addr);
998 break;
999 default:
1000 case 4:
1001 ret = ldl_phys(addr);
1002 break;
1003 case 8:
1004 ret = ldq_phys(addr);
1005 break;
1006 }
1007 break;
1008 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1009 switch(size) {
1010 case 1:
1011 ret = ldub_phys((target_phys_addr_t)addr
1012 | ((target_phys_addr_t)(asi & 0xf) << 32));
1013 break;
1014 case 2:
1015 ret = lduw_phys((target_phys_addr_t)addr
1016 | ((target_phys_addr_t)(asi & 0xf) << 32));
1017 break;
1018 default:
1019 case 4:
1020 ret = ldl_phys((target_phys_addr_t)addr
1021 | ((target_phys_addr_t)(asi & 0xf) << 32));
1022 break;
1023 case 8:
1024 ret = ldq_phys((target_phys_addr_t)addr
1025 | ((target_phys_addr_t)(asi & 0xf) << 32));
1026 break;
1027 }
1028 break;
1029 case 0x30: // Turbosparc secondary cache diagnostic
1030 case 0x31: // Turbosparc RAM snoop
1031 case 0x32: // Turbosparc page table descriptor diagnostic
1032 case 0x39: /* data cache diagnostic register */
1033 ret = 0;
1034 break;
1035 case 8: /* User code access, XXX */
1036 default:
1037 do_unassigned_access(addr, 0, 0, asi);
1038 ret = 0;
1039 break;
1040 }
1041 if (sign) {
1042 switch(size) {
1043 case 1:
1044 ret = (int8_t) ret;
1045 break;
1046 case 2:
1047 ret = (int16_t) ret;
1048 break;
1049 case 4:
1050 ret = (int32_t) ret;
1051 break;
1052 default:
1053 break;
1054 }
1055 }
1056 #ifdef DEBUG_ASI
1057 dump_asi("read ", last_addr, asi, size, ret);
1058 #endif
1059 return ret;
1060 }
1061
1062 void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
1063 {
1064 helper_check_align(addr, size - 1);
1065 switch(asi) {
1066 case 2: /* SuperSparc MXCC registers */
1067 switch (addr) {
1068 case 0x01c00000: /* MXCC stream data register 0 */
1069 if (size == 8)
1070 env->mxccdata[0] = val;
1071 else
1072 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1073 size);
1074 break;
1075 case 0x01c00008: /* MXCC stream data register 1 */
1076 if (size == 8)
1077 env->mxccdata[1] = val;
1078 else
1079 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1080 size);
1081 break;
1082 case 0x01c00010: /* MXCC stream data register 2 */
1083 if (size == 8)
1084 env->mxccdata[2] = val;
1085 else
1086 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1087 size);
1088 break;
1089 case 0x01c00018: /* MXCC stream data register 3 */
1090 if (size == 8)
1091 env->mxccdata[3] = val;
1092 else
1093 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1094 size);
1095 break;
1096 case 0x01c00100: /* MXCC stream source */
1097 if (size == 8)
1098 env->mxccregs[0] = val;
1099 else
1100 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1101 size);
1102 env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1103 0);
1104 env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1105 8);
1106 env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1107 16);
1108 env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1109 24);
1110 break;
1111 case 0x01c00200: /* MXCC stream destination */
1112 if (size == 8)
1113 env->mxccregs[1] = val;
1114 else
1115 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1116 size);
1117 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0,
1118 env->mxccdata[0]);
1119 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8,
1120 env->mxccdata[1]);
1121 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16,
1122 env->mxccdata[2]);
1123 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24,
1124 env->mxccdata[3]);
1125 break;
1126 case 0x01c00a00: /* MXCC control register */
1127 if (size == 8)
1128 env->mxccregs[3] = val;
1129 else
1130 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1131 size);
1132 break;
1133 case 0x01c00a04: /* MXCC control register */
1134 if (size == 4)
1135 env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000ULL)
1136 | val;
1137 else
1138 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1139 size);
1140 break;
1141 case 0x01c00e00: /* MXCC error register */
1142 // writing a 1 bit clears the error
1143 if (size == 8)
1144 env->mxccregs[6] &= ~val;
1145 else
1146 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1147 size);
1148 break;
1149 case 0x01c00f00: /* MBus port address register */
1150 if (size == 8)
1151 env->mxccregs[7] = val;
1152 else
1153 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1154 size);
1155 break;
1156 default:
1157 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
1158 size);
1159 break;
1160 }
1161 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %08x\n", asi,
1162 size, addr, val);
1163 #ifdef DEBUG_MXCC
1164 dump_mxcc(env);
1165 #endif
1166 break;
1167 case 3: /* MMU flush */
1168 {
1169 int mmulev;
1170
1171 mmulev = (addr >> 8) & 15;
1172 DPRINTF_MMU("mmu flush level %d\n", mmulev);
1173 switch (mmulev) {
1174 case 0: // flush page
1175 tlb_flush_page(env, addr & 0xfffff000);
1176 break;
1177 case 1: // flush segment (256k)
1178 case 2: // flush region (16M)
1179 case 3: // flush context (4G)
1180 case 4: // flush entire
1181 tlb_flush(env, 1);
1182 break;
1183 default:
1184 break;
1185 }
1186 #ifdef DEBUG_MMU
1187 dump_mmu(env);
1188 #endif
1189 }
1190 break;
1191 case 4: /* write MMU regs */
1192 {
1193 int reg = (addr >> 8) & 0x1f;
1194 uint32_t oldreg;
1195
1196 oldreg = env->mmuregs[reg];
1197 switch(reg) {
1198 case 0: // Control Register
1199 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
1200 (val & 0x00ffffff);
1201 // Mappings generated during no-fault mode or MMU
1202 // disabled mode are invalid in normal mode
1203 if ((oldreg & (MMU_E | MMU_NF | env->mmu_bm)) !=
1204 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->mmu_bm)))
1205 tlb_flush(env, 1);
1206 break;
1207 case 1: // Context Table Pointer Register
1208 env->mmuregs[reg] = val & env->mmu_ctpr_mask;
1209 break;
1210 case 2: // Context Register
1211 env->mmuregs[reg] = val & env->mmu_cxr_mask;
1212 if (oldreg != env->mmuregs[reg]) {
1213 /* we flush when the MMU context changes because
1214 QEMU has no MMU context support */
1215 tlb_flush(env, 1);
1216 }
1217 break;
1218 case 3: // Synchronous Fault Status Register with Clear
1219 case 4: // Synchronous Fault Address Register
1220 break;
1221 case 0x10: // TLB Replacement Control Register
1222 env->mmuregs[reg] = val & env->mmu_trcr_mask;
1223 break;
1224 case 0x13: // Synchronous Fault Status Register with Read and Clear
1225 env->mmuregs[3] = val & env->mmu_sfsr_mask;
1226 break;
1227 case 0x14: // Synchronous Fault Address Register
1228 env->mmuregs[4] = val;
1229 break;
1230 default:
1231 env->mmuregs[reg] = val;
1232 break;
1233 }
1234 if (oldreg != env->mmuregs[reg]) {
1235 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
1236 reg, oldreg, env->mmuregs[reg]);
1237 }
1238 #ifdef DEBUG_MMU
1239 dump_mmu(env);
1240 #endif
1241 }
1242 break;
1243 case 5: // Turbosparc ITLB Diagnostic
1244 case 6: // Turbosparc DTLB Diagnostic
1245 case 7: // Turbosparc IOTLB Diagnostic
1246 break;
1247 case 0xa: /* User data access */
1248 switch(size) {
1249 case 1:
1250 stb_user(addr, val);
1251 break;
1252 case 2:
1253 stw_user(addr, val);
1254 break;
1255 default:
1256 case 4:
1257 stl_user(addr, val);
1258 break;
1259 case 8:
1260 stq_user(addr, val);
1261 break;
1262 }
1263 break;
1264 case 0xb: /* Supervisor data access */
1265 switch(size) {
1266 case 1:
1267 stb_kernel(addr, val);
1268 break;
1269 case 2:
1270 stw_kernel(addr, val);
1271 break;
1272 default:
1273 case 4:
1274 stl_kernel(addr, val);
1275 break;
1276 case 8:
1277 stq_kernel(addr, val);
1278 break;
1279 }
1280 break;
1281 case 0xc: /* I-cache tag */
1282 case 0xd: /* I-cache data */
1283 case 0xe: /* D-cache tag */
1284 case 0xf: /* D-cache data */
1285 case 0x10: /* I/D-cache flush page */
1286 case 0x11: /* I/D-cache flush segment */
1287 case 0x12: /* I/D-cache flush region */
1288 case 0x13: /* I/D-cache flush context */
1289 case 0x14: /* I/D-cache flush user */
1290 break;
1291 case 0x17: /* Block copy, sta access */
1292 {
1293 // val = src
1294 // addr = dst
1295 // copy 32 bytes
1296 unsigned int i;
1297 uint32_t src = val & ~3, dst = addr & ~3, temp;
1298
1299 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
1300 temp = ldl_kernel(src);
1301 stl_kernel(dst, temp);
1302 }
1303 }
1304 break;
1305 case 0x1f: /* Block fill, stda access */
1306 {
1307 // addr = dst
1308 // fill 32 bytes with val
1309 unsigned int i;
1310 uint32_t dst = addr & 7;
1311
1312 for (i = 0; i < 32; i += 8, dst += 8)
1313 stq_kernel(dst, val);
1314 }
1315 break;
1316 case 0x20: /* MMU passthrough */
1317 {
1318 switch(size) {
1319 case 1:
1320 stb_phys(addr, val);
1321 break;
1322 case 2:
1323 stw_phys(addr, val);
1324 break;
1325 case 4:
1326 default:
1327 stl_phys(addr, val);
1328 break;
1329 case 8:
1330 stq_phys(addr, val);
1331 break;
1332 }
1333 }
1334 break;
1335 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1336 {
1337 switch(size) {
1338 case 1:
1339 stb_phys((target_phys_addr_t)addr
1340 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1341 break;
1342 case 2:
1343 stw_phys((target_phys_addr_t)addr
1344 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1345 break;
1346 case 4:
1347 default:
1348 stl_phys((target_phys_addr_t)addr
1349 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1350 break;
1351 case 8:
1352 stq_phys((target_phys_addr_t)addr
1353 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1354 break;
1355 }
1356 }
1357 break;
1358 case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
1359 case 0x31: // store buffer data, Ross RT620 I-cache flush or
1360 // Turbosparc snoop RAM
1361 case 0x32: // store buffer control or Turbosparc page table
1362 // descriptor diagnostic
1363 case 0x36: /* I-cache flash clear */
1364 case 0x37: /* D-cache flash clear */
1365 case 0x38: /* breakpoint diagnostics */
1366 case 0x4c: /* breakpoint action */
1367 break;
1368 case 8: /* User code access, XXX */
1369 case 9: /* Supervisor code access, XXX */
1370 default:
1371 do_unassigned_access(addr, 1, 0, asi);
1372 break;
1373 }
1374 #ifdef DEBUG_ASI
1375 dump_asi("write", addr, asi, size, val);
1376 #endif
1377 }
1378
1379 #endif /* CONFIG_USER_ONLY */
1380 #else /* TARGET_SPARC64 */
1381
1382 #ifdef CONFIG_USER_ONLY
1383 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
1384 {
1385 uint64_t ret = 0;
1386 #if defined(DEBUG_ASI)
1387 target_ulong last_addr = addr;
1388 #endif
1389
1390 if (asi < 0x80)
1391 raise_exception(TT_PRIV_ACT);
1392
1393 helper_check_align(addr, size - 1);
1394 address_mask(env, &addr);
1395
1396 switch (asi) {
1397 case 0x80: // Primary
1398 case 0x82: // Primary no-fault
1399 case 0x88: // Primary LE
1400 case 0x8a: // Primary no-fault LE
1401 {
1402 switch(size) {
1403 case 1:
1404 ret = ldub_raw(addr);
1405 break;
1406 case 2:
1407 ret = lduw_raw(addr);
1408 break;
1409 case 4:
1410 ret = ldl_raw(addr);
1411 break;
1412 default:
1413 case 8:
1414 ret = ldq_raw(addr);
1415 break;
1416 }
1417 }
1418 break;
1419 case 0x81: // Secondary
1420 case 0x83: // Secondary no-fault
1421 case 0x89: // Secondary LE
1422 case 0x8b: // Secondary no-fault LE
1423 // XXX
1424 break;
1425 default:
1426 break;
1427 }
1428
1429 /* Convert from little endian */
1430 switch (asi) {
1431 case 0x88: // Primary LE
1432 case 0x89: // Secondary LE
1433 case 0x8a: // Primary no-fault LE
1434 case 0x8b: // Secondary no-fault LE
1435 switch(size) {
1436 case 2:
1437 ret = bswap16(ret);
1438 break;
1439 case 4:
1440 ret = bswap32(ret);
1441 break;
1442 case 8:
1443 ret = bswap64(ret);
1444 break;
1445 default:
1446 break;
1447 }
1448 default:
1449 break;
1450 }
1451
1452 /* Convert to signed number */
1453 if (sign) {
1454 switch(size) {
1455 case 1:
1456 ret = (int8_t) ret;
1457 break;
1458 case 2:
1459 ret = (int16_t) ret;
1460 break;
1461 case 4:
1462 ret = (int32_t) ret;
1463 break;
1464 default:
1465 break;
1466 }
1467 }
1468 #ifdef DEBUG_ASI
1469 dump_asi("read ", last_addr, asi, size, ret);
1470 #endif
1471 return ret;
1472 }
1473
1474 void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
1475 {
1476 #ifdef DEBUG_ASI
1477 dump_asi("write", addr, asi, size, val);
1478 #endif
1479 if (asi < 0x80)
1480 raise_exception(TT_PRIV_ACT);
1481
1482 helper_check_align(addr, size - 1);
1483 address_mask(env, &addr);
1484
1485 /* Convert to little endian */
1486 switch (asi) {
1487 case 0x88: // Primary LE
1488 case 0x89: // Secondary LE
1489 switch(size) {
1490 case 2:
1491 addr = bswap16(addr);
1492 break;
1493 case 4:
1494 addr = bswap32(addr);
1495 break;
1496 case 8:
1497 addr = bswap64(addr);
1498 break;
1499 default:
1500 break;
1501 }
1502 default:
1503 break;
1504 }
1505
1506 switch(asi) {
1507 case 0x80: // Primary
1508 case 0x88: // Primary LE
1509 {
1510 switch(size) {
1511 case 1:
1512 stb_raw(addr, val);
1513 break;
1514 case 2:
1515 stw_raw(addr, val);
1516 break;
1517 case 4:
1518 stl_raw(addr, val);
1519 break;
1520 case 8:
1521 default:
1522 stq_raw(addr, val);
1523 break;
1524 }
1525 }
1526 break;
1527 case 0x81: // Secondary
1528 case 0x89: // Secondary LE
1529 // XXX
1530 return;
1531
1532 case 0x82: // Primary no-fault, RO
1533 case 0x83: // Secondary no-fault, RO
1534 case 0x8a: // Primary no-fault LE, RO
1535 case 0x8b: // Secondary no-fault LE, RO
1536 default:
1537 do_unassigned_access(addr, 1, 0, 1);
1538 return;
1539 }
1540 }
1541
1542 #else /* CONFIG_USER_ONLY */
1543
1544 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
1545 {
1546 uint64_t ret = 0;
1547 #if defined(DEBUG_ASI)
1548 target_ulong last_addr = addr;
1549 #endif
1550
1551 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1552 || ((env->features & CPU_FEATURE_HYPV) && asi >= 0x30 && asi < 0x80
1553 && !(env->hpstate & HS_PRIV)))
1554 raise_exception(TT_PRIV_ACT);
1555
1556 helper_check_align(addr, size - 1);
1557 switch (asi) {
1558 case 0x10: // As if user primary
1559 case 0x18: // As if user primary LE
1560 case 0x80: // Primary
1561 case 0x82: // Primary no-fault
1562 case 0x88: // Primary LE
1563 case 0x8a: // Primary no-fault LE
1564 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1565 if ((env->features & CPU_FEATURE_HYPV) && env->hpstate & HS_PRIV) {
1566 switch(size) {
1567 case 1:
1568 ret = ldub_hypv(addr);
1569 break;
1570 case 2:
1571 ret = lduw_hypv(addr);
1572 break;
1573 case 4:
1574 ret = ldl_hypv(addr);
1575 break;
1576 default:
1577 case 8:
1578 ret = ldq_hypv(addr);
1579 break;
1580 }
1581 } else {
1582 switch(size) {
1583 case 1:
1584 ret = ldub_kernel(addr);
1585 break;
1586 case 2:
1587 ret = lduw_kernel(addr);
1588 break;
1589 case 4:
1590 ret = ldl_kernel(addr);
1591 break;
1592 default:
1593 case 8:
1594 ret = ldq_kernel(addr);
1595 break;
1596 }
1597 }
1598 } else {
1599 switch(size) {
1600 case 1:
1601 ret = ldub_user(addr);
1602 break;
1603 case 2:
1604 ret = lduw_user(addr);
1605 break;
1606 case 4:
1607 ret = ldl_user(addr);
1608 break;
1609 default:
1610 case 8:
1611 ret = ldq_user(addr);
1612 break;
1613 }
1614 }
1615 break;
1616 case 0x14: // Bypass
1617 case 0x15: // Bypass, non-cacheable
1618 case 0x1c: // Bypass LE
1619 case 0x1d: // Bypass, non-cacheable LE
1620 {
1621 switch(size) {
1622 case 1:
1623 ret = ldub_phys(addr);
1624 break;
1625 case 2:
1626 ret = lduw_phys(addr);
1627 break;
1628 case 4:
1629 ret = ldl_phys(addr);
1630 break;
1631 default:
1632 case 8:
1633 ret = ldq_phys(addr);
1634 break;
1635 }
1636 break;
1637 }
1638 case 0x24: // Nucleus quad LDD 128 bit atomic
1639 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
1640 // Only ldda allowed
1641 raise_exception(TT_ILL_INSN);
1642 return 0;
1643 case 0x04: // Nucleus
1644 case 0x0c: // Nucleus Little Endian (LE)
1645 case 0x11: // As if user secondary
1646 case 0x19: // As if user secondary LE
1647 case 0x4a: // UPA config
1648 case 0x81: // Secondary
1649 case 0x83: // Secondary no-fault
1650 case 0x89: // Secondary LE
1651 case 0x8b: // Secondary no-fault LE
1652 // XXX
1653 break;
1654 case 0x45: // LSU
1655 ret = env->lsu;
1656 break;
1657 case 0x50: // I-MMU regs
1658 {
1659 int reg = (addr >> 3) & 0xf;
1660
1661 ret = env->immuregs[reg];
1662 break;
1663 }
1664 case 0x51: // I-MMU 8k TSB pointer
1665 case 0x52: // I-MMU 64k TSB pointer
1666 // XXX
1667 break;
1668 case 0x55: // I-MMU data access
1669 {
1670 int reg = (addr >> 3) & 0x3f;
1671
1672 ret = env->itlb_tte[reg];
1673 break;
1674 }
1675 case 0x56: // I-MMU tag read
1676 {
1677 unsigned int i;
1678
1679 for (i = 0; i < 64; i++) {
1680 // Valid, ctx match, vaddr match
1681 if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
1682 uint64_t mask;
1683
1684 switch ((env->itlb_tte[i] >> 61) & 3) {
1685 default:
1686 case 0x0:
1687 mask = 0xffffffffffffffff;
1688 break;
1689 case 0x1:
1690 mask = 0xffffffffffff0fff;
1691 break;
1692 case 0x2:
1693 mask = 0xfffffffffff80fff;
1694 break;
1695 case 0x3:
1696 mask = 0xffffffffffc00fff;
1697 break;
1698 }
1699 if ((env->itlb_tag[i] & mask) == (addr & mask)) {
1700 ret = env->itlb_tte[i];
1701 break;
1702 }
1703 }
1704 }
1705 break;
1706 }
1707 case 0x58: // D-MMU regs
1708 {
1709 int reg = (addr >> 3) & 0xf;
1710
1711 ret = env->dmmuregs[reg];
1712 break;
1713 }
1714 case 0x5d: // D-MMU data access
1715 {
1716 int reg = (addr >> 3) & 0x3f;
1717
1718 ret = env->dtlb_tte[reg];
1719 break;
1720 }
1721 case 0x5e: // D-MMU tag read
1722 {
1723 unsigned int i;
1724
1725 for (i = 0; i < 64; i++) {
1726 // Valid, ctx match, vaddr match
1727 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
1728 uint64_t mask;
1729
1730 switch ((env->dtlb_tte[i] >> 61) & 3) {
1731 default:
1732 case 0x0:
1733 mask = 0xffffffffffffffff;
1734 break;
1735 case 0x1:
1736 mask = 0xffffffffffff0fff;
1737 break;
1738 case 0x2:
1739 mask = 0xfffffffffff80fff;
1740 break;
1741 case 0x3:
1742 mask = 0xffffffffffc00fff;
1743 break;
1744 }
1745 if ((env->dtlb_tag[i] & mask) == (addr & mask)) {
1746 ret = env->dtlb_tte[i];
1747 break;
1748 }
1749 }
1750 }
1751 break;
1752 }
1753 case 0x46: // D-cache data
1754 case 0x47: // D-cache tag access
1755 case 0x4b: // E-cache error enable
1756 case 0x4c: // E-cache asynchronous fault status
1757 case 0x4d: // E-cache asynchronous fault address
1758 case 0x4e: // E-cache tag data
1759 case 0x66: // I-cache instruction access
1760 case 0x67: // I-cache tag access
1761 case 0x6e: // I-cache predecode
1762 case 0x6f: // I-cache LRU etc.
1763 case 0x76: // E-cache tag
1764 case 0x7e: // E-cache tag
1765 break;
1766 case 0x59: // D-MMU 8k TSB pointer
1767 case 0x5a: // D-MMU 64k TSB pointer
1768 case 0x5b: // D-MMU data pointer
1769 case 0x48: // Interrupt dispatch, RO
1770 case 0x49: // Interrupt data receive
1771 case 0x7f: // Incoming interrupt vector, RO
1772 // XXX
1773 break;
1774 case 0x54: // I-MMU data in, WO
1775 case 0x57: // I-MMU demap, WO
1776 case 0x5c: // D-MMU data in, WO
1777 case 0x5f: // D-MMU demap, WO
1778 case 0x77: // Interrupt vector, WO
1779 default:
1780 do_unassigned_access(addr, 0, 0, 1);
1781 ret = 0;
1782 break;
1783 }
1784
1785 /* Convert from little endian */
1786 switch (asi) {
1787 case 0x0c: // Nucleus Little Endian (LE)
1788 case 0x18: // As if user primary LE
1789 case 0x19: // As if user secondary LE
1790 case 0x1c: // Bypass LE
1791 case 0x1d: // Bypass, non-cacheable LE
1792 case 0x88: // Primary LE
1793 case 0x89: // Secondary LE
1794 case 0x8a: // Primary no-fault LE
1795 case 0x8b: // Secondary no-fault LE
1796 switch(size) {
1797 case 2:
1798 ret = bswap16(ret);
1799 break;
1800 case 4:
1801 ret = bswap32(ret);
1802 break;
1803 case 8:
1804 ret = bswap64(ret);
1805 break;
1806 default:
1807 break;
1808 }
1809 default:
1810 break;
1811 }
1812
1813 /* Convert to signed number */
1814 if (sign) {
1815 switch(size) {
1816 case 1:
1817 ret = (int8_t) ret;
1818 break;
1819 case 2:
1820 ret = (int16_t) ret;
1821 break;
1822 case 4:
1823 ret = (int32_t) ret;
1824 break;
1825 default:
1826 break;
1827 }
1828 }
1829 #ifdef DEBUG_ASI
1830 dump_asi("read ", last_addr, asi, size, ret);
1831 #endif
1832 return ret;
1833 }
1834
1835 void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
1836 {
1837 #ifdef DEBUG_ASI
1838 dump_asi("write", addr, asi, size, val);
1839 #endif
1840 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1841 || ((env->features & CPU_FEATURE_HYPV) && asi >= 0x30 && asi < 0x80
1842 && !(env->hpstate & HS_PRIV)))
1843 raise_exception(TT_PRIV_ACT);
1844
1845 helper_check_align(addr, size - 1);
1846 /* Convert to little endian */
1847 switch (asi) {
1848 case 0x0c: // Nucleus Little Endian (LE)
1849 case 0x18: // As if user primary LE
1850 case 0x19: // As if user secondary LE
1851 case 0x1c: // Bypass LE
1852 case 0x1d: // Bypass, non-cacheable LE
1853 case 0x88: // Primary LE
1854 case 0x89: // Secondary LE
1855 switch(size) {
1856 case 2:
1857 addr = bswap16(addr);
1858 break;
1859 case 4:
1860 addr = bswap32(addr);
1861 break;
1862 case 8:
1863 addr = bswap64(addr);
1864 break;
1865 default:
1866 break;
1867 }
1868 default:
1869 break;
1870 }
1871
1872 switch(asi) {
1873 case 0x10: // As if user primary
1874 case 0x18: // As if user primary LE
1875 case 0x80: // Primary
1876 case 0x88: // Primary LE
1877 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1878 if ((env->features & CPU_FEATURE_HYPV) && env->hpstate & HS_PRIV) {
1879 switch(size) {
1880 case 1:
1881 stb_hypv(addr, val);
1882 break;
1883 case 2:
1884 stw_hypv(addr, val);
1885 break;
1886 case 4:
1887 stl_hypv(addr, val);
1888 break;
1889 case 8:
1890 default:
1891 stq_hypv(addr, val);
1892 break;
1893 }
1894 } else {
1895 switch(size) {
1896 case 1:
1897 stb_kernel(addr, val);
1898 break;
1899 case 2:
1900 stw_kernel(addr, val);
1901 break;
1902 case 4:
1903 stl_kernel(addr, val);
1904 break;
1905 case 8:
1906 default:
1907 stq_kernel(addr, val);
1908 break;
1909 }
1910 }
1911 } else {
1912 switch(size) {
1913 case 1:
1914 stb_user(addr, val);
1915 break;
1916 case 2:
1917 stw_user(addr, val);
1918 break;
1919 case 4:
1920 stl_user(addr, val);
1921 break;
1922 case 8:
1923 default:
1924 stq_user(addr, val);
1925 break;
1926 }
1927 }
1928 break;
1929 case 0x14: // Bypass
1930 case 0x15: // Bypass, non-cacheable
1931 case 0x1c: // Bypass LE
1932 case 0x1d: // Bypass, non-cacheable LE
1933 {
1934 switch(size) {
1935 case 1:
1936 stb_phys(addr, val);
1937 break;
1938 case 2:
1939 stw_phys(addr, val);
1940 break;
1941 case 4:
1942 stl_phys(addr, val);
1943 break;
1944 case 8:
1945 default:
1946 stq_phys(addr, val);
1947 break;
1948 }
1949 }
1950 return;
1951 case 0x24: // Nucleus quad LDD 128 bit atomic
1952 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
1953 // Only ldda allowed
1954 raise_exception(TT_ILL_INSN);
1955 return;
1956 case 0x04: // Nucleus
1957 case 0x0c: // Nucleus Little Endian (LE)
1958 case 0x11: // As if user secondary
1959 case 0x19: // As if user secondary LE
1960 case 0x4a: // UPA config
1961 case 0x81: // Secondary
1962 case 0x89: // Secondary LE
1963 // XXX
1964 return;
1965 case 0x45: // LSU
1966 {
1967 uint64_t oldreg;
1968
1969 oldreg = env->lsu;
1970 env->lsu = val & (DMMU_E | IMMU_E);
1971 // Mappings generated during D/I MMU disabled mode are
1972 // invalid in normal mode
1973 if (oldreg != env->lsu) {
1974 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
1975 oldreg, env->lsu);
1976 #ifdef DEBUG_MMU
1977 dump_mmu(env);
1978 #endif
1979 tlb_flush(env, 1);
1980 }
1981 return;
1982 }
1983 case 0x50: // I-MMU regs
1984 {
1985 int reg = (addr >> 3) & 0xf;
1986 uint64_t oldreg;
1987
1988 oldreg = env->immuregs[reg];
1989 switch(reg) {
1990 case 0: // RO
1991 case 4:
1992 return;
1993 case 1: // Not in I-MMU
1994 case 2:
1995 case 7:
1996 case 8:
1997 return;
1998 case 3: // SFSR
1999 if ((val & 1) == 0)
2000 val = 0; // Clear SFSR
2001 break;
2002 case 5: // TSB access
2003 case 6: // Tag access
2004 default:
2005 break;
2006 }
2007 env->immuregs[reg] = val;
2008 if (oldreg != env->immuregs[reg]) {
2009 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08"
2010 PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
2011 }
2012 #ifdef DEBUG_MMU
2013 dump_mmu(env);
2014 #endif
2015 return;
2016 }
2017 case 0x54: // I-MMU data in
2018 {
2019 unsigned int i;
2020
2021 // Try finding an invalid entry
2022 for (i = 0; i < 64; i++) {
2023 if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
2024 env->itlb_tag[i] = env->immuregs[6];
2025 env->itlb_tte[i] = val;
2026 return;
2027 }
2028 }
2029 // Try finding an unlocked entry
2030 for (i = 0; i < 64; i++) {
2031 if ((env->itlb_tte[i] & 0x40) == 0) {
2032 env->itlb_tag[i] = env->immuregs[6];
2033 env->itlb_tte[i] = val;
2034 return;
2035 }
2036 }
2037 // error state?
2038 return;
2039 }
2040 case 0x55: // I-MMU data access
2041 {
2042 unsigned int i = (addr >> 3) & 0x3f;
2043
2044 env->itlb_tag[i] = env->immuregs[6];
2045 env->itlb_tte[i] = val;
2046 return;
2047 }
2048 case 0x57: // I-MMU demap
2049 // XXX
2050 return;
2051 case 0x58: // D-MMU regs
2052 {
2053 int reg = (addr >> 3) & 0xf;
2054 uint64_t oldreg;
2055
2056 oldreg = env->dmmuregs[reg];
2057 switch(reg) {
2058 case 0: // RO
2059 case 4:
2060 return;
2061 case 3: // SFSR
2062 if ((val & 1) == 0) {
2063 val = 0; // Clear SFSR, Fault address
2064 env->dmmuregs[4] = 0;
2065 }
2066 env->dmmuregs[reg] = val;
2067 break;
2068 case 1: // Primary context
2069 case 2: // Secondary context
2070 case 5: // TSB access
2071 case 6: // Tag access
2072 case 7: // Virtual Watchpoint
2073 case 8: // Physical Watchpoint
2074 default:
2075 break;
2076 }
2077 env->dmmuregs[reg] = val;
2078 if (oldreg != env->dmmuregs[reg]) {
2079 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08"
2080 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
2081 }
2082 #ifdef DEBUG_MMU
2083 dump_mmu(env);
2084 #endif
2085 return;
2086 }
2087 case 0x5c: // D-MMU data in
2088 {
2089 unsigned int i;
2090
2091 // Try finding an invalid entry
2092 for (i = 0; i < 64; i++) {
2093 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
2094 env->dtlb_tag[i] = env->dmmuregs[6];
2095 env->dtlb_tte[i] = val;
2096 return;
2097 }
2098 }
2099 // Try finding an unlocked entry
2100 for (i = 0; i < 64; i++) {
2101 if ((env->dtlb_tte[i] & 0x40) == 0) {
2102 env->dtlb_tag[i] = env->dmmuregs[6];
2103 env->dtlb_tte[i] = val;
2104 return;
2105 }
2106 }
2107 // error state?
2108 return;
2109 }
2110 case 0x5d: // D-MMU data access
2111 {
2112 unsigned int i = (addr >> 3) & 0x3f;
2113
2114 env->dtlb_tag[i] = env->dmmuregs[6];
2115 env->dtlb_tte[i] = val;
2116 return;
2117 }
2118 case 0x5f: // D-MMU demap
2119 case 0x49: // Interrupt data receive
2120 // XXX
2121 return;
2122 case 0x46: // D-cache data
2123 case 0x47: // D-cache tag access
2124 case 0x4b: // E-cache error enable
2125 case 0x4c: // E-cache asynchronous fault status
2126 case 0x4d: // E-cache asynchronous fault address
2127 case 0x4e: // E-cache tag data
2128 case 0x66: // I-cache instruction access
2129 case 0x67: // I-cache tag access
2130 case 0x6e: // I-cache predecode
2131 case 0x6f: // I-cache LRU etc.
2132 case 0x76: // E-cache tag
2133 case 0x7e: // E-cache tag
2134 return;
2135 case 0x51: // I-MMU 8k TSB pointer, RO
2136 case 0x52: // I-MMU 64k TSB pointer, RO
2137 case 0x56: // I-MMU tag read, RO
2138 case 0x59: // D-MMU 8k TSB pointer, RO
2139 case 0x5a: // D-MMU 64k TSB pointer, RO
2140 case 0x5b: // D-MMU data pointer, RO
2141 case 0x5e: // D-MMU tag read, RO
2142 case 0x48: // Interrupt dispatch, RO
2143 case 0x7f: // Incoming interrupt vector, RO
2144 case 0x82: // Primary no-fault, RO
2145 case 0x83: // Secondary no-fault, RO
2146 case 0x8a: // Primary no-fault LE, RO
2147 case 0x8b: // Secondary no-fault LE, RO
2148 default:
2149 do_unassigned_access(addr, 1, 0, 1);
2150 return;
2151 }
2152 }
2153 #endif /* CONFIG_USER_ONLY */
2154
2155 void helper_ldda_asi(target_ulong addr, int asi, int rd)
2156 {
2157 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2158 || ((env->features & CPU_FEATURE_HYPV) && asi >= 0x30 && asi < 0x80
2159 && !(env->hpstate & HS_PRIV)))
2160 raise_exception(TT_PRIV_ACT);
2161
2162 switch (asi) {
2163 case 0x24: // Nucleus quad LDD 128 bit atomic
2164 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2165 helper_check_align(addr, 0xf);
2166 if (rd == 0) {
2167 env->gregs[1] = ldq_kernel(addr + 8);
2168 if (asi == 0x2c)
2169 bswap64s(&env->gregs[1]);
2170 } else if (rd < 8) {
2171 env->gregs[rd] = ldq_kernel(addr);
2172 env->gregs[rd + 1] = ldq_kernel(addr + 8);
2173 if (asi == 0x2c) {
2174 bswap64s(&env->gregs[rd]);
2175 bswap64s(&env->gregs[rd + 1]);
2176 }
2177 } else {
2178 env->regwptr[rd] = ldq_kernel(addr);
2179 env->regwptr[rd + 1] = ldq_kernel(addr + 8);
2180 if (asi == 0x2c) {
2181 bswap64s(&env->regwptr[rd]);
2182 bswap64s(&env->regwptr[rd + 1]);
2183 }
2184 }
2185 break;
2186 default:
2187 helper_check_align(addr, 0x3);
2188 if (rd == 0)
2189 env->gregs[1] = helper_ld_asi(addr + 4, asi, 4, 0);
2190 else if (rd < 8) {
2191 env->gregs[rd] = helper_ld_asi(addr, asi, 4, 0);
2192 env->gregs[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
2193 } else {
2194 env->regwptr[rd] = helper_ld_asi(addr, asi, 4, 0);
2195 env->regwptr[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
2196 }
2197 break;
2198 }
2199 }
2200
2201 void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
2202 {
2203 unsigned int i;
2204 target_ulong val;
2205
2206 helper_check_align(addr, 3);
2207 switch (asi) {
2208 case 0xf0: // Block load primary
2209 case 0xf1: // Block load secondary
2210 case 0xf8: // Block load primary LE
2211 case 0xf9: // Block load secondary LE
2212 if (rd & 7) {
2213 raise_exception(TT_ILL_INSN);
2214 return;
2215 }
2216 helper_check_align(addr, 0x3f);
2217 for (i = 0; i < 16; i++) {
2218 *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4,
2219 0);
2220 addr += 4;
2221 }
2222
2223 return;
2224 default:
2225 break;
2226 }
2227
2228 val = helper_ld_asi(addr, asi, size, 0);
2229 switch(size) {
2230 default:
2231 case 4:
2232 *((uint32_t *)&FT0) = val;
2233 break;
2234 case 8:
2235 *((int64_t *)&DT0) = val;
2236 break;
2237 case 16:
2238 // XXX
2239 break;
2240 }
2241 }
2242
2243 void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
2244 {
2245 unsigned int i;
2246 target_ulong val = 0;
2247
2248 helper_check_align(addr, 3);
2249 switch (asi) {
2250 case 0xf0: // Block store primary
2251 case 0xf1: // Block store secondary
2252 case 0xf8: // Block store primary LE
2253 case 0xf9: // Block store secondary LE
2254 if (rd & 7) {
2255 raise_exception(TT_ILL_INSN);
2256 return;
2257 }
2258 helper_check_align(addr, 0x3f);
2259 for (i = 0; i < 16; i++) {
2260 val = *(uint32_t *)&env->fpr[rd++];
2261 helper_st_asi(addr, val, asi & 0x8f, 4);
2262 addr += 4;
2263 }
2264
2265 return;
2266 default:
2267 break;
2268 }
2269
2270 switch(size) {
2271 default:
2272 case 4:
2273 val = *((uint32_t *)&FT0);
2274 break;
2275 case 8:
2276 val = *((int64_t *)&DT0);
2277 break;
2278 case 16:
2279 // XXX
2280 break;
2281 }
2282 helper_st_asi(addr, val, asi, size);
2283 }
2284
2285 target_ulong helper_cas_asi(target_ulong addr, target_ulong val1,
2286 target_ulong val2, uint32_t asi)
2287 {
2288 target_ulong ret;
2289
2290 val1 &= 0xffffffffUL;
2291 ret = helper_ld_asi(addr, asi, 4, 0);
2292 ret &= 0xffffffffUL;
2293 if (val1 == ret)
2294 helper_st_asi(addr, val2 & 0xffffffffUL, asi, 4);
2295 return ret;
2296 }
2297
2298 target_ulong helper_casx_asi(target_ulong addr, target_ulong val1,
2299 target_ulong val2, uint32_t asi)
2300 {
2301 target_ulong ret;
2302
2303 ret = helper_ld_asi(addr, asi, 8, 0);
2304 if (val1 == ret)
2305 helper_st_asi(addr, val2, asi, 8);
2306 return ret;
2307 }
2308 #endif /* TARGET_SPARC64 */
2309
2310 #ifndef TARGET_SPARC64
2311 void helper_rett(void)
2312 {
2313 unsigned int cwp;
2314
2315 if (env->psret == 1)
2316 raise_exception(TT_ILL_INSN);
2317
2318 env->psret = 1;
2319 cwp = cpu_cwp_inc(env, env->cwp + 1) ;
2320 if (env->wim & (1 << cwp)) {
2321 raise_exception(TT_WIN_UNF);
2322 }
2323 set_cwp(cwp);
2324 env->psrs = env->psrps;
2325 }
2326 #endif
2327
2328 target_ulong helper_udiv(target_ulong a, target_ulong b)
2329 {
2330 uint64_t x0;
2331 uint32_t x1;
2332
2333 x0 = a | ((uint64_t) (env->y) << 32);
2334 x1 = b;
2335
2336 if (x1 == 0) {
2337 raise_exception(TT_DIV_ZERO);
2338 }
2339
2340 x0 = x0 / x1;
2341 if (x0 > 0xffffffff) {
2342 env->cc_src2 = 1;
2343 return 0xffffffff;
2344 } else {
2345 env->cc_src2 = 0;
2346 return x0;
2347 }
2348 }
2349
2350 target_ulong helper_sdiv(target_ulong a, target_ulong b)
2351 {
2352 int64_t x0;
2353 int32_t x1;
2354
2355 x0 = a | ((int64_t) (env->y) << 32);
2356 x1 = b;
2357
2358 if (x1 == 0) {
2359 raise_exception(TT_DIV_ZERO);
2360 }
2361
2362 x0 = x0 / x1;
2363 if ((int32_t) x0 != x0) {
2364 env->cc_src2 = 1;
2365 return x0 < 0? 0x80000000: 0x7fffffff;
2366 } else {
2367 env->cc_src2 = 0;
2368 return x0;
2369 }
2370 }
2371
2372 uint64_t helper_pack64(target_ulong high, target_ulong low)
2373 {
2374 return ((uint64_t)high << 32) | (uint64_t)(low & 0xffffffff);
2375 }
2376
2377 void helper_stdf(target_ulong addr, int mem_idx)
2378 {
2379 helper_check_align(addr, 7);
2380 #if !defined(CONFIG_USER_ONLY)
2381 switch (mem_idx) {
2382 case 0:
2383 stfq_user(addr, DT0);
2384 break;
2385 case 1:
2386 stfq_kernel(addr, DT0);
2387 break;
2388 #ifdef TARGET_SPARC64
2389 case 2:
2390 stfq_hypv(addr, DT0);
2391 break;
2392 #endif
2393 default:
2394 break;
2395 }
2396 #else
2397 address_mask(env, &addr);
2398 stfq_raw(addr, DT0);
2399 #endif
2400 }
2401
2402 void helper_lddf(target_ulong addr, int mem_idx)
2403 {
2404 helper_check_align(addr, 7);
2405 #if !defined(CONFIG_USER_ONLY)
2406 switch (mem_idx) {
2407 case 0:
2408 DT0 = ldfq_user(addr);
2409 break;
2410 case 1:
2411 DT0 = ldfq_kernel(addr);
2412 break;
2413 #ifdef TARGET_SPARC64
2414 case 2:
2415 DT0 = ldfq_hypv(addr);
2416 break;
2417 #endif
2418 default:
2419 break;
2420 }
2421 #else
2422 address_mask(env, &addr);
2423 DT0 = ldfq_raw(addr);
2424 #endif
2425 }
2426
2427 void helper_ldqf(target_ulong addr, int mem_idx)
2428 {
2429 // XXX add 128 bit load
2430 CPU_QuadU u;
2431
2432 helper_check_align(addr, 7);
2433 #if !defined(CONFIG_USER_ONLY)
2434 switch (mem_idx) {
2435 case 0:
2436 u.ll.upper = ldq_user(addr);
2437 u.ll.lower = ldq_user(addr + 8);
2438 QT0 = u.q;
2439 break;
2440 case 1:
2441 u.ll.upper = ldq_kernel(addr);
2442 u.ll.lower = ldq_kernel(addr + 8);
2443 QT0 = u.q;
2444 break;
2445 #ifdef TARGET_SPARC64
2446 case 2:
2447 u.ll.upper = ldq_hypv(addr);
2448 u.ll.lower = ldq_hypv(addr + 8);
2449 QT0 = u.q;
2450 break;
2451 #endif
2452 default:
2453 break;
2454 }
2455 #else
2456 address_mask(env, &addr);
2457 u.ll.upper = ldq_raw(addr);
2458 u.ll.lower = ldq_raw((addr + 8) & 0xffffffffULL);
2459 QT0 = u.q;
2460 #endif
2461 }
2462
2463 void helper_stqf(target_ulong addr, int mem_idx)
2464 {
2465 // XXX add 128 bit store
2466 CPU_QuadU u;
2467
2468 helper_check_align(addr, 7);
2469 #if !defined(CONFIG_USER_ONLY)
2470 switch (mem_idx) {
2471 case 0:
2472 u.q = QT0;
2473 stq_user(addr, u.ll.upper);
2474 stq_user(addr + 8, u.ll.lower);
2475 break;
2476 case 1:
2477 u.q = QT0;
2478 stq_kernel(addr, u.ll.upper);
2479 stq_kernel(addr + 8, u.ll.lower);
2480 break;
2481 #ifdef TARGET_SPARC64
2482 case 2:
2483 u.q = QT0;
2484 stq_hypv(addr, u.ll.upper);
2485 stq_hypv(addr + 8, u.ll.lower);
2486 break;
2487 #endif
2488 default:
2489 break;
2490 }
2491 #else
2492 u.q = QT0;
2493 address_mask(env, &addr);
2494 stq_raw(addr, u.ll.upper);
2495 stq_raw((addr + 8) & 0xffffffffULL, u.ll.lower);
2496 #endif
2497 }
2498
2499 void helper_ldfsr(void)
2500 {
2501 int rnd_mode;
2502
2503 PUT_FSR32(env, *((uint32_t *) &FT0));
2504 switch (env->fsr & FSR_RD_MASK) {
2505 case FSR_RD_NEAREST:
2506 rnd_mode = float_round_nearest_even;
2507 break;
2508 default:
2509 case FSR_RD_ZERO:
2510 rnd_mode = float_round_to_zero;
2511 break;
2512 case FSR_RD_POS:
2513 rnd_mode = float_round_up;
2514 break;
2515 case FSR_RD_NEG:
2516 rnd_mode = float_round_down;
2517 break;
2518 }
2519 set_float_rounding_mode(rnd_mode, &env->fp_status);
2520 }
2521
2522 void helper_stfsr(void)
2523 {
2524 *((uint32_t *) &FT0) = GET_FSR32(env);
2525 }
2526
2527 void helper_debug(void)
2528 {
2529 env->exception_index = EXCP_DEBUG;
2530 cpu_loop_exit();
2531 }
2532
2533 #ifndef TARGET_SPARC64
2534 /* XXX: use another pointer for %iN registers to avoid slow wrapping
2535 handling ? */
2536 void helper_save(void)
2537 {
2538 uint32_t cwp;
2539
2540 cwp = cpu_cwp_dec(env, env->cwp - 1);
2541 if (env->wim & (1 << cwp)) {
2542 raise_exception(TT_WIN_OVF);
2543 }
2544 set_cwp(cwp);
2545 }
2546
2547 void helper_restore(void)
2548 {
2549 uint32_t cwp;
2550
2551 cwp = cpu_cwp_inc(env, env->cwp + 1);
2552 if (env->wim & (1 << cwp)) {
2553 raise_exception(TT_WIN_UNF);
2554 }
2555 set_cwp(cwp);
2556 }
2557
2558 void helper_wrpsr(target_ulong new_psr)
2559 {
2560 if ((new_psr & PSR_CWP) >= env->nwindows)
2561 raise_exception(TT_ILL_INSN);
2562 else
2563 PUT_PSR(env, new_psr);
2564 }
2565
2566 target_ulong helper_rdpsr(void)
2567 {
2568 return GET_PSR(env);
2569 }
2570
2571 #else
2572 /* XXX: use another pointer for %iN registers to avoid slow wrapping
2573 handling ? */
2574 void helper_save(void)
2575 {
2576 uint32_t cwp;
2577
2578 cwp = cpu_cwp_dec(env, env->cwp - 1);
2579 if (env->cansave == 0) {
2580 raise_exception(TT_SPILL | (env->otherwin != 0 ?
2581 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
2582 ((env->wstate & 0x7) << 2)));
2583 } else {
2584 if (env->cleanwin - env->canrestore == 0) {
2585 // XXX Clean windows without trap
2586 raise_exception(TT_CLRWIN);
2587 } else {
2588 env->cansave--;
2589 env->canrestore++;
2590 set_cwp(cwp);
2591 }
2592 }
2593 }
2594
2595 void helper_restore(void)
2596 {
2597 uint32_t cwp;
2598
2599 cwp = cpu_cwp_inc(env, env->cwp + 1);
2600 if (env->canrestore == 0) {
2601 raise_exception(TT_FILL | (env->otherwin != 0 ?
2602 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
2603 ((env->wstate & 0x7) << 2)));
2604 } else {
2605 env->cansave++;
2606 env->canrestore--;
2607 set_cwp(cwp);
2608 }
2609 }
2610
2611 void helper_flushw(void)
2612 {
2613 if (env->cansave != env->nwindows - 2) {
2614 raise_exception(TT_SPILL | (env->otherwin != 0 ?
2615 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
2616 ((env->wstate & 0x7) << 2)));
2617 }
2618 }
2619
2620 void helper_saved(void)
2621 {
2622 env->cansave++;
2623 if (env->otherwin == 0)
2624 env->canrestore--;
2625 else
2626 env->otherwin--;
2627 }
2628
2629 void helper_restored(void)
2630 {
2631 env->canrestore++;
2632 if (env->cleanwin < env->nwindows - 1)
2633 env->cleanwin++;
2634 if (env->otherwin == 0)
2635 env->cansave--;
2636 else
2637 env->otherwin--;
2638 }
2639
2640 target_ulong helper_rdccr(void)
2641 {
2642 return GET_CCR(env);
2643 }
2644
2645 void helper_wrccr(target_ulong new_ccr)
2646 {
2647 PUT_CCR(env, new_ccr);
2648 }
2649
2650 // CWP handling is reversed in V9, but we still use the V8 register
2651 // order.
2652 target_ulong helper_rdcwp(void)
2653 {
2654 return GET_CWP64(env);
2655 }
2656
2657 void helper_wrcwp(target_ulong new_cwp)
2658 {
2659 PUT_CWP64(env, new_cwp);
2660 }
2661
2662 // This function uses non-native bit order
2663 #define GET_FIELD(X, FROM, TO) \
2664 ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
2665
2666 // This function uses the order in the manuals, i.e. bit 0 is 2^0
2667 #define GET_FIELD_SP(X, FROM, TO) \
2668 GET_FIELD(X, 63 - (TO), 63 - (FROM))
2669
2670 target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize)
2671 {
2672 return (GET_FIELD_SP(pixel_addr, 60, 63) << (17 + 2 * cubesize)) |
2673 (GET_FIELD_SP(pixel_addr, 39, 39 + cubesize - 1) << (17 + cubesize)) |
2674 (GET_FIELD_SP(pixel_addr, 17 + cubesize - 1, 17) << 17) |
2675 (GET_FIELD_SP(pixel_addr, 56, 59) << 13) |
2676 (GET_FIELD_SP(pixel_addr, 35, 38) << 9) |
2677 (GET_FIELD_SP(pixel_addr, 13, 16) << 5) |
2678 (((pixel_addr >> 55) & 1) << 4) |
2679 (GET_FIELD_SP(pixel_addr, 33, 34) << 2) |
2680 GET_FIELD_SP(pixel_addr, 11, 12);
2681 }
2682
2683 target_ulong helper_alignaddr(target_ulong addr, target_ulong offset)
2684 {
2685 uint64_t tmp;
2686
2687 tmp = addr + offset;
2688 env->gsr &= ~7ULL;
2689 env->gsr |= tmp & 7ULL;
2690 return tmp & ~7ULL;
2691 }
2692
2693 target_ulong helper_popc(target_ulong val)
2694 {
2695 return ctpop64(val);
2696 }
2697
2698 static inline uint64_t *get_gregset(uint64_t pstate)
2699 {
2700 switch (pstate) {
2701 default:
2702 case 0:
2703 return env->bgregs;
2704 case PS_AG:
2705 return env->agregs;
2706 case PS_MG:
2707 return env->mgregs;
2708 case PS_IG:
2709 return env->igregs;
2710 }
2711 }
2712
2713 void change_pstate(uint64_t new_pstate)
2714 {
2715 uint64_t pstate_regs, new_pstate_regs;
2716 uint64_t *src, *dst;
2717
2718 pstate_regs = env->pstate & 0xc01;
2719 new_pstate_regs = new_pstate & 0xc01;
2720 if (new_pstate_regs != pstate_regs) {
2721 // Switch global register bank
2722 src = get_gregset(new_pstate_regs);
2723 dst = get_gregset(pstate_regs);
2724 memcpy32(dst, env->gregs);
2725 memcpy32(env->gregs, src);
2726 }
2727 env->pstate = new_pstate;
2728 }
2729
2730 void helper_wrpstate(target_ulong new_state)
2731 {
2732 if (!(env->features & CPU_FEATURE_GL))
2733 change_pstate(new_state & 0xf3f);
2734 }
2735
2736 void helper_done(void)
2737 {
2738 env->pc = env->tsptr->tpc;
2739 env->npc = env->tsptr->tnpc + 4;
2740 PUT_CCR(env, env->tsptr->tstate >> 32);
2741 env->asi = (env->tsptr->tstate >> 24) & 0xff;
2742 change_pstate((env->tsptr->tstate >> 8) & 0xf3f);
2743 PUT_CWP64(env, env->tsptr->tstate & 0xff);
2744 env->tl--;
2745 env->tsptr = &env->ts[env->tl];
2746 }
2747
2748 void helper_retry(void)
2749 {
2750 env->pc = env->tsptr->tpc;
2751 env->npc = env->tsptr->tnpc;
2752 PUT_CCR(env, env->tsptr->tstate >> 32);
2753 env->asi = (env->tsptr->tstate >> 24) & 0xff;
2754 change_pstate((env->tsptr->tstate >> 8) & 0xf3f);
2755 PUT_CWP64(env, env->tsptr->tstate & 0xff);
2756 env->tl--;
2757 env->tsptr = &env->ts[env->tl];
2758 }
2759 #endif
2760
2761 void cpu_set_cwp(CPUState *env1, int new_cwp)
2762 {
2763 /* put the modified wrap registers at their proper location */
2764 if (env1->cwp == env1->nwindows - 1)
2765 memcpy32(env1->regbase, env1->regbase + env1->nwindows * 16);
2766 env1->cwp = new_cwp;
2767 /* put the wrap registers at their temporary location */
2768 if (new_cwp == env1->nwindows - 1)
2769 memcpy32(env1->regbase + env1->nwindows * 16, env1->regbase);
2770 env1->regwptr = env1->regbase + (new_cwp * 16);
2771 }
2772
2773 void set_cwp(int new_cwp)
2774 {
2775 cpu_set_cwp(env, new_cwp);
2776 }
2777
2778 void helper_flush(target_ulong addr)
2779 {
2780 addr &= ~7;
2781 tb_invalidate_page_range(addr, addr + 8);
2782 }
2783
2784 #if !defined(CONFIG_USER_ONLY)
2785
2786 static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
2787 void *retaddr);
2788
2789 #define MMUSUFFIX _mmu
2790 #define ALIGNED_ONLY
2791
2792 #define SHIFT 0
2793 #include "softmmu_template.h"
2794
2795 #define SHIFT 1
2796 #include "softmmu_template.h"
2797
2798 #define SHIFT 2
2799 #include "softmmu_template.h"
2800
2801 #define SHIFT 3
2802 #include "softmmu_template.h"
2803
2804 /* XXX: make it generic ? */
2805 static void cpu_restore_state2(void *retaddr)
2806 {
2807 TranslationBlock *tb;
2808 unsigned long pc;
2809
2810 if (retaddr) {
2811 /* now we have a real cpu fault */
2812 pc = (unsigned long)retaddr;
2813 tb = tb_find_pc(pc);
2814 if (tb) {
2815 /* the PC is inside the translated code. It means that we have
2816 a virtual CPU fault */
2817 cpu_restore_state(tb, env, pc, (void *)(long)env->cond);
2818 }
2819 }
2820 }
2821
2822 static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
2823 void *retaddr)
2824 {
2825 #ifdef DEBUG_UNALIGNED
2826 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
2827 "\n", addr, env->pc);
2828 #endif
2829 cpu_restore_state2(retaddr);
2830 raise_exception(TT_UNALIGNED);
2831 }
2832
2833 /* try to fill the TLB and return an exception if error. If retaddr is
2834 NULL, it means that the function was called in C code (i.e. not
2835 from generated code or from helper.c) */
2836 /* XXX: fix it to restore all registers */
2837 void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
2838 {
2839 int ret;
2840 CPUState *saved_env;
2841
2842 /* XXX: hack to restore env in all cases, even if not called from
2843 generated code */
2844 saved_env = env;
2845 env = cpu_single_env;
2846
2847 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
2848 if (ret) {
2849 cpu_restore_state2(retaddr);
2850 cpu_loop_exit();
2851 }
2852 env = saved_env;
2853 }
2854
2855 #endif
2856
2857 #ifndef TARGET_SPARC64
2858 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
2859 int is_asi)
2860 {
2861 CPUState *saved_env;
2862
2863 /* XXX: hack to restore env in all cases, even if not called from
2864 generated code */
2865 saved_env = env;
2866 env = cpu_single_env;
2867 #ifdef DEBUG_UNASSIGNED
2868 if (is_asi)
2869 printf("Unassigned mem %s access to " TARGET_FMT_plx
2870 " asi 0x%02x from " TARGET_FMT_lx "\n",
2871 is_exec ? "exec" : is_write ? "write" : "read", addr, is_asi,
2872 env->pc);
2873 else
2874 printf("Unassigned mem %s access to " TARGET_FMT_plx " from "
2875 TARGET_FMT_lx "\n",
2876 is_exec ? "exec" : is_write ? "write" : "read", addr, env->pc);
2877 #endif
2878 if (env->mmuregs[3]) /* Fault status register */
2879 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
2880 if (is_asi)
2881 env->mmuregs[3] |= 1 << 16;
2882 if (env->psrs)
2883 env->mmuregs[3] |= 1 << 5;
2884 if (is_exec)
2885 env->mmuregs[3] |= 1 << 6;
2886 if (is_write)
2887 env->mmuregs[3] |= 1 << 7;
2888 env->mmuregs[3] |= (5 << 2) | 2;
2889 env->mmuregs[4] = addr; /* Fault address register */
2890 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
2891 if (is_exec)
2892 raise_exception(TT_CODE_ACCESS);
2893 else
2894 raise_exception(TT_DATA_ACCESS);
2895 }
2896 env = saved_env;
2897 }
2898 #else
2899 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
2900 int is_asi)
2901 {
2902 #ifdef DEBUG_UNASSIGNED
2903 CPUState *saved_env;
2904
2905 /* XXX: hack to restore env in all cases, even if not called from
2906 generated code */
2907 saved_env = env;
2908 env = cpu_single_env;
2909 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
2910 "\n", addr, env->pc);
2911 env = saved_env;
2912 #endif
2913 if (is_exec)
2914 raise_exception(TT_CODE_ACCESS);
2915 else
2916 raise_exception(TT_DATA_ACCESS);
2917 }
2918 #endif
2919
Qemu copy for testing