4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 Rest of V9 instructions, VIS instructions
26 NPC/PC static optimisations (use JUMP_TB when possible)
27 Optimize synthetic instructions
43 #define DYNAMIC_PC 1 /* dynamic pc value */
44 #define JUMP_PC 2 /* dynamic pc value which takes only two values
45 according to jump_pc[T2] */
47 typedef struct DisasContext
{
48 target_ulong pc
; /* current Program Counter: integer or DYNAMIC_PC */
49 target_ulong npc
; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
50 target_ulong jump_pc
[2]; /* used when JUMP_PC pc value is used */
54 struct TranslationBlock
*tb
;
58 const unsigned char *name
;
59 target_ulong iu_version
;
64 static uint16_t *gen_opc_ptr
;
65 static uint32_t *gen_opparam_ptr
;
70 #define DEF(s,n,copy_size) INDEX_op_ ## s,
78 // This function uses non-native bit order
79 #define GET_FIELD(X, FROM, TO) \
80 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
82 // This function uses the order in the manuals, i.e. bit 0 is 2^0
83 #define GET_FIELD_SP(X, FROM, TO) \
84 GET_FIELD(X, 31 - (TO), 31 - (FROM))
86 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
87 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
90 #define DFPREG(r) (((r & 1) << 6) | (r & 0x1e))
92 #define DFPREG(r) (r & 0x1e)
95 #ifdef USE_DIRECT_JUMP
98 #define TBPARAM(x) (long)(x)
101 static int sign_extend(int x
, int len
)
104 return (x
<< len
) >> len
;
107 #define IS_IMM (insn & (1<<13))
109 static void disas_sparc_insn(DisasContext
* dc
);
111 static GenOpFunc
* const gen_op_movl_TN_reg
[2][32] = {
182 static GenOpFunc
* const gen_op_movl_reg_TN
[3][32] = {
287 static GenOpFunc1
* const gen_op_movl_TN_im
[3] = {
293 // Sign extending version
294 static GenOpFunc1
* const gen_op_movl_TN_sim
[3] = {
300 #ifdef TARGET_SPARC64
301 #define GEN32(func, NAME) \
302 static GenOpFunc * const NAME ## _table [64] = { \
303 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
304 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
305 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
306 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
307 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
308 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
309 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
310 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
311 NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0, \
312 NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0, \
313 NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0, \
314 NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0, \
316 static inline void func(int n) \
318 NAME ## _table[n](); \
321 #define GEN32(func, NAME) \
322 static GenOpFunc *const NAME ## _table [32] = { \
323 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
324 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
325 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
326 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
327 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
328 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
329 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
330 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
332 static inline void func(int n) \
334 NAME ## _table[n](); \
338 /* floating point registers moves */
339 GEN32(gen_op_load_fpr_FT0
, gen_op_load_fpr_FT0_fprf
);
340 GEN32(gen_op_load_fpr_FT1
, gen_op_load_fpr_FT1_fprf
);
341 GEN32(gen_op_store_FT0_fpr
, gen_op_store_FT0_fpr_fprf
);
342 GEN32(gen_op_store_FT1_fpr
, gen_op_store_FT1_fpr_fprf
);
344 GEN32(gen_op_load_fpr_DT0
, gen_op_load_fpr_DT0_fprf
);
345 GEN32(gen_op_load_fpr_DT1
, gen_op_load_fpr_DT1_fprf
);
346 GEN32(gen_op_store_DT0_fpr
, gen_op_store_DT0_fpr_fprf
);
347 GEN32(gen_op_store_DT1_fpr
, gen_op_store_DT1_fpr_fprf
);
349 #ifdef TARGET_SPARC64
350 // 'a' versions allowed to user depending on asi
351 #if defined(CONFIG_USER_ONLY)
352 #define supervisor(dc) 0
353 #define hypervisor(dc) 0
354 #define gen_op_ldst(name) gen_op_##name##_raw()
355 #define OP_LD_TABLE(width) \
356 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
361 offset = GET_FIELD(insn, 25, 31); \
363 gen_op_ld_asi_reg(offset, size, sign); \
365 gen_op_st_asi_reg(offset, size, sign); \
368 asi = GET_FIELD(insn, 19, 26); \
370 case 0x80: /* Primary address space */ \
371 gen_op_##width##_raw(); \
373 case 0x82: /* Primary address space, non-faulting load */ \
374 gen_op_##width##_raw(); \
382 #define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
383 #define OP_LD_TABLE(width) \
384 static GenOpFunc * const gen_op_##width[] = { \
385 &gen_op_##width##_user, \
386 &gen_op_##width##_kernel, \
389 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
394 offset = GET_FIELD(insn, 25, 31); \
396 gen_op_ld_asi_reg(offset, size, sign); \
398 gen_op_st_asi_reg(offset, size, sign); \
401 asi = GET_FIELD(insn, 19, 26); \
403 gen_op_ld_asi(asi, size, sign); \
405 gen_op_st_asi(asi, size, sign); \
408 #define supervisor(dc) (dc->mem_idx == 1)
409 #define hypervisor(dc) (dc->mem_idx == 2)
412 #if defined(CONFIG_USER_ONLY)
413 #define gen_op_ldst(name) gen_op_##name##_raw()
414 #define OP_LD_TABLE(width)
415 #define supervisor(dc) 0
417 #define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
418 #define OP_LD_TABLE(width) \
419 static GenOpFunc * const gen_op_##width[] = { \
420 &gen_op_##width##_user, \
421 &gen_op_##width##_kernel, \
424 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
428 asi = GET_FIELD(insn, 19, 26); \
430 case 10: /* User data access */ \
431 gen_op_##width##_user(); \
433 case 11: /* Supervisor data access */ \
434 gen_op_##width##_kernel(); \
436 case 0x20 ... 0x2f: /* MMU passthrough */ \
438 gen_op_ld_asi(asi, size, sign); \
440 gen_op_st_asi(asi, size, sign); \
444 gen_op_ld_asi(asi, size, sign); \
446 gen_op_st_asi(asi, size, sign); \
451 #define supervisor(dc) (dc->mem_idx == 1)
472 #ifdef TARGET_SPARC64
481 static inline void gen_movl_imm_TN(int reg
, uint32_t imm
)
483 gen_op_movl_TN_im
[reg
](imm
);
486 static inline void gen_movl_imm_T1(uint32_t val
)
488 gen_movl_imm_TN(1, val
);
491 static inline void gen_movl_imm_T0(uint32_t val
)
493 gen_movl_imm_TN(0, val
);
496 static inline void gen_movl_simm_TN(int reg
, int32_t imm
)
498 gen_op_movl_TN_sim
[reg
](imm
);
501 static inline void gen_movl_simm_T1(int32_t val
)
503 gen_movl_simm_TN(1, val
);
506 static inline void gen_movl_simm_T0(int32_t val
)
508 gen_movl_simm_TN(0, val
);
511 static inline void gen_movl_reg_TN(int reg
, int t
)
514 gen_op_movl_reg_TN
[t
][reg
] ();
516 gen_movl_imm_TN(t
, 0);
519 static inline void gen_movl_reg_T0(int reg
)
521 gen_movl_reg_TN(reg
, 0);
524 static inline void gen_movl_reg_T1(int reg
)
526 gen_movl_reg_TN(reg
, 1);
529 static inline void gen_movl_reg_T2(int reg
)
531 gen_movl_reg_TN(reg
, 2);
534 static inline void gen_movl_TN_reg(int reg
, int t
)
537 gen_op_movl_TN_reg
[t
][reg
] ();
540 static inline void gen_movl_T0_reg(int reg
)
542 gen_movl_TN_reg(reg
, 0);
545 static inline void gen_movl_T1_reg(int reg
)
547 gen_movl_TN_reg(reg
, 1);
550 static inline void gen_jmp_im(target_ulong pc
)
552 #ifdef TARGET_SPARC64
553 if (pc
== (uint32_t)pc
) {
556 gen_op_jmp_im64(pc
>> 32, pc
);
563 static inline void gen_movl_npc_im(target_ulong npc
)
565 #ifdef TARGET_SPARC64
566 if (npc
== (uint32_t)npc
) {
567 gen_op_movl_npc_im(npc
);
569 gen_op_movq_npc_im64(npc
>> 32, npc
);
572 gen_op_movl_npc_im(npc
);
576 static inline void gen_goto_tb(DisasContext
*s
, int tb_num
,
577 target_ulong pc
, target_ulong npc
)
579 TranslationBlock
*tb
;
582 if ((pc
& TARGET_PAGE_MASK
) == (tb
->pc
& TARGET_PAGE_MASK
) &&
583 (npc
& TARGET_PAGE_MASK
) == (tb
->pc
& TARGET_PAGE_MASK
)) {
584 /* jump to same page: we can use a direct jump */
586 gen_op_goto_tb0(TBPARAM(tb
));
588 gen_op_goto_tb1(TBPARAM(tb
));
590 gen_movl_npc_im(npc
);
591 gen_op_movl_T0_im((long)tb
+ tb_num
);
594 /* jump to another page: currently not optimized */
596 gen_movl_npc_im(npc
);
602 static inline void gen_branch2(DisasContext
*dc
, target_ulong pc1
,
607 l1
= gen_new_label();
609 gen_op_jz_T2_label(l1
);
611 gen_goto_tb(dc
, 0, pc1
, pc1
+ 4);
614 gen_goto_tb(dc
, 1, pc2
, pc2
+ 4);
617 static inline void gen_branch_a(DisasContext
*dc
, target_ulong pc1
,
622 l1
= gen_new_label();
624 gen_op_jz_T2_label(l1
);
626 gen_goto_tb(dc
, 0, pc2
, pc1
);
629 gen_goto_tb(dc
, 1, pc2
+ 4, pc2
+ 8);
632 static inline void gen_branch(DisasContext
*dc
, target_ulong pc
,
635 gen_goto_tb(dc
, 0, pc
, npc
);
638 static inline void gen_generic_branch(target_ulong npc1
, target_ulong npc2
)
642 l1
= gen_new_label();
643 l2
= gen_new_label();
644 gen_op_jz_T2_label(l1
);
646 gen_movl_npc_im(npc1
);
647 gen_op_jmp_label(l2
);
650 gen_movl_npc_im(npc2
);
654 /* call this function before using T2 as it may have been set for a jump */
655 static inline void flush_T2(DisasContext
* dc
)
657 if (dc
->npc
== JUMP_PC
) {
658 gen_generic_branch(dc
->jump_pc
[0], dc
->jump_pc
[1]);
659 dc
->npc
= DYNAMIC_PC
;
663 static inline void save_npc(DisasContext
* dc
)
665 if (dc
->npc
== JUMP_PC
) {
666 gen_generic_branch(dc
->jump_pc
[0], dc
->jump_pc
[1]);
667 dc
->npc
= DYNAMIC_PC
;
668 } else if (dc
->npc
!= DYNAMIC_PC
) {
669 gen_movl_npc_im(dc
->npc
);
673 static inline void save_state(DisasContext
* dc
)
679 static inline void gen_mov_pc_npc(DisasContext
* dc
)
681 if (dc
->npc
== JUMP_PC
) {
682 gen_generic_branch(dc
->jump_pc
[0], dc
->jump_pc
[1]);
685 } else if (dc
->npc
== DYNAMIC_PC
) {
693 static GenOpFunc
* const gen_cond
[2][16] = {
713 #ifdef TARGET_SPARC64
734 static GenOpFunc
* const gen_fcond
[4][16] = {
753 #ifdef TARGET_SPARC64
756 gen_op_eval_fbne_fcc1
,
757 gen_op_eval_fblg_fcc1
,
758 gen_op_eval_fbul_fcc1
,
759 gen_op_eval_fbl_fcc1
,
760 gen_op_eval_fbug_fcc1
,
761 gen_op_eval_fbg_fcc1
,
762 gen_op_eval_fbu_fcc1
,
764 gen_op_eval_fbe_fcc1
,
765 gen_op_eval_fbue_fcc1
,
766 gen_op_eval_fbge_fcc1
,
767 gen_op_eval_fbuge_fcc1
,
768 gen_op_eval_fble_fcc1
,
769 gen_op_eval_fbule_fcc1
,
770 gen_op_eval_fbo_fcc1
,
774 gen_op_eval_fbne_fcc2
,
775 gen_op_eval_fblg_fcc2
,
776 gen_op_eval_fbul_fcc2
,
777 gen_op_eval_fbl_fcc2
,
778 gen_op_eval_fbug_fcc2
,
779 gen_op_eval_fbg_fcc2
,
780 gen_op_eval_fbu_fcc2
,
782 gen_op_eval_fbe_fcc2
,
783 gen_op_eval_fbue_fcc2
,
784 gen_op_eval_fbge_fcc2
,
785 gen_op_eval_fbuge_fcc2
,
786 gen_op_eval_fble_fcc2
,
787 gen_op_eval_fbule_fcc2
,
788 gen_op_eval_fbo_fcc2
,
792 gen_op_eval_fbne_fcc3
,
793 gen_op_eval_fblg_fcc3
,
794 gen_op_eval_fbul_fcc3
,
795 gen_op_eval_fbl_fcc3
,
796 gen_op_eval_fbug_fcc3
,
797 gen_op_eval_fbg_fcc3
,
798 gen_op_eval_fbu_fcc3
,
800 gen_op_eval_fbe_fcc3
,
801 gen_op_eval_fbue_fcc3
,
802 gen_op_eval_fbge_fcc3
,
803 gen_op_eval_fbuge_fcc3
,
804 gen_op_eval_fble_fcc3
,
805 gen_op_eval_fbule_fcc3
,
806 gen_op_eval_fbo_fcc3
,
813 #ifdef TARGET_SPARC64
814 static void gen_cond_reg(int cond
)
840 /* XXX: potentially incorrect if dynamic npc */
841 static void do_branch(DisasContext
* dc
, int32_t offset
, uint32_t insn
, int cc
)
843 unsigned int cond
= GET_FIELD(insn
, 3, 6), a
= (insn
& (1 << 29));
844 target_ulong target
= dc
->pc
+ offset
;
847 /* unconditional not taken */
849 dc
->pc
= dc
->npc
+ 4;
850 dc
->npc
= dc
->pc
+ 4;
853 dc
->npc
= dc
->pc
+ 4;
855 } else if (cond
== 0x8) {
856 /* unconditional taken */
859 dc
->npc
= dc
->pc
+ 4;
866 gen_cond
[cc
][cond
]();
868 gen_branch_a(dc
, target
, dc
->npc
);
872 dc
->jump_pc
[0] = target
;
873 dc
->jump_pc
[1] = dc
->npc
+ 4;
879 /* XXX: potentially incorrect if dynamic npc */
880 static void do_fbranch(DisasContext
* dc
, int32_t offset
, uint32_t insn
, int cc
)
882 unsigned int cond
= GET_FIELD(insn
, 3, 6), a
= (insn
& (1 << 29));
883 target_ulong target
= dc
->pc
+ offset
;
886 /* unconditional not taken */
888 dc
->pc
= dc
->npc
+ 4;
889 dc
->npc
= dc
->pc
+ 4;
892 dc
->npc
= dc
->pc
+ 4;
894 } else if (cond
== 0x8) {
895 /* unconditional taken */
898 dc
->npc
= dc
->pc
+ 4;
905 gen_fcond
[cc
][cond
]();
907 gen_branch_a(dc
, target
, dc
->npc
);
911 dc
->jump_pc
[0] = target
;
912 dc
->jump_pc
[1] = dc
->npc
+ 4;
918 #ifdef TARGET_SPARC64
919 /* XXX: potentially incorrect if dynamic npc */
920 static void do_branch_reg(DisasContext
* dc
, int32_t offset
, uint32_t insn
)
922 unsigned int cond
= GET_FIELD_SP(insn
, 25, 27), a
= (insn
& (1 << 29));
923 target_ulong target
= dc
->pc
+ offset
;
928 gen_branch_a(dc
, target
, dc
->npc
);
932 dc
->jump_pc
[0] = target
;
933 dc
->jump_pc
[1] = dc
->npc
+ 4;
938 static GenOpFunc
* const gen_fcmps
[4] = {
945 static GenOpFunc
* const gen_fcmpd
[4] = {
952 static GenOpFunc
* const gen_fcmpes
[4] = {
959 static GenOpFunc
* const gen_fcmped
[4] = {
968 static int gen_trap_ifnofpu(DisasContext
* dc
)
970 #if !defined(CONFIG_USER_ONLY)
971 if (!dc
->fpu_enabled
) {
973 gen_op_exception(TT_NFPU_INSN
);
981 /* before an instruction, dc->pc must be static */
982 static void disas_sparc_insn(DisasContext
* dc
)
984 unsigned int insn
, opc
, rs1
, rs2
, rd
;
986 insn
= ldl_code(dc
->pc
);
987 opc
= GET_FIELD(insn
, 0, 1);
989 rd
= GET_FIELD(insn
, 2, 6);
991 case 0: /* branches/sethi */
993 unsigned int xop
= GET_FIELD(insn
, 7, 9);
996 #ifdef TARGET_SPARC64
997 case 0x1: /* V9 BPcc */
1001 target
= GET_FIELD_SP(insn
, 0, 18);
1002 target
= sign_extend(target
, 18);
1004 cc
= GET_FIELD_SP(insn
, 20, 21);
1006 do_branch(dc
, target
, insn
, 0);
1008 do_branch(dc
, target
, insn
, 1);
1013 case 0x3: /* V9 BPr */
1015 target
= GET_FIELD_SP(insn
, 0, 13) |
1016 (GET_FIELD_SP(insn
, 20, 21) << 14);
1017 target
= sign_extend(target
, 16);
1019 rs1
= GET_FIELD(insn
, 13, 17);
1020 gen_movl_reg_T0(rs1
);
1021 do_branch_reg(dc
, target
, insn
);
1024 case 0x5: /* V9 FBPcc */
1026 int cc
= GET_FIELD_SP(insn
, 20, 21);
1027 if (gen_trap_ifnofpu(dc
))
1029 target
= GET_FIELD_SP(insn
, 0, 18);
1030 target
= sign_extend(target
, 19);
1032 do_fbranch(dc
, target
, insn
, cc
);
1036 case 0x7: /* CBN+x */
1041 case 0x2: /* BN+x */
1043 target
= GET_FIELD(insn
, 10, 31);
1044 target
= sign_extend(target
, 22);
1046 do_branch(dc
, target
, insn
, 0);
1049 case 0x6: /* FBN+x */
1051 if (gen_trap_ifnofpu(dc
))
1053 target
= GET_FIELD(insn
, 10, 31);
1054 target
= sign_extend(target
, 22);
1056 do_fbranch(dc
, target
, insn
, 0);
1059 case 0x4: /* SETHI */
1064 uint32_t value
= GET_FIELD(insn
, 10, 31);
1065 gen_movl_imm_T0(value
<< 10);
1066 gen_movl_T0_reg(rd
);
1071 case 0x0: /* UNIMPL */
1080 target_long target
= GET_FIELDs(insn
, 2, 31) << 2;
1082 #ifdef TARGET_SPARC64
1083 if (dc
->pc
== (uint32_t)dc
->pc
) {
1084 gen_op_movl_T0_im(dc
->pc
);
1086 gen_op_movq_T0_im64(dc
->pc
>> 32, dc
->pc
);
1089 gen_op_movl_T0_im(dc
->pc
);
1091 gen_movl_T0_reg(15);
1097 case 2: /* FPU & Logical Operations */
1099 unsigned int xop
= GET_FIELD(insn
, 7, 12);
1100 if (xop
== 0x3a) { /* generate trap */
1103 rs1
= GET_FIELD(insn
, 13, 17);
1104 gen_movl_reg_T0(rs1
);
1106 rs2
= GET_FIELD(insn
, 25, 31);
1110 gen_movl_simm_T1(rs2
);
1116 rs2
= GET_FIELD(insn
, 27, 31);
1120 gen_movl_reg_T1(rs2
);
1126 cond
= GET_FIELD(insn
, 3, 6);
1130 } else if (cond
!= 0) {
1131 #ifdef TARGET_SPARC64
1133 int cc
= GET_FIELD_SP(insn
, 11, 12);
1137 gen_cond
[0][cond
]();
1139 gen_cond
[1][cond
]();
1145 gen_cond
[0][cond
]();
1154 } else if (xop
== 0x28) {
1155 rs1
= GET_FIELD(insn
, 13, 17);
1158 #ifndef TARGET_SPARC64
1159 case 0x01 ... 0x0e: /* undefined in the SPARCv8
1160 manual, rdy on the microSPARC
1162 case 0x0f: /* stbar in the SPARCv8 manual,
1163 rdy on the microSPARC II */
1164 case 0x10 ... 0x1f: /* implementation-dependent in the
1165 SPARCv8 manual, rdy on the
1168 gen_op_movtl_T0_env(offsetof(CPUSPARCState
, y
));
1169 gen_movl_T0_reg(rd
);
1171 #ifdef TARGET_SPARC64
1172 case 0x2: /* V9 rdccr */
1174 gen_movl_T0_reg(rd
);
1176 case 0x3: /* V9 rdasi */
1177 gen_op_movl_T0_env(offsetof(CPUSPARCState
, asi
));
1178 gen_movl_T0_reg(rd
);
1180 case 0x4: /* V9 rdtick */
1182 gen_movl_T0_reg(rd
);
1184 case 0x5: /* V9 rdpc */
1185 if (dc
->pc
== (uint32_t)dc
->pc
) {
1186 gen_op_movl_T0_im(dc
->pc
);
1188 gen_op_movq_T0_im64(dc
->pc
>> 32, dc
->pc
);
1190 gen_movl_T0_reg(rd
);
1192 case 0x6: /* V9 rdfprs */
1193 gen_op_movl_T0_env(offsetof(CPUSPARCState
, fprs
));
1194 gen_movl_T0_reg(rd
);
1196 case 0xf: /* V9 membar */
1197 break; /* no effect */
1198 case 0x13: /* Graphics Status */
1199 if (gen_trap_ifnofpu(dc
))
1201 gen_op_movtl_T0_env(offsetof(CPUSPARCState
, gsr
));
1202 gen_movl_T0_reg(rd
);
1204 case 0x17: /* Tick compare */
1205 gen_op_movtl_T0_env(offsetof(CPUSPARCState
, tick_cmpr
));
1206 gen_movl_T0_reg(rd
);
1208 case 0x18: /* System tick */
1210 gen_movl_T0_reg(rd
);
1212 case 0x19: /* System tick compare */
1213 gen_op_movtl_T0_env(offsetof(CPUSPARCState
, stick_cmpr
));
1214 gen_movl_T0_reg(rd
);
1216 case 0x10: /* Performance Control */
1217 case 0x11: /* Performance Instrumentation Counter */
1218 case 0x12: /* Dispatch Control */
1219 case 0x14: /* Softint set, WO */
1220 case 0x15: /* Softint clear, WO */
1221 case 0x16: /* Softint write */
1226 #if !defined(CONFIG_USER_ONLY)
1227 } else if (xop
== 0x29) { /* rdpsr / UA2005 rdhpr */
1228 #ifndef TARGET_SPARC64
1229 if (!supervisor(dc
))
1233 if (!hypervisor(dc
))
1235 rs1
= GET_FIELD(insn
, 13, 17);
1238 // gen_op_rdhpstate();
1241 // gen_op_rdhtstate();
1244 gen_op_movl_T0_env(offsetof(CPUSPARCState
, hintp
));
1247 gen_op_movl_T0_env(offsetof(CPUSPARCState
, htba
));
1250 gen_op_movl_T0_env(offsetof(CPUSPARCState
, hver
));
1252 case 31: // hstick_cmpr
1253 gen_op_movl_env_T0(offsetof(CPUSPARCState
, hstick_cmpr
));
1259 gen_movl_T0_reg(rd
);
1261 } else if (xop
== 0x2a) { /* rdwim / V9 rdpr */
1262 if (!supervisor(dc
))
1264 #ifdef TARGET_SPARC64
1265 rs1
= GET_FIELD(insn
, 13, 17);
1283 gen_op_movtl_T0_env(offsetof(CPUSPARCState
, tbr
));
1289 gen_op_movl_T0_env(offsetof(CPUSPARCState
, tl
));
1292 gen_op_movl_T0_env(offsetof(CPUSPARCState
, psrpil
));
1298 gen_op_movl_T0_env(offsetof(CPUSPARCState
, cansave
));
1300 case 11: // canrestore
1301 gen_op_movl_T0_env(offsetof(CPUSPARCState
, canrestore
));
1303 case 12: // cleanwin
1304 gen_op_movl_T0_env(offsetof(CPUSPARCState
, cleanwin
));
1306 case 13: // otherwin
1307 gen_op_movl_T0_env(offsetof(CPUSPARCState
, otherwin
));
1310 gen_op_movl_T0_env(offsetof(CPUSPARCState
, wstate
));
1312 case 16: // UA2005 gl
1313 gen_op_movl_T0_env(offsetof(CPUSPARCState
, gl
));
1315 case 26: // UA2005 strand status
1316 if (!hypervisor(dc
))
1318 gen_op_movl_T0_env(offsetof(CPUSPARCState
, ssr
));
1321 gen_op_movtl_T0_env(offsetof(CPUSPARCState
, version
));
1328 gen_op_movl_T0_env(offsetof(CPUSPARCState
, wim
));
1330 gen_movl_T0_reg(rd
);
1332 } else if (xop
== 0x2b) { /* rdtbr / V9 flushw */
1333 #ifdef TARGET_SPARC64
1336 if (!supervisor(dc
))
1338 gen_op_movtl_T0_env(offsetof(CPUSPARCState
, tbr
));
1339 gen_movl_T0_reg(rd
);
1343 } else if (xop
== 0x34) { /* FPU Operations */
1344 if (gen_trap_ifnofpu(dc
))
1346 gen_op_clear_ieee_excp_and_FTT();
1347 rs1
= GET_FIELD(insn
, 13, 17);
1348 rs2
= GET_FIELD(insn
, 27, 31);
1349 xop
= GET_FIELD(insn
, 18, 26);
1351 case 0x1: /* fmovs */
1352 gen_op_load_fpr_FT0(rs2
);
1353 gen_op_store_FT0_fpr(rd
);
1355 case 0x5: /* fnegs */
1356 gen_op_load_fpr_FT1(rs2
);
1358 gen_op_store_FT0_fpr(rd
);
1360 case 0x9: /* fabss */
1361 gen_op_load_fpr_FT1(rs2
);
1363 gen_op_store_FT0_fpr(rd
);
1365 case 0x29: /* fsqrts */
1366 gen_op_load_fpr_FT1(rs2
);
1368 gen_op_store_FT0_fpr(rd
);
1370 case 0x2a: /* fsqrtd */
1371 gen_op_load_fpr_DT1(DFPREG(rs2
));
1373 gen_op_store_DT0_fpr(DFPREG(rd
));
1375 case 0x2b: /* fsqrtq */
1378 gen_op_load_fpr_FT0(rs1
);
1379 gen_op_load_fpr_FT1(rs2
);
1381 gen_op_store_FT0_fpr(rd
);
1384 gen_op_load_fpr_DT0(DFPREG(rs1
));
1385 gen_op_load_fpr_DT1(DFPREG(rs2
));
1387 gen_op_store_DT0_fpr(DFPREG(rd
));
1389 case 0x43: /* faddq */
1392 gen_op_load_fpr_FT0(rs1
);
1393 gen_op_load_fpr_FT1(rs2
);
1395 gen_op_store_FT0_fpr(rd
);
1398 gen_op_load_fpr_DT0(DFPREG(rs1
));
1399 gen_op_load_fpr_DT1(DFPREG(rs2
));
1401 gen_op_store_DT0_fpr(DFPREG(rd
));
1403 case 0x47: /* fsubq */
1406 gen_op_load_fpr_FT0(rs1
);
1407 gen_op_load_fpr_FT1(rs2
);
1409 gen_op_store_FT0_fpr(rd
);
1412 gen_op_load_fpr_DT0(DFPREG(rs1
));
1413 gen_op_load_fpr_DT1(DFPREG(rs2
));
1415 gen_op_store_DT0_fpr(rd
);
1417 case 0x4b: /* fmulq */
1420 gen_op_load_fpr_FT0(rs1
);
1421 gen_op_load_fpr_FT1(rs2
);
1423 gen_op_store_FT0_fpr(rd
);
1426 gen_op_load_fpr_DT0(DFPREG(rs1
));
1427 gen_op_load_fpr_DT1(DFPREG(rs2
));
1429 gen_op_store_DT0_fpr(DFPREG(rd
));
1431 case 0x4f: /* fdivq */
1434 gen_op_load_fpr_FT0(rs1
);
1435 gen_op_load_fpr_FT1(rs2
);
1437 gen_op_store_DT0_fpr(DFPREG(rd
));
1439 case 0x6e: /* fdmulq */
1442 gen_op_load_fpr_FT1(rs2
);
1444 gen_op_store_FT0_fpr(rd
);
1447 gen_op_load_fpr_DT1(DFPREG(rs2
));
1449 gen_op_store_FT0_fpr(rd
);
1451 case 0xc7: /* fqtos */
1454 gen_op_load_fpr_FT1(rs2
);
1456 gen_op_store_DT0_fpr(DFPREG(rd
));
1459 gen_op_load_fpr_FT1(rs2
);
1461 gen_op_store_DT0_fpr(DFPREG(rd
));
1463 case 0xcb: /* fqtod */
1465 case 0xcc: /* fitoq */
1467 case 0xcd: /* fstoq */
1469 case 0xce: /* fdtoq */
1472 gen_op_load_fpr_FT1(rs2
);
1474 gen_op_store_FT0_fpr(rd
);
1477 gen_op_load_fpr_DT1(rs2
);
1479 gen_op_store_FT0_fpr(rd
);
1481 case 0xd3: /* fqtoi */
1483 #ifdef TARGET_SPARC64
1484 case 0x2: /* V9 fmovd */
1485 gen_op_load_fpr_DT0(DFPREG(rs2
));
1486 gen_op_store_DT0_fpr(DFPREG(rd
));
1488 case 0x6: /* V9 fnegd */
1489 gen_op_load_fpr_DT1(DFPREG(rs2
));
1491 gen_op_store_DT0_fpr(DFPREG(rd
));
1493 case 0xa: /* V9 fabsd */
1494 gen_op_load_fpr_DT1(DFPREG(rs2
));
1496 gen_op_store_DT0_fpr(DFPREG(rd
));
1498 case 0x81: /* V9 fstox */
1499 gen_op_load_fpr_FT1(rs2
);
1501 gen_op_store_DT0_fpr(DFPREG(rd
));
1503 case 0x82: /* V9 fdtox */
1504 gen_op_load_fpr_DT1(DFPREG(rs2
));
1506 gen_op_store_DT0_fpr(DFPREG(rd
));
1508 case 0x84: /* V9 fxtos */
1509 gen_op_load_fpr_DT1(DFPREG(rs2
));
1511 gen_op_store_FT0_fpr(rd
);
1513 case 0x88: /* V9 fxtod */
1514 gen_op_load_fpr_DT1(DFPREG(rs2
));
1516 gen_op_store_DT0_fpr(DFPREG(rd
));
1518 case 0x3: /* V9 fmovq */
1519 case 0x7: /* V9 fnegq */
1520 case 0xb: /* V9 fabsq */
1521 case 0x83: /* V9 fqtox */
1522 case 0x8c: /* V9 fxtoq */
1528 } else if (xop
== 0x35) { /* FPU Operations */
1529 #ifdef TARGET_SPARC64
1532 if (gen_trap_ifnofpu(dc
))
1534 gen_op_clear_ieee_excp_and_FTT();
1535 rs1
= GET_FIELD(insn
, 13, 17);
1536 rs2
= GET_FIELD(insn
, 27, 31);
1537 xop
= GET_FIELD(insn
, 18, 26);
1538 #ifdef TARGET_SPARC64
1539 if ((xop
& 0x11f) == 0x005) { // V9 fmovsr
1540 cond
= GET_FIELD_SP(insn
, 14, 17);
1541 gen_op_load_fpr_FT0(rd
);
1542 gen_op_load_fpr_FT1(rs2
);
1543 rs1
= GET_FIELD(insn
, 13, 17);
1544 gen_movl_reg_T0(rs1
);
1548 gen_op_store_FT0_fpr(rd
);
1550 } else if ((xop
& 0x11f) == 0x006) { // V9 fmovdr
1551 cond
= GET_FIELD_SP(insn
, 14, 17);
1552 gen_op_load_fpr_DT0(rd
);
1553 gen_op_load_fpr_DT1(rs2
);
1555 rs1
= GET_FIELD(insn
, 13, 17);
1556 gen_movl_reg_T0(rs1
);
1559 gen_op_store_DT0_fpr(rd
);
1561 } else if ((xop
& 0x11f) == 0x007) { // V9 fmovqr
1566 #ifdef TARGET_SPARC64
1567 case 0x001: /* V9 fmovscc %fcc0 */
1568 cond
= GET_FIELD_SP(insn
, 14, 17);
1569 gen_op_load_fpr_FT0(rd
);
1570 gen_op_load_fpr_FT1(rs2
);
1572 gen_fcond
[0][cond
]();
1574 gen_op_store_FT0_fpr(rd
);
1576 case 0x002: /* V9 fmovdcc %fcc0 */
1577 cond
= GET_FIELD_SP(insn
, 14, 17);
1578 gen_op_load_fpr_DT0(rd
);
1579 gen_op_load_fpr_DT1(rs2
);
1581 gen_fcond
[0][cond
]();
1583 gen_op_store_DT0_fpr(rd
);
1585 case 0x003: /* V9 fmovqcc %fcc0 */
1587 case 0x041: /* V9 fmovscc %fcc1 */
1588 cond
= GET_FIELD_SP(insn
, 14, 17);
1589 gen_op_load_fpr_FT0(rd
);
1590 gen_op_load_fpr_FT1(rs2
);
1592 gen_fcond
[1][cond
]();
1594 gen_op_store_FT0_fpr(rd
);
1596 case 0x042: /* V9 fmovdcc %fcc1 */
1597 cond
= GET_FIELD_SP(insn
, 14, 17);
1598 gen_op_load_fpr_DT0(rd
);
1599 gen_op_load_fpr_DT1(rs2
);
1601 gen_fcond
[1][cond
]();
1603 gen_op_store_DT0_fpr(rd
);
1605 case 0x043: /* V9 fmovqcc %fcc1 */
1607 case 0x081: /* V9 fmovscc %fcc2 */
1608 cond
= GET_FIELD_SP(insn
, 14, 17);
1609 gen_op_load_fpr_FT0(rd
);
1610 gen_op_load_fpr_FT1(rs2
);
1612 gen_fcond
[2][cond
]();
1614 gen_op_store_FT0_fpr(rd
);
1616 case 0x082: /* V9 fmovdcc %fcc2 */
1617 cond
= GET_FIELD_SP(insn
, 14, 17);
1618 gen_op_load_fpr_DT0(rd
);
1619 gen_op_load_fpr_DT1(rs2
);
1621 gen_fcond
[2][cond
]();
1623 gen_op_store_DT0_fpr(rd
);
1625 case 0x083: /* V9 fmovqcc %fcc2 */
1627 case 0x0c1: /* V9 fmovscc %fcc3 */
1628 cond
= GET_FIELD_SP(insn
, 14, 17);
1629 gen_op_load_fpr_FT0(rd
);
1630 gen_op_load_fpr_FT1(rs2
);
1632 gen_fcond
[3][cond
]();
1634 gen_op_store_FT0_fpr(rd
);
1636 case 0x0c2: /* V9 fmovdcc %fcc3 */
1637 cond
= GET_FIELD_SP(insn
, 14, 17);
1638 gen_op_load_fpr_DT0(rd
);
1639 gen_op_load_fpr_DT1(rs2
);
1641 gen_fcond
[3][cond
]();
1643 gen_op_store_DT0_fpr(rd
);
1645 case 0x0c3: /* V9 fmovqcc %fcc3 */
1647 case 0x101: /* V9 fmovscc %icc */
1648 cond
= GET_FIELD_SP(insn
, 14, 17);
1649 gen_op_load_fpr_FT0(rd
);
1650 gen_op_load_fpr_FT1(rs2
);
1652 gen_cond
[0][cond
]();
1654 gen_op_store_FT0_fpr(rd
);
1656 case 0x102: /* V9 fmovdcc %icc */
1657 cond
= GET_FIELD_SP(insn
, 14, 17);
1658 gen_op_load_fpr_DT0(rd
);
1659 gen_op_load_fpr_DT1(rs2
);
1661 gen_cond
[0][cond
]();
1663 gen_op_store_DT0_fpr(rd
);
1665 case 0x103: /* V9 fmovqcc %icc */
1667 case 0x181: /* V9 fmovscc %xcc */
1668 cond
= GET_FIELD_SP(insn
, 14, 17);
1669 gen_op_load_fpr_FT0(rd
);
1670 gen_op_load_fpr_FT1(rs2
);
1672 gen_cond
[1][cond
]();
1674 gen_op_store_FT0_fpr(rd
);
1676 case 0x182: /* V9 fmovdcc %xcc */
1677 cond
= GET_FIELD_SP(insn
, 14, 17);
1678 gen_op_load_fpr_DT0(rd
);
1679 gen_op_load_fpr_DT1(rs2
);
1681 gen_cond
[1][cond
]();
1683 gen_op_store_DT0_fpr(rd
);
1685 case 0x183: /* V9 fmovqcc %xcc */
1688 case 0x51: /* V9 %fcc */
1689 gen_op_load_fpr_FT0(rs1
);
1690 gen_op_load_fpr_FT1(rs2
);
1691 #ifdef TARGET_SPARC64
1692 gen_fcmps
[rd
& 3]();
1697 case 0x52: /* V9 %fcc */
1698 gen_op_load_fpr_DT0(DFPREG(rs1
));
1699 gen_op_load_fpr_DT1(DFPREG(rs2
));
1700 #ifdef TARGET_SPARC64
1701 gen_fcmpd
[rd
& 3]();
1706 case 0x53: /* fcmpq */
1708 case 0x55: /* fcmpes, V9 %fcc */
1709 gen_op_load_fpr_FT0(rs1
);
1710 gen_op_load_fpr_FT1(rs2
);
1711 #ifdef TARGET_SPARC64
1712 gen_fcmpes
[rd
& 3]();
1717 case 0x56: /* fcmped, V9 %fcc */
1718 gen_op_load_fpr_DT0(DFPREG(rs1
));
1719 gen_op_load_fpr_DT1(DFPREG(rs2
));
1720 #ifdef TARGET_SPARC64
1721 gen_fcmped
[rd
& 3]();
1726 case 0x57: /* fcmpeq */
1732 } else if (xop
== 0x2) {
1735 rs1
= GET_FIELD(insn
, 13, 17);
1737 // or %g0, x, y -> mov T1, x; mov y, T1
1738 if (IS_IMM
) { /* immediate */
1739 rs2
= GET_FIELDs(insn
, 19, 31);
1740 gen_movl_simm_T1(rs2
);
1741 } else { /* register */
1742 rs2
= GET_FIELD(insn
, 27, 31);
1743 gen_movl_reg_T1(rs2
);
1745 gen_movl_T1_reg(rd
);
1747 gen_movl_reg_T0(rs1
);
1748 if (IS_IMM
) { /* immediate */
1749 // or x, #0, y -> mov T1, x; mov y, T1
1750 rs2
= GET_FIELDs(insn
, 19, 31);
1752 gen_movl_simm_T1(rs2
);
1755 } else { /* register */
1756 // or x, %g0, y -> mov T1, x; mov y, T1
1757 rs2
= GET_FIELD(insn
, 27, 31);
1759 gen_movl_reg_T1(rs2
);
1763 gen_movl_T0_reg(rd
);
1766 #ifdef TARGET_SPARC64
1767 } else if (xop
== 0x25) { /* sll, V9 sllx */
1768 rs1
= GET_FIELD(insn
, 13, 17);
1769 gen_movl_reg_T0(rs1
);
1770 if (IS_IMM
) { /* immediate */
1771 rs2
= GET_FIELDs(insn
, 20, 31);
1772 gen_movl_simm_T1(rs2
);
1773 } else { /* register */
1774 rs2
= GET_FIELD(insn
, 27, 31);
1775 gen_movl_reg_T1(rs2
);
1777 if (insn
& (1 << 12))
1781 gen_movl_T0_reg(rd
);
1782 } else if (xop
== 0x26) { /* srl, V9 srlx */
1783 rs1
= GET_FIELD(insn
, 13, 17);
1784 gen_movl_reg_T0(rs1
);
1785 if (IS_IMM
) { /* immediate */
1786 rs2
= GET_FIELDs(insn
, 20, 31);
1787 gen_movl_simm_T1(rs2
);
1788 } else { /* register */
1789 rs2
= GET_FIELD(insn
, 27, 31);
1790 gen_movl_reg_T1(rs2
);
1792 if (insn
& (1 << 12))
1796 gen_movl_T0_reg(rd
);
1797 } else if (xop
== 0x27) { /* sra, V9 srax */
1798 rs1
= GET_FIELD(insn
, 13, 17);
1799 gen_movl_reg_T0(rs1
);
1800 if (IS_IMM
) { /* immediate */
1801 rs2
= GET_FIELDs(insn
, 20, 31);
1802 gen_movl_simm_T1(rs2
);
1803 } else { /* register */
1804 rs2
= GET_FIELD(insn
, 27, 31);
1805 gen_movl_reg_T1(rs2
);
1807 if (insn
& (1 << 12))
1811 gen_movl_T0_reg(rd
);
1813 } else if (xop
< 0x36) {
1814 rs1
= GET_FIELD(insn
, 13, 17);
1815 gen_movl_reg_T0(rs1
);
1816 if (IS_IMM
) { /* immediate */
1817 rs2
= GET_FIELDs(insn
, 19, 31);
1818 gen_movl_simm_T1(rs2
);
1819 } else { /* register */
1820 rs2
= GET_FIELD(insn
, 27, 31);
1821 gen_movl_reg_T1(rs2
);
1824 switch (xop
& ~0x10) {
1827 gen_op_add_T1_T0_cc();
1834 gen_op_logic_T0_cc();
1839 gen_op_logic_T0_cc();
1844 gen_op_logic_T0_cc();
1848 gen_op_sub_T1_T0_cc();
1853 gen_op_andn_T1_T0();
1855 gen_op_logic_T0_cc();
1860 gen_op_logic_T0_cc();
1863 gen_op_xnor_T1_T0();
1865 gen_op_logic_T0_cc();
1869 gen_op_addx_T1_T0_cc();
1871 gen_op_addx_T1_T0();
1873 #ifdef TARGET_SPARC64
1874 case 0x9: /* V9 mulx */
1875 gen_op_mulx_T1_T0();
1879 gen_op_umul_T1_T0();
1881 gen_op_logic_T0_cc();
1884 gen_op_smul_T1_T0();
1886 gen_op_logic_T0_cc();
1890 gen_op_subx_T1_T0_cc();
1892 gen_op_subx_T1_T0();
1894 #ifdef TARGET_SPARC64
1895 case 0xd: /* V9 udivx */
1896 gen_op_udivx_T1_T0();
1900 gen_op_udiv_T1_T0();
1905 gen_op_sdiv_T1_T0();
1912 gen_movl_T0_reg(rd
);
1915 case 0x20: /* taddcc */
1916 gen_op_tadd_T1_T0_cc();
1917 gen_movl_T0_reg(rd
);
1919 case 0x21: /* tsubcc */
1920 gen_op_tsub_T1_T0_cc();
1921 gen_movl_T0_reg(rd
);
1923 case 0x22: /* taddcctv */
1924 gen_op_tadd_T1_T0_ccTV();
1925 gen_movl_T0_reg(rd
);
1927 case 0x23: /* tsubcctv */
1928 gen_op_tsub_T1_T0_ccTV();
1929 gen_movl_T0_reg(rd
);
1931 case 0x24: /* mulscc */
1932 gen_op_mulscc_T1_T0();
1933 gen_movl_T0_reg(rd
);
1935 #ifndef TARGET_SPARC64
1936 case 0x25: /* sll */
1938 gen_movl_T0_reg(rd
);
1940 case 0x26: /* srl */
1942 gen_movl_T0_reg(rd
);
1944 case 0x27: /* sra */
1946 gen_movl_T0_reg(rd
);
1954 gen_op_movtl_env_T0(offsetof(CPUSPARCState
, y
));
1956 #ifndef TARGET_SPARC64
1957 case 0x01 ... 0x0f: /* undefined in the
1961 case 0x10 ... 0x1f: /* implementation-dependent
1967 case 0x2: /* V9 wrccr */
1970 case 0x3: /* V9 wrasi */
1971 gen_op_movl_env_T0(offsetof(CPUSPARCState
, asi
));
1973 case 0x6: /* V9 wrfprs */
1975 gen_op_movl_env_T0(offsetof(CPUSPARCState
, fprs
));
1982 case 0xf: /* V9 sir, nop if user */
1983 #if !defined(CONFIG_USER_ONLY)
1988 case 0x13: /* Graphics Status */
1989 if (gen_trap_ifnofpu(dc
))
1991 gen_op_movtl_env_T0(offsetof(CPUSPARCState
, gsr
));
1993 case 0x17: /* Tick compare */
1994 #if !defined(CONFIG_USER_ONLY)
1995 if (!supervisor(dc
))
1998 gen_op_movtl_env_T0(offsetof(CPUSPARCState
, tick_cmpr
));
1999 gen_op_wrtick_cmpr();
2001 case 0x18: /* System tick */
2002 #if !defined(CONFIG_USER_ONLY)
2003 if (!supervisor(dc
))
2008 case 0x19: /* System tick compare */
2009 #if !defined(CONFIG_USER_ONLY)
2010 if (!supervisor(dc
))
2013 gen_op_movtl_env_T0(offsetof(CPUSPARCState
, stick_cmpr
));
2014 gen_op_wrstick_cmpr();
2017 case 0x10: /* Performance Control */
2018 case 0x11: /* Performance Instrumentation Counter */
2019 case 0x12: /* Dispatch Control */
2020 case 0x14: /* Softint set */
2021 case 0x15: /* Softint clear */
2022 case 0x16: /* Softint write */
2029 #if !defined(CONFIG_USER_ONLY)
2030 case 0x31: /* wrpsr, V9 saved, restored */
2032 if (!supervisor(dc
))
2034 #ifdef TARGET_SPARC64
2042 case 2: /* UA2005 allclean */
2043 case 3: /* UA2005 otherw */
2044 case 4: /* UA2005 normalw */
2045 case 5: /* UA2005 invalw */
2061 case 0x32: /* wrwim, V9 wrpr */
2063 if (!supervisor(dc
))
2066 #ifdef TARGET_SPARC64
2084 gen_op_movtl_env_T0(offsetof(CPUSPARCState
, tbr
));
2095 gen_op_movl_env_T0(offsetof(CPUSPARCState
, tl
));
2098 gen_op_movl_env_T0(offsetof(CPUSPARCState
, psrpil
));
2104 gen_op_movl_env_T0(offsetof(CPUSPARCState
, cansave
));
2106 case 11: // canrestore
2107 gen_op_movl_env_T0(offsetof(CPUSPARCState
, canrestore
));
2109 case 12: // cleanwin
2110 gen_op_movl_env_T0(offsetof(CPUSPARCState
, cleanwin
));
2112 case 13: // otherwin
2113 gen_op_movl_env_T0(offsetof(CPUSPARCState
, otherwin
));
2116 gen_op_movl_env_T0(offsetof(CPUSPARCState
, wstate
));
2118 case 16: // UA2005 gl
2119 gen_op_movl_env_T0(offsetof(CPUSPARCState
, gl
));
2121 case 26: // UA2005 strand status
2122 if (!hypervisor(dc
))
2124 gen_op_movl_env_T0(offsetof(CPUSPARCState
, ssr
));
2134 case 0x33: /* wrtbr, UA2005 wrhpr */
2136 #ifndef TARGET_SPARC64
2137 if (!supervisor(dc
))
2140 gen_op_movtl_env_T0(offsetof(CPUSPARCState
, tbr
));
2142 if (!hypervisor(dc
))
2147 // XXX gen_op_wrhpstate();
2155 // XXX gen_op_wrhtstate();
2158 gen_op_movl_env_T0(offsetof(CPUSPARCState
, hintp
));
2161 gen_op_movl_env_T0(offsetof(CPUSPARCState
, htba
));
2163 case 31: // hstick_cmpr
2164 gen_op_movtl_env_T0(offsetof(CPUSPARCState
, hstick_cmpr
));
2165 gen_op_wrhstick_cmpr();
2167 case 6: // hver readonly
2175 #ifdef TARGET_SPARC64
2176 case 0x2c: /* V9 movcc */
2178 int cc
= GET_FIELD_SP(insn
, 11, 12);
2179 int cond
= GET_FIELD_SP(insn
, 14, 17);
2180 if (IS_IMM
) { /* immediate */
2181 rs2
= GET_FIELD_SPs(insn
, 0, 10);
2182 gen_movl_simm_T1(rs2
);
2185 rs2
= GET_FIELD_SP(insn
, 0, 4);
2186 gen_movl_reg_T1(rs2
);
2188 gen_movl_reg_T0(rd
);
2190 if (insn
& (1 << 18)) {
2192 gen_cond
[0][cond
]();
2194 gen_cond
[1][cond
]();
2198 gen_fcond
[cc
][cond
]();
2201 gen_movl_T0_reg(rd
);
2204 case 0x2d: /* V9 sdivx */
2205 gen_op_sdivx_T1_T0();
2206 gen_movl_T0_reg(rd
);
2208 case 0x2e: /* V9 popc */
2210 if (IS_IMM
) { /* immediate */
2211 rs2
= GET_FIELD_SPs(insn
, 0, 12);
2212 gen_movl_simm_T1(rs2
);
2213 // XXX optimize: popc(constant)
2216 rs2
= GET_FIELD_SP(insn
, 0, 4);
2217 gen_movl_reg_T1(rs2
);
2220 gen_movl_T0_reg(rd
);
2222 case 0x2f: /* V9 movr */
2224 int cond
= GET_FIELD_SP(insn
, 10, 12);
2225 rs1
= GET_FIELD(insn
, 13, 17);
2227 gen_movl_reg_T0(rs1
);
2229 if (IS_IMM
) { /* immediate */
2230 rs2
= GET_FIELD_SPs(insn
, 0, 9);
2231 gen_movl_simm_T1(rs2
);
2234 rs2
= GET_FIELD_SP(insn
, 0, 4);
2235 gen_movl_reg_T1(rs2
);
2237 gen_movl_reg_T0(rd
);
2239 gen_movl_T0_reg(rd
);
2247 } else if (xop
== 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
2248 #ifdef TARGET_SPARC64
2249 int opf
= GET_FIELD_SP(insn
, 5, 13);
2250 rs1
= GET_FIELD(insn
, 13, 17);
2251 rs2
= GET_FIELD(insn
, 27, 31);
2252 if (gen_trap_ifnofpu(dc
))
2256 case 0x000: /* VIS I edge8cc */
2257 case 0x001: /* VIS II edge8n */
2258 case 0x002: /* VIS I edge8lcc */
2259 case 0x003: /* VIS II edge8ln */
2260 case 0x004: /* VIS I edge16cc */
2261 case 0x005: /* VIS II edge16n */
2262 case 0x006: /* VIS I edge16lcc */
2263 case 0x007: /* VIS II edge16ln */
2264 case 0x008: /* VIS I edge32cc */
2265 case 0x009: /* VIS II edge32n */
2266 case 0x00a: /* VIS I edge32lcc */
2267 case 0x00b: /* VIS II edge32ln */
2270 case 0x010: /* VIS I array8 */
2271 gen_movl_reg_T0(rs1
);
2272 gen_movl_reg_T1(rs2
);
2274 gen_movl_T0_reg(rd
);
2276 case 0x012: /* VIS I array16 */
2277 gen_movl_reg_T0(rs1
);
2278 gen_movl_reg_T1(rs2
);
2280 gen_movl_T0_reg(rd
);
2282 case 0x014: /* VIS I array32 */
2283 gen_movl_reg_T0(rs1
);
2284 gen_movl_reg_T1(rs2
);
2286 gen_movl_T0_reg(rd
);
2288 case 0x018: /* VIS I alignaddr */
2289 gen_movl_reg_T0(rs1
);
2290 gen_movl_reg_T1(rs2
);
2292 gen_movl_T0_reg(rd
);
2294 case 0x019: /* VIS II bmask */
2295 case 0x01a: /* VIS I alignaddrl */
2298 case 0x020: /* VIS I fcmple16 */
2299 gen_op_load_fpr_DT0(rs1
);
2300 gen_op_load_fpr_DT1(rs2
);
2302 gen_op_store_DT0_fpr(rd
);
2304 case 0x022: /* VIS I fcmpne16 */
2305 gen_op_load_fpr_DT0(rs1
);
2306 gen_op_load_fpr_DT1(rs2
);
2308 gen_op_store_DT0_fpr(rd
);
2310 case 0x024: /* VIS I fcmple32 */
2311 gen_op_load_fpr_DT0(rs1
);
2312 gen_op_load_fpr_DT1(rs2
);
2314 gen_op_store_DT0_fpr(rd
);
2316 case 0x026: /* VIS I fcmpne32 */
2317 gen_op_load_fpr_DT0(rs1
);
2318 gen_op_load_fpr_DT1(rs2
);
2320 gen_op_store_DT0_fpr(rd
);
2322 case 0x028: /* VIS I fcmpgt16 */
2323 gen_op_load_fpr_DT0(rs1
);
2324 gen_op_load_fpr_DT1(rs2
);
2326 gen_op_store_DT0_fpr(rd
);
2328 case 0x02a: /* VIS I fcmpeq16 */
2329 gen_op_load_fpr_DT0(rs1
);
2330 gen_op_load_fpr_DT1(rs2
);
2332 gen_op_store_DT0_fpr(rd
);
2334 case 0x02c: /* VIS I fcmpgt32 */
2335 gen_op_load_fpr_DT0(rs1
);
2336 gen_op_load_fpr_DT1(rs2
);
2338 gen_op_store_DT0_fpr(rd
);
2340 case 0x02e: /* VIS I fcmpeq32 */
2341 gen_op_load_fpr_DT0(rs1
);
2342 gen_op_load_fpr_DT1(rs2
);
2344 gen_op_store_DT0_fpr(rd
);
2346 case 0x031: /* VIS I fmul8x16 */
2347 gen_op_load_fpr_DT0(rs1
);
2348 gen_op_load_fpr_DT1(rs2
);
2350 gen_op_store_DT0_fpr(rd
);
2352 case 0x033: /* VIS I fmul8x16au */
2353 gen_op_load_fpr_DT0(rs1
);
2354 gen_op_load_fpr_DT1(rs2
);
2355 gen_op_fmul8x16au();
2356 gen_op_store_DT0_fpr(rd
);
2358 case 0x035: /* VIS I fmul8x16al */
2359 gen_op_load_fpr_DT0(rs1
);
2360 gen_op_load_fpr_DT1(rs2
);
2361 gen_op_fmul8x16al();
2362 gen_op_store_DT0_fpr(rd
);
2364 case 0x036: /* VIS I fmul8sux16 */
2365 gen_op_load_fpr_DT0(rs1
);
2366 gen_op_load_fpr_DT1(rs2
);
2367 gen_op_fmul8sux16();
2368 gen_op_store_DT0_fpr(rd
);
2370 case 0x037: /* VIS I fmul8ulx16 */
2371 gen_op_load_fpr_DT0(rs1
);
2372 gen_op_load_fpr_DT1(rs2
);
2373 gen_op_fmul8ulx16();
2374 gen_op_store_DT0_fpr(rd
);
2376 case 0x038: /* VIS I fmuld8sux16 */
2377 gen_op_load_fpr_DT0(rs1
);
2378 gen_op_load_fpr_DT1(rs2
);
2379 gen_op_fmuld8sux16();
2380 gen_op_store_DT0_fpr(rd
);
2382 case 0x039: /* VIS I fmuld8ulx16 */
2383 gen_op_load_fpr_DT0(rs1
);
2384 gen_op_load_fpr_DT1(rs2
);
2385 gen_op_fmuld8ulx16();
2386 gen_op_store_DT0_fpr(rd
);
2388 case 0x03a: /* VIS I fpack32 */
2389 case 0x03b: /* VIS I fpack16 */
2390 case 0x03d: /* VIS I fpackfix */
2391 case 0x03e: /* VIS I pdist */
2394 case 0x048: /* VIS I faligndata */
2395 gen_op_load_fpr_DT0(rs1
);
2396 gen_op_load_fpr_DT1(rs2
);
2397 gen_op_faligndata();
2398 gen_op_store_DT0_fpr(rd
);
2400 case 0x04b: /* VIS I fpmerge */
2401 gen_op_load_fpr_DT0(rs1
);
2402 gen_op_load_fpr_DT1(rs2
);
2404 gen_op_store_DT0_fpr(rd
);
2406 case 0x04c: /* VIS II bshuffle */
2409 case 0x04d: /* VIS I fexpand */
2410 gen_op_load_fpr_DT0(rs1
);
2411 gen_op_load_fpr_DT1(rs2
);
2413 gen_op_store_DT0_fpr(rd
);
2415 case 0x050: /* VIS I fpadd16 */
2416 gen_op_load_fpr_DT0(rs1
);
2417 gen_op_load_fpr_DT1(rs2
);
2419 gen_op_store_DT0_fpr(rd
);
2421 case 0x051: /* VIS I fpadd16s */
2422 gen_op_load_fpr_FT0(rs1
);
2423 gen_op_load_fpr_FT1(rs2
);
2425 gen_op_store_FT0_fpr(rd
);
2427 case 0x052: /* VIS I fpadd32 */
2428 gen_op_load_fpr_DT0(rs1
);
2429 gen_op_load_fpr_DT1(rs2
);
2431 gen_op_store_DT0_fpr(rd
);
2433 case 0x053: /* VIS I fpadd32s */
2434 gen_op_load_fpr_FT0(rs1
);
2435 gen_op_load_fpr_FT1(rs2
);
2437 gen_op_store_FT0_fpr(rd
);
2439 case 0x054: /* VIS I fpsub16 */
2440 gen_op_load_fpr_DT0(rs1
);
2441 gen_op_load_fpr_DT1(rs2
);
2443 gen_op_store_DT0_fpr(rd
);
2445 case 0x055: /* VIS I fpsub16s */
2446 gen_op_load_fpr_FT0(rs1
);
2447 gen_op_load_fpr_FT1(rs2
);
2449 gen_op_store_FT0_fpr(rd
);
2451 case 0x056: /* VIS I fpsub32 */
2452 gen_op_load_fpr_DT0(rs1
);
2453 gen_op_load_fpr_DT1(rs2
);
2455 gen_op_store_DT0_fpr(rd
);
2457 case 0x057: /* VIS I fpsub32s */
2458 gen_op_load_fpr_FT0(rs1
);
2459 gen_op_load_fpr_FT1(rs2
);
2461 gen_op_store_FT0_fpr(rd
);
2463 case 0x060: /* VIS I fzero */
2464 gen_op_movl_DT0_0();
2465 gen_op_store_DT0_fpr(rd
);
2467 case 0x061: /* VIS I fzeros */
2468 gen_op_movl_FT0_0();
2469 gen_op_store_FT0_fpr(rd
);
2471 case 0x062: /* VIS I fnor */
2472 gen_op_load_fpr_DT0(rs1
);
2473 gen_op_load_fpr_DT1(rs2
);
2475 gen_op_store_DT0_fpr(rd
);
2477 case 0x063: /* VIS I fnors */
2478 gen_op_load_fpr_FT0(rs1
);
2479 gen_op_load_fpr_FT1(rs2
);
2481 gen_op_store_FT0_fpr(rd
);
2483 case 0x064: /* VIS I fandnot2 */
2484 gen_op_load_fpr_DT1(rs1
);
2485 gen_op_load_fpr_DT0(rs2
);
2487 gen_op_store_DT0_fpr(rd
);
2489 case 0x065: /* VIS I fandnot2s */
2490 gen_op_load_fpr_FT1(rs1
);
2491 gen_op_load_fpr_FT0(rs2
);
2493 gen_op_store_FT0_fpr(rd
);
2495 case 0x066: /* VIS I fnot2 */
2496 gen_op_load_fpr_DT1(rs2
);
2498 gen_op_store_DT0_fpr(rd
);
2500 case 0x067: /* VIS I fnot2s */
2501 gen_op_load_fpr_FT1(rs2
);
2503 gen_op_store_FT0_fpr(rd
);
2505 case 0x068: /* VIS I fandnot1 */
2506 gen_op_load_fpr_DT0(rs1
);
2507 gen_op_load_fpr_DT1(rs2
);
2509 gen_op_store_DT0_fpr(rd
);
2511 case 0x069: /* VIS I fandnot1s */
2512 gen_op_load_fpr_FT0(rs1
);
2513 gen_op_load_fpr_FT1(rs2
);
2515 gen_op_store_FT0_fpr(rd
);
2517 case 0x06a: /* VIS I fnot1 */
2518 gen_op_load_fpr_DT1(rs1
);
2520 gen_op_store_DT0_fpr(rd
);
2522 case 0x06b: /* VIS I fnot1s */
2523 gen_op_load_fpr_FT1(rs1
);
2525 gen_op_store_FT0_fpr(rd
);
2527 case 0x06c: /* VIS I fxor */
2528 gen_op_load_fpr_DT0(rs1
);
2529 gen_op_load_fpr_DT1(rs2
);
2531 gen_op_store_DT0_fpr(rd
);
2533 case 0x06d: /* VIS I fxors */
2534 gen_op_load_fpr_FT0(rs1
);
2535 gen_op_load_fpr_FT1(rs2
);
2537 gen_op_store_FT0_fpr(rd
);
2539 case 0x06e: /* VIS I fnand */
2540 gen_op_load_fpr_DT0(rs1
);
2541 gen_op_load_fpr_DT1(rs2
);
2543 gen_op_store_DT0_fpr(rd
);
2545 case 0x06f: /* VIS I fnands */
2546 gen_op_load_fpr_FT0(rs1
);
2547 gen_op_load_fpr_FT1(rs2
);
2549 gen_op_store_FT0_fpr(rd
);
2551 case 0x070: /* VIS I fand */
2552 gen_op_load_fpr_DT0(rs1
);
2553 gen_op_load_fpr_DT1(rs2
);
2555 gen_op_store_DT0_fpr(rd
);
2557 case 0x071: /* VIS I fands */
2558 gen_op_load_fpr_FT0(rs1
);
2559 gen_op_load_fpr_FT1(rs2
);
2561 gen_op_store_FT0_fpr(rd
);
2563 case 0x072: /* VIS I fxnor */
2564 gen_op_load_fpr_DT0(rs1
);
2565 gen_op_load_fpr_DT1(rs2
);
2567 gen_op_store_DT0_fpr(rd
);
2569 case 0x073: /* VIS I fxnors */
2570 gen_op_load_fpr_FT0(rs1
);
2571 gen_op_load_fpr_FT1(rs2
);
2573 gen_op_store_FT0_fpr(rd
);
2575 case 0x074: /* VIS I fsrc1 */
2576 gen_op_load_fpr_DT0(rs1
);
2577 gen_op_store_DT0_fpr(rd
);
2579 case 0x075: /* VIS I fsrc1s */
2580 gen_op_load_fpr_FT0(rs1
);
2581 gen_op_store_FT0_fpr(rd
);
2583 case 0x076: /* VIS I fornot2 */
2584 gen_op_load_fpr_DT1(rs1
);
2585 gen_op_load_fpr_DT0(rs2
);
2587 gen_op_store_DT0_fpr(rd
);
2589 case 0x077: /* VIS I fornot2s */
2590 gen_op_load_fpr_FT1(rs1
);
2591 gen_op_load_fpr_FT0(rs2
);
2593 gen_op_store_FT0_fpr(rd
);
2595 case 0x078: /* VIS I fsrc2 */
2596 gen_op_load_fpr_DT0(rs2
);
2597 gen_op_store_DT0_fpr(rd
);
2599 case 0x079: /* VIS I fsrc2s */
2600 gen_op_load_fpr_FT0(rs2
);
2601 gen_op_store_FT0_fpr(rd
);
2603 case 0x07a: /* VIS I fornot1 */
2604 gen_op_load_fpr_DT0(rs1
);
2605 gen_op_load_fpr_DT1(rs2
);
2607 gen_op_store_DT0_fpr(rd
);
2609 case 0x07b: /* VIS I fornot1s */
2610 gen_op_load_fpr_FT0(rs1
);
2611 gen_op_load_fpr_FT1(rs2
);
2613 gen_op_store_FT0_fpr(rd
);
2615 case 0x07c: /* VIS I for */
2616 gen_op_load_fpr_DT0(rs1
);
2617 gen_op_load_fpr_DT1(rs2
);
2619 gen_op_store_DT0_fpr(rd
);
2621 case 0x07d: /* VIS I fors */
2622 gen_op_load_fpr_FT0(rs1
);
2623 gen_op_load_fpr_FT1(rs2
);
2625 gen_op_store_FT0_fpr(rd
);
2627 case 0x07e: /* VIS I fone */
2628 gen_op_movl_DT0_1();
2629 gen_op_store_DT0_fpr(rd
);
2631 case 0x07f: /* VIS I fones */
2632 gen_op_movl_FT0_1();
2633 gen_op_store_FT0_fpr(rd
);
2635 case 0x080: /* VIS I shutdown */
2636 case 0x081: /* VIS II siam */
2645 } else if (xop
== 0x37) { /* V8 CPop2, V9 impdep2 */
2646 #ifdef TARGET_SPARC64
2651 #ifdef TARGET_SPARC64
2652 } else if (xop
== 0x39) { /* V9 return */
2653 rs1
= GET_FIELD(insn
, 13, 17);
2654 gen_movl_reg_T0(rs1
);
2655 if (IS_IMM
) { /* immediate */
2656 rs2
= GET_FIELDs(insn
, 19, 31);
2660 gen_movl_simm_T1(rs2
);
2665 } else { /* register */
2666 rs2
= GET_FIELD(insn
, 27, 31);
2670 gen_movl_reg_T1(rs2
);
2678 gen_op_movl_npc_T0();
2679 dc
->npc
= DYNAMIC_PC
;
2683 rs1
= GET_FIELD(insn
, 13, 17);
2684 gen_movl_reg_T0(rs1
);
2685 if (IS_IMM
) { /* immediate */
2686 rs2
= GET_FIELDs(insn
, 19, 31);
2690 gen_movl_simm_T1(rs2
);
2695 } else { /* register */
2696 rs2
= GET_FIELD(insn
, 27, 31);
2700 gen_movl_reg_T1(rs2
);
2707 case 0x38: /* jmpl */
2710 #ifdef TARGET_SPARC64
2711 if (dc
->pc
== (uint32_t)dc
->pc
) {
2712 gen_op_movl_T1_im(dc
->pc
);
2714 gen_op_movq_T1_im64(dc
->pc
>> 32, dc
->pc
);
2717 gen_op_movl_T1_im(dc
->pc
);
2719 gen_movl_T1_reg(rd
);
2722 gen_op_movl_npc_T0();
2723 dc
->npc
= DYNAMIC_PC
;
2726 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
2727 case 0x39: /* rett, V9 return */
2729 if (!supervisor(dc
))
2732 gen_op_movl_npc_T0();
2733 dc
->npc
= DYNAMIC_PC
;
2738 case 0x3b: /* flush */
2741 case 0x3c: /* save */
2744 gen_movl_T0_reg(rd
);
2746 case 0x3d: /* restore */
2749 gen_movl_T0_reg(rd
);
2751 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
2752 case 0x3e: /* V9 done/retry */
2756 if (!supervisor(dc
))
2758 dc
->npc
= DYNAMIC_PC
;
2759 dc
->pc
= DYNAMIC_PC
;
2763 if (!supervisor(dc
))
2765 dc
->npc
= DYNAMIC_PC
;
2766 dc
->pc
= DYNAMIC_PC
;
2782 case 3: /* load/store instructions */
2784 unsigned int xop
= GET_FIELD(insn
, 7, 12);
2785 rs1
= GET_FIELD(insn
, 13, 17);
2787 gen_movl_reg_T0(rs1
);
2788 if (IS_IMM
) { /* immediate */
2789 rs2
= GET_FIELDs(insn
, 19, 31);
2793 gen_movl_simm_T1(rs2
);
2798 } else { /* register */
2799 rs2
= GET_FIELD(insn
, 27, 31);
2803 gen_movl_reg_T1(rs2
);
2809 if (xop
< 4 || (xop
> 7 && xop
< 0x14 && xop
!= 0x0e) ||
2810 (xop
> 0x17 && xop
<= 0x1d ) ||
2811 (xop
> 0x2c && xop
<= 0x33) || xop
== 0x1f || xop
== 0x3d) {
2813 case 0x0: /* load word */
2814 #ifndef TARGET_SPARC64
2820 case 0x1: /* load unsigned byte */
2823 case 0x2: /* load unsigned halfword */
2826 case 0x3: /* load double word */
2830 gen_movl_T0_reg(rd
+ 1);
2832 case 0x9: /* load signed byte */
2835 case 0xa: /* load signed halfword */
2838 case 0xd: /* ldstub -- XXX: should be atomically */
2839 gen_op_ldst(ldstub
);
2841 case 0x0f: /* swap register with memory. Also atomically */
2842 gen_movl_reg_T1(rd
);
2845 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2846 case 0x10: /* load word alternate */
2847 #ifndef TARGET_SPARC64
2850 if (!supervisor(dc
))
2852 gen_op_lda(insn
, 1, 4, 0);
2854 gen_op_lduwa(insn
, 1, 4, 0);
2857 case 0x11: /* load unsigned byte alternate */
2858 #ifndef TARGET_SPARC64
2861 if (!supervisor(dc
))
2864 gen_op_lduba(insn
, 1, 1, 0);
2866 case 0x12: /* load unsigned halfword alternate */
2867 #ifndef TARGET_SPARC64
2870 if (!supervisor(dc
))
2873 gen_op_lduha(insn
, 1, 2, 0);
2875 case 0x13: /* load double word alternate */
2876 #ifndef TARGET_SPARC64
2879 if (!supervisor(dc
))
2884 gen_op_ldda(insn
, 1, 8, 0);
2885 gen_movl_T0_reg(rd
+ 1);
2887 case 0x19: /* load signed byte alternate */
2888 #ifndef TARGET_SPARC64
2891 if (!supervisor(dc
))
2894 gen_op_ldsba(insn
, 1, 1, 1);
2896 case 0x1a: /* load signed halfword alternate */
2897 #ifndef TARGET_SPARC64
2900 if (!supervisor(dc
))
2903 gen_op_ldsha(insn
, 1, 2 ,1);
2905 case 0x1d: /* ldstuba -- XXX: should be atomically */
2906 #ifndef TARGET_SPARC64
2909 if (!supervisor(dc
))
2912 gen_op_ldstuba(insn
, 1, 1, 0);
2914 case 0x1f: /* swap reg with alt. memory. Also atomically */
2915 #ifndef TARGET_SPARC64
2918 if (!supervisor(dc
))
2921 gen_movl_reg_T1(rd
);
2922 gen_op_swapa(insn
, 1, 4, 0);
2925 #ifndef TARGET_SPARC64
2926 case 0x30: /* ldc */
2927 case 0x31: /* ldcsr */
2928 case 0x33: /* lddc */
2930 /* avoid warnings */
2931 (void) &gen_op_stfa
;
2932 (void) &gen_op_stdfa
;
2933 (void) &gen_op_ldfa
;
2934 (void) &gen_op_lddfa
;
2937 #if !defined(CONFIG_USER_ONLY)
2939 (void) &gen_op_casx
;
2943 #ifdef TARGET_SPARC64
2944 case 0x08: /* V9 ldsw */
2947 case 0x0b: /* V9 ldx */
2950 case 0x18: /* V9 ldswa */
2951 gen_op_ldswa(insn
, 1, 4, 1);
2953 case 0x1b: /* V9 ldxa */
2954 gen_op_ldxa(insn
, 1, 8, 0);
2956 case 0x2d: /* V9 prefetch, no effect */
2958 case 0x30: /* V9 ldfa */
2959 gen_op_ldfa(insn
, 1, 8, 0); // XXX
2961 case 0x33: /* V9 lddfa */
2962 gen_op_lddfa(insn
, 1, 8, 0); // XXX
2965 case 0x3d: /* V9 prefetcha, no effect */
2967 case 0x32: /* V9 ldqfa */
2973 gen_movl_T1_reg(rd
);
2974 #ifdef TARGET_SPARC64
2977 } else if (xop
>= 0x20 && xop
< 0x24) {
2978 if (gen_trap_ifnofpu(dc
))
2981 case 0x20: /* load fpreg */
2983 gen_op_store_FT0_fpr(rd
);
2985 case 0x21: /* load fsr */
2989 case 0x22: /* load quad fpreg */
2991 case 0x23: /* load double fpreg */
2993 gen_op_store_DT0_fpr(DFPREG(rd
));
2998 } else if (xop
< 8 || (xop
>= 0x14 && xop
< 0x18) || \
2999 xop
== 0xe || xop
== 0x1e) {
3000 gen_movl_reg_T1(rd
);
3015 gen_movl_reg_T2(rd
+ 1);
3018 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
3020 #ifndef TARGET_SPARC64
3023 if (!supervisor(dc
))
3026 gen_op_sta(insn
, 0, 4, 0);
3029 #ifndef TARGET_SPARC64
3032 if (!supervisor(dc
))
3035 gen_op_stba(insn
, 0, 1, 0);
3038 #ifndef TARGET_SPARC64
3041 if (!supervisor(dc
))
3044 gen_op_stha(insn
, 0, 2, 0);
3047 #ifndef TARGET_SPARC64
3050 if (!supervisor(dc
))
3056 gen_movl_reg_T2(rd
+ 1);
3057 gen_op_stda(insn
, 0, 8, 0);
3060 #ifdef TARGET_SPARC64
3061 case 0x0e: /* V9 stx */
3064 case 0x1e: /* V9 stxa */
3065 gen_op_stxa(insn
, 0, 8, 0); // XXX
3071 } else if (xop
> 0x23 && xop
< 0x28) {
3072 if (gen_trap_ifnofpu(dc
))
3076 gen_op_load_fpr_FT0(rd
);
3079 case 0x25: /* stfsr, V9 stxfsr */
3083 #if !defined(CONFIG_USER_ONLY)
3084 case 0x26: /* stdfq */
3085 if (!supervisor(dc
))
3087 if (gen_trap_ifnofpu(dc
))
3092 gen_op_load_fpr_DT0(DFPREG(rd
));
3098 } else if (xop
> 0x33 && xop
< 0x3f) {
3100 #ifdef TARGET_SPARC64
3101 case 0x34: /* V9 stfa */
3102 gen_op_stfa(insn
, 0, 0, 0); // XXX
3104 case 0x37: /* V9 stdfa */
3105 gen_op_stdfa(insn
, 0, 0, 0); // XXX
3107 case 0x3c: /* V9 casa */
3108 gen_op_casa(insn
, 0, 4, 0); // XXX
3110 case 0x3e: /* V9 casxa */
3111 gen_op_casxa(insn
, 0, 8, 0); // XXX
3113 case 0x36: /* V9 stqfa */
3116 case 0x34: /* stc */
3117 case 0x35: /* stcsr */
3118 case 0x36: /* stdcq */
3119 case 0x37: /* stdc */
3131 /* default case for non jump instructions */
3132 if (dc
->npc
== DYNAMIC_PC
) {
3133 dc
->pc
= DYNAMIC_PC
;
3135 } else if (dc
->npc
== JUMP_PC
) {
3136 /* we can do a static jump */
3137 gen_branch2(dc
, dc
->jump_pc
[0], dc
->jump_pc
[1]);
3141 dc
->npc
= dc
->npc
+ 4;
3147 gen_op_exception(TT_ILL_INSN
);
3150 #if !defined(CONFIG_USER_ONLY)
3153 gen_op_exception(TT_PRIV_INSN
);
3159 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP
);
3162 #if !defined(CONFIG_USER_ONLY)
3165 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR
);
3169 #ifndef TARGET_SPARC64
3172 gen_op_exception(TT_NCP_INSN
);
3178 static inline int gen_intermediate_code_internal(TranslationBlock
* tb
,
3179 int spc
, CPUSPARCState
*env
)
3181 target_ulong pc_start
, last_pc
;
3182 uint16_t *gen_opc_end
;
3183 DisasContext dc1
, *dc
= &dc1
;
3186 memset(dc
, 0, sizeof(DisasContext
));
3191 dc
->npc
= (target_ulong
) tb
->cs_base
;
3192 #if defined(CONFIG_USER_ONLY)
3194 dc
->fpu_enabled
= 1;
3196 dc
->mem_idx
= ((env
->psrs
) != 0);
3197 #ifdef TARGET_SPARC64
3198 dc
->fpu_enabled
= (((env
->pstate
& PS_PEF
) != 0) && ((env
->fprs
& FPRS_FEF
) != 0));
3200 dc
->fpu_enabled
= ((env
->psref
) != 0);
3203 gen_opc_ptr
= gen_opc_buf
;
3204 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
3205 gen_opparam_ptr
= gen_opparam_buf
;
3209 if (env
->nb_breakpoints
> 0) {
3210 for(j
= 0; j
< env
->nb_breakpoints
; j
++) {
3211 if (env
->breakpoints
[j
] == dc
->pc
) {
3212 if (dc
->pc
!= pc_start
)
3224 fprintf(logfile
, "Search PC...\n");
3225 j
= gen_opc_ptr
- gen_opc_buf
;
3229 gen_opc_instr_start
[lj
++] = 0;
3230 gen_opc_pc
[lj
] = dc
->pc
;
3231 gen_opc_npc
[lj
] = dc
->npc
;
3232 gen_opc_instr_start
[lj
] = 1;
3236 disas_sparc_insn(dc
);
3240 /* if the next PC is different, we abort now */
3241 if (dc
->pc
!= (last_pc
+ 4))
3243 /* if we reach a page boundary, we stop generation so that the
3244 PC of a TT_TFAULT exception is always in the right page */
3245 if ((dc
->pc
& (TARGET_PAGE_SIZE
- 1)) == 0)
3247 /* if single step mode, we generate only one instruction and
3248 generate an exception */
3249 if (env
->singlestep_enabled
) {
3255 } while ((gen_opc_ptr
< gen_opc_end
) &&
3256 (dc
->pc
- pc_start
) < (TARGET_PAGE_SIZE
- 32));
3260 if (dc
->pc
!= DYNAMIC_PC
&&
3261 (dc
->npc
!= DYNAMIC_PC
&& dc
->npc
!= JUMP_PC
)) {
3262 /* static PC and NPC: we can use direct chaining */
3263 gen_branch(dc
, dc
->pc
, dc
->npc
);
3265 if (dc
->pc
!= DYNAMIC_PC
)
3272 *gen_opc_ptr
= INDEX_op_end
;
3274 j
= gen_opc_ptr
- gen_opc_buf
;
3277 gen_opc_instr_start
[lj
++] = 0;
3284 gen_opc_jump_pc
[0] = dc
->jump_pc
[0];
3285 gen_opc_jump_pc
[1] = dc
->jump_pc
[1];
3287 tb
->size
= last_pc
+ 4 - pc_start
;
3290 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3291 fprintf(logfile
, "--------------\n");
3292 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
3293 target_disas(logfile
, pc_start
, last_pc
+ 4 - pc_start
, 0);
3294 fprintf(logfile
, "\n");
3295 if (loglevel
& CPU_LOG_TB_OP
) {
3296 fprintf(logfile
, "OP:\n");
3297 dump_ops(gen_opc_buf
, gen_opparam_buf
);
3298 fprintf(logfile
, "\n");
3305 int gen_intermediate_code(CPUSPARCState
* env
, TranslationBlock
* tb
)
3307 return gen_intermediate_code_internal(tb
, 0, env
);
3310 int gen_intermediate_code_pc(CPUSPARCState
* env
, TranslationBlock
* tb
)
3312 return gen_intermediate_code_internal(tb
, 1, env
);
3315 extern int ram_size
;
3317 void cpu_reset(CPUSPARCState
*env
)
3322 env
->regwptr
= env
->regbase
+ (env
->cwp
* 16);
3323 #if defined(CONFIG_USER_ONLY)
3324 env
->user_mode_only
= 1;
3325 #ifdef TARGET_SPARC64
3326 env
->cleanwin
= NWINDOWS
- 2;
3327 env
->cansave
= NWINDOWS
- 2;
3328 env
->pstate
= PS_RMO
| PS_PEF
| PS_IE
;
3329 env
->asi
= 0x82; // Primary no-fault
3335 #ifdef TARGET_SPARC64
3336 env
->pstate
= PS_PRIV
;
3337 env
->pc
= 0x1fff0000000ULL
;
3339 env
->pc
= 0xffd00000;
3340 env
->mmuregs
[0] &= ~(MMU_E
| MMU_NF
);
3342 env
->npc
= env
->pc
+ 4;
3346 CPUSPARCState
*cpu_sparc_init(void)
3350 env
= qemu_mallocz(sizeof(CPUSPARCState
));
3358 static const sparc_def_t sparc_defs
[] = {
3359 #ifdef TARGET_SPARC64
3361 .name
= "TI UltraSparc II",
3362 .iu_version
= ((0x17ULL
<< 48) | (0x11ULL
<< 32) | (0 << 24)
3363 | (MAXTL
<< 8) | (NWINDOWS
- 1)),
3364 .fpu_version
= 0x00000000,
3369 .name
= "Fujitsu MB86904",
3370 .iu_version
= 0x04 << 24, /* Impl 0, ver 4 */
3371 .fpu_version
= 4 << 17, /* FPU version 4 (Meiko) */
3372 .mmu_version
= 0x04 << 24, /* Impl 0, ver 4 */
3375 .name
= "Fujitsu MB86907",
3376 .iu_version
= 0x05 << 24, /* Impl 0, ver 5 */
3377 .fpu_version
= 4 << 17, /* FPU version 4 (Meiko) */
3378 .mmu_version
= 0x05 << 24, /* Impl 0, ver 5 */
3381 .name
= "TI MicroSparc I",
3382 .iu_version
= 0x41000000,
3383 .fpu_version
= 4 << 17,
3384 .mmu_version
= 0x41000000,
3387 .name
= "TI SuperSparc II",
3388 .iu_version
= 0x40000000,
3389 .fpu_version
= 0 << 17,
3390 .mmu_version
= 0x04000000,
3393 .name
= "Ross RT620",
3394 .iu_version
= 0x1e000000,
3395 .fpu_version
= 1 << 17,
3396 .mmu_version
= 0x17000000,
3401 int sparc_find_by_name(const unsigned char *name
, const sparc_def_t
**def
)
3408 for (i
= 0; i
< sizeof(sparc_defs
) / sizeof(sparc_def_t
); i
++) {
3409 if (strcasecmp(name
, sparc_defs
[i
].name
) == 0) {
3410 *def
= &sparc_defs
[i
];
3419 void sparc_cpu_list (FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...))
3423 for (i
= 0; i
< sizeof(sparc_defs
) / sizeof(sparc_def_t
); i
++) {
3424 (*cpu_fprintf
)(f
, "Sparc %16s IU " TARGET_FMT_lx
" FPU %08x MMU %08x\n",
3426 sparc_defs
[i
].iu_version
,
3427 sparc_defs
[i
].fpu_version
,
3428 sparc_defs
[i
].mmu_version
);
3432 int cpu_sparc_register (CPUSPARCState
*env
, const sparc_def_t
*def
)
3434 env
->version
= def
->iu_version
;
3435 env
->fsr
= def
->fpu_version
;
3436 #if !defined(TARGET_SPARC64)
3437 env
->mmuregs
[0] = def
->mmu_version
;
3442 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
3444 void cpu_dump_state(CPUState
*env
, FILE *f
,
3445 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
3450 cpu_fprintf(f
, "pc: " TARGET_FMT_lx
" npc: " TARGET_FMT_lx
"\n", env
->pc
, env
->npc
);
3451 cpu_fprintf(f
, "General Registers:\n");
3452 for (i
= 0; i
< 4; i
++)
3453 cpu_fprintf(f
, "%%g%c: " TARGET_FMT_lx
"\t", i
+ '0', env
->gregs
[i
]);
3454 cpu_fprintf(f
, "\n");
3456 cpu_fprintf(f
, "%%g%c: " TARGET_FMT_lx
"\t", i
+ '0', env
->gregs
[i
]);
3457 cpu_fprintf(f
, "\nCurrent Register Window:\n");
3458 for (x
= 0; x
< 3; x
++) {
3459 for (i
= 0; i
< 4; i
++)
3460 cpu_fprintf(f
, "%%%c%d: " TARGET_FMT_lx
"\t",
3461 (x
== 0 ? 'o' : (x
== 1 ? 'l' : 'i')), i
,
3462 env
->regwptr
[i
+ x
* 8]);
3463 cpu_fprintf(f
, "\n");
3465 cpu_fprintf(f
, "%%%c%d: " TARGET_FMT_lx
"\t",
3466 (x
== 0 ? 'o' : x
== 1 ? 'l' : 'i'), i
,
3467 env
->regwptr
[i
+ x
* 8]);
3468 cpu_fprintf(f
, "\n");
3470 cpu_fprintf(f
, "\nFloating Point Registers:\n");
3471 for (i
= 0; i
< 32; i
++) {
3473 cpu_fprintf(f
, "%%f%02d:", i
);
3474 cpu_fprintf(f
, " %016lf", env
->fpr
[i
]);
3476 cpu_fprintf(f
, "\n");
3478 #ifdef TARGET_SPARC64
3479 cpu_fprintf(f
, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
3480 env
->pstate
, GET_CCR(env
), env
->asi
, env
->tl
, env
->fprs
);
3481 cpu_fprintf(f
, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
3482 env
->cansave
, env
->canrestore
, env
->otherwin
, env
->wstate
,
3483 env
->cleanwin
, NWINDOWS
- 1 - env
->cwp
);
3485 cpu_fprintf(f
, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env
),
3486 GET_FLAG(PSR_ZERO
, 'Z'), GET_FLAG(PSR_OVF
, 'V'),
3487 GET_FLAG(PSR_NEG
, 'N'), GET_FLAG(PSR_CARRY
, 'C'),
3488 env
->psrs
?'S':'-', env
->psrps
?'P':'-',
3489 env
->psret
?'E':'-', env
->wim
);
3491 cpu_fprintf(f
, "fsr: 0x%08x\n", GET_FSR32(env
));
3494 #if defined(CONFIG_USER_ONLY)
3495 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
3501 extern int get_physical_address (CPUState
*env
, target_phys_addr_t
*physical
, int *prot
,
3502 int *access_index
, target_ulong address
, int rw
,
3505 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
3507 target_phys_addr_t phys_addr
;
3508 int prot
, access_index
;
3510 if (get_physical_address(env
, &phys_addr
, &prot
, &access_index
, addr
, 2, 0) != 0)
3511 if (get_physical_address(env
, &phys_addr
, &prot
, &access_index
, addr
, 0, 0) != 0)
3513 if (cpu_get_physical_page_desc(phys_addr
) == IO_MEM_UNASSIGNED
)
3519 void helper_flush(target_ulong addr
)
3522 tb_invalidate_page_range(addr
, addr
+ 8);