4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003 Fabrice Bellard
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 NPC/PC static optimisations (use JUMP_TB when possible)
27 Privileged instructions
28 Coprocessor-Instructions
29 Optimize synthetic instructions
30 Optional alignment and privileged instruction check
45 #define DYNAMIC_PC 1 /* dynamic pc value */
46 #define JUMP_PC 2 /* dynamic pc value which takes only two values
47 according to jump_pc[T2] */
49 typedef struct DisasContext
{
50 target_ulong pc
; /* current Program Counter: integer or DYNAMIC_PC */
51 target_ulong npc
; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
52 target_ulong jump_pc
[2]; /* used when JUMP_PC pc value is used */
55 struct TranslationBlock
*tb
;
58 static uint16_t *gen_opc_ptr
;
59 static uint32_t *gen_opparam_ptr
;
64 #define DEF(s,n,copy_size) INDEX_op_ ## s,
72 #define GET_FIELD(X, FROM, TO) \
73 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
75 #define IS_IMM (insn & (1<<13))
77 static void disas_sparc_insn(DisasContext
* dc
);
79 static GenOpFunc
*gen_op_movl_TN_reg
[2][32] = {
150 static GenOpFunc
*gen_op_movl_reg_TN
[3][32] = {
255 static GenOpFunc1
*gen_op_movl_TN_im
[3] = {
261 #define GEN32(func, NAME) \
262 static GenOpFunc *NAME ## _table [32] = { \
263 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
264 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
265 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
266 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
267 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
268 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
269 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
270 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
272 static inline void func(int n) \
274 NAME ## _table[n](); \
277 /* floating point registers moves */
278 GEN32(gen_op_load_fpr_FT0
, gen_op_load_fpr_FT0_fprf
);
279 GEN32(gen_op_load_fpr_FT1
, gen_op_load_fpr_FT1_fprf
);
280 GEN32(gen_op_load_fpr_FT2
, gen_op_load_fpr_FT2_fprf
);
281 GEN32(gen_op_store_FT0_fpr
, gen_op_store_FT0_fpr_fprf
);
282 GEN32(gen_op_store_FT1_fpr
, gen_op_store_FT1_fpr_fprf
);
283 GEN32(gen_op_store_FT2_fpr
, gen_op_store_FT2_fpr_fprf
);
285 GEN32(gen_op_load_fpr_DT0
, gen_op_load_fpr_DT0_fprf
);
286 GEN32(gen_op_load_fpr_DT1
, gen_op_load_fpr_DT1_fprf
);
287 GEN32(gen_op_load_fpr_DT2
, gen_op_load_fpr_DT2_fprf
);
288 GEN32(gen_op_store_DT0_fpr
, gen_op_store_DT0_fpr_fprf
);
289 GEN32(gen_op_store_DT1_fpr
, gen_op_store_DT1_fpr_fprf
);
290 GEN32(gen_op_store_DT2_fpr
, gen_op_store_DT2_fpr_fprf
);
292 #if defined(CONFIG_USER_ONLY)
293 #define gen_op_ldst(name) gen_op_##name##_raw()
294 #define OP_LD_TABLE(width)
295 #define supervisor(dc) 0
297 #define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
298 #define OP_LD_TABLE(width) \
299 static GenOpFunc *gen_op_##width[] = { \
300 &gen_op_##width##_user, \
301 &gen_op_##width##_kernel, \
304 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
308 asi = GET_FIELD(insn, 19, 26); \
310 case 10: /* User data access */ \
311 gen_op_##width##_user(); \
313 case 11: /* Supervisor data access */ \
314 gen_op_##width##_kernel(); \
316 case 0x20 ... 0x2f: /* MMU passthrough */ \
318 gen_op_ld_asi(asi, size, sign); \
320 gen_op_st_asi(asi, size, sign); \
324 gen_op_ld_asi(asi, size, sign); \
326 gen_op_st_asi(asi, size, sign); \
331 #define supervisor(dc) (dc->mem_idx == 1)
351 static inline void gen_movl_imm_TN(int reg
, int imm
)
353 gen_op_movl_TN_im
[reg
] (imm
);
356 static inline void gen_movl_imm_T1(int val
)
358 gen_movl_imm_TN(1, val
);
361 static inline void gen_movl_imm_T0(int val
)
363 gen_movl_imm_TN(0, val
);
366 static inline void gen_movl_reg_TN(int reg
, int t
)
369 gen_op_movl_reg_TN
[t
][reg
] ();
371 gen_movl_imm_TN(t
, 0);
374 static inline void gen_movl_reg_T0(int reg
)
376 gen_movl_reg_TN(reg
, 0);
379 static inline void gen_movl_reg_T1(int reg
)
381 gen_movl_reg_TN(reg
, 1);
384 static inline void gen_movl_reg_T2(int reg
)
386 gen_movl_reg_TN(reg
, 2);
389 static inline void gen_movl_TN_reg(int reg
, int t
)
392 gen_op_movl_TN_reg
[t
][reg
] ();
395 static inline void gen_movl_T0_reg(int reg
)
397 gen_movl_TN_reg(reg
, 0);
400 static inline void gen_movl_T1_reg(int reg
)
402 gen_movl_TN_reg(reg
, 1);
405 /* call this function before using T2 as it may have been set for a jump */
406 static inline void flush_T2(DisasContext
* dc
)
408 if (dc
->npc
== JUMP_PC
) {
409 gen_op_generic_branch(dc
->jump_pc
[0], dc
->jump_pc
[1]);
410 dc
->npc
= DYNAMIC_PC
;
414 static inline void save_npc(DisasContext
* dc
)
416 if (dc
->npc
== JUMP_PC
) {
417 gen_op_generic_branch(dc
->jump_pc
[0], dc
->jump_pc
[1]);
418 dc
->npc
= DYNAMIC_PC
;
419 } else if (dc
->npc
!= DYNAMIC_PC
) {
420 gen_op_movl_npc_im(dc
->npc
);
424 static inline void save_state(DisasContext
* dc
)
426 gen_op_jmp_im((uint32_t)dc
->pc
);
430 static void gen_cond(int cond
)
485 static void gen_fcond(int cond
)
540 static void do_branch(DisasContext
* dc
, uint32_t target
, uint32_t insn
)
542 unsigned int cond
= GET_FIELD(insn
, 3, 6), a
= (insn
& (1 << 29));
543 target
+= (uint32_t) dc
->pc
;
545 /* unconditional not taken */
547 dc
->pc
= dc
->npc
+ 4;
548 dc
->npc
= dc
->pc
+ 4;
551 dc
->npc
= dc
->pc
+ 4;
553 } else if (cond
== 0x8) {
554 /* unconditional taken */
557 dc
->npc
= dc
->pc
+ 4;
566 gen_op_branch_a((long)dc
->tb
, target
, dc
->npc
);
570 dc
->jump_pc
[0] = target
;
571 dc
->jump_pc
[1] = dc
->npc
+ 4;
577 static void do_fbranch(DisasContext
* dc
, uint32_t target
, uint32_t insn
)
579 unsigned int cond
= GET_FIELD(insn
, 3, 6), a
= (insn
& (1 << 29));
580 target
+= (uint32_t) dc
->pc
;
582 /* unconditional not taken */
584 dc
->pc
= dc
->npc
+ 4;
585 dc
->npc
= dc
->pc
+ 4;
588 dc
->npc
= dc
->pc
+ 4;
590 } else if (cond
== 0x8) {
591 /* unconditional taken */
594 dc
->npc
= dc
->pc
+ 4;
603 gen_op_branch_a((long)dc
->tb
, target
, dc
->npc
);
607 dc
->jump_pc
[0] = target
;
608 dc
->jump_pc
[1] = dc
->npc
+ 4;
614 static void gen_debug(DisasContext
*s
, uint32_t pc
)
621 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
623 static int sign_extend(int x
, int len
)
626 return (x
<< len
) >> len
;
629 static void disas_sparc_insn(DisasContext
* dc
)
631 unsigned int insn
, opc
, rs1
, rs2
, rd
;
633 insn
= ldl_code((uint8_t *)dc
->pc
);
634 opc
= GET_FIELD(insn
, 0, 1);
636 rd
= GET_FIELD(insn
, 2, 6);
638 case 0: /* branches/sethi */
640 unsigned int xop
= GET_FIELD(insn
, 7, 9);
642 target
= GET_FIELD(insn
, 10, 31);
645 case 0x1: /* UNIMPL */
651 target
= sign_extend(target
, 22);
652 do_branch(dc
, target
, insn
);
655 case 0x6: /* FBN+x */
658 target
= sign_extend(target
, 22);
659 do_fbranch(dc
, target
, insn
);
662 case 0x4: /* SETHI */
663 gen_movl_imm_T0(target
<< 10);
673 unsigned int target
= GET_FIELDs(insn
, 2, 31) << 2;
675 gen_op_movl_T0_im((long) (dc
->pc
));
677 target
= dc
->pc
+ target
;
682 case 2: /* FPU & Logical Operations */
684 unsigned int xop
= GET_FIELD(insn
, 7, 12);
685 if (xop
== 0x3a) { /* generate trap */
687 rs1
= GET_FIELD(insn
, 13, 17);
688 gen_movl_reg_T0(rs1
);
690 rs2
= GET_FIELD(insn
, 25, 31);
692 gen_movl_imm_T1(rs2
);
696 rs2
= GET_FIELD(insn
, 27, 31);
697 gen_movl_reg_T1(rs2
);
701 cond
= GET_FIELD(insn
, 3, 6);
709 } else if (xop
== 0x28) {
710 rs1
= GET_FIELD(insn
, 13, 17);
717 break; /* no effect? */
721 #if !defined(CONFIG_USER_ONLY)
722 } else if (xop
== 0x29) {
728 } else if (xop
== 0x2a) {
734 } else if (xop
== 0x2b) {
741 } else if (xop
== 0x34 || xop
== 0x35) { /* FPU Operations */
742 rs1
= GET_FIELD(insn
, 13, 17);
743 rs2
= GET_FIELD(insn
, 27, 31);
744 xop
= GET_FIELD(insn
, 18, 26);
746 case 0x1: /* fmovs */
747 gen_op_load_fpr_FT0(rs2
);
748 gen_op_store_FT0_fpr(rd
);
750 case 0x5: /* fnegs */
751 gen_op_load_fpr_FT1(rs2
);
753 gen_op_store_FT0_fpr(rd
);
755 case 0x9: /* fabss */
756 gen_op_load_fpr_FT1(rs2
);
758 gen_op_store_FT0_fpr(rd
);
760 case 0x29: /* fsqrts */
761 gen_op_load_fpr_FT1(rs2
);
763 gen_op_store_FT0_fpr(rd
);
765 case 0x2a: /* fsqrtd */
766 gen_op_load_fpr_DT1(rs2
);
768 gen_op_store_DT0_fpr(rd
);
771 gen_op_load_fpr_FT0(rs1
);
772 gen_op_load_fpr_FT1(rs2
);
774 gen_op_store_FT0_fpr(rd
);
777 gen_op_load_fpr_DT0(rs1
);
778 gen_op_load_fpr_DT1(rs2
);
780 gen_op_store_DT0_fpr(rd
);
783 gen_op_load_fpr_FT0(rs1
);
784 gen_op_load_fpr_FT1(rs2
);
786 gen_op_store_FT0_fpr(rd
);
789 gen_op_load_fpr_DT0(rs1
);
790 gen_op_load_fpr_DT1(rs2
);
792 gen_op_store_DT0_fpr(rd
);
795 gen_op_load_fpr_FT0(rs1
);
796 gen_op_load_fpr_FT1(rs2
);
798 gen_op_store_FT0_fpr(rd
);
801 gen_op_load_fpr_DT0(rs1
);
802 gen_op_load_fpr_DT1(rs2
);
804 gen_op_store_DT0_fpr(rd
);
807 gen_op_load_fpr_FT0(rs1
);
808 gen_op_load_fpr_FT1(rs2
);
810 gen_op_store_FT0_fpr(rd
);
813 gen_op_load_fpr_DT0(rs1
);
814 gen_op_load_fpr_DT1(rs2
);
816 gen_op_store_DT0_fpr(rd
);
819 gen_op_load_fpr_FT0(rs1
);
820 gen_op_load_fpr_FT1(rs2
);
824 gen_op_load_fpr_DT0(rs1
);
825 gen_op_load_fpr_DT1(rs2
);
828 case 0x55: /* fcmpes */
829 gen_op_load_fpr_FT0(rs1
);
830 gen_op_load_fpr_FT1(rs2
);
831 gen_op_fcmps(); /* XXX */
833 case 0x56: /* fcmped */
834 gen_op_load_fpr_DT0(rs1
);
835 gen_op_load_fpr_DT1(rs2
);
836 gen_op_fcmpd(); /* XXX */
839 gen_op_load_fpr_FT0(rs1
);
840 gen_op_load_fpr_FT1(rs2
);
842 gen_op_store_DT0_fpr(rd
);
845 gen_op_load_fpr_FT1(rs2
);
847 gen_op_store_FT0_fpr(rd
);
850 gen_op_load_fpr_DT1(rs2
);
852 gen_op_store_FT0_fpr(rd
);
855 gen_op_load_fpr_FT1(rs2
);
857 gen_op_store_DT0_fpr(rd
);
860 gen_op_load_fpr_FT1(rs2
);
862 gen_op_store_DT0_fpr(rd
);
865 gen_op_load_fpr_FT1(rs2
);
867 gen_op_store_FT0_fpr(rd
);
870 gen_op_load_fpr_DT1(rs2
);
872 gen_op_store_FT0_fpr(rd
);
878 rs1
= GET_FIELD(insn
, 13, 17);
879 gen_movl_reg_T0(rs1
);
880 if (IS_IMM
) { /* immediate */
881 rs2
= GET_FIELDs(insn
, 19, 31);
882 gen_movl_imm_T1(rs2
);
883 } else { /* register */
884 rs2
= GET_FIELD(insn
, 27, 31);
885 gen_movl_reg_T1(rs2
);
888 switch (xop
& ~0x10) {
891 gen_op_add_T1_T0_cc();
898 gen_op_logic_T0_cc();
903 gen_op_logic_T0_cc();
908 gen_op_logic_T0_cc();
912 gen_op_sub_T1_T0_cc();
919 gen_op_logic_T0_cc();
924 gen_op_logic_T0_cc();
929 gen_op_logic_T0_cc();
939 gen_op_logic_T0_cc();
944 gen_op_logic_T0_cc();
967 case 0x24: /* mulscc */
968 gen_op_mulscc_T1_T0();
995 #if !defined(CONFIG_USER_ONLY)
1006 if (!supervisor(dc
))
1014 if (!supervisor(dc
))
1021 case 0x38: /* jmpl */
1024 gen_op_movl_npc_T0();
1026 gen_op_movl_T0_im((long) (dc
->pc
));
1027 gen_movl_T0_reg(rd
);
1030 dc
->npc
= DYNAMIC_PC
;
1033 #if !defined(CONFIG_USER_ONLY)
1034 case 0x39: /* rett */
1036 if (!supervisor(dc
))
1039 gen_op_movl_npc_T0();
1043 dc
->npc
= DYNAMIC_PC
;
1051 case 0x3b: /* flush */
1055 case 0x3c: /* save */
1059 gen_movl_T0_reg(rd
);
1061 case 0x3d: /* restore */
1065 gen_movl_T0_reg(rd
);
1074 case 3: /* load/store instructions */
1076 unsigned int xop
= GET_FIELD(insn
, 7, 12);
1077 rs1
= GET_FIELD(insn
, 13, 17);
1078 gen_movl_reg_T0(rs1
);
1079 if (IS_IMM
) { /* immediate */
1080 rs2
= GET_FIELDs(insn
, 19, 31);
1082 gen_movl_imm_T1(rs2
);
1085 } else { /* register */
1086 rs2
= GET_FIELD(insn
, 27, 31);
1087 gen_movl_reg_T1(rs2
);
1090 if (xop
< 4 || (xop
> 7 && xop
< 0x14) || \
1091 (xop
> 0x17 && xop
< 0x20)) {
1093 case 0x0: /* load word */
1096 case 0x1: /* load unsigned byte */
1099 case 0x2: /* load unsigned halfword */
1102 case 0x3: /* load double word */
1104 gen_movl_T0_reg(rd
+ 1);
1106 case 0x9: /* load signed byte */
1109 case 0xa: /* load signed halfword */
1112 case 0xd: /* ldstub -- XXX: should be atomically */
1113 gen_op_ldst(ldstub
);
1115 case 0x0f: /* swap register with memory. Also atomically */
1118 case 0x10: /* load word alternate */
1119 if (!supervisor(dc
))
1121 gen_op_lda(insn
, 1, 4, 0);
1123 case 0x11: /* load unsigned byte alternate */
1124 if (!supervisor(dc
))
1126 gen_op_lduba(insn
, 1, 1, 0);
1128 case 0x12: /* load unsigned halfword alternate */
1129 if (!supervisor(dc
))
1131 gen_op_lduha(insn
, 1, 2, 0);
1133 case 0x13: /* load double word alternate */
1134 if (!supervisor(dc
))
1136 gen_op_ldda(insn
, 1, 8, 0);
1137 gen_movl_T0_reg(rd
+ 1);
1139 case 0x19: /* load signed byte alternate */
1140 if (!supervisor(dc
))
1142 gen_op_ldsba(insn
, 1, 1, 1);
1144 case 0x1a: /* load signed halfword alternate */
1145 if (!supervisor(dc
))
1147 gen_op_ldsha(insn
, 1, 2 ,1);
1149 case 0x1d: /* ldstuba -- XXX: should be atomically */
1150 if (!supervisor(dc
))
1152 gen_op_ldstuba(insn
, 1, 1, 0);
1154 case 0x1f: /* swap reg with alt. memory. Also atomically */
1155 if (!supervisor(dc
))
1157 gen_op_swapa(insn
, 1, 4, 0);
1160 gen_movl_T1_reg(rd
);
1161 } else if (xop
>= 0x20 && xop
< 0x24) {
1163 case 0x20: /* load fpreg */
1165 gen_op_store_FT0_fpr(rd
);
1167 case 0x21: /* load fsr */
1170 case 0x23: /* load double fpreg */
1172 gen_op_store_DT0_fpr(rd
);
1175 } else if (xop
< 8 || (xop
>= 0x14 && xop
< 0x18)) {
1176 gen_movl_reg_T1(rd
);
1189 gen_movl_reg_T2(rd
+ 1);
1193 if (!supervisor(dc
))
1195 gen_op_sta(insn
, 0, 4, 0);
1198 if (!supervisor(dc
))
1200 gen_op_stba(insn
, 0, 1, 0);
1203 if (!supervisor(dc
))
1205 gen_op_stha(insn
, 0, 2, 0);
1208 if (!supervisor(dc
))
1211 gen_movl_reg_T2(rd
+ 1);
1212 gen_op_stda(insn
, 0, 8, 0);
1215 } else if (xop
> 0x23 && xop
< 0x28) {
1218 gen_op_load_fpr_FT0(rd
);
1225 gen_op_load_fpr_DT0(rd
);
1229 } else if (xop
> 0x33 && xop
< 0x38) {
1234 /* default case for non jump instructions */
1235 if (dc
->npc
== DYNAMIC_PC
) {
1236 dc
->pc
= DYNAMIC_PC
;
1238 } else if (dc
->npc
== JUMP_PC
) {
1239 /* we can do a static jump */
1240 gen_op_branch2((long)dc
->tb
, dc
->jump_pc
[0], dc
->jump_pc
[1]);
1244 dc
->npc
= dc
->npc
+ 4;
1250 gen_op_exception(TT_ILL_INSN
);
1255 gen_op_exception(TT_PRIV_INSN
);
1259 static inline int gen_intermediate_code_internal(TranslationBlock
* tb
,
1260 int spc
, CPUSPARCState
*env
)
1262 target_ulong pc_start
, last_pc
;
1263 uint16_t *gen_opc_end
;
1264 DisasContext dc1
, *dc
= &dc1
;
1267 memset(dc
, 0, sizeof(DisasContext
));
1271 dc
->npc
= (target_ulong
) tb
->cs_base
;
1272 #if defined(CONFIG_USER_ONLY)
1275 dc
->mem_idx
= ((env
->psrs
) != 0);
1277 gen_opc_ptr
= gen_opc_buf
;
1278 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
1279 gen_opparam_ptr
= gen_opparam_buf
;
1282 if (env
->nb_breakpoints
> 0) {
1283 for(j
= 0; j
< env
->nb_breakpoints
; j
++) {
1284 if (env
->breakpoints
[j
] == dc
->pc
) {
1285 gen_debug(dc
, dc
->pc
);
1292 fprintf(logfile
, "Search PC...\n");
1293 j
= gen_opc_ptr
- gen_opc_buf
;
1297 gen_opc_instr_start
[lj
++] = 0;
1298 gen_opc_pc
[lj
] = dc
->pc
;
1299 gen_opc_npc
[lj
] = dc
->npc
;
1300 gen_opc_instr_start
[lj
] = 1;
1304 disas_sparc_insn(dc
);
1307 /* if the next PC is different, we abort now */
1308 if (dc
->pc
!= (last_pc
+ 4))
1310 } while ((gen_opc_ptr
< gen_opc_end
) &&
1311 (dc
->pc
- pc_start
) < (TARGET_PAGE_SIZE
- 32));
1313 if (dc
->pc
!= DYNAMIC_PC
&&
1314 (dc
->npc
!= DYNAMIC_PC
&& dc
->npc
!= JUMP_PC
)) {
1315 /* static PC and NPC: we can use direct chaining */
1316 gen_op_branch((long)tb
, dc
->pc
, dc
->npc
);
1318 if (dc
->pc
!= DYNAMIC_PC
)
1319 gen_op_jmp_im(dc
->pc
);
1325 *gen_opc_ptr
= INDEX_op_end
;
1327 j
= gen_opc_ptr
- gen_opc_buf
;
1330 gen_opc_instr_start
[lj
++] = 0;
1338 tb
->size
= dc
->npc
- pc_start
;
1341 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
1342 fprintf(logfile
, "--------------\n");
1343 fprintf(logfile
, "IN: %s\n", lookup_symbol((uint8_t *)pc_start
));
1344 disas(logfile
, (uint8_t *)pc_start
, last_pc
+ 4 - pc_start
, 0, 0);
1345 fprintf(logfile
, "\n");
1346 if (loglevel
& CPU_LOG_TB_OP
) {
1347 fprintf(logfile
, "OP:\n");
1348 dump_ops(gen_opc_buf
, gen_opparam_buf
);
1349 fprintf(logfile
, "\n");
1356 int gen_intermediate_code(CPUSPARCState
* env
, TranslationBlock
* tb
)
1358 return gen_intermediate_code_internal(tb
, 0, env
);
1361 int gen_intermediate_code_pc(CPUSPARCState
* env
, TranslationBlock
* tb
)
1363 return gen_intermediate_code_internal(tb
, 1, env
);
1366 CPUSPARCState
*cpu_sparc_init(void)
1372 if (!(env
= malloc(sizeof(CPUSPARCState
))))
1374 memset(env
, 0, sizeof(*env
));
1377 env
->regwptr
= env
->regbase
+ (env
->cwp
* 16);
1378 #if defined(CONFIG_USER_ONLY)
1379 env
->user_mode_only
= 1;
1384 env
->npc
= env
->pc
+ 4;
1385 env
->mmuregs
[0] = (0x10<<24) | MMU_E
; /* Impl 1, ver 0, MMU Enabled */
1386 env
->mmuregs
[1] = 0x3000 >> 4; /* MMU Context table */
1388 cpu_single_env
= env
;
1392 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
1394 void cpu_dump_state(CPUState
*env
, FILE *f
,
1395 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
1400 cpu_fprintf(f
, "pc: 0x%08x npc: 0x%08x\n", (int) env
->pc
, (int) env
->npc
);
1401 cpu_fprintf(f
, "General Registers:\n");
1402 for (i
= 0; i
< 4; i
++)
1403 cpu_fprintf(f
, "%%g%c: 0x%08x\t", i
+ '0', env
->gregs
[i
]);
1404 cpu_fprintf(f
, "\n");
1406 cpu_fprintf(f
, "%%g%c: 0x%08x\t", i
+ '0', env
->gregs
[i
]);
1407 cpu_fprintf(f
, "\nCurrent Register Window:\n");
1408 for (x
= 0; x
< 3; x
++) {
1409 for (i
= 0; i
< 4; i
++)
1410 cpu_fprintf(f
, "%%%c%d: 0x%08x\t",
1411 (x
== 0 ? 'o' : (x
== 1 ? 'l' : 'i')), i
,
1412 env
->regwptr
[i
+ x
* 8]);
1413 cpu_fprintf(f
, "\n");
1415 cpu_fprintf(f
, "%%%c%d: 0x%08x\t",
1416 (x
== 0 ? 'o' : x
== 1 ? 'l' : 'i'), i
,
1417 env
->regwptr
[i
+ x
* 8]);
1418 cpu_fprintf(f
, "\n");
1420 cpu_fprintf(f
, "\nFloating Point Registers:\n");
1421 for (i
= 0; i
< 32; i
++) {
1423 cpu_fprintf(f
, "%%f%02d:", i
);
1424 cpu_fprintf(f
, " %016lf", env
->fpr
[i
]);
1426 cpu_fprintf(f
, "\n");
1428 cpu_fprintf(f
, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env
),
1429 GET_FLAG(PSR_ZERO
, 'Z'), GET_FLAG(PSR_OVF
, 'V'),
1430 GET_FLAG(PSR_NEG
, 'N'), GET_FLAG(PSR_CARRY
, 'C'),
1431 env
->psrs
?'S':'-', env
->psrps
?'P':'-',
1432 env
->psret
?'E':'-', env
->wim
);
1433 cpu_fprintf(f
, "fsr: 0x%08x\n", env
->fsr
);
1436 target_ulong
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
1441 void helper_flush(target_ulong addr
)
1444 tb_invalidate_page_range(addr
, addr
+ 8);