target-tricore/op_helper.c

   1 /*
   2  *  Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
   3  *
   4  * This library is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU Lesser General Public
   6  * License as published by the Free Software Foundation; either
   7  * version 2 of the License, or (at your option) any later version.
   8  *
   9  * This library is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * Lesser General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU Lesser General Public
  15  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17 #include <stdlib.h>
  18 #include "cpu.h"
  19 #include "qemu/host-utils.h"
  20 #include "exec/helper-proto.h"
  21 #include "exec/cpu_ldst.h"
  22
  23 #define SSOV(env, ret, arg, len) do {               \
  24     int64_t max_pos = INT##len ##_MAX;              \
  25     int64_t max_neg = INT##len ##_MIN;              \
  26     if (arg > max_pos) {                            \
  27         env->PSW_USB_V = (1 << 31);                 \
  28         env->PSW_USB_SV = (1 << 31);                \
  29         ret = (target_ulong)max_pos;                \
  30     } else {                                        \
  31         if (arg < max_neg) {                        \
  32             env->PSW_USB_V = (1 << 31);             \
  33             env->PSW_USB_SV = (1 << 31);            \
  34             ret = (target_ulong)max_neg;            \
  35         } else {                                    \
  36             env->PSW_USB_V = 0;                     \
  37             ret = (target_ulong)arg;                \
  38         }                                           \
  39     }                                               \
  40     env->PSW_USB_AV = arg ^ arg * 2u;               \
  41     env->PSW_USB_SAV |= env->PSW_USB_AV;            \
  42 } while (0)
  43
  44 target_ulong helper_add_ssov(CPUTriCoreState *env, target_ulong r1,
  45                              target_ulong r2)
  46 {
  47     target_ulong ret;
  48     int64_t t1 = sextract64(r1, 0, 32);
  49     int64_t t2 = sextract64(r2, 0, 32);
  50     int64_t result = t1 + t2;
  51     SSOV(env, ret, result, 32);
  52     return ret;
  53 }
  54
  55 target_ulong helper_sub_ssov(CPUTriCoreState *env, target_ulong r1,
  56                              target_ulong r2)
  57 {
  58     target_ulong ret;
  59     int64_t t1 = sextract64(r1, 0, 32);
  60     int64_t t2 = sextract64(r2, 0, 32);
  61     int64_t result = t1 - t2;
  62     SSOV(env, ret, result, 32);
  63     return ret;
  64 }
  65
  66 /* context save area (CSA) related helpers */
  67
  68 static int cdc_increment(target_ulong *psw)
  69 {
  70     if ((*psw & MASK_PSW_CDC) == 0x7f) {
  71         return 0;
  72     }
  73
  74     (*psw)++;
  75     /* check for overflow */
  76     int lo = clo32((*psw & MASK_PSW_CDC) << (32 - 7));
  77     int mask = (1u << (7 - lo)) - 1;
  78     int count = *psw & mask;
  79     if (count == 0) {
  80         (*psw)--;
  81         return 1;
  82     }
  83     return 0;
  84 }
  85
  86 static int cdc_decrement(target_ulong *psw)
  87 {
  88     if ((*psw & MASK_PSW_CDC) == 0x7f) {
  89         return 0;
  90     }
  91     /* check for underflow */
  92     int lo = clo32((*psw & MASK_PSW_CDC) << (32 - 7));
  93     int mask = (1u << (7 - lo)) - 1;
  94     int count = *psw & mask;
  95     if (count == 0) {
  96         return 1;
  97     }
  98     (*psw)--;
  99     return 0;
 100 }
 101
 102 static bool cdc_zero(target_ulong *psw)
 103 {
 104     int cdc = *psw & MASK_PSW_CDC;
 105     /* Returns TRUE if PSW.CDC.COUNT == 0 or if PSW.CDC ==
 106        7'b1111111, otherwise returns FALSE. */
 107     if (cdc == 0x7f) {
 108         return true;
 109     }
 110     /* find CDC.COUNT */
 111     int lo = clo32((*psw & MASK_PSW_CDC) << (32 - 7));
 112     int mask = (1u << (7 - lo)) - 1;
 113     int count = *psw & mask;
 114     return count == 0;
 115 }
 116
 117 static void save_context_upper(CPUTriCoreState *env, int ea)
 118 {
 119     cpu_stl_data(env, ea, env->PCXI);
 120     cpu_stl_data(env, ea+4, env->PSW);
 121     cpu_stl_data(env, ea+8, env->gpr_a[10]);
 122     cpu_stl_data(env, ea+12, env->gpr_a[11]);
 123     cpu_stl_data(env, ea+16, env->gpr_d[8]);
 124     cpu_stl_data(env, ea+20, env->gpr_d[9]);
 125     cpu_stl_data(env, ea+24, env->gpr_d[10]);
 126     cpu_stl_data(env, ea+28, env->gpr_d[11]);
 127     cpu_stl_data(env, ea+32, env->gpr_a[12]);
 128     cpu_stl_data(env, ea+36, env->gpr_a[13]);
 129     cpu_stl_data(env, ea+40, env->gpr_a[14]);
 130     cpu_stl_data(env, ea+44, env->gpr_a[15]);
 131     cpu_stl_data(env, ea+48, env->gpr_d[12]);
 132     cpu_stl_data(env, ea+52, env->gpr_d[13]);
 133     cpu_stl_data(env, ea+56, env->gpr_d[14]);
 134     cpu_stl_data(env, ea+60, env->gpr_d[15]);
 135 }
 136
 137 static void save_context_lower(CPUTriCoreState *env, int ea)
 138 {
 139     cpu_stl_data(env, ea, env->PCXI);
 140     cpu_stl_data(env, ea+4, env->gpr_a[11]);
 141     cpu_stl_data(env, ea+8, env->gpr_a[2]);
 142     cpu_stl_data(env, ea+12, env->gpr_a[3]);
 143     cpu_stl_data(env, ea+16, env->gpr_d[0]);
 144     cpu_stl_data(env, ea+20, env->gpr_d[1]);
 145     cpu_stl_data(env, ea+24, env->gpr_d[2]);
 146     cpu_stl_data(env, ea+28, env->gpr_d[3]);
 147     cpu_stl_data(env, ea+32, env->gpr_a[4]);
 148     cpu_stl_data(env, ea+36, env->gpr_a[5]);
 149     cpu_stl_data(env, ea+40, env->gpr_a[6]);
 150     cpu_stl_data(env, ea+44, env->gpr_a[7]);
 151     cpu_stl_data(env, ea+48, env->gpr_d[4]);
 152     cpu_stl_data(env, ea+52, env->gpr_d[5]);
 153     cpu_stl_data(env, ea+56, env->gpr_d[6]);
 154     cpu_stl_data(env, ea+60, env->gpr_d[7]);
 155 }
 156
 157 static void restore_context_upper(CPUTriCoreState *env, int ea,
 158                                   target_ulong *new_PCXI, target_ulong *new_PSW)
 159 {
 160     *new_PCXI = cpu_ldl_data(env, ea);
 161     *new_PSW = cpu_ldl_data(env, ea+4);
 162     env->gpr_a[10] = cpu_ldl_data(env, ea+8);
 163     env->gpr_a[11] = cpu_ldl_data(env, ea+12);
 164     env->gpr_d[8]  = cpu_ldl_data(env, ea+16);
 165     env->gpr_d[9]  = cpu_ldl_data(env, ea+20);
 166     env->gpr_d[10] = cpu_ldl_data(env, ea+24);
 167     env->gpr_d[11] = cpu_ldl_data(env, ea+28);
 168     env->gpr_a[12] = cpu_ldl_data(env, ea+32);
 169     env->gpr_a[13] = cpu_ldl_data(env, ea+36);
 170     env->gpr_a[14] = cpu_ldl_data(env, ea+40);
 171     env->gpr_a[15] = cpu_ldl_data(env, ea+44);
 172     env->gpr_d[12] = cpu_ldl_data(env, ea+48);
 173     env->gpr_d[13] = cpu_ldl_data(env, ea+52);
 174     env->gpr_d[14] = cpu_ldl_data(env, ea+56);
 175     env->gpr_d[15] = cpu_ldl_data(env, ea+60);
 176 }
 177
 178 void helper_call(CPUTriCoreState *env, uint32_t next_pc)
 179 {
 180     target_ulong tmp_FCX;
 181     target_ulong ea;
 182     target_ulong new_FCX;
 183     target_ulong psw;
 184
 185     psw = psw_read(env);
 186     /* if (FCX == 0) trap(FCU); */
 187     if (env->FCX == 0) {
 188         /* FCU trap */
 189     }
 190     /* if (PSW.CDE) then if (cdc_increment()) then trap(CDO); */
 191     if (psw & MASK_PSW_CDE) {
 192         if (cdc_increment(&psw)) {
 193             /* CDO trap */
 194         }
 195     }
 196     /* PSW.CDE = 1;*/
 197     psw |= MASK_PSW_CDE;
 198     /* tmp_FCX = FCX; */
 199     tmp_FCX = env->FCX;
 200     /* EA = {FCX.FCXS, 6'b0, FCX.FCXO, 6'b0}; */
 201     ea = ((env->FCX & MASK_FCX_FCXS) << 12) +
 202          ((env->FCX & MASK_FCX_FCXO) << 6);
 203     /* new_FCX = M(EA, word); */
 204     new_FCX = cpu_ldl_data(env, ea);
 205     /* M(EA, 16 * word) = {PCXI, PSW, A[10], A[11], D[8], D[9], D[10], D[11],
 206                            A[12], A[13], A[14], A[15], D[12], D[13], D[14],
 207                            D[15]}; */
 208     save_context_upper(env, ea);
 209
 210     /* PCXI.PCPN = ICR.CCPN; */
 211     env->PCXI = (env->PCXI & 0xffffff) +
 212                 ((env->ICR & MASK_ICR_CCPN) << 24);
 213     /* PCXI.PIE = ICR.IE; */
 214     env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) +
 215                 ((env->ICR & MASK_ICR_IE) << 15));
 216     /* PCXI.UL = 1; */
 217     env->PCXI |= MASK_PCXI_UL;
 218
 219     /* PCXI[19: 0] = FCX[19: 0]; */
 220     env->PCXI = (env->PCXI & 0xfff00000) + (env->FCX & 0xfffff);
 221     /* FCX[19: 0] = new_FCX[19: 0]; */
 222     env->FCX = (env->FCX & 0xfff00000) + (new_FCX & 0xfffff);
 223     /* A[11] = next_pc[31: 0]; */
 224     env->gpr_a[11] = next_pc;
 225
 226     /* if (tmp_FCX == LCX) trap(FCD);*/
 227     if (tmp_FCX == env->LCX) {
 228         /* FCD trap */
 229     }
 230     psw_write(env, psw);
 231 }
 232
 233 void helper_ret(CPUTriCoreState *env)
 234 {
 235     target_ulong ea;
 236     target_ulong new_PCXI;
 237     target_ulong new_PSW, psw;
 238
 239     psw = psw_read(env);
 240      /* if (PSW.CDE) then if (cdc_decrement()) then trap(CDU);*/
 241     if (env->PSW & MASK_PSW_CDE) {
 242         if (cdc_decrement(&(env->PSW))) {
 243             /* CDU trap */
 244         }
 245     }
 246     /*   if (PCXI[19: 0] == 0) then trap(CSU); */
 247     if ((env->PCXI & 0xfffff) == 0) {
 248         /* CSU trap */
 249     }
 250     /* if (PCXI.UL == 0) then trap(CTYP); */
 251     if ((env->PCXI & MASK_PCXI_UL) == 0) {
 252         /* CTYP trap */
 253     }
 254     /* PC = {A11 [31: 1], 1’b0}; */
 255     env->PC = env->gpr_a[11] & 0xfffffffe;
 256
 257     /* EA = {PCXI.PCXS, 6'b0, PCXI.PCXO, 6'b0}; */
 258     ea = ((env->PCXI & MASK_PCXI_PCXS) << 12) +
 259          ((env->PCXI & MASK_PCXI_PCXO) << 6);
 260     /* {new_PCXI, new_PSW, A[10], A[11], D[8], D[9], D[10], D[11], A[12],
 261         A[13], A[14], A[15], D[12], D[13], D[14], D[15]} = M(EA, 16 * word); */
 262     restore_context_upper(env, ea, &new_PCXI, &new_PSW);
 263     /* M(EA, word) = FCX; */
 264     cpu_stl_data(env, ea, env->FCX);
 265     /* FCX[19: 0] = PCXI[19: 0]; */
 266     env->FCX = (env->FCX & 0xfff00000) + (env->PCXI & 0x000fffff);
 267     /* PCXI = new_PCXI; */
 268     env->PCXI = new_PCXI;
 269
 270     if (tricore_feature(env, TRICORE_FEATURE_13)) {
 271         /* PSW = new_PSW */
 272         psw_write(env, new_PSW);
 273     } else {
 274         /* PSW = {new_PSW[31:26], PSW[25:24], new_PSW[23:0]}; */
 275         psw_write(env, (new_PSW & ~(0x3000000)) + (psw & (0x3000000)));
 276     }
 277 }
 278
 279 void helper_bisr(CPUTriCoreState *env, uint32_t const9)
 280 {
 281     target_ulong tmp_FCX;
 282     target_ulong ea;
 283     target_ulong new_FCX;
 284
 285     if (env->FCX == 0) {
 286         /* FCU trap */
 287     }
 288
 289     tmp_FCX = env->FCX;
 290     ea = ((env->FCX & 0xf0000) << 12) + ((env->FCX & 0xffff) << 6);
 291
 292     /* new_FCX = M(EA, word); */
 293     new_FCX = cpu_ldl_data(env, ea);
 294     /* M(EA, 16 * word) = {PCXI, A[11], A[2], A[3], D[0], D[1], D[2], D[3], A[4]
 295                            , A[5], A[6], A[7], D[4], D[5], D[6], D[7]}; */
 296     save_context_lower(env, ea);
 297
 298
 299     /* PCXI.PCPN = ICR.CCPN */
 300     env->PCXI = (env->PCXI & 0xffffff) +
 301                  ((env->ICR & MASK_ICR_CCPN) << 24);
 302     /* PCXI.PIE  = ICR.IE */
 303     env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) +
 304                  ((env->ICR & MASK_ICR_IE) << 15));
 305     /* PCXI.UL = 0 */
 306     env->PCXI &= ~(MASK_PCXI_UL);
 307     /* PCXI[19: 0] = FCX[19: 0] */
 308     env->PCXI = (env->PCXI & 0xfff00000) + (env->FCX & 0xfffff);
 309     /* FXC[19: 0] = new_FCX[19: 0] */
 310     env->FCX = (env->FCX & 0xfff00000) + (new_FCX & 0xfffff);
 311     /* ICR.IE = 1 */
 312     env->ICR |= MASK_ICR_IE;
 313
 314     env->ICR |= const9; /* ICR.CCPN = const9[7: 0];*/
 315
 316     if (tmp_FCX == env->LCX) {
 317         /* FCD trap */
 318     }
 319 }
 320
 321 void helper_rfe(CPUTriCoreState *env)
 322 {
 323     target_ulong ea;
 324     target_ulong new_PCXI;
 325     target_ulong new_PSW;
 326     /* if (PCXI[19: 0] == 0) then trap(CSU); */
 327     if ((env->PCXI & 0xfffff) == 0) {
 328         /* raise csu trap */
 329     }
 330     /* if (PCXI.UL == 0) then trap(CTYP); */
 331     if ((env->PCXI & MASK_PCXI_UL) == 0) {
 332         /* raise CTYP trap */
 333     }
 334     /* if (!cdc_zero() AND PSW.CDE) then trap(NEST); */
 335     if (!cdc_zero(&(env->PSW)) && (env->PSW & MASK_PSW_CDE)) {
 336         /* raise MNG trap */
 337     }
 338     /* ICR.IE = PCXI.PIE; */
 339     env->ICR = (env->ICR & ~MASK_ICR_IE) + ((env->PCXI & MASK_PCXI_PIE) >> 15);
 340     /* ICR.CCPN = PCXI.PCPN; */
 341     env->ICR = (env->ICR & ~MASK_ICR_CCPN) +
 342                ((env->PCXI & MASK_PCXI_PCPN) >> 24);
 343     /*EA = {PCXI.PCXS, 6'b0, PCXI.PCXO, 6'b0};*/
 344     ea = ((env->PCXI & MASK_PCXI_PCXS) << 12) +
 345          ((env->PCXI & MASK_PCXI_PCXO) << 6);
 346     /*{new_PCXI, PSW, A[10], A[11], D[8], D[9], D[10], D[11], A[12],
 347       A[13], A[14], A[15], D[12], D[13], D[14], D[15]} = M(EA, 16 * word); */
 348     restore_context_upper(env, ea, &new_PCXI, &new_PSW);
 349     /* M(EA, word) = FCX;*/
 350     cpu_stl_data(env, ea, env->FCX);
 351     /* FCX[19: 0] = PCXI[19: 0]; */
 352     env->FCX = (env->FCX & 0xfff00000) + (env->PCXI & 0x000fffff);
 353     /* PCXI = new_PCXI; */
 354     env->PCXI = new_PCXI;
 355     /* write psw */
 356     psw_write(env, new_PSW);
 357 }
 358
 359 static inline void QEMU_NORETURN do_raise_exception_err(CPUTriCoreState *env,
 360                                                         uint32_t exception,
 361                                                         int error_code,
 362                                                         uintptr_t pc)
 363 {
 364     CPUState *cs = CPU(tricore_env_get_cpu(env));
 365     cs->exception_index = exception;
 366     env->error_code = error_code;
 367
 368     if (pc) {
 369         /* now we have a real cpu fault */
 370         cpu_restore_state(cs, pc);
 371     }
 372
 373     cpu_loop_exit(cs);
 374 }
 375
 376 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
 377               uintptr_t retaddr)
 378 {
 379     int ret;
 380     ret = cpu_tricore_handle_mmu_fault(cs, addr, is_write, mmu_idx);
 381     if (ret) {
 382         TriCoreCPU *cpu = TRICORE_CPU(cs);
 383         CPUTriCoreState *env = &cpu->env;
 384         do_raise_exception_err(env, cs->exception_index,
 385                                env->error_code, retaddr);
 386     }
 387 }