3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 typedef struct DisasContext
{
45 const XtensaConfig
*config
;
55 int singlestep_enabled
;
59 bool sar_m32_allocated
;
62 uint32_t ccount_delta
;
66 static TCGv_ptr cpu_env
;
67 static TCGv_i32 cpu_pc
;
68 static TCGv_i32 cpu_R
[16];
69 static TCGv_i32 cpu_SR
[256];
70 static TCGv_i32 cpu_UR
[256];
72 #include "gen-icount.h"
74 static const char * const sregnames
[256] = {
79 [LITBASE
] = "LITBASE",
80 [SCOMPARE1
] = "SCOMPARE1",
81 [WINDOW_BASE
] = "WINDOW_BASE",
82 [WINDOW_START
] = "WINDOW_START",
83 [PTEVADDR
] = "PTEVADDR",
85 [ITLBCFG
] = "ITLBCFG",
86 [DTLBCFG
] = "DTLBCFG",
101 [EXCSAVE1
] = "EXCSAVE1",
102 [EXCSAVE1
+ 1] = "EXCSAVE2",
103 [EXCSAVE1
+ 2] = "EXCSAVE3",
104 [EXCSAVE1
+ 3] = "EXCSAVE4",
105 [EXCSAVE1
+ 4] = "EXCSAVE5",
106 [EXCSAVE1
+ 5] = "EXCSAVE6",
107 [EXCSAVE1
+ 6] = "EXCSAVE7",
108 [CPENABLE
] = "CPENABLE",
110 [INTCLEAR
] = "INTCLEAR",
111 [INTENABLE
] = "INTENABLE",
113 [VECBASE
] = "VECBASE",
114 [EXCCAUSE
] = "EXCCAUSE",
117 [EXCVADDR
] = "EXCVADDR",
118 [CCOMPARE
] = "CCOMPARE0",
119 [CCOMPARE
+ 1] = "CCOMPARE1",
120 [CCOMPARE
+ 2] = "CCOMPARE2",
123 static const char * const uregnames
[256] = {
124 [THREADPTR
] = "THREADPTR",
129 void xtensa_translate_init(void)
131 static const char * const regnames
[] = {
132 "ar0", "ar1", "ar2", "ar3",
133 "ar4", "ar5", "ar6", "ar7",
134 "ar8", "ar9", "ar10", "ar11",
135 "ar12", "ar13", "ar14", "ar15",
139 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
140 cpu_pc
= tcg_global_mem_new_i32(TCG_AREG0
,
141 offsetof(CPUState
, pc
), "pc");
143 for (i
= 0; i
< 16; i
++) {
144 cpu_R
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
145 offsetof(CPUState
, regs
[i
]),
149 for (i
= 0; i
< 256; ++i
) {
151 cpu_SR
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
152 offsetof(CPUState
, sregs
[i
]),
157 for (i
= 0; i
< 256; ++i
) {
159 cpu_UR
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
160 offsetof(CPUState
, uregs
[i
]),
168 static inline bool option_bits_enabled(DisasContext
*dc
, uint64_t opt
)
170 return xtensa_option_bits_enabled(dc
->config
, opt
);
173 static inline bool option_enabled(DisasContext
*dc
, int opt
)
175 return xtensa_option_enabled(dc
->config
, opt
);
178 static void init_litbase(DisasContext
*dc
)
180 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
181 dc
->litbase
= tcg_temp_local_new_i32();
182 tcg_gen_andi_i32(dc
->litbase
, cpu_SR
[LITBASE
], 0xfffff000);
186 static void reset_litbase(DisasContext
*dc
)
188 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
189 tcg_temp_free(dc
->litbase
);
193 static void init_sar_tracker(DisasContext
*dc
)
195 dc
->sar_5bit
= false;
196 dc
->sar_m32_5bit
= false;
197 dc
->sar_m32_allocated
= false;
200 static void reset_sar_tracker(DisasContext
*dc
)
202 if (dc
->sar_m32_allocated
) {
203 tcg_temp_free(dc
->sar_m32
);
207 static void gen_right_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
209 tcg_gen_andi_i32(cpu_SR
[SAR
], sa
, 0x1f);
210 if (dc
->sar_m32_5bit
) {
211 tcg_gen_discard_i32(dc
->sar_m32
);
214 dc
->sar_m32_5bit
= false;
217 static void gen_left_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
219 TCGv_i32 tmp
= tcg_const_i32(32);
220 if (!dc
->sar_m32_allocated
) {
221 dc
->sar_m32
= tcg_temp_local_new_i32();
222 dc
->sar_m32_allocated
= true;
224 tcg_gen_andi_i32(dc
->sar_m32
, sa
, 0x1f);
225 tcg_gen_sub_i32(cpu_SR
[SAR
], tmp
, dc
->sar_m32
);
226 dc
->sar_5bit
= false;
227 dc
->sar_m32_5bit
= true;
231 static void gen_advance_ccount(DisasContext
*dc
)
233 if (dc
->ccount_delta
> 0) {
234 TCGv_i32 tmp
= tcg_const_i32(dc
->ccount_delta
);
235 dc
->ccount_delta
= 0;
236 gen_helper_advance_ccount(tmp
);
241 static void reset_used_window(DisasContext
*dc
)
246 static void gen_exception(DisasContext
*dc
, int excp
)
248 TCGv_i32 tmp
= tcg_const_i32(excp
);
249 gen_advance_ccount(dc
);
250 gen_helper_exception(tmp
);
254 static void gen_exception_cause(DisasContext
*dc
, uint32_t cause
)
256 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
257 TCGv_i32 tcause
= tcg_const_i32(cause
);
258 gen_advance_ccount(dc
);
259 gen_helper_exception_cause(tpc
, tcause
);
261 tcg_temp_free(tcause
);
264 static void gen_exception_cause_vaddr(DisasContext
*dc
, uint32_t cause
,
267 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
268 TCGv_i32 tcause
= tcg_const_i32(cause
);
269 gen_advance_ccount(dc
);
270 gen_helper_exception_cause_vaddr(tpc
, tcause
, vaddr
);
272 tcg_temp_free(tcause
);
275 static void gen_check_privilege(DisasContext
*dc
)
278 gen_exception_cause(dc
, PRIVILEGED_CAUSE
);
282 static void gen_jump_slot(DisasContext
*dc
, TCGv dest
, int slot
)
284 tcg_gen_mov_i32(cpu_pc
, dest
);
285 if (dc
->singlestep_enabled
) {
286 gen_exception(dc
, EXCP_DEBUG
);
288 gen_advance_ccount(dc
);
290 tcg_gen_goto_tb(slot
);
291 tcg_gen_exit_tb((tcg_target_long
)dc
->tb
+ slot
);
296 dc
->is_jmp
= DISAS_UPDATE
;
299 static void gen_jump(DisasContext
*dc
, TCGv dest
)
301 gen_jump_slot(dc
, dest
, -1);
304 static void gen_jumpi(DisasContext
*dc
, uint32_t dest
, int slot
)
306 TCGv_i32 tmp
= tcg_const_i32(dest
);
307 if (((dc
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
310 gen_jump_slot(dc
, tmp
, slot
);
314 static void gen_callw_slot(DisasContext
*dc
, int callinc
, TCGv_i32 dest
,
317 TCGv_i32 tcallinc
= tcg_const_i32(callinc
);
319 tcg_gen_deposit_i32(cpu_SR
[PS
], cpu_SR
[PS
],
320 tcallinc
, PS_CALLINC_SHIFT
, PS_CALLINC_LEN
);
321 tcg_temp_free(tcallinc
);
322 tcg_gen_movi_i32(cpu_R
[callinc
<< 2],
323 (callinc
<< 30) | (dc
->next_pc
& 0x3fffffff));
324 gen_jump_slot(dc
, dest
, slot
);
327 static void gen_callw(DisasContext
*dc
, int callinc
, TCGv_i32 dest
)
329 gen_callw_slot(dc
, callinc
, dest
, -1);
332 static void gen_callwi(DisasContext
*dc
, int callinc
, uint32_t dest
, int slot
)
334 TCGv_i32 tmp
= tcg_const_i32(dest
);
335 if (((dc
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
338 gen_callw_slot(dc
, callinc
, tmp
, slot
);
342 static bool gen_check_loop_end(DisasContext
*dc
, int slot
)
344 if (option_enabled(dc
, XTENSA_OPTION_LOOP
) &&
345 !(dc
->tb
->flags
& XTENSA_TBFLAG_EXCM
) &&
346 dc
->next_pc
== dc
->lend
) {
347 int label
= gen_new_label();
349 tcg_gen_brcondi_i32(TCG_COND_EQ
, cpu_SR
[LCOUNT
], 0, label
);
350 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_SR
[LCOUNT
], 1);
351 gen_jumpi(dc
, dc
->lbeg
, slot
);
352 gen_set_label(label
);
353 gen_jumpi(dc
, dc
->next_pc
, -1);
359 static void gen_jumpi_check_loop_end(DisasContext
*dc
, int slot
)
361 if (!gen_check_loop_end(dc
, slot
)) {
362 gen_jumpi(dc
, dc
->next_pc
, slot
);
366 static void gen_brcond(DisasContext
*dc
, TCGCond cond
,
367 TCGv_i32 t0
, TCGv_i32 t1
, uint32_t offset
)
369 int label
= gen_new_label();
371 tcg_gen_brcond_i32(cond
, t0
, t1
, label
);
372 gen_jumpi_check_loop_end(dc
, 0);
373 gen_set_label(label
);
374 gen_jumpi(dc
, dc
->pc
+ offset
, 1);
377 static void gen_brcondi(DisasContext
*dc
, TCGCond cond
,
378 TCGv_i32 t0
, uint32_t t1
, uint32_t offset
)
380 TCGv_i32 tmp
= tcg_const_i32(t1
);
381 gen_brcond(dc
, cond
, t0
, tmp
, offset
);
385 static void gen_rsr_ccount(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
387 gen_advance_ccount(dc
);
388 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
391 static void gen_rsr_ptevaddr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
393 tcg_gen_shri_i32(d
, cpu_SR
[EXCVADDR
], 10);
394 tcg_gen_or_i32(d
, d
, cpu_SR
[sr
]);
395 tcg_gen_andi_i32(d
, d
, 0xfffffffc);
398 static void gen_rsr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
400 static void (* const rsr_handler
[256])(DisasContext
*dc
,
401 TCGv_i32 d
, uint32_t sr
) = {
402 [CCOUNT
] = gen_rsr_ccount
,
403 [PTEVADDR
] = gen_rsr_ptevaddr
,
407 if (rsr_handler
[sr
]) {
408 rsr_handler
[sr
](dc
, d
, sr
);
410 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
413 qemu_log("RSR %d not implemented, ", sr
);
417 static void gen_wsr_lbeg(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
419 gen_helper_wsr_lbeg(s
);
422 static void gen_wsr_lend(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
424 gen_helper_wsr_lend(s
);
427 static void gen_wsr_sar(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
429 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0x3f);
430 if (dc
->sar_m32_5bit
) {
431 tcg_gen_discard_i32(dc
->sar_m32
);
433 dc
->sar_5bit
= false;
434 dc
->sar_m32_5bit
= false;
437 static void gen_wsr_litbase(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
439 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0xfffff001);
440 /* This can change tb->flags, so exit tb */
441 gen_jumpi_check_loop_end(dc
, -1);
444 static void gen_wsr_windowbase(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
446 gen_helper_wsr_windowbase(v
);
447 reset_used_window(dc
);
450 static void gen_wsr_windowstart(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
452 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
453 reset_used_window(dc
);
456 static void gen_wsr_ptevaddr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
458 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xffc00000);
461 static void gen_wsr_rasid(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
463 gen_helper_wsr_rasid(v
);
464 /* This can change tb->flags, so exit tb */
465 gen_jumpi_check_loop_end(dc
, -1);
468 static void gen_wsr_tlbcfg(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
470 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0x01130000);
473 static void gen_wsr_intset(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
475 tcg_gen_andi_i32(cpu_SR
[sr
], v
,
476 dc
->config
->inttype_mask
[INTTYPE_SOFTWARE
]);
477 gen_helper_check_interrupts(cpu_env
);
478 gen_jumpi_check_loop_end(dc
, 0);
481 static void gen_wsr_intclear(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
483 TCGv_i32 tmp
= tcg_temp_new_i32();
485 tcg_gen_andi_i32(tmp
, v
,
486 dc
->config
->inttype_mask
[INTTYPE_EDGE
] |
487 dc
->config
->inttype_mask
[INTTYPE_NMI
] |
488 dc
->config
->inttype_mask
[INTTYPE_SOFTWARE
]);
489 tcg_gen_andc_i32(cpu_SR
[INTSET
], cpu_SR
[INTSET
], tmp
);
491 gen_helper_check_interrupts(cpu_env
);
494 static void gen_wsr_intenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
496 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
497 gen_helper_check_interrupts(cpu_env
);
498 gen_jumpi_check_loop_end(dc
, 0);
501 static void gen_wsr_ps(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
503 uint32_t mask
= PS_WOE
| PS_CALLINC
| PS_OWB
|
504 PS_UM
| PS_EXCM
| PS_INTLEVEL
;
506 if (option_enabled(dc
, XTENSA_OPTION_MMU
)) {
509 tcg_gen_andi_i32(cpu_SR
[sr
], v
, mask
);
510 reset_used_window(dc
);
511 gen_helper_check_interrupts(cpu_env
);
512 /* This can change mmu index and tb->flags, so exit tb */
513 gen_jumpi_check_loop_end(dc
, -1);
516 static void gen_wsr_prid(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
520 static void gen_wsr_ccompare(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
522 uint32_t id
= sr
- CCOMPARE
;
523 if (id
< dc
->config
->nccompare
) {
524 uint32_t int_bit
= 1 << dc
->config
->timerint
[id
];
525 gen_advance_ccount(dc
);
526 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
527 tcg_gen_andi_i32(cpu_SR
[INTSET
], cpu_SR
[INTSET
], ~int_bit
);
528 gen_helper_check_interrupts(cpu_env
);
532 static void gen_wsr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
534 static void (* const wsr_handler
[256])(DisasContext
*dc
,
535 uint32_t sr
, TCGv_i32 v
) = {
536 [LBEG
] = gen_wsr_lbeg
,
537 [LEND
] = gen_wsr_lend
,
539 [LITBASE
] = gen_wsr_litbase
,
540 [WINDOW_BASE
] = gen_wsr_windowbase
,
541 [WINDOW_START
] = gen_wsr_windowstart
,
542 [PTEVADDR
] = gen_wsr_ptevaddr
,
543 [RASID
] = gen_wsr_rasid
,
544 [ITLBCFG
] = gen_wsr_tlbcfg
,
545 [DTLBCFG
] = gen_wsr_tlbcfg
,
546 [INTSET
] = gen_wsr_intset
,
547 [INTCLEAR
] = gen_wsr_intclear
,
548 [INTENABLE
] = gen_wsr_intenable
,
550 [PRID
] = gen_wsr_prid
,
551 [CCOMPARE
] = gen_wsr_ccompare
,
552 [CCOMPARE
+ 1] = gen_wsr_ccompare
,
553 [CCOMPARE
+ 2] = gen_wsr_ccompare
,
557 if (wsr_handler
[sr
]) {
558 wsr_handler
[sr
](dc
, sr
, s
);
560 tcg_gen_mov_i32(cpu_SR
[sr
], s
);
563 qemu_log("WSR %d not implemented, ", sr
);
567 static void gen_load_store_alignment(DisasContext
*dc
, int shift
,
568 TCGv_i32 addr
, bool no_hw_alignment
)
570 if (!option_enabled(dc
, XTENSA_OPTION_UNALIGNED_EXCEPTION
)) {
571 tcg_gen_andi_i32(addr
, addr
, ~0 << shift
);
572 } else if (option_enabled(dc
, XTENSA_OPTION_HW_ALIGNMENT
) &&
574 int label
= gen_new_label();
575 TCGv_i32 tmp
= tcg_temp_new_i32();
576 tcg_gen_andi_i32(tmp
, addr
, ~(~0 << shift
));
577 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
578 gen_exception_cause_vaddr(dc
, LOAD_STORE_ALIGNMENT_CAUSE
, addr
);
579 gen_set_label(label
);
584 static void gen_waiti(DisasContext
*dc
, uint32_t imm4
)
586 TCGv_i32 pc
= tcg_const_i32(dc
->next_pc
);
587 TCGv_i32 intlevel
= tcg_const_i32(imm4
);
588 gen_advance_ccount(dc
);
589 gen_helper_waiti(pc
, intlevel
);
591 tcg_temp_free(intlevel
);
594 static void gen_window_check1(DisasContext
*dc
, unsigned r1
)
596 if (dc
->tb
->flags
& XTENSA_TBFLAG_EXCM
) {
599 if (option_enabled(dc
, XTENSA_OPTION_WINDOWED_REGISTER
) &&
600 r1
/ 4 > dc
->used_window
) {
601 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
602 TCGv_i32 w
= tcg_const_i32(r1
/ 4);
604 dc
->used_window
= r1
/ 4;
605 gen_advance_ccount(dc
);
606 gen_helper_window_check(pc
, w
);
613 static void gen_window_check2(DisasContext
*dc
, unsigned r1
, unsigned r2
)
615 gen_window_check1(dc
, r1
> r2
? r1
: r2
);
618 static void gen_window_check3(DisasContext
*dc
, unsigned r1
, unsigned r2
,
621 gen_window_check2(dc
, r1
, r2
> r3
? r2
: r3
);
624 static void disas_xtensa_insn(DisasContext
*dc
)
626 #define HAS_OPTION_BITS(opt) do { \
627 if (!option_bits_enabled(dc, opt)) { \
628 qemu_log("Option is not enabled %s:%d\n", \
629 __FILE__, __LINE__); \
630 goto invalid_opcode; \
634 #define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
636 #define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
637 #define RESERVED() do { \
638 qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
639 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
640 goto invalid_opcode; \
644 #ifdef TARGET_WORDS_BIGENDIAN
645 #define OP0 (((b0) & 0xf0) >> 4)
646 #define OP1 (((b2) & 0xf0) >> 4)
647 #define OP2 ((b2) & 0xf)
648 #define RRR_R ((b1) & 0xf)
649 #define RRR_S (((b1) & 0xf0) >> 4)
650 #define RRR_T ((b0) & 0xf)
652 #define OP0 (((b0) & 0xf))
653 #define OP1 (((b2) & 0xf))
654 #define OP2 (((b2) & 0xf0) >> 4)
655 #define RRR_R (((b1) & 0xf0) >> 4)
656 #define RRR_S (((b1) & 0xf))
657 #define RRR_T (((b0) & 0xf0) >> 4)
667 #define RRI8_IMM8 (b2)
668 #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
670 #ifdef TARGET_WORDS_BIGENDIAN
671 #define RI16_IMM16 (((b1) << 8) | (b2))
673 #define RI16_IMM16 (((b2) << 8) | (b1))
676 #ifdef TARGET_WORDS_BIGENDIAN
677 #define CALL_N (((b0) & 0xc) >> 2)
678 #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
680 #define CALL_N (((b0) & 0x30) >> 4)
681 #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
683 #define CALL_OFFSET_SE \
684 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
686 #define CALLX_N CALL_N
687 #ifdef TARGET_WORDS_BIGENDIAN
688 #define CALLX_M ((b0) & 0x3)
690 #define CALLX_M (((b0) & 0xc0) >> 6)
692 #define CALLX_S RRR_S
694 #define BRI12_M CALLX_M
695 #define BRI12_S RRR_S
696 #ifdef TARGET_WORDS_BIGENDIAN
697 #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
699 #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
701 #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
703 #define BRI8_M BRI12_M
704 #define BRI8_R RRI8_R
705 #define BRI8_S RRI8_S
706 #define BRI8_IMM8 RRI8_IMM8
707 #define BRI8_IMM8_SE RRI8_IMM8_SE
711 uint8_t b0
= ldub_code(dc
->pc
);
712 uint8_t b1
= ldub_code(dc
->pc
+ 1);
713 uint8_t b2
= ldub_code(dc
->pc
+ 2);
715 static const uint32_t B4CONST
[] = {
716 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
719 static const uint32_t B4CONSTU
[] = {
720 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
724 dc
->next_pc
= dc
->pc
+ 2;
725 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY
);
727 dc
->next_pc
= dc
->pc
+ 3;
736 if ((RRR_R
& 0xc) == 0x8) {
737 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
744 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
755 gen_window_check1(dc
, CALLX_S
);
756 gen_jump(dc
, cpu_R
[CALLX_S
]);
760 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
762 TCGv_i32 tmp
= tcg_const_i32(dc
->pc
);
763 gen_advance_ccount(dc
);
764 gen_helper_retw(tmp
, tmp
);
777 gen_window_check2(dc
, CALLX_S
, CALLX_N
<< 2);
781 TCGv_i32 tmp
= tcg_temp_new_i32();
782 tcg_gen_mov_i32(tmp
, cpu_R
[CALLX_S
]);
783 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
792 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
794 TCGv_i32 tmp
= tcg_temp_new_i32();
796 tcg_gen_mov_i32(tmp
, cpu_R
[CALLX_S
]);
797 gen_callw(dc
, CALLX_N
, tmp
);
807 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
808 gen_window_check2(dc
, RRR_T
, RRR_S
);
810 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
811 gen_advance_ccount(dc
);
812 gen_helper_movsp(pc
);
813 tcg_gen_mov_i32(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
833 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
845 default: /*reserved*/
854 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
857 gen_check_privilege(dc
);
858 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
859 gen_helper_check_interrupts(cpu_env
);
860 gen_jump(dc
, cpu_SR
[EPC1
]);
868 gen_check_privilege(dc
);
870 dc
->config
->ndepc
? DEPC
: EPC1
]);
875 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
876 gen_check_privilege(dc
);
878 TCGv_i32 tmp
= tcg_const_i32(1);
881 cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
882 tcg_gen_shl_i32(tmp
, tmp
, cpu_SR
[WINDOW_BASE
]);
885 tcg_gen_andc_i32(cpu_SR
[WINDOW_START
],
886 cpu_SR
[WINDOW_START
], tmp
);
888 tcg_gen_or_i32(cpu_SR
[WINDOW_START
],
889 cpu_SR
[WINDOW_START
], tmp
);
892 gen_helper_restore_owb();
893 gen_helper_check_interrupts(cpu_env
);
894 gen_jump(dc
, cpu_SR
[EPC1
]);
900 default: /*reserved*/
907 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
);
908 if (RRR_S
>= 2 && RRR_S
<= dc
->config
->nlevel
) {
909 gen_check_privilege(dc
);
910 tcg_gen_mov_i32(cpu_SR
[PS
],
911 cpu_SR
[EPS2
+ RRR_S
- 2]);
912 gen_helper_check_interrupts(cpu_env
);
913 gen_jump(dc
, cpu_SR
[EPC1
+ RRR_S
- 1]);
915 qemu_log("RFI %d is illegal\n", RRR_S
);
916 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
924 default: /*reserved*/
932 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
937 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
940 gen_exception_cause(dc
, SYSCALL_CAUSE
);
944 if (semihosting_enabled
) {
945 gen_check_privilege(dc
);
946 gen_helper_simcall(cpu_env
);
948 qemu_log("SIMCALL but semihosting is disabled\n");
949 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
960 HAS_OPTION(XTENSA_OPTION_INTERRUPT
);
961 gen_check_privilege(dc
);
962 gen_window_check1(dc
, RRR_T
);
963 tcg_gen_mov_i32(cpu_R
[RRR_T
], cpu_SR
[PS
]);
964 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_INTLEVEL
);
965 tcg_gen_ori_i32(cpu_SR
[PS
], cpu_SR
[PS
], RRR_S
);
966 gen_helper_check_interrupts(cpu_env
);
967 gen_jumpi_check_loop_end(dc
, 0);
971 HAS_OPTION(XTENSA_OPTION_INTERRUPT
);
972 gen_check_privilege(dc
);
973 gen_waiti(dc
, RRR_S
);
977 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
982 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
987 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
992 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
996 default: /*reserved*/
1004 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1005 tcg_gen_and_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1009 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1010 tcg_gen_or_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1014 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1015 tcg_gen_xor_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1021 gen_window_check1(dc
, RRR_S
);
1022 gen_right_shift_sar(dc
, cpu_R
[RRR_S
]);
1026 gen_window_check1(dc
, RRR_S
);
1027 gen_left_shift_sar(dc
, cpu_R
[RRR_S
]);
1031 gen_window_check1(dc
, RRR_S
);
1033 TCGv_i32 tmp
= tcg_temp_new_i32();
1034 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], 3);
1035 gen_right_shift_sar(dc
, tmp
);
1041 gen_window_check1(dc
, RRR_S
);
1043 TCGv_i32 tmp
= tcg_temp_new_i32();
1044 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], 3);
1045 gen_left_shift_sar(dc
, tmp
);
1052 TCGv_i32 tmp
= tcg_const_i32(
1053 RRR_S
| ((RRR_T
& 1) << 4));
1054 gen_right_shift_sar(dc
, tmp
);
1068 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1069 gen_check_privilege(dc
);
1071 TCGv_i32 tmp
= tcg_const_i32(
1072 RRR_T
| ((RRR_T
& 8) ? 0xfffffff0 : 0));
1073 gen_helper_rotw(tmp
);
1075 reset_used_window(dc
);
1080 HAS_OPTION(XTENSA_OPTION_MISC_OP
);
1081 gen_window_check2(dc
, RRR_S
, RRR_T
);
1082 gen_helper_nsa(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1086 HAS_OPTION(XTENSA_OPTION_MISC_OP
);
1087 gen_window_check2(dc
, RRR_S
, RRR_T
);
1088 gen_helper_nsau(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1091 default: /*reserved*/
1099 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU
) |
1100 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION
) |
1101 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION
));
1102 gen_check_privilege(dc
);
1103 gen_window_check2(dc
, RRR_S
, RRR_T
);
1105 TCGv_i32 dtlb
= tcg_const_i32((RRR_R
& 8) != 0);
1107 switch (RRR_R
& 7) {
1108 case 3: /*RITLB0*/ /*RDTLB0*/
1109 gen_helper_rtlb0(cpu_R
[RRR_T
], cpu_R
[RRR_S
], dtlb
);
1112 case 4: /*IITLB*/ /*IDTLB*/
1113 gen_helper_itlb(cpu_R
[RRR_S
], dtlb
);
1114 /* This could change memory mapping, so exit tb */
1115 gen_jumpi_check_loop_end(dc
, -1);
1118 case 5: /*PITLB*/ /*PDTLB*/
1119 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
1120 gen_helper_ptlb(cpu_R
[RRR_T
], cpu_R
[RRR_S
], dtlb
);
1123 case 6: /*WITLB*/ /*WDTLB*/
1124 gen_helper_wtlb(cpu_R
[RRR_T
], cpu_R
[RRR_S
], dtlb
);
1125 /* This could change memory mapping, so exit tb */
1126 gen_jumpi_check_loop_end(dc
, -1);
1129 case 7: /*RITLB1*/ /*RDTLB1*/
1130 gen_helper_rtlb1(cpu_R
[RRR_T
], cpu_R
[RRR_S
], dtlb
);
1134 tcg_temp_free(dtlb
);
1138 tcg_temp_free(dtlb
);
1143 gen_window_check2(dc
, RRR_R
, RRR_T
);
1146 tcg_gen_neg_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1151 int label
= gen_new_label();
1152 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1153 tcg_gen_brcondi_i32(
1154 TCG_COND_GE
, cpu_R
[RRR_R
], 0, label
);
1155 tcg_gen_neg_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1156 gen_set_label(label
);
1160 default: /*reserved*/
1166 case 7: /*reserved*/
1171 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1172 tcg_gen_add_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1178 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1180 TCGv_i32 tmp
= tcg_temp_new_i32();
1181 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], OP2
- 8);
1182 tcg_gen_add_i32(cpu_R
[RRR_R
], tmp
, cpu_R
[RRR_T
]);
1188 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1189 tcg_gen_sub_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1195 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1197 TCGv_i32 tmp
= tcg_temp_new_i32();
1198 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], OP2
- 12);
1199 tcg_gen_sub_i32(cpu_R
[RRR_R
], tmp
, cpu_R
[RRR_T
]);
1210 gen_window_check2(dc
, RRR_R
, RRR_S
);
1211 tcg_gen_shli_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
],
1212 32 - (RRR_T
| ((OP2
& 1) << 4)));
1217 gen_window_check2(dc
, RRR_R
, RRR_T
);
1218 tcg_gen_sari_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
],
1219 RRR_S
| ((OP2
& 1) << 4));
1223 gen_window_check2(dc
, RRR_R
, RRR_T
);
1224 tcg_gen_shri_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], RRR_S
);
1229 TCGv_i32 tmp
= tcg_temp_new_i32();
1231 gen_check_privilege(dc
);
1233 gen_window_check1(dc
, RRR_T
);
1234 tcg_gen_mov_i32(tmp
, cpu_R
[RRR_T
]);
1235 gen_rsr(dc
, cpu_R
[RRR_T
], RSR_SR
);
1236 gen_wsr(dc
, RSR_SR
, tmp
);
1238 if (!sregnames
[RSR_SR
]) {
1245 * Note: 64 bit ops are used here solely because SAR values
1248 #define gen_shift_reg(cmd, reg) do { \
1249 TCGv_i64 tmp = tcg_temp_new_i64(); \
1250 tcg_gen_extu_i32_i64(tmp, reg); \
1251 tcg_gen_##cmd##_i64(v, v, tmp); \
1252 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \
1253 tcg_temp_free_i64(v); \
1254 tcg_temp_free_i64(tmp); \
1257 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1260 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1262 TCGv_i64 v
= tcg_temp_new_i64();
1263 tcg_gen_concat_i32_i64(v
, cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1269 gen_window_check2(dc
, RRR_R
, RRR_T
);
1271 tcg_gen_shr_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], cpu_SR
[SAR
]);
1273 TCGv_i64 v
= tcg_temp_new_i64();
1274 tcg_gen_extu_i32_i64(v
, cpu_R
[RRR_T
]);
1280 gen_window_check2(dc
, RRR_R
, RRR_S
);
1281 if (dc
->sar_m32_5bit
) {
1282 tcg_gen_shl_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], dc
->sar_m32
);
1284 TCGv_i64 v
= tcg_temp_new_i64();
1285 TCGv_i32 s
= tcg_const_i32(32);
1286 tcg_gen_sub_i32(s
, s
, cpu_SR
[SAR
]);
1287 tcg_gen_andi_i32(s
, s
, 0x3f);
1288 tcg_gen_extu_i32_i64(v
, cpu_R
[RRR_S
]);
1289 gen_shift_reg(shl
, s
);
1295 gen_window_check2(dc
, RRR_R
, RRR_T
);
1297 tcg_gen_sar_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], cpu_SR
[SAR
]);
1299 TCGv_i64 v
= tcg_temp_new_i64();
1300 tcg_gen_ext_i32_i64(v
, cpu_R
[RRR_T
]);
1305 #undef gen_shift_reg
1308 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL
);
1309 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1311 TCGv_i32 v1
= tcg_temp_new_i32();
1312 TCGv_i32 v2
= tcg_temp_new_i32();
1313 tcg_gen_ext16u_i32(v1
, cpu_R
[RRR_S
]);
1314 tcg_gen_ext16u_i32(v2
, cpu_R
[RRR_T
]);
1315 tcg_gen_mul_i32(cpu_R
[RRR_R
], v1
, v2
);
1322 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL
);
1323 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1325 TCGv_i32 v1
= tcg_temp_new_i32();
1326 TCGv_i32 v2
= tcg_temp_new_i32();
1327 tcg_gen_ext16s_i32(v1
, cpu_R
[RRR_S
]);
1328 tcg_gen_ext16s_i32(v2
, cpu_R
[RRR_T
]);
1329 tcg_gen_mul_i32(cpu_R
[RRR_R
], v1
, v2
);
1335 default: /*reserved*/
1342 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1345 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV
);
1346 int label
= gen_new_label();
1347 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_T
], 0, label
);
1348 gen_exception_cause(dc
, INTEGER_DIVIDE_BY_ZERO_CAUSE
);
1349 gen_set_label(label
);
1354 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL
);
1355 tcg_gen_mul_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1360 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL
);
1362 TCGv_i64 r
= tcg_temp_new_i64();
1363 TCGv_i64 s
= tcg_temp_new_i64();
1364 TCGv_i64 t
= tcg_temp_new_i64();
1367 tcg_gen_extu_i32_i64(s
, cpu_R
[RRR_S
]);
1368 tcg_gen_extu_i32_i64(t
, cpu_R
[RRR_T
]);
1370 tcg_gen_ext_i32_i64(s
, cpu_R
[RRR_S
]);
1371 tcg_gen_ext_i32_i64(t
, cpu_R
[RRR_T
]);
1373 tcg_gen_mul_i64(r
, s
, t
);
1374 tcg_gen_shri_i64(r
, r
, 32);
1375 tcg_gen_trunc_i64_i32(cpu_R
[RRR_R
], r
);
1377 tcg_temp_free_i64(r
);
1378 tcg_temp_free_i64(s
);
1379 tcg_temp_free_i64(t
);
1384 tcg_gen_divu_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1390 int label1
= gen_new_label();
1391 int label2
= gen_new_label();
1393 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_S
], 0x80000000,
1395 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_T
], 0xffffffff,
1397 tcg_gen_movi_i32(cpu_R
[RRR_R
],
1398 OP2
== 13 ? 0x80000000 : 0);
1400 gen_set_label(label1
);
1402 tcg_gen_div_i32(cpu_R
[RRR_R
],
1403 cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1405 tcg_gen_rem_i32(cpu_R
[RRR_R
],
1406 cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1408 gen_set_label(label2
);
1413 tcg_gen_remu_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1416 default: /*reserved*/
1426 gen_check_privilege(dc
);
1428 gen_window_check1(dc
, RRR_T
);
1429 gen_rsr(dc
, cpu_R
[RRR_T
], RSR_SR
);
1430 if (!sregnames
[RSR_SR
]) {
1437 gen_check_privilege(dc
);
1439 gen_window_check1(dc
, RRR_T
);
1440 gen_wsr(dc
, RSR_SR
, cpu_R
[RRR_T
]);
1441 if (!sregnames
[RSR_SR
]) {
1447 HAS_OPTION(XTENSA_OPTION_MISC_OP
);
1448 gen_window_check2(dc
, RRR_R
, RRR_S
);
1450 int shift
= 24 - RRR_T
;
1453 tcg_gen_ext8s_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1454 } else if (shift
== 16) {
1455 tcg_gen_ext16s_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1457 TCGv_i32 tmp
= tcg_temp_new_i32();
1458 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], shift
);
1459 tcg_gen_sari_i32(cpu_R
[RRR_R
], tmp
, shift
);
1466 HAS_OPTION(XTENSA_OPTION_MISC_OP
);
1467 gen_window_check2(dc
, RRR_R
, RRR_S
);
1469 TCGv_i32 tmp1
= tcg_temp_new_i32();
1470 TCGv_i32 tmp2
= tcg_temp_new_i32();
1471 int label
= gen_new_label();
1473 tcg_gen_sari_i32(tmp1
, cpu_R
[RRR_S
], 24 - RRR_T
);
1474 tcg_gen_xor_i32(tmp2
, tmp1
, cpu_R
[RRR_S
]);
1475 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffffffff << (RRR_T
+ 7));
1476 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1477 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp2
, 0, label
);
1479 tcg_gen_sari_i32(tmp1
, cpu_R
[RRR_S
], 31);
1480 tcg_gen_xori_i32(cpu_R
[RRR_R
], tmp1
,
1481 0xffffffff >> (25 - RRR_T
));
1483 gen_set_label(label
);
1485 tcg_temp_free(tmp1
);
1486 tcg_temp_free(tmp2
);
1494 HAS_OPTION(XTENSA_OPTION_MISC_OP
);
1495 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1497 static const TCGCond cond
[] = {
1503 int label
= gen_new_label();
1505 if (RRR_R
!= RRR_T
) {
1506 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1507 tcg_gen_brcond_i32(cond
[OP2
- 4],
1508 cpu_R
[RRR_S
], cpu_R
[RRR_T
], label
);
1509 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1511 tcg_gen_brcond_i32(cond
[OP2
- 4],
1512 cpu_R
[RRR_T
], cpu_R
[RRR_S
], label
);
1513 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1515 gen_set_label(label
);
1523 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1525 static const TCGCond cond
[] = {
1531 int label
= gen_new_label();
1532 tcg_gen_brcondi_i32(cond
[OP2
- 8], cpu_R
[RRR_T
], 0, label
);
1533 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1534 gen_set_label(label
);
1539 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
1544 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
1549 gen_window_check1(dc
, RRR_R
);
1551 int st
= (RRR_S
<< 4) + RRR_T
;
1552 if (uregnames
[st
]) {
1553 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_UR
[st
]);
1555 qemu_log("RUR %d not implemented, ", st
);
1562 gen_window_check1(dc
, RRR_T
);
1564 if (uregnames
[RSR_SR
]) {
1565 tcg_gen_mov_i32(cpu_UR
[RSR_SR
], cpu_R
[RRR_T
]);
1567 qemu_log("WUR %d not implemented, ", RSR_SR
);
1578 gen_window_check2(dc
, RRR_R
, RRR_T
);
1580 int shiftimm
= RRR_S
| (OP1
<< 4);
1581 int maskimm
= (1 << (OP2
+ 1)) - 1;
1583 TCGv_i32 tmp
= tcg_temp_new_i32();
1584 tcg_gen_shri_i32(tmp
, cpu_R
[RRR_T
], shiftimm
);
1585 tcg_gen_andi_i32(cpu_R
[RRR_R
], tmp
, maskimm
);
1599 HAS_OPTION(XTENSA_OPTION_COPROCESSOR
);
1604 gen_window_check2(dc
, RRR_S
, RRR_T
);
1607 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1608 gen_check_privilege(dc
);
1610 TCGv_i32 addr
= tcg_temp_new_i32();
1611 tcg_gen_addi_i32(addr
, cpu_R
[RRR_S
],
1612 (0xffffffc0 | (RRR_R
<< 2)));
1613 tcg_gen_qemu_ld32u(cpu_R
[RRR_T
], addr
, dc
->ring
);
1614 tcg_temp_free(addr
);
1619 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1620 gen_check_privilege(dc
);
1622 TCGv_i32 addr
= tcg_temp_new_i32();
1623 tcg_gen_addi_i32(addr
, cpu_R
[RRR_S
],
1624 (0xffffffc0 | (RRR_R
<< 2)));
1625 tcg_gen_qemu_st32(cpu_R
[RRR_T
], addr
, dc
->ring
);
1626 tcg_temp_free(addr
);
1637 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
1642 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
1646 default: /*reserved*/
1653 gen_window_check1(dc
, RRR_T
);
1655 TCGv_i32 tmp
= tcg_const_i32(
1656 ((dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) ?
1657 0 : ((dc
->pc
+ 3) & ~3)) +
1658 (0xfffc0000 | (RI16_IMM16
<< 2)));
1660 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
1661 tcg_gen_add_i32(tmp
, tmp
, dc
->litbase
);
1663 tcg_gen_qemu_ld32u(cpu_R
[RRR_T
], tmp
, dc
->cring
);
1669 #define gen_load_store(type, shift) do { \
1670 TCGv_i32 addr = tcg_temp_new_i32(); \
1671 gen_window_check2(dc, RRI8_S, RRI8_T); \
1672 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
1674 gen_load_store_alignment(dc, shift, addr, false); \
1676 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
1677 tcg_temp_free(addr); \
1682 gen_load_store(ld8u
, 0);
1686 gen_load_store(ld16u
, 1);
1690 gen_load_store(ld32u
, 2);
1694 gen_load_store(st8
, 0);
1698 gen_load_store(st16
, 1);
1702 gen_load_store(st32
, 2);
1707 HAS_OPTION(XTENSA_OPTION_DCACHE
);
1738 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
1742 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
1746 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
1750 HAS_OPTION(XTENSA_OPTION_DCACHE
);
1754 HAS_OPTION(XTENSA_OPTION_DCACHE
);
1757 default: /*reserved*/
1765 HAS_OPTION(XTENSA_OPTION_ICACHE
);
1771 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
1775 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
1779 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
1782 default: /*reserved*/
1789 HAS_OPTION(XTENSA_OPTION_ICACHE
);
1793 HAS_OPTION(XTENSA_OPTION_ICACHE
);
1796 default: /*reserved*/
1803 gen_load_store(ld16s
, 1);
1805 #undef gen_load_store
1808 gen_window_check1(dc
, RRI8_T
);
1809 tcg_gen_movi_i32(cpu_R
[RRI8_T
],
1810 RRI8_IMM8
| (RRI8_S
<< 8) |
1811 ((RRI8_S
& 0x8) ? 0xfffff000 : 0));
1814 #define gen_load_store_no_hw_align(type) do { \
1815 TCGv_i32 addr = tcg_temp_local_new_i32(); \
1816 gen_window_check2(dc, RRI8_S, RRI8_T); \
1817 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
1818 gen_load_store_alignment(dc, 2, addr, true); \
1819 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
1820 tcg_temp_free(addr); \
1824 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO
);
1825 gen_load_store_no_hw_align(ld32u
); /*TODO acquire?*/
1829 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
1830 tcg_gen_addi_i32(cpu_R
[RRI8_T
], cpu_R
[RRI8_S
], RRI8_IMM8_SE
);
1834 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
1835 tcg_gen_addi_i32(cpu_R
[RRI8_T
], cpu_R
[RRI8_S
], RRI8_IMM8_SE
<< 8);
1838 case 14: /*S32C1Iy*/
1839 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO
);
1840 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
1842 int label
= gen_new_label();
1843 TCGv_i32 tmp
= tcg_temp_local_new_i32();
1844 TCGv_i32 addr
= tcg_temp_local_new_i32();
1846 tcg_gen_mov_i32(tmp
, cpu_R
[RRI8_T
]);
1847 tcg_gen_addi_i32(addr
, cpu_R
[RRI8_S
], RRI8_IMM8
<< 2);
1848 gen_load_store_alignment(dc
, 2, addr
, true);
1849 tcg_gen_qemu_ld32u(cpu_R
[RRI8_T
], addr
, dc
->cring
);
1850 tcg_gen_brcond_i32(TCG_COND_NE
, cpu_R
[RRI8_T
],
1851 cpu_SR
[SCOMPARE1
], label
);
1853 tcg_gen_qemu_st32(tmp
, addr
, dc
->cring
);
1855 gen_set_label(label
);
1856 tcg_temp_free(addr
);
1862 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO
);
1863 gen_load_store_no_hw_align(st32
); /*TODO release?*/
1865 #undef gen_load_store_no_hw_align
1867 default: /*reserved*/
1874 HAS_OPTION(XTENSA_OPTION_COPROCESSOR
);
1879 HAS_OPTION(XTENSA_OPTION_MAC16
);
1886 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
1887 gen_jumpi(dc
, (dc
->pc
& ~3) + (CALL_OFFSET_SE
<< 2) + 4, 0);
1893 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1894 gen_window_check1(dc
, CALL_N
<< 2);
1895 gen_callwi(dc
, CALL_N
,
1896 (dc
->pc
& ~3) + (CALL_OFFSET_SE
<< 2) + 4, 0);
1904 gen_jumpi(dc
, dc
->pc
+ 4 + CALL_OFFSET_SE
, 0);
1908 gen_window_check1(dc
, BRI12_S
);
1910 static const TCGCond cond
[] = {
1911 TCG_COND_EQ
, /*BEQZ*/
1912 TCG_COND_NE
, /*BNEZ*/
1913 TCG_COND_LT
, /*BLTZ*/
1914 TCG_COND_GE
, /*BGEZ*/
1917 gen_brcondi(dc
, cond
[BRI12_M
& 3], cpu_R
[BRI12_S
], 0,
1918 4 + BRI12_IMM12_SE
);
1923 gen_window_check1(dc
, BRI8_S
);
1925 static const TCGCond cond
[] = {
1926 TCG_COND_EQ
, /*BEQI*/
1927 TCG_COND_NE
, /*BNEI*/
1928 TCG_COND_LT
, /*BLTI*/
1929 TCG_COND_GE
, /*BGEI*/
1932 gen_brcondi(dc
, cond
[BRI8_M
& 3],
1933 cpu_R
[BRI8_S
], B4CONST
[BRI8_R
], 4 + BRI8_IMM8_SE
);
1940 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1942 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
1943 TCGv_i32 s
= tcg_const_i32(BRI12_S
);
1944 TCGv_i32 imm
= tcg_const_i32(BRI12_IMM12
);
1945 gen_advance_ccount(dc
);
1946 gen_helper_entry(pc
, s
, imm
);
1950 reset_used_window(dc
);
1957 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
1962 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
1968 case 10: /*LOOPGTZ*/
1969 HAS_OPTION(XTENSA_OPTION_LOOP
);
1970 gen_window_check1(dc
, RRI8_S
);
1972 uint32_t lend
= dc
->pc
+ RRI8_IMM8
+ 4;
1973 TCGv_i32 tmp
= tcg_const_i32(lend
);
1975 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_R
[RRI8_S
], 1);
1976 tcg_gen_movi_i32(cpu_SR
[LBEG
], dc
->next_pc
);
1977 gen_wsr_lend(dc
, LEND
, tmp
);
1981 int label
= gen_new_label();
1982 tcg_gen_brcondi_i32(
1983 BRI8_R
== 9 ? TCG_COND_NE
: TCG_COND_GT
,
1984 cpu_R
[RRI8_S
], 0, label
);
1985 gen_jumpi(dc
, lend
, 1);
1986 gen_set_label(label
);
1989 gen_jumpi(dc
, dc
->next_pc
, 0);
1993 default: /*reserved*/
2002 gen_window_check1(dc
, BRI8_S
);
2003 gen_brcondi(dc
, BRI8_M
== 2 ? TCG_COND_LTU
: TCG_COND_GEU
,
2004 cpu_R
[BRI8_S
], B4CONSTU
[BRI8_R
], 4 + BRI8_IMM8_SE
);
2014 TCGCond eq_ne
= (RRI8_R
& 8) ? TCG_COND_NE
: TCG_COND_EQ
;
2016 switch (RRI8_R
& 7) {
2017 case 0: /*BNONE*/ /*BANY*/
2018 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2020 TCGv_i32 tmp
= tcg_temp_new_i32();
2021 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], cpu_R
[RRI8_T
]);
2022 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2027 case 1: /*BEQ*/ /*BNE*/
2028 case 2: /*BLT*/ /*BGE*/
2029 case 3: /*BLTU*/ /*BGEU*/
2030 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2032 static const TCGCond cond
[] = {
2038 [11] = TCG_COND_GEU
,
2040 gen_brcond(dc
, cond
[RRI8_R
], cpu_R
[RRI8_S
], cpu_R
[RRI8_T
],
2045 case 4: /*BALL*/ /*BNALL*/
2046 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2048 TCGv_i32 tmp
= tcg_temp_new_i32();
2049 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], cpu_R
[RRI8_T
]);
2050 gen_brcond(dc
, eq_ne
, tmp
, cpu_R
[RRI8_T
],
2056 case 5: /*BBC*/ /*BBS*/
2057 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2059 TCGv_i32 bit
= tcg_const_i32(1);
2060 TCGv_i32 tmp
= tcg_temp_new_i32();
2061 tcg_gen_andi_i32(tmp
, cpu_R
[RRI8_T
], 0x1f);
2062 tcg_gen_shl_i32(bit
, bit
, tmp
);
2063 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], bit
);
2064 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2070 case 6: /*BBCI*/ /*BBSI*/
2072 gen_window_check1(dc
, RRI8_S
);
2074 TCGv_i32 tmp
= tcg_temp_new_i32();
2075 tcg_gen_andi_i32(tmp
, cpu_R
[RRI8_S
],
2076 1 << (((RRI8_R
& 1) << 4) | RRI8_T
));
2077 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2086 #define gen_narrow_load_store(type) do { \
2087 TCGv_i32 addr = tcg_temp_new_i32(); \
2088 gen_window_check2(dc, RRRN_S, RRRN_T); \
2089 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
2090 gen_load_store_alignment(dc, 2, addr, false); \
2091 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
2092 tcg_temp_free(addr); \
2096 gen_narrow_load_store(ld32u
);
2100 gen_narrow_load_store(st32
);
2102 #undef gen_narrow_load_store
2105 gen_window_check3(dc
, RRRN_R
, RRRN_S
, RRRN_T
);
2106 tcg_gen_add_i32(cpu_R
[RRRN_R
], cpu_R
[RRRN_S
], cpu_R
[RRRN_T
]);
2109 case 11: /*ADDI.Nn*/
2110 gen_window_check2(dc
, RRRN_R
, RRRN_S
);
2111 tcg_gen_addi_i32(cpu_R
[RRRN_R
], cpu_R
[RRRN_S
], RRRN_T
? RRRN_T
: -1);
2115 gen_window_check1(dc
, RRRN_S
);
2116 if (RRRN_T
< 8) { /*MOVI.Nn*/
2117 tcg_gen_movi_i32(cpu_R
[RRRN_S
],
2118 RRRN_R
| (RRRN_T
<< 4) |
2119 ((RRRN_T
& 6) == 6 ? 0xffffff80 : 0));
2120 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
2121 TCGCond eq_ne
= (RRRN_T
& 4) ? TCG_COND_NE
: TCG_COND_EQ
;
2123 gen_brcondi(dc
, eq_ne
, cpu_R
[RRRN_S
], 0,
2124 4 + (RRRN_R
| ((RRRN_T
& 3) << 4)));
2131 gen_window_check2(dc
, RRRN_S
, RRRN_T
);
2132 tcg_gen_mov_i32(cpu_R
[RRRN_T
], cpu_R
[RRRN_S
]);
2138 gen_jump(dc
, cpu_R
[0]);
2142 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
2144 TCGv_i32 tmp
= tcg_const_i32(dc
->pc
);
2145 gen_advance_ccount(dc
);
2146 gen_helper_retw(tmp
, tmp
);
2152 case 2: /*BREAK.Nn*/
2160 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
2163 default: /*reserved*/
2169 default: /*reserved*/
2175 default: /*reserved*/
2180 gen_check_loop_end(dc
, 0);
2181 dc
->pc
= dc
->next_pc
;
2186 qemu_log("INVALID(pc = %08x)\n", dc
->pc
);
2187 dc
->pc
= dc
->next_pc
;
2191 static void check_breakpoint(CPUState
*env
, DisasContext
*dc
)
2195 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
2196 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
2197 if (bp
->pc
== dc
->pc
) {
2198 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
2199 gen_exception(dc
, EXCP_DEBUG
);
2200 dc
->is_jmp
= DISAS_UPDATE
;
2206 static void gen_intermediate_code_internal(
2207 CPUState
*env
, TranslationBlock
*tb
, int search_pc
)
2212 uint16_t *gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
2213 int max_insns
= tb
->cflags
& CF_COUNT_MASK
;
2214 uint32_t pc_start
= tb
->pc
;
2215 uint32_t next_page_start
=
2216 (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
2218 if (max_insns
== 0) {
2219 max_insns
= CF_COUNT_MASK
;
2222 dc
.config
= env
->config
;
2223 dc
.singlestep_enabled
= env
->singlestep_enabled
;
2226 dc
.ring
= tb
->flags
& XTENSA_TBFLAG_RING_MASK
;
2227 dc
.cring
= (tb
->flags
& XTENSA_TBFLAG_EXCM
) ? 0 : dc
.ring
;
2228 dc
.lbeg
= env
->sregs
[LBEG
];
2229 dc
.lend
= env
->sregs
[LEND
];
2230 dc
.is_jmp
= DISAS_NEXT
;
2231 dc
.ccount_delta
= 0;
2234 init_sar_tracker(&dc
);
2235 reset_used_window(&dc
);
2239 if (env
->singlestep_enabled
&& env
->exception_taken
) {
2240 env
->exception_taken
= 0;
2241 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
2242 gen_exception(&dc
, EXCP_DEBUG
);
2246 check_breakpoint(env
, &dc
);
2249 j
= gen_opc_ptr
- gen_opc_buf
;
2253 gen_opc_instr_start
[lj
++] = 0;
2256 gen_opc_pc
[lj
] = dc
.pc
;
2257 gen_opc_instr_start
[lj
] = 1;
2258 gen_opc_icount
[lj
] = insn_count
;
2261 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
))) {
2262 tcg_gen_debug_insn_start(dc
.pc
);
2267 if (insn_count
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
2271 disas_xtensa_insn(&dc
);
2273 if (env
->singlestep_enabled
) {
2274 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
2275 gen_exception(&dc
, EXCP_DEBUG
);
2278 } while (dc
.is_jmp
== DISAS_NEXT
&&
2279 insn_count
< max_insns
&&
2280 dc
.pc
< next_page_start
&&
2281 gen_opc_ptr
< gen_opc_end
);
2284 reset_sar_tracker(&dc
);
2286 if (tb
->cflags
& CF_LAST_IO
) {
2290 if (dc
.is_jmp
== DISAS_NEXT
) {
2291 gen_jumpi(&dc
, dc
.pc
, 0);
2293 gen_icount_end(tb
, insn_count
);
2294 *gen_opc_ptr
= INDEX_op_end
;
2297 tb
->size
= dc
.pc
- pc_start
;
2298 tb
->icount
= insn_count
;
2302 void gen_intermediate_code(CPUState
*env
, TranslationBlock
*tb
)
2304 gen_intermediate_code_internal(env
, tb
, 0);
2307 void gen_intermediate_code_pc(CPUState
*env
, TranslationBlock
*tb
)
2309 gen_intermediate_code_internal(env
, tb
, 1);
2312 void cpu_dump_state(CPUState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
2317 cpu_fprintf(f
, "PC=%08x\n\n", env
->pc
);
2319 for (i
= j
= 0; i
< 256; ++i
) {
2321 cpu_fprintf(f
, "%s=%08x%c", sregnames
[i
], env
->sregs
[i
],
2322 (j
++ % 4) == 3 ? '\n' : ' ');
2326 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
2328 for (i
= j
= 0; i
< 256; ++i
) {
2330 cpu_fprintf(f
, "%s=%08x%c", uregnames
[i
], env
->uregs
[i
],
2331 (j
++ % 4) == 3 ? '\n' : ' ');
2335 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
2337 for (i
= 0; i
< 16; ++i
) {
2338 cpu_fprintf(f
, "A%02d=%08x%c", i
, env
->regs
[i
],
2339 (i
% 4) == 3 ? '\n' : ' ');
2342 cpu_fprintf(f
, "\n");
2344 for (i
= 0; i
< env
->config
->nareg
; ++i
) {
2345 cpu_fprintf(f
, "AR%02d=%08x%c", i
, env
->phys_regs
[i
],
2346 (i
% 4) == 3 ? '\n' : ' ');
2350 void restore_state_to_opc(CPUState
*env
, TranslationBlock
*tb
, int pc_pos
)
2352 env
->pc
= gen_opc_pc
[pc_pos
];