2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Andrzej Zaborowski
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #if defined(__ARM_ARCH_7__) || \
26 defined(__ARM_ARCH_7A__) || \
27 defined(__ARM_ARCH_7EM__) || \
28 defined(__ARM_ARCH_7M__) || \
29 defined(__ARM_ARCH_7R__)
30 #define USE_ARMV7_INSTRUCTIONS
33 #if defined(USE_ARMV7_INSTRUCTIONS) || \
34 defined(__ARM_ARCH_6J__) || \
35 defined(__ARM_ARCH_6K__) || \
36 defined(__ARM_ARCH_6T2__) || \
37 defined(__ARM_ARCH_6Z__) || \
38 defined(__ARM_ARCH_6ZK__)
39 #define USE_ARMV6_INSTRUCTIONS
42 #if defined(USE_ARMV6_INSTRUCTIONS) || \
43 defined(__ARM_ARCH_5T__) || \
44 defined(__ARM_ARCH_5TE__) || \
45 defined(__ARM_ARCH_5TEJ__)
46 #define USE_ARMV5_INSTRUCTIONS
49 #ifdef USE_ARMV5_INSTRUCTIONS
50 static const int use_armv5_instructions
= 1;
52 static const int use_armv5_instructions
= 0;
54 #undef USE_ARMV5_INSTRUCTIONS
56 #ifdef USE_ARMV6_INSTRUCTIONS
57 static const int use_armv6_instructions
= 1;
59 static const int use_armv6_instructions
= 0;
61 #undef USE_ARMV6_INSTRUCTIONS
63 #ifdef USE_ARMV7_INSTRUCTIONS
64 static const int use_armv7_instructions
= 1;
66 static const int use_armv7_instructions
= 0;
68 #undef USE_ARMV7_INSTRUCTIONS
71 static const char * const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
91 static const int tcg_target_reg_alloc_order
[] = {
109 static const int tcg_target_call_iarg_regs
[4] = {
110 TCG_REG_R0
, TCG_REG_R1
, TCG_REG_R2
, TCG_REG_R3
112 static const int tcg_target_call_oarg_regs
[2] = {
113 TCG_REG_R0
, TCG_REG_R1
116 static void patch_reloc(uint8_t *code_ptr
, int type
,
117 tcg_target_long value
, tcg_target_long addend
)
121 *(uint32_t *) code_ptr
= value
;
130 *(uint32_t *) code_ptr
= ((*(uint32_t *) code_ptr
) & 0xff000000) |
131 (((value
- ((tcg_target_long
) code_ptr
+ 8)) >> 2) & 0xffffff);
136 /* maximum number of register used for input function arguments */
137 static inline int tcg_target_get_call_iarg_regs_count(int flags
)
142 /* parse target specific constraints */
143 static int target_parse_constraint(TCGArgConstraint
*ct
, const char **pct_str
)
150 ct
->ct
|= TCG_CT_CONST_ARM
;
154 #ifndef CONFIG_SOFTMMU
160 ct
->ct
|= TCG_CT_REG
;
161 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
164 #ifdef CONFIG_SOFTMMU
165 /* qemu_ld/st inputs (unless 'X', 'd' or 'D') */
167 ct
->ct
|= TCG_CT_REG
;
168 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
169 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R0
);
170 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
173 /* qemu_ld64 data_reg */
175 ct
->ct
|= TCG_CT_REG
;
176 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
177 /* r1 is still needed to load data_reg2, so don't use it. */
178 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
181 /* qemu_ld/st64 data_reg2 */
183 ct
->ct
|= TCG_CT_REG
;
184 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
185 /* r0, r1 and optionally r2 will be overwritten by the address
186 * and the low word of data, so don't use these. */
187 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R0
);
188 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
189 # if TARGET_LONG_BITS == 64
190 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R2
);
194 # if TARGET_LONG_BITS == 64
195 /* qemu_ld/st addr_reg2 */
197 ct
->ct
|= TCG_CT_REG
;
198 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
199 /* r0 will be overwritten by the low word of base, so don't use it. */
200 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R0
);
201 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
215 static inline uint32_t rotl(uint32_t val
, int n
)
217 return (val
<< n
) | (val
>> (32 - n
));
220 /* ARM immediates for ALU instructions are made of an unsigned 8-bit
221 right-rotated by an even amount between 0 and 30. */
222 static inline int encode_imm(uint32_t imm
)
226 /* simple case, only lower bits */
227 if ((imm
& ~0xff) == 0)
229 /* then try a simple even shift */
230 shift
= ctz32(imm
) & ~1;
231 if (((imm
>> shift
) & ~0xff) == 0)
233 /* now try harder with rotations */
234 if ((rotl(imm
, 2) & ~0xff) == 0)
236 if ((rotl(imm
, 4) & ~0xff) == 0)
238 if ((rotl(imm
, 6) & ~0xff) == 0)
240 /* imm can't be encoded */
244 static inline int check_fit_imm(uint32_t imm
)
246 return encode_imm(imm
) >= 0;
249 /* Test if a constant matches the constraint.
250 * TODO: define constraints for:
252 * ldr/str offset: between -0xfff and 0xfff
253 * ldrh/strh offset: between -0xff and 0xff
254 * mov operand2: values represented with x << (2 * y), x < 0x100
255 * add, sub, eor...: ditto
257 static inline int tcg_target_const_match(tcg_target_long val
,
258 const TCGArgConstraint
*arg_ct
)
262 if (ct
& TCG_CT_CONST
)
264 else if ((ct
& TCG_CT_CONST_ARM
) && check_fit_imm(val
))
270 enum arm_data_opc_e
{
288 #define TO_CPSR(opc) \
289 ((opc == ARITH_CMP || opc == ARITH_CMN || opc == ARITH_TST) << 20)
291 #define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
292 #define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20)
293 #define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40)
294 #define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60)
295 #define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10)
296 #define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30)
297 #define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50)
298 #define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70)
300 enum arm_cond_code_e
{
303 COND_CS
= 0x2, /* Unsigned greater or equal */
304 COND_CC
= 0x3, /* Unsigned less than */
305 COND_MI
= 0x4, /* Negative */
306 COND_PL
= 0x5, /* Zero or greater */
307 COND_VS
= 0x6, /* Overflow */
308 COND_VC
= 0x7, /* No overflow */
309 COND_HI
= 0x8, /* Unsigned greater than */
310 COND_LS
= 0x9, /* Unsigned less or equal */
318 static const uint8_t tcg_cond_to_arm_cond
[10] = {
319 [TCG_COND_EQ
] = COND_EQ
,
320 [TCG_COND_NE
] = COND_NE
,
321 [TCG_COND_LT
] = COND_LT
,
322 [TCG_COND_GE
] = COND_GE
,
323 [TCG_COND_LE
] = COND_LE
,
324 [TCG_COND_GT
] = COND_GT
,
326 [TCG_COND_LTU
] = COND_CC
,
327 [TCG_COND_GEU
] = COND_CS
,
328 [TCG_COND_LEU
] = COND_LS
,
329 [TCG_COND_GTU
] = COND_HI
,
332 static inline void tcg_out_bx(TCGContext
*s
, int cond
, int rn
)
334 tcg_out32(s
, (cond
<< 28) | 0x012fff10 | rn
);
337 static inline void tcg_out_b(TCGContext
*s
, int cond
, int32_t offset
)
339 tcg_out32(s
, (cond
<< 28) | 0x0a000000 |
340 (((offset
- 8) >> 2) & 0x00ffffff));
343 static inline void tcg_out_b_noaddr(TCGContext
*s
, int cond
)
345 #ifdef HOST_WORDS_BIGENDIAN
346 tcg_out8(s
, (cond
<< 4) | 0x0a);
350 tcg_out8(s
, (cond
<< 4) | 0x0a);
354 static inline void tcg_out_bl(TCGContext
*s
, int cond
, int32_t offset
)
356 tcg_out32(s
, (cond
<< 28) | 0x0b000000 |
357 (((offset
- 8) >> 2) & 0x00ffffff));
360 static inline void tcg_out_blx(TCGContext
*s
, int cond
, int rn
)
362 tcg_out32(s
, (cond
<< 28) | 0x012fff30 | rn
);
365 static inline void tcg_out_dat_reg(TCGContext
*s
,
366 int cond
, int opc
, int rd
, int rn
, int rm
, int shift
)
368 tcg_out32(s
, (cond
<< 28) | (0 << 25) | (opc
<< 21) | TO_CPSR(opc
) |
369 (rn
<< 16) | (rd
<< 12) | shift
| rm
);
372 static inline void tcg_out_dat_reg2(TCGContext
*s
,
373 int cond
, int opc0
, int opc1
, int rd0
, int rd1
,
374 int rn0
, int rn1
, int rm0
, int rm1
, int shift
)
376 if (rd0
== rn1
|| rd0
== rm1
) {
377 tcg_out32(s
, (cond
<< 28) | (0 << 25) | (opc0
<< 21) | (1 << 20) |
378 (rn0
<< 16) | (8 << 12) | shift
| rm0
);
379 tcg_out32(s
, (cond
<< 28) | (0 << 25) | (opc1
<< 21) |
380 (rn1
<< 16) | (rd1
<< 12) | shift
| rm1
);
381 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
382 rd0
, 0, TCG_REG_R8
, SHIFT_IMM_LSL(0));
384 tcg_out32(s
, (cond
<< 28) | (0 << 25) | (opc0
<< 21) | (1 << 20) |
385 (rn0
<< 16) | (rd0
<< 12) | shift
| rm0
);
386 tcg_out32(s
, (cond
<< 28) | (0 << 25) | (opc1
<< 21) |
387 (rn1
<< 16) | (rd1
<< 12) | shift
| rm1
);
391 static inline void tcg_out_dat_imm(TCGContext
*s
,
392 int cond
, int opc
, int rd
, int rn
, int im
)
394 tcg_out32(s
, (cond
<< 28) | (1 << 25) | (opc
<< 21) | TO_CPSR(opc
) |
395 (rn
<< 16) | (rd
<< 12) | im
);
398 static inline void tcg_out_movi32(TCGContext
*s
,
399 int cond
, int rd
, int32_t arg
)
401 int offset
= (uint32_t) arg
- ((uint32_t) s
->code_ptr
+ 8);
403 /* TODO: This is very suboptimal, we can easily have a constant
404 * pool somewhere after all the instructions. */
406 if (arg
< 0 && arg
> -0x100)
407 return tcg_out_dat_imm(s
, cond
, ARITH_MVN
, rd
, 0, (~arg
) & 0xff);
409 if (offset
< 0x100 && offset
> -0x100)
411 tcg_out_dat_imm(s
, cond
, ARITH_ADD
, rd
, 15, offset
) :
412 tcg_out_dat_imm(s
, cond
, ARITH_SUB
, rd
, 15, -offset
);
414 if (use_armv7_instructions
) {
417 tcg_out32(s
, (cond
<< 28) | 0x03000000 | (rd
<< 12)
418 | ((arg
<< 4) & 0x000f0000) | (arg
& 0xfff));
419 if (arg
& 0xffff0000)
421 tcg_out32(s
, (cond
<< 28) | 0x03400000 | (rd
<< 12)
422 | ((arg
>> 12) & 0x000f0000) | ((arg
>> 16) & 0xfff));
424 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, rd
, 0, arg
& 0xff);
425 if (arg
& 0x0000ff00)
426 tcg_out_dat_imm(s
, cond
, ARITH_ORR
, rd
, rd
,
427 ((arg
>> 8) & 0xff) | 0xc00);
428 if (arg
& 0x00ff0000)
429 tcg_out_dat_imm(s
, cond
, ARITH_ORR
, rd
, rd
,
430 ((arg
>> 16) & 0xff) | 0x800);
431 if (arg
& 0xff000000)
432 tcg_out_dat_imm(s
, cond
, ARITH_ORR
, rd
, rd
,
433 ((arg
>> 24) & 0xff) | 0x400);
437 static inline void tcg_out_mul32(TCGContext
*s
,
438 int cond
, int rd
, int rs
, int rm
)
441 tcg_out32(s
, (cond
<< 28) | (rd
<< 16) | (0 << 12) |
442 (rs
<< 8) | 0x90 | rm
);
444 tcg_out32(s
, (cond
<< 28) | (rd
<< 16) | (0 << 12) |
445 (rm
<< 8) | 0x90 | rs
);
447 tcg_out32(s
, (cond
<< 28) | ( 8 << 16) | (0 << 12) |
448 (rs
<< 8) | 0x90 | rm
);
449 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
450 rd
, 0, TCG_REG_R8
, SHIFT_IMM_LSL(0));
454 static inline void tcg_out_umull32(TCGContext
*s
,
455 int cond
, int rd0
, int rd1
, int rs
, int rm
)
457 if (rd0
!= rm
&& rd1
!= rm
)
458 tcg_out32(s
, (cond
<< 28) | 0x800090 |
459 (rd1
<< 16) | (rd0
<< 12) | (rs
<< 8) | rm
);
460 else if (rd0
!= rs
&& rd1
!= rs
)
461 tcg_out32(s
, (cond
<< 28) | 0x800090 |
462 (rd1
<< 16) | (rd0
<< 12) | (rm
<< 8) | rs
);
464 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
465 TCG_REG_R8
, 0, rm
, SHIFT_IMM_LSL(0));
466 tcg_out32(s
, (cond
<< 28) | 0x800098 |
467 (rd1
<< 16) | (rd0
<< 12) | (rs
<< 8));
471 static inline void tcg_out_smull32(TCGContext
*s
,
472 int cond
, int rd0
, int rd1
, int rs
, int rm
)
474 if (rd0
!= rm
&& rd1
!= rm
)
475 tcg_out32(s
, (cond
<< 28) | 0xc00090 |
476 (rd1
<< 16) | (rd0
<< 12) | (rs
<< 8) | rm
);
477 else if (rd0
!= rs
&& rd1
!= rs
)
478 tcg_out32(s
, (cond
<< 28) | 0xc00090 |
479 (rd1
<< 16) | (rd0
<< 12) | (rm
<< 8) | rs
);
481 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
482 TCG_REG_R8
, 0, rm
, SHIFT_IMM_LSL(0));
483 tcg_out32(s
, (cond
<< 28) | 0xc00098 |
484 (rd1
<< 16) | (rd0
<< 12) | (rs
<< 8));
488 static inline void tcg_out_ld32_12(TCGContext
*s
, int cond
,
489 int rd
, int rn
, tcg_target_long im
)
492 tcg_out32(s
, (cond
<< 28) | 0x05900000 |
493 (rn
<< 16) | (rd
<< 12) | (im
& 0xfff));
495 tcg_out32(s
, (cond
<< 28) | 0x05100000 |
496 (rn
<< 16) | (rd
<< 12) | ((-im
) & 0xfff));
499 static inline void tcg_out_st32_12(TCGContext
*s
, int cond
,
500 int rd
, int rn
, tcg_target_long im
)
503 tcg_out32(s
, (cond
<< 28) | 0x05800000 |
504 (rn
<< 16) | (rd
<< 12) | (im
& 0xfff));
506 tcg_out32(s
, (cond
<< 28) | 0x05000000 |
507 (rn
<< 16) | (rd
<< 12) | ((-im
) & 0xfff));
510 static inline void tcg_out_ld32_r(TCGContext
*s
, int cond
,
511 int rd
, int rn
, int rm
)
513 tcg_out32(s
, (cond
<< 28) | 0x07900000 |
514 (rn
<< 16) | (rd
<< 12) | rm
);
517 static inline void tcg_out_st32_r(TCGContext
*s
, int cond
,
518 int rd
, int rn
, int rm
)
520 tcg_out32(s
, (cond
<< 28) | 0x07800000 |
521 (rn
<< 16) | (rd
<< 12) | rm
);
524 /* Register pre-increment with base writeback. */
525 static inline void tcg_out_ld32_rwb(TCGContext
*s
, int cond
,
526 int rd
, int rn
, int rm
)
528 tcg_out32(s
, (cond
<< 28) | 0x07b00000 |
529 (rn
<< 16) | (rd
<< 12) | rm
);
532 static inline void tcg_out_st32_rwb(TCGContext
*s
, int cond
,
533 int rd
, int rn
, int rm
)
535 tcg_out32(s
, (cond
<< 28) | 0x07a00000 |
536 (rn
<< 16) | (rd
<< 12) | rm
);
539 static inline void tcg_out_ld16u_8(TCGContext
*s
, int cond
,
540 int rd
, int rn
, tcg_target_long im
)
543 tcg_out32(s
, (cond
<< 28) | 0x01d000b0 |
544 (rn
<< 16) | (rd
<< 12) |
545 ((im
& 0xf0) << 4) | (im
& 0xf));
547 tcg_out32(s
, (cond
<< 28) | 0x015000b0 |
548 (rn
<< 16) | (rd
<< 12) |
549 (((-im
) & 0xf0) << 4) | ((-im
) & 0xf));
552 static inline void tcg_out_st16_8(TCGContext
*s
, int cond
,
553 int rd
, int rn
, tcg_target_long im
)
556 tcg_out32(s
, (cond
<< 28) | 0x01c000b0 |
557 (rn
<< 16) | (rd
<< 12) |
558 ((im
& 0xf0) << 4) | (im
& 0xf));
560 tcg_out32(s
, (cond
<< 28) | 0x014000b0 |
561 (rn
<< 16) | (rd
<< 12) |
562 (((-im
) & 0xf0) << 4) | ((-im
) & 0xf));
565 static inline void tcg_out_ld16u_r(TCGContext
*s
, int cond
,
566 int rd
, int rn
, int rm
)
568 tcg_out32(s
, (cond
<< 28) | 0x019000b0 |
569 (rn
<< 16) | (rd
<< 12) | rm
);
572 static inline void tcg_out_st16_r(TCGContext
*s
, int cond
,
573 int rd
, int rn
, int rm
)
575 tcg_out32(s
, (cond
<< 28) | 0x018000b0 |
576 (rn
<< 16) | (rd
<< 12) | rm
);
579 static inline void tcg_out_ld16s_8(TCGContext
*s
, int cond
,
580 int rd
, int rn
, tcg_target_long im
)
583 tcg_out32(s
, (cond
<< 28) | 0x01d000f0 |
584 (rn
<< 16) | (rd
<< 12) |
585 ((im
& 0xf0) << 4) | (im
& 0xf));
587 tcg_out32(s
, (cond
<< 28) | 0x015000f0 |
588 (rn
<< 16) | (rd
<< 12) |
589 (((-im
) & 0xf0) << 4) | ((-im
) & 0xf));
592 static inline void tcg_out_ld16s_r(TCGContext
*s
, int cond
,
593 int rd
, int rn
, int rm
)
595 tcg_out32(s
, (cond
<< 28) | 0x019000f0 |
596 (rn
<< 16) | (rd
<< 12) | rm
);
599 static inline void tcg_out_ld8_12(TCGContext
*s
, int cond
,
600 int rd
, int rn
, tcg_target_long im
)
603 tcg_out32(s
, (cond
<< 28) | 0x05d00000 |
604 (rn
<< 16) | (rd
<< 12) | (im
& 0xfff));
606 tcg_out32(s
, (cond
<< 28) | 0x05500000 |
607 (rn
<< 16) | (rd
<< 12) | ((-im
) & 0xfff));
610 static inline void tcg_out_st8_12(TCGContext
*s
, int cond
,
611 int rd
, int rn
, tcg_target_long im
)
614 tcg_out32(s
, (cond
<< 28) | 0x05c00000 |
615 (rn
<< 16) | (rd
<< 12) | (im
& 0xfff));
617 tcg_out32(s
, (cond
<< 28) | 0x05400000 |
618 (rn
<< 16) | (rd
<< 12) | ((-im
) & 0xfff));
621 static inline void tcg_out_ld8_r(TCGContext
*s
, int cond
,
622 int rd
, int rn
, int rm
)
624 tcg_out32(s
, (cond
<< 28) | 0x07d00000 |
625 (rn
<< 16) | (rd
<< 12) | rm
);
628 static inline void tcg_out_st8_r(TCGContext
*s
, int cond
,
629 int rd
, int rn
, int rm
)
631 tcg_out32(s
, (cond
<< 28) | 0x07c00000 |
632 (rn
<< 16) | (rd
<< 12) | rm
);
635 static inline void tcg_out_ld8s_8(TCGContext
*s
, int cond
,
636 int rd
, int rn
, tcg_target_long im
)
639 tcg_out32(s
, (cond
<< 28) | 0x01d000d0 |
640 (rn
<< 16) | (rd
<< 12) |
641 ((im
& 0xf0) << 4) | (im
& 0xf));
643 tcg_out32(s
, (cond
<< 28) | 0x015000d0 |
644 (rn
<< 16) | (rd
<< 12) |
645 (((-im
) & 0xf0) << 4) | ((-im
) & 0xf));
648 static inline void tcg_out_ld8s_r(TCGContext
*s
, int cond
,
649 int rd
, int rn
, int rm
)
651 tcg_out32(s
, (cond
<< 28) | 0x019000d0 |
652 (rn
<< 16) | (rd
<< 12) | rm
);
655 static inline void tcg_out_ld32u(TCGContext
*s
, int cond
,
656 int rd
, int rn
, int32_t offset
)
658 if (offset
> 0xfff || offset
< -0xfff) {
659 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
660 tcg_out_ld32_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
662 tcg_out_ld32_12(s
, cond
, rd
, rn
, offset
);
665 static inline void tcg_out_st32(TCGContext
*s
, int cond
,
666 int rd
, int rn
, int32_t offset
)
668 if (offset
> 0xfff || offset
< -0xfff) {
669 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
670 tcg_out_st32_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
672 tcg_out_st32_12(s
, cond
, rd
, rn
, offset
);
675 static inline void tcg_out_ld16u(TCGContext
*s
, int cond
,
676 int rd
, int rn
, int32_t offset
)
678 if (offset
> 0xff || offset
< -0xff) {
679 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
680 tcg_out_ld16u_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
682 tcg_out_ld16u_8(s
, cond
, rd
, rn
, offset
);
685 static inline void tcg_out_ld16s(TCGContext
*s
, int cond
,
686 int rd
, int rn
, int32_t offset
)
688 if (offset
> 0xff || offset
< -0xff) {
689 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
690 tcg_out_ld16s_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
692 tcg_out_ld16s_8(s
, cond
, rd
, rn
, offset
);
695 static inline void tcg_out_st16(TCGContext
*s
, int cond
,
696 int rd
, int rn
, int32_t offset
)
698 if (offset
> 0xff || offset
< -0xff) {
699 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
700 tcg_out_st16_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
702 tcg_out_st16_8(s
, cond
, rd
, rn
, offset
);
705 static inline void tcg_out_ld8u(TCGContext
*s
, int cond
,
706 int rd
, int rn
, int32_t offset
)
708 if (offset
> 0xfff || offset
< -0xfff) {
709 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
710 tcg_out_ld8_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
712 tcg_out_ld8_12(s
, cond
, rd
, rn
, offset
);
715 static inline void tcg_out_ld8s(TCGContext
*s
, int cond
,
716 int rd
, int rn
, int32_t offset
)
718 if (offset
> 0xff || offset
< -0xff) {
719 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
720 tcg_out_ld8s_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
722 tcg_out_ld8s_8(s
, cond
, rd
, rn
, offset
);
725 static inline void tcg_out_st8(TCGContext
*s
, int cond
,
726 int rd
, int rn
, int32_t offset
)
728 if (offset
> 0xfff || offset
< -0xfff) {
729 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
730 tcg_out_st8_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
732 tcg_out_st8_12(s
, cond
, rd
, rn
, offset
);
735 static inline void tcg_out_goto(TCGContext
*s
, int cond
, uint32_t addr
)
739 val
= addr
- (tcg_target_long
) s
->code_ptr
;
740 if (val
- 8 < 0x01fffffd && val
- 8 > -0x01fffffd)
741 tcg_out_b(s
, cond
, val
);
746 if (cond
== COND_AL
) {
747 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_PC
, -4);
748 tcg_out32(s
, addr
); /* XXX: This is l->u.value, can we use it? */
750 tcg_out_movi32(s
, cond
, TCG_REG_R8
, val
- 8);
751 tcg_out_dat_reg(s
, cond
, ARITH_ADD
,
752 TCG_REG_PC
, TCG_REG_PC
,
753 TCG_REG_R8
, SHIFT_IMM_LSL(0));
759 static inline void tcg_out_call(TCGContext
*s
, int cond
, uint32_t addr
)
763 val
= addr
- (tcg_target_long
) s
->code_ptr
;
764 if (val
< 0x01fffffd && val
> -0x01fffffd)
765 tcg_out_bl(s
, cond
, val
);
770 if (cond
== COND_AL
) {
771 tcg_out_dat_imm(s
, cond
, ARITH_ADD
, TCG_REG_R14
, TCG_REG_PC
, 4);
772 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_PC
, -4);
773 tcg_out32(s
, addr
); /* XXX: This is l->u.value, can we use it? */
775 tcg_out_movi32(s
, cond
, TCG_REG_R9
, addr
);
776 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, TCG_REG_R14
, 0,
777 TCG_REG_PC
, SHIFT_IMM_LSL(0));
778 tcg_out_bx(s
, cond
, TCG_REG_R9
);
784 static inline void tcg_out_callr(TCGContext
*s
, int cond
, int arg
)
786 if (use_armv5_instructions
) {
787 tcg_out_blx(s
, cond
, arg
);
789 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, TCG_REG_R14
, 0,
790 TCG_REG_PC
, SHIFT_IMM_LSL(0));
791 tcg_out_bx(s
, cond
, arg
);
795 static inline void tcg_out_goto_label(TCGContext
*s
, int cond
, int label_index
)
797 TCGLabel
*l
= &s
->labels
[label_index
];
800 tcg_out_goto(s
, cond
, l
->u
.value
);
801 else if (cond
== COND_AL
) {
802 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_PC
, -4);
803 tcg_out_reloc(s
, s
->code_ptr
, R_ARM_ABS32
, label_index
, 31337);
806 /* Probably this should be preferred even for COND_AL... */
807 tcg_out_reloc(s
, s
->code_ptr
, R_ARM_PC24
, label_index
, 31337);
808 tcg_out_b_noaddr(s
, cond
);
812 #ifdef CONFIG_SOFTMMU
814 #include "../../softmmu_defs.h"
816 static void *qemu_ld_helpers
[4] = {
823 static void *qemu_st_helpers
[4] = {
831 #define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
833 static inline void tcg_out_qemu_ld(TCGContext
*s
, int cond
,
834 const TCGArg
*args
, int opc
)
836 int addr_reg
, data_reg
, data_reg2
;
837 #ifdef CONFIG_SOFTMMU
838 int mem_index
, s_bits
;
839 # if TARGET_LONG_BITS == 64
849 data_reg2
= 0; /* suppress warning */
851 #ifdef CONFIG_SOFTMMU
852 # if TARGET_LONG_BITS == 64
858 /* Should generate something like the following:
859 * shr r8, addr_reg, #TARGET_PAGE_BITS
860 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
861 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
863 # if CPU_TLB_BITS > 8
866 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, TCG_REG_R8
,
867 0, addr_reg
, SHIFT_IMM_LSR(TARGET_PAGE_BITS
));
868 tcg_out_dat_imm(s
, COND_AL
, ARITH_AND
,
869 TCG_REG_R0
, TCG_REG_R8
, CPU_TLB_SIZE
- 1);
870 tcg_out_dat_reg(s
, COND_AL
, ARITH_ADD
, TCG_REG_R0
, TCG_AREG0
,
871 TCG_REG_R0
, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS
));
873 * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_read))]
874 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
875 * not exceed otherwise, so use an
876 * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
880 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, TCG_REG_R0
, TCG_REG_R0
,
881 (mem_index
<< (TLB_SHIFT
& 1)) |
882 ((16 - (TLB_SHIFT
>> 1)) << 8));
883 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_R1
, TCG_REG_R0
,
884 offsetof(CPUState
, tlb_table
[0][0].addr_read
));
885 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0, TCG_REG_R1
,
886 TCG_REG_R8
, SHIFT_IMM_LSL(TARGET_PAGE_BITS
));
887 /* Check alignment. */
889 tcg_out_dat_imm(s
, COND_EQ
, ARITH_TST
,
890 0, addr_reg
, (1 << s_bits
) - 1);
891 # if TARGET_LONG_BITS == 64
892 /* XXX: possibly we could use a block data load or writeback in
893 * the first access. */
894 tcg_out_ld32_12(s
, COND_EQ
, TCG_REG_R1
, TCG_REG_R0
,
895 offsetof(CPUState
, tlb_table
[0][0].addr_read
) + 4);
896 tcg_out_dat_reg(s
, COND_EQ
, ARITH_CMP
, 0,
897 TCG_REG_R1
, addr_reg2
, SHIFT_IMM_LSL(0));
899 tcg_out_ld32_12(s
, COND_EQ
, TCG_REG_R1
, TCG_REG_R0
,
900 offsetof(CPUState
, tlb_table
[0][0].addend
));
904 tcg_out_ld8_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
907 tcg_out_ld8s_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
910 tcg_out_ld16u_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
913 tcg_out_ld16s_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
917 tcg_out_ld32_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
920 tcg_out_ld32_rwb(s
, COND_EQ
, data_reg
, TCG_REG_R1
, addr_reg
);
921 tcg_out_ld32_12(s
, COND_EQ
, data_reg2
, TCG_REG_R1
, 4);
925 label_ptr
= (void *) s
->code_ptr
;
926 tcg_out_b(s
, COND_EQ
, 8);
928 /* TODO: move this code to where the constants pool will be */
929 if (addr_reg
!= TCG_REG_R0
) {
930 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
931 TCG_REG_R0
, 0, addr_reg
, SHIFT_IMM_LSL(0));
933 # if TARGET_LONG_BITS == 32
934 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, TCG_REG_R1
, 0, mem_index
);
936 if (addr_reg2
!= TCG_REG_R1
) {
937 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
938 TCG_REG_R1
, 0, addr_reg2
, SHIFT_IMM_LSL(0));
940 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, TCG_REG_R2
, 0, mem_index
);
942 tcg_out_bl(s
, cond
, (tcg_target_long
) qemu_ld_helpers
[s_bits
] -
943 (tcg_target_long
) s
->code_ptr
);
947 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
948 TCG_REG_R0
, 0, TCG_REG_R0
, SHIFT_IMM_LSL(24));
949 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
950 data_reg
, 0, TCG_REG_R0
, SHIFT_IMM_ASR(24));
953 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
954 TCG_REG_R0
, 0, TCG_REG_R0
, SHIFT_IMM_LSL(16));
955 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
956 data_reg
, 0, TCG_REG_R0
, SHIFT_IMM_ASR(16));
962 if (data_reg
!= TCG_REG_R0
) {
963 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
964 data_reg
, 0, TCG_REG_R0
, SHIFT_IMM_LSL(0));
968 if (data_reg
!= TCG_REG_R0
) {
969 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
970 data_reg
, 0, TCG_REG_R0
, SHIFT_IMM_LSL(0));
972 if (data_reg2
!= TCG_REG_R1
) {
973 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
974 data_reg2
, 0, TCG_REG_R1
, SHIFT_IMM_LSL(0));
979 *label_ptr
+= ((void *) s
->code_ptr
- (void *) label_ptr
- 8) >> 2;
980 #else /* !CONFIG_SOFTMMU */
982 uint32_t offset
= GUEST_BASE
;
987 i
= ctz32(offset
) & ~1;
988 rot
= ((32 - i
) << 7) & 0xf00;
990 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, TCG_REG_R8
, addr_reg
,
991 ((offset
>> i
) & 0xff) | rot
);
992 addr_reg
= TCG_REG_R8
;
993 offset
&= ~(0xff << i
);
998 tcg_out_ld8_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1001 tcg_out_ld8s_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
1004 tcg_out_ld16u_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
1007 tcg_out_ld16s_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
1011 tcg_out_ld32_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1014 /* TODO: use block load -
1015 * check that data_reg2 > data_reg or the other way */
1016 if (data_reg
== addr_reg
) {
1017 tcg_out_ld32_12(s
, COND_AL
, data_reg2
, addr_reg
, 4);
1018 tcg_out_ld32_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1020 tcg_out_ld32_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1021 tcg_out_ld32_12(s
, COND_AL
, data_reg2
, addr_reg
, 4);
1028 static inline void tcg_out_qemu_st(TCGContext
*s
, int cond
,
1029 const TCGArg
*args
, int opc
)
1031 int addr_reg
, data_reg
, data_reg2
;
1032 #ifdef CONFIG_SOFTMMU
1033 int mem_index
, s_bits
;
1034 # if TARGET_LONG_BITS == 64
1037 uint32_t *label_ptr
;
1042 data_reg2
= *args
++;
1044 data_reg2
= 0; /* suppress warning */
1046 #ifdef CONFIG_SOFTMMU
1047 # if TARGET_LONG_BITS == 64
1048 addr_reg2
= *args
++;
1053 /* Should generate something like the following:
1054 * shr r8, addr_reg, #TARGET_PAGE_BITS
1055 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
1056 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
1058 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1059 TCG_REG_R8
, 0, addr_reg
, SHIFT_IMM_LSR(TARGET_PAGE_BITS
));
1060 tcg_out_dat_imm(s
, COND_AL
, ARITH_AND
,
1061 TCG_REG_R0
, TCG_REG_R8
, CPU_TLB_SIZE
- 1);
1062 tcg_out_dat_reg(s
, COND_AL
, ARITH_ADD
, TCG_REG_R0
,
1063 TCG_AREG0
, TCG_REG_R0
, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS
));
1065 * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_write))]
1066 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
1067 * not exceed otherwise, so use an
1068 * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
1072 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, TCG_REG_R0
, TCG_REG_R0
,
1073 (mem_index
<< (TLB_SHIFT
& 1)) |
1074 ((16 - (TLB_SHIFT
>> 1)) << 8));
1075 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_R1
, TCG_REG_R0
,
1076 offsetof(CPUState
, tlb_table
[0][0].addr_write
));
1077 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0, TCG_REG_R1
,
1078 TCG_REG_R8
, SHIFT_IMM_LSL(TARGET_PAGE_BITS
));
1079 /* Check alignment. */
1081 tcg_out_dat_imm(s
, COND_EQ
, ARITH_TST
,
1082 0, addr_reg
, (1 << s_bits
) - 1);
1083 # if TARGET_LONG_BITS == 64
1084 /* XXX: possibly we could use a block data load or writeback in
1085 * the first access. */
1086 tcg_out_ld32_12(s
, COND_EQ
, TCG_REG_R1
, TCG_REG_R0
,
1087 offsetof(CPUState
, tlb_table
[0][0].addr_write
) + 4);
1088 tcg_out_dat_reg(s
, COND_EQ
, ARITH_CMP
, 0,
1089 TCG_REG_R1
, addr_reg2
, SHIFT_IMM_LSL(0));
1091 tcg_out_ld32_12(s
, COND_EQ
, TCG_REG_R1
, TCG_REG_R0
,
1092 offsetof(CPUState
, tlb_table
[0][0].addend
));
1096 tcg_out_st8_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
1099 tcg_out_st16_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
1103 tcg_out_st32_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
1106 tcg_out_st32_rwb(s
, COND_EQ
, data_reg
, TCG_REG_R1
, addr_reg
);
1107 tcg_out_st32_12(s
, COND_EQ
, data_reg2
, TCG_REG_R1
, 4);
1111 label_ptr
= (void *) s
->code_ptr
;
1112 tcg_out_b(s
, COND_EQ
, 8);
1114 /* TODO: move this code to where the constants pool will be */
1115 if (addr_reg
!= TCG_REG_R0
) {
1116 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1117 TCG_REG_R0
, 0, addr_reg
, SHIFT_IMM_LSL(0));
1119 # if TARGET_LONG_BITS == 32
1122 tcg_out_dat_imm(s
, cond
, ARITH_AND
, TCG_REG_R1
, data_reg
, 0xff);
1123 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, TCG_REG_R2
, 0, mem_index
);
1126 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1127 TCG_REG_R1
, 0, data_reg
, SHIFT_IMM_LSL(16));
1128 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1129 TCG_REG_R1
, 0, TCG_REG_R1
, SHIFT_IMM_LSR(16));
1130 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, TCG_REG_R2
, 0, mem_index
);
1133 if (data_reg
!= TCG_REG_R1
) {
1134 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1135 TCG_REG_R1
, 0, data_reg
, SHIFT_IMM_LSL(0));
1137 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, TCG_REG_R2
, 0, mem_index
);
1140 if (data_reg
!= TCG_REG_R1
) {
1141 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1142 TCG_REG_R1
, 0, data_reg
, SHIFT_IMM_LSL(0));
1144 if (data_reg2
!= TCG_REG_R2
) {
1145 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1146 TCG_REG_R2
, 0, data_reg2
, SHIFT_IMM_LSL(0));
1148 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, TCG_REG_R3
, 0, mem_index
);
1152 if (addr_reg2
!= TCG_REG_R1
) {
1153 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1154 TCG_REG_R1
, 0, addr_reg2
, SHIFT_IMM_LSL(0));
1158 tcg_out_dat_imm(s
, cond
, ARITH_AND
, TCG_REG_R2
, data_reg
, 0xff);
1159 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, TCG_REG_R3
, 0, mem_index
);
1162 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1163 TCG_REG_R2
, 0, data_reg
, SHIFT_IMM_LSL(16));
1164 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1165 TCG_REG_R2
, 0, TCG_REG_R2
, SHIFT_IMM_LSR(16));
1166 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, TCG_REG_R3
, 0, mem_index
);
1169 if (data_reg
!= TCG_REG_R2
) {
1170 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1171 TCG_REG_R2
, 0, data_reg
, SHIFT_IMM_LSL(0));
1173 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, TCG_REG_R3
, 0, mem_index
);
1176 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, TCG_REG_R8
, 0, mem_index
);
1177 tcg_out32(s
, (cond
<< 28) | 0x052d8010); /* str r8, [sp, #-0x10]! */
1178 if (data_reg
!= TCG_REG_R2
) {
1179 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1180 TCG_REG_R2
, 0, data_reg
, SHIFT_IMM_LSL(0));
1182 if (data_reg2
!= TCG_REG_R3
) {
1183 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1184 TCG_REG_R3
, 0, data_reg2
, SHIFT_IMM_LSL(0));
1190 tcg_out_bl(s
, cond
, (tcg_target_long
) qemu_st_helpers
[s_bits
] -
1191 (tcg_target_long
) s
->code_ptr
);
1192 # if TARGET_LONG_BITS == 64
1194 tcg_out_dat_imm(s
, cond
, ARITH_ADD
, TCG_REG_R13
, TCG_REG_R13
, 0x10);
1197 *label_ptr
+= ((void *) s
->code_ptr
- (void *) label_ptr
- 8) >> 2;
1198 #else /* !CONFIG_SOFTMMU */
1200 uint32_t offset
= GUEST_BASE
;
1205 i
= ctz32(offset
) & ~1;
1206 rot
= ((32 - i
) << 7) & 0xf00;
1208 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, TCG_REG_R8
, addr_reg
,
1209 ((offset
>> i
) & 0xff) | rot
);
1210 addr_reg
= TCG_REG_R8
;
1211 offset
&= ~(0xff << i
);
1216 tcg_out_st8_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1219 tcg_out_st16_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
1223 tcg_out_st32_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1226 /* TODO: use block store -
1227 * check that data_reg2 > data_reg or the other way */
1228 tcg_out_st32_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1229 tcg_out_st32_12(s
, COND_AL
, data_reg2
, addr_reg
, 4);
1235 static uint8_t *tb_ret_addr
;
1237 static inline void tcg_out_op(TCGContext
*s
, TCGOpcode opc
,
1238 const TCGArg
*args
, const int *const_args
)
1243 case INDEX_op_exit_tb
:
1245 uint8_t *ld_ptr
= s
->code_ptr
;
1247 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_R0
, TCG_REG_PC
, 0);
1249 tcg_out_dat_imm(s
, COND_AL
, ARITH_MOV
, TCG_REG_R0
, 0, args
[0]);
1250 tcg_out_goto(s
, COND_AL
, (tcg_target_ulong
) tb_ret_addr
);
1252 *ld_ptr
= (uint8_t) (s
->code_ptr
- ld_ptr
) - 8;
1253 tcg_out32(s
, args
[0]);
1257 case INDEX_op_goto_tb
:
1258 if (s
->tb_jmp_offset
) {
1259 /* Direct jump method */
1260 #if defined(USE_DIRECT_JUMP)
1261 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1262 tcg_out_b(s
, COND_AL
, 8);
1264 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_PC
, -4);
1265 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1269 /* Indirect jump method */
1271 c
= (int) (s
->tb_next
+ args
[0]) - ((int) s
->code_ptr
+ 8);
1272 if (c
> 0xfff || c
< -0xfff) {
1273 tcg_out_movi32(s
, COND_AL
, TCG_REG_R0
,
1274 (tcg_target_long
) (s
->tb_next
+ args
[0]));
1275 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_R0
, 0);
1277 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_PC
, c
);
1279 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_R0
, TCG_REG_PC
, 0);
1280 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_R0
, 0);
1281 tcg_out32(s
, (tcg_target_long
) (s
->tb_next
+ args
[0]));
1284 s
->tb_next_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1288 tcg_out_call(s
, COND_AL
, args
[0]);
1290 tcg_out_callr(s
, COND_AL
, args
[0]);
1294 tcg_out_goto(s
, COND_AL
, args
[0]);
1296 tcg_out_bx(s
, COND_AL
, args
[0]);
1299 tcg_out_goto_label(s
, COND_AL
, args
[0]);
1302 case INDEX_op_ld8u_i32
:
1303 tcg_out_ld8u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1305 case INDEX_op_ld8s_i32
:
1306 tcg_out_ld8s(s
, COND_AL
, args
[0], args
[1], args
[2]);
1308 case INDEX_op_ld16u_i32
:
1309 tcg_out_ld16u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1311 case INDEX_op_ld16s_i32
:
1312 tcg_out_ld16s(s
, COND_AL
, args
[0], args
[1], args
[2]);
1314 case INDEX_op_ld_i32
:
1315 tcg_out_ld32u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1317 case INDEX_op_st8_i32
:
1318 tcg_out_st8(s
, COND_AL
, args
[0], args
[1], args
[2]);
1320 case INDEX_op_st16_i32
:
1321 tcg_out_st16(s
, COND_AL
, args
[0], args
[1], args
[2]);
1323 case INDEX_op_st_i32
:
1324 tcg_out_st32(s
, COND_AL
, args
[0], args
[1], args
[2]);
1327 case INDEX_op_mov_i32
:
1328 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1329 args
[0], 0, args
[1], SHIFT_IMM_LSL(0));
1331 case INDEX_op_movi_i32
:
1332 tcg_out_movi32(s
, COND_AL
, args
[0], args
[1]);
1334 case INDEX_op_add_i32
:
1337 case INDEX_op_sub_i32
:
1340 case INDEX_op_and_i32
:
1343 case INDEX_op_andc_i32
:
1346 case INDEX_op_or_i32
:
1349 case INDEX_op_xor_i32
:
1353 if (const_args
[2]) {
1355 rot
= encode_imm(args
[2]);
1356 tcg_out_dat_imm(s
, COND_AL
, c
,
1357 args
[0], args
[1], rotl(args
[2], rot
) | (rot
<< 7));
1359 tcg_out_dat_reg(s
, COND_AL
, c
,
1360 args
[0], args
[1], args
[2], SHIFT_IMM_LSL(0));
1362 case INDEX_op_add2_i32
:
1363 tcg_out_dat_reg2(s
, COND_AL
, ARITH_ADD
, ARITH_ADC
,
1364 args
[0], args
[1], args
[2], args
[3],
1365 args
[4], args
[5], SHIFT_IMM_LSL(0));
1367 case INDEX_op_sub2_i32
:
1368 tcg_out_dat_reg2(s
, COND_AL
, ARITH_SUB
, ARITH_SBC
,
1369 args
[0], args
[1], args
[2], args
[3],
1370 args
[4], args
[5], SHIFT_IMM_LSL(0));
1372 case INDEX_op_neg_i32
:
1373 tcg_out_dat_imm(s
, COND_AL
, ARITH_RSB
, args
[0], args
[1], 0);
1375 case INDEX_op_not_i32
:
1376 tcg_out_dat_reg(s
, COND_AL
,
1377 ARITH_MVN
, args
[0], 0, args
[1], SHIFT_IMM_LSL(0));
1379 case INDEX_op_mul_i32
:
1380 tcg_out_mul32(s
, COND_AL
, args
[0], args
[1], args
[2]);
1382 case INDEX_op_mulu2_i32
:
1383 tcg_out_umull32(s
, COND_AL
, args
[0], args
[1], args
[2], args
[3]);
1385 /* XXX: Perhaps args[2] & 0x1f is wrong */
1386 case INDEX_op_shl_i32
:
1388 SHIFT_IMM_LSL(args
[2] & 0x1f) : SHIFT_REG_LSL(args
[2]);
1390 case INDEX_op_shr_i32
:
1391 c
= const_args
[2] ? (args
[2] & 0x1f) ? SHIFT_IMM_LSR(args
[2] & 0x1f) :
1392 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args
[2]);
1394 case INDEX_op_sar_i32
:
1395 c
= const_args
[2] ? (args
[2] & 0x1f) ? SHIFT_IMM_ASR(args
[2] & 0x1f) :
1396 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args
[2]);
1399 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, args
[0], 0, args
[1], c
);
1402 case INDEX_op_brcond_i32
:
1403 if (const_args
[1]) {
1405 rot
= encode_imm(args
[1]);
1406 tcg_out_dat_imm(s
, COND_AL
, ARITH_CMP
, 0,
1407 args
[0], rotl(args
[1], rot
) | (rot
<< 7));
1409 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0,
1410 args
[0], args
[1], SHIFT_IMM_LSL(0));
1412 tcg_out_goto_label(s
, tcg_cond_to_arm_cond
[args
[2]], args
[3]);
1414 case INDEX_op_brcond2_i32
:
1415 /* The resulting conditions are:
1416 * TCG_COND_EQ --> a0 == a2 && a1 == a3,
1417 * TCG_COND_NE --> (a0 != a2 && a1 == a3) || a1 != a3,
1418 * TCG_COND_LT(U) --> (a0 < a2 && a1 == a3) || a1 < a3,
1419 * TCG_COND_GE(U) --> (a0 >= a2 && a1 == a3) || (a1 >= a3 && a1 != a3),
1420 * TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3),
1421 * TCG_COND_GT(U) --> (a0 > a2 && a1 == a3) || a1 > a3,
1423 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0,
1424 args
[1], args
[3], SHIFT_IMM_LSL(0));
1425 tcg_out_dat_reg(s
, COND_EQ
, ARITH_CMP
, 0,
1426 args
[0], args
[2], SHIFT_IMM_LSL(0));
1427 tcg_out_goto_label(s
, tcg_cond_to_arm_cond
[args
[4]], args
[5]);
1429 case INDEX_op_setcond_i32
:
1430 if (const_args
[2]) {
1432 rot
= encode_imm(args
[2]);
1433 tcg_out_dat_imm(s
, COND_AL
, ARITH_CMP
, 0,
1434 args
[1], rotl(args
[2], rot
) | (rot
<< 7));
1436 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0,
1437 args
[1], args
[2], SHIFT_IMM_LSL(0));
1439 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[args
[3]],
1440 ARITH_MOV
, args
[0], 0, 1);
1441 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[tcg_invert_cond(args
[3])],
1442 ARITH_MOV
, args
[0], 0, 0);
1444 case INDEX_op_setcond2_i32
:
1445 /* See brcond2_i32 comment */
1446 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0,
1447 args
[2], args
[4], SHIFT_IMM_LSL(0));
1448 tcg_out_dat_reg(s
, COND_EQ
, ARITH_CMP
, 0,
1449 args
[1], args
[3], SHIFT_IMM_LSL(0));
1450 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[args
[5]],
1451 ARITH_MOV
, args
[0], 0, 1);
1452 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[tcg_invert_cond(args
[5])],
1453 ARITH_MOV
, args
[0], 0, 0);
1456 case INDEX_op_qemu_ld8u
:
1457 tcg_out_qemu_ld(s
, COND_AL
, args
, 0);
1459 case INDEX_op_qemu_ld8s
:
1460 tcg_out_qemu_ld(s
, COND_AL
, args
, 0 | 4);
1462 case INDEX_op_qemu_ld16u
:
1463 tcg_out_qemu_ld(s
, COND_AL
, args
, 1);
1465 case INDEX_op_qemu_ld16s
:
1466 tcg_out_qemu_ld(s
, COND_AL
, args
, 1 | 4);
1468 case INDEX_op_qemu_ld32
:
1469 tcg_out_qemu_ld(s
, COND_AL
, args
, 2);
1471 case INDEX_op_qemu_ld64
:
1472 tcg_out_qemu_ld(s
, COND_AL
, args
, 3);
1475 case INDEX_op_qemu_st8
:
1476 tcg_out_qemu_st(s
, COND_AL
, args
, 0);
1478 case INDEX_op_qemu_st16
:
1479 tcg_out_qemu_st(s
, COND_AL
, args
, 1);
1481 case INDEX_op_qemu_st32
:
1482 tcg_out_qemu_st(s
, COND_AL
, args
, 2);
1484 case INDEX_op_qemu_st64
:
1485 tcg_out_qemu_st(s
, COND_AL
, args
, 3);
1488 case INDEX_op_ext8s_i32
:
1489 if (use_armv6_instructions
) {
1491 tcg_out32(s
, 0xe6af0070 | (args
[0] << 12) | args
[1]);
1493 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1494 args
[0], 0, args
[1], SHIFT_IMM_LSL(24));
1495 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1496 args
[0], 0, args
[0], SHIFT_IMM_ASR(24));
1499 case INDEX_op_ext16s_i32
:
1500 if (use_armv6_instructions
) {
1502 tcg_out32(s
, 0xe6bf0070 | (args
[0] << 12) | args
[1]);
1504 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1505 args
[0], 0, args
[1], SHIFT_IMM_LSL(16));
1506 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1507 args
[0], 0, args
[0], SHIFT_IMM_ASR(16));
1516 static const TCGTargetOpDef arm_op_defs
[] = {
1517 { INDEX_op_exit_tb
, { } },
1518 { INDEX_op_goto_tb
, { } },
1519 { INDEX_op_call
, { "ri" } },
1520 { INDEX_op_jmp
, { "ri" } },
1521 { INDEX_op_br
, { } },
1523 { INDEX_op_mov_i32
, { "r", "r" } },
1524 { INDEX_op_movi_i32
, { "r" } },
1526 { INDEX_op_ld8u_i32
, { "r", "r" } },
1527 { INDEX_op_ld8s_i32
, { "r", "r" } },
1528 { INDEX_op_ld16u_i32
, { "r", "r" } },
1529 { INDEX_op_ld16s_i32
, { "r", "r" } },
1530 { INDEX_op_ld_i32
, { "r", "r" } },
1531 { INDEX_op_st8_i32
, { "r", "r" } },
1532 { INDEX_op_st16_i32
, { "r", "r" } },
1533 { INDEX_op_st_i32
, { "r", "r" } },
1535 /* TODO: "r", "r", "ri" */
1536 { INDEX_op_add_i32
, { "r", "r", "rI" } },
1537 { INDEX_op_sub_i32
, { "r", "r", "rI" } },
1538 { INDEX_op_mul_i32
, { "r", "r", "r" } },
1539 { INDEX_op_mulu2_i32
, { "r", "r", "r", "r" } },
1540 { INDEX_op_and_i32
, { "r", "r", "rI" } },
1541 { INDEX_op_andc_i32
, { "r", "r", "rI" } },
1542 { INDEX_op_or_i32
, { "r", "r", "rI" } },
1543 { INDEX_op_xor_i32
, { "r", "r", "rI" } },
1544 { INDEX_op_neg_i32
, { "r", "r" } },
1545 { INDEX_op_not_i32
, { "r", "r" } },
1547 { INDEX_op_shl_i32
, { "r", "r", "ri" } },
1548 { INDEX_op_shr_i32
, { "r", "r", "ri" } },
1549 { INDEX_op_sar_i32
, { "r", "r", "ri" } },
1551 { INDEX_op_brcond_i32
, { "r", "rI" } },
1552 { INDEX_op_setcond_i32
, { "r", "r", "rI" } },
1554 /* TODO: "r", "r", "r", "r", "ri", "ri" */
1555 { INDEX_op_add2_i32
, { "r", "r", "r", "r", "r", "r" } },
1556 { INDEX_op_sub2_i32
, { "r", "r", "r", "r", "r", "r" } },
1557 { INDEX_op_brcond2_i32
, { "r", "r", "r", "r" } },
1558 { INDEX_op_setcond2_i32
, { "r", "r", "r", "r", "r" } },
1560 #if TARGET_LONG_BITS == 32
1561 { INDEX_op_qemu_ld8u
, { "r", "x" } },
1562 { INDEX_op_qemu_ld8s
, { "r", "x" } },
1563 { INDEX_op_qemu_ld16u
, { "r", "x" } },
1564 { INDEX_op_qemu_ld16s
, { "r", "x" } },
1565 { INDEX_op_qemu_ld32
, { "r", "x" } },
1566 { INDEX_op_qemu_ld64
, { "d", "r", "x" } },
1568 { INDEX_op_qemu_st8
, { "x", "x" } },
1569 { INDEX_op_qemu_st16
, { "x", "x" } },
1570 { INDEX_op_qemu_st32
, { "x", "x" } },
1571 { INDEX_op_qemu_st64
, { "x", "D", "x" } },
1573 { INDEX_op_qemu_ld8u
, { "r", "x", "X" } },
1574 { INDEX_op_qemu_ld8s
, { "r", "x", "X" } },
1575 { INDEX_op_qemu_ld16u
, { "r", "x", "X" } },
1576 { INDEX_op_qemu_ld16s
, { "r", "x", "X" } },
1577 { INDEX_op_qemu_ld32
, { "r", "x", "X" } },
1578 { INDEX_op_qemu_ld64
, { "d", "r", "x", "X" } },
1580 { INDEX_op_qemu_st8
, { "x", "x", "X" } },
1581 { INDEX_op_qemu_st16
, { "x", "x", "X" } },
1582 { INDEX_op_qemu_st32
, { "x", "x", "X" } },
1583 { INDEX_op_qemu_st64
, { "x", "D", "x", "X" } },
1586 { INDEX_op_ext8s_i32
, { "r", "r" } },
1587 { INDEX_op_ext16s_i32
, { "r", "r" } },
1592 void tcg_target_init(TCGContext
*s
)
1594 #if !defined(CONFIG_USER_ONLY)
1596 if ((1 << CPU_TLB_ENTRY_BITS
) != sizeof(CPUTLBEntry
))
1600 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I32
], 0, 0xffff);
1601 tcg_regset_set32(tcg_target_call_clobber_regs
, 0,
1606 (1 << TCG_REG_R12
) |
1607 (1 << TCG_REG_R14
));
1609 tcg_regset_clear(s
->reserved_regs
);
1610 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_CALL_STACK
);
1611 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R8
);
1612 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_PC
);
1614 tcg_add_target_add_op_defs(arm_op_defs
);
1617 static inline void tcg_out_ld(TCGContext
*s
, TCGType type
, int arg
,
1618 int arg1
, tcg_target_long arg2
)
1620 tcg_out_ld32u(s
, COND_AL
, arg
, arg1
, arg2
);
1623 static inline void tcg_out_st(TCGContext
*s
, TCGType type
, int arg
,
1624 int arg1
, tcg_target_long arg2
)
1626 tcg_out_st32(s
, COND_AL
, arg
, arg1
, arg2
);
1629 static void tcg_out_addi(TCGContext
*s
, int reg
, tcg_target_long val
)
1633 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, reg
, reg
, val
);
1638 tcg_out_dat_imm(s
, COND_AL
, ARITH_SUB
, reg
, reg
, -val
);
1644 static inline void tcg_out_mov(TCGContext
*s
, int ret
, int arg
)
1646 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, ret
, 0, arg
, SHIFT_IMM_LSL(0));
1649 static inline void tcg_out_movi(TCGContext
*s
, TCGType type
,
1650 int ret
, tcg_target_long arg
)
1652 tcg_out_movi32(s
, COND_AL
, ret
, arg
);
1655 void tcg_target_qemu_prologue(TCGContext
*s
)
1657 /* There is no need to save r7, it is used to store the address
1658 of the env structure and is not modified by GCC. */
1660 /* stmdb sp!, { r4 - r6, r8 - r11, lr } */
1661 tcg_out32(s
, (COND_AL
<< 28) | 0x092d4f70);
1663 tcg_out_bx(s
, COND_AL
, TCG_REG_R0
);
1664 tb_ret_addr
= s
->code_ptr
;
1666 /* ldmia sp!, { r4 - r6, r8 - r11, pc } */
1667 tcg_out32(s
, (COND_AL
<< 28) | 0x08bd8f70);