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tcg/arm: add bswap ops
[mirror_qemu.git] / tcg / arm / tcg-target.c
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Andrzej Zaborowski
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #if defined(__ARM_ARCH_7__) || \
26 defined(__ARM_ARCH_7A__) || \
27 defined(__ARM_ARCH_7EM__) || \
28 defined(__ARM_ARCH_7M__) || \
29 defined(__ARM_ARCH_7R__)
30 #define USE_ARMV7_INSTRUCTIONS
31 #endif
32
33 #if defined(USE_ARMV7_INSTRUCTIONS) || \
34 defined(__ARM_ARCH_6J__) || \
35 defined(__ARM_ARCH_6K__) || \
36 defined(__ARM_ARCH_6T2__) || \
37 defined(__ARM_ARCH_6Z__) || \
38 defined(__ARM_ARCH_6ZK__)
39 #define USE_ARMV6_INSTRUCTIONS
40 #endif
41
42 #if defined(USE_ARMV6_INSTRUCTIONS) || \
43 defined(__ARM_ARCH_5T__) || \
44 defined(__ARM_ARCH_5TE__) || \
45 defined(__ARM_ARCH_5TEJ__)
46 #define USE_ARMV5_INSTRUCTIONS
47 #endif
48
49 #ifdef USE_ARMV5_INSTRUCTIONS
50 static const int use_armv5_instructions = 1;
51 #else
52 static const int use_armv5_instructions = 0;
53 #endif
54 #undef USE_ARMV5_INSTRUCTIONS
55
56 #ifdef USE_ARMV6_INSTRUCTIONS
57 static const int use_armv6_instructions = 1;
58 #else
59 static const int use_armv6_instructions = 0;
60 #endif
61 #undef USE_ARMV6_INSTRUCTIONS
62
63 #ifdef USE_ARMV7_INSTRUCTIONS
64 static const int use_armv7_instructions = 1;
65 #else
66 static const int use_armv7_instructions = 0;
67 #endif
68 #undef USE_ARMV7_INSTRUCTIONS
69
70 #ifndef NDEBUG
71 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
72 "%r0",
73 "%r1",
74 "%r2",
75 "%r3",
76 "%r4",
77 "%r5",
78 "%r6",
79 "%r7",
80 "%r8",
81 "%r9",
82 "%r10",
83 "%r11",
84 "%r12",
85 "%r13",
86 "%r14",
87 "%pc",
88 };
89 #endif
90
91 static const int tcg_target_reg_alloc_order[] = {
92 TCG_REG_R0,
93 TCG_REG_R1,
94 TCG_REG_R2,
95 TCG_REG_R3,
96 TCG_REG_R4,
97 TCG_REG_R5,
98 TCG_REG_R6,
99 TCG_REG_R7,
100 TCG_REG_R8,
101 TCG_REG_R9,
102 TCG_REG_R10,
103 TCG_REG_R11,
104 TCG_REG_R12,
105 TCG_REG_R13,
106 TCG_REG_R14,
107 };
108
109 static const int tcg_target_call_iarg_regs[4] = {
110 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3
111 };
112 static const int tcg_target_call_oarg_regs[2] = {
113 TCG_REG_R0, TCG_REG_R1
114 };
115
116 static void patch_reloc(uint8_t *code_ptr, int type,
117 tcg_target_long value, tcg_target_long addend)
118 {
119 switch (type) {
120 case R_ARM_ABS32:
121 *(uint32_t *) code_ptr = value;
122 break;
123
124 case R_ARM_CALL:
125 case R_ARM_JUMP24:
126 default:
127 tcg_abort();
128
129 case R_ARM_PC24:
130 *(uint32_t *) code_ptr = ((*(uint32_t *) code_ptr) & 0xff000000) |
131 (((value - ((tcg_target_long) code_ptr + 8)) >> 2) & 0xffffff);
132 break;
133 }
134 }
135
136 /* maximum number of register used for input function arguments */
137 static inline int tcg_target_get_call_iarg_regs_count(int flags)
138 {
139 return 4;
140 }
141
142 /* parse target specific constraints */
143 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
144 {
145 const char *ct_str;
146
147 ct_str = *pct_str;
148 switch (ct_str[0]) {
149 case 'I':
150 ct->ct |= TCG_CT_CONST_ARM;
151 break;
152
153 case 'r':
154 #ifndef CONFIG_SOFTMMU
155 case 'd':
156 case 'D':
157 case 'x':
158 case 'X':
159 #endif
160 ct->ct |= TCG_CT_REG;
161 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
162 break;
163
164 #ifdef CONFIG_SOFTMMU
165 /* qemu_ld/st inputs (unless 'X', 'd' or 'D') */
166 case 'x':
167 ct->ct |= TCG_CT_REG;
168 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
169 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
170 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
171 break;
172
173 /* qemu_ld64 data_reg */
174 case 'd':
175 ct->ct |= TCG_CT_REG;
176 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
177 /* r1 is still needed to load data_reg2, so don't use it. */
178 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
179 break;
180
181 /* qemu_ld/st64 data_reg2 */
182 case 'D':
183 ct->ct |= TCG_CT_REG;
184 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
185 /* r0, r1 and optionally r2 will be overwritten by the address
186 * and the low word of data, so don't use these. */
187 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
188 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
189 # if TARGET_LONG_BITS == 64
190 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
191 # endif
192 break;
193
194 # if TARGET_LONG_BITS == 64
195 /* qemu_ld/st addr_reg2 */
196 case 'X':
197 ct->ct |= TCG_CT_REG;
198 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
199 /* r0 will be overwritten by the low word of base, so don't use it. */
200 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
201 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
202 break;
203 # endif
204 #endif
205
206 default:
207 return -1;
208 }
209 ct_str++;
210 *pct_str = ct_str;
211
212 return 0;
213 }
214
215 static inline uint32_t rotl(uint32_t val, int n)
216 {
217 return (val << n) | (val >> (32 - n));
218 }
219
220 /* ARM immediates for ALU instructions are made of an unsigned 8-bit
221 right-rotated by an even amount between 0 and 30. */
222 static inline int encode_imm(uint32_t imm)
223 {
224 int shift;
225
226 /* simple case, only lower bits */
227 if ((imm & ~0xff) == 0)
228 return 0;
229 /* then try a simple even shift */
230 shift = ctz32(imm) & ~1;
231 if (((imm >> shift) & ~0xff) == 0)
232 return 32 - shift;
233 /* now try harder with rotations */
234 if ((rotl(imm, 2) & ~0xff) == 0)
235 return 2;
236 if ((rotl(imm, 4) & ~0xff) == 0)
237 return 4;
238 if ((rotl(imm, 6) & ~0xff) == 0)
239 return 6;
240 /* imm can't be encoded */
241 return -1;
242 }
243
244 static inline int check_fit_imm(uint32_t imm)
245 {
246 return encode_imm(imm) >= 0;
247 }
248
249 /* Test if a constant matches the constraint.
250 * TODO: define constraints for:
251 *
252 * ldr/str offset: between -0xfff and 0xfff
253 * ldrh/strh offset: between -0xff and 0xff
254 * mov operand2: values represented with x << (2 * y), x < 0x100
255 * add, sub, eor...: ditto
256 */
257 static inline int tcg_target_const_match(tcg_target_long val,
258 const TCGArgConstraint *arg_ct)
259 {
260 int ct;
261 ct = arg_ct->ct;
262 if (ct & TCG_CT_CONST)
263 return 1;
264 else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val))
265 return 1;
266 else
267 return 0;
268 }
269
270 enum arm_data_opc_e {
271 ARITH_AND = 0x0,
272 ARITH_EOR = 0x1,
273 ARITH_SUB = 0x2,
274 ARITH_RSB = 0x3,
275 ARITH_ADD = 0x4,
276 ARITH_ADC = 0x5,
277 ARITH_SBC = 0x6,
278 ARITH_RSC = 0x7,
279 ARITH_TST = 0x8,
280 ARITH_CMP = 0xa,
281 ARITH_CMN = 0xb,
282 ARITH_ORR = 0xc,
283 ARITH_MOV = 0xd,
284 ARITH_BIC = 0xe,
285 ARITH_MVN = 0xf,
286 };
287
288 #define TO_CPSR(opc) \
289 ((opc == ARITH_CMP || opc == ARITH_CMN || opc == ARITH_TST) << 20)
290
291 #define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
292 #define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20)
293 #define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40)
294 #define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60)
295 #define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10)
296 #define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30)
297 #define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50)
298 #define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70)
299
300 enum arm_cond_code_e {
301 COND_EQ = 0x0,
302 COND_NE = 0x1,
303 COND_CS = 0x2, /* Unsigned greater or equal */
304 COND_CC = 0x3, /* Unsigned less than */
305 COND_MI = 0x4, /* Negative */
306 COND_PL = 0x5, /* Zero or greater */
307 COND_VS = 0x6, /* Overflow */
308 COND_VC = 0x7, /* No overflow */
309 COND_HI = 0x8, /* Unsigned greater than */
310 COND_LS = 0x9, /* Unsigned less or equal */
311 COND_GE = 0xa,
312 COND_LT = 0xb,
313 COND_GT = 0xc,
314 COND_LE = 0xd,
315 COND_AL = 0xe,
316 };
317
318 static const uint8_t tcg_cond_to_arm_cond[10] = {
319 [TCG_COND_EQ] = COND_EQ,
320 [TCG_COND_NE] = COND_NE,
321 [TCG_COND_LT] = COND_LT,
322 [TCG_COND_GE] = COND_GE,
323 [TCG_COND_LE] = COND_LE,
324 [TCG_COND_GT] = COND_GT,
325 /* unsigned */
326 [TCG_COND_LTU] = COND_CC,
327 [TCG_COND_GEU] = COND_CS,
328 [TCG_COND_LEU] = COND_LS,
329 [TCG_COND_GTU] = COND_HI,
330 };
331
332 static inline void tcg_out_bx(TCGContext *s, int cond, int rn)
333 {
334 tcg_out32(s, (cond << 28) | 0x012fff10 | rn);
335 }
336
337 static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset)
338 {
339 tcg_out32(s, (cond << 28) | 0x0a000000 |
340 (((offset - 8) >> 2) & 0x00ffffff));
341 }
342
343 static inline void tcg_out_b_noaddr(TCGContext *s, int cond)
344 {
345 #ifdef HOST_WORDS_BIGENDIAN
346 tcg_out8(s, (cond << 4) | 0x0a);
347 s->code_ptr += 3;
348 #else
349 s->code_ptr += 3;
350 tcg_out8(s, (cond << 4) | 0x0a);
351 #endif
352 }
353
354 static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset)
355 {
356 tcg_out32(s, (cond << 28) | 0x0b000000 |
357 (((offset - 8) >> 2) & 0x00ffffff));
358 }
359
360 static inline void tcg_out_blx(TCGContext *s, int cond, int rn)
361 {
362 tcg_out32(s, (cond << 28) | 0x012fff30 | rn);
363 }
364
365 static inline void tcg_out_dat_reg(TCGContext *s,
366 int cond, int opc, int rd, int rn, int rm, int shift)
367 {
368 tcg_out32(s, (cond << 28) | (0 << 25) | (opc << 21) | TO_CPSR(opc) |
369 (rn << 16) | (rd << 12) | shift | rm);
370 }
371
372 static inline void tcg_out_dat_reg2(TCGContext *s,
373 int cond, int opc0, int opc1, int rd0, int rd1,
374 int rn0, int rn1, int rm0, int rm1, int shift)
375 {
376 if (rd0 == rn1 || rd0 == rm1) {
377 tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
378 (rn0 << 16) | (8 << 12) | shift | rm0);
379 tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
380 (rn1 << 16) | (rd1 << 12) | shift | rm1);
381 tcg_out_dat_reg(s, cond, ARITH_MOV,
382 rd0, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
383 } else {
384 tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
385 (rn0 << 16) | (rd0 << 12) | shift | rm0);
386 tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
387 (rn1 << 16) | (rd1 << 12) | shift | rm1);
388 }
389 }
390
391 static inline void tcg_out_dat_imm(TCGContext *s,
392 int cond, int opc, int rd, int rn, int im)
393 {
394 tcg_out32(s, (cond << 28) | (1 << 25) | (opc << 21) | TO_CPSR(opc) |
395 (rn << 16) | (rd << 12) | im);
396 }
397
398 static inline void tcg_out_movi32(TCGContext *s,
399 int cond, int rd, int32_t arg)
400 {
401 int offset = (uint32_t) arg - ((uint32_t) s->code_ptr + 8);
402
403 /* TODO: This is very suboptimal, we can easily have a constant
404 * pool somewhere after all the instructions. */
405
406 if (arg < 0 && arg > -0x100)
407 return tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, (~arg) & 0xff);
408
409 if (offset < 0x100 && offset > -0x100)
410 return offset >= 0 ?
411 tcg_out_dat_imm(s, cond, ARITH_ADD, rd, 15, offset) :
412 tcg_out_dat_imm(s, cond, ARITH_SUB, rd, 15, -offset);
413
414 if (use_armv7_instructions) {
415 /* use movw/movt */
416 /* movw */
417 tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12)
418 | ((arg << 4) & 0x000f0000) | (arg & 0xfff));
419 if (arg & 0xffff0000)
420 /* movt */
421 tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12)
422 | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff));
423 } else {
424 tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, arg & 0xff);
425 if (arg & 0x0000ff00)
426 tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
427 ((arg >> 8) & 0xff) | 0xc00);
428 if (arg & 0x00ff0000)
429 tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
430 ((arg >> 16) & 0xff) | 0x800);
431 if (arg & 0xff000000)
432 tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
433 ((arg >> 24) & 0xff) | 0x400);
434 }
435 }
436
437 static inline void tcg_out_mul32(TCGContext *s,
438 int cond, int rd, int rs, int rm)
439 {
440 if (rd != rm)
441 tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
442 (rs << 8) | 0x90 | rm);
443 else if (rd != rs)
444 tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
445 (rm << 8) | 0x90 | rs);
446 else {
447 tcg_out32(s, (cond << 28) | ( 8 << 16) | (0 << 12) |
448 (rs << 8) | 0x90 | rm);
449 tcg_out_dat_reg(s, cond, ARITH_MOV,
450 rd, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
451 }
452 }
453
454 static inline void tcg_out_umull32(TCGContext *s,
455 int cond, int rd0, int rd1, int rs, int rm)
456 {
457 if (rd0 != rm && rd1 != rm)
458 tcg_out32(s, (cond << 28) | 0x800090 |
459 (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
460 else if (rd0 != rs && rd1 != rs)
461 tcg_out32(s, (cond << 28) | 0x800090 |
462 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
463 else {
464 tcg_out_dat_reg(s, cond, ARITH_MOV,
465 TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
466 tcg_out32(s, (cond << 28) | 0x800098 |
467 (rd1 << 16) | (rd0 << 12) | (rs << 8));
468 }
469 }
470
471 static inline void tcg_out_smull32(TCGContext *s,
472 int cond, int rd0, int rd1, int rs, int rm)
473 {
474 if (rd0 != rm && rd1 != rm)
475 tcg_out32(s, (cond << 28) | 0xc00090 |
476 (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
477 else if (rd0 != rs && rd1 != rs)
478 tcg_out32(s, (cond << 28) | 0xc00090 |
479 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
480 else {
481 tcg_out_dat_reg(s, cond, ARITH_MOV,
482 TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
483 tcg_out32(s, (cond << 28) | 0xc00098 |
484 (rd1 << 16) | (rd0 << 12) | (rs << 8));
485 }
486 }
487
488 static inline void tcg_out_ext8s(TCGContext *s, int cond,
489 int rd, int rn)
490 {
491 if (use_armv6_instructions) {
492 /* sxtb */
493 tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | rn);
494 } else {
495 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
496 rd, 0, rn, SHIFT_IMM_LSL(24));
497 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
498 rd, 0, rd, SHIFT_IMM_ASR(24));
499 }
500 }
501
502 static inline void tcg_out_ext16s(TCGContext *s, int cond,
503 int rd, int rn)
504 {
505 if (use_armv6_instructions) {
506 /* sxth */
507 tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | rn);
508 } else {
509 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
510 rd, 0, rn, SHIFT_IMM_LSL(16));
511 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
512 rd, 0, rd, SHIFT_IMM_ASR(16));
513 }
514 }
515
516 static inline void tcg_out_ext16u(TCGContext *s, int cond,
517 int rd, int rn)
518 {
519 if (use_armv6_instructions) {
520 /* uxth */
521 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rn);
522 } else {
523 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
524 rd, 0, rn, SHIFT_IMM_LSL(16));
525 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
526 rd, 0, rd, SHIFT_IMM_LSR(16));
527 }
528 }
529
530 static inline void tcg_out_bswap16(TCGContext *s, int cond, int rd, int rn)
531 {
532 if (use_armv6_instructions) {
533 /* rev16 */
534 tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn);
535 } else {
536 tcg_out_dat_reg(s, cond, ARITH_MOV,
537 TCG_REG_R8, 0, rn, SHIFT_IMM_LSL(24));
538 tcg_out_dat_reg(s, cond, ARITH_MOV,
539 TCG_REG_R8, 0, TCG_REG_R8, SHIFT_IMM_LSR(16));
540 tcg_out_dat_reg(s, cond, ARITH_ORR,
541 rd, TCG_REG_R8, rn, SHIFT_IMM_LSR(8));
542 }
543 }
544
545 static inline void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn)
546 {
547 if (use_armv6_instructions) {
548 /* rev */
549 tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn);
550 } else {
551 tcg_out_dat_reg(s, cond, ARITH_EOR,
552 TCG_REG_R8, rn, rn, SHIFT_IMM_ROR(16));
553 tcg_out_dat_imm(s, cond, ARITH_BIC,
554 TCG_REG_R8, TCG_REG_R8, 0xff | 0x800);
555 tcg_out_dat_reg(s, cond, ARITH_MOV,
556 rd, 0, rn, SHIFT_IMM_ROR(8));
557 tcg_out_dat_reg(s, cond, ARITH_EOR,
558 rd, rd, TCG_REG_R8, SHIFT_IMM_LSR(8));
559 }
560 }
561
562 static inline void tcg_out_ld32_12(TCGContext *s, int cond,
563 int rd, int rn, tcg_target_long im)
564 {
565 if (im >= 0)
566 tcg_out32(s, (cond << 28) | 0x05900000 |
567 (rn << 16) | (rd << 12) | (im & 0xfff));
568 else
569 tcg_out32(s, (cond << 28) | 0x05100000 |
570 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
571 }
572
573 static inline void tcg_out_st32_12(TCGContext *s, int cond,
574 int rd, int rn, tcg_target_long im)
575 {
576 if (im >= 0)
577 tcg_out32(s, (cond << 28) | 0x05800000 |
578 (rn << 16) | (rd << 12) | (im & 0xfff));
579 else
580 tcg_out32(s, (cond << 28) | 0x05000000 |
581 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
582 }
583
584 static inline void tcg_out_ld32_r(TCGContext *s, int cond,
585 int rd, int rn, int rm)
586 {
587 tcg_out32(s, (cond << 28) | 0x07900000 |
588 (rn << 16) | (rd << 12) | rm);
589 }
590
591 static inline void tcg_out_st32_r(TCGContext *s, int cond,
592 int rd, int rn, int rm)
593 {
594 tcg_out32(s, (cond << 28) | 0x07800000 |
595 (rn << 16) | (rd << 12) | rm);
596 }
597
598 /* Register pre-increment with base writeback. */
599 static inline void tcg_out_ld32_rwb(TCGContext *s, int cond,
600 int rd, int rn, int rm)
601 {
602 tcg_out32(s, (cond << 28) | 0x07b00000 |
603 (rn << 16) | (rd << 12) | rm);
604 }
605
606 static inline void tcg_out_st32_rwb(TCGContext *s, int cond,
607 int rd, int rn, int rm)
608 {
609 tcg_out32(s, (cond << 28) | 0x07a00000 |
610 (rn << 16) | (rd << 12) | rm);
611 }
612
613 static inline void tcg_out_ld16u_8(TCGContext *s, int cond,
614 int rd, int rn, tcg_target_long im)
615 {
616 if (im >= 0)
617 tcg_out32(s, (cond << 28) | 0x01d000b0 |
618 (rn << 16) | (rd << 12) |
619 ((im & 0xf0) << 4) | (im & 0xf));
620 else
621 tcg_out32(s, (cond << 28) | 0x015000b0 |
622 (rn << 16) | (rd << 12) |
623 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
624 }
625
626 static inline void tcg_out_st16_8(TCGContext *s, int cond,
627 int rd, int rn, tcg_target_long im)
628 {
629 if (im >= 0)
630 tcg_out32(s, (cond << 28) | 0x01c000b0 |
631 (rn << 16) | (rd << 12) |
632 ((im & 0xf0) << 4) | (im & 0xf));
633 else
634 tcg_out32(s, (cond << 28) | 0x014000b0 |
635 (rn << 16) | (rd << 12) |
636 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
637 }
638
639 static inline void tcg_out_ld16u_r(TCGContext *s, int cond,
640 int rd, int rn, int rm)
641 {
642 tcg_out32(s, (cond << 28) | 0x019000b0 |
643 (rn << 16) | (rd << 12) | rm);
644 }
645
646 static inline void tcg_out_st16_r(TCGContext *s, int cond,
647 int rd, int rn, int rm)
648 {
649 tcg_out32(s, (cond << 28) | 0x018000b0 |
650 (rn << 16) | (rd << 12) | rm);
651 }
652
653 static inline void tcg_out_ld16s_8(TCGContext *s, int cond,
654 int rd, int rn, tcg_target_long im)
655 {
656 if (im >= 0)
657 tcg_out32(s, (cond << 28) | 0x01d000f0 |
658 (rn << 16) | (rd << 12) |
659 ((im & 0xf0) << 4) | (im & 0xf));
660 else
661 tcg_out32(s, (cond << 28) | 0x015000f0 |
662 (rn << 16) | (rd << 12) |
663 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
664 }
665
666 static inline void tcg_out_ld16s_r(TCGContext *s, int cond,
667 int rd, int rn, int rm)
668 {
669 tcg_out32(s, (cond << 28) | 0x019000f0 |
670 (rn << 16) | (rd << 12) | rm);
671 }
672
673 static inline void tcg_out_ld8_12(TCGContext *s, int cond,
674 int rd, int rn, tcg_target_long im)
675 {
676 if (im >= 0)
677 tcg_out32(s, (cond << 28) | 0x05d00000 |
678 (rn << 16) | (rd << 12) | (im & 0xfff));
679 else
680 tcg_out32(s, (cond << 28) | 0x05500000 |
681 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
682 }
683
684 static inline void tcg_out_st8_12(TCGContext *s, int cond,
685 int rd, int rn, tcg_target_long im)
686 {
687 if (im >= 0)
688 tcg_out32(s, (cond << 28) | 0x05c00000 |
689 (rn << 16) | (rd << 12) | (im & 0xfff));
690 else
691 tcg_out32(s, (cond << 28) | 0x05400000 |
692 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
693 }
694
695 static inline void tcg_out_ld8_r(TCGContext *s, int cond,
696 int rd, int rn, int rm)
697 {
698 tcg_out32(s, (cond << 28) | 0x07d00000 |
699 (rn << 16) | (rd << 12) | rm);
700 }
701
702 static inline void tcg_out_st8_r(TCGContext *s, int cond,
703 int rd, int rn, int rm)
704 {
705 tcg_out32(s, (cond << 28) | 0x07c00000 |
706 (rn << 16) | (rd << 12) | rm);
707 }
708
709 static inline void tcg_out_ld8s_8(TCGContext *s, int cond,
710 int rd, int rn, tcg_target_long im)
711 {
712 if (im >= 0)
713 tcg_out32(s, (cond << 28) | 0x01d000d0 |
714 (rn << 16) | (rd << 12) |
715 ((im & 0xf0) << 4) | (im & 0xf));
716 else
717 tcg_out32(s, (cond << 28) | 0x015000d0 |
718 (rn << 16) | (rd << 12) |
719 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
720 }
721
722 static inline void tcg_out_ld8s_r(TCGContext *s, int cond,
723 int rd, int rn, int rm)
724 {
725 tcg_out32(s, (cond << 28) | 0x019000d0 |
726 (rn << 16) | (rd << 12) | rm);
727 }
728
729 static inline void tcg_out_ld32u(TCGContext *s, int cond,
730 int rd, int rn, int32_t offset)
731 {
732 if (offset > 0xfff || offset < -0xfff) {
733 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
734 tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_R8);
735 } else
736 tcg_out_ld32_12(s, cond, rd, rn, offset);
737 }
738
739 static inline void tcg_out_st32(TCGContext *s, int cond,
740 int rd, int rn, int32_t offset)
741 {
742 if (offset > 0xfff || offset < -0xfff) {
743 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
744 tcg_out_st32_r(s, cond, rd, rn, TCG_REG_R8);
745 } else
746 tcg_out_st32_12(s, cond, rd, rn, offset);
747 }
748
749 static inline void tcg_out_ld16u(TCGContext *s, int cond,
750 int rd, int rn, int32_t offset)
751 {
752 if (offset > 0xff || offset < -0xff) {
753 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
754 tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_R8);
755 } else
756 tcg_out_ld16u_8(s, cond, rd, rn, offset);
757 }
758
759 static inline void tcg_out_ld16s(TCGContext *s, int cond,
760 int rd, int rn, int32_t offset)
761 {
762 if (offset > 0xff || offset < -0xff) {
763 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
764 tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_R8);
765 } else
766 tcg_out_ld16s_8(s, cond, rd, rn, offset);
767 }
768
769 static inline void tcg_out_st16(TCGContext *s, int cond,
770 int rd, int rn, int32_t offset)
771 {
772 if (offset > 0xff || offset < -0xff) {
773 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
774 tcg_out_st16_r(s, cond, rd, rn, TCG_REG_R8);
775 } else
776 tcg_out_st16_8(s, cond, rd, rn, offset);
777 }
778
779 static inline void tcg_out_ld8u(TCGContext *s, int cond,
780 int rd, int rn, int32_t offset)
781 {
782 if (offset > 0xfff || offset < -0xfff) {
783 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
784 tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_R8);
785 } else
786 tcg_out_ld8_12(s, cond, rd, rn, offset);
787 }
788
789 static inline void tcg_out_ld8s(TCGContext *s, int cond,
790 int rd, int rn, int32_t offset)
791 {
792 if (offset > 0xff || offset < -0xff) {
793 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
794 tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_R8);
795 } else
796 tcg_out_ld8s_8(s, cond, rd, rn, offset);
797 }
798
799 static inline void tcg_out_st8(TCGContext *s, int cond,
800 int rd, int rn, int32_t offset)
801 {
802 if (offset > 0xfff || offset < -0xfff) {
803 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
804 tcg_out_st8_r(s, cond, rd, rn, TCG_REG_R8);
805 } else
806 tcg_out_st8_12(s, cond, rd, rn, offset);
807 }
808
809 static inline void tcg_out_goto(TCGContext *s, int cond, uint32_t addr)
810 {
811 int32_t val;
812
813 val = addr - (tcg_target_long) s->code_ptr;
814 if (val - 8 < 0x01fffffd && val - 8 > -0x01fffffd)
815 tcg_out_b(s, cond, val);
816 else {
817 #if 1
818 tcg_abort();
819 #else
820 if (cond == COND_AL) {
821 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
822 tcg_out32(s, addr); /* XXX: This is l->u.value, can we use it? */
823 } else {
824 tcg_out_movi32(s, cond, TCG_REG_R8, val - 8);
825 tcg_out_dat_reg(s, cond, ARITH_ADD,
826 TCG_REG_PC, TCG_REG_PC,
827 TCG_REG_R8, SHIFT_IMM_LSL(0));
828 }
829 #endif
830 }
831 }
832
833 static inline void tcg_out_call(TCGContext *s, int cond, uint32_t addr)
834 {
835 int32_t val;
836
837 val = addr - (tcg_target_long) s->code_ptr;
838 if (val < 0x01fffffd && val > -0x01fffffd)
839 tcg_out_bl(s, cond, val);
840 else {
841 #if 1
842 tcg_abort();
843 #else
844 if (cond == COND_AL) {
845 tcg_out_dat_imm(s, cond, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 4);
846 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
847 tcg_out32(s, addr); /* XXX: This is l->u.value, can we use it? */
848 } else {
849 tcg_out_movi32(s, cond, TCG_REG_R9, addr);
850 tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R14, 0,
851 TCG_REG_PC, SHIFT_IMM_LSL(0));
852 tcg_out_bx(s, cond, TCG_REG_R9);
853 }
854 #endif
855 }
856 }
857
858 static inline void tcg_out_callr(TCGContext *s, int cond, int arg)
859 {
860 if (use_armv5_instructions) {
861 tcg_out_blx(s, cond, arg);
862 } else {
863 tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R14, 0,
864 TCG_REG_PC, SHIFT_IMM_LSL(0));
865 tcg_out_bx(s, cond, arg);
866 }
867 }
868
869 static inline void tcg_out_goto_label(TCGContext *s, int cond, int label_index)
870 {
871 TCGLabel *l = &s->labels[label_index];
872
873 if (l->has_value)
874 tcg_out_goto(s, cond, l->u.value);
875 else if (cond == COND_AL) {
876 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
877 tcg_out_reloc(s, s->code_ptr, R_ARM_ABS32, label_index, 31337);
878 s->code_ptr += 4;
879 } else {
880 /* Probably this should be preferred even for COND_AL... */
881 tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, label_index, 31337);
882 tcg_out_b_noaddr(s, cond);
883 }
884 }
885
886 #ifdef CONFIG_SOFTMMU
887
888 #include "../../softmmu_defs.h"
889
890 static void *qemu_ld_helpers[4] = {
891 __ldb_mmu,
892 __ldw_mmu,
893 __ldl_mmu,
894 __ldq_mmu,
895 };
896
897 static void *qemu_st_helpers[4] = {
898 __stb_mmu,
899 __stw_mmu,
900 __stl_mmu,
901 __stq_mmu,
902 };
903 #endif
904
905 #define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
906
907 static inline void tcg_out_qemu_ld(TCGContext *s, int cond,
908 const TCGArg *args, int opc)
909 {
910 int addr_reg, data_reg, data_reg2;
911 #ifdef CONFIG_SOFTMMU
912 int mem_index, s_bits;
913 # if TARGET_LONG_BITS == 64
914 int addr_reg2;
915 # endif
916 uint32_t *label_ptr;
917 #endif
918
919 data_reg = *args++;
920 if (opc == 3)
921 data_reg2 = *args++;
922 else
923 data_reg2 = 0; /* suppress warning */
924 addr_reg = *args++;
925 #ifdef CONFIG_SOFTMMU
926 # if TARGET_LONG_BITS == 64
927 addr_reg2 = *args++;
928 # endif
929 mem_index = *args;
930 s_bits = opc & 3;
931
932 /* Should generate something like the following:
933 * shr r8, addr_reg, #TARGET_PAGE_BITS
934 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
935 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
936 */
937 # if CPU_TLB_BITS > 8
938 # error
939 # endif
940 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_R8,
941 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
942 tcg_out_dat_imm(s, COND_AL, ARITH_AND,
943 TCG_REG_R0, TCG_REG_R8, CPU_TLB_SIZE - 1);
944 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_AREG0,
945 TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
946 /* In the
947 * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_read))]
948 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
949 * not exceed otherwise, so use an
950 * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
951 * before.
952 */
953 if (mem_index)
954 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0,
955 (mem_index << (TLB_SHIFT & 1)) |
956 ((16 - (TLB_SHIFT >> 1)) << 8));
957 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R0,
958 offsetof(CPUState, tlb_table[0][0].addr_read));
959 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1,
960 TCG_REG_R8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
961 /* Check alignment. */
962 if (s_bits)
963 tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
964 0, addr_reg, (1 << s_bits) - 1);
965 # if TARGET_LONG_BITS == 64
966 /* XXX: possibly we could use a block data load or writeback in
967 * the first access. */
968 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
969 offsetof(CPUState, tlb_table[0][0].addr_read) + 4);
970 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
971 TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0));
972 # endif
973 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
974 offsetof(CPUState, tlb_table[0][0].addend));
975
976 switch (opc) {
977 case 0:
978 tcg_out_ld8_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
979 break;
980 case 0 | 4:
981 tcg_out_ld8s_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
982 break;
983 case 1:
984 tcg_out_ld16u_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
985 break;
986 case 1 | 4:
987 tcg_out_ld16s_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
988 break;
989 case 2:
990 default:
991 tcg_out_ld32_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
992 break;
993 case 3:
994 tcg_out_ld32_rwb(s, COND_EQ, data_reg, TCG_REG_R1, addr_reg);
995 tcg_out_ld32_12(s, COND_EQ, data_reg2, TCG_REG_R1, 4);
996 break;
997 }
998
999 label_ptr = (void *) s->code_ptr;
1000 tcg_out_b(s, COND_EQ, 8);
1001
1002 /* TODO: move this code to where the constants pool will be */
1003 if (addr_reg != TCG_REG_R0) {
1004 tcg_out_dat_reg(s, cond, ARITH_MOV,
1005 TCG_REG_R0, 0, addr_reg, SHIFT_IMM_LSL(0));
1006 }
1007 # if TARGET_LONG_BITS == 32
1008 tcg_out_dat_imm(s, cond, ARITH_MOV, TCG_REG_R1, 0, mem_index);
1009 # else
1010 if (addr_reg2 != TCG_REG_R1) {
1011 tcg_out_dat_reg(s, cond, ARITH_MOV,
1012 TCG_REG_R1, 0, addr_reg2, SHIFT_IMM_LSL(0));
1013 }
1014 tcg_out_dat_imm(s, cond, ARITH_MOV, TCG_REG_R2, 0, mem_index);
1015 # endif
1016 tcg_out_bl(s, cond, (tcg_target_long) qemu_ld_helpers[s_bits] -
1017 (tcg_target_long) s->code_ptr);
1018
1019 switch (opc) {
1020 case 0 | 4:
1021 tcg_out_dat_reg(s, cond, ARITH_MOV,
1022 TCG_REG_R0, 0, TCG_REG_R0, SHIFT_IMM_LSL(24));
1023 tcg_out_dat_reg(s, cond, ARITH_MOV,
1024 data_reg, 0, TCG_REG_R0, SHIFT_IMM_ASR(24));
1025 break;
1026 case 1 | 4:
1027 tcg_out_dat_reg(s, cond, ARITH_MOV,
1028 TCG_REG_R0, 0, TCG_REG_R0, SHIFT_IMM_LSL(16));
1029 tcg_out_dat_reg(s, cond, ARITH_MOV,
1030 data_reg, 0, TCG_REG_R0, SHIFT_IMM_ASR(16));
1031 break;
1032 case 0:
1033 case 1:
1034 case 2:
1035 default:
1036 if (data_reg != TCG_REG_R0) {
1037 tcg_out_dat_reg(s, cond, ARITH_MOV,
1038 data_reg, 0, TCG_REG_R0, SHIFT_IMM_LSL(0));
1039 }
1040 break;
1041 case 3:
1042 if (data_reg != TCG_REG_R0) {
1043 tcg_out_dat_reg(s, cond, ARITH_MOV,
1044 data_reg, 0, TCG_REG_R0, SHIFT_IMM_LSL(0));
1045 }
1046 if (data_reg2 != TCG_REG_R1) {
1047 tcg_out_dat_reg(s, cond, ARITH_MOV,
1048 data_reg2, 0, TCG_REG_R1, SHIFT_IMM_LSL(0));
1049 }
1050 break;
1051 }
1052
1053 *label_ptr += ((void *) s->code_ptr - (void *) label_ptr - 8) >> 2;
1054 #else /* !CONFIG_SOFTMMU */
1055 if (GUEST_BASE) {
1056 uint32_t offset = GUEST_BASE;
1057 int i;
1058 int rot;
1059
1060 while (offset) {
1061 i = ctz32(offset) & ~1;
1062 rot = ((32 - i) << 7) & 0xf00;
1063
1064 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R8, addr_reg,
1065 ((offset >> i) & 0xff) | rot);
1066 addr_reg = TCG_REG_R8;
1067 offset &= ~(0xff << i);
1068 }
1069 }
1070 switch (opc) {
1071 case 0:
1072 tcg_out_ld8_12(s, COND_AL, data_reg, addr_reg, 0);
1073 break;
1074 case 0 | 4:
1075 tcg_out_ld8s_8(s, COND_AL, data_reg, addr_reg, 0);
1076 break;
1077 case 1:
1078 tcg_out_ld16u_8(s, COND_AL, data_reg, addr_reg, 0);
1079 break;
1080 case 1 | 4:
1081 tcg_out_ld16s_8(s, COND_AL, data_reg, addr_reg, 0);
1082 break;
1083 case 2:
1084 default:
1085 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
1086 break;
1087 case 3:
1088 /* TODO: use block load -
1089 * check that data_reg2 > data_reg or the other way */
1090 if (data_reg == addr_reg) {
1091 tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, 4);
1092 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
1093 } else {
1094 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
1095 tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, 4);
1096 }
1097 break;
1098 }
1099 #endif
1100 }
1101
1102 static inline void tcg_out_qemu_st(TCGContext *s, int cond,
1103 const TCGArg *args, int opc)
1104 {
1105 int addr_reg, data_reg, data_reg2;
1106 #ifdef CONFIG_SOFTMMU
1107 int mem_index, s_bits;
1108 # if TARGET_LONG_BITS == 64
1109 int addr_reg2;
1110 # endif
1111 uint32_t *label_ptr;
1112 #endif
1113
1114 data_reg = *args++;
1115 if (opc == 3)
1116 data_reg2 = *args++;
1117 else
1118 data_reg2 = 0; /* suppress warning */
1119 addr_reg = *args++;
1120 #ifdef CONFIG_SOFTMMU
1121 # if TARGET_LONG_BITS == 64
1122 addr_reg2 = *args++;
1123 # endif
1124 mem_index = *args;
1125 s_bits = opc & 3;
1126
1127 /* Should generate something like the following:
1128 * shr r8, addr_reg, #TARGET_PAGE_BITS
1129 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
1130 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
1131 */
1132 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1133 TCG_REG_R8, 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
1134 tcg_out_dat_imm(s, COND_AL, ARITH_AND,
1135 TCG_REG_R0, TCG_REG_R8, CPU_TLB_SIZE - 1);
1136 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0,
1137 TCG_AREG0, TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
1138 /* In the
1139 * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_write))]
1140 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
1141 * not exceed otherwise, so use an
1142 * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
1143 * before.
1144 */
1145 if (mem_index)
1146 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0,
1147 (mem_index << (TLB_SHIFT & 1)) |
1148 ((16 - (TLB_SHIFT >> 1)) << 8));
1149 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R0,
1150 offsetof(CPUState, tlb_table[0][0].addr_write));
1151 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1,
1152 TCG_REG_R8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
1153 /* Check alignment. */
1154 if (s_bits)
1155 tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
1156 0, addr_reg, (1 << s_bits) - 1);
1157 # if TARGET_LONG_BITS == 64
1158 /* XXX: possibly we could use a block data load or writeback in
1159 * the first access. */
1160 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
1161 offsetof(CPUState, tlb_table[0][0].addr_write) + 4);
1162 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1163 TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0));
1164 # endif
1165 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
1166 offsetof(CPUState, tlb_table[0][0].addend));
1167
1168 switch (opc) {
1169 case 0:
1170 tcg_out_st8_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1171 break;
1172 case 1:
1173 tcg_out_st16_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1174 break;
1175 case 2:
1176 default:
1177 tcg_out_st32_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1178 break;
1179 case 3:
1180 tcg_out_st32_rwb(s, COND_EQ, data_reg, TCG_REG_R1, addr_reg);
1181 tcg_out_st32_12(s, COND_EQ, data_reg2, TCG_REG_R1, 4);
1182 break;
1183 }
1184
1185 label_ptr = (void *) s->code_ptr;
1186 tcg_out_b(s, COND_EQ, 8);
1187
1188 /* TODO: move this code to where the constants pool will be */
1189 if (addr_reg != TCG_REG_R0) {
1190 tcg_out_dat_reg(s, cond, ARITH_MOV,
1191 TCG_REG_R0, 0, addr_reg, SHIFT_IMM_LSL(0));
1192 }
1193 # if TARGET_LONG_BITS == 32
1194 switch (opc) {
1195 case 0:
1196 tcg_out_dat_imm(s, cond, ARITH_AND, TCG_REG_R1, data_reg, 0xff);
1197 tcg_out_dat_imm(s, cond, ARITH_MOV, TCG_REG_R2, 0, mem_index);
1198 break;
1199 case 1:
1200 tcg_out_dat_reg(s, cond, ARITH_MOV,
1201 TCG_REG_R1, 0, data_reg, SHIFT_IMM_LSL(16));
1202 tcg_out_dat_reg(s, cond, ARITH_MOV,
1203 TCG_REG_R1, 0, TCG_REG_R1, SHIFT_IMM_LSR(16));
1204 tcg_out_dat_imm(s, cond, ARITH_MOV, TCG_REG_R2, 0, mem_index);
1205 break;
1206 case 2:
1207 if (data_reg != TCG_REG_R1) {
1208 tcg_out_dat_reg(s, cond, ARITH_MOV,
1209 TCG_REG_R1, 0, data_reg, SHIFT_IMM_LSL(0));
1210 }
1211 tcg_out_dat_imm(s, cond, ARITH_MOV, TCG_REG_R2, 0, mem_index);
1212 break;
1213 case 3:
1214 if (data_reg != TCG_REG_R1) {
1215 tcg_out_dat_reg(s, cond, ARITH_MOV,
1216 TCG_REG_R1, 0, data_reg, SHIFT_IMM_LSL(0));
1217 }
1218 if (data_reg2 != TCG_REG_R2) {
1219 tcg_out_dat_reg(s, cond, ARITH_MOV,
1220 TCG_REG_R2, 0, data_reg2, SHIFT_IMM_LSL(0));
1221 }
1222 tcg_out_dat_imm(s, cond, ARITH_MOV, TCG_REG_R3, 0, mem_index);
1223 break;
1224 }
1225 # else
1226 if (addr_reg2 != TCG_REG_R1) {
1227 tcg_out_dat_reg(s, cond, ARITH_MOV,
1228 TCG_REG_R1, 0, addr_reg2, SHIFT_IMM_LSL(0));
1229 }
1230 switch (opc) {
1231 case 0:
1232 tcg_out_dat_imm(s, cond, ARITH_AND, TCG_REG_R2, data_reg, 0xff);
1233 tcg_out_dat_imm(s, cond, ARITH_MOV, TCG_REG_R3, 0, mem_index);
1234 break;
1235 case 1:
1236 tcg_out_dat_reg(s, cond, ARITH_MOV,
1237 TCG_REG_R2, 0, data_reg, SHIFT_IMM_LSL(16));
1238 tcg_out_dat_reg(s, cond, ARITH_MOV,
1239 TCG_REG_R2, 0, TCG_REG_R2, SHIFT_IMM_LSR(16));
1240 tcg_out_dat_imm(s, cond, ARITH_MOV, TCG_REG_R3, 0, mem_index);
1241 break;
1242 case 2:
1243 if (data_reg != TCG_REG_R2) {
1244 tcg_out_dat_reg(s, cond, ARITH_MOV,
1245 TCG_REG_R2, 0, data_reg, SHIFT_IMM_LSL(0));
1246 }
1247 tcg_out_dat_imm(s, cond, ARITH_MOV, TCG_REG_R3, 0, mem_index);
1248 break;
1249 case 3:
1250 tcg_out_dat_imm(s, cond, ARITH_MOV, TCG_REG_R8, 0, mem_index);
1251 tcg_out32(s, (cond << 28) | 0x052d8010); /* str r8, [sp, #-0x10]! */
1252 if (data_reg != TCG_REG_R2) {
1253 tcg_out_dat_reg(s, cond, ARITH_MOV,
1254 TCG_REG_R2, 0, data_reg, SHIFT_IMM_LSL(0));
1255 }
1256 if (data_reg2 != TCG_REG_R3) {
1257 tcg_out_dat_reg(s, cond, ARITH_MOV,
1258 TCG_REG_R3, 0, data_reg2, SHIFT_IMM_LSL(0));
1259 }
1260 break;
1261 }
1262 # endif
1263
1264 tcg_out_bl(s, cond, (tcg_target_long) qemu_st_helpers[s_bits] -
1265 (tcg_target_long) s->code_ptr);
1266 # if TARGET_LONG_BITS == 64
1267 if (opc == 3)
1268 tcg_out_dat_imm(s, cond, ARITH_ADD, TCG_REG_R13, TCG_REG_R13, 0x10);
1269 # endif
1270
1271 *label_ptr += ((void *) s->code_ptr - (void *) label_ptr - 8) >> 2;
1272 #else /* !CONFIG_SOFTMMU */
1273 if (GUEST_BASE) {
1274 uint32_t offset = GUEST_BASE;
1275 int i;
1276 int rot;
1277
1278 while (offset) {
1279 i = ctz32(offset) & ~1;
1280 rot = ((32 - i) << 7) & 0xf00;
1281
1282 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R8, addr_reg,
1283 ((offset >> i) & 0xff) | rot);
1284 addr_reg = TCG_REG_R8;
1285 offset &= ~(0xff << i);
1286 }
1287 }
1288 switch (opc) {
1289 case 0:
1290 tcg_out_st8_12(s, COND_AL, data_reg, addr_reg, 0);
1291 break;
1292 case 1:
1293 tcg_out_st16_8(s, COND_AL, data_reg, addr_reg, 0);
1294 break;
1295 case 2:
1296 default:
1297 tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1298 break;
1299 case 3:
1300 /* TODO: use block store -
1301 * check that data_reg2 > data_reg or the other way */
1302 tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1303 tcg_out_st32_12(s, COND_AL, data_reg2, addr_reg, 4);
1304 break;
1305 }
1306 #endif
1307 }
1308
1309 static uint8_t *tb_ret_addr;
1310
1311 static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
1312 const TCGArg *args, const int *const_args)
1313 {
1314 int c;
1315
1316 switch (opc) {
1317 case INDEX_op_exit_tb:
1318 {
1319 uint8_t *ld_ptr = s->code_ptr;
1320 if (args[0] >> 8)
1321 tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, TCG_REG_PC, 0);
1322 else
1323 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R0, 0, args[0]);
1324 tcg_out_goto(s, COND_AL, (tcg_target_ulong) tb_ret_addr);
1325 if (args[0] >> 8) {
1326 *ld_ptr = (uint8_t) (s->code_ptr - ld_ptr) - 8;
1327 tcg_out32(s, args[0]);
1328 }
1329 }
1330 break;
1331 case INDEX_op_goto_tb:
1332 if (s->tb_jmp_offset) {
1333 /* Direct jump method */
1334 #if defined(USE_DIRECT_JUMP)
1335 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1336 tcg_out_b(s, COND_AL, 8);
1337 #else
1338 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
1339 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1340 tcg_out32(s, 0);
1341 #endif
1342 } else {
1343 /* Indirect jump method */
1344 #if 1
1345 c = (int) (s->tb_next + args[0]) - ((int) s->code_ptr + 8);
1346 if (c > 0xfff || c < -0xfff) {
1347 tcg_out_movi32(s, COND_AL, TCG_REG_R0,
1348 (tcg_target_long) (s->tb_next + args[0]));
1349 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, 0);
1350 } else
1351 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, c);
1352 #else
1353 tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, TCG_REG_PC, 0);
1354 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, 0);
1355 tcg_out32(s, (tcg_target_long) (s->tb_next + args[0]));
1356 #endif
1357 }
1358 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1359 break;
1360 case INDEX_op_call:
1361 if (const_args[0])
1362 tcg_out_call(s, COND_AL, args[0]);
1363 else
1364 tcg_out_callr(s, COND_AL, args[0]);
1365 break;
1366 case INDEX_op_jmp:
1367 if (const_args[0])
1368 tcg_out_goto(s, COND_AL, args[0]);
1369 else
1370 tcg_out_bx(s, COND_AL, args[0]);
1371 break;
1372 case INDEX_op_br:
1373 tcg_out_goto_label(s, COND_AL, args[0]);
1374 break;
1375
1376 case INDEX_op_ld8u_i32:
1377 tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]);
1378 break;
1379 case INDEX_op_ld8s_i32:
1380 tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]);
1381 break;
1382 case INDEX_op_ld16u_i32:
1383 tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]);
1384 break;
1385 case INDEX_op_ld16s_i32:
1386 tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]);
1387 break;
1388 case INDEX_op_ld_i32:
1389 tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]);
1390 break;
1391 case INDEX_op_st8_i32:
1392 tcg_out_st8(s, COND_AL, args[0], args[1], args[2]);
1393 break;
1394 case INDEX_op_st16_i32:
1395 tcg_out_st16(s, COND_AL, args[0], args[1], args[2]);
1396 break;
1397 case INDEX_op_st_i32:
1398 tcg_out_st32(s, COND_AL, args[0], args[1], args[2]);
1399 break;
1400
1401 case INDEX_op_mov_i32:
1402 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1403 args[0], 0, args[1], SHIFT_IMM_LSL(0));
1404 break;
1405 case INDEX_op_movi_i32:
1406 tcg_out_movi32(s, COND_AL, args[0], args[1]);
1407 break;
1408 case INDEX_op_add_i32:
1409 c = ARITH_ADD;
1410 goto gen_arith;
1411 case INDEX_op_sub_i32:
1412 c = ARITH_SUB;
1413 goto gen_arith;
1414 case INDEX_op_and_i32:
1415 c = ARITH_AND;
1416 goto gen_arith;
1417 case INDEX_op_andc_i32:
1418 c = ARITH_BIC;
1419 goto gen_arith;
1420 case INDEX_op_or_i32:
1421 c = ARITH_ORR;
1422 goto gen_arith;
1423 case INDEX_op_xor_i32:
1424 c = ARITH_EOR;
1425 /* Fall through. */
1426 gen_arith:
1427 if (const_args[2]) {
1428 int rot;
1429 rot = encode_imm(args[2]);
1430 tcg_out_dat_imm(s, COND_AL, c,
1431 args[0], args[1], rotl(args[2], rot) | (rot << 7));
1432 } else
1433 tcg_out_dat_reg(s, COND_AL, c,
1434 args[0], args[1], args[2], SHIFT_IMM_LSL(0));
1435 break;
1436 case INDEX_op_add2_i32:
1437 tcg_out_dat_reg2(s, COND_AL, ARITH_ADD, ARITH_ADC,
1438 args[0], args[1], args[2], args[3],
1439 args[4], args[5], SHIFT_IMM_LSL(0));
1440 break;
1441 case INDEX_op_sub2_i32:
1442 tcg_out_dat_reg2(s, COND_AL, ARITH_SUB, ARITH_SBC,
1443 args[0], args[1], args[2], args[3],
1444 args[4], args[5], SHIFT_IMM_LSL(0));
1445 break;
1446 case INDEX_op_neg_i32:
1447 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0);
1448 break;
1449 case INDEX_op_not_i32:
1450 tcg_out_dat_reg(s, COND_AL,
1451 ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0));
1452 break;
1453 case INDEX_op_mul_i32:
1454 tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]);
1455 break;
1456 case INDEX_op_mulu2_i32:
1457 tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]);
1458 break;
1459 /* XXX: Perhaps args[2] & 0x1f is wrong */
1460 case INDEX_op_shl_i32:
1461 c = const_args[2] ?
1462 SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]);
1463 goto gen_shift32;
1464 case INDEX_op_shr_i32:
1465 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) :
1466 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]);
1467 goto gen_shift32;
1468 case INDEX_op_sar_i32:
1469 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) :
1470 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]);
1471 goto gen_shift32;
1472 case INDEX_op_rotr_i32:
1473 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ROR(args[2] & 0x1f) :
1474 SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args[2]);
1475 /* Fall through. */
1476 gen_shift32:
1477 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c);
1478 break;
1479
1480 case INDEX_op_rotl_i32:
1481 if (const_args[2]) {
1482 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1],
1483 ((0x20 - args[2]) & 0x1f) ?
1484 SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) :
1485 SHIFT_IMM_LSL(0));
1486 } else {
1487 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_R8, args[1], 0x20);
1488 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1],
1489 SHIFT_REG_ROR(TCG_REG_R8));
1490 }
1491 break;
1492
1493 case INDEX_op_brcond_i32:
1494 if (const_args[1]) {
1495 int rot;
1496 rot = encode_imm(args[1]);
1497 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0,
1498 args[0], rotl(args[1], rot) | (rot << 7));
1499 } else {
1500 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1501 args[0], args[1], SHIFT_IMM_LSL(0));
1502 }
1503 tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], args[3]);
1504 break;
1505 case INDEX_op_brcond2_i32:
1506 /* The resulting conditions are:
1507 * TCG_COND_EQ --> a0 == a2 && a1 == a3,
1508 * TCG_COND_NE --> (a0 != a2 && a1 == a3) || a1 != a3,
1509 * TCG_COND_LT(U) --> (a0 < a2 && a1 == a3) || a1 < a3,
1510 * TCG_COND_GE(U) --> (a0 >= a2 && a1 == a3) || (a1 >= a3 && a1 != a3),
1511 * TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3),
1512 * TCG_COND_GT(U) --> (a0 > a2 && a1 == a3) || a1 > a3,
1513 */
1514 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1515 args[1], args[3], SHIFT_IMM_LSL(0));
1516 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1517 args[0], args[2], SHIFT_IMM_LSL(0));
1518 tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[4]], args[5]);
1519 break;
1520 case INDEX_op_setcond_i32:
1521 if (const_args[2]) {
1522 int rot;
1523 rot = encode_imm(args[2]);
1524 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0,
1525 args[1], rotl(args[2], rot) | (rot << 7));
1526 } else {
1527 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1528 args[1], args[2], SHIFT_IMM_LSL(0));
1529 }
1530 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]],
1531 ARITH_MOV, args[0], 0, 1);
1532 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])],
1533 ARITH_MOV, args[0], 0, 0);
1534 break;
1535 case INDEX_op_setcond2_i32:
1536 /* See brcond2_i32 comment */
1537 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1538 args[2], args[4], SHIFT_IMM_LSL(0));
1539 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1540 args[1], args[3], SHIFT_IMM_LSL(0));
1541 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[5]],
1542 ARITH_MOV, args[0], 0, 1);
1543 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[5])],
1544 ARITH_MOV, args[0], 0, 0);
1545 break;
1546
1547 case INDEX_op_qemu_ld8u:
1548 tcg_out_qemu_ld(s, COND_AL, args, 0);
1549 break;
1550 case INDEX_op_qemu_ld8s:
1551 tcg_out_qemu_ld(s, COND_AL, args, 0 | 4);
1552 break;
1553 case INDEX_op_qemu_ld16u:
1554 tcg_out_qemu_ld(s, COND_AL, args, 1);
1555 break;
1556 case INDEX_op_qemu_ld16s:
1557 tcg_out_qemu_ld(s, COND_AL, args, 1 | 4);
1558 break;
1559 case INDEX_op_qemu_ld32:
1560 tcg_out_qemu_ld(s, COND_AL, args, 2);
1561 break;
1562 case INDEX_op_qemu_ld64:
1563 tcg_out_qemu_ld(s, COND_AL, args, 3);
1564 break;
1565
1566 case INDEX_op_qemu_st8:
1567 tcg_out_qemu_st(s, COND_AL, args, 0);
1568 break;
1569 case INDEX_op_qemu_st16:
1570 tcg_out_qemu_st(s, COND_AL, args, 1);
1571 break;
1572 case INDEX_op_qemu_st32:
1573 tcg_out_qemu_st(s, COND_AL, args, 2);
1574 break;
1575 case INDEX_op_qemu_st64:
1576 tcg_out_qemu_st(s, COND_AL, args, 3);
1577 break;
1578
1579 case INDEX_op_bswap16_i32:
1580 tcg_out_bswap16(s, COND_AL, args[0], args[1]);
1581 break;
1582 case INDEX_op_bswap32_i32:
1583 tcg_out_bswap32(s, COND_AL, args[0], args[1]);
1584 break;
1585
1586 case INDEX_op_ext8s_i32:
1587 tcg_out_ext8s(s, COND_AL, args[0], args[1]);
1588 break;
1589 case INDEX_op_ext16s_i32:
1590 tcg_out_ext16s(s, COND_AL, args[0], args[1]);
1591 break;
1592 case INDEX_op_ext16u_i32:
1593 tcg_out_ext16u(s, COND_AL, args[0], args[1]);
1594 break;
1595
1596 default:
1597 tcg_abort();
1598 }
1599 }
1600
1601 static const TCGTargetOpDef arm_op_defs[] = {
1602 { INDEX_op_exit_tb, { } },
1603 { INDEX_op_goto_tb, { } },
1604 { INDEX_op_call, { "ri" } },
1605 { INDEX_op_jmp, { "ri" } },
1606 { INDEX_op_br, { } },
1607
1608 { INDEX_op_mov_i32, { "r", "r" } },
1609 { INDEX_op_movi_i32, { "r" } },
1610
1611 { INDEX_op_ld8u_i32, { "r", "r" } },
1612 { INDEX_op_ld8s_i32, { "r", "r" } },
1613 { INDEX_op_ld16u_i32, { "r", "r" } },
1614 { INDEX_op_ld16s_i32, { "r", "r" } },
1615 { INDEX_op_ld_i32, { "r", "r" } },
1616 { INDEX_op_st8_i32, { "r", "r" } },
1617 { INDEX_op_st16_i32, { "r", "r" } },
1618 { INDEX_op_st_i32, { "r", "r" } },
1619
1620 /* TODO: "r", "r", "ri" */
1621 { INDEX_op_add_i32, { "r", "r", "rI" } },
1622 { INDEX_op_sub_i32, { "r", "r", "rI" } },
1623 { INDEX_op_mul_i32, { "r", "r", "r" } },
1624 { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
1625 { INDEX_op_and_i32, { "r", "r", "rI" } },
1626 { INDEX_op_andc_i32, { "r", "r", "rI" } },
1627 { INDEX_op_or_i32, { "r", "r", "rI" } },
1628 { INDEX_op_xor_i32, { "r", "r", "rI" } },
1629 { INDEX_op_neg_i32, { "r", "r" } },
1630 { INDEX_op_not_i32, { "r", "r" } },
1631
1632 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1633 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1634 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1635 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
1636 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
1637
1638 { INDEX_op_brcond_i32, { "r", "rI" } },
1639 { INDEX_op_setcond_i32, { "r", "r", "rI" } },
1640
1641 /* TODO: "r", "r", "r", "r", "ri", "ri" */
1642 { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1643 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1644 { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
1645 { INDEX_op_setcond2_i32, { "r", "r", "r", "r", "r" } },
1646
1647 #if TARGET_LONG_BITS == 32
1648 { INDEX_op_qemu_ld8u, { "r", "x" } },
1649 { INDEX_op_qemu_ld8s, { "r", "x" } },
1650 { INDEX_op_qemu_ld16u, { "r", "x" } },
1651 { INDEX_op_qemu_ld16s, { "r", "x" } },
1652 { INDEX_op_qemu_ld32, { "r", "x" } },
1653 { INDEX_op_qemu_ld64, { "d", "r", "x" } },
1654
1655 { INDEX_op_qemu_st8, { "x", "x" } },
1656 { INDEX_op_qemu_st16, { "x", "x" } },
1657 { INDEX_op_qemu_st32, { "x", "x" } },
1658 { INDEX_op_qemu_st64, { "x", "D", "x" } },
1659 #else
1660 { INDEX_op_qemu_ld8u, { "r", "x", "X" } },
1661 { INDEX_op_qemu_ld8s, { "r", "x", "X" } },
1662 { INDEX_op_qemu_ld16u, { "r", "x", "X" } },
1663 { INDEX_op_qemu_ld16s, { "r", "x", "X" } },
1664 { INDEX_op_qemu_ld32, { "r", "x", "X" } },
1665 { INDEX_op_qemu_ld64, { "d", "r", "x", "X" } },
1666
1667 { INDEX_op_qemu_st8, { "x", "x", "X" } },
1668 { INDEX_op_qemu_st16, { "x", "x", "X" } },
1669 { INDEX_op_qemu_st32, { "x", "x", "X" } },
1670 { INDEX_op_qemu_st64, { "x", "D", "x", "X" } },
1671 #endif
1672
1673 { INDEX_op_bswap16_i32, { "r", "r" } },
1674 { INDEX_op_bswap32_i32, { "r", "r" } },
1675
1676 { INDEX_op_ext8s_i32, { "r", "r" } },
1677 { INDEX_op_ext16s_i32, { "r", "r" } },
1678 { INDEX_op_ext16u_i32, { "r", "r" } },
1679
1680 { -1 },
1681 };
1682
1683 void tcg_target_init(TCGContext *s)
1684 {
1685 #if !defined(CONFIG_USER_ONLY)
1686 /* fail safe */
1687 if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1688 tcg_abort();
1689 #endif
1690
1691 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
1692 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1693 (1 << TCG_REG_R0) |
1694 (1 << TCG_REG_R1) |
1695 (1 << TCG_REG_R2) |
1696 (1 << TCG_REG_R3) |
1697 (1 << TCG_REG_R12) |
1698 (1 << TCG_REG_R14));
1699
1700 tcg_regset_clear(s->reserved_regs);
1701 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
1702 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R8);
1703 tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC);
1704
1705 tcg_add_target_add_op_defs(arm_op_defs);
1706 }
1707
1708 static inline void tcg_out_ld(TCGContext *s, TCGType type, int arg,
1709 int arg1, tcg_target_long arg2)
1710 {
1711 tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
1712 }
1713
1714 static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
1715 int arg1, tcg_target_long arg2)
1716 {
1717 tcg_out_st32(s, COND_AL, arg, arg1, arg2);
1718 }
1719
1720 static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
1721 {
1722 if (val > 0)
1723 if (val < 0x100)
1724 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, reg, reg, val);
1725 else
1726 tcg_abort();
1727 else if (val < 0) {
1728 if (val > -0x100)
1729 tcg_out_dat_imm(s, COND_AL, ARITH_SUB, reg, reg, -val);
1730 else
1731 tcg_abort();
1732 }
1733 }
1734
1735 static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
1736 {
1737 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, ret, 0, arg, SHIFT_IMM_LSL(0));
1738 }
1739
1740 static inline void tcg_out_movi(TCGContext *s, TCGType type,
1741 int ret, tcg_target_long arg)
1742 {
1743 tcg_out_movi32(s, COND_AL, ret, arg);
1744 }
1745
1746 void tcg_target_qemu_prologue(TCGContext *s)
1747 {
1748 /* There is no need to save r7, it is used to store the address
1749 of the env structure and is not modified by GCC. */
1750
1751 /* stmdb sp!, { r4 - r6, r8 - r11, lr } */
1752 tcg_out32(s, (COND_AL << 28) | 0x092d4f70);
1753
1754 tcg_out_bx(s, COND_AL, TCG_REG_R0);
1755 tb_ret_addr = s->code_ptr;
1756
1757 /* ldmia sp!, { r4 - r6, r8 - r11, pc } */
1758 tcg_out32(s, (COND_AL << 28) | 0x08bd8f70);
1759 }
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