2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Andrzej Zaborowski
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #if defined(__ARM_ARCH_7__) || \
26 defined(__ARM_ARCH_7A__) || \
27 defined(__ARM_ARCH_7EM__) || \
28 defined(__ARM_ARCH_7M__) || \
29 defined(__ARM_ARCH_7R__)
30 #define USE_ARMV7_INSTRUCTIONS
33 #if defined(USE_ARMV7_INSTRUCTIONS) || \
34 defined(__ARM_ARCH_6J__) || \
35 defined(__ARM_ARCH_6K__) || \
36 defined(__ARM_ARCH_6T2__) || \
37 defined(__ARM_ARCH_6Z__) || \
38 defined(__ARM_ARCH_6ZK__)
39 #define USE_ARMV6_INSTRUCTIONS
42 #if defined(USE_ARMV6_INSTRUCTIONS) || \
43 defined(__ARM_ARCH_5T__) || \
44 defined(__ARM_ARCH_5TE__) || \
45 defined(__ARM_ARCH_5TEJ__)
46 #define USE_ARMV5_INSTRUCTIONS
49 #ifdef USE_ARMV5_INSTRUCTIONS
50 static const int use_armv5_instructions
= 1;
52 static const int use_armv5_instructions
= 0;
54 #undef USE_ARMV5_INSTRUCTIONS
56 #ifdef USE_ARMV6_INSTRUCTIONS
57 static const int use_armv6_instructions
= 1;
59 static const int use_armv6_instructions
= 0;
61 #undef USE_ARMV6_INSTRUCTIONS
63 #ifdef USE_ARMV7_INSTRUCTIONS
64 static const int use_armv7_instructions
= 1;
66 static const int use_armv7_instructions
= 0;
68 #undef USE_ARMV7_INSTRUCTIONS
71 static const char * const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
91 static const int tcg_target_reg_alloc_order
[] = {
109 static const int tcg_target_call_iarg_regs
[4] = {
110 TCG_REG_R0
, TCG_REG_R1
, TCG_REG_R2
, TCG_REG_R3
112 static const int tcg_target_call_oarg_regs
[2] = {
113 TCG_REG_R0
, TCG_REG_R1
116 static inline void reloc_abs32(void *code_ptr
, tcg_target_long target
)
118 *(uint32_t *) code_ptr
= target
;
121 static inline void reloc_pc24(void *code_ptr
, tcg_target_long target
)
123 uint32_t offset
= ((target
- ((tcg_target_long
) code_ptr
+ 8)) >> 2);
125 *(uint32_t *) code_ptr
= ((*(uint32_t *) code_ptr
) & ~0xffffff)
126 | (offset
& 0xffffff);
129 static void patch_reloc(uint8_t *code_ptr
, int type
,
130 tcg_target_long value
, tcg_target_long addend
)
134 reloc_abs32(code_ptr
, value
);
143 reloc_pc24(code_ptr
, value
);
148 /* maximum number of register used for input function arguments */
149 static inline int tcg_target_get_call_iarg_regs_count(int flags
)
154 /* parse target specific constraints */
155 static int target_parse_constraint(TCGArgConstraint
*ct
, const char **pct_str
)
162 ct
->ct
|= TCG_CT_CONST_ARM
;
166 ct
->ct
|= TCG_CT_REG
;
167 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
170 /* qemu_ld address */
172 ct
->ct
|= TCG_CT_REG
;
173 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
174 #ifdef CONFIG_SOFTMMU
175 /* r0 and r1 will be overwritten when reading the tlb entry,
176 so don't use these. */
177 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R0
);
178 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
179 #if TARGET_LONG_BITS == 64
180 /* If we're passing env to the helper as r0 and need a regpair
181 * for the address then r2 will be overwritten as we're setting
182 * up the args to the helper.
184 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R2
);
189 ct
->ct
|= TCG_CT_REG
;
190 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
191 #ifdef CONFIG_SOFTMMU
192 /* r1 is still needed to load data_reg or data_reg2,
194 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
198 /* qemu_st address & data_reg */
200 ct
->ct
|= TCG_CT_REG
;
201 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
202 /* r0 and r1 will be overwritten when reading the tlb entry
203 (softmmu only) and doing the byte swapping, so don't
205 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R0
);
206 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
207 #if defined(CONFIG_SOFTMMU) && (TARGET_LONG_BITS == 64)
208 /* Avoid clashes with registers being used for helper args */
209 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R2
);
210 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R3
);
213 /* qemu_st64 data_reg2 */
215 ct
->ct
|= TCG_CT_REG
;
216 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
217 /* r0 and r1 will be overwritten when reading the tlb entry
218 (softmmu only) and doing the byte swapping, so don't
220 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R0
);
221 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
222 #ifdef CONFIG_SOFTMMU
223 /* r2 is still needed to load data_reg, so don't use it. */
224 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R2
);
225 #if TARGET_LONG_BITS == 64
226 /* Avoid clashes with registers being used for helper args */
227 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R3
);
241 static inline uint32_t rotl(uint32_t val
, int n
)
243 return (val
<< n
) | (val
>> (32 - n
));
246 /* ARM immediates for ALU instructions are made of an unsigned 8-bit
247 right-rotated by an even amount between 0 and 30. */
248 static inline int encode_imm(uint32_t imm
)
252 /* simple case, only lower bits */
253 if ((imm
& ~0xff) == 0)
255 /* then try a simple even shift */
256 shift
= ctz32(imm
) & ~1;
257 if (((imm
>> shift
) & ~0xff) == 0)
259 /* now try harder with rotations */
260 if ((rotl(imm
, 2) & ~0xff) == 0)
262 if ((rotl(imm
, 4) & ~0xff) == 0)
264 if ((rotl(imm
, 6) & ~0xff) == 0)
266 /* imm can't be encoded */
270 static inline int check_fit_imm(uint32_t imm
)
272 return encode_imm(imm
) >= 0;
275 /* Test if a constant matches the constraint.
276 * TODO: define constraints for:
278 * ldr/str offset: between -0xfff and 0xfff
279 * ldrh/strh offset: between -0xff and 0xff
280 * mov operand2: values represented with x << (2 * y), x < 0x100
281 * add, sub, eor...: ditto
283 static inline int tcg_target_const_match(tcg_target_long val
,
284 const TCGArgConstraint
*arg_ct
)
288 if (ct
& TCG_CT_CONST
)
290 else if ((ct
& TCG_CT_CONST_ARM
) && check_fit_imm(val
))
296 enum arm_data_opc_e
{
314 #define TO_CPSR(opc) \
315 ((opc == ARITH_CMP || opc == ARITH_CMN || opc == ARITH_TST) << 20)
317 #define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
318 #define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20)
319 #define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40)
320 #define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60)
321 #define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10)
322 #define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30)
323 #define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50)
324 #define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70)
326 enum arm_cond_code_e
{
329 COND_CS
= 0x2, /* Unsigned greater or equal */
330 COND_CC
= 0x3, /* Unsigned less than */
331 COND_MI
= 0x4, /* Negative */
332 COND_PL
= 0x5, /* Zero or greater */
333 COND_VS
= 0x6, /* Overflow */
334 COND_VC
= 0x7, /* No overflow */
335 COND_HI
= 0x8, /* Unsigned greater than */
336 COND_LS
= 0x9, /* Unsigned less or equal */
344 static const uint8_t tcg_cond_to_arm_cond
[10] = {
345 [TCG_COND_EQ
] = COND_EQ
,
346 [TCG_COND_NE
] = COND_NE
,
347 [TCG_COND_LT
] = COND_LT
,
348 [TCG_COND_GE
] = COND_GE
,
349 [TCG_COND_LE
] = COND_LE
,
350 [TCG_COND_GT
] = COND_GT
,
352 [TCG_COND_LTU
] = COND_CC
,
353 [TCG_COND_GEU
] = COND_CS
,
354 [TCG_COND_LEU
] = COND_LS
,
355 [TCG_COND_GTU
] = COND_HI
,
358 static inline void tcg_out_bx(TCGContext
*s
, int cond
, int rn
)
360 tcg_out32(s
, (cond
<< 28) | 0x012fff10 | rn
);
363 static inline void tcg_out_b(TCGContext
*s
, int cond
, int32_t offset
)
365 tcg_out32(s
, (cond
<< 28) | 0x0a000000 |
366 (((offset
- 8) >> 2) & 0x00ffffff));
369 static inline void tcg_out_b_noaddr(TCGContext
*s
, int cond
)
371 /* We pay attention here to not modify the branch target by skipping
372 the corresponding bytes. This ensure that caches and memory are
373 kept coherent during retranslation. */
374 #ifdef HOST_WORDS_BIGENDIAN
375 tcg_out8(s
, (cond
<< 4) | 0x0a);
379 tcg_out8(s
, (cond
<< 4) | 0x0a);
383 static inline void tcg_out_bl(TCGContext
*s
, int cond
, int32_t offset
)
385 tcg_out32(s
, (cond
<< 28) | 0x0b000000 |
386 (((offset
- 8) >> 2) & 0x00ffffff));
389 static inline void tcg_out_blx(TCGContext
*s
, int cond
, int rn
)
391 tcg_out32(s
, (cond
<< 28) | 0x012fff30 | rn
);
394 static inline void tcg_out_blx_imm(TCGContext
*s
, int32_t offset
)
396 tcg_out32(s
, 0xfa000000 | ((offset
& 2) << 23) |
397 (((offset
- 8) >> 2) & 0x00ffffff));
400 static inline void tcg_out_dat_reg(TCGContext
*s
,
401 int cond
, int opc
, int rd
, int rn
, int rm
, int shift
)
403 tcg_out32(s
, (cond
<< 28) | (0 << 25) | (opc
<< 21) | TO_CPSR(opc
) |
404 (rn
<< 16) | (rd
<< 12) | shift
| rm
);
407 static inline void tcg_out_mov_reg(TCGContext
*s
, int cond
, int rd
, int rm
)
409 /* Simple reg-reg move, optimising out the 'do nothing' case */
411 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, rd
, 0, rm
, SHIFT_IMM_LSL(0));
415 static inline void tcg_out_dat_reg2(TCGContext
*s
,
416 int cond
, int opc0
, int opc1
, int rd0
, int rd1
,
417 int rn0
, int rn1
, int rm0
, int rm1
, int shift
)
419 if (rd0
== rn1
|| rd0
== rm1
) {
420 tcg_out32(s
, (cond
<< 28) | (0 << 25) | (opc0
<< 21) | (1 << 20) |
421 (rn0
<< 16) | (8 << 12) | shift
| rm0
);
422 tcg_out32(s
, (cond
<< 28) | (0 << 25) | (opc1
<< 21) |
423 (rn1
<< 16) | (rd1
<< 12) | shift
| rm1
);
424 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
425 rd0
, 0, TCG_REG_R8
, SHIFT_IMM_LSL(0));
427 tcg_out32(s
, (cond
<< 28) | (0 << 25) | (opc0
<< 21) | (1 << 20) |
428 (rn0
<< 16) | (rd0
<< 12) | shift
| rm0
);
429 tcg_out32(s
, (cond
<< 28) | (0 << 25) | (opc1
<< 21) |
430 (rn1
<< 16) | (rd1
<< 12) | shift
| rm1
);
434 static inline void tcg_out_dat_imm(TCGContext
*s
,
435 int cond
, int opc
, int rd
, int rn
, int im
)
437 tcg_out32(s
, (cond
<< 28) | (1 << 25) | (opc
<< 21) | TO_CPSR(opc
) |
438 (rn
<< 16) | (rd
<< 12) | im
);
441 static inline void tcg_out_movi32(TCGContext
*s
,
442 int cond
, int rd
, uint32_t arg
)
444 /* TODO: This is very suboptimal, we can easily have a constant
445 * pool somewhere after all the instructions. */
446 if ((int)arg
< 0 && (int)arg
>= -0x100) {
447 tcg_out_dat_imm(s
, cond
, ARITH_MVN
, rd
, 0, (~arg
) & 0xff);
448 } else if (use_armv7_instructions
) {
451 tcg_out32(s
, (cond
<< 28) | 0x03000000 | (rd
<< 12)
452 | ((arg
<< 4) & 0x000f0000) | (arg
& 0xfff));
453 if (arg
& 0xffff0000) {
455 tcg_out32(s
, (cond
<< 28) | 0x03400000 | (rd
<< 12)
456 | ((arg
>> 12) & 0x000f0000) | ((arg
>> 16) & 0xfff));
466 rot
= ((32 - i
) << 7) & 0xf00;
467 tcg_out_dat_imm(s
, cond
, opc
, rd
, rn
, ((arg
>> i
) & 0xff) | rot
);
476 static inline void tcg_out_mul32(TCGContext
*s
,
477 int cond
, int rd
, int rs
, int rm
)
480 tcg_out32(s
, (cond
<< 28) | (rd
<< 16) | (0 << 12) |
481 (rs
<< 8) | 0x90 | rm
);
483 tcg_out32(s
, (cond
<< 28) | (rd
<< 16) | (0 << 12) |
484 (rm
<< 8) | 0x90 | rs
);
486 tcg_out32(s
, (cond
<< 28) | ( 8 << 16) | (0 << 12) |
487 (rs
<< 8) | 0x90 | rm
);
488 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
489 rd
, 0, TCG_REG_R8
, SHIFT_IMM_LSL(0));
493 static inline void tcg_out_umull32(TCGContext
*s
,
494 int cond
, int rd0
, int rd1
, int rs
, int rm
)
496 if (rd0
!= rm
&& rd1
!= rm
)
497 tcg_out32(s
, (cond
<< 28) | 0x800090 |
498 (rd1
<< 16) | (rd0
<< 12) | (rs
<< 8) | rm
);
499 else if (rd0
!= rs
&& rd1
!= rs
)
500 tcg_out32(s
, (cond
<< 28) | 0x800090 |
501 (rd1
<< 16) | (rd0
<< 12) | (rm
<< 8) | rs
);
503 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
504 TCG_REG_R8
, 0, rm
, SHIFT_IMM_LSL(0));
505 tcg_out32(s
, (cond
<< 28) | 0x800098 |
506 (rd1
<< 16) | (rd0
<< 12) | (rs
<< 8));
510 static inline void tcg_out_smull32(TCGContext
*s
,
511 int cond
, int rd0
, int rd1
, int rs
, int rm
)
513 if (rd0
!= rm
&& rd1
!= rm
)
514 tcg_out32(s
, (cond
<< 28) | 0xc00090 |
515 (rd1
<< 16) | (rd0
<< 12) | (rs
<< 8) | rm
);
516 else if (rd0
!= rs
&& rd1
!= rs
)
517 tcg_out32(s
, (cond
<< 28) | 0xc00090 |
518 (rd1
<< 16) | (rd0
<< 12) | (rm
<< 8) | rs
);
520 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
521 TCG_REG_R8
, 0, rm
, SHIFT_IMM_LSL(0));
522 tcg_out32(s
, (cond
<< 28) | 0xc00098 |
523 (rd1
<< 16) | (rd0
<< 12) | (rs
<< 8));
527 static inline void tcg_out_ext8s(TCGContext
*s
, int cond
,
530 if (use_armv6_instructions
) {
532 tcg_out32(s
, 0x06af0070 | (cond
<< 28) | (rd
<< 12) | rn
);
534 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
535 rd
, 0, rn
, SHIFT_IMM_LSL(24));
536 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
537 rd
, 0, rd
, SHIFT_IMM_ASR(24));
541 static inline void tcg_out_ext8u(TCGContext
*s
, int cond
,
544 tcg_out_dat_imm(s
, cond
, ARITH_AND
, rd
, rn
, 0xff);
547 static inline void tcg_out_ext16s(TCGContext
*s
, int cond
,
550 if (use_armv6_instructions
) {
552 tcg_out32(s
, 0x06bf0070 | (cond
<< 28) | (rd
<< 12) | rn
);
554 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
555 rd
, 0, rn
, SHIFT_IMM_LSL(16));
556 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
557 rd
, 0, rd
, SHIFT_IMM_ASR(16));
561 static inline void tcg_out_ext16u(TCGContext
*s
, int cond
,
564 if (use_armv6_instructions
) {
566 tcg_out32(s
, 0x06ff0070 | (cond
<< 28) | (rd
<< 12) | rn
);
568 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
569 rd
, 0, rn
, SHIFT_IMM_LSL(16));
570 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
571 rd
, 0, rd
, SHIFT_IMM_LSR(16));
575 static inline void tcg_out_bswap16s(TCGContext
*s
, int cond
, int rd
, int rn
)
577 if (use_armv6_instructions
) {
579 tcg_out32(s
, 0x06ff0fb0 | (cond
<< 28) | (rd
<< 12) | rn
);
581 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
582 TCG_REG_R8
, 0, rn
, SHIFT_IMM_LSL(24));
583 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
584 TCG_REG_R8
, 0, TCG_REG_R8
, SHIFT_IMM_ASR(16));
585 tcg_out_dat_reg(s
, cond
, ARITH_ORR
,
586 rd
, TCG_REG_R8
, rn
, SHIFT_IMM_LSR(8));
590 static inline void tcg_out_bswap16(TCGContext
*s
, int cond
, int rd
, int rn
)
592 if (use_armv6_instructions
) {
594 tcg_out32(s
, 0x06bf0fb0 | (cond
<< 28) | (rd
<< 12) | rn
);
596 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
597 TCG_REG_R8
, 0, rn
, SHIFT_IMM_LSL(24));
598 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
599 TCG_REG_R8
, 0, TCG_REG_R8
, SHIFT_IMM_LSR(16));
600 tcg_out_dat_reg(s
, cond
, ARITH_ORR
,
601 rd
, TCG_REG_R8
, rn
, SHIFT_IMM_LSR(8));
605 static inline void tcg_out_bswap32(TCGContext
*s
, int cond
, int rd
, int rn
)
607 if (use_armv6_instructions
) {
609 tcg_out32(s
, 0x06bf0f30 | (cond
<< 28) | (rd
<< 12) | rn
);
611 tcg_out_dat_reg(s
, cond
, ARITH_EOR
,
612 TCG_REG_R8
, rn
, rn
, SHIFT_IMM_ROR(16));
613 tcg_out_dat_imm(s
, cond
, ARITH_BIC
,
614 TCG_REG_R8
, TCG_REG_R8
, 0xff | 0x800);
615 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
616 rd
, 0, rn
, SHIFT_IMM_ROR(8));
617 tcg_out_dat_reg(s
, cond
, ARITH_EOR
,
618 rd
, rd
, TCG_REG_R8
, SHIFT_IMM_LSR(8));
622 static inline void tcg_out_ld32_12(TCGContext
*s
, int cond
,
623 int rd
, int rn
, tcg_target_long im
)
626 tcg_out32(s
, (cond
<< 28) | 0x05900000 |
627 (rn
<< 16) | (rd
<< 12) | (im
& 0xfff));
629 tcg_out32(s
, (cond
<< 28) | 0x05100000 |
630 (rn
<< 16) | (rd
<< 12) | ((-im
) & 0xfff));
633 static inline void tcg_out_st32_12(TCGContext
*s
, int cond
,
634 int rd
, int rn
, tcg_target_long im
)
637 tcg_out32(s
, (cond
<< 28) | 0x05800000 |
638 (rn
<< 16) | (rd
<< 12) | (im
& 0xfff));
640 tcg_out32(s
, (cond
<< 28) | 0x05000000 |
641 (rn
<< 16) | (rd
<< 12) | ((-im
) & 0xfff));
644 static inline void tcg_out_ld32_r(TCGContext
*s
, int cond
,
645 int rd
, int rn
, int rm
)
647 tcg_out32(s
, (cond
<< 28) | 0x07900000 |
648 (rn
<< 16) | (rd
<< 12) | rm
);
651 static inline void tcg_out_st32_r(TCGContext
*s
, int cond
,
652 int rd
, int rn
, int rm
)
654 tcg_out32(s
, (cond
<< 28) | 0x07800000 |
655 (rn
<< 16) | (rd
<< 12) | rm
);
658 /* Register pre-increment with base writeback. */
659 static inline void tcg_out_ld32_rwb(TCGContext
*s
, int cond
,
660 int rd
, int rn
, int rm
)
662 tcg_out32(s
, (cond
<< 28) | 0x07b00000 |
663 (rn
<< 16) | (rd
<< 12) | rm
);
666 static inline void tcg_out_st32_rwb(TCGContext
*s
, int cond
,
667 int rd
, int rn
, int rm
)
669 tcg_out32(s
, (cond
<< 28) | 0x07a00000 |
670 (rn
<< 16) | (rd
<< 12) | rm
);
673 static inline void tcg_out_ld16u_8(TCGContext
*s
, int cond
,
674 int rd
, int rn
, tcg_target_long im
)
677 tcg_out32(s
, (cond
<< 28) | 0x01d000b0 |
678 (rn
<< 16) | (rd
<< 12) |
679 ((im
& 0xf0) << 4) | (im
& 0xf));
681 tcg_out32(s
, (cond
<< 28) | 0x015000b0 |
682 (rn
<< 16) | (rd
<< 12) |
683 (((-im
) & 0xf0) << 4) | ((-im
) & 0xf));
686 static inline void tcg_out_st16_8(TCGContext
*s
, int cond
,
687 int rd
, int rn
, tcg_target_long im
)
690 tcg_out32(s
, (cond
<< 28) | 0x01c000b0 |
691 (rn
<< 16) | (rd
<< 12) |
692 ((im
& 0xf0) << 4) | (im
& 0xf));
694 tcg_out32(s
, (cond
<< 28) | 0x014000b0 |
695 (rn
<< 16) | (rd
<< 12) |
696 (((-im
) & 0xf0) << 4) | ((-im
) & 0xf));
699 static inline void tcg_out_ld16u_r(TCGContext
*s
, int cond
,
700 int rd
, int rn
, int rm
)
702 tcg_out32(s
, (cond
<< 28) | 0x019000b0 |
703 (rn
<< 16) | (rd
<< 12) | rm
);
706 static inline void tcg_out_st16_r(TCGContext
*s
, int cond
,
707 int rd
, int rn
, int rm
)
709 tcg_out32(s
, (cond
<< 28) | 0x018000b0 |
710 (rn
<< 16) | (rd
<< 12) | rm
);
713 static inline void tcg_out_ld16s_8(TCGContext
*s
, int cond
,
714 int rd
, int rn
, tcg_target_long im
)
717 tcg_out32(s
, (cond
<< 28) | 0x01d000f0 |
718 (rn
<< 16) | (rd
<< 12) |
719 ((im
& 0xf0) << 4) | (im
& 0xf));
721 tcg_out32(s
, (cond
<< 28) | 0x015000f0 |
722 (rn
<< 16) | (rd
<< 12) |
723 (((-im
) & 0xf0) << 4) | ((-im
) & 0xf));
726 static inline void tcg_out_ld16s_r(TCGContext
*s
, int cond
,
727 int rd
, int rn
, int rm
)
729 tcg_out32(s
, (cond
<< 28) | 0x019000f0 |
730 (rn
<< 16) | (rd
<< 12) | rm
);
733 static inline void tcg_out_ld8_12(TCGContext
*s
, int cond
,
734 int rd
, int rn
, tcg_target_long im
)
737 tcg_out32(s
, (cond
<< 28) | 0x05d00000 |
738 (rn
<< 16) | (rd
<< 12) | (im
& 0xfff));
740 tcg_out32(s
, (cond
<< 28) | 0x05500000 |
741 (rn
<< 16) | (rd
<< 12) | ((-im
) & 0xfff));
744 static inline void tcg_out_st8_12(TCGContext
*s
, int cond
,
745 int rd
, int rn
, tcg_target_long im
)
748 tcg_out32(s
, (cond
<< 28) | 0x05c00000 |
749 (rn
<< 16) | (rd
<< 12) | (im
& 0xfff));
751 tcg_out32(s
, (cond
<< 28) | 0x05400000 |
752 (rn
<< 16) | (rd
<< 12) | ((-im
) & 0xfff));
755 static inline void tcg_out_ld8_r(TCGContext
*s
, int cond
,
756 int rd
, int rn
, int rm
)
758 tcg_out32(s
, (cond
<< 28) | 0x07d00000 |
759 (rn
<< 16) | (rd
<< 12) | rm
);
762 static inline void tcg_out_st8_r(TCGContext
*s
, int cond
,
763 int rd
, int rn
, int rm
)
765 tcg_out32(s
, (cond
<< 28) | 0x07c00000 |
766 (rn
<< 16) | (rd
<< 12) | rm
);
769 static inline void tcg_out_ld8s_8(TCGContext
*s
, int cond
,
770 int rd
, int rn
, tcg_target_long im
)
773 tcg_out32(s
, (cond
<< 28) | 0x01d000d0 |
774 (rn
<< 16) | (rd
<< 12) |
775 ((im
& 0xf0) << 4) | (im
& 0xf));
777 tcg_out32(s
, (cond
<< 28) | 0x015000d0 |
778 (rn
<< 16) | (rd
<< 12) |
779 (((-im
) & 0xf0) << 4) | ((-im
) & 0xf));
782 static inline void tcg_out_ld8s_r(TCGContext
*s
, int cond
,
783 int rd
, int rn
, int rm
)
785 tcg_out32(s
, (cond
<< 28) | 0x019000d0 |
786 (rn
<< 16) | (rd
<< 12) | rm
);
789 static inline void tcg_out_ld32u(TCGContext
*s
, int cond
,
790 int rd
, int rn
, int32_t offset
)
792 if (offset
> 0xfff || offset
< -0xfff) {
793 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
794 tcg_out_ld32_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
796 tcg_out_ld32_12(s
, cond
, rd
, rn
, offset
);
799 static inline void tcg_out_st32(TCGContext
*s
, int cond
,
800 int rd
, int rn
, int32_t offset
)
802 if (offset
> 0xfff || offset
< -0xfff) {
803 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
804 tcg_out_st32_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
806 tcg_out_st32_12(s
, cond
, rd
, rn
, offset
);
809 static inline void tcg_out_ld16u(TCGContext
*s
, int cond
,
810 int rd
, int rn
, int32_t offset
)
812 if (offset
> 0xff || offset
< -0xff) {
813 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
814 tcg_out_ld16u_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
816 tcg_out_ld16u_8(s
, cond
, rd
, rn
, offset
);
819 static inline void tcg_out_ld16s(TCGContext
*s
, int cond
,
820 int rd
, int rn
, int32_t offset
)
822 if (offset
> 0xff || offset
< -0xff) {
823 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
824 tcg_out_ld16s_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
826 tcg_out_ld16s_8(s
, cond
, rd
, rn
, offset
);
829 static inline void tcg_out_st16(TCGContext
*s
, int cond
,
830 int rd
, int rn
, int32_t offset
)
832 if (offset
> 0xff || offset
< -0xff) {
833 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
834 tcg_out_st16_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
836 tcg_out_st16_8(s
, cond
, rd
, rn
, offset
);
839 static inline void tcg_out_ld8u(TCGContext
*s
, int cond
,
840 int rd
, int rn
, int32_t offset
)
842 if (offset
> 0xfff || offset
< -0xfff) {
843 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
844 tcg_out_ld8_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
846 tcg_out_ld8_12(s
, cond
, rd
, rn
, offset
);
849 static inline void tcg_out_ld8s(TCGContext
*s
, int cond
,
850 int rd
, int rn
, int32_t offset
)
852 if (offset
> 0xff || offset
< -0xff) {
853 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
854 tcg_out_ld8s_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
856 tcg_out_ld8s_8(s
, cond
, rd
, rn
, offset
);
859 static inline void tcg_out_st8(TCGContext
*s
, int cond
,
860 int rd
, int rn
, int32_t offset
)
862 if (offset
> 0xfff || offset
< -0xfff) {
863 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
864 tcg_out_st8_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
866 tcg_out_st8_12(s
, cond
, rd
, rn
, offset
);
869 /* The _goto case is normally between TBs within the same code buffer,
870 * and with the code buffer limited to 16MB we shouldn't need the long
873 * .... except to the prologue that is in its own buffer.
875 static inline void tcg_out_goto(TCGContext
*s
, int cond
, uint32_t addr
)
880 /* goto to a Thumb destination isn't supported */
884 val
= addr
- (tcg_target_long
) s
->code_ptr
;
885 if (val
- 8 < 0x01fffffd && val
- 8 > -0x01fffffd)
886 tcg_out_b(s
, cond
, val
);
888 if (cond
== COND_AL
) {
889 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_PC
, -4);
892 tcg_out_movi32(s
, cond
, TCG_REG_R8
, val
- 8);
893 tcg_out_dat_reg(s
, cond
, ARITH_ADD
,
894 TCG_REG_PC
, TCG_REG_PC
,
895 TCG_REG_R8
, SHIFT_IMM_LSL(0));
900 /* The call case is mostly used for helpers - so it's not unreasonable
901 * for them to be beyond branch range */
902 static inline void tcg_out_call(TCGContext
*s
, uint32_t addr
)
906 val
= addr
- (tcg_target_long
) s
->code_ptr
;
907 if (val
- 8 < 0x02000000 && val
- 8 >= -0x02000000) {
909 /* Use BLX if the target is in Thumb mode */
910 if (!use_armv5_instructions
) {
913 tcg_out_blx_imm(s
, val
);
915 tcg_out_bl(s
, COND_AL
, val
);
918 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, TCG_REG_R14
, TCG_REG_PC
, 4);
919 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_PC
, -4);
924 static inline void tcg_out_callr(TCGContext
*s
, int cond
, int arg
)
926 if (use_armv5_instructions
) {
927 tcg_out_blx(s
, cond
, arg
);
929 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, TCG_REG_R14
, 0,
930 TCG_REG_PC
, SHIFT_IMM_LSL(0));
931 tcg_out_bx(s
, cond
, arg
);
935 static inline void tcg_out_goto_label(TCGContext
*s
, int cond
, int label_index
)
937 TCGLabel
*l
= &s
->labels
[label_index
];
940 tcg_out_goto(s
, cond
, l
->u
.value
);
941 else if (cond
== COND_AL
) {
942 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_PC
, -4);
943 tcg_out_reloc(s
, s
->code_ptr
, R_ARM_ABS32
, label_index
, 31337);
946 /* Probably this should be preferred even for COND_AL... */
947 tcg_out_reloc(s
, s
->code_ptr
, R_ARM_PC24
, label_index
, 31337);
948 tcg_out_b_noaddr(s
, cond
);
952 #ifdef CONFIG_SOFTMMU
954 #include "../../softmmu_defs.h"
956 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
958 static const void * const qemu_ld_helpers
[4] = {
965 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
966 uintxx_t val, int mmu_idx) */
967 static const void * const qemu_st_helpers
[4] = {
974 /* Helper routines for marshalling helper function arguments into
975 * the correct registers and stack.
976 * argreg is where we want to put this argument, arg is the argument itself.
977 * Return value is the updated argreg ready for the next call.
978 * Note that argreg 0..3 is real registers, 4+ on stack.
979 * When we reach the first stacked argument, we allocate space for it
980 * and the following stacked arguments using "str r8, [sp, #-0x10]!".
981 * Following arguments are filled in with "str r8, [sp, #0xNN]".
982 * For more than 4 stacked arguments we'd need to know how much
983 * space to allocate when we pushed the first stacked argument.
984 * We don't need this, so don't implement it (and will assert if you try it.)
986 * We provide routines for arguments which are: immediate, 32 bit
987 * value in register, 16 and 8 bit values in register (which must be zero
988 * extended before use) and 64 bit value in a lo:hi register pair.
990 #define DEFINE_TCG_OUT_ARG(NAME, ARGPARAM) \
991 static TCGReg NAME(TCGContext *s, TCGReg argreg, ARGPARAM) \
994 TCG_OUT_ARG_GET_ARG(argreg); \
995 } else if (argreg == 4) { \
996 TCG_OUT_ARG_GET_ARG(TCG_REG_R8); \
997 tcg_out32(s, (COND_AL << 28) | 0x052d8010); \
999 assert(argreg < 8); \
1000 TCG_OUT_ARG_GET_ARG(TCG_REG_R8); \
1001 tcg_out32(s, (COND_AL << 28) | 0x058d8000 | (argreg - 4) * 4); \
1003 return argreg + 1; \
1006 #define TCG_OUT_ARG_GET_ARG(A) tcg_out_dat_imm(s, COND_AL, ARITH_MOV, A, 0, arg)
1007 DEFINE_TCG_OUT_ARG(tcg_out_arg_imm32
, uint32_t arg
)
1008 #undef TCG_OUT_ARG_GET_ARG
1009 #define TCG_OUT_ARG_GET_ARG(A) tcg_out_ext8u(s, COND_AL, A, arg)
1010 DEFINE_TCG_OUT_ARG(tcg_out_arg_reg8
, TCGReg arg
)
1011 #undef TCG_OUT_ARG_GET_ARG
1012 #define TCG_OUT_ARG_GET_ARG(A) tcg_out_ext16u(s, COND_AL, A, arg)
1013 DEFINE_TCG_OUT_ARG(tcg_out_arg_reg16
, TCGReg arg
)
1014 #undef TCG_OUT_ARG_GET_ARG
1016 /* We don't use the macro for this one to avoid an unnecessary reg-reg
1017 * move when storing to the stack.
1019 static TCGReg
tcg_out_arg_reg32(TCGContext
*s
, TCGReg argreg
, TCGReg arg
)
1022 tcg_out_mov_reg(s
, COND_AL
, argreg
, arg
);
1023 } else if (argreg
== 4) {
1024 /* str arg, [sp, #-0x10]! */
1025 tcg_out32(s
, (COND_AL
<< 28) | 0x052d0010 | (arg
<< 12));
1028 /* str arg, [sp, #0xNN] */
1029 tcg_out32(s
, (COND_AL
<< 28) | 0x058d0000 |
1030 (arg
<< 12) | (argreg
- 4) * 4);
1035 static inline TCGReg
tcg_out_arg_reg64(TCGContext
*s
, TCGReg argreg
,
1036 TCGReg arglo
, TCGReg arghi
)
1038 /* 64 bit arguments must go in even/odd register pairs
1039 * and in 8-aligned stack slots.
1044 argreg
= tcg_out_arg_reg32(s
, argreg
, arglo
);
1045 argreg
= tcg_out_arg_reg32(s
, argreg
, arghi
);
1049 static inline void tcg_out_arg_stacktidy(TCGContext
*s
, TCGReg argreg
)
1051 /* Output any necessary post-call cleanup of the stack */
1053 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, TCG_REG_R13
, TCG_REG_R13
, 0x10);
1059 #define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
1061 static inline void tcg_out_qemu_ld(TCGContext
*s
, const TCGArg
*args
, int opc
)
1063 int addr_reg
, data_reg
, data_reg2
, bswap
;
1064 #ifdef CONFIG_SOFTMMU
1065 int mem_index
, s_bits
;
1067 # if TARGET_LONG_BITS == 64
1070 uint32_t *label_ptr
;
1073 #ifdef TARGET_WORDS_BIGENDIAN
1080 data_reg2
= *args
++;
1082 data_reg2
= 0; /* suppress warning */
1084 #ifdef CONFIG_SOFTMMU
1085 # if TARGET_LONG_BITS == 64
1086 addr_reg2
= *args
++;
1091 /* Should generate something like the following:
1092 * shr r8, addr_reg, #TARGET_PAGE_BITS
1093 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
1094 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
1096 # if CPU_TLB_BITS > 8
1099 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, TCG_REG_R8
,
1100 0, addr_reg
, SHIFT_IMM_LSR(TARGET_PAGE_BITS
));
1101 tcg_out_dat_imm(s
, COND_AL
, ARITH_AND
,
1102 TCG_REG_R0
, TCG_REG_R8
, CPU_TLB_SIZE
- 1);
1103 tcg_out_dat_reg(s
, COND_AL
, ARITH_ADD
, TCG_REG_R0
, TCG_AREG0
,
1104 TCG_REG_R0
, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS
));
1106 * ldr r1 [r0, #(offsetof(CPUArchState, tlb_table[mem_index][0].addr_read))]
1107 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
1108 * not exceed otherwise, so use an
1109 * add r0, r0, #(mem_index * sizeof *CPUArchState.tlb_table)
1113 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, TCG_REG_R0
, TCG_REG_R0
,
1114 (mem_index
<< (TLB_SHIFT
& 1)) |
1115 ((16 - (TLB_SHIFT
>> 1)) << 8));
1116 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_R1
, TCG_REG_R0
,
1117 offsetof(CPUArchState
, tlb_table
[0][0].addr_read
));
1118 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0, TCG_REG_R1
,
1119 TCG_REG_R8
, SHIFT_IMM_LSL(TARGET_PAGE_BITS
));
1120 /* Check alignment. */
1122 tcg_out_dat_imm(s
, COND_EQ
, ARITH_TST
,
1123 0, addr_reg
, (1 << s_bits
) - 1);
1124 # if TARGET_LONG_BITS == 64
1125 /* XXX: possibly we could use a block data load or writeback in
1126 * the first access. */
1127 tcg_out_ld32_12(s
, COND_EQ
, TCG_REG_R1
, TCG_REG_R0
,
1128 offsetof(CPUArchState
, tlb_table
[0][0].addr_read
) + 4);
1129 tcg_out_dat_reg(s
, COND_EQ
, ARITH_CMP
, 0,
1130 TCG_REG_R1
, addr_reg2
, SHIFT_IMM_LSL(0));
1132 tcg_out_ld32_12(s
, COND_EQ
, TCG_REG_R1
, TCG_REG_R0
,
1133 offsetof(CPUArchState
, tlb_table
[0][0].addend
));
1137 tcg_out_ld8_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
1140 tcg_out_ld8s_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
1143 tcg_out_ld16u_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
1145 tcg_out_bswap16(s
, COND_EQ
, data_reg
, data_reg
);
1150 tcg_out_ld16u_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
1151 tcg_out_bswap16s(s
, COND_EQ
, data_reg
, data_reg
);
1153 tcg_out_ld16s_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
1158 tcg_out_ld32_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
1160 tcg_out_bswap32(s
, COND_EQ
, data_reg
, data_reg
);
1165 tcg_out_ld32_rwb(s
, COND_EQ
, data_reg2
, TCG_REG_R1
, addr_reg
);
1166 tcg_out_ld32_12(s
, COND_EQ
, data_reg
, TCG_REG_R1
, 4);
1167 tcg_out_bswap32(s
, COND_EQ
, data_reg2
, data_reg2
);
1168 tcg_out_bswap32(s
, COND_EQ
, data_reg
, data_reg
);
1170 tcg_out_ld32_rwb(s
, COND_EQ
, data_reg
, TCG_REG_R1
, addr_reg
);
1171 tcg_out_ld32_12(s
, COND_EQ
, data_reg2
, TCG_REG_R1
, 4);
1176 label_ptr
= (void *) s
->code_ptr
;
1177 tcg_out_b_noaddr(s
, COND_EQ
);
1179 /* TODO: move this code to where the constants pool will be */
1180 /* Note that this code relies on the constraints we set in arm_op_defs[]
1181 * to ensure that later arguments are not passed to us in registers we
1182 * trash by moving the earlier arguments into them.
1184 argreg
= TCG_REG_R0
;
1185 argreg
= tcg_out_arg_reg32(s
, argreg
, TCG_AREG0
);
1186 #if TARGET_LONG_BITS == 64
1187 argreg
= tcg_out_arg_reg64(s
, argreg
, addr_reg
, addr_reg2
);
1189 argreg
= tcg_out_arg_reg32(s
, argreg
, addr_reg
);
1191 argreg
= tcg_out_arg_imm32(s
, argreg
, mem_index
);
1192 tcg_out_call(s
, (tcg_target_long
) qemu_ld_helpers
[s_bits
]);
1193 tcg_out_arg_stacktidy(s
, argreg
);
1197 tcg_out_ext8s(s
, COND_AL
, data_reg
, TCG_REG_R0
);
1200 tcg_out_ext16s(s
, COND_AL
, data_reg
, TCG_REG_R0
);
1206 if (data_reg
!= TCG_REG_R0
) {
1207 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1208 data_reg
, 0, TCG_REG_R0
, SHIFT_IMM_LSL(0));
1212 if (data_reg
!= TCG_REG_R0
) {
1213 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1214 data_reg
, 0, TCG_REG_R0
, SHIFT_IMM_LSL(0));
1216 if (data_reg2
!= TCG_REG_R1
) {
1217 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1218 data_reg2
, 0, TCG_REG_R1
, SHIFT_IMM_LSL(0));
1223 reloc_pc24(label_ptr
, (tcg_target_long
)s
->code_ptr
);
1224 #else /* !CONFIG_SOFTMMU */
1226 uint32_t offset
= GUEST_BASE
;
1231 i
= ctz32(offset
) & ~1;
1232 rot
= ((32 - i
) << 7) & 0xf00;
1234 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, TCG_REG_R8
, addr_reg
,
1235 ((offset
>> i
) & 0xff) | rot
);
1236 addr_reg
= TCG_REG_R8
;
1237 offset
&= ~(0xff << i
);
1242 tcg_out_ld8_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1245 tcg_out_ld8s_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
1248 tcg_out_ld16u_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
1250 tcg_out_bswap16(s
, COND_AL
, data_reg
, data_reg
);
1255 tcg_out_ld16u_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
1256 tcg_out_bswap16s(s
, COND_AL
, data_reg
, data_reg
);
1258 tcg_out_ld16s_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
1263 tcg_out_ld32_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1265 tcg_out_bswap32(s
, COND_AL
, data_reg
, data_reg
);
1269 /* TODO: use block load -
1270 * check that data_reg2 > data_reg or the other way */
1271 if (data_reg
== addr_reg
) {
1272 tcg_out_ld32_12(s
, COND_AL
, data_reg2
, addr_reg
, bswap
? 0 : 4);
1273 tcg_out_ld32_12(s
, COND_AL
, data_reg
, addr_reg
, bswap
? 4 : 0);
1275 tcg_out_ld32_12(s
, COND_AL
, data_reg
, addr_reg
, bswap
? 4 : 0);
1276 tcg_out_ld32_12(s
, COND_AL
, data_reg2
, addr_reg
, bswap
? 0 : 4);
1279 tcg_out_bswap32(s
, COND_AL
, data_reg
, data_reg
);
1280 tcg_out_bswap32(s
, COND_AL
, data_reg2
, data_reg2
);
1287 static inline void tcg_out_qemu_st(TCGContext
*s
, const TCGArg
*args
, int opc
)
1289 int addr_reg
, data_reg
, data_reg2
, bswap
;
1290 #ifdef CONFIG_SOFTMMU
1291 int mem_index
, s_bits
;
1293 # if TARGET_LONG_BITS == 64
1296 uint32_t *label_ptr
;
1299 #ifdef TARGET_WORDS_BIGENDIAN
1306 data_reg2
= *args
++;
1308 data_reg2
= 0; /* suppress warning */
1310 #ifdef CONFIG_SOFTMMU
1311 # if TARGET_LONG_BITS == 64
1312 addr_reg2
= *args
++;
1317 /* Should generate something like the following:
1318 * shr r8, addr_reg, #TARGET_PAGE_BITS
1319 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
1320 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
1322 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1323 TCG_REG_R8
, 0, addr_reg
, SHIFT_IMM_LSR(TARGET_PAGE_BITS
));
1324 tcg_out_dat_imm(s
, COND_AL
, ARITH_AND
,
1325 TCG_REG_R0
, TCG_REG_R8
, CPU_TLB_SIZE
- 1);
1326 tcg_out_dat_reg(s
, COND_AL
, ARITH_ADD
, TCG_REG_R0
,
1327 TCG_AREG0
, TCG_REG_R0
, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS
));
1329 * ldr r1 [r0, #(offsetof(CPUArchState, tlb_table[mem_index][0].addr_write))]
1330 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
1331 * not exceed otherwise, so use an
1332 * add r0, r0, #(mem_index * sizeof *CPUArchState.tlb_table)
1336 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, TCG_REG_R0
, TCG_REG_R0
,
1337 (mem_index
<< (TLB_SHIFT
& 1)) |
1338 ((16 - (TLB_SHIFT
>> 1)) << 8));
1339 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_R1
, TCG_REG_R0
,
1340 offsetof(CPUArchState
, tlb_table
[0][0].addr_write
));
1341 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0, TCG_REG_R1
,
1342 TCG_REG_R8
, SHIFT_IMM_LSL(TARGET_PAGE_BITS
));
1343 /* Check alignment. */
1345 tcg_out_dat_imm(s
, COND_EQ
, ARITH_TST
,
1346 0, addr_reg
, (1 << s_bits
) - 1);
1347 # if TARGET_LONG_BITS == 64
1348 /* XXX: possibly we could use a block data load or writeback in
1349 * the first access. */
1350 tcg_out_ld32_12(s
, COND_EQ
, TCG_REG_R1
, TCG_REG_R0
,
1351 offsetof(CPUArchState
, tlb_table
[0][0].addr_write
) + 4);
1352 tcg_out_dat_reg(s
, COND_EQ
, ARITH_CMP
, 0,
1353 TCG_REG_R1
, addr_reg2
, SHIFT_IMM_LSL(0));
1355 tcg_out_ld32_12(s
, COND_EQ
, TCG_REG_R1
, TCG_REG_R0
,
1356 offsetof(CPUArchState
, tlb_table
[0][0].addend
));
1360 tcg_out_st8_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
1364 tcg_out_bswap16(s
, COND_EQ
, TCG_REG_R0
, data_reg
);
1365 tcg_out_st16_r(s
, COND_EQ
, TCG_REG_R0
, addr_reg
, TCG_REG_R1
);
1367 tcg_out_st16_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
1373 tcg_out_bswap32(s
, COND_EQ
, TCG_REG_R0
, data_reg
);
1374 tcg_out_st32_r(s
, COND_EQ
, TCG_REG_R0
, addr_reg
, TCG_REG_R1
);
1376 tcg_out_st32_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
1381 tcg_out_bswap32(s
, COND_EQ
, TCG_REG_R0
, data_reg2
);
1382 tcg_out_st32_rwb(s
, COND_EQ
, TCG_REG_R0
, TCG_REG_R1
, addr_reg
);
1383 tcg_out_bswap32(s
, COND_EQ
, TCG_REG_R0
, data_reg
);
1384 tcg_out_st32_12(s
, COND_EQ
, TCG_REG_R0
, TCG_REG_R1
, 4);
1386 tcg_out_st32_rwb(s
, COND_EQ
, data_reg
, TCG_REG_R1
, addr_reg
);
1387 tcg_out_st32_12(s
, COND_EQ
, data_reg2
, TCG_REG_R1
, 4);
1392 label_ptr
= (void *) s
->code_ptr
;
1393 tcg_out_b_noaddr(s
, COND_EQ
);
1395 /* TODO: move this code to where the constants pool will be */
1396 /* Note that this code relies on the constraints we set in arm_op_defs[]
1397 * to ensure that later arguments are not passed to us in registers we
1398 * trash by moving the earlier arguments into them.
1400 argreg
= TCG_REG_R0
;
1401 argreg
= tcg_out_arg_reg32(s
, argreg
, TCG_AREG0
);
1402 #if TARGET_LONG_BITS == 64
1403 argreg
= tcg_out_arg_reg64(s
, argreg
, addr_reg
, addr_reg2
);
1405 argreg
= tcg_out_arg_reg32(s
, argreg
, addr_reg
);
1410 argreg
= tcg_out_arg_reg8(s
, argreg
, data_reg
);
1413 argreg
= tcg_out_arg_reg16(s
, argreg
, data_reg
);
1416 argreg
= tcg_out_arg_reg32(s
, argreg
, data_reg
);
1419 argreg
= tcg_out_arg_reg64(s
, argreg
, data_reg
, data_reg2
);
1423 argreg
= tcg_out_arg_imm32(s
, argreg
, mem_index
);
1424 tcg_out_call(s
, (tcg_target_long
) qemu_st_helpers
[s_bits
]);
1425 tcg_out_arg_stacktidy(s
, argreg
);
1427 reloc_pc24(label_ptr
, (tcg_target_long
)s
->code_ptr
);
1428 #else /* !CONFIG_SOFTMMU */
1430 uint32_t offset
= GUEST_BASE
;
1435 i
= ctz32(offset
) & ~1;
1436 rot
= ((32 - i
) << 7) & 0xf00;
1438 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, TCG_REG_R1
, addr_reg
,
1439 ((offset
>> i
) & 0xff) | rot
);
1440 addr_reg
= TCG_REG_R1
;
1441 offset
&= ~(0xff << i
);
1446 tcg_out_st8_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1450 tcg_out_bswap16(s
, COND_AL
, TCG_REG_R0
, data_reg
);
1451 tcg_out_st16_8(s
, COND_AL
, TCG_REG_R0
, addr_reg
, 0);
1453 tcg_out_st16_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
1459 tcg_out_bswap32(s
, COND_AL
, TCG_REG_R0
, data_reg
);
1460 tcg_out_st32_12(s
, COND_AL
, TCG_REG_R0
, addr_reg
, 0);
1462 tcg_out_st32_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1466 /* TODO: use block store -
1467 * check that data_reg2 > data_reg or the other way */
1469 tcg_out_bswap32(s
, COND_AL
, TCG_REG_R0
, data_reg2
);
1470 tcg_out_st32_12(s
, COND_AL
, TCG_REG_R0
, addr_reg
, 0);
1471 tcg_out_bswap32(s
, COND_AL
, TCG_REG_R0
, data_reg
);
1472 tcg_out_st32_12(s
, COND_AL
, TCG_REG_R0
, addr_reg
, 4);
1474 tcg_out_st32_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1475 tcg_out_st32_12(s
, COND_AL
, data_reg2
, addr_reg
, 4);
1482 static uint8_t *tb_ret_addr
;
1484 static inline void tcg_out_op(TCGContext
*s
, TCGOpcode opc
,
1485 const TCGArg
*args
, const int *const_args
)
1490 case INDEX_op_exit_tb
:
1492 uint8_t *ld_ptr
= s
->code_ptr
;
1494 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_R0
, TCG_REG_PC
, 0);
1496 tcg_out_dat_imm(s
, COND_AL
, ARITH_MOV
, TCG_REG_R0
, 0, args
[0]);
1497 tcg_out_goto(s
, COND_AL
, (tcg_target_ulong
) tb_ret_addr
);
1499 *ld_ptr
= (uint8_t) (s
->code_ptr
- ld_ptr
) - 8;
1500 tcg_out32(s
, args
[0]);
1504 case INDEX_op_goto_tb
:
1505 if (s
->tb_jmp_offset
) {
1506 /* Direct jump method */
1507 #if defined(USE_DIRECT_JUMP)
1508 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1509 tcg_out_b_noaddr(s
, COND_AL
);
1511 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_PC
, -4);
1512 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1516 /* Indirect jump method */
1518 c
= (int) (s
->tb_next
+ args
[0]) - ((int) s
->code_ptr
+ 8);
1519 if (c
> 0xfff || c
< -0xfff) {
1520 tcg_out_movi32(s
, COND_AL
, TCG_REG_R0
,
1521 (tcg_target_long
) (s
->tb_next
+ args
[0]));
1522 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_R0
, 0);
1524 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_PC
, c
);
1526 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_R0
, TCG_REG_PC
, 0);
1527 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_R0
, 0);
1528 tcg_out32(s
, (tcg_target_long
) (s
->tb_next
+ args
[0]));
1531 s
->tb_next_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1535 tcg_out_call(s
, args
[0]);
1537 tcg_out_callr(s
, COND_AL
, args
[0]);
1541 tcg_out_goto(s
, COND_AL
, args
[0]);
1543 tcg_out_bx(s
, COND_AL
, args
[0]);
1546 tcg_out_goto_label(s
, COND_AL
, args
[0]);
1549 case INDEX_op_ld8u_i32
:
1550 tcg_out_ld8u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1552 case INDEX_op_ld8s_i32
:
1553 tcg_out_ld8s(s
, COND_AL
, args
[0], args
[1], args
[2]);
1555 case INDEX_op_ld16u_i32
:
1556 tcg_out_ld16u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1558 case INDEX_op_ld16s_i32
:
1559 tcg_out_ld16s(s
, COND_AL
, args
[0], args
[1], args
[2]);
1561 case INDEX_op_ld_i32
:
1562 tcg_out_ld32u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1564 case INDEX_op_st8_i32
:
1565 tcg_out_st8(s
, COND_AL
, args
[0], args
[1], args
[2]);
1567 case INDEX_op_st16_i32
:
1568 tcg_out_st16(s
, COND_AL
, args
[0], args
[1], args
[2]);
1570 case INDEX_op_st_i32
:
1571 tcg_out_st32(s
, COND_AL
, args
[0], args
[1], args
[2]);
1574 case INDEX_op_mov_i32
:
1575 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1576 args
[0], 0, args
[1], SHIFT_IMM_LSL(0));
1578 case INDEX_op_movi_i32
:
1579 tcg_out_movi32(s
, COND_AL
, args
[0], args
[1]);
1581 case INDEX_op_add_i32
:
1584 case INDEX_op_sub_i32
:
1587 case INDEX_op_and_i32
:
1590 case INDEX_op_andc_i32
:
1593 case INDEX_op_or_i32
:
1596 case INDEX_op_xor_i32
:
1600 if (const_args
[2]) {
1602 rot
= encode_imm(args
[2]);
1603 tcg_out_dat_imm(s
, COND_AL
, c
,
1604 args
[0], args
[1], rotl(args
[2], rot
) | (rot
<< 7));
1606 tcg_out_dat_reg(s
, COND_AL
, c
,
1607 args
[0], args
[1], args
[2], SHIFT_IMM_LSL(0));
1609 case INDEX_op_add2_i32
:
1610 tcg_out_dat_reg2(s
, COND_AL
, ARITH_ADD
, ARITH_ADC
,
1611 args
[0], args
[1], args
[2], args
[3],
1612 args
[4], args
[5], SHIFT_IMM_LSL(0));
1614 case INDEX_op_sub2_i32
:
1615 tcg_out_dat_reg2(s
, COND_AL
, ARITH_SUB
, ARITH_SBC
,
1616 args
[0], args
[1], args
[2], args
[3],
1617 args
[4], args
[5], SHIFT_IMM_LSL(0));
1619 case INDEX_op_neg_i32
:
1620 tcg_out_dat_imm(s
, COND_AL
, ARITH_RSB
, args
[0], args
[1], 0);
1622 case INDEX_op_not_i32
:
1623 tcg_out_dat_reg(s
, COND_AL
,
1624 ARITH_MVN
, args
[0], 0, args
[1], SHIFT_IMM_LSL(0));
1626 case INDEX_op_mul_i32
:
1627 tcg_out_mul32(s
, COND_AL
, args
[0], args
[1], args
[2]);
1629 case INDEX_op_mulu2_i32
:
1630 tcg_out_umull32(s
, COND_AL
, args
[0], args
[1], args
[2], args
[3]);
1632 /* XXX: Perhaps args[2] & 0x1f is wrong */
1633 case INDEX_op_shl_i32
:
1635 SHIFT_IMM_LSL(args
[2] & 0x1f) : SHIFT_REG_LSL(args
[2]);
1637 case INDEX_op_shr_i32
:
1638 c
= const_args
[2] ? (args
[2] & 0x1f) ? SHIFT_IMM_LSR(args
[2] & 0x1f) :
1639 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args
[2]);
1641 case INDEX_op_sar_i32
:
1642 c
= const_args
[2] ? (args
[2] & 0x1f) ? SHIFT_IMM_ASR(args
[2] & 0x1f) :
1643 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args
[2]);
1645 case INDEX_op_rotr_i32
:
1646 c
= const_args
[2] ? (args
[2] & 0x1f) ? SHIFT_IMM_ROR(args
[2] & 0x1f) :
1647 SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args
[2]);
1650 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, args
[0], 0, args
[1], c
);
1653 case INDEX_op_rotl_i32
:
1654 if (const_args
[2]) {
1655 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, args
[0], 0, args
[1],
1656 ((0x20 - args
[2]) & 0x1f) ?
1657 SHIFT_IMM_ROR((0x20 - args
[2]) & 0x1f) :
1660 tcg_out_dat_imm(s
, COND_AL
, ARITH_RSB
, TCG_REG_R8
, args
[1], 0x20);
1661 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, args
[0], 0, args
[1],
1662 SHIFT_REG_ROR(TCG_REG_R8
));
1666 case INDEX_op_brcond_i32
:
1667 if (const_args
[1]) {
1669 rot
= encode_imm(args
[1]);
1670 tcg_out_dat_imm(s
, COND_AL
, ARITH_CMP
, 0,
1671 args
[0], rotl(args
[1], rot
) | (rot
<< 7));
1673 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0,
1674 args
[0], args
[1], SHIFT_IMM_LSL(0));
1676 tcg_out_goto_label(s
, tcg_cond_to_arm_cond
[args
[2]], args
[3]);
1678 case INDEX_op_brcond2_i32
:
1679 /* The resulting conditions are:
1680 * TCG_COND_EQ --> a0 == a2 && a1 == a3,
1681 * TCG_COND_NE --> (a0 != a2 && a1 == a3) || a1 != a3,
1682 * TCG_COND_LT(U) --> (a0 < a2 && a1 == a3) || a1 < a3,
1683 * TCG_COND_GE(U) --> (a0 >= a2 && a1 == a3) || (a1 >= a3 && a1 != a3),
1684 * TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3),
1685 * TCG_COND_GT(U) --> (a0 > a2 && a1 == a3) || a1 > a3,
1687 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0,
1688 args
[1], args
[3], SHIFT_IMM_LSL(0));
1689 tcg_out_dat_reg(s
, COND_EQ
, ARITH_CMP
, 0,
1690 args
[0], args
[2], SHIFT_IMM_LSL(0));
1691 tcg_out_goto_label(s
, tcg_cond_to_arm_cond
[args
[4]], args
[5]);
1693 case INDEX_op_setcond_i32
:
1694 if (const_args
[2]) {
1696 rot
= encode_imm(args
[2]);
1697 tcg_out_dat_imm(s
, COND_AL
, ARITH_CMP
, 0,
1698 args
[1], rotl(args
[2], rot
) | (rot
<< 7));
1700 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0,
1701 args
[1], args
[2], SHIFT_IMM_LSL(0));
1703 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[args
[3]],
1704 ARITH_MOV
, args
[0], 0, 1);
1705 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[tcg_invert_cond(args
[3])],
1706 ARITH_MOV
, args
[0], 0, 0);
1708 case INDEX_op_setcond2_i32
:
1709 /* See brcond2_i32 comment */
1710 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0,
1711 args
[2], args
[4], SHIFT_IMM_LSL(0));
1712 tcg_out_dat_reg(s
, COND_EQ
, ARITH_CMP
, 0,
1713 args
[1], args
[3], SHIFT_IMM_LSL(0));
1714 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[args
[5]],
1715 ARITH_MOV
, args
[0], 0, 1);
1716 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[tcg_invert_cond(args
[5])],
1717 ARITH_MOV
, args
[0], 0, 0);
1720 case INDEX_op_qemu_ld8u
:
1721 tcg_out_qemu_ld(s
, args
, 0);
1723 case INDEX_op_qemu_ld8s
:
1724 tcg_out_qemu_ld(s
, args
, 0 | 4);
1726 case INDEX_op_qemu_ld16u
:
1727 tcg_out_qemu_ld(s
, args
, 1);
1729 case INDEX_op_qemu_ld16s
:
1730 tcg_out_qemu_ld(s
, args
, 1 | 4);
1732 case INDEX_op_qemu_ld32
:
1733 tcg_out_qemu_ld(s
, args
, 2);
1735 case INDEX_op_qemu_ld64
:
1736 tcg_out_qemu_ld(s
, args
, 3);
1739 case INDEX_op_qemu_st8
:
1740 tcg_out_qemu_st(s
, args
, 0);
1742 case INDEX_op_qemu_st16
:
1743 tcg_out_qemu_st(s
, args
, 1);
1745 case INDEX_op_qemu_st32
:
1746 tcg_out_qemu_st(s
, args
, 2);
1748 case INDEX_op_qemu_st64
:
1749 tcg_out_qemu_st(s
, args
, 3);
1752 case INDEX_op_bswap16_i32
:
1753 tcg_out_bswap16(s
, COND_AL
, args
[0], args
[1]);
1755 case INDEX_op_bswap32_i32
:
1756 tcg_out_bswap32(s
, COND_AL
, args
[0], args
[1]);
1759 case INDEX_op_ext8s_i32
:
1760 tcg_out_ext8s(s
, COND_AL
, args
[0], args
[1]);
1762 case INDEX_op_ext16s_i32
:
1763 tcg_out_ext16s(s
, COND_AL
, args
[0], args
[1]);
1765 case INDEX_op_ext16u_i32
:
1766 tcg_out_ext16u(s
, COND_AL
, args
[0], args
[1]);
1774 static const TCGTargetOpDef arm_op_defs
[] = {
1775 { INDEX_op_exit_tb
, { } },
1776 { INDEX_op_goto_tb
, { } },
1777 { INDEX_op_call
, { "ri" } },
1778 { INDEX_op_jmp
, { "ri" } },
1779 { INDEX_op_br
, { } },
1781 { INDEX_op_mov_i32
, { "r", "r" } },
1782 { INDEX_op_movi_i32
, { "r" } },
1784 { INDEX_op_ld8u_i32
, { "r", "r" } },
1785 { INDEX_op_ld8s_i32
, { "r", "r" } },
1786 { INDEX_op_ld16u_i32
, { "r", "r" } },
1787 { INDEX_op_ld16s_i32
, { "r", "r" } },
1788 { INDEX_op_ld_i32
, { "r", "r" } },
1789 { INDEX_op_st8_i32
, { "r", "r" } },
1790 { INDEX_op_st16_i32
, { "r", "r" } },
1791 { INDEX_op_st_i32
, { "r", "r" } },
1793 /* TODO: "r", "r", "ri" */
1794 { INDEX_op_add_i32
, { "r", "r", "rI" } },
1795 { INDEX_op_sub_i32
, { "r", "r", "rI" } },
1796 { INDEX_op_mul_i32
, { "r", "r", "r" } },
1797 { INDEX_op_mulu2_i32
, { "r", "r", "r", "r" } },
1798 { INDEX_op_and_i32
, { "r", "r", "rI" } },
1799 { INDEX_op_andc_i32
, { "r", "r", "rI" } },
1800 { INDEX_op_or_i32
, { "r", "r", "rI" } },
1801 { INDEX_op_xor_i32
, { "r", "r", "rI" } },
1802 { INDEX_op_neg_i32
, { "r", "r" } },
1803 { INDEX_op_not_i32
, { "r", "r" } },
1805 { INDEX_op_shl_i32
, { "r", "r", "ri" } },
1806 { INDEX_op_shr_i32
, { "r", "r", "ri" } },
1807 { INDEX_op_sar_i32
, { "r", "r", "ri" } },
1808 { INDEX_op_rotl_i32
, { "r", "r", "ri" } },
1809 { INDEX_op_rotr_i32
, { "r", "r", "ri" } },
1811 { INDEX_op_brcond_i32
, { "r", "rI" } },
1812 { INDEX_op_setcond_i32
, { "r", "r", "rI" } },
1814 /* TODO: "r", "r", "r", "r", "ri", "ri" */
1815 { INDEX_op_add2_i32
, { "r", "r", "r", "r", "r", "r" } },
1816 { INDEX_op_sub2_i32
, { "r", "r", "r", "r", "r", "r" } },
1817 { INDEX_op_brcond2_i32
, { "r", "r", "r", "r" } },
1818 { INDEX_op_setcond2_i32
, { "r", "r", "r", "r", "r" } },
1820 #if TARGET_LONG_BITS == 32
1821 { INDEX_op_qemu_ld8u
, { "r", "l" } },
1822 { INDEX_op_qemu_ld8s
, { "r", "l" } },
1823 { INDEX_op_qemu_ld16u
, { "r", "l" } },
1824 { INDEX_op_qemu_ld16s
, { "r", "l" } },
1825 { INDEX_op_qemu_ld32
, { "r", "l" } },
1826 { INDEX_op_qemu_ld64
, { "L", "L", "l" } },
1828 { INDEX_op_qemu_st8
, { "s", "s" } },
1829 { INDEX_op_qemu_st16
, { "s", "s" } },
1830 { INDEX_op_qemu_st32
, { "s", "s" } },
1831 { INDEX_op_qemu_st64
, { "S", "S", "s" } },
1833 { INDEX_op_qemu_ld8u
, { "r", "l", "l" } },
1834 { INDEX_op_qemu_ld8s
, { "r", "l", "l" } },
1835 { INDEX_op_qemu_ld16u
, { "r", "l", "l" } },
1836 { INDEX_op_qemu_ld16s
, { "r", "l", "l" } },
1837 { INDEX_op_qemu_ld32
, { "r", "l", "l" } },
1838 { INDEX_op_qemu_ld64
, { "L", "L", "l", "l" } },
1840 { INDEX_op_qemu_st8
, { "s", "s", "s" } },
1841 { INDEX_op_qemu_st16
, { "s", "s", "s" } },
1842 { INDEX_op_qemu_st32
, { "s", "s", "s" } },
1843 { INDEX_op_qemu_st64
, { "S", "S", "s", "s" } },
1846 { INDEX_op_bswap16_i32
, { "r", "r" } },
1847 { INDEX_op_bswap32_i32
, { "r", "r" } },
1849 { INDEX_op_ext8s_i32
, { "r", "r" } },
1850 { INDEX_op_ext16s_i32
, { "r", "r" } },
1851 { INDEX_op_ext16u_i32
, { "r", "r" } },
1856 static void tcg_target_init(TCGContext
*s
)
1858 #if !defined(CONFIG_USER_ONLY)
1860 if ((1 << CPU_TLB_ENTRY_BITS
) != sizeof(CPUTLBEntry
))
1864 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I32
], 0, 0xffff);
1865 tcg_regset_set32(tcg_target_call_clobber_regs
, 0,
1870 (1 << TCG_REG_R12
) |
1871 (1 << TCG_REG_R14
));
1873 tcg_regset_clear(s
->reserved_regs
);
1874 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_CALL_STACK
);
1875 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R8
);
1876 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_PC
);
1878 tcg_add_target_add_op_defs(arm_op_defs
);
1879 tcg_set_frame(s
, TCG_AREG0
, offsetof(CPUArchState
, temp_buf
),
1880 CPU_TEMP_BUF_NLONGS
* sizeof(long));
1883 static inline void tcg_out_ld(TCGContext
*s
, TCGType type
, TCGReg arg
,
1884 TCGReg arg1
, tcg_target_long arg2
)
1886 tcg_out_ld32u(s
, COND_AL
, arg
, arg1
, arg2
);
1889 static inline void tcg_out_st(TCGContext
*s
, TCGType type
, TCGReg arg
,
1890 TCGReg arg1
, tcg_target_long arg2
)
1892 tcg_out_st32(s
, COND_AL
, arg
, arg1
, arg2
);
1895 static inline void tcg_out_mov(TCGContext
*s
, TCGType type
,
1896 TCGReg ret
, TCGReg arg
)
1898 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, ret
, 0, arg
, SHIFT_IMM_LSL(0));
1901 static inline void tcg_out_movi(TCGContext
*s
, TCGType type
,
1902 TCGReg ret
, tcg_target_long arg
)
1904 tcg_out_movi32(s
, COND_AL
, ret
, arg
);
1907 static void tcg_target_qemu_prologue(TCGContext
*s
)
1909 /* Calling convention requires us to save r4-r11 and lr;
1910 * save also r12 to maintain stack 8-alignment.
1913 /* stmdb sp!, { r4 - r12, lr } */
1914 tcg_out32(s
, (COND_AL
<< 28) | 0x092d5ff0);
1916 tcg_out_mov(s
, TCG_TYPE_PTR
, TCG_AREG0
, tcg_target_call_iarg_regs
[0]);
1918 tcg_out_bx(s
, COND_AL
, tcg_target_call_iarg_regs
[1]);
1919 tb_ret_addr
= s
->code_ptr
;
1921 /* ldmia sp!, { r4 - r12, pc } */
1922 tcg_out32(s
, (COND_AL
<< 28) | 0x08bd9ff0);