2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Andrzej Zaborowski
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 static const char * const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
46 static const int tcg_target_reg_alloc_order
[] = {
64 static const int tcg_target_call_iarg_regs
[4] = {
65 TCG_REG_R0
, TCG_REG_R1
, TCG_REG_R2
, TCG_REG_R3
67 static const int tcg_target_call_oarg_regs
[2] = {
68 TCG_REG_R0
, TCG_REG_R1
71 static void patch_reloc(uint8_t *code_ptr
, int type
,
72 tcg_target_long value
, tcg_target_long addend
)
76 *(uint32_t *) code_ptr
= value
;
85 *(uint32_t *) code_ptr
= ((*(uint32_t *) code_ptr
) & 0xff000000) |
86 (((value
- ((tcg_target_long
) code_ptr
+ 8)) >> 2) & 0xffffff);
91 /* maximum number of register used for input function arguments */
92 static inline int tcg_target_get_call_iarg_regs_count(int flags
)
97 /* parse target specific constraints */
98 static int target_parse_constraint(TCGArgConstraint
*ct
, const char **pct_str
)
105 ct
->ct
|= TCG_CT_CONST_ARM
;
109 #ifndef CONFIG_SOFTMMU
115 ct
->ct
|= TCG_CT_REG
;
116 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
119 #ifdef CONFIG_SOFTMMU
120 /* qemu_ld/st inputs (unless 'X', 'd' or 'D') */
122 ct
->ct
|= TCG_CT_REG
;
123 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
124 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R0
);
125 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
128 /* qemu_ld64 data_reg */
130 ct
->ct
|= TCG_CT_REG
;
131 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
132 /* r1 is still needed to load data_reg2, so don't use it. */
133 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
136 /* qemu_ld/st64 data_reg2 */
138 ct
->ct
|= TCG_CT_REG
;
139 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
140 /* r0, r1 and optionally r2 will be overwritten by the address
141 * and the low word of data, so don't use these. */
142 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R0
);
143 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
144 # if TARGET_LONG_BITS == 64
145 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R2
);
149 # if TARGET_LONG_BITS == 64
150 /* qemu_ld/st addr_reg2 */
152 ct
->ct
|= TCG_CT_REG
;
153 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
154 /* r0 will be overwritten by the low word of base, so don't use it. */
155 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R0
);
156 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
170 static inline uint32_t rotl(uint32_t val
, int n
)
172 return (val
<< n
) | (val
>> (32 - n
));
175 /* ARM immediates for ALU instructions are made of an unsigned 8-bit
176 right-rotated by an even amount between 0 and 30. */
177 static inline int encode_imm(uint32_t imm
)
181 /* simple case, only lower bits */
182 if ((imm
& ~0xff) == 0)
184 /* then try a simple even shift */
185 shift
= ctz32(imm
) & ~1;
186 if (((imm
>> shift
) & ~0xff) == 0)
188 /* now try harder with rotations */
189 if ((rotl(imm
, 2) & ~0xff) == 0)
191 if ((rotl(imm
, 4) & ~0xff) == 0)
193 if ((rotl(imm
, 6) & ~0xff) == 0)
195 /* imm can't be encoded */
199 static inline int check_fit_imm(uint32_t imm
)
201 return encode_imm(imm
) >= 0;
204 /* Test if a constant matches the constraint.
205 * TODO: define constraints for:
207 * ldr/str offset: between -0xfff and 0xfff
208 * ldrh/strh offset: between -0xff and 0xff
209 * mov operand2: values represented with x << (2 * y), x < 0x100
210 * add, sub, eor...: ditto
212 static inline int tcg_target_const_match(tcg_target_long val
,
213 const TCGArgConstraint
*arg_ct
)
217 if (ct
& TCG_CT_CONST
)
219 else if ((ct
& TCG_CT_CONST_ARM
) && check_fit_imm(val
))
225 enum arm_data_opc_e
{
243 #define TO_CPSR(opc) \
244 ((opc == ARITH_CMP || opc == ARITH_CMN || opc == ARITH_TST) << 20)
246 #define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
247 #define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20)
248 #define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40)
249 #define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60)
250 #define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10)
251 #define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30)
252 #define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50)
253 #define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70)
255 enum arm_cond_code_e
{
258 COND_CS
= 0x2, /* Unsigned greater or equal */
259 COND_CC
= 0x3, /* Unsigned less than */
260 COND_MI
= 0x4, /* Negative */
261 COND_PL
= 0x5, /* Zero or greater */
262 COND_VS
= 0x6, /* Overflow */
263 COND_VC
= 0x7, /* No overflow */
264 COND_HI
= 0x8, /* Unsigned greater than */
265 COND_LS
= 0x9, /* Unsigned less or equal */
273 static const uint8_t tcg_cond_to_arm_cond
[10] = {
274 [TCG_COND_EQ
] = COND_EQ
,
275 [TCG_COND_NE
] = COND_NE
,
276 [TCG_COND_LT
] = COND_LT
,
277 [TCG_COND_GE
] = COND_GE
,
278 [TCG_COND_LE
] = COND_LE
,
279 [TCG_COND_GT
] = COND_GT
,
281 [TCG_COND_LTU
] = COND_CC
,
282 [TCG_COND_GEU
] = COND_CS
,
283 [TCG_COND_LEU
] = COND_LS
,
284 [TCG_COND_GTU
] = COND_HI
,
287 static inline void tcg_out_bx(TCGContext
*s
, int cond
, int rn
)
289 tcg_out32(s
, (cond
<< 28) | 0x012fff10 | rn
);
292 static inline void tcg_out_b(TCGContext
*s
, int cond
, int32_t offset
)
294 tcg_out32(s
, (cond
<< 28) | 0x0a000000 |
295 (((offset
- 8) >> 2) & 0x00ffffff));
298 static inline void tcg_out_b_noaddr(TCGContext
*s
, int cond
)
300 #ifdef HOST_WORDS_BIGENDIAN
301 tcg_out8(s
, (cond
<< 4) | 0x0a);
305 tcg_out8(s
, (cond
<< 4) | 0x0a);
309 static inline void tcg_out_bl(TCGContext
*s
, int cond
, int32_t offset
)
311 tcg_out32(s
, (cond
<< 28) | 0x0b000000 |
312 (((offset
- 8) >> 2) & 0x00ffffff));
315 static inline void tcg_out_dat_reg(TCGContext
*s
,
316 int cond
, int opc
, int rd
, int rn
, int rm
, int shift
)
318 tcg_out32(s
, (cond
<< 28) | (0 << 25) | (opc
<< 21) | TO_CPSR(opc
) |
319 (rn
<< 16) | (rd
<< 12) | shift
| rm
);
322 static inline void tcg_out_dat_reg2(TCGContext
*s
,
323 int cond
, int opc0
, int opc1
, int rd0
, int rd1
,
324 int rn0
, int rn1
, int rm0
, int rm1
, int shift
)
326 if (rd0
== rn1
|| rd0
== rm1
) {
327 tcg_out32(s
, (cond
<< 28) | (0 << 25) | (opc0
<< 21) | (1 << 20) |
328 (rn0
<< 16) | (8 << 12) | shift
| rm0
);
329 tcg_out32(s
, (cond
<< 28) | (0 << 25) | (opc1
<< 21) |
330 (rn1
<< 16) | (rd1
<< 12) | shift
| rm1
);
331 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
332 rd0
, 0, TCG_REG_R8
, SHIFT_IMM_LSL(0));
334 tcg_out32(s
, (cond
<< 28) | (0 << 25) | (opc0
<< 21) | (1 << 20) |
335 (rn0
<< 16) | (rd0
<< 12) | shift
| rm0
);
336 tcg_out32(s
, (cond
<< 28) | (0 << 25) | (opc1
<< 21) |
337 (rn1
<< 16) | (rd1
<< 12) | shift
| rm1
);
341 static inline void tcg_out_dat_imm(TCGContext
*s
,
342 int cond
, int opc
, int rd
, int rn
, int im
)
344 tcg_out32(s
, (cond
<< 28) | (1 << 25) | (opc
<< 21) | TO_CPSR(opc
) |
345 (rn
<< 16) | (rd
<< 12) | im
);
348 static inline void tcg_out_movi32(TCGContext
*s
,
349 int cond
, int rd
, int32_t arg
)
351 int offset
= (uint32_t) arg
- ((uint32_t) s
->code_ptr
+ 8);
353 /* TODO: This is very suboptimal, we can easily have a constant
354 * pool somewhere after all the instructions. */
356 if (arg
< 0 && arg
> -0x100)
357 return tcg_out_dat_imm(s
, cond
, ARITH_MVN
, rd
, 0, (~arg
) & 0xff);
359 if (offset
< 0x100 && offset
> -0x100)
361 tcg_out_dat_imm(s
, cond
, ARITH_ADD
, rd
, 15, offset
) :
362 tcg_out_dat_imm(s
, cond
, ARITH_SUB
, rd
, 15, -offset
);
364 #ifdef __ARM_ARCH_7A__
367 tcg_out32(s
, (cond
<< 28) | 0x03000000 | (rd
<< 12)
368 | ((arg
<< 4) & 0x000f0000) | (arg
& 0xfff));
369 if (arg
& 0xffff0000)
371 tcg_out32(s
, (cond
<< 28) | 0x03400000 | (rd
<< 12)
372 | ((arg
>> 12) & 0x000f0000) | ((arg
>> 16) & 0xfff));
374 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, rd
, 0, arg
& 0xff);
375 if (arg
& 0x0000ff00)
376 tcg_out_dat_imm(s
, cond
, ARITH_ORR
, rd
, rd
,
377 ((arg
>> 8) & 0xff) | 0xc00);
378 if (arg
& 0x00ff0000)
379 tcg_out_dat_imm(s
, cond
, ARITH_ORR
, rd
, rd
,
380 ((arg
>> 16) & 0xff) | 0x800);
381 if (arg
& 0xff000000)
382 tcg_out_dat_imm(s
, cond
, ARITH_ORR
, rd
, rd
,
383 ((arg
>> 24) & 0xff) | 0x400);
387 static inline void tcg_out_mul32(TCGContext
*s
,
388 int cond
, int rd
, int rs
, int rm
)
391 tcg_out32(s
, (cond
<< 28) | (rd
<< 16) | (0 << 12) |
392 (rs
<< 8) | 0x90 | rm
);
394 tcg_out32(s
, (cond
<< 28) | (rd
<< 16) | (0 << 12) |
395 (rm
<< 8) | 0x90 | rs
);
397 tcg_out32(s
, (cond
<< 28) | ( 8 << 16) | (0 << 12) |
398 (rs
<< 8) | 0x90 | rm
);
399 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
400 rd
, 0, 8, SHIFT_IMM_LSL(0));
404 static inline void tcg_out_umull32(TCGContext
*s
,
405 int cond
, int rd0
, int rd1
, int rs
, int rm
)
407 if (rd0
!= rm
&& rd1
!= rm
)
408 tcg_out32(s
, (cond
<< 28) | 0x800090 |
409 (rd1
<< 16) | (rd0
<< 12) | (rs
<< 8) | rm
);
410 else if (rd0
!= rs
&& rd1
!= rs
)
411 tcg_out32(s
, (cond
<< 28) | 0x800090 |
412 (rd1
<< 16) | (rd0
<< 12) | (rm
<< 8) | rs
);
414 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
415 TCG_REG_R8
, 0, rm
, SHIFT_IMM_LSL(0));
416 tcg_out32(s
, (cond
<< 28) | 0x800098 |
417 (rd1
<< 16) | (rd0
<< 12) | (rs
<< 8));
421 static inline void tcg_out_smull32(TCGContext
*s
,
422 int cond
, int rd0
, int rd1
, int rs
, int rm
)
424 if (rd0
!= rm
&& rd1
!= rm
)
425 tcg_out32(s
, (cond
<< 28) | 0xc00090 |
426 (rd1
<< 16) | (rd0
<< 12) | (rs
<< 8) | rm
);
427 else if (rd0
!= rs
&& rd1
!= rs
)
428 tcg_out32(s
, (cond
<< 28) | 0xc00090 |
429 (rd1
<< 16) | (rd0
<< 12) | (rm
<< 8) | rs
);
431 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
432 TCG_REG_R8
, 0, rm
, SHIFT_IMM_LSL(0));
433 tcg_out32(s
, (cond
<< 28) | 0xc00098 |
434 (rd1
<< 16) | (rd0
<< 12) | (rs
<< 8));
438 static inline void tcg_out_ld32_12(TCGContext
*s
, int cond
,
439 int rd
, int rn
, tcg_target_long im
)
442 tcg_out32(s
, (cond
<< 28) | 0x05900000 |
443 (rn
<< 16) | (rd
<< 12) | (im
& 0xfff));
445 tcg_out32(s
, (cond
<< 28) | 0x05100000 |
446 (rn
<< 16) | (rd
<< 12) | ((-im
) & 0xfff));
449 static inline void tcg_out_st32_12(TCGContext
*s
, int cond
,
450 int rd
, int rn
, tcg_target_long im
)
453 tcg_out32(s
, (cond
<< 28) | 0x05800000 |
454 (rn
<< 16) | (rd
<< 12) | (im
& 0xfff));
456 tcg_out32(s
, (cond
<< 28) | 0x05000000 |
457 (rn
<< 16) | (rd
<< 12) | ((-im
) & 0xfff));
460 static inline void tcg_out_ld32_r(TCGContext
*s
, int cond
,
461 int rd
, int rn
, int rm
)
463 tcg_out32(s
, (cond
<< 28) | 0x07900000 |
464 (rn
<< 16) | (rd
<< 12) | rm
);
467 static inline void tcg_out_st32_r(TCGContext
*s
, int cond
,
468 int rd
, int rn
, int rm
)
470 tcg_out32(s
, (cond
<< 28) | 0x07800000 |
471 (rn
<< 16) | (rd
<< 12) | rm
);
474 /* Register pre-increment with base writeback. */
475 static inline void tcg_out_ld32_rwb(TCGContext
*s
, int cond
,
476 int rd
, int rn
, int rm
)
478 tcg_out32(s
, (cond
<< 28) | 0x07b00000 |
479 (rn
<< 16) | (rd
<< 12) | rm
);
482 static inline void tcg_out_st32_rwb(TCGContext
*s
, int cond
,
483 int rd
, int rn
, int rm
)
485 tcg_out32(s
, (cond
<< 28) | 0x07a00000 |
486 (rn
<< 16) | (rd
<< 12) | rm
);
489 static inline void tcg_out_ld16u_8(TCGContext
*s
, int cond
,
490 int rd
, int rn
, tcg_target_long im
)
493 tcg_out32(s
, (cond
<< 28) | 0x01d000b0 |
494 (rn
<< 16) | (rd
<< 12) |
495 ((im
& 0xf0) << 4) | (im
& 0xf));
497 tcg_out32(s
, (cond
<< 28) | 0x015000b0 |
498 (rn
<< 16) | (rd
<< 12) |
499 (((-im
) & 0xf0) << 4) | ((-im
) & 0xf));
502 static inline void tcg_out_st16u_8(TCGContext
*s
, int cond
,
503 int rd
, int rn
, tcg_target_long im
)
506 tcg_out32(s
, (cond
<< 28) | 0x01c000b0 |
507 (rn
<< 16) | (rd
<< 12) |
508 ((im
& 0xf0) << 4) | (im
& 0xf));
510 tcg_out32(s
, (cond
<< 28) | 0x014000b0 |
511 (rn
<< 16) | (rd
<< 12) |
512 (((-im
) & 0xf0) << 4) | ((-im
) & 0xf));
515 static inline void tcg_out_ld16u_r(TCGContext
*s
, int cond
,
516 int rd
, int rn
, int rm
)
518 tcg_out32(s
, (cond
<< 28) | 0x019000b0 |
519 (rn
<< 16) | (rd
<< 12) | rm
);
522 static inline void tcg_out_st16u_r(TCGContext
*s
, int cond
,
523 int rd
, int rn
, int rm
)
525 tcg_out32(s
, (cond
<< 28) | 0x018000b0 |
526 (rn
<< 16) | (rd
<< 12) | rm
);
529 static inline void tcg_out_ld16s_8(TCGContext
*s
, int cond
,
530 int rd
, int rn
, tcg_target_long im
)
533 tcg_out32(s
, (cond
<< 28) | 0x01d000f0 |
534 (rn
<< 16) | (rd
<< 12) |
535 ((im
& 0xf0) << 4) | (im
& 0xf));
537 tcg_out32(s
, (cond
<< 28) | 0x015000f0 |
538 (rn
<< 16) | (rd
<< 12) |
539 (((-im
) & 0xf0) << 4) | ((-im
) & 0xf));
542 static inline void tcg_out_st16s_8(TCGContext
*s
, int cond
,
543 int rd
, int rn
, tcg_target_long im
)
546 tcg_out32(s
, (cond
<< 28) | 0x01c000f0 |
547 (rn
<< 16) | (rd
<< 12) |
548 ((im
& 0xf0) << 4) | (im
& 0xf));
550 tcg_out32(s
, (cond
<< 28) | 0x014000f0 |
551 (rn
<< 16) | (rd
<< 12) |
552 (((-im
) & 0xf0) << 4) | ((-im
) & 0xf));
555 static inline void tcg_out_ld16s_r(TCGContext
*s
, int cond
,
556 int rd
, int rn
, int rm
)
558 tcg_out32(s
, (cond
<< 28) | 0x019000f0 |
559 (rn
<< 16) | (rd
<< 12) | rm
);
562 static inline void tcg_out_st16s_r(TCGContext
*s
, int cond
,
563 int rd
, int rn
, int rm
)
565 tcg_out32(s
, (cond
<< 28) | 0x018000f0 |
566 (rn
<< 16) | (rd
<< 12) | rm
);
569 static inline void tcg_out_ld8_12(TCGContext
*s
, int cond
,
570 int rd
, int rn
, tcg_target_long im
)
573 tcg_out32(s
, (cond
<< 28) | 0x05d00000 |
574 (rn
<< 16) | (rd
<< 12) | (im
& 0xfff));
576 tcg_out32(s
, (cond
<< 28) | 0x05500000 |
577 (rn
<< 16) | (rd
<< 12) | ((-im
) & 0xfff));
580 static inline void tcg_out_st8_12(TCGContext
*s
, int cond
,
581 int rd
, int rn
, tcg_target_long im
)
584 tcg_out32(s
, (cond
<< 28) | 0x05c00000 |
585 (rn
<< 16) | (rd
<< 12) | (im
& 0xfff));
587 tcg_out32(s
, (cond
<< 28) | 0x05400000 |
588 (rn
<< 16) | (rd
<< 12) | ((-im
) & 0xfff));
591 static inline void tcg_out_ld8_r(TCGContext
*s
, int cond
,
592 int rd
, int rn
, int rm
)
594 tcg_out32(s
, (cond
<< 28) | 0x07d00000 |
595 (rn
<< 16) | (rd
<< 12) | rm
);
598 static inline void tcg_out_st8_r(TCGContext
*s
, int cond
,
599 int rd
, int rn
, int rm
)
601 tcg_out32(s
, (cond
<< 28) | 0x07c00000 |
602 (rn
<< 16) | (rd
<< 12) | rm
);
605 static inline void tcg_out_ld8s_8(TCGContext
*s
, int cond
,
606 int rd
, int rn
, tcg_target_long im
)
609 tcg_out32(s
, (cond
<< 28) | 0x01d000d0 |
610 (rn
<< 16) | (rd
<< 12) |
611 ((im
& 0xf0) << 4) | (im
& 0xf));
613 tcg_out32(s
, (cond
<< 28) | 0x015000d0 |
614 (rn
<< 16) | (rd
<< 12) |
615 (((-im
) & 0xf0) << 4) | ((-im
) & 0xf));
618 static inline void tcg_out_st8s_8(TCGContext
*s
, int cond
,
619 int rd
, int rn
, tcg_target_long im
)
622 tcg_out32(s
, (cond
<< 28) | 0x01c000d0 |
623 (rn
<< 16) | (rd
<< 12) |
624 ((im
& 0xf0) << 4) | (im
& 0xf));
626 tcg_out32(s
, (cond
<< 28) | 0x014000d0 |
627 (rn
<< 16) | (rd
<< 12) |
628 (((-im
) & 0xf0) << 4) | ((-im
) & 0xf));
631 static inline void tcg_out_ld8s_r(TCGContext
*s
, int cond
,
632 int rd
, int rn
, int rm
)
634 tcg_out32(s
, (cond
<< 28) | 0x019000d0 |
635 (rn
<< 16) | (rd
<< 12) | rm
);
638 static inline void tcg_out_st8s_r(TCGContext
*s
, int cond
,
639 int rd
, int rn
, int rm
)
641 tcg_out32(s
, (cond
<< 28) | 0x018000d0 |
642 (rn
<< 16) | (rd
<< 12) | rm
);
645 static inline void tcg_out_ld32u(TCGContext
*s
, int cond
,
646 int rd
, int rn
, int32_t offset
)
648 if (offset
> 0xfff || offset
< -0xfff) {
649 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
650 tcg_out_ld32_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
652 tcg_out_ld32_12(s
, cond
, rd
, rn
, offset
);
655 static inline void tcg_out_st32(TCGContext
*s
, int cond
,
656 int rd
, int rn
, int32_t offset
)
658 if (offset
> 0xfff || offset
< -0xfff) {
659 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
660 tcg_out_st32_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
662 tcg_out_st32_12(s
, cond
, rd
, rn
, offset
);
665 static inline void tcg_out_ld16u(TCGContext
*s
, int cond
,
666 int rd
, int rn
, int32_t offset
)
668 if (offset
> 0xff || offset
< -0xff) {
669 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
670 tcg_out_ld16u_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
672 tcg_out_ld16u_8(s
, cond
, rd
, rn
, offset
);
675 static inline void tcg_out_ld16s(TCGContext
*s
, int cond
,
676 int rd
, int rn
, int32_t offset
)
678 if (offset
> 0xff || offset
< -0xff) {
679 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
680 tcg_out_ld16s_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
682 tcg_out_ld16s_8(s
, cond
, rd
, rn
, offset
);
685 static inline void tcg_out_st16u(TCGContext
*s
, int cond
,
686 int rd
, int rn
, int32_t offset
)
688 if (offset
> 0xff || offset
< -0xff) {
689 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
690 tcg_out_st16u_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
692 tcg_out_st16u_8(s
, cond
, rd
, rn
, offset
);
695 static inline void tcg_out_ld8u(TCGContext
*s
, int cond
,
696 int rd
, int rn
, int32_t offset
)
698 if (offset
> 0xfff || offset
< -0xfff) {
699 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
700 tcg_out_ld8_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
702 tcg_out_ld8_12(s
, cond
, rd
, rn
, offset
);
705 static inline void tcg_out_ld8s(TCGContext
*s
, int cond
,
706 int rd
, int rn
, int32_t offset
)
708 if (offset
> 0xff || offset
< -0xff) {
709 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
710 tcg_out_ld8s_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
712 tcg_out_ld8s_8(s
, cond
, rd
, rn
, offset
);
715 static inline void tcg_out_st8u(TCGContext
*s
, int cond
,
716 int rd
, int rn
, int32_t offset
)
718 if (offset
> 0xfff || offset
< -0xfff) {
719 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
720 tcg_out_st8_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
722 tcg_out_st8_12(s
, cond
, rd
, rn
, offset
);
725 static inline void tcg_out_goto(TCGContext
*s
, int cond
, uint32_t addr
)
729 val
= addr
- (tcg_target_long
) s
->code_ptr
;
730 if (val
- 8 < 0x01fffffd && val
- 8 > -0x01fffffd)
731 tcg_out_b(s
, cond
, val
);
736 if (cond
== COND_AL
) {
737 tcg_out_ld32_12(s
, COND_AL
, 15, 15, -4);
738 tcg_out32(s
, addr
); /* XXX: This is l->u.value, can we use it? */
740 tcg_out_movi32(s
, cond
, TCG_REG_R8
, val
- 8);
741 tcg_out_dat_reg(s
, cond
, ARITH_ADD
,
742 15, 15, TCG_REG_R8
, SHIFT_IMM_LSL(0));
748 static inline void tcg_out_call(TCGContext
*s
, int cond
, uint32_t addr
)
752 val
= addr
- (tcg_target_long
) s
->code_ptr
;
753 if (val
< 0x01fffffd && val
> -0x01fffffd)
754 tcg_out_bl(s
, cond
, val
);
759 if (cond
== COND_AL
) {
760 tcg_out_dat_imm(s
, cond
, ARITH_ADD
, 14, 15, 4);
761 tcg_out_ld32_12(s
, COND_AL
, 15, 15, -4);
762 tcg_out32(s
, addr
); /* XXX: This is l->u.value, can we use it? */
764 tcg_out_movi32(s
, cond
, TCG_REG_R9
, addr
);
765 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, 14, 0, 15);
766 tcg_out_bx(s
, cond
, TCG_REG_R9
);
772 static inline void tcg_out_callr(TCGContext
*s
, int cond
, int arg
)
774 /* TODO: on ARMv5 and ARMv6 replace with tcg_out_blx(s, cond, arg); */
775 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, 14, 0, 15, SHIFT_IMM_LSL(0));
776 tcg_out_bx(s
, cond
, arg
);
779 static inline void tcg_out_goto_label(TCGContext
*s
, int cond
, int label_index
)
781 TCGLabel
*l
= &s
->labels
[label_index
];
784 tcg_out_goto(s
, cond
, l
->u
.value
);
785 else if (cond
== COND_AL
) {
786 tcg_out_ld32_12(s
, COND_AL
, 15, 15, -4);
787 tcg_out_reloc(s
, s
->code_ptr
, R_ARM_ABS32
, label_index
, 31337);
790 /* Probably this should be preferred even for COND_AL... */
791 tcg_out_reloc(s
, s
->code_ptr
, R_ARM_PC24
, label_index
, 31337);
792 tcg_out_b_noaddr(s
, cond
);
796 #ifdef CONFIG_SOFTMMU
798 #include "../../softmmu_defs.h"
800 static void *qemu_ld_helpers
[4] = {
807 static void *qemu_st_helpers
[4] = {
815 #define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
817 static inline void tcg_out_qemu_ld(TCGContext
*s
, int cond
,
818 const TCGArg
*args
, int opc
)
820 int addr_reg
, data_reg
, data_reg2
;
821 #ifdef CONFIG_SOFTMMU
822 int mem_index
, s_bits
;
823 # if TARGET_LONG_BITS == 64
833 data_reg2
= 0; /* suppress warning */
835 #ifdef CONFIG_SOFTMMU
836 # if TARGET_LONG_BITS == 64
842 /* Should generate something like the following:
843 * shr r8, addr_reg, #TARGET_PAGE_BITS
844 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
845 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
847 # if CPU_TLB_BITS > 8
850 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
851 8, 0, addr_reg
, SHIFT_IMM_LSR(TARGET_PAGE_BITS
));
852 tcg_out_dat_imm(s
, COND_AL
, ARITH_AND
,
853 0, 8, CPU_TLB_SIZE
- 1);
854 tcg_out_dat_reg(s
, COND_AL
, ARITH_ADD
,
855 0, TCG_AREG0
, 0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS
));
857 * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_read))]
858 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
859 * not exceed otherwise, so use an
860 * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
864 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, 0, 0,
865 (mem_index
<< (TLB_SHIFT
& 1)) |
866 ((16 - (TLB_SHIFT
>> 1)) << 8));
867 tcg_out_ld32_12(s
, COND_AL
, 1, 0,
868 offsetof(CPUState
, tlb_table
[0][0].addr_read
));
869 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
,
870 0, 1, 8, SHIFT_IMM_LSL(TARGET_PAGE_BITS
));
871 /* Check alignment. */
873 tcg_out_dat_imm(s
, COND_EQ
, ARITH_TST
,
874 0, addr_reg
, (1 << s_bits
) - 1);
875 # if TARGET_LONG_BITS == 64
876 /* XXX: possibly we could use a block data load or writeback in
877 * the first access. */
878 tcg_out_ld32_12(s
, COND_EQ
, 1, 0,
879 offsetof(CPUState
, tlb_table
[0][0].addr_read
) + 4);
880 tcg_out_dat_reg(s
, COND_EQ
, ARITH_CMP
,
881 0, 1, addr_reg2
, SHIFT_IMM_LSL(0));
883 tcg_out_ld32_12(s
, COND_EQ
, 1, 0,
884 offsetof(CPUState
, tlb_table
[0][0].addend
));
888 tcg_out_ld8_r(s
, COND_EQ
, data_reg
, addr_reg
, 1);
891 tcg_out_ld8s_r(s
, COND_EQ
, data_reg
, addr_reg
, 1);
894 tcg_out_ld16u_r(s
, COND_EQ
, data_reg
, addr_reg
, 1);
897 tcg_out_ld16s_r(s
, COND_EQ
, data_reg
, addr_reg
, 1);
901 tcg_out_ld32_r(s
, COND_EQ
, data_reg
, addr_reg
, 1);
904 tcg_out_ld32_rwb(s
, COND_EQ
, data_reg
, 1, addr_reg
);
905 tcg_out_ld32_12(s
, COND_EQ
, data_reg2
, 1, 4);
909 label_ptr
= (void *) s
->code_ptr
;
910 tcg_out_b(s
, COND_EQ
, 8);
912 /* TODO: move this code to where the constants pool will be */
914 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
915 0, 0, addr_reg
, SHIFT_IMM_LSL(0));
916 # if TARGET_LONG_BITS == 32
917 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, 1, 0, mem_index
);
920 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
921 1, 0, addr_reg2
, SHIFT_IMM_LSL(0));
922 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, 2, 0, mem_index
);
924 tcg_out_bl(s
, cond
, (tcg_target_long
) qemu_ld_helpers
[s_bits
] -
925 (tcg_target_long
) s
->code_ptr
);
929 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
930 0, 0, 0, SHIFT_IMM_LSL(24));
931 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
932 data_reg
, 0, 0, SHIFT_IMM_ASR(24));
935 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
936 0, 0, 0, SHIFT_IMM_LSL(16));
937 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
938 data_reg
, 0, 0, SHIFT_IMM_ASR(16));
945 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
946 data_reg
, 0, 0, SHIFT_IMM_LSL(0));
950 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
951 data_reg
, 0, 0, SHIFT_IMM_LSL(0));
953 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
954 data_reg2
, 0, 1, SHIFT_IMM_LSL(0));
958 *label_ptr
+= ((void *) s
->code_ptr
- (void *) label_ptr
- 8) >> 2;
959 #else /* !CONFIG_SOFTMMU */
961 uint32_t offset
= GUEST_BASE
;
966 i
= ctz32(offset
) & ~1;
967 rot
= ((32 - i
) << 7) & 0xf00;
969 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, 8, addr_reg
,
970 ((offset
>> i
) & 0xff) | rot
);
972 offset
&= ~(0xff << i
);
977 tcg_out_ld8_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
980 tcg_out_ld8s_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
983 tcg_out_ld16u_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
986 tcg_out_ld16s_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
990 tcg_out_ld32_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
993 /* TODO: use block load -
994 * check that data_reg2 > data_reg or the other way */
995 if (data_reg
== addr_reg
) {
996 tcg_out_ld32_12(s
, COND_AL
, data_reg2
, addr_reg
, 4);
997 tcg_out_ld32_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
999 tcg_out_ld32_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1000 tcg_out_ld32_12(s
, COND_AL
, data_reg2
, addr_reg
, 4);
1007 static inline void tcg_out_qemu_st(TCGContext
*s
, int cond
,
1008 const TCGArg
*args
, int opc
)
1010 int addr_reg
, data_reg
, data_reg2
;
1011 #ifdef CONFIG_SOFTMMU
1012 int mem_index
, s_bits
;
1013 # if TARGET_LONG_BITS == 64
1016 uint32_t *label_ptr
;
1021 data_reg2
= *args
++;
1023 data_reg2
= 0; /* suppress warning */
1025 #ifdef CONFIG_SOFTMMU
1026 # if TARGET_LONG_BITS == 64
1027 addr_reg2
= *args
++;
1032 /* Should generate something like the following:
1033 * shr r8, addr_reg, #TARGET_PAGE_BITS
1034 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
1035 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
1037 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1038 8, 0, addr_reg
, SHIFT_IMM_LSR(TARGET_PAGE_BITS
));
1039 tcg_out_dat_imm(s
, COND_AL
, ARITH_AND
,
1040 0, 8, CPU_TLB_SIZE
- 1);
1041 tcg_out_dat_reg(s
, COND_AL
, ARITH_ADD
,
1042 0, TCG_AREG0
, 0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS
));
1044 * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_write))]
1045 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
1046 * not exceed otherwise, so use an
1047 * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
1051 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, 0, 0,
1052 (mem_index
<< (TLB_SHIFT
& 1)) |
1053 ((16 - (TLB_SHIFT
>> 1)) << 8));
1054 tcg_out_ld32_12(s
, COND_AL
, 1, 0,
1055 offsetof(CPUState
, tlb_table
[0][0].addr_write
));
1056 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
,
1057 0, 1, 8, SHIFT_IMM_LSL(TARGET_PAGE_BITS
));
1058 /* Check alignment. */
1060 tcg_out_dat_imm(s
, COND_EQ
, ARITH_TST
,
1061 0, addr_reg
, (1 << s_bits
) - 1);
1062 # if TARGET_LONG_BITS == 64
1063 /* XXX: possibly we could use a block data load or writeback in
1064 * the first access. */
1065 tcg_out_ld32_12(s
, COND_EQ
, 1, 0,
1066 offsetof(CPUState
, tlb_table
[0][0].addr_write
)
1068 tcg_out_dat_reg(s
, COND_EQ
, ARITH_CMP
,
1069 0, 1, addr_reg2
, SHIFT_IMM_LSL(0));
1071 tcg_out_ld32_12(s
, COND_EQ
, 1, 0,
1072 offsetof(CPUState
, tlb_table
[0][0].addend
));
1076 tcg_out_st8_r(s
, COND_EQ
, data_reg
, addr_reg
, 1);
1079 tcg_out_st8s_r(s
, COND_EQ
, data_reg
, addr_reg
, 1);
1082 tcg_out_st16u_r(s
, COND_EQ
, data_reg
, addr_reg
, 1);
1085 tcg_out_st16s_r(s
, COND_EQ
, data_reg
, addr_reg
, 1);
1089 tcg_out_st32_r(s
, COND_EQ
, data_reg
, addr_reg
, 1);
1092 tcg_out_st32_rwb(s
, COND_EQ
, data_reg
, 1, addr_reg
);
1093 tcg_out_st32_12(s
, COND_EQ
, data_reg2
, 1, 4);
1097 label_ptr
= (void *) s
->code_ptr
;
1098 tcg_out_b(s
, COND_EQ
, 8);
1100 /* TODO: move this code to where the constants pool will be */
1102 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1103 0, 0, addr_reg
, SHIFT_IMM_LSL(0));
1104 # if TARGET_LONG_BITS == 32
1107 tcg_out_dat_imm(s
, cond
, ARITH_AND
, 1, data_reg
, 0xff);
1108 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, 2, 0, mem_index
);
1111 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1112 1, 0, data_reg
, SHIFT_IMM_LSL(16));
1113 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1114 1, 0, 1, SHIFT_IMM_LSR(16));
1115 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, 2, 0, mem_index
);
1119 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1120 1, 0, data_reg
, SHIFT_IMM_LSL(0));
1121 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, 2, 0, mem_index
);
1125 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1126 1, 0, data_reg
, SHIFT_IMM_LSL(0));
1128 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1129 2, 0, data_reg2
, SHIFT_IMM_LSL(0));
1130 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, 3, 0, mem_index
);
1135 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1136 1, 0, addr_reg2
, SHIFT_IMM_LSL(0));
1139 tcg_out_dat_imm(s
, cond
, ARITH_AND
, 2, data_reg
, 0xff);
1140 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, 3, 0, mem_index
);
1143 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1144 2, 0, data_reg
, SHIFT_IMM_LSL(16));
1145 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1146 2, 0, 2, SHIFT_IMM_LSR(16));
1147 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, 3, 0, mem_index
);
1151 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1152 2, 0, data_reg
, SHIFT_IMM_LSL(0));
1153 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, 3, 0, mem_index
);
1156 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, 8, 0, mem_index
);
1157 tcg_out32(s
, (cond
<< 28) | 0x052d8010); /* str r8, [sp, #-0x10]! */
1159 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1160 2, 0, data_reg
, SHIFT_IMM_LSL(0));
1162 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1163 3, 0, data_reg2
, SHIFT_IMM_LSL(0));
1168 tcg_out_bl(s
, cond
, (tcg_target_long
) qemu_st_helpers
[s_bits
] -
1169 (tcg_target_long
) s
->code_ptr
);
1170 # if TARGET_LONG_BITS == 64
1172 tcg_out_dat_imm(s
, cond
, ARITH_ADD
, 13, 13, 0x10);
1175 *label_ptr
+= ((void *) s
->code_ptr
- (void *) label_ptr
- 8) >> 2;
1176 #else /* !CONFIG_SOFTMMU */
1178 uint32_t offset
= GUEST_BASE
;
1183 i
= ctz32(offset
) & ~1;
1184 rot
= ((32 - i
) << 7) & 0xf00;
1186 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, 8, addr_reg
,
1187 ((offset
>> i
) & 0xff) | rot
);
1189 offset
&= ~(0xff << i
);
1194 tcg_out_st8_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1197 tcg_out_st8s_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
1200 tcg_out_st16u_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
1203 tcg_out_st16s_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
1207 tcg_out_st32_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1210 /* TODO: use block store -
1211 * check that data_reg2 > data_reg or the other way */
1212 tcg_out_st32_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1213 tcg_out_st32_12(s
, COND_AL
, data_reg2
, addr_reg
, 4);
1219 static uint8_t *tb_ret_addr
;
1221 static inline void tcg_out_op(TCGContext
*s
, TCGOpcode opc
,
1222 const TCGArg
*args
, const int *const_args
)
1227 case INDEX_op_exit_tb
:
1229 uint8_t *ld_ptr
= s
->code_ptr
;
1231 tcg_out_ld32_12(s
, COND_AL
, 0, 15, 0);
1233 tcg_out_dat_imm(s
, COND_AL
, ARITH_MOV
, 0, 0, args
[0]);
1234 tcg_out_goto(s
, COND_AL
, (tcg_target_ulong
) tb_ret_addr
);
1236 *ld_ptr
= (uint8_t) (s
->code_ptr
- ld_ptr
) - 8;
1237 tcg_out32(s
, args
[0]);
1241 case INDEX_op_goto_tb
:
1242 if (s
->tb_jmp_offset
) {
1243 /* Direct jump method */
1244 #if defined(USE_DIRECT_JUMP)
1245 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1246 tcg_out_b(s
, COND_AL
, 8);
1248 tcg_out_ld32_12(s
, COND_AL
, 15, 15, -4);
1249 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1253 /* Indirect jump method */
1255 c
= (int) (s
->tb_next
+ args
[0]) - ((int) s
->code_ptr
+ 8);
1256 if (c
> 0xfff || c
< -0xfff) {
1257 tcg_out_movi32(s
, COND_AL
, TCG_REG_R0
,
1258 (tcg_target_long
) (s
->tb_next
+ args
[0]));
1259 tcg_out_ld32_12(s
, COND_AL
, 15, TCG_REG_R0
, 0);
1261 tcg_out_ld32_12(s
, COND_AL
, 15, 15, c
);
1263 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_R0
, 15, 0);
1264 tcg_out_ld32_12(s
, COND_AL
, 15, TCG_REG_R0
, 0);
1265 tcg_out32(s
, (tcg_target_long
) (s
->tb_next
+ args
[0]));
1268 s
->tb_next_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1272 tcg_out_call(s
, COND_AL
, args
[0]);
1274 tcg_out_callr(s
, COND_AL
, args
[0]);
1278 tcg_out_goto(s
, COND_AL
, args
[0]);
1280 tcg_out_bx(s
, COND_AL
, args
[0]);
1283 tcg_out_goto_label(s
, COND_AL
, args
[0]);
1286 case INDEX_op_ld8u_i32
:
1287 tcg_out_ld8u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1289 case INDEX_op_ld8s_i32
:
1290 tcg_out_ld8s(s
, COND_AL
, args
[0], args
[1], args
[2]);
1292 case INDEX_op_ld16u_i32
:
1293 tcg_out_ld16u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1295 case INDEX_op_ld16s_i32
:
1296 tcg_out_ld16s(s
, COND_AL
, args
[0], args
[1], args
[2]);
1298 case INDEX_op_ld_i32
:
1299 tcg_out_ld32u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1301 case INDEX_op_st8_i32
:
1302 tcg_out_st8u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1304 case INDEX_op_st16_i32
:
1305 tcg_out_st16u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1307 case INDEX_op_st_i32
:
1308 tcg_out_st32(s
, COND_AL
, args
[0], args
[1], args
[2]);
1311 case INDEX_op_mov_i32
:
1312 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1313 args
[0], 0, args
[1], SHIFT_IMM_LSL(0));
1315 case INDEX_op_movi_i32
:
1316 tcg_out_movi32(s
, COND_AL
, args
[0], args
[1]);
1318 case INDEX_op_add_i32
:
1321 case INDEX_op_sub_i32
:
1324 case INDEX_op_and_i32
:
1327 case INDEX_op_andc_i32
:
1330 case INDEX_op_or_i32
:
1333 case INDEX_op_xor_i32
:
1337 if (const_args
[2]) {
1339 rot
= encode_imm(args
[2]);
1340 tcg_out_dat_imm(s
, COND_AL
, c
,
1341 args
[0], args
[1], rotl(args
[2], rot
) | (rot
<< 7));
1343 tcg_out_dat_reg(s
, COND_AL
, c
,
1344 args
[0], args
[1], args
[2], SHIFT_IMM_LSL(0));
1346 case INDEX_op_add2_i32
:
1347 tcg_out_dat_reg2(s
, COND_AL
, ARITH_ADD
, ARITH_ADC
,
1348 args
[0], args
[1], args
[2], args
[3],
1349 args
[4], args
[5], SHIFT_IMM_LSL(0));
1351 case INDEX_op_sub2_i32
:
1352 tcg_out_dat_reg2(s
, COND_AL
, ARITH_SUB
, ARITH_SBC
,
1353 args
[0], args
[1], args
[2], args
[3],
1354 args
[4], args
[5], SHIFT_IMM_LSL(0));
1356 case INDEX_op_neg_i32
:
1357 tcg_out_dat_imm(s
, COND_AL
, ARITH_RSB
, args
[0], args
[1], 0);
1359 case INDEX_op_not_i32
:
1360 tcg_out_dat_reg(s
, COND_AL
,
1361 ARITH_MVN
, args
[0], 0, args
[1], SHIFT_IMM_LSL(0));
1363 case INDEX_op_mul_i32
:
1364 tcg_out_mul32(s
, COND_AL
, args
[0], args
[1], args
[2]);
1366 case INDEX_op_mulu2_i32
:
1367 tcg_out_umull32(s
, COND_AL
, args
[0], args
[1], args
[2], args
[3]);
1369 /* XXX: Perhaps args[2] & 0x1f is wrong */
1370 case INDEX_op_shl_i32
:
1372 SHIFT_IMM_LSL(args
[2] & 0x1f) : SHIFT_REG_LSL(args
[2]);
1374 case INDEX_op_shr_i32
:
1375 c
= const_args
[2] ? (args
[2] & 0x1f) ? SHIFT_IMM_LSR(args
[2] & 0x1f) :
1376 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args
[2]);
1378 case INDEX_op_sar_i32
:
1379 c
= const_args
[2] ? (args
[2] & 0x1f) ? SHIFT_IMM_ASR(args
[2] & 0x1f) :
1380 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args
[2]);
1383 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, args
[0], 0, args
[1], c
);
1386 case INDEX_op_brcond_i32
:
1387 if (const_args
[1]) {
1389 rot
= encode_imm(args
[1]);
1390 tcg_out_dat_imm(s
, COND_AL
, ARITH_CMP
,
1391 0, args
[0], rotl(args
[1], rot
) | (rot
<< 7));
1393 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0,
1394 args
[0], args
[1], SHIFT_IMM_LSL(0));
1396 tcg_out_goto_label(s
, tcg_cond_to_arm_cond
[args
[2]], args
[3]);
1398 case INDEX_op_brcond2_i32
:
1399 /* The resulting conditions are:
1400 * TCG_COND_EQ --> a0 == a2 && a1 == a3,
1401 * TCG_COND_NE --> (a0 != a2 && a1 == a3) || a1 != a3,
1402 * TCG_COND_LT(U) --> (a0 < a2 && a1 == a3) || a1 < a3,
1403 * TCG_COND_GE(U) --> (a0 >= a2 && a1 == a3) || (a1 >= a3 && a1 != a3),
1404 * TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3),
1405 * TCG_COND_GT(U) --> (a0 > a2 && a1 == a3) || a1 > a3,
1407 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0,
1408 args
[1], args
[3], SHIFT_IMM_LSL(0));
1409 tcg_out_dat_reg(s
, COND_EQ
, ARITH_CMP
, 0,
1410 args
[0], args
[2], SHIFT_IMM_LSL(0));
1411 tcg_out_goto_label(s
, tcg_cond_to_arm_cond
[args
[4]], args
[5]);
1413 case INDEX_op_setcond_i32
:
1414 if (const_args
[2]) {
1416 rot
= encode_imm(args
[2]);
1417 tcg_out_dat_imm(s
, COND_AL
, ARITH_CMP
,
1418 0, args
[1], rotl(args
[2], rot
) | (rot
<< 7));
1420 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0,
1421 args
[1], args
[2], SHIFT_IMM_LSL(0));
1423 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[args
[3]],
1424 ARITH_MOV
, args
[0], 0, 1);
1425 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[tcg_invert_cond(args
[3])],
1426 ARITH_MOV
, args
[0], 0, 0);
1428 case INDEX_op_setcond2_i32
:
1429 /* See brcond2_i32 comment */
1430 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0,
1431 args
[2], args
[4], SHIFT_IMM_LSL(0));
1432 tcg_out_dat_reg(s
, COND_EQ
, ARITH_CMP
, 0,
1433 args
[1], args
[3], SHIFT_IMM_LSL(0));
1434 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[args
[5]],
1435 ARITH_MOV
, args
[0], 0, 1);
1436 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[tcg_invert_cond(args
[5])],
1437 ARITH_MOV
, args
[0], 0, 0);
1440 case INDEX_op_qemu_ld8u
:
1441 tcg_out_qemu_ld(s
, COND_AL
, args
, 0);
1443 case INDEX_op_qemu_ld8s
:
1444 tcg_out_qemu_ld(s
, COND_AL
, args
, 0 | 4);
1446 case INDEX_op_qemu_ld16u
:
1447 tcg_out_qemu_ld(s
, COND_AL
, args
, 1);
1449 case INDEX_op_qemu_ld16s
:
1450 tcg_out_qemu_ld(s
, COND_AL
, args
, 1 | 4);
1452 case INDEX_op_qemu_ld32
:
1453 tcg_out_qemu_ld(s
, COND_AL
, args
, 2);
1455 case INDEX_op_qemu_ld64
:
1456 tcg_out_qemu_ld(s
, COND_AL
, args
, 3);
1459 case INDEX_op_qemu_st8
:
1460 tcg_out_qemu_st(s
, COND_AL
, args
, 0);
1462 case INDEX_op_qemu_st16
:
1463 tcg_out_qemu_st(s
, COND_AL
, args
, 1);
1465 case INDEX_op_qemu_st32
:
1466 tcg_out_qemu_st(s
, COND_AL
, args
, 2);
1468 case INDEX_op_qemu_st64
:
1469 tcg_out_qemu_st(s
, COND_AL
, args
, 3);
1472 case INDEX_op_ext8s_i32
:
1473 #ifdef __ARM_ARCH_7A__
1475 tcg_out32(s
, 0xe6af0070 | (args
[0] << 12) | args
[1]);
1477 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1478 args
[0], 0, args
[1], SHIFT_IMM_LSL(24));
1479 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1480 args
[0], 0, args
[0], SHIFT_IMM_ASR(24));
1483 case INDEX_op_ext16s_i32
:
1484 #ifdef __ARM_ARCH_7A__
1486 tcg_out32(s
, 0xe6bf0070 | (args
[0] << 12) | args
[1]);
1488 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1489 args
[0], 0, args
[1], SHIFT_IMM_LSL(16));
1490 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1491 args
[0], 0, args
[0], SHIFT_IMM_ASR(16));
1500 static const TCGTargetOpDef arm_op_defs
[] = {
1501 { INDEX_op_exit_tb
, { } },
1502 { INDEX_op_goto_tb
, { } },
1503 { INDEX_op_call
, { "ri" } },
1504 { INDEX_op_jmp
, { "ri" } },
1505 { INDEX_op_br
, { } },
1507 { INDEX_op_mov_i32
, { "r", "r" } },
1508 { INDEX_op_movi_i32
, { "r" } },
1510 { INDEX_op_ld8u_i32
, { "r", "r" } },
1511 { INDEX_op_ld8s_i32
, { "r", "r" } },
1512 { INDEX_op_ld16u_i32
, { "r", "r" } },
1513 { INDEX_op_ld16s_i32
, { "r", "r" } },
1514 { INDEX_op_ld_i32
, { "r", "r" } },
1515 { INDEX_op_st8_i32
, { "r", "r" } },
1516 { INDEX_op_st16_i32
, { "r", "r" } },
1517 { INDEX_op_st_i32
, { "r", "r" } },
1519 /* TODO: "r", "r", "ri" */
1520 { INDEX_op_add_i32
, { "r", "r", "rI" } },
1521 { INDEX_op_sub_i32
, { "r", "r", "rI" } },
1522 { INDEX_op_mul_i32
, { "r", "r", "r" } },
1523 { INDEX_op_mulu2_i32
, { "r", "r", "r", "r" } },
1524 { INDEX_op_and_i32
, { "r", "r", "rI" } },
1525 { INDEX_op_andc_i32
, { "r", "r", "rI" } },
1526 { INDEX_op_or_i32
, { "r", "r", "rI" } },
1527 { INDEX_op_xor_i32
, { "r", "r", "rI" } },
1528 { INDEX_op_neg_i32
, { "r", "r" } },
1529 { INDEX_op_not_i32
, { "r", "r" } },
1531 { INDEX_op_shl_i32
, { "r", "r", "ri" } },
1532 { INDEX_op_shr_i32
, { "r", "r", "ri" } },
1533 { INDEX_op_sar_i32
, { "r", "r", "ri" } },
1535 { INDEX_op_brcond_i32
, { "r", "rI" } },
1536 { INDEX_op_setcond_i32
, { "r", "r", "rI" } },
1538 /* TODO: "r", "r", "r", "r", "ri", "ri" */
1539 { INDEX_op_add2_i32
, { "r", "r", "r", "r", "r", "r" } },
1540 { INDEX_op_sub2_i32
, { "r", "r", "r", "r", "r", "r" } },
1541 { INDEX_op_brcond2_i32
, { "r", "r", "r", "r" } },
1542 { INDEX_op_setcond2_i32
, { "r", "r", "r", "r", "r" } },
1544 #if TARGET_LONG_BITS == 32
1545 { INDEX_op_qemu_ld8u
, { "r", "x" } },
1546 { INDEX_op_qemu_ld8s
, { "r", "x" } },
1547 { INDEX_op_qemu_ld16u
, { "r", "x" } },
1548 { INDEX_op_qemu_ld16s
, { "r", "x" } },
1549 { INDEX_op_qemu_ld32
, { "r", "x" } },
1550 { INDEX_op_qemu_ld64
, { "d", "r", "x" } },
1552 { INDEX_op_qemu_st8
, { "x", "x" } },
1553 { INDEX_op_qemu_st16
, { "x", "x" } },
1554 { INDEX_op_qemu_st32
, { "x", "x" } },
1555 { INDEX_op_qemu_st64
, { "x", "D", "x" } },
1557 { INDEX_op_qemu_ld8u
, { "r", "x", "X" } },
1558 { INDEX_op_qemu_ld8s
, { "r", "x", "X" } },
1559 { INDEX_op_qemu_ld16u
, { "r", "x", "X" } },
1560 { INDEX_op_qemu_ld16s
, { "r", "x", "X" } },
1561 { INDEX_op_qemu_ld32
, { "r", "x", "X" } },
1562 { INDEX_op_qemu_ld64
, { "d", "r", "x", "X" } },
1564 { INDEX_op_qemu_st8
, { "x", "x", "X" } },
1565 { INDEX_op_qemu_st16
, { "x", "x", "X" } },
1566 { INDEX_op_qemu_st32
, { "x", "x", "X" } },
1567 { INDEX_op_qemu_st64
, { "x", "D", "x", "X" } },
1570 { INDEX_op_ext8s_i32
, { "r", "r" } },
1571 { INDEX_op_ext16s_i32
, { "r", "r" } },
1576 void tcg_target_init(TCGContext
*s
)
1578 #if !defined(CONFIG_USER_ONLY)
1580 if ((1 << CPU_TLB_ENTRY_BITS
) != sizeof(CPUTLBEntry
))
1584 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I32
], 0, 0xffff);
1585 tcg_regset_set32(tcg_target_call_clobber_regs
, 0,
1590 (1 << TCG_REG_R12
) |
1591 (1 << TCG_REG_R14
));
1593 tcg_regset_clear(s
->reserved_regs
);
1594 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_CALL_STACK
);
1595 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R8
);
1596 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_PC
);
1598 tcg_add_target_add_op_defs(arm_op_defs
);
1601 static inline void tcg_out_ld(TCGContext
*s
, TCGType type
, int arg
,
1602 int arg1
, tcg_target_long arg2
)
1604 tcg_out_ld32u(s
, COND_AL
, arg
, arg1
, arg2
);
1607 static inline void tcg_out_st(TCGContext
*s
, TCGType type
, int arg
,
1608 int arg1
, tcg_target_long arg2
)
1610 tcg_out_st32(s
, COND_AL
, arg
, arg1
, arg2
);
1613 static void tcg_out_addi(TCGContext
*s
, int reg
, tcg_target_long val
)
1617 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, reg
, reg
, val
);
1622 tcg_out_dat_imm(s
, COND_AL
, ARITH_SUB
, reg
, reg
, -val
);
1628 static inline void tcg_out_mov(TCGContext
*s
, int ret
, int arg
)
1630 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, ret
, 0, arg
, SHIFT_IMM_LSL(0));
1633 static inline void tcg_out_movi(TCGContext
*s
, TCGType type
,
1634 int ret
, tcg_target_long arg
)
1636 tcg_out_movi32(s
, COND_AL
, ret
, arg
);
1639 void tcg_target_qemu_prologue(TCGContext
*s
)
1641 /* There is no need to save r7, it is used to store the address
1642 of the env structure and is not modified by GCC. */
1644 /* stmdb sp!, { r4 - r6, r8 - r11, lr } */
1645 tcg_out32(s
, (COND_AL
<< 28) | 0x092d4f70);
1647 tcg_out_bx(s
, COND_AL
, TCG_REG_R0
);
1648 tb_ret_addr
= s
->code_ptr
;
1650 /* ldmia sp!, { r4 - r6, r8 - r11, pc } */
1651 tcg_out32(s
, (COND_AL
<< 28) | 0x08bd8f70);