2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 static uint8_t *tb_ret_addr
;
28 #if TARGET_PHYS_ADDR_BITS <= 32
29 #define ADDEND_OFFSET 0
31 #define ADDEND_OFFSET 4
34 static const char * const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
69 static const int tcg_target_reg_alloc_order
[] = {
104 static const int tcg_target_call_iarg_regs
[] = {
115 static const int tcg_target_call_oarg_regs
[2] = {
120 static const int tcg_target_callee_save_regs
[] = {
137 static uint32_t reloc_pc24_val (void *pc
, tcg_target_long target
)
139 tcg_target_long disp
;
141 disp
= target
- (tcg_target_long
) pc
;
142 if ((disp
<< 6) >> 6 != disp
)
145 return disp
& 0x3fffffc;
148 static void reloc_pc24 (void *pc
, tcg_target_long target
)
150 *(uint32_t *) pc
= (*(uint32_t *) pc
& ~0x3fffffc)
151 | reloc_pc24_val (pc
, target
);
154 static uint16_t reloc_pc14_val (void *pc
, tcg_target_long target
)
156 tcg_target_long disp
;
158 disp
= target
- (tcg_target_long
) pc
;
159 if (disp
!= (int16_t) disp
)
162 return disp
& 0xfffc;
165 static void reloc_pc14 (void *pc
, tcg_target_long target
)
167 *(uint32_t *) pc
= (*(uint32_t *) pc
& ~0xfffc)
168 | reloc_pc14_val (pc
, target
);
171 static void patch_reloc(uint8_t *code_ptr
, int type
,
172 tcg_target_long value
, tcg_target_long addend
)
177 reloc_pc14 (code_ptr
, value
);
180 reloc_pc24 (code_ptr
, value
);
187 /* maximum number of register used for input function arguments */
188 static int tcg_target_get_call_iarg_regs_count(int flags
)
190 return sizeof (tcg_target_call_iarg_regs
) / sizeof (tcg_target_call_iarg_regs
[0]);
193 /* parse target specific constraints */
194 static int target_parse_constraint(TCGArgConstraint
*ct
, const char **pct_str
)
200 case 'A': case 'B': case 'C': case 'D':
201 ct
->ct
|= TCG_CT_REG
;
202 tcg_regset_set_reg(ct
->u
.regs
, 3 + ct_str
[0] - 'A');
205 ct
->ct
|= TCG_CT_REG
;
206 tcg_regset_set32(ct
->u
.regs
, 0, 0xffffffff);
208 case 'L': /* qemu_ld constraint */
209 ct
->ct
|= TCG_CT_REG
;
210 tcg_regset_set32(ct
->u
.regs
, 0, 0xffffffff);
211 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R3
);
212 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R4
);
214 case 'K': /* qemu_st[8..32] constraint */
215 ct
->ct
|= TCG_CT_REG
;
216 tcg_regset_set32(ct
->u
.regs
, 0, 0xffffffff);
217 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R3
);
218 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R4
);
219 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R5
);
220 #if TARGET_LONG_BITS == 64
221 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R6
);
224 case 'M': /* qemu_st64 constraint */
225 ct
->ct
|= TCG_CT_REG
;
226 tcg_regset_set32(ct
->u
.regs
, 0, 0xffffffff);
227 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R3
);
228 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R4
);
229 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R5
);
230 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R6
);
231 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R7
);
241 /* test if a constant matches the constraint */
242 static int tcg_target_const_match(tcg_target_long val
,
243 const TCGArgConstraint
*arg_ct
)
248 if (ct
& TCG_CT_CONST
)
253 #define OPCD(opc) ((opc)<<26)
254 #define XO31(opc) (OPCD(31)|((opc)<<1))
255 #define XO19(opc) (OPCD(19)|((opc)<<1))
267 #define ADDI OPCD(14)
268 #define ADDIS OPCD(15)
270 #define ORIS OPCD(25)
271 #define XORI OPCD(26)
272 #define XORIS OPCD(27)
273 #define ANDI OPCD(28)
274 #define ANDIS OPCD(29)
275 #define MULLI OPCD( 7)
276 #define CMPLI OPCD(10)
277 #define CMPI OPCD(11)
279 #define LWZU OPCD(33)
280 #define STWU OPCD(37)
282 #define RLWINM OPCD(21)
284 #define BCLR XO19( 16)
285 #define BCCTR XO19(528)
286 #define CRAND XO19(257)
287 #define CRANDC XO19(129)
288 #define CRNAND XO19(225)
289 #define CROR XO19(449)
291 #define EXTSB XO31(954)
292 #define EXTSH XO31(922)
293 #define ADD XO31(266)
294 #define ADDE XO31(138)
295 #define ADDC XO31( 10)
296 #define AND XO31( 28)
297 #define SUBF XO31( 40)
298 #define SUBFC XO31( 8)
299 #define SUBFE XO31(136)
301 #define XOR XO31(316)
302 #define MULLW XO31(235)
303 #define MULHWU XO31( 11)
304 #define DIVW XO31(491)
305 #define DIVWU XO31(459)
307 #define CMPL XO31( 32)
308 #define LHBRX XO31(790)
309 #define LWBRX XO31(534)
310 #define STHBRX XO31(918)
311 #define STWBRX XO31(662)
312 #define MFSPR XO31(339)
313 #define MTSPR XO31(467)
314 #define SRAWI XO31(824)
315 #define NEG XO31(104)
317 #define LBZX XO31( 87)
318 #define LHZX XO31(276)
319 #define LHAX XO31(343)
320 #define LWZX XO31( 23)
321 #define STBX XO31(215)
322 #define STHX XO31(407)
323 #define STWX XO31(151)
325 #define SPR(a,b) ((((a)<<5)|(b))<<11)
327 #define CTR SPR(9, 0)
329 #define SLW XO31( 24)
330 #define SRW XO31(536)
331 #define SRAW XO31(792)
334 #define STMW OPCD(47)
337 #define TRAP (TW | TO (31))
339 #define RT(r) ((r)<<21)
340 #define RS(r) ((r)<<21)
341 #define RA(r) ((r)<<16)
342 #define RB(r) ((r)<<11)
343 #define TO(t) ((t)<<21)
344 #define SH(s) ((s)<<11)
345 #define MB(b) ((b)<<6)
346 #define ME(e) ((e)<<1)
347 #define BO(o) ((o)<<21)
351 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
352 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
354 #define BF(n) ((n)<<23)
355 #define BI(n, c) (((c)+((n)*4))<<16)
356 #define BT(n, c) (((c)+((n)*4))<<21)
357 #define BA(n, c) (((c)+((n)*4))<<16)
358 #define BB(n, c) (((c)+((n)*4))<<11)
360 #define BO_COND_TRUE BO (12)
361 #define BO_COND_FALSE BO (4)
362 #define BO_ALWAYS BO (20)
371 static const uint32_t tcg_to_bc
[10] = {
372 [TCG_COND_EQ
] = BC
| BI (7, CR_EQ
) | BO_COND_TRUE
,
373 [TCG_COND_NE
] = BC
| BI (7, CR_EQ
) | BO_COND_FALSE
,
374 [TCG_COND_LT
] = BC
| BI (7, CR_LT
) | BO_COND_TRUE
,
375 [TCG_COND_GE
] = BC
| BI (7, CR_LT
) | BO_COND_FALSE
,
376 [TCG_COND_LE
] = BC
| BI (7, CR_GT
) | BO_COND_FALSE
,
377 [TCG_COND_GT
] = BC
| BI (7, CR_GT
) | BO_COND_TRUE
,
378 [TCG_COND_LTU
] = BC
| BI (7, CR_LT
) | BO_COND_TRUE
,
379 [TCG_COND_GEU
] = BC
| BI (7, CR_LT
) | BO_COND_FALSE
,
380 [TCG_COND_LEU
] = BC
| BI (7, CR_GT
) | BO_COND_FALSE
,
381 [TCG_COND_GTU
] = BC
| BI (7, CR_GT
) | BO_COND_TRUE
,
384 static void tcg_out_mov(TCGContext
*s
, int ret
, int arg
)
386 tcg_out32 (s
, OR
| SAB (arg
, ret
, arg
));
389 static void tcg_out_movi(TCGContext
*s
, TCGType type
,
390 int ret
, tcg_target_long arg
)
392 if (arg
== (int16_t) arg
)
393 tcg_out32 (s
, ADDI
| RT (ret
) | RA (0) | (arg
& 0xffff));
395 tcg_out32 (s
, ADDIS
| RT (ret
) | RA (0) | ((arg
>> 16) & 0xffff));
397 tcg_out32 (s
, ORI
| RS (ret
) | RA (ret
) | (arg
& 0xffff));
401 static void tcg_out_ldst (TCGContext
*s
, int ret
, int addr
,
402 int offset
, int op1
, int op2
)
404 if (offset
== (int16_t) offset
)
405 tcg_out32 (s
, op1
| RT (ret
) | RA (addr
) | (offset
& 0xffff));
407 tcg_out_movi (s
, TCG_TYPE_I32
, 0, offset
);
408 tcg_out32 (s
, op2
| RT (ret
) | RA (addr
) | RB (0));
412 static void tcg_out_b (TCGContext
*s
, int mask
, tcg_target_long target
)
414 tcg_target_long disp
;
416 disp
= target
- (tcg_target_long
) s
->code_ptr
;
417 if ((disp
<< 6) >> 6 == disp
)
418 tcg_out32 (s
, B
| (disp
& 0x3fffffc) | mask
);
420 tcg_out_movi (s
, TCG_TYPE_I32
, 0, (tcg_target_long
) target
);
421 tcg_out32 (s
, MTSPR
| RS (0) | CTR
);
422 tcg_out32 (s
, BCCTR
| BO_ALWAYS
| mask
);
426 #if defined(CONFIG_SOFTMMU)
427 extern void __ldb_mmu(void);
428 extern void __ldw_mmu(void);
429 extern void __ldl_mmu(void);
430 extern void __ldq_mmu(void);
432 extern void __stb_mmu(void);
433 extern void __stw_mmu(void);
434 extern void __stl_mmu(void);
435 extern void __stq_mmu(void);
437 static void *qemu_ld_helpers
[4] = {
444 static void *qemu_st_helpers
[4] = {
452 static void tcg_out_qemu_ld (TCGContext
*s
, const TCGArg
*args
, int opc
)
454 int addr_reg
, data_reg
, data_reg2
, r0
, mem_index
, s_bits
, bswap
;
455 #ifdef CONFIG_SOFTMMU
457 void *label1_ptr
, *label2_ptr
;
459 #if TARGET_LONG_BITS == 64
469 #if TARGET_LONG_BITS == 64
475 #ifdef CONFIG_SOFTMMU
480 tcg_out32 (s
, (RLWINM
483 | SH (32 - (TARGET_PAGE_BITS
- CPU_TLB_ENTRY_BITS
))
484 | MB (32 - (CPU_TLB_BITS
+ CPU_TLB_ENTRY_BITS
))
485 | ME (31 - CPU_TLB_ENTRY_BITS
)
488 tcg_out32 (s
, ADD
| RT (r0
) | RA (r0
) | RB (TCG_AREG0
));
492 | offsetof (CPUState
, tlb_table
[mem_index
][0].addr_read
)
495 tcg_out32 (s
, (RLWINM
499 | MB ((32 - s_bits
) & 31)
500 | ME (31 - TARGET_PAGE_BITS
)
504 tcg_out32 (s
, CMP
| BF (7) | RA (r2
) | RB (r1
));
505 #if TARGET_LONG_BITS == 64
506 tcg_out32 (s
, LWZ
| RT (r1
) | RA (r0
) | 4);
507 tcg_out32 (s
, CMP
| BF (6) | RA (addr_reg2
) | RB (r1
));
508 tcg_out32 (s
, CRAND
| BT (7, CR_EQ
) | BA (6, CR_EQ
) | BB (7, CR_EQ
));
511 label1_ptr
= s
->code_ptr
;
513 tcg_out32 (s
, BC
| BI (7, CR_EQ
) | BO_COND_TRUE
);
517 #if TARGET_LONG_BITS == 32
518 tcg_out_mov (s
, 3, addr_reg
);
519 tcg_out_movi (s
, TCG_TYPE_I32
, 4, mem_index
);
521 tcg_out_mov (s
, 3, addr_reg2
);
522 tcg_out_mov (s
, 4, addr_reg
);
523 tcg_out_movi (s
, TCG_TYPE_I32
, 5, mem_index
);
526 tcg_out_b (s
, LK
, (tcg_target_long
) qemu_ld_helpers
[s_bits
]);
529 tcg_out32 (s
, EXTSB
| RA (data_reg
) | RS (3));
532 tcg_out32 (s
, EXTSH
| RA (data_reg
) | RS (3));
538 tcg_out_mov (s
, data_reg
, 3);
542 if (data_reg2
== 4) {
543 tcg_out_mov (s
, 0, 4);
544 tcg_out_mov (s
, 4, 3);
545 tcg_out_mov (s
, 3, 0);
548 tcg_out_mov (s
, data_reg2
, 3);
549 tcg_out_mov (s
, 3, 4);
553 if (data_reg
!= 4) tcg_out_mov (s
, data_reg
, 4);
554 if (data_reg2
!= 3) tcg_out_mov (s
, data_reg2
, 3);
558 label2_ptr
= s
->code_ptr
;
561 /* label1: fast path */
563 reloc_pc14 (label1_ptr
, (tcg_target_long
) s
->code_ptr
);
566 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
570 | (ADDEND_OFFSET
+ offsetof (CPUTLBEntry
, addend
)
571 - offsetof (CPUTLBEntry
, addr_read
))
573 /* r0 = env->tlb_table[mem_index][index].addend */
574 tcg_out32 (s
, ADD
| RT (r0
) | RA (r0
) | RB (addr_reg
));
575 /* r0 = env->tlb_table[mem_index][index].addend + addr */
577 #else /* !CONFIG_SOFTMMU */
581 #ifdef TARGET_WORDS_BIGENDIAN
589 tcg_out32 (s
, LBZ
| RT (data_reg
) | RA (r0
));
592 tcg_out32 (s
, LBZ
| RT (data_reg
) | RA (r0
));
593 tcg_out32 (s
, EXTSB
| RA (data_reg
) | RS (data_reg
));
596 if (bswap
) tcg_out32 (s
, LHBRX
| RT (data_reg
) | RB (r0
));
597 else tcg_out32 (s
, LHZ
| RT (data_reg
) | RA (r0
));
601 tcg_out32 (s
, LHBRX
| RT (data_reg
) | RB (r0
));
602 tcg_out32 (s
, EXTSH
| RA (data_reg
) | RS (data_reg
));
604 else tcg_out32 (s
, LHA
| RT (data_reg
) | RA (r0
));
607 if (bswap
) tcg_out32 (s
, LWBRX
| RT (data_reg
) | RB (r0
));
608 else tcg_out32 (s
, LWZ
| RT (data_reg
)| RA (r0
));
612 if (r0
== data_reg
) {
613 tcg_out32 (s
, LWBRX
| RT (0) | RB (r0
));
614 tcg_out32 (s
, ADDI
| RT (r0
) | RA (r0
) | 4);
615 tcg_out32 (s
, LWBRX
| RT (data_reg2
) | RB (r0
));
616 tcg_out_mov (s
, data_reg
, 0);
619 tcg_out32 (s
, LWBRX
| RT (data_reg
) | RB (r0
));
620 tcg_out32 (s
, ADDI
| RT (r0
) | RA (r0
) | 4);
621 tcg_out32 (s
, LWBRX
| RT (data_reg2
) | RB (r0
));
625 if (r0
== data_reg2
) {
626 tcg_out32 (s
, LWZ
| RT (0) | RA (r0
));
627 tcg_out32 (s
, LWZ
| RT (data_reg
) | RA (r0
) | 4);
628 tcg_out_mov (s
, data_reg2
, 0);
631 tcg_out32 (s
, LWZ
| RT (data_reg2
) | RA (r0
));
632 tcg_out32 (s
, LWZ
| RT (data_reg
) | RA (r0
) | 4);
638 #ifdef CONFIG_SOFTMMU
639 reloc_pc24 (label2_ptr
, (tcg_target_long
) s
->code_ptr
);
643 static void tcg_out_qemu_st (TCGContext
*s
, const TCGArg
*args
, int opc
)
645 int addr_reg
, r0
, r1
, data_reg
, data_reg2
, mem_index
, bswap
;
646 #ifdef CONFIG_SOFTMMU
648 void *label1_ptr
, *label2_ptr
;
650 #if TARGET_LONG_BITS == 64
660 #if TARGET_LONG_BITS == 64
665 #ifdef CONFIG_SOFTMMU
670 tcg_out32 (s
, (RLWINM
673 | SH (32 - (TARGET_PAGE_BITS
- CPU_TLB_ENTRY_BITS
))
674 | MB (32 - (CPU_TLB_ENTRY_BITS
+ CPU_TLB_BITS
))
675 | ME (31 - CPU_TLB_ENTRY_BITS
)
678 tcg_out32 (s
, ADD
| RT (r0
) | RA (r0
) | RB (TCG_AREG0
));
682 | offsetof (CPUState
, tlb_table
[mem_index
][0].addr_write
)
685 tcg_out32 (s
, (RLWINM
689 | MB ((32 - opc
) & 31)
690 | ME (31 - TARGET_PAGE_BITS
)
694 tcg_out32 (s
, CMP
| (7 << 23) | RA (r2
) | RB (r1
));
695 #if TARGET_LONG_BITS == 64
696 tcg_out32 (s
, LWZ
| RT (r1
) | RA (r0
) | 4);
697 tcg_out32 (s
, CMP
| BF (6) | RA (addr_reg2
) | RB (r1
));
698 tcg_out32 (s
, CRAND
| BT (7, CR_EQ
) | BA (6, CR_EQ
) | BB (7, CR_EQ
));
701 label1_ptr
= s
->code_ptr
;
703 tcg_out32 (s
, BC
| BI (7, CR_EQ
) | BO_COND_TRUE
);
707 #if TARGET_LONG_BITS == 32
708 tcg_out_mov (s
, 3, addr_reg
);
711 tcg_out_mov (s
, 3, addr_reg2
);
712 tcg_out_mov (s
, 4, addr_reg
);
718 tcg_out32 (s
, (RLWINM
726 tcg_out32 (s
, (RLWINM
734 tcg_out_mov (s
, ir
, data_reg
);
737 tcg_out_mov (s
, 5, data_reg2
);
738 tcg_out_mov (s
, 6, data_reg
);
744 tcg_out_movi (s
, TCG_TYPE_I32
, ir
, mem_index
);
745 tcg_out_b (s
, LK
, (tcg_target_long
) qemu_st_helpers
[opc
]);
746 label2_ptr
= s
->code_ptr
;
749 /* label1: fast path */
751 reloc_pc14 (label1_ptr
, (tcg_target_long
) s
->code_ptr
);
757 | (ADDEND_OFFSET
+ offsetof (CPUTLBEntry
, addend
)
758 - offsetof (CPUTLBEntry
, addr_write
))
760 /* r0 = env->tlb_table[mem_index][index].addend */
761 tcg_out32 (s
, ADD
| RT (r0
) | RA (r0
) | RB (addr_reg
));
762 /* r0 = env->tlb_table[mem_index][index].addend + addr */
764 #else /* !CONFIG_SOFTMMU */
769 #ifdef TARGET_WORDS_BIGENDIAN
776 tcg_out32 (s
, STB
| RS (data_reg
) | RA (r0
));
779 if (bswap
) tcg_out32 (s
, STHBRX
| RS (data_reg
) | RA (0) | RB (r0
));
780 else tcg_out32 (s
, STH
| RS (data_reg
) | RA (r0
));
783 if (bswap
) tcg_out32 (s
, STWBRX
| RS (data_reg
) | RA (0) | RB (r0
));
784 else tcg_out32 (s
, STW
| RS (data_reg
) | RA (r0
));
788 tcg_out32 (s
, ADDI
| RT (r1
) | RA (r0
) | 4);
789 tcg_out32 (s
, STWBRX
| RS (data_reg
) | RA (0) | RB (r0
));
790 tcg_out32 (s
, STWBRX
| RS (data_reg2
) | RA (0) | RB (r1
));
793 tcg_out32 (s
, STW
| RS (data_reg2
) | RA (r0
));
794 tcg_out32 (s
, STW
| RS (data_reg
) | RA (r0
) | 4);
799 #ifdef CONFIG_SOFTMMU
800 reloc_pc24 (label2_ptr
, (tcg_target_long
) s
->code_ptr
);
804 void tcg_target_qemu_prologue (TCGContext
*s
)
811 + TCG_STATIC_CALL_ARGS_SIZE
812 + ARRAY_SIZE (tcg_target_callee_save_regs
) * 4
814 frame_size
= (frame_size
+ 15) & ~15;
816 tcg_out32 (s
, MFSPR
| RT (0) | LR
);
817 tcg_out32 (s
, STWU
| RS (1) | RA (1) | (-frame_size
& 0xffff));
818 for (i
= 0; i
< ARRAY_SIZE (tcg_target_callee_save_regs
); ++i
)
820 | RS (tcg_target_callee_save_regs
[i
])
822 | (i
* 4 + 8 + TCG_STATIC_CALL_ARGS_SIZE
)
825 tcg_out32 (s
, STW
| RS (0) | RA (1) | (frame_size
+ 4));
827 tcg_out32 (s
, MTSPR
| RS (3) | CTR
);
828 tcg_out32 (s
, BCCTR
| BO_ALWAYS
);
829 tb_ret_addr
= s
->code_ptr
;
831 for (i
= 0; i
< ARRAY_SIZE (tcg_target_callee_save_regs
); ++i
)
833 | RT (tcg_target_callee_save_regs
[i
])
835 | (i
* 4 + 8 + TCG_STATIC_CALL_ARGS_SIZE
)
838 tcg_out32 (s
, LWZ
| RT (0) | RA (1) | (frame_size
+ 4));
839 tcg_out32 (s
, MTSPR
| RS (0) | LR
);
840 tcg_out32 (s
, ADDI
| RT (1) | RA (1) | frame_size
);
841 tcg_out32 (s
, BCLR
| BO_ALWAYS
);
844 static void tcg_out_ld (TCGContext
*s
, TCGType type
, int ret
, int arg1
,
845 tcg_target_long arg2
)
847 tcg_out_ldst (s
, ret
, arg1
, arg2
, LWZ
, LWZX
);
850 static void tcg_out_st (TCGContext
*s
, TCGType type
, int arg
, int arg1
,
851 tcg_target_long arg2
)
853 tcg_out_ldst (s
, arg
, arg1
, arg2
, STW
, STWX
);
856 static void ppc_addi (TCGContext
*s
, int rt
, int ra
, tcg_target_long si
)
861 if (si
== (int16_t) si
)
862 tcg_out32 (s
, ADDI
| RT (rt
) | RA (ra
) | (si
& 0xffff));
864 uint16_t h
= ((si
>> 16) & 0xffff) + ((uint16_t) si
>> 15);
865 tcg_out32 (s
, ADDIS
| RT (rt
) | RA (ra
) | h
);
866 tcg_out32 (s
, ADDI
| RT (rt
) | RA (rt
) | (si
& 0xffff));
870 static void tcg_out_addi(TCGContext
*s
, int reg
, tcg_target_long val
)
872 ppc_addi (s
, reg
, reg
, val
);
875 static void tcg_out_cmp (TCGContext
*s
, int cond
, TCGArg arg1
, TCGArg arg2
,
876 int const_arg2
, int cr
)
885 if ((int16_t) arg2
== arg2
) {
890 else if ((uint16_t) arg2
== arg2
) {
905 if ((int16_t) arg2
== arg2
) {
920 if ((uint16_t) arg2
== arg2
) {
936 tcg_out32 (s
, op
| RA (arg1
) | (arg2
& 0xffff));
939 tcg_out_movi (s
, TCG_TYPE_I32
, 0, arg2
);
940 tcg_out32 (s
, op
| RA (arg1
) | RB (0));
943 tcg_out32 (s
, op
| RA (arg1
) | RB (arg2
));
948 static void tcg_out_bc (TCGContext
*s
, int bc
, int label_index
)
950 TCGLabel
*l
= &s
->labels
[label_index
];
953 tcg_out32 (s
, bc
| reloc_pc14_val (s
->code_ptr
, l
->u
.value
));
955 uint16_t val
= *(uint16_t *) &s
->code_ptr
[2];
957 /* Thanks to Andrzej Zaborowski */
958 tcg_out32 (s
, bc
| (val
& 0xfffc));
959 tcg_out_reloc (s
, s
->code_ptr
- 4, R_PPC_REL14
, label_index
, 0);
963 static void tcg_out_brcond (TCGContext
*s
, int cond
,
964 TCGArg arg1
, TCGArg arg2
, int const_arg2
,
967 tcg_out_cmp (s
, cond
, arg1
, arg2
, const_arg2
, 7);
968 tcg_out_bc (s
, tcg_to_bc
[cond
], label_index
);
971 /* XXX: we implement it at the target level to avoid having to
972 handle cross basic blocks temporaries */
973 static void tcg_out_brcond2 (TCGContext
*s
, const TCGArg
*args
,
974 const int *const_args
)
976 int cond
= args
[4], label_index
= args
[5], op
;
977 struct { int bit1
; int bit2
; int cond2
; } bits
[] = {
978 [TCG_COND_LT
] = { CR_LT
, CR_LT
, TCG_COND_LT
},
979 [TCG_COND_LE
] = { CR_LT
, CR_GT
, TCG_COND_LT
},
980 [TCG_COND_GT
] = { CR_GT
, CR_GT
, TCG_COND_GT
},
981 [TCG_COND_GE
] = { CR_GT
, CR_LT
, TCG_COND_GT
},
982 [TCG_COND_LTU
] = { CR_LT
, CR_LT
, TCG_COND_LTU
},
983 [TCG_COND_LEU
] = { CR_LT
, CR_GT
, TCG_COND_LTU
},
984 [TCG_COND_GTU
] = { CR_GT
, CR_GT
, TCG_COND_GTU
},
985 [TCG_COND_GEU
] = { CR_GT
, CR_LT
, TCG_COND_GTU
},
990 tcg_out_cmp (s
, TCG_COND_EQ
, args
[0], args
[2], const_args
[2], 6);
991 tcg_out_cmp (s
, TCG_COND_EQ
, args
[1], args
[3], const_args
[3], 7);
992 tcg_out32 (s
, CRAND
| BT (7, CR_EQ
) | BA (6, CR_EQ
) | BB (7, CR_EQ
));
995 tcg_out_cmp (s
, TCG_COND_NE
, args
[0], args
[2], const_args
[2], 6);
996 tcg_out_cmp (s
, TCG_COND_NE
, args
[1], args
[3], const_args
[3], 7);
997 tcg_out32 (s
, CRNAND
| BT (7, CR_EQ
) | BA (6, CR_EQ
) | BB (7, CR_EQ
));
1007 op
= (b
->bit1
!= b
->bit2
) ? CRANDC
: CRAND
;
1008 tcg_out_cmp (s
, b
->cond2
, args
[1], args
[3], const_args
[3], 5);
1009 tcg_out_cmp (s
, TCG_COND_EQ
, args
[1], args
[3], const_args
[3], 6);
1010 tcg_out_cmp (s
, cond
, args
[0], args
[2], const_args
[2], 7);
1011 tcg_out32 (s
, op
| BT (7, CR_EQ
) | BA (6, CR_EQ
) | BB (7, b
->bit2
));
1012 tcg_out32 (s
, CROR
| BT (7, CR_EQ
) | BA (5, b
->bit1
) | BB (7, CR_EQ
));
1018 tcg_out_bc (s
, (BC
| BI (7, CR_EQ
) | BO_COND_TRUE
), label_index
);
1021 static void tcg_out_op(TCGContext
*s
, int opc
, const TCGArg
*args
,
1022 const int *const_args
)
1025 case INDEX_op_exit_tb
:
1026 tcg_out_movi (s
, TCG_TYPE_I32
, TCG_REG_R3
, args
[0]);
1027 tcg_out_b (s
, 0, (tcg_target_long
) tb_ret_addr
);
1029 case INDEX_op_goto_tb
:
1030 if (s
->tb_jmp_offset
) {
1031 /* direct jump method */
1033 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1039 s
->tb_next_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1043 TCGLabel
*l
= &s
->labels
[args
[0]];
1046 tcg_out_b (s
, 0, l
->u
.value
);
1049 uint32_t val
= *(uint32_t *) s
->code_ptr
;
1051 /* Thanks to Andrzej Zaborowski */
1052 tcg_out32 (s
, B
| (val
& 0x3fffffc));
1053 tcg_out_reloc (s
, s
->code_ptr
- 4, R_PPC_REL24
, args
[0], 0);
1058 if (const_args
[0]) {
1059 tcg_out_b (s
, LK
, args
[0]);
1062 tcg_out32 (s
, MTSPR
| RS (args
[0]) | LR
);
1063 tcg_out32 (s
, BCLR
| BO_ALWAYS
| LK
);
1067 if (const_args
[0]) {
1068 tcg_out_b (s
, 0, args
[0]);
1071 tcg_out32 (s
, MTSPR
| RS (args
[0]) | CTR
);
1072 tcg_out32 (s
, BCCTR
| BO_ALWAYS
);
1075 case INDEX_op_movi_i32
:
1076 tcg_out_movi(s
, TCG_TYPE_I32
, args
[0], args
[1]);
1078 case INDEX_op_ld8u_i32
:
1079 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LBZ
, LBZX
);
1081 case INDEX_op_ld8s_i32
:
1082 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LBZ
, LBZX
);
1083 tcg_out32 (s
, EXTSB
| RS (args
[0]) | RA (args
[0]));
1085 case INDEX_op_ld16u_i32
:
1086 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LHZ
, LHZX
);
1088 case INDEX_op_ld16s_i32
:
1089 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LHA
, LHAX
);
1091 case INDEX_op_ld_i32
:
1092 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LWZ
, LWZX
);
1094 case INDEX_op_st8_i32
:
1095 tcg_out_ldst (s
, args
[0], args
[1], args
[2], STB
, STBX
);
1097 case INDEX_op_st16_i32
:
1098 tcg_out_ldst (s
, args
[0], args
[1], args
[2], STH
, STHX
);
1100 case INDEX_op_st_i32
:
1101 tcg_out_ldst (s
, args
[0], args
[1], args
[2], STW
, STWX
);
1104 case INDEX_op_add_i32
:
1106 ppc_addi (s
, args
[0], args
[1], args
[2]);
1108 tcg_out32 (s
, ADD
| TAB (args
[0], args
[1], args
[2]));
1110 case INDEX_op_sub_i32
:
1112 ppc_addi (s
, args
[0], args
[1], -args
[2]);
1114 tcg_out32 (s
, SUBF
| TAB (args
[0], args
[2], args
[1]));
1117 case INDEX_op_and_i32
:
1118 if (const_args
[2]) {
1120 tcg_out_movi (s
, TCG_TYPE_I32
, args
[0], 0);
1122 if ((args
[2] & 0xffff) == args
[2])
1123 tcg_out32 (s
, ANDI
| RS (args
[1]) | RA (args
[0]) | args
[2]);
1124 else if ((args
[2] & 0xffff0000) == args
[2])
1125 tcg_out32 (s
, ANDIS
| RS (args
[1]) | RA (args
[0])
1126 | ((args
[2] >> 16) & 0xffff));
1127 else if (args
[2] == 0xffffffff) {
1128 if (args
[0] != args
[1])
1129 tcg_out_mov (s
, args
[0], args
[1]);
1132 tcg_out_movi (s
, TCG_TYPE_I32
, 0, args
[2]);
1133 tcg_out32 (s
, AND
| SAB (args
[1], args
[0], 0));
1138 tcg_out32 (s
, AND
| SAB (args
[1], args
[0], args
[2]));
1140 case INDEX_op_or_i32
:
1141 if (const_args
[2]) {
1143 if (args
[2] & 0xffff) {
1144 tcg_out32 (s
, ORI
| RS (args
[1]) | RA (args
[0])
1145 | (args
[2] & 0xffff));
1147 tcg_out32 (s
, ORIS
| RS (args
[0]) | RA (args
[0])
1148 | ((args
[2] >> 16) & 0xffff));
1151 tcg_out32 (s
, ORIS
| RS (args
[1]) | RA (args
[0])
1152 | ((args
[2] >> 16) & 0xffff));
1156 if (args
[0] != args
[1])
1157 tcg_out_mov (s
, args
[0], args
[1]);
1161 tcg_out32 (s
, OR
| SAB (args
[1], args
[0], args
[2]));
1163 case INDEX_op_xor_i32
:
1164 if (const_args
[2]) {
1166 if ((args
[2] & 0xffff) == args
[2])
1167 tcg_out32 (s
, XORI
| RS (args
[1]) | RA (args
[0])
1168 | (args
[2] & 0xffff));
1169 else if ((args
[2] & 0xffff0000) == args
[2])
1170 tcg_out32 (s
, XORIS
| RS (args
[1]) | RA (args
[0])
1171 | ((args
[2] >> 16) & 0xffff));
1173 tcg_out_movi (s
, TCG_TYPE_I32
, 0, args
[2]);
1174 tcg_out32 (s
, XOR
| SAB (args
[1], args
[0], 0));
1178 if (args
[0] != args
[1])
1179 tcg_out_mov (s
, args
[0], args
[1]);
1183 tcg_out32 (s
, XOR
| SAB (args
[1], args
[0], args
[2]));
1186 case INDEX_op_mul_i32
:
1187 if (const_args
[2]) {
1188 if (args
[2] == (int16_t) args
[2])
1189 tcg_out32 (s
, MULLI
| RT (args
[0]) | RA (args
[1])
1190 | (args
[2] & 0xffff));
1192 tcg_out_movi (s
, TCG_TYPE_I32
, 0, args
[2]);
1193 tcg_out32 (s
, MULLW
| TAB (args
[0], args
[1], 0));
1197 tcg_out32 (s
, MULLW
| TAB (args
[0], args
[1], args
[2]));
1200 case INDEX_op_div_i32
:
1201 tcg_out32 (s
, DIVW
| TAB (args
[0], args
[1], args
[2]));
1204 case INDEX_op_divu_i32
:
1205 tcg_out32 (s
, DIVWU
| TAB (args
[0], args
[1], args
[2]));
1208 case INDEX_op_rem_i32
:
1209 tcg_out32 (s
, DIVW
| TAB (0, args
[1], args
[2]));
1210 tcg_out32 (s
, MULLW
| TAB (0, 0, args
[2]));
1211 tcg_out32 (s
, SUBF
| TAB (args
[0], 0, args
[1]));
1214 case INDEX_op_remu_i32
:
1215 tcg_out32 (s
, DIVWU
| TAB (0, args
[1], args
[2]));
1216 tcg_out32 (s
, MULLW
| TAB (0, 0, args
[2]));
1217 tcg_out32 (s
, SUBF
| TAB (args
[0], 0, args
[1]));
1220 case INDEX_op_mulu2_i32
:
1221 if (args
[0] == args
[2] || args
[0] == args
[3]) {
1222 tcg_out32 (s
, MULLW
| TAB (0, args
[2], args
[3]));
1223 tcg_out32 (s
, MULHWU
| TAB (args
[1], args
[2], args
[3]));
1224 tcg_out_mov (s
, args
[0], 0);
1227 tcg_out32 (s
, MULLW
| TAB (args
[0], args
[2], args
[3]));
1228 tcg_out32 (s
, MULHWU
| TAB (args
[1], args
[2], args
[3]));
1232 case INDEX_op_shl_i32
:
1233 if (const_args
[2]) {
1235 tcg_out32 (s
, (RLWINM
1244 tcg_out_mov (s
, args
[0], args
[1]);
1247 tcg_out32 (s
, SLW
| SAB (args
[1], args
[0], args
[2]));
1249 case INDEX_op_shr_i32
:
1250 if (const_args
[2]) {
1252 tcg_out32 (s
, (RLWINM
1261 tcg_out_mov (s
, args
[0], args
[1]);
1264 tcg_out32 (s
, SRW
| SAB (args
[1], args
[0], args
[2]));
1266 case INDEX_op_sar_i32
:
1268 tcg_out32 (s
, SRAWI
| RS (args
[1]) | RA (args
[0]) | SH (args
[2]));
1270 tcg_out32 (s
, SRAW
| SAB (args
[1], args
[0], args
[2]));
1273 case INDEX_op_add2_i32
:
1274 if (args
[0] == args
[3] || args
[0] == args
[5]) {
1275 tcg_out32 (s
, ADDC
| TAB (0, args
[2], args
[4]));
1276 tcg_out32 (s
, ADDE
| TAB (args
[1], args
[3], args
[5]));
1277 tcg_out_mov (s
, args
[0], 0);
1280 tcg_out32 (s
, ADDC
| TAB (args
[0], args
[2], args
[4]));
1281 tcg_out32 (s
, ADDE
| TAB (args
[1], args
[3], args
[5]));
1284 case INDEX_op_sub2_i32
:
1285 if (args
[0] == args
[3] || args
[0] == args
[5]) {
1286 tcg_out32 (s
, SUBFC
| TAB (0, args
[4], args
[2]));
1287 tcg_out32 (s
, SUBFE
| TAB (args
[1], args
[5], args
[3]));
1288 tcg_out_mov (s
, args
[0], 0);
1291 tcg_out32 (s
, SUBFC
| TAB (args
[0], args
[4], args
[2]));
1292 tcg_out32 (s
, SUBFE
| TAB (args
[1], args
[5], args
[3]));
1296 case INDEX_op_brcond_i32
:
1301 args[3] = r1 is const
1302 args[4] = label_index
1304 tcg_out_brcond (s
, args
[2], args
[0], args
[1], const_args
[1], args
[3]);
1306 case INDEX_op_brcond2_i32
:
1307 tcg_out_brcond2(s
, args
, const_args
);
1310 case INDEX_op_neg_i32
:
1311 tcg_out32 (s
, NEG
| RT (args
[0]) | RA (args
[1]));
1314 case INDEX_op_qemu_ld8u
:
1315 tcg_out_qemu_ld(s
, args
, 0);
1317 case INDEX_op_qemu_ld8s
:
1318 tcg_out_qemu_ld(s
, args
, 0 | 4);
1320 case INDEX_op_qemu_ld16u
:
1321 tcg_out_qemu_ld(s
, args
, 1);
1323 case INDEX_op_qemu_ld16s
:
1324 tcg_out_qemu_ld(s
, args
, 1 | 4);
1326 case INDEX_op_qemu_ld32u
:
1327 tcg_out_qemu_ld(s
, args
, 2);
1329 case INDEX_op_qemu_ld64
:
1330 tcg_out_qemu_ld(s
, args
, 3);
1332 case INDEX_op_qemu_st8
:
1333 tcg_out_qemu_st(s
, args
, 0);
1335 case INDEX_op_qemu_st16
:
1336 tcg_out_qemu_st(s
, args
, 1);
1338 case INDEX_op_qemu_st32
:
1339 tcg_out_qemu_st(s
, args
, 2);
1341 case INDEX_op_qemu_st64
:
1342 tcg_out_qemu_st(s
, args
, 3);
1346 tcg_dump_ops (s
, stderr
);
1351 static const TCGTargetOpDef ppc_op_defs
[] = {
1352 { INDEX_op_exit_tb
, { } },
1353 { INDEX_op_goto_tb
, { } },
1354 { INDEX_op_call
, { "ri" } },
1355 { INDEX_op_jmp
, { "ri" } },
1356 { INDEX_op_br
, { } },
1358 { INDEX_op_mov_i32
, { "r", "r" } },
1359 { INDEX_op_movi_i32
, { "r" } },
1360 { INDEX_op_ld8u_i32
, { "r", "r" } },
1361 { INDEX_op_ld8s_i32
, { "r", "r" } },
1362 { INDEX_op_ld16u_i32
, { "r", "r" } },
1363 { INDEX_op_ld16s_i32
, { "r", "r" } },
1364 { INDEX_op_ld_i32
, { "r", "r" } },
1365 { INDEX_op_st8_i32
, { "r", "r" } },
1366 { INDEX_op_st16_i32
, { "r", "r" } },
1367 { INDEX_op_st_i32
, { "r", "r" } },
1369 { INDEX_op_add_i32
, { "r", "r", "ri" } },
1370 { INDEX_op_mul_i32
, { "r", "r", "ri" } },
1371 { INDEX_op_div_i32
, { "r", "r", "r" } },
1372 { INDEX_op_divu_i32
, { "r", "r", "r" } },
1373 { INDEX_op_rem_i32
, { "r", "r", "r" } },
1374 { INDEX_op_remu_i32
, { "r", "r", "r" } },
1375 { INDEX_op_mulu2_i32
, { "r", "r", "r", "r" } },
1376 { INDEX_op_sub_i32
, { "r", "r", "ri" } },
1377 { INDEX_op_and_i32
, { "r", "r", "ri" } },
1378 { INDEX_op_or_i32
, { "r", "r", "ri" } },
1379 { INDEX_op_xor_i32
, { "r", "r", "ri" } },
1381 { INDEX_op_shl_i32
, { "r", "r", "ri" } },
1382 { INDEX_op_shr_i32
, { "r", "r", "ri" } },
1383 { INDEX_op_sar_i32
, { "r", "r", "ri" } },
1385 { INDEX_op_brcond_i32
, { "r", "ri" } },
1387 { INDEX_op_add2_i32
, { "r", "r", "r", "r", "r", "r" } },
1388 { INDEX_op_sub2_i32
, { "r", "r", "r", "r", "r", "r" } },
1389 { INDEX_op_brcond2_i32
, { "r", "r", "r", "r" } },
1391 { INDEX_op_neg_i32
, { "r", "r" } },
1393 #if TARGET_LONG_BITS == 32
1394 { INDEX_op_qemu_ld8u
, { "r", "L" } },
1395 { INDEX_op_qemu_ld8s
, { "r", "L" } },
1396 { INDEX_op_qemu_ld16u
, { "r", "L" } },
1397 { INDEX_op_qemu_ld16s
, { "r", "L" } },
1398 { INDEX_op_qemu_ld32u
, { "r", "L" } },
1399 { INDEX_op_qemu_ld32s
, { "r", "L" } },
1400 { INDEX_op_qemu_ld64
, { "r", "r", "L" } },
1402 { INDEX_op_qemu_st8
, { "K", "K" } },
1403 { INDEX_op_qemu_st16
, { "K", "K" } },
1404 { INDEX_op_qemu_st32
, { "K", "K" } },
1405 { INDEX_op_qemu_st64
, { "M", "M", "M" } },
1407 { INDEX_op_qemu_ld8u
, { "r", "L", "L" } },
1408 { INDEX_op_qemu_ld8s
, { "r", "L", "L" } },
1409 { INDEX_op_qemu_ld16u
, { "r", "L", "L" } },
1410 { INDEX_op_qemu_ld16s
, { "r", "L", "L" } },
1411 { INDEX_op_qemu_ld32u
, { "r", "L", "L" } },
1412 { INDEX_op_qemu_ld32s
, { "r", "L", "L" } },
1413 { INDEX_op_qemu_ld64
, { "r", "L", "L", "L" } },
1415 { INDEX_op_qemu_st8
, { "K", "K", "K" } },
1416 { INDEX_op_qemu_st16
, { "K", "K", "K" } },
1417 { INDEX_op_qemu_st32
, { "K", "K", "K" } },
1418 { INDEX_op_qemu_st64
, { "M", "M", "M", "M" } },
1424 void tcg_target_init(TCGContext
*s
)
1426 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I32
], 0, 0xffffffff);
1427 tcg_regset_set32(tcg_target_call_clobber_regs
, 0,
1436 (1 << TCG_REG_R10
) |
1437 (1 << TCG_REG_R11
) |
1441 tcg_regset_clear(s
->reserved_regs
);
1442 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R0
);
1443 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R1
);
1444 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R2
);
1446 tcg_add_target_add_op_defs(ppc_op_defs
);