2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 static uint8_t *tb_ret_addr
;
28 #define LINKAGE_AREA_SIZE 12
29 #define BACK_CHAIN_OFFSET 8
31 #define LINKAGE_AREA_SIZE 8
32 #define BACK_CHAIN_OFFSET 4
36 #if TARGET_PHYS_ADDR_BITS <= 32
37 #define ADDEND_OFFSET 0
39 #define ADDEND_OFFSET 4
42 static const char * const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
77 static const int tcg_target_reg_alloc_order
[] = {
117 static const int tcg_target_call_iarg_regs
[] = {
128 static const int tcg_target_call_oarg_regs
[2] = {
133 static const int tcg_target_callee_save_regs
[] = {
154 static uint32_t reloc_pc24_val (void *pc
, tcg_target_long target
)
156 tcg_target_long disp
;
158 disp
= target
- (tcg_target_long
) pc
;
159 if ((disp
<< 6) >> 6 != disp
)
162 return disp
& 0x3fffffc;
165 static void reloc_pc24 (void *pc
, tcg_target_long target
)
167 *(uint32_t *) pc
= (*(uint32_t *) pc
& ~0x3fffffc)
168 | reloc_pc24_val (pc
, target
);
171 static uint16_t reloc_pc14_val (void *pc
, tcg_target_long target
)
173 tcg_target_long disp
;
175 disp
= target
- (tcg_target_long
) pc
;
176 if (disp
!= (int16_t) disp
)
179 return disp
& 0xfffc;
182 static void reloc_pc14 (void *pc
, tcg_target_long target
)
184 *(uint32_t *) pc
= (*(uint32_t *) pc
& ~0xfffc)
185 | reloc_pc14_val (pc
, target
);
188 static void patch_reloc(uint8_t *code_ptr
, int type
,
189 tcg_target_long value
, tcg_target_long addend
)
194 reloc_pc14 (code_ptr
, value
);
197 reloc_pc24 (code_ptr
, value
);
204 /* maximum number of register used for input function arguments */
205 static int tcg_target_get_call_iarg_regs_count(int flags
)
207 return sizeof (tcg_target_call_iarg_regs
) / sizeof (tcg_target_call_iarg_regs
[0]);
210 /* parse target specific constraints */
211 static int target_parse_constraint(TCGArgConstraint
*ct
, const char **pct_str
)
217 case 'A': case 'B': case 'C': case 'D':
218 ct
->ct
|= TCG_CT_REG
;
219 tcg_regset_set_reg(ct
->u
.regs
, 3 + ct_str
[0] - 'A');
222 ct
->ct
|= TCG_CT_REG
;
223 tcg_regset_set32(ct
->u
.regs
, 0, 0xffffffff);
225 case 'L': /* qemu_ld constraint */
226 ct
->ct
|= TCG_CT_REG
;
227 tcg_regset_set32(ct
->u
.regs
, 0, 0xffffffff);
228 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R3
);
229 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R4
);
231 case 'K': /* qemu_st[8..32] constraint */
232 ct
->ct
|= TCG_CT_REG
;
233 tcg_regset_set32(ct
->u
.regs
, 0, 0xffffffff);
234 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R3
);
235 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R4
);
236 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R5
);
237 #if TARGET_LONG_BITS == 64
238 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R6
);
241 case 'M': /* qemu_st64 constraint */
242 ct
->ct
|= TCG_CT_REG
;
243 tcg_regset_set32(ct
->u
.regs
, 0, 0xffffffff);
244 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R3
);
245 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R4
);
246 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R5
);
247 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R6
);
248 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R7
);
258 /* test if a constant matches the constraint */
259 static int tcg_target_const_match(tcg_target_long val
,
260 const TCGArgConstraint
*arg_ct
)
265 if (ct
& TCG_CT_CONST
)
270 #define OPCD(opc) ((opc)<<26)
271 #define XO31(opc) (OPCD(31)|((opc)<<1))
272 #define XO19(opc) (OPCD(19)|((opc)<<1))
284 #define ADDI OPCD(14)
285 #define ADDIS OPCD(15)
287 #define ORIS OPCD(25)
288 #define XORI OPCD(26)
289 #define XORIS OPCD(27)
290 #define ANDI OPCD(28)
291 #define ANDIS OPCD(29)
292 #define MULLI OPCD( 7)
293 #define CMPLI OPCD(10)
294 #define CMPI OPCD(11)
296 #define LWZU OPCD(33)
297 #define STWU OPCD(37)
299 #define RLWINM OPCD(21)
301 #define BCLR XO19( 16)
302 #define BCCTR XO19(528)
303 #define CRAND XO19(257)
304 #define CRANDC XO19(129)
305 #define CRNAND XO19(225)
306 #define CROR XO19(449)
308 #define EXTSB XO31(954)
309 #define EXTSH XO31(922)
310 #define ADD XO31(266)
311 #define ADDE XO31(138)
312 #define ADDC XO31( 10)
313 #define AND XO31( 28)
314 #define SUBF XO31( 40)
315 #define SUBFC XO31( 8)
316 #define SUBFE XO31(136)
318 #define XOR XO31(316)
319 #define MULLW XO31(235)
320 #define MULHWU XO31( 11)
321 #define DIVW XO31(491)
322 #define DIVWU XO31(459)
324 #define CMPL XO31( 32)
325 #define LHBRX XO31(790)
326 #define LWBRX XO31(534)
327 #define STHBRX XO31(918)
328 #define STWBRX XO31(662)
329 #define MFSPR XO31(339)
330 #define MTSPR XO31(467)
331 #define SRAWI XO31(824)
332 #define NEG XO31(104)
334 #define LBZX XO31( 87)
335 #define LHZX XO31(276)
336 #define LHAX XO31(343)
337 #define LWZX XO31( 23)
338 #define STBX XO31(215)
339 #define STHX XO31(407)
340 #define STWX XO31(151)
342 #define SPR(a,b) ((((a)<<5)|(b))<<11)
344 #define CTR SPR(9, 0)
346 #define SLW XO31( 24)
347 #define SRW XO31(536)
348 #define SRAW XO31(792)
351 #define STMW OPCD(47)
354 #define TRAP (TW | TO (31))
356 #define RT(r) ((r)<<21)
357 #define RS(r) ((r)<<21)
358 #define RA(r) ((r)<<16)
359 #define RB(r) ((r)<<11)
360 #define TO(t) ((t)<<21)
361 #define SH(s) ((s)<<11)
362 #define MB(b) ((b)<<6)
363 #define ME(e) ((e)<<1)
364 #define BO(o) ((o)<<21)
368 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
369 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
371 #define BF(n) ((n)<<23)
372 #define BI(n, c) (((c)+((n)*4))<<16)
373 #define BT(n, c) (((c)+((n)*4))<<21)
374 #define BA(n, c) (((c)+((n)*4))<<16)
375 #define BB(n, c) (((c)+((n)*4))<<11)
377 #define BO_COND_TRUE BO (12)
378 #define BO_COND_FALSE BO (4)
379 #define BO_ALWAYS BO (20)
388 static const uint32_t tcg_to_bc
[10] = {
389 [TCG_COND_EQ
] = BC
| BI (7, CR_EQ
) | BO_COND_TRUE
,
390 [TCG_COND_NE
] = BC
| BI (7, CR_EQ
) | BO_COND_FALSE
,
391 [TCG_COND_LT
] = BC
| BI (7, CR_LT
) | BO_COND_TRUE
,
392 [TCG_COND_GE
] = BC
| BI (7, CR_LT
) | BO_COND_FALSE
,
393 [TCG_COND_LE
] = BC
| BI (7, CR_GT
) | BO_COND_FALSE
,
394 [TCG_COND_GT
] = BC
| BI (7, CR_GT
) | BO_COND_TRUE
,
395 [TCG_COND_LTU
] = BC
| BI (7, CR_LT
) | BO_COND_TRUE
,
396 [TCG_COND_GEU
] = BC
| BI (7, CR_LT
) | BO_COND_FALSE
,
397 [TCG_COND_LEU
] = BC
| BI (7, CR_GT
) | BO_COND_FALSE
,
398 [TCG_COND_GTU
] = BC
| BI (7, CR_GT
) | BO_COND_TRUE
,
401 static void tcg_out_mov(TCGContext
*s
, int ret
, int arg
)
403 tcg_out32 (s
, OR
| SAB (arg
, ret
, arg
));
406 static void tcg_out_movi(TCGContext
*s
, TCGType type
,
407 int ret
, tcg_target_long arg
)
409 if (arg
== (int16_t) arg
)
410 tcg_out32 (s
, ADDI
| RT (ret
) | RA (0) | (arg
& 0xffff));
412 tcg_out32 (s
, ADDIS
| RT (ret
) | RA (0) | ((arg
>> 16) & 0xffff));
414 tcg_out32 (s
, ORI
| RS (ret
) | RA (ret
) | (arg
& 0xffff));
418 static void tcg_out_ldst (TCGContext
*s
, int ret
, int addr
,
419 int offset
, int op1
, int op2
)
421 if (offset
== (int16_t) offset
)
422 tcg_out32 (s
, op1
| RT (ret
) | RA (addr
) | (offset
& 0xffff));
424 tcg_out_movi (s
, TCG_TYPE_I32
, 0, offset
);
425 tcg_out32 (s
, op2
| RT (ret
) | RA (addr
) | RB (0));
429 static void tcg_out_b (TCGContext
*s
, int mask
, tcg_target_long target
)
431 tcg_target_long disp
;
433 disp
= target
- (tcg_target_long
) s
->code_ptr
;
434 if ((disp
<< 6) >> 6 == disp
)
435 tcg_out32 (s
, B
| (disp
& 0x3fffffc) | mask
);
437 tcg_out_movi (s
, TCG_TYPE_I32
, 0, (tcg_target_long
) target
);
438 tcg_out32 (s
, MTSPR
| RS (0) | CTR
);
439 tcg_out32 (s
, BCCTR
| BO_ALWAYS
| mask
);
443 #if defined(CONFIG_SOFTMMU)
444 extern void __ldb_mmu(void);
445 extern void __ldw_mmu(void);
446 extern void __ldl_mmu(void);
447 extern void __ldq_mmu(void);
449 extern void __stb_mmu(void);
450 extern void __stw_mmu(void);
451 extern void __stl_mmu(void);
452 extern void __stq_mmu(void);
454 static void *qemu_ld_helpers
[4] = {
461 static void *qemu_st_helpers
[4] = {
469 static void tcg_out_qemu_ld (TCGContext
*s
, const TCGArg
*args
, int opc
)
471 int addr_reg
, data_reg
, data_reg2
, r0
, mem_index
, s_bits
, bswap
;
472 #ifdef CONFIG_SOFTMMU
474 void *label1_ptr
, *label2_ptr
;
476 #if TARGET_LONG_BITS == 64
486 #if TARGET_LONG_BITS == 64
492 #ifdef CONFIG_SOFTMMU
497 tcg_out32 (s
, (RLWINM
500 | SH (32 - (TARGET_PAGE_BITS
- CPU_TLB_ENTRY_BITS
))
501 | MB (32 - (CPU_TLB_BITS
+ CPU_TLB_ENTRY_BITS
))
502 | ME (31 - CPU_TLB_ENTRY_BITS
)
505 tcg_out32 (s
, ADD
| RT (r0
) | RA (r0
) | RB (TCG_AREG0
));
509 | offsetof (CPUState
, tlb_table
[mem_index
][0].addr_read
)
512 tcg_out32 (s
, (RLWINM
516 | MB ((32 - s_bits
) & 31)
517 | ME (31 - TARGET_PAGE_BITS
)
521 tcg_out32 (s
, CMP
| BF (7) | RA (r2
) | RB (r1
));
522 #if TARGET_LONG_BITS == 64
523 tcg_out32 (s
, LWZ
| RT (r1
) | RA (r0
) | 4);
524 tcg_out32 (s
, CMP
| BF (6) | RA (addr_reg2
) | RB (r1
));
525 tcg_out32 (s
, CRAND
| BT (7, CR_EQ
) | BA (6, CR_EQ
) | BB (7, CR_EQ
));
528 label1_ptr
= s
->code_ptr
;
530 tcg_out32 (s
, BC
| BI (7, CR_EQ
) | BO_COND_TRUE
);
534 #if TARGET_LONG_BITS == 32
535 tcg_out_mov (s
, 3, addr_reg
);
536 tcg_out_movi (s
, TCG_TYPE_I32
, 4, mem_index
);
538 tcg_out_mov (s
, 3, addr_reg2
);
539 tcg_out_mov (s
, 4, addr_reg
);
540 tcg_out_movi (s
, TCG_TYPE_I32
, 5, mem_index
);
543 tcg_out_b (s
, LK
, (tcg_target_long
) qemu_ld_helpers
[s_bits
]);
546 tcg_out32 (s
, EXTSB
| RA (data_reg
) | RS (3));
549 tcg_out32 (s
, EXTSH
| RA (data_reg
) | RS (3));
555 tcg_out_mov (s
, data_reg
, 3);
559 if (data_reg2
== 4) {
560 tcg_out_mov (s
, 0, 4);
561 tcg_out_mov (s
, 4, 3);
562 tcg_out_mov (s
, 3, 0);
565 tcg_out_mov (s
, data_reg2
, 3);
566 tcg_out_mov (s
, 3, 4);
570 if (data_reg
!= 4) tcg_out_mov (s
, data_reg
, 4);
571 if (data_reg2
!= 3) tcg_out_mov (s
, data_reg2
, 3);
575 label2_ptr
= s
->code_ptr
;
578 /* label1: fast path */
580 reloc_pc14 (label1_ptr
, (tcg_target_long
) s
->code_ptr
);
583 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
587 | (ADDEND_OFFSET
+ offsetof (CPUTLBEntry
, addend
)
588 - offsetof (CPUTLBEntry
, addr_read
))
590 /* r0 = env->tlb_table[mem_index][index].addend */
591 tcg_out32 (s
, ADD
| RT (r0
) | RA (r0
) | RB (addr_reg
));
592 /* r0 = env->tlb_table[mem_index][index].addend + addr */
594 #else /* !CONFIG_SOFTMMU */
598 #ifdef TARGET_WORDS_BIGENDIAN
606 tcg_out32 (s
, LBZ
| RT (data_reg
) | RA (r0
));
609 tcg_out32 (s
, LBZ
| RT (data_reg
) | RA (r0
));
610 tcg_out32 (s
, EXTSB
| RA (data_reg
) | RS (data_reg
));
613 if (bswap
) tcg_out32 (s
, LHBRX
| RT (data_reg
) | RB (r0
));
614 else tcg_out32 (s
, LHZ
| RT (data_reg
) | RA (r0
));
618 tcg_out32 (s
, LHBRX
| RT (data_reg
) | RB (r0
));
619 tcg_out32 (s
, EXTSH
| RA (data_reg
) | RS (data_reg
));
621 else tcg_out32 (s
, LHA
| RT (data_reg
) | RA (r0
));
624 if (bswap
) tcg_out32 (s
, LWBRX
| RT (data_reg
) | RB (r0
));
625 else tcg_out32 (s
, LWZ
| RT (data_reg
)| RA (r0
));
629 if (r0
== data_reg
) {
630 tcg_out32 (s
, LWBRX
| RT (0) | RB (r0
));
631 tcg_out32 (s
, ADDI
| RT (r0
) | RA (r0
) | 4);
632 tcg_out32 (s
, LWBRX
| RT (data_reg2
) | RB (r0
));
633 tcg_out_mov (s
, data_reg
, 0);
636 tcg_out32 (s
, LWBRX
| RT (data_reg
) | RB (r0
));
637 tcg_out32 (s
, ADDI
| RT (r0
) | RA (r0
) | 4);
638 tcg_out32 (s
, LWBRX
| RT (data_reg2
) | RB (r0
));
642 if (r0
== data_reg2
) {
643 tcg_out32 (s
, LWZ
| RT (0) | RA (r0
));
644 tcg_out32 (s
, LWZ
| RT (data_reg
) | RA (r0
) | 4);
645 tcg_out_mov (s
, data_reg2
, 0);
648 tcg_out32 (s
, LWZ
| RT (data_reg2
) | RA (r0
));
649 tcg_out32 (s
, LWZ
| RT (data_reg
) | RA (r0
) | 4);
655 #ifdef CONFIG_SOFTMMU
656 reloc_pc24 (label2_ptr
, (tcg_target_long
) s
->code_ptr
);
660 static void tcg_out_qemu_st (TCGContext
*s
, const TCGArg
*args
, int opc
)
662 int addr_reg
, r0
, r1
, data_reg
, data_reg2
, mem_index
, bswap
;
663 #ifdef CONFIG_SOFTMMU
665 void *label1_ptr
, *label2_ptr
;
667 #if TARGET_LONG_BITS == 64
677 #if TARGET_LONG_BITS == 64
682 #ifdef CONFIG_SOFTMMU
687 tcg_out32 (s
, (RLWINM
690 | SH (32 - (TARGET_PAGE_BITS
- CPU_TLB_ENTRY_BITS
))
691 | MB (32 - (CPU_TLB_ENTRY_BITS
+ CPU_TLB_BITS
))
692 | ME (31 - CPU_TLB_ENTRY_BITS
)
695 tcg_out32 (s
, ADD
| RT (r0
) | RA (r0
) | RB (TCG_AREG0
));
699 | offsetof (CPUState
, tlb_table
[mem_index
][0].addr_write
)
702 tcg_out32 (s
, (RLWINM
706 | MB ((32 - opc
) & 31)
707 | ME (31 - TARGET_PAGE_BITS
)
711 tcg_out32 (s
, CMP
| (7 << 23) | RA (r2
) | RB (r1
));
712 #if TARGET_LONG_BITS == 64
713 tcg_out32 (s
, LWZ
| RT (r1
) | RA (r0
) | 4);
714 tcg_out32 (s
, CMP
| BF (6) | RA (addr_reg2
) | RB (r1
));
715 tcg_out32 (s
, CRAND
| BT (7, CR_EQ
) | BA (6, CR_EQ
) | BB (7, CR_EQ
));
718 label1_ptr
= s
->code_ptr
;
720 tcg_out32 (s
, BC
| BI (7, CR_EQ
) | BO_COND_TRUE
);
724 #if TARGET_LONG_BITS == 32
725 tcg_out_mov (s
, 3, addr_reg
);
728 tcg_out_mov (s
, 3, addr_reg2
);
729 tcg_out_mov (s
, 4, addr_reg
);
730 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
739 tcg_out32 (s
, (RLWINM
747 tcg_out32 (s
, (RLWINM
755 tcg_out_mov (s
, ir
, data_reg
);
758 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
761 tcg_out_mov (s
, ir
++, data_reg2
);
762 tcg_out_mov (s
, ir
, data_reg
);
767 tcg_out_movi (s
, TCG_TYPE_I32
, ir
, mem_index
);
768 tcg_out_b (s
, LK
, (tcg_target_long
) qemu_st_helpers
[opc
]);
769 label2_ptr
= s
->code_ptr
;
772 /* label1: fast path */
774 reloc_pc14 (label1_ptr
, (tcg_target_long
) s
->code_ptr
);
780 | (ADDEND_OFFSET
+ offsetof (CPUTLBEntry
, addend
)
781 - offsetof (CPUTLBEntry
, addr_write
))
783 /* r0 = env->tlb_table[mem_index][index].addend */
784 tcg_out32 (s
, ADD
| RT (r0
) | RA (r0
) | RB (addr_reg
));
785 /* r0 = env->tlb_table[mem_index][index].addend + addr */
787 #else /* !CONFIG_SOFTMMU */
792 #ifdef TARGET_WORDS_BIGENDIAN
799 tcg_out32 (s
, STB
| RS (data_reg
) | RA (r0
));
802 if (bswap
) tcg_out32 (s
, STHBRX
| RS (data_reg
) | RA (0) | RB (r0
));
803 else tcg_out32 (s
, STH
| RS (data_reg
) | RA (r0
));
806 if (bswap
) tcg_out32 (s
, STWBRX
| RS (data_reg
) | RA (0) | RB (r0
));
807 else tcg_out32 (s
, STW
| RS (data_reg
) | RA (r0
));
811 tcg_out32 (s
, ADDI
| RT (r1
) | RA (r0
) | 4);
812 tcg_out32 (s
, STWBRX
| RS (data_reg
) | RA (0) | RB (r0
));
813 tcg_out32 (s
, STWBRX
| RS (data_reg2
) | RA (0) | RB (r1
));
816 tcg_out32 (s
, STW
| RS (data_reg2
) | RA (r0
));
817 tcg_out32 (s
, STW
| RS (data_reg
) | RA (r0
) | 4);
822 #ifdef CONFIG_SOFTMMU
823 reloc_pc24 (label2_ptr
, (tcg_target_long
) s
->code_ptr
);
827 void tcg_target_qemu_prologue (TCGContext
*s
)
833 + TCG_STATIC_CALL_ARGS_SIZE
834 + ARRAY_SIZE (tcg_target_callee_save_regs
) * 4
836 frame_size
= (frame_size
+ 15) & ~15;
838 tcg_out32 (s
, MFSPR
| RT (0) | LR
);
839 tcg_out32 (s
, STWU
| RS (1) | RA (1) | (-frame_size
& 0xffff));
840 for (i
= 0; i
< ARRAY_SIZE (tcg_target_callee_save_regs
); ++i
)
842 | RS (tcg_target_callee_save_regs
[i
])
844 | (i
* 4 + LINKAGE_AREA_SIZE
+ TCG_STATIC_CALL_ARGS_SIZE
)
847 tcg_out32 (s
, STW
| RS (0) | RA (1) | (frame_size
+ BACK_CHAIN_OFFSET
));
849 tcg_out32 (s
, MTSPR
| RS (3) | CTR
);
850 tcg_out32 (s
, BCCTR
| BO_ALWAYS
);
851 tb_ret_addr
= s
->code_ptr
;
853 for (i
= 0; i
< ARRAY_SIZE (tcg_target_callee_save_regs
); ++i
)
855 | RT (tcg_target_callee_save_regs
[i
])
857 | (i
* 4 + LINKAGE_AREA_SIZE
+ TCG_STATIC_CALL_ARGS_SIZE
)
860 tcg_out32 (s
, LWZ
| RT (0) | RA (1) | (frame_size
+ BACK_CHAIN_OFFSET
));
861 tcg_out32 (s
, MTSPR
| RS (0) | LR
);
862 tcg_out32 (s
, ADDI
| RT (1) | RA (1) | frame_size
);
863 tcg_out32 (s
, BCLR
| BO_ALWAYS
);
866 static void tcg_out_ld (TCGContext
*s
, TCGType type
, int ret
, int arg1
,
867 tcg_target_long arg2
)
869 tcg_out_ldst (s
, ret
, arg1
, arg2
, LWZ
, LWZX
);
872 static void tcg_out_st (TCGContext
*s
, TCGType type
, int arg
, int arg1
,
873 tcg_target_long arg2
)
875 tcg_out_ldst (s
, arg
, arg1
, arg2
, STW
, STWX
);
878 static void ppc_addi (TCGContext
*s
, int rt
, int ra
, tcg_target_long si
)
883 if (si
== (int16_t) si
)
884 tcg_out32 (s
, ADDI
| RT (rt
) | RA (ra
) | (si
& 0xffff));
886 uint16_t h
= ((si
>> 16) & 0xffff) + ((uint16_t) si
>> 15);
887 tcg_out32 (s
, ADDIS
| RT (rt
) | RA (ra
) | h
);
888 tcg_out32 (s
, ADDI
| RT (rt
) | RA (rt
) | (si
& 0xffff));
892 static void tcg_out_addi(TCGContext
*s
, int reg
, tcg_target_long val
)
894 ppc_addi (s
, reg
, reg
, val
);
897 static void tcg_out_cmp (TCGContext
*s
, int cond
, TCGArg arg1
, TCGArg arg2
,
898 int const_arg2
, int cr
)
907 if ((int16_t) arg2
== arg2
) {
912 else if ((uint16_t) arg2
== arg2
) {
927 if ((int16_t) arg2
== arg2
) {
942 if ((uint16_t) arg2
== arg2
) {
958 tcg_out32 (s
, op
| RA (arg1
) | (arg2
& 0xffff));
961 tcg_out_movi (s
, TCG_TYPE_I32
, 0, arg2
);
962 tcg_out32 (s
, op
| RA (arg1
) | RB (0));
965 tcg_out32 (s
, op
| RA (arg1
) | RB (arg2
));
970 static void tcg_out_bc (TCGContext
*s
, int bc
, int label_index
)
972 TCGLabel
*l
= &s
->labels
[label_index
];
975 tcg_out32 (s
, bc
| reloc_pc14_val (s
->code_ptr
, l
->u
.value
));
977 uint16_t val
= *(uint16_t *) &s
->code_ptr
[2];
979 /* Thanks to Andrzej Zaborowski */
980 tcg_out32 (s
, bc
| (val
& 0xfffc));
981 tcg_out_reloc (s
, s
->code_ptr
- 4, R_PPC_REL14
, label_index
, 0);
985 static void tcg_out_brcond (TCGContext
*s
, int cond
,
986 TCGArg arg1
, TCGArg arg2
, int const_arg2
,
989 tcg_out_cmp (s
, cond
, arg1
, arg2
, const_arg2
, 7);
990 tcg_out_bc (s
, tcg_to_bc
[cond
], label_index
);
993 /* XXX: we implement it at the target level to avoid having to
994 handle cross basic blocks temporaries */
995 static void tcg_out_brcond2 (TCGContext
*s
, const TCGArg
*args
,
996 const int *const_args
)
998 int cond
= args
[4], label_index
= args
[5], op
;
999 struct { int bit1
; int bit2
; int cond2
; } bits
[] = {
1000 [TCG_COND_LT
] = { CR_LT
, CR_LT
, TCG_COND_LT
},
1001 [TCG_COND_LE
] = { CR_LT
, CR_GT
, TCG_COND_LT
},
1002 [TCG_COND_GT
] = { CR_GT
, CR_GT
, TCG_COND_GT
},
1003 [TCG_COND_GE
] = { CR_GT
, CR_LT
, TCG_COND_GT
},
1004 [TCG_COND_LTU
] = { CR_LT
, CR_LT
, TCG_COND_LTU
},
1005 [TCG_COND_LEU
] = { CR_LT
, CR_GT
, TCG_COND_LTU
},
1006 [TCG_COND_GTU
] = { CR_GT
, CR_GT
, TCG_COND_GTU
},
1007 [TCG_COND_GEU
] = { CR_GT
, CR_LT
, TCG_COND_GTU
},
1008 }, *b
= &bits
[cond
];
1013 op
= (cond
== TCG_COND_EQ
) ? CRAND
: CRNAND
;
1014 tcg_out_cmp (s
, cond
, args
[0], args
[2], const_args
[2], 6);
1015 tcg_out_cmp (s
, cond
, args
[1], args
[3], const_args
[3], 7);
1016 tcg_out32 (s
, op
| BT (7, CR_EQ
) | BA (6, CR_EQ
) | BB (7, CR_EQ
));
1026 op
= (b
->bit1
!= b
->bit2
) ? CRANDC
: CRAND
;
1027 tcg_out_cmp (s
, b
->cond2
, args
[1], args
[3], const_args
[3], 5);
1028 tcg_out_cmp (s
, TCG_COND_EQ
, args
[1], args
[3], const_args
[3], 6);
1029 tcg_out_cmp (s
, cond
, args
[0], args
[2], const_args
[2], 7);
1030 tcg_out32 (s
, op
| BT (7, CR_EQ
) | BA (6, CR_EQ
) | BB (7, b
->bit2
));
1031 tcg_out32 (s
, CROR
| BT (7, CR_EQ
) | BA (5, b
->bit1
) | BB (7, CR_EQ
));
1037 tcg_out_bc (s
, (BC
| BI (7, CR_EQ
) | BO_COND_TRUE
), label_index
);
1040 void ppc_tb_set_jmp_target (unsigned long jmp_addr
, unsigned long addr
)
1043 long disp
= addr
- jmp_addr
;
1044 unsigned long patch_size
;
1046 ptr
= (uint32_t *)jmp_addr
;
1048 if ((disp
<< 6) >> 6 != disp
) {
1049 ptr
[0] = 0x3c000000 | (addr
>> 16); /* lis 0,addr@ha */
1050 ptr
[1] = 0x60000000 | (addr
& 0xffff); /* la 0,addr@l(0) */
1051 ptr
[2] = 0x7c0903a6; /* mtctr 0 */
1052 ptr
[3] = 0x4e800420; /* brctr */
1055 /* patch the branch destination */
1057 *ptr
= 0x48000000 | (disp
& 0x03fffffc); /* b disp */
1060 ptr
[0] = 0x60000000; /* nop */
1061 ptr
[1] = 0x60000000;
1062 ptr
[2] = 0x60000000;
1063 ptr
[3] = 0x60000000;
1068 flush_icache_range(jmp_addr
, jmp_addr
+ patch_size
);
1071 static void tcg_out_op(TCGContext
*s
, int opc
, const TCGArg
*args
,
1072 const int *const_args
)
1075 case INDEX_op_exit_tb
:
1076 tcg_out_movi (s
, TCG_TYPE_I32
, TCG_REG_R3
, args
[0]);
1077 tcg_out_b (s
, 0, (tcg_target_long
) tb_ret_addr
);
1079 case INDEX_op_goto_tb
:
1080 if (s
->tb_jmp_offset
) {
1081 /* direct jump method */
1083 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1089 s
->tb_next_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1093 TCGLabel
*l
= &s
->labels
[args
[0]];
1096 tcg_out_b (s
, 0, l
->u
.value
);
1099 uint32_t val
= *(uint32_t *) s
->code_ptr
;
1101 /* Thanks to Andrzej Zaborowski */
1102 tcg_out32 (s
, B
| (val
& 0x3fffffc));
1103 tcg_out_reloc (s
, s
->code_ptr
- 4, R_PPC_REL24
, args
[0], 0);
1108 if (const_args
[0]) {
1109 tcg_out_b (s
, LK
, args
[0]);
1112 tcg_out32 (s
, MTSPR
| RS (args
[0]) | LR
);
1113 tcg_out32 (s
, BCLR
| BO_ALWAYS
| LK
);
1117 if (const_args
[0]) {
1118 tcg_out_b (s
, 0, args
[0]);
1121 tcg_out32 (s
, MTSPR
| RS (args
[0]) | CTR
);
1122 tcg_out32 (s
, BCCTR
| BO_ALWAYS
);
1125 case INDEX_op_movi_i32
:
1126 tcg_out_movi(s
, TCG_TYPE_I32
, args
[0], args
[1]);
1128 case INDEX_op_ld8u_i32
:
1129 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LBZ
, LBZX
);
1131 case INDEX_op_ld8s_i32
:
1132 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LBZ
, LBZX
);
1133 tcg_out32 (s
, EXTSB
| RS (args
[0]) | RA (args
[0]));
1135 case INDEX_op_ld16u_i32
:
1136 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LHZ
, LHZX
);
1138 case INDEX_op_ld16s_i32
:
1139 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LHA
, LHAX
);
1141 case INDEX_op_ld_i32
:
1142 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LWZ
, LWZX
);
1144 case INDEX_op_st8_i32
:
1145 tcg_out_ldst (s
, args
[0], args
[1], args
[2], STB
, STBX
);
1147 case INDEX_op_st16_i32
:
1148 tcg_out_ldst (s
, args
[0], args
[1], args
[2], STH
, STHX
);
1150 case INDEX_op_st_i32
:
1151 tcg_out_ldst (s
, args
[0], args
[1], args
[2], STW
, STWX
);
1154 case INDEX_op_add_i32
:
1156 ppc_addi (s
, args
[0], args
[1], args
[2]);
1158 tcg_out32 (s
, ADD
| TAB (args
[0], args
[1], args
[2]));
1160 case INDEX_op_sub_i32
:
1162 ppc_addi (s
, args
[0], args
[1], -args
[2]);
1164 tcg_out32 (s
, SUBF
| TAB (args
[0], args
[2], args
[1]));
1167 case INDEX_op_and_i32
:
1168 if (const_args
[2]) {
1169 if ((args
[2] & 0xffff) == args
[2])
1170 tcg_out32 (s
, ANDI
| RS (args
[1]) | RA (args
[0]) | args
[2]);
1171 else if ((args
[2] & 0xffff0000) == args
[2])
1172 tcg_out32 (s
, ANDIS
| RS (args
[1]) | RA (args
[0])
1173 | ((args
[2] >> 16) & 0xffff));
1175 tcg_out_movi (s
, TCG_TYPE_I32
, 0, args
[2]);
1176 tcg_out32 (s
, AND
| SAB (args
[1], args
[0], 0));
1180 tcg_out32 (s
, AND
| SAB (args
[1], args
[0], args
[2]));
1182 case INDEX_op_or_i32
:
1183 if (const_args
[2]) {
1184 if (args
[2] & 0xffff) {
1185 tcg_out32 (s
, ORI
| RS (args
[1]) | RA (args
[0])
1186 | (args
[2] & 0xffff));
1188 tcg_out32 (s
, ORIS
| RS (args
[0]) | RA (args
[0])
1189 | ((args
[2] >> 16) & 0xffff));
1192 tcg_out32 (s
, ORIS
| RS (args
[1]) | RA (args
[0])
1193 | ((args
[2] >> 16) & 0xffff));
1197 tcg_out32 (s
, OR
| SAB (args
[1], args
[0], args
[2]));
1199 case INDEX_op_xor_i32
:
1200 if (const_args
[2]) {
1201 if ((args
[2] & 0xffff) == args
[2])
1202 tcg_out32 (s
, XORI
| RS (args
[1]) | RA (args
[0])
1203 | (args
[2] & 0xffff));
1204 else if ((args
[2] & 0xffff0000) == args
[2])
1205 tcg_out32 (s
, XORIS
| RS (args
[1]) | RA (args
[0])
1206 | ((args
[2] >> 16) & 0xffff));
1208 tcg_out_movi (s
, TCG_TYPE_I32
, 0, args
[2]);
1209 tcg_out32 (s
, XOR
| SAB (args
[1], args
[0], 0));
1213 tcg_out32 (s
, XOR
| SAB (args
[1], args
[0], args
[2]));
1216 case INDEX_op_mul_i32
:
1217 if (const_args
[2]) {
1218 if (args
[2] == (int16_t) args
[2])
1219 tcg_out32 (s
, MULLI
| RT (args
[0]) | RA (args
[1])
1220 | (args
[2] & 0xffff));
1222 tcg_out_movi (s
, TCG_TYPE_I32
, 0, args
[2]);
1223 tcg_out32 (s
, MULLW
| TAB (args
[0], args
[1], 0));
1227 tcg_out32 (s
, MULLW
| TAB (args
[0], args
[1], args
[2]));
1230 case INDEX_op_div_i32
:
1231 tcg_out32 (s
, DIVW
| TAB (args
[0], args
[1], args
[2]));
1234 case INDEX_op_divu_i32
:
1235 tcg_out32 (s
, DIVWU
| TAB (args
[0], args
[1], args
[2]));
1238 case INDEX_op_rem_i32
:
1239 tcg_out32 (s
, DIVW
| TAB (0, args
[1], args
[2]));
1240 tcg_out32 (s
, MULLW
| TAB (0, 0, args
[2]));
1241 tcg_out32 (s
, SUBF
| TAB (args
[0], 0, args
[1]));
1244 case INDEX_op_remu_i32
:
1245 tcg_out32 (s
, DIVWU
| TAB (0, args
[1], args
[2]));
1246 tcg_out32 (s
, MULLW
| TAB (0, 0, args
[2]));
1247 tcg_out32 (s
, SUBF
| TAB (args
[0], 0, args
[1]));
1250 case INDEX_op_mulu2_i32
:
1251 if (args
[0] == args
[2] || args
[0] == args
[3]) {
1252 tcg_out32 (s
, MULLW
| TAB (0, args
[2], args
[3]));
1253 tcg_out32 (s
, MULHWU
| TAB (args
[1], args
[2], args
[3]));
1254 tcg_out_mov (s
, args
[0], 0);
1257 tcg_out32 (s
, MULLW
| TAB (args
[0], args
[2], args
[3]));
1258 tcg_out32 (s
, MULHWU
| TAB (args
[1], args
[2], args
[3]));
1262 case INDEX_op_shl_i32
:
1263 if (const_args
[2]) {
1264 tcg_out32 (s
, (RLWINM
1274 tcg_out32 (s
, SLW
| SAB (args
[1], args
[0], args
[2]));
1276 case INDEX_op_shr_i32
:
1277 if (const_args
[2]) {
1278 tcg_out32 (s
, (RLWINM
1288 tcg_out32 (s
, SRW
| SAB (args
[1], args
[0], args
[2]));
1290 case INDEX_op_sar_i32
:
1292 tcg_out32 (s
, SRAWI
| RS (args
[1]) | RA (args
[0]) | SH (args
[2]));
1294 tcg_out32 (s
, SRAW
| SAB (args
[1], args
[0], args
[2]));
1297 case INDEX_op_add2_i32
:
1298 if (args
[0] == args
[3] || args
[0] == args
[5]) {
1299 tcg_out32 (s
, ADDC
| TAB (0, args
[2], args
[4]));
1300 tcg_out32 (s
, ADDE
| TAB (args
[1], args
[3], args
[5]));
1301 tcg_out_mov (s
, args
[0], 0);
1304 tcg_out32 (s
, ADDC
| TAB (args
[0], args
[2], args
[4]));
1305 tcg_out32 (s
, ADDE
| TAB (args
[1], args
[3], args
[5]));
1308 case INDEX_op_sub2_i32
:
1309 if (args
[0] == args
[3] || args
[0] == args
[5]) {
1310 tcg_out32 (s
, SUBFC
| TAB (0, args
[4], args
[2]));
1311 tcg_out32 (s
, SUBFE
| TAB (args
[1], args
[5], args
[3]));
1312 tcg_out_mov (s
, args
[0], 0);
1315 tcg_out32 (s
, SUBFC
| TAB (args
[0], args
[4], args
[2]));
1316 tcg_out32 (s
, SUBFE
| TAB (args
[1], args
[5], args
[3]));
1320 case INDEX_op_brcond_i32
:
1325 args[3] = r1 is const
1326 args[4] = label_index
1328 tcg_out_brcond (s
, args
[2], args
[0], args
[1], const_args
[1], args
[3]);
1330 case INDEX_op_brcond2_i32
:
1331 tcg_out_brcond2(s
, args
, const_args
);
1334 case INDEX_op_neg_i32
:
1335 tcg_out32 (s
, NEG
| RT (args
[0]) | RA (args
[1]));
1338 case INDEX_op_qemu_ld8u
:
1339 tcg_out_qemu_ld(s
, args
, 0);
1341 case INDEX_op_qemu_ld8s
:
1342 tcg_out_qemu_ld(s
, args
, 0 | 4);
1344 case INDEX_op_qemu_ld16u
:
1345 tcg_out_qemu_ld(s
, args
, 1);
1347 case INDEX_op_qemu_ld16s
:
1348 tcg_out_qemu_ld(s
, args
, 1 | 4);
1350 case INDEX_op_qemu_ld32u
:
1351 tcg_out_qemu_ld(s
, args
, 2);
1353 case INDEX_op_qemu_ld64
:
1354 tcg_out_qemu_ld(s
, args
, 3);
1356 case INDEX_op_qemu_st8
:
1357 tcg_out_qemu_st(s
, args
, 0);
1359 case INDEX_op_qemu_st16
:
1360 tcg_out_qemu_st(s
, args
, 1);
1362 case INDEX_op_qemu_st32
:
1363 tcg_out_qemu_st(s
, args
, 2);
1365 case INDEX_op_qemu_st64
:
1366 tcg_out_qemu_st(s
, args
, 3);
1369 case INDEX_op_ext8s_i32
:
1370 tcg_out32 (s
, EXTSB
| RS (args
[1]) | RA (args
[0]));
1372 case INDEX_op_ext16s_i32
:
1373 tcg_out32 (s
, EXTSH
| RS (args
[1]) | RA (args
[0]));
1377 tcg_dump_ops (s
, stderr
);
1382 static const TCGTargetOpDef ppc_op_defs
[] = {
1383 { INDEX_op_exit_tb
, { } },
1384 { INDEX_op_goto_tb
, { } },
1385 { INDEX_op_call
, { "ri" } },
1386 { INDEX_op_jmp
, { "ri" } },
1387 { INDEX_op_br
, { } },
1389 { INDEX_op_mov_i32
, { "r", "r" } },
1390 { INDEX_op_movi_i32
, { "r" } },
1391 { INDEX_op_ld8u_i32
, { "r", "r" } },
1392 { INDEX_op_ld8s_i32
, { "r", "r" } },
1393 { INDEX_op_ld16u_i32
, { "r", "r" } },
1394 { INDEX_op_ld16s_i32
, { "r", "r" } },
1395 { INDEX_op_ld_i32
, { "r", "r" } },
1396 { INDEX_op_st8_i32
, { "r", "r" } },
1397 { INDEX_op_st16_i32
, { "r", "r" } },
1398 { INDEX_op_st_i32
, { "r", "r" } },
1400 { INDEX_op_add_i32
, { "r", "r", "ri" } },
1401 { INDEX_op_mul_i32
, { "r", "r", "ri" } },
1402 { INDEX_op_div_i32
, { "r", "r", "r" } },
1403 { INDEX_op_divu_i32
, { "r", "r", "r" } },
1404 { INDEX_op_rem_i32
, { "r", "r", "r" } },
1405 { INDEX_op_remu_i32
, { "r", "r", "r" } },
1406 { INDEX_op_mulu2_i32
, { "r", "r", "r", "r" } },
1407 { INDEX_op_sub_i32
, { "r", "r", "ri" } },
1408 { INDEX_op_and_i32
, { "r", "r", "ri" } },
1409 { INDEX_op_or_i32
, { "r", "r", "ri" } },
1410 { INDEX_op_xor_i32
, { "r", "r", "ri" } },
1412 { INDEX_op_shl_i32
, { "r", "r", "ri" } },
1413 { INDEX_op_shr_i32
, { "r", "r", "ri" } },
1414 { INDEX_op_sar_i32
, { "r", "r", "ri" } },
1416 { INDEX_op_brcond_i32
, { "r", "ri" } },
1418 { INDEX_op_add2_i32
, { "r", "r", "r", "r", "r", "r" } },
1419 { INDEX_op_sub2_i32
, { "r", "r", "r", "r", "r", "r" } },
1420 { INDEX_op_brcond2_i32
, { "r", "r", "r", "r" } },
1422 { INDEX_op_neg_i32
, { "r", "r" } },
1424 #if TARGET_LONG_BITS == 32
1425 { INDEX_op_qemu_ld8u
, { "r", "L" } },
1426 { INDEX_op_qemu_ld8s
, { "r", "L" } },
1427 { INDEX_op_qemu_ld16u
, { "r", "L" } },
1428 { INDEX_op_qemu_ld16s
, { "r", "L" } },
1429 { INDEX_op_qemu_ld32u
, { "r", "L" } },
1430 { INDEX_op_qemu_ld32s
, { "r", "L" } },
1431 { INDEX_op_qemu_ld64
, { "r", "r", "L" } },
1433 { INDEX_op_qemu_st8
, { "K", "K" } },
1434 { INDEX_op_qemu_st16
, { "K", "K" } },
1435 { INDEX_op_qemu_st32
, { "K", "K" } },
1436 { INDEX_op_qemu_st64
, { "M", "M", "M" } },
1438 { INDEX_op_qemu_ld8u
, { "r", "L", "L" } },
1439 { INDEX_op_qemu_ld8s
, { "r", "L", "L" } },
1440 { INDEX_op_qemu_ld16u
, { "r", "L", "L" } },
1441 { INDEX_op_qemu_ld16s
, { "r", "L", "L" } },
1442 { INDEX_op_qemu_ld32u
, { "r", "L", "L" } },
1443 { INDEX_op_qemu_ld32s
, { "r", "L", "L" } },
1444 { INDEX_op_qemu_ld64
, { "r", "L", "L", "L" } },
1446 { INDEX_op_qemu_st8
, { "K", "K", "K" } },
1447 { INDEX_op_qemu_st16
, { "K", "K", "K" } },
1448 { INDEX_op_qemu_st32
, { "K", "K", "K" } },
1449 { INDEX_op_qemu_st64
, { "M", "M", "M", "M" } },
1452 { INDEX_op_ext8s_i32
, { "r", "r" } },
1453 { INDEX_op_ext16s_i32
, { "r", "r" } },
1458 void tcg_target_init(TCGContext
*s
)
1460 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I32
], 0, 0xffffffff);
1461 tcg_regset_set32(tcg_target_call_clobber_regs
, 0,
1473 (1 << TCG_REG_R10
) |
1474 (1 << TCG_REG_R11
) |
1478 tcg_regset_clear(s
->reserved_regs
);
1479 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R0
);
1480 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R1
);
1482 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R2
);
1485 tcg_add_target_add_op_defs(ppc_op_defs
);