2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #define TCG_CT_CONST_S16 0x100
26 #define TCG_CT_CONST_U16 0x200
27 #define TCG_CT_CONST_S32 0x400
28 #define TCG_CT_CONST_U32 0x800
29 #define TCG_CT_CONST_ZERO 0x1000
30 #define TCG_CT_CONST_MONE 0x2000
32 static uint8_t *tb_ret_addr
;
36 #if TARGET_LONG_BITS == 32
48 #ifdef CONFIG_GETAUXVAL
50 static bool have_isa_2_06
;
51 #define HAVE_ISA_2_06 have_isa_2_06
52 #define HAVE_ISEL have_isa_2_06
54 #define HAVE_ISA_2_06 0
58 #ifdef CONFIG_USE_GUEST_BASE
59 #define TCG_GUEST_BASE_REG 30
61 #define TCG_GUEST_BASE_REG 0
65 static const char * const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
101 static const int tcg_target_reg_alloc_order
[] = {
137 static const int tcg_target_call_iarg_regs
[] = {
148 static const int tcg_target_call_oarg_regs
[] = {
152 static const int tcg_target_callee_save_regs
[] = {
169 TCG_REG_R27
, /* currently used for the global env */
176 static uint32_t reloc_pc24_val (void *pc
, tcg_target_long target
)
178 tcg_target_long disp
;
180 disp
= target
- (tcg_target_long
) pc
;
181 if ((disp
<< 38) >> 38 != disp
)
184 return disp
& 0x3fffffc;
187 static void reloc_pc24 (void *pc
, tcg_target_long target
)
189 *(uint32_t *) pc
= (*(uint32_t *) pc
& ~0x3fffffc)
190 | reloc_pc24_val (pc
, target
);
193 static uint16_t reloc_pc14_val (void *pc
, tcg_target_long target
)
195 tcg_target_long disp
;
197 disp
= target
- (tcg_target_long
) pc
;
198 if (disp
!= (int16_t) disp
)
201 return disp
& 0xfffc;
204 static void reloc_pc14 (void *pc
, tcg_target_long target
)
206 *(uint32_t *) pc
= (*(uint32_t *) pc
& ~0xfffc)
207 | reloc_pc14_val (pc
, target
);
210 static void patch_reloc (uint8_t *code_ptr
, int type
,
211 tcg_target_long value
, tcg_target_long addend
)
216 reloc_pc14 (code_ptr
, value
);
219 reloc_pc24 (code_ptr
, value
);
226 /* parse target specific constraints */
227 static int target_parse_constraint (TCGArgConstraint
*ct
, const char **pct_str
)
233 case 'A': case 'B': case 'C': case 'D':
234 ct
->ct
|= TCG_CT_REG
;
235 tcg_regset_set_reg (ct
->u
.regs
, 3 + ct_str
[0] - 'A');
238 ct
->ct
|= TCG_CT_REG
;
239 tcg_regset_set32 (ct
->u
.regs
, 0, 0xffffffff);
241 case 'L': /* qemu_ld constraint */
242 ct
->ct
|= TCG_CT_REG
;
243 tcg_regset_set32 (ct
->u
.regs
, 0, 0xffffffff);
244 tcg_regset_reset_reg (ct
->u
.regs
, TCG_REG_R3
);
245 #ifdef CONFIG_SOFTMMU
246 tcg_regset_reset_reg (ct
->u
.regs
, TCG_REG_R4
);
247 tcg_regset_reset_reg (ct
->u
.regs
, TCG_REG_R5
);
250 case 'S': /* qemu_st constraint */
251 ct
->ct
|= TCG_CT_REG
;
252 tcg_regset_set32 (ct
->u
.regs
, 0, 0xffffffff);
253 tcg_regset_reset_reg (ct
->u
.regs
, TCG_REG_R3
);
254 #ifdef CONFIG_SOFTMMU
255 tcg_regset_reset_reg (ct
->u
.regs
, TCG_REG_R4
);
256 tcg_regset_reset_reg (ct
->u
.regs
, TCG_REG_R5
);
257 tcg_regset_reset_reg (ct
->u
.regs
, TCG_REG_R6
);
261 ct
->ct
|= TCG_CT_CONST_S16
;
264 ct
->ct
|= TCG_CT_CONST_U16
;
267 ct
->ct
|= TCG_CT_CONST_MONE
;
270 ct
->ct
|= TCG_CT_CONST_S32
;
273 ct
->ct
|= TCG_CT_CONST_U32
;
276 ct
->ct
|= TCG_CT_CONST_ZERO
;
286 /* test if a constant matches the constraint */
287 static int tcg_target_const_match (tcg_target_long val
,
288 const TCGArgConstraint
*arg_ct
)
291 if (ct
& TCG_CT_CONST
) {
293 } else if ((ct
& TCG_CT_CONST_S16
) && val
== (int16_t)val
) {
295 } else if ((ct
& TCG_CT_CONST_U16
) && val
== (uint16_t)val
) {
297 } else if ((ct
& TCG_CT_CONST_S32
) && val
== (int32_t)val
) {
299 } else if ((ct
& TCG_CT_CONST_U32
) && val
== (uint32_t)val
) {
301 } else if ((ct
& TCG_CT_CONST_ZERO
) && val
== 0) {
303 } else if ((ct
& TCG_CT_CONST_MONE
) && val
== -1) {
309 #define OPCD(opc) ((opc)<<26)
310 #define XO19(opc) (OPCD(19)|((opc)<<1))
311 #define MD30(opc) (OPCD(30)|((opc)<<2))
312 #define MDS30(opc) (OPCD(30)|((opc)<<1))
313 #define XO31(opc) (OPCD(31)|((opc)<<1))
314 #define XO58(opc) (OPCD(58)|(opc))
315 #define XO62(opc) (OPCD(62)|(opc))
319 #define LBZ OPCD( 34)
320 #define LHZ OPCD( 40)
321 #define LHA OPCD( 42)
322 #define LWZ OPCD( 32)
323 #define STB OPCD( 38)
324 #define STH OPCD( 44)
325 #define STW OPCD( 36)
328 #define STDU XO62( 1)
329 #define STDX XO31(149)
332 #define LDX XO31( 21)
335 #define LWAX XO31(341)
337 #define ADDIC OPCD( 12)
338 #define ADDI OPCD( 14)
339 #define ADDIS OPCD( 15)
340 #define ORI OPCD( 24)
341 #define ORIS OPCD( 25)
342 #define XORI OPCD( 26)
343 #define XORIS OPCD( 27)
344 #define ANDI OPCD( 28)
345 #define ANDIS OPCD( 29)
346 #define MULLI OPCD( 7)
347 #define CMPLI OPCD( 10)
348 #define CMPI OPCD( 11)
349 #define SUBFIC OPCD( 8)
351 #define LWZU OPCD( 33)
352 #define STWU OPCD( 37)
354 #define RLWIMI OPCD( 20)
355 #define RLWINM OPCD( 21)
356 #define RLWNM OPCD( 23)
358 #define RLDICL MD30( 0)
359 #define RLDICR MD30( 1)
360 #define RLDIMI MD30( 3)
361 #define RLDCL MDS30( 8)
363 #define BCLR XO19( 16)
364 #define BCCTR XO19(528)
365 #define CRAND XO19(257)
366 #define CRANDC XO19(129)
367 #define CRNAND XO19(225)
368 #define CROR XO19(449)
369 #define CRNOR XO19( 33)
371 #define EXTSB XO31(954)
372 #define EXTSH XO31(922)
373 #define EXTSW XO31(986)
374 #define ADD XO31(266)
375 #define ADDE XO31(138)
376 #define ADDME XO31(234)
377 #define ADDZE XO31(202)
378 #define ADDC XO31( 10)
379 #define AND XO31( 28)
380 #define SUBF XO31( 40)
381 #define SUBFC XO31( 8)
382 #define SUBFE XO31(136)
383 #define SUBFME XO31(232)
384 #define SUBFZE XO31(200)
386 #define XOR XO31(316)
387 #define MULLW XO31(235)
388 #define MULHWU XO31( 11)
389 #define DIVW XO31(491)
390 #define DIVWU XO31(459)
392 #define CMPL XO31( 32)
393 #define LHBRX XO31(790)
394 #define LWBRX XO31(534)
395 #define LDBRX XO31(532)
396 #define STHBRX XO31(918)
397 #define STWBRX XO31(662)
398 #define STDBRX XO31(660)
399 #define MFSPR XO31(339)
400 #define MTSPR XO31(467)
401 #define SRAWI XO31(824)
402 #define NEG XO31(104)
403 #define MFCR XO31( 19)
404 #define MFOCRF (MFCR | (1u << 20))
405 #define NOR XO31(124)
406 #define CNTLZW XO31( 26)
407 #define CNTLZD XO31( 58)
408 #define ANDC XO31( 60)
409 #define ORC XO31(412)
410 #define EQV XO31(284)
411 #define NAND XO31(476)
412 #define ISEL XO31( 15)
414 #define MULLD XO31(233)
415 #define MULHD XO31( 73)
416 #define MULHDU XO31( 9)
417 #define DIVD XO31(489)
418 #define DIVDU XO31(457)
420 #define LBZX XO31( 87)
421 #define LHZX XO31(279)
422 #define LHAX XO31(343)
423 #define LWZX XO31( 23)
424 #define STBX XO31(215)
425 #define STHX XO31(407)
426 #define STWX XO31(151)
428 #define SPR(a,b) ((((a)<<5)|(b))<<11)
430 #define CTR SPR(9, 0)
432 #define SLW XO31( 24)
433 #define SRW XO31(536)
434 #define SRAW XO31(792)
436 #define SLD XO31( 27)
437 #define SRD XO31(539)
438 #define SRAD XO31(794)
439 #define SRADI XO31(413<<1)
442 #define TRAP (TW | TO (31))
444 #define RT(r) ((r)<<21)
445 #define RS(r) ((r)<<21)
446 #define RA(r) ((r)<<16)
447 #define RB(r) ((r)<<11)
448 #define TO(t) ((t)<<21)
449 #define SH(s) ((s)<<11)
450 #define MB(b) ((b)<<6)
451 #define ME(e) ((e)<<1)
452 #define BO(o) ((o)<<21)
453 #define MB64(b) ((b)<<5)
454 #define FXM(b) (1 << (19 - (b)))
458 #define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
459 #define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
460 #define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
461 #define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff))
463 #define BF(n) ((n)<<23)
464 #define BI(n, c) (((c)+((n)*4))<<16)
465 #define BT(n, c) (((c)+((n)*4))<<21)
466 #define BA(n, c) (((c)+((n)*4))<<16)
467 #define BB(n, c) (((c)+((n)*4))<<11)
468 #define BC_(n, c) (((c)+((n)*4))<<6)
470 #define BO_COND_TRUE BO (12)
471 #define BO_COND_FALSE BO ( 4)
472 #define BO_ALWAYS BO (20)
481 static const uint32_t tcg_to_bc
[] = {
482 [TCG_COND_EQ
] = BC
| BI (7, CR_EQ
) | BO_COND_TRUE
,
483 [TCG_COND_NE
] = BC
| BI (7, CR_EQ
) | BO_COND_FALSE
,
484 [TCG_COND_LT
] = BC
| BI (7, CR_LT
) | BO_COND_TRUE
,
485 [TCG_COND_GE
] = BC
| BI (7, CR_LT
) | BO_COND_FALSE
,
486 [TCG_COND_LE
] = BC
| BI (7, CR_GT
) | BO_COND_FALSE
,
487 [TCG_COND_GT
] = BC
| BI (7, CR_GT
) | BO_COND_TRUE
,
488 [TCG_COND_LTU
] = BC
| BI (7, CR_LT
) | BO_COND_TRUE
,
489 [TCG_COND_GEU
] = BC
| BI (7, CR_LT
) | BO_COND_FALSE
,
490 [TCG_COND_LEU
] = BC
| BI (7, CR_GT
) | BO_COND_FALSE
,
491 [TCG_COND_GTU
] = BC
| BI (7, CR_GT
) | BO_COND_TRUE
,
494 /* The low bit here is set if the RA and RB fields must be inverted. */
495 static const uint32_t tcg_to_isel
[] = {
496 [TCG_COND_EQ
] = ISEL
| BC_(7, CR_EQ
),
497 [TCG_COND_NE
] = ISEL
| BC_(7, CR_EQ
) | 1,
498 [TCG_COND_LT
] = ISEL
| BC_(7, CR_LT
),
499 [TCG_COND_GE
] = ISEL
| BC_(7, CR_LT
) | 1,
500 [TCG_COND_LE
] = ISEL
| BC_(7, CR_GT
) | 1,
501 [TCG_COND_GT
] = ISEL
| BC_(7, CR_GT
),
502 [TCG_COND_LTU
] = ISEL
| BC_(7, CR_LT
),
503 [TCG_COND_GEU
] = ISEL
| BC_(7, CR_LT
) | 1,
504 [TCG_COND_LEU
] = ISEL
| BC_(7, CR_GT
) | 1,
505 [TCG_COND_GTU
] = ISEL
| BC_(7, CR_GT
),
508 static inline void tcg_out_mov(TCGContext
*s
, TCGType type
,
509 TCGReg ret
, TCGReg arg
)
511 tcg_out32 (s
, OR
| SAB (arg
, ret
, arg
));
514 static inline void tcg_out_rld(TCGContext
*s
, int op
, TCGReg ra
, TCGReg rs
,
517 sh
= SH (sh
& 0x1f) | (((sh
>> 5) & 1) << 1);
518 mb
= MB64 ((mb
>> 5) | ((mb
<< 1) & 0x3f));
519 tcg_out32 (s
, op
| RA (ra
) | RS (rs
) | sh
| mb
);
522 static inline void tcg_out_rlw(TCGContext
*s
, int op
, TCGReg ra
, TCGReg rs
,
523 int sh
, int mb
, int me
)
525 tcg_out32(s
, op
| RA(ra
) | RS(rs
) | SH(sh
) | MB(mb
) | ME(me
));
528 static inline void tcg_out_ext32u(TCGContext
*s
, TCGReg dst
, TCGReg src
)
530 tcg_out_rld(s
, RLDICL
, dst
, src
, 0, 32);
533 static inline void tcg_out_shli64(TCGContext
*s
, TCGReg dst
, TCGReg src
, int c
)
535 tcg_out_rld(s
, RLDICR
, dst
, src
, c
, 63 - c
);
538 static inline void tcg_out_shri64(TCGContext
*s
, TCGReg dst
, TCGReg src
, int c
)
540 tcg_out_rld(s
, RLDICL
, dst
, src
, 64 - c
, c
);
543 static void tcg_out_movi32(TCGContext
*s
, TCGReg ret
, int32_t arg
)
545 if (arg
== (int16_t) arg
) {
546 tcg_out32(s
, ADDI
| TAI(ret
, 0, arg
));
548 tcg_out32(s
, ADDIS
| TAI(ret
, 0, arg
>> 16));
550 tcg_out32(s
, ORI
| SAI(ret
, ret
, arg
));
555 static void tcg_out_movi(TCGContext
*s
, TCGType type
, TCGReg ret
,
558 if (type
== TCG_TYPE_I32
|| arg
== (int32_t)arg
) {
559 tcg_out_movi32(s
, ret
, arg
);
560 } else if (arg
== (uint32_t)arg
&& !(arg
& 0x8000)) {
561 tcg_out32(s
, ADDI
| TAI(ret
, 0, arg
));
562 tcg_out32(s
, ORIS
| SAI(ret
, ret
, arg
>> 16));
564 int32_t high
= arg
>> 32;
565 tcg_out_movi32(s
, ret
, high
);
567 tcg_out_shli64(s
, ret
, ret
, 32);
569 if (arg
& 0xffff0000) {
570 tcg_out32(s
, ORIS
| SAI(ret
, ret
, arg
>> 16));
573 tcg_out32(s
, ORI
| SAI(ret
, ret
, arg
));
578 static bool mask_operand(uint32_t c
, int *mb
, int *me
)
582 /* Accept a bit pattern like:
586 Keep track of the transitions. */
587 if (c
== 0 || c
== -1) {
593 if (test
& (test
- 1)) {
598 *mb
= test
? clz32(test
& -test
) + 1 : 0;
602 static bool mask64_operand(uint64_t c
, int *mb
, int *me
)
611 /* Accept 1..10..0. */
617 /* Accept 0..01..1. */
618 if (lsb
== 1 && (c
& (c
+ 1)) == 0) {
619 *mb
= clz64(c
+ 1) + 1;
626 static void tcg_out_andi32(TCGContext
*s
, TCGReg dst
, TCGReg src
, uint32_t c
)
630 if ((c
& 0xffff) == c
) {
631 tcg_out32(s
, ANDI
| SAI(src
, dst
, c
));
633 } else if ((c
& 0xffff0000) == c
) {
634 tcg_out32(s
, ANDIS
| SAI(src
, dst
, c
>> 16));
636 } else if (mask_operand(c
, &mb
, &me
)) {
637 tcg_out_rlw(s
, RLWINM
, dst
, src
, 0, mb
, me
);
639 tcg_out_movi(s
, TCG_TYPE_I32
, 0, c
);
640 tcg_out32(s
, AND
| SAB(src
, dst
, 0));
644 static void tcg_out_andi64(TCGContext
*s
, TCGReg dst
, TCGReg src
, uint64_t c
)
648 if ((c
& 0xffff) == c
) {
649 tcg_out32(s
, ANDI
| SAI(src
, dst
, c
));
651 } else if ((c
& 0xffff0000) == c
) {
652 tcg_out32(s
, ANDIS
| SAI(src
, dst
, c
>> 16));
654 } else if (mask64_operand(c
, &mb
, &me
)) {
656 tcg_out_rld(s
, RLDICR
, dst
, src
, 0, me
);
658 tcg_out_rld(s
, RLDICL
, dst
, src
, 0, mb
);
661 tcg_out_movi(s
, TCG_TYPE_I64
, 0, c
);
662 tcg_out32(s
, AND
| SAB(src
, dst
, 0));
666 static void tcg_out_zori32(TCGContext
*s
, TCGReg dst
, TCGReg src
, uint32_t c
,
667 int op_lo
, int op_hi
)
670 tcg_out32(s
, op_hi
| SAI(src
, dst
, c
>> 16));
674 tcg_out32(s
, op_lo
| SAI(src
, dst
, c
));
679 static void tcg_out_ori32(TCGContext
*s
, TCGReg dst
, TCGReg src
, uint32_t c
)
681 tcg_out_zori32(s
, dst
, src
, c
, ORI
, ORIS
);
684 static void tcg_out_xori32(TCGContext
*s
, TCGReg dst
, TCGReg src
, uint32_t c
)
686 tcg_out_zori32(s
, dst
, src
, c
, XORI
, XORIS
);
689 static void tcg_out_b (TCGContext
*s
, int mask
, tcg_target_long target
)
691 tcg_target_long disp
;
693 disp
= target
- (tcg_target_long
) s
->code_ptr
;
694 if ((disp
<< 38) >> 38 == disp
)
695 tcg_out32 (s
, B
| (disp
& 0x3fffffc) | mask
);
697 tcg_out_movi (s
, TCG_TYPE_I64
, 0, (tcg_target_long
) target
);
698 tcg_out32 (s
, MTSPR
| RS (0) | CTR
);
699 tcg_out32 (s
, BCCTR
| BO_ALWAYS
| mask
);
703 static void tcg_out_call (TCGContext
*s
, tcg_target_long arg
, int const_arg
)
707 tcg_out_b (s
, LK
, arg
);
710 tcg_out32 (s
, MTSPR
| RS (arg
) | LR
);
711 tcg_out32 (s
, BCLR
| BO_ALWAYS
| LK
);
718 tcg_out_movi (s
, TCG_TYPE_I64
, reg
, arg
);
722 tcg_out32 (s
, LD
| RT (0) | RA (reg
));
723 tcg_out32 (s
, MTSPR
| RA (0) | CTR
);
724 tcg_out32 (s
, LD
| RT (11) | RA (reg
) | 16);
725 tcg_out32 (s
, LD
| RT (2) | RA (reg
) | 8);
726 tcg_out32 (s
, BCCTR
| BO_ALWAYS
| LK
);
730 static void tcg_out_ldst(TCGContext
*s
, TCGReg ret
, TCGReg addr
,
731 int offset
, int op1
, int op2
)
733 if (offset
== (int16_t) offset
) {
734 tcg_out32(s
, op1
| TAI(ret
, addr
, offset
));
736 tcg_out_movi(s
, TCG_TYPE_I64
, 0, offset
);
737 tcg_out32(s
, op2
| TAB(ret
, addr
, 0));
741 static void tcg_out_ldsta(TCGContext
*s
, TCGReg ret
, TCGReg addr
,
742 int offset
, int op1
, int op2
)
744 if (offset
== (int16_t) (offset
& ~3)) {
745 tcg_out32(s
, op1
| TAI(ret
, addr
, offset
));
747 tcg_out_movi(s
, TCG_TYPE_I64
, 0, offset
);
748 tcg_out32(s
, op2
| TAB(ret
, addr
, 0));
752 #if defined (CONFIG_SOFTMMU)
754 #include "exec/softmmu_defs.h"
756 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
758 static const void * const qemu_ld_helpers
[4] = {
765 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
766 uintxx_t val, int mmu_idx) */
767 static const void * const qemu_st_helpers
[4] = {
774 static void tcg_out_tlb_read(TCGContext
*s
, TCGReg r0
, TCGReg r1
, TCGReg r2
,
775 TCGReg addr_reg
, int s_bits
, int offset
)
777 #if TARGET_LONG_BITS == 32
778 tcg_out_ext32u(s
, addr_reg
, addr_reg
);
780 tcg_out_rlw(s
, RLWINM
, r0
, addr_reg
,
781 32 - (TARGET_PAGE_BITS
- CPU_TLB_ENTRY_BITS
),
782 32 - (CPU_TLB_BITS
+ CPU_TLB_ENTRY_BITS
),
783 31 - CPU_TLB_ENTRY_BITS
);
784 tcg_out32(s
, ADD
| TAB(r0
, r0
, TCG_AREG0
));
785 tcg_out32(s
, LWZU
| TAI(r1
, r0
, offset
));
786 tcg_out_rlw(s
, RLWINM
, r2
, addr_reg
, 0,
787 (32 - s_bits
) & 31, 31 - TARGET_PAGE_BITS
);
789 tcg_out_rld (s
, RLDICL
, r0
, addr_reg
,
790 64 - TARGET_PAGE_BITS
,
792 tcg_out_shli64(s
, r0
, r0
, CPU_TLB_ENTRY_BITS
);
794 tcg_out32(s
, ADD
| TAB(r0
, r0
, TCG_AREG0
));
795 tcg_out32(s
, LD_ADDR
| TAI(r1
, r0
, offset
));
798 tcg_out_rld (s
, RLDICR
, r2
, addr_reg
, 0, 63 - TARGET_PAGE_BITS
);
801 tcg_out_rld (s
, RLDICL
, r2
, addr_reg
,
802 64 - TARGET_PAGE_BITS
,
803 TARGET_PAGE_BITS
- s_bits
);
804 tcg_out_rld (s
, RLDICL
, r2
, r2
, TARGET_PAGE_BITS
, 0);
810 static const uint32_t qemu_ldx_opc
[8] = {
811 #ifdef TARGET_WORDS_BIGENDIAN
812 LBZX
, LHZX
, LWZX
, LDX
,
815 LBZX
, LHBRX
, LWBRX
, LDBRX
,
820 static const uint32_t qemu_stx_opc
[4] = {
821 #ifdef TARGET_WORDS_BIGENDIAN
822 STBX
, STHX
, STWX
, STDX
824 STBX
, STHBRX
, STWBRX
, STDBRX
,
828 static const uint32_t qemu_exts_opc
[4] = {
829 EXTSB
, EXTSH
, EXTSW
, 0
832 static void tcg_out_qemu_ld (TCGContext
*s
, const TCGArg
*args
, int opc
)
834 TCGReg addr_reg
, data_reg
, r0
, r1
, rbase
;
835 uint32_t insn
, s_bits
;
836 #ifdef CONFIG_SOFTMMU
839 void *label1_ptr
, *label2_ptr
;
846 #ifdef CONFIG_SOFTMMU
854 tcg_out_tlb_read (s
, r0
, r1
, r2
, addr_reg
, s_bits
,
855 offsetof (CPUArchState
, tlb_table
[mem_index
][0].addr_read
));
857 tcg_out32 (s
, CMP
| BF (7) | RA (r2
) | RB (r1
) | CMP_L
);
859 label1_ptr
= s
->code_ptr
;
861 tcg_out32 (s
, BC
| BI (7, CR_EQ
) | BO_COND_TRUE
);
866 tcg_out_mov (s
, TCG_TYPE_I64
, ir
++, TCG_AREG0
);
867 tcg_out_mov (s
, TCG_TYPE_I64
, ir
++, addr_reg
);
868 tcg_out_movi (s
, TCG_TYPE_I64
, ir
++, mem_index
);
870 tcg_out_call (s
, (tcg_target_long
) qemu_ld_helpers
[s_bits
], 1);
873 insn
= qemu_exts_opc
[s_bits
];
874 tcg_out32(s
, insn
| RA(data_reg
) | RS(3));
875 } else if (data_reg
!= 3) {
876 tcg_out_mov(s
, TCG_TYPE_I64
, data_reg
, 3);
878 label2_ptr
= s
->code_ptr
;
881 /* label1: fast path */
883 reloc_pc14 (label1_ptr
, (tcg_target_long
) s
->code_ptr
);
886 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
887 tcg_out32(s
, LD
| TAI(r0
, r0
,
888 offsetof(CPUTLBEntry
, addend
)
889 - offsetof(CPUTLBEntry
, addr_read
)));
890 /* r0 = env->tlb_table[mem_index][index].addend */
891 tcg_out32(s
, ADD
| TAB(r0
, r0
, addr_reg
));
892 /* r0 = env->tlb_table[mem_index][index].addend + addr */
894 #else /* !CONFIG_SOFTMMU */
895 #if TARGET_LONG_BITS == 32
896 tcg_out_ext32u(s
, addr_reg
, addr_reg
);
900 rbase
= GUEST_BASE
? TCG_GUEST_BASE_REG
: 0;
903 insn
= qemu_ldx_opc
[opc
];
904 if (!HAVE_ISA_2_06
&& insn
== LDBRX
) {
905 tcg_out32(s
, ADDI
| TAI(r1
, r0
, 4));
906 tcg_out32(s
, LWBRX
| TAB(data_reg
, rbase
, r0
));
907 tcg_out32(s
, LWBRX
| TAB( r1
, rbase
, r1
));
908 tcg_out_rld(s
, RLDIMI
, data_reg
, r1
, 32, 0);
910 tcg_out32(s
, insn
| TAB(data_reg
, rbase
, r0
));
912 insn
= qemu_ldx_opc
[s_bits
];
913 tcg_out32(s
, insn
| TAB(data_reg
, rbase
, r0
));
914 insn
= qemu_exts_opc
[s_bits
];
915 tcg_out32 (s
, insn
| RA(data_reg
) | RS(data_reg
));
918 #ifdef CONFIG_SOFTMMU
919 reloc_pc24 (label2_ptr
, (tcg_target_long
) s
->code_ptr
);
923 static void tcg_out_qemu_st (TCGContext
*s
, const TCGArg
*args
, int opc
)
925 TCGReg addr_reg
, r0
, r1
, rbase
, data_reg
;
927 #ifdef CONFIG_SOFTMMU
930 void *label1_ptr
, *label2_ptr
;
936 #ifdef CONFIG_SOFTMMU
944 tcg_out_tlb_read (s
, r0
, r1
, r2
, addr_reg
, opc
,
945 offsetof (CPUArchState
, tlb_table
[mem_index
][0].addr_write
));
947 tcg_out32 (s
, CMP
| BF (7) | RA (r2
) | RB (r1
) | CMP_L
);
949 label1_ptr
= s
->code_ptr
;
951 tcg_out32 (s
, BC
| BI (7, CR_EQ
) | BO_COND_TRUE
);
956 tcg_out_mov (s
, TCG_TYPE_I64
, ir
++, TCG_AREG0
);
957 tcg_out_mov (s
, TCG_TYPE_I64
, ir
++, addr_reg
);
958 tcg_out_rld (s
, RLDICL
, ir
++, data_reg
, 0, 64 - (1 << (3 + opc
)));
959 tcg_out_movi (s
, TCG_TYPE_I64
, ir
++, mem_index
);
961 tcg_out_call (s
, (tcg_target_long
) qemu_st_helpers
[opc
], 1);
963 label2_ptr
= s
->code_ptr
;
966 /* label1: fast path */
968 reloc_pc14 (label1_ptr
, (tcg_target_long
) s
->code_ptr
);
974 | (offsetof (CPUTLBEntry
, addend
)
975 - offsetof (CPUTLBEntry
, addr_write
))
977 /* r0 = env->tlb_table[mem_index][index].addend */
978 tcg_out32(s
, ADD
| TAB(r0
, r0
, addr_reg
));
979 /* r0 = env->tlb_table[mem_index][index].addend + addr */
981 #else /* !CONFIG_SOFTMMU */
982 #if TARGET_LONG_BITS == 32
983 tcg_out_ext32u(s
, addr_reg
, addr_reg
);
987 rbase
= GUEST_BASE
? TCG_GUEST_BASE_REG
: 0;
990 insn
= qemu_stx_opc
[opc
];
991 if (!HAVE_ISA_2_06
&& insn
== STDBRX
) {
992 tcg_out32(s
, STWBRX
| SAB(data_reg
, rbase
, r0
));
993 tcg_out32(s
, ADDI
| TAI(r1
, r0
, 4));
994 tcg_out_shri64(s
, 0, data_reg
, 32);
995 tcg_out32(s
, STWBRX
| SAB(0, rbase
, r1
));
997 tcg_out32(s
, insn
| SAB(data_reg
, rbase
, r0
));
1000 #ifdef CONFIG_SOFTMMU
1001 reloc_pc24 (label2_ptr
, (tcg_target_long
) s
->code_ptr
);
1005 static void tcg_target_qemu_prologue (TCGContext
*s
)
1013 + 8 /* back chain */
1016 + 8 /* compiler doubleword */
1017 + 8 /* link editor doubleword */
1018 + 8 /* TOC save area */
1019 + TCG_STATIC_CALL_ARGS_SIZE
1020 + ARRAY_SIZE (tcg_target_callee_save_regs
) * 8
1021 + CPU_TEMP_BUF_NLONGS
* sizeof(long)
1023 frame_size
= (frame_size
+ 15) & ~15;
1025 tcg_set_frame (s
, TCG_REG_CALL_STACK
, frame_size
1026 - CPU_TEMP_BUF_NLONGS
* sizeof (long),
1027 CPU_TEMP_BUF_NLONGS
* sizeof (long));
1030 /* First emit adhoc function descriptor */
1031 addr
= (uint64_t) s
->code_ptr
+ 24;
1032 tcg_out32 (s
, addr
>> 32); tcg_out32 (s
, addr
); /* entry point */
1033 s
->code_ptr
+= 16; /* skip TOC and environment pointer */
1037 tcg_out32 (s
, MFSPR
| RT (0) | LR
);
1038 tcg_out32 (s
, STDU
| RS (1) | RA (1) | (-frame_size
& 0xffff));
1039 for (i
= 0; i
< ARRAY_SIZE (tcg_target_callee_save_regs
); ++i
)
1041 | RS (tcg_target_callee_save_regs
[i
])
1043 | (i
* 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE
)
1046 tcg_out32 (s
, STD
| RS (0) | RA (1) | (frame_size
+ 16));
1048 #ifdef CONFIG_USE_GUEST_BASE
1050 tcg_out_movi (s
, TCG_TYPE_I64
, TCG_GUEST_BASE_REG
, GUEST_BASE
);
1051 tcg_regset_set_reg (s
->reserved_regs
, TCG_GUEST_BASE_REG
);
1055 tcg_out_mov (s
, TCG_TYPE_PTR
, TCG_AREG0
, tcg_target_call_iarg_regs
[0]);
1056 tcg_out32 (s
, MTSPR
| RS (tcg_target_call_iarg_regs
[1]) | CTR
);
1057 tcg_out32 (s
, BCCTR
| BO_ALWAYS
);
1060 tb_ret_addr
= s
->code_ptr
;
1062 for (i
= 0; i
< ARRAY_SIZE (tcg_target_callee_save_regs
); ++i
)
1064 | RT (tcg_target_callee_save_regs
[i
])
1066 | (i
* 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE
)
1069 tcg_out32(s
, LD
| TAI(0, 1, frame_size
+ 16));
1070 tcg_out32(s
, MTSPR
| RS(0) | LR
);
1071 tcg_out32(s
, ADDI
| TAI(1, 1, frame_size
));
1072 tcg_out32(s
, BCLR
| BO_ALWAYS
);
1075 static void tcg_out_ld (TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg1
,
1076 tcg_target_long arg2
)
1078 if (type
== TCG_TYPE_I32
)
1079 tcg_out_ldst (s
, ret
, arg1
, arg2
, LWZ
, LWZX
);
1081 tcg_out_ldsta (s
, ret
, arg1
, arg2
, LD
, LDX
);
1084 static void tcg_out_st (TCGContext
*s
, TCGType type
, TCGReg arg
, TCGReg arg1
,
1085 tcg_target_long arg2
)
1087 if (type
== TCG_TYPE_I32
)
1088 tcg_out_ldst (s
, arg
, arg1
, arg2
, STW
, STWX
);
1090 tcg_out_ldsta (s
, arg
, arg1
, arg2
, STD
, STDX
);
1093 static void tcg_out_cmp(TCGContext
*s
, int cond
, TCGArg arg1
, TCGArg arg2
,
1094 int const_arg2
, int cr
, TCGType type
)
1099 /* Simplify the comparisons below wrt CMPI. */
1100 if (type
== TCG_TYPE_I32
) {
1101 arg2
= (int32_t)arg2
;
1108 if ((int16_t) arg2
== arg2
) {
1113 else if ((uint16_t) arg2
== arg2
) {
1128 if ((int16_t) arg2
== arg2
) {
1143 if ((uint16_t) arg2
== arg2
) {
1156 op
|= BF(cr
) | ((type
== TCG_TYPE_I64
) << 21);
1159 tcg_out32(s
, op
| RA(arg1
) | (arg2
& 0xffff));
1162 tcg_out_movi(s
, type
, 0, arg2
);
1165 tcg_out32(s
, op
| RA(arg1
) | RB(arg2
));
1169 static void tcg_out_setcond_eq0(TCGContext
*s
, TCGType type
,
1170 TCGReg dst
, TCGReg src
)
1172 tcg_out32(s
, (type
== TCG_TYPE_I64
? CNTLZD
: CNTLZW
) | RS(src
) | RA(dst
));
1173 tcg_out_shri64(s
, dst
, dst
, type
== TCG_TYPE_I64
? 6 : 5);
1176 static void tcg_out_setcond_ne0(TCGContext
*s
, TCGReg dst
, TCGReg src
)
1178 /* X != 0 implies X + -1 generates a carry. Extra addition
1179 trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */
1181 tcg_out32(s
, ADDIC
| TAI(dst
, src
, -1));
1182 tcg_out32(s
, SUBFE
| TAB(dst
, dst
, src
));
1184 tcg_out32(s
, ADDIC
| TAI(0, src
, -1));
1185 tcg_out32(s
, SUBFE
| TAB(dst
, 0, src
));
1189 static TCGReg
tcg_gen_setcond_xor(TCGContext
*s
, TCGReg arg1
, TCGArg arg2
,
1193 if ((uint32_t)arg2
== arg2
) {
1194 tcg_out_xori32(s
, TCG_REG_R0
, arg1
, arg2
);
1196 tcg_out_movi(s
, TCG_TYPE_I64
, TCG_REG_R0
, arg2
);
1197 tcg_out32(s
, XOR
| SAB(arg1
, TCG_REG_R0
, TCG_REG_R0
));
1200 tcg_out32(s
, XOR
| SAB(arg1
, TCG_REG_R0
, arg2
));
1205 static void tcg_out_setcond(TCGContext
*s
, TCGType type
, TCGCond cond
,
1206 TCGArg arg0
, TCGArg arg1
, TCGArg arg2
,
1211 /* Ignore high bits of a potential constant arg2. */
1212 if (type
== TCG_TYPE_I32
) {
1213 arg2
= (uint32_t)arg2
;
1216 /* Handle common and trivial cases before handling anything else. */
1220 tcg_out_setcond_eq0(s
, type
, arg0
, arg1
);
1223 if (type
== TCG_TYPE_I32
) {
1224 tcg_out_ext32u(s
, TCG_REG_R0
, arg1
);
1227 tcg_out_setcond_ne0(s
, arg0
, arg1
);
1230 tcg_out32(s
, NOR
| SAB(arg1
, arg0
, arg1
));
1234 /* Extract the sign bit. */
1235 tcg_out_rld(s
, RLDICL
, arg0
, arg1
,
1236 type
== TCG_TYPE_I64
? 1 : 33, 63);
1243 /* If we have ISEL, we can implement everything with 3 or 4 insns.
1244 All other cases below are also at least 3 insns, so speed up the
1245 code generator by not considering them and always using ISEL. */
1249 tcg_out_cmp(s
, cond
, arg1
, arg2
, const_arg2
, 7, type
);
1251 isel
= tcg_to_isel
[cond
];
1253 tcg_out_movi(s
, type
, arg0
, 1);
1255 /* arg0 = (bc ? 0 : 1) */
1256 tab
= TAB(arg0
, 0, arg0
);
1259 /* arg0 = (bc ? 1 : 0) */
1260 tcg_out_movi(s
, type
, TCG_REG_R0
, 0);
1261 tab
= TAB(arg0
, arg0
, TCG_REG_R0
);
1263 tcg_out32(s
, isel
| tab
);
1269 arg1
= tcg_gen_setcond_xor(s
, arg1
, arg2
, const_arg2
);
1270 tcg_out_setcond_eq0(s
, type
, arg0
, arg1
);
1274 arg1
= tcg_gen_setcond_xor(s
, arg1
, arg2
, const_arg2
);
1275 /* Discard the high bits only once, rather than both inputs. */
1276 if (type
== TCG_TYPE_I32
) {
1277 tcg_out_ext32u(s
, TCG_REG_R0
, arg1
);
1280 tcg_out_setcond_ne0(s
, arg0
, arg1
);
1298 crop
= CRNOR
| BT (7, CR_EQ
) | BA (7, CR_LT
) | BB (7, CR_LT
);
1304 crop
= CRNOR
| BT (7, CR_EQ
) | BA (7, CR_GT
) | BB (7, CR_GT
);
1306 tcg_out_cmp(s
, cond
, arg1
, arg2
, const_arg2
, 7, type
);
1310 tcg_out32(s
, MFOCRF
| RT(TCG_REG_R0
) | FXM(7));
1311 tcg_out_rlw(s
, RLWINM
, arg0
, TCG_REG_R0
, sh
, 31, 31);
1319 static void tcg_out_bc (TCGContext
*s
, int bc
, int label_index
)
1321 TCGLabel
*l
= &s
->labels
[label_index
];
1324 tcg_out32 (s
, bc
| reloc_pc14_val (s
->code_ptr
, l
->u
.value
));
1326 uint16_t val
= *(uint16_t *) &s
->code_ptr
[2];
1328 /* Thanks to Andrzej Zaborowski */
1329 tcg_out32 (s
, bc
| (val
& 0xfffc));
1330 tcg_out_reloc (s
, s
->code_ptr
- 4, R_PPC_REL14
, label_index
, 0);
1334 static void tcg_out_brcond(TCGContext
*s
, TCGCond cond
,
1335 TCGArg arg1
, TCGArg arg2
, int const_arg2
,
1336 int label_index
, TCGType type
)
1338 tcg_out_cmp(s
, cond
, arg1
, arg2
, const_arg2
, 7, type
);
1339 tcg_out_bc(s
, tcg_to_bc
[cond
], label_index
);
1342 static void tcg_out_movcond(TCGContext
*s
, TCGType type
, TCGCond cond
,
1343 TCGArg dest
, TCGArg c1
, TCGArg c2
, TCGArg v1
,
1344 TCGArg v2
, bool const_c2
)
1346 /* If for some reason both inputs are zero, don't produce bad code. */
1347 if (v1
== 0 && v2
== 0) {
1348 tcg_out_movi(s
, type
, dest
, 0);
1352 tcg_out_cmp(s
, cond
, c1
, c2
, const_c2
, 7, type
);
1355 int isel
= tcg_to_isel
[cond
];
1357 /* Swap the V operands if the operation indicates inversion. */
1364 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */
1366 tcg_out_movi(s
, type
, 0, 0);
1368 tcg_out32(s
, isel
| TAB(dest
, v1
, v2
));
1371 cond
= tcg_invert_cond(cond
);
1373 } else if (dest
!= v1
) {
1375 tcg_out_movi(s
, type
, dest
, 0);
1377 tcg_out_mov(s
, type
, dest
, v1
);
1380 /* Branch forward over one insn */
1381 tcg_out32(s
, tcg_to_bc
[cond
] | 8);
1383 tcg_out_movi(s
, type
, dest
, 0);
1385 tcg_out_mov(s
, type
, dest
, v2
);
1390 void ppc_tb_set_jmp_target (unsigned long jmp_addr
, unsigned long addr
)
1393 unsigned long patch_size
;
1395 s
.code_ptr
= (uint8_t *) jmp_addr
;
1396 tcg_out_b (&s
, 0, addr
);
1397 patch_size
= s
.code_ptr
- (uint8_t *) jmp_addr
;
1398 flush_icache_range (jmp_addr
, jmp_addr
+ patch_size
);
1401 static void tcg_out_op (TCGContext
*s
, TCGOpcode opc
, const TCGArg
*args
,
1402 const int *const_args
)
1408 case INDEX_op_exit_tb
:
1409 tcg_out_movi (s
, TCG_TYPE_I64
, TCG_REG_R3
, args
[0]);
1410 tcg_out_b (s
, 0, (tcg_target_long
) tb_ret_addr
);
1412 case INDEX_op_goto_tb
:
1413 if (s
->tb_jmp_offset
) {
1414 /* direct jump method */
1416 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1422 s
->tb_next_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1426 TCGLabel
*l
= &s
->labels
[args
[0]];
1429 tcg_out_b (s
, 0, l
->u
.value
);
1432 uint32_t val
= *(uint32_t *) s
->code_ptr
;
1434 /* Thanks to Andrzej Zaborowski */
1435 tcg_out32 (s
, B
| (val
& 0x3fffffc));
1436 tcg_out_reloc (s
, s
->code_ptr
- 4, R_PPC_REL24
, args
[0], 0);
1441 tcg_out_call (s
, args
[0], const_args
[0]);
1443 case INDEX_op_movi_i32
:
1444 tcg_out_movi (s
, TCG_TYPE_I32
, args
[0], args
[1]);
1446 case INDEX_op_movi_i64
:
1447 tcg_out_movi (s
, TCG_TYPE_I64
, args
[0], args
[1]);
1449 case INDEX_op_ld8u_i32
:
1450 case INDEX_op_ld8u_i64
:
1451 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LBZ
, LBZX
);
1453 case INDEX_op_ld8s_i32
:
1454 case INDEX_op_ld8s_i64
:
1455 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LBZ
, LBZX
);
1456 tcg_out32 (s
, EXTSB
| RS (args
[0]) | RA (args
[0]));
1458 case INDEX_op_ld16u_i32
:
1459 case INDEX_op_ld16u_i64
:
1460 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LHZ
, LHZX
);
1462 case INDEX_op_ld16s_i32
:
1463 case INDEX_op_ld16s_i64
:
1464 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LHA
, LHAX
);
1466 case INDEX_op_ld_i32
:
1467 case INDEX_op_ld32u_i64
:
1468 tcg_out_ldst (s
, args
[0], args
[1], args
[2], LWZ
, LWZX
);
1470 case INDEX_op_ld32s_i64
:
1471 tcg_out_ldsta (s
, args
[0], args
[1], args
[2], LWA
, LWAX
);
1473 case INDEX_op_ld_i64
:
1474 tcg_out_ldsta (s
, args
[0], args
[1], args
[2], LD
, LDX
);
1476 case INDEX_op_st8_i32
:
1477 case INDEX_op_st8_i64
:
1478 tcg_out_ldst (s
, args
[0], args
[1], args
[2], STB
, STBX
);
1480 case INDEX_op_st16_i32
:
1481 case INDEX_op_st16_i64
:
1482 tcg_out_ldst (s
, args
[0], args
[1], args
[2], STH
, STHX
);
1484 case INDEX_op_st_i32
:
1485 case INDEX_op_st32_i64
:
1486 tcg_out_ldst (s
, args
[0], args
[1], args
[2], STW
, STWX
);
1488 case INDEX_op_st_i64
:
1489 tcg_out_ldsta (s
, args
[0], args
[1], args
[2], STD
, STDX
);
1492 case INDEX_op_add_i32
:
1493 a0
= args
[0], a1
= args
[1], a2
= args
[2];
1494 if (const_args
[2]) {
1500 tcg_out32(s
, ADDIS
| TAI(a0
, a1
, h
>> 16));
1503 if (l
|| a0
!= a1
) {
1504 tcg_out32(s
, ADDI
| TAI(a0
, a1
, l
));
1507 tcg_out32(s
, ADD
| TAB(a0
, a1
, a2
));
1510 case INDEX_op_sub_i32
:
1511 a0
= args
[0], a1
= args
[1], a2
= args
[2];
1512 if (const_args
[1]) {
1513 if (const_args
[2]) {
1514 tcg_out_movi(s
, TCG_TYPE_I32
, a0
, a1
- a2
);
1516 tcg_out32(s
, SUBFIC
| TAI(a0
, a2
, a1
));
1518 } else if (const_args
[2]) {
1522 tcg_out32(s
, SUBF
| TAB(a0
, a2
, a1
));
1526 case INDEX_op_and_i32
:
1527 a0
= args
[0], a1
= args
[1], a2
= args
[2];
1528 if (const_args
[2]) {
1529 tcg_out_andi32(s
, a0
, a1
, a2
);
1531 tcg_out32(s
, AND
| SAB(a1
, a0
, a2
));
1534 case INDEX_op_and_i64
:
1535 a0
= args
[0], a1
= args
[1], a2
= args
[2];
1536 if (const_args
[2]) {
1537 tcg_out_andi64(s
, a0
, a1
, a2
);
1539 tcg_out32(s
, AND
| SAB(a1
, a0
, a2
));
1542 case INDEX_op_or_i64
:
1543 case INDEX_op_or_i32
:
1544 a0
= args
[0], a1
= args
[1], a2
= args
[2];
1545 if (const_args
[2]) {
1546 tcg_out_ori32(s
, a0
, a1
, a2
);
1548 tcg_out32(s
, OR
| SAB(a1
, a0
, a2
));
1551 case INDEX_op_xor_i64
:
1552 case INDEX_op_xor_i32
:
1553 a0
= args
[0], a1
= args
[1], a2
= args
[2];
1554 if (const_args
[2]) {
1555 tcg_out_xori32(s
, a0
, a1
, a2
);
1557 tcg_out32(s
, XOR
| SAB(a1
, a0
, a2
));
1560 case INDEX_op_andc_i32
:
1561 a0
= args
[0], a1
= args
[1], a2
= args
[2];
1562 if (const_args
[2]) {
1563 tcg_out_andi32(s
, a0
, a1
, ~a2
);
1565 tcg_out32(s
, ANDC
| SAB(a1
, a0
, a2
));
1568 case INDEX_op_andc_i64
:
1569 a0
= args
[0], a1
= args
[1], a2
= args
[2];
1570 if (const_args
[2]) {
1571 tcg_out_andi64(s
, a0
, a1
, ~a2
);
1573 tcg_out32(s
, ANDC
| SAB(a1
, a0
, a2
));
1576 case INDEX_op_orc_i32
:
1577 if (const_args
[2]) {
1578 tcg_out_ori32(s
, args
[0], args
[1], ~args
[2]);
1582 case INDEX_op_orc_i64
:
1583 tcg_out32(s
, ORC
| SAB(args
[1], args
[0], args
[2]));
1585 case INDEX_op_eqv_i32
:
1586 if (const_args
[2]) {
1587 tcg_out_xori32(s
, args
[0], args
[1], ~args
[2]);
1591 case INDEX_op_eqv_i64
:
1592 tcg_out32(s
, EQV
| SAB(args
[1], args
[0], args
[2]));
1594 case INDEX_op_nand_i32
:
1595 case INDEX_op_nand_i64
:
1596 tcg_out32(s
, NAND
| SAB(args
[1], args
[0], args
[2]));
1598 case INDEX_op_nor_i32
:
1599 case INDEX_op_nor_i64
:
1600 tcg_out32(s
, NOR
| SAB(args
[1], args
[0], args
[2]));
1603 case INDEX_op_mul_i32
:
1604 a0
= args
[0], a1
= args
[1], a2
= args
[2];
1605 if (const_args
[2]) {
1606 tcg_out32(s
, MULLI
| TAI(a0
, a1
, a2
));
1608 tcg_out32(s
, MULLW
| TAB(a0
, a1
, a2
));
1612 case INDEX_op_div_i32
:
1613 tcg_out32 (s
, DIVW
| TAB (args
[0], args
[1], args
[2]));
1616 case INDEX_op_divu_i32
:
1617 tcg_out32 (s
, DIVWU
| TAB (args
[0], args
[1], args
[2]));
1620 case INDEX_op_rem_i32
:
1621 tcg_out32 (s
, DIVW
| TAB (0, args
[1], args
[2]));
1622 tcg_out32 (s
, MULLW
| TAB (0, 0, args
[2]));
1623 tcg_out32 (s
, SUBF
| TAB (args
[0], 0, args
[1]));
1626 case INDEX_op_remu_i32
:
1627 tcg_out32 (s
, DIVWU
| TAB (0, args
[1], args
[2]));
1628 tcg_out32 (s
, MULLW
| TAB (0, 0, args
[2]));
1629 tcg_out32 (s
, SUBF
| TAB (args
[0], 0, args
[1]));
1632 case INDEX_op_shl_i32
:
1633 if (const_args
[2]) {
1634 tcg_out_rlw(s
, RLWINM
, args
[0], args
[1], args
[2], 0, 31 - args
[2]);
1636 tcg_out32 (s
, SLW
| SAB (args
[1], args
[0], args
[2]));
1639 case INDEX_op_shr_i32
:
1640 if (const_args
[2]) {
1641 tcg_out_rlw(s
, RLWINM
, args
[0], args
[1], 32 - args
[2], args
[2], 31);
1643 tcg_out32 (s
, SRW
| SAB (args
[1], args
[0], args
[2]));
1646 case INDEX_op_sar_i32
:
1648 tcg_out32 (s
, SRAWI
| RS (args
[1]) | RA (args
[0]) | SH (args
[2]));
1650 tcg_out32 (s
, SRAW
| SAB (args
[1], args
[0], args
[2]));
1652 case INDEX_op_rotl_i32
:
1653 if (const_args
[2]) {
1654 tcg_out_rlw(s
, RLWINM
, args
[0], args
[1], args
[2], 0, 31);
1656 tcg_out32(s
, RLWNM
| SAB(args
[1], args
[0], args
[2])
1660 case INDEX_op_rotr_i32
:
1661 if (const_args
[2]) {
1662 tcg_out_rlw(s
, RLWINM
, args
[0], args
[1], 32 - args
[2], 0, 31);
1664 tcg_out32(s
, SUBFIC
| TAI(0, args
[2], 32));
1665 tcg_out32(s
, RLWNM
| SAB(args
[1], args
[0], args
[2])
1670 case INDEX_op_brcond_i32
:
1671 tcg_out_brcond(s
, args
[2], args
[0], args
[1], const_args
[1],
1672 args
[3], TCG_TYPE_I32
);
1675 case INDEX_op_brcond_i64
:
1676 tcg_out_brcond(s
, args
[2], args
[0], args
[1], const_args
[1],
1677 args
[3], TCG_TYPE_I64
);
1680 case INDEX_op_neg_i32
:
1681 case INDEX_op_neg_i64
:
1682 tcg_out32 (s
, NEG
| RT (args
[0]) | RA (args
[1]));
1685 case INDEX_op_not_i32
:
1686 case INDEX_op_not_i64
:
1687 tcg_out32 (s
, NOR
| SAB (args
[1], args
[0], args
[1]));
1690 case INDEX_op_add_i64
:
1691 a0
= args
[0], a1
= args
[1], a2
= args
[2];
1692 if (const_args
[2]) {
1695 /* We can always split any 32-bit signed constant into 3 pieces.
1696 Note the positive 0x80000000 coming from the sub_i64 path,
1697 handled with the same code we need for eg 0x7fff8000. */
1698 assert(a2
== (int32_t)a2
|| a2
== 0x80000000);
1702 if (h1
< 0 && (int64_t)a2
> 0) {
1706 assert((TCGArg
)h2
+ h1
+ l0
== a2
);
1709 tcg_out32(s
, ADDIS
| TAI(a0
, a1
, h2
>> 16));
1713 tcg_out32(s
, ADDIS
| TAI(a0
, a1
, h1
>> 16));
1716 if (l0
|| a0
!= a1
) {
1717 tcg_out32(s
, ADDI
| TAI(a0
, a1
, l0
));
1720 tcg_out32(s
, ADD
| TAB(a0
, a1
, a2
));
1723 case INDEX_op_sub_i64
:
1724 a0
= args
[0], a1
= args
[1], a2
= args
[2];
1725 if (const_args
[1]) {
1726 if (const_args
[2]) {
1727 tcg_out_movi(s
, TCG_TYPE_I64
, a0
, a1
- a2
);
1729 tcg_out32(s
, SUBFIC
| TAI(a0
, a2
, a1
));
1731 } else if (const_args
[2]) {
1735 tcg_out32(s
, SUBF
| TAB(a0
, a2
, a1
));
1739 case INDEX_op_shl_i64
:
1741 tcg_out_shli64(s
, args
[0], args
[1], args
[2]);
1743 tcg_out32 (s
, SLD
| SAB (args
[1], args
[0], args
[2]));
1745 case INDEX_op_shr_i64
:
1747 tcg_out_shri64(s
, args
[0], args
[1], args
[2]);
1749 tcg_out32 (s
, SRD
| SAB (args
[1], args
[0], args
[2]));
1751 case INDEX_op_sar_i64
:
1752 if (const_args
[2]) {
1753 int sh
= SH (args
[2] & 0x1f) | (((args
[2] >> 5) & 1) << 1);
1754 tcg_out32 (s
, SRADI
| RA (args
[0]) | RS (args
[1]) | sh
);
1757 tcg_out32 (s
, SRAD
| SAB (args
[1], args
[0], args
[2]));
1759 case INDEX_op_rotl_i64
:
1760 if (const_args
[2]) {
1761 tcg_out_rld(s
, RLDICL
, args
[0], args
[1], args
[2], 0);
1763 tcg_out32(s
, RLDCL
| SAB(args
[1], args
[0], args
[2]) | MB64(0));
1766 case INDEX_op_rotr_i64
:
1767 if (const_args
[2]) {
1768 tcg_out_rld(s
, RLDICL
, args
[0], args
[1], 64 - args
[2], 0);
1770 tcg_out32(s
, SUBFIC
| TAI(0, args
[2], 64));
1771 tcg_out32(s
, RLDCL
| SAB(args
[1], args
[0], 0) | MB64(0));
1775 case INDEX_op_mul_i64
:
1776 a0
= args
[0], a1
= args
[1], a2
= args
[2];
1777 if (const_args
[2]) {
1778 tcg_out32(s
, MULLI
| TAI(a0
, a1
, a2
));
1780 tcg_out32(s
, MULLD
| TAB(a0
, a1
, a2
));
1783 case INDEX_op_div_i64
:
1784 tcg_out32 (s
, DIVD
| TAB (args
[0], args
[1], args
[2]));
1786 case INDEX_op_divu_i64
:
1787 tcg_out32 (s
, DIVDU
| TAB (args
[0], args
[1], args
[2]));
1789 case INDEX_op_rem_i64
:
1790 tcg_out32 (s
, DIVD
| TAB (0, args
[1], args
[2]));
1791 tcg_out32 (s
, MULLD
| TAB (0, 0, args
[2]));
1792 tcg_out32 (s
, SUBF
| TAB (args
[0], 0, args
[1]));
1794 case INDEX_op_remu_i64
:
1795 tcg_out32 (s
, DIVDU
| TAB (0, args
[1], args
[2]));
1796 tcg_out32 (s
, MULLD
| TAB (0, 0, args
[2]));
1797 tcg_out32 (s
, SUBF
| TAB (args
[0], 0, args
[1]));
1800 case INDEX_op_qemu_ld8u
:
1801 tcg_out_qemu_ld (s
, args
, 0);
1803 case INDEX_op_qemu_ld8s
:
1804 tcg_out_qemu_ld (s
, args
, 0 | 4);
1806 case INDEX_op_qemu_ld16u
:
1807 tcg_out_qemu_ld (s
, args
, 1);
1809 case INDEX_op_qemu_ld16s
:
1810 tcg_out_qemu_ld (s
, args
, 1 | 4);
1812 case INDEX_op_qemu_ld32
:
1813 case INDEX_op_qemu_ld32u
:
1814 tcg_out_qemu_ld (s
, args
, 2);
1816 case INDEX_op_qemu_ld32s
:
1817 tcg_out_qemu_ld (s
, args
, 2 | 4);
1819 case INDEX_op_qemu_ld64
:
1820 tcg_out_qemu_ld (s
, args
, 3);
1822 case INDEX_op_qemu_st8
:
1823 tcg_out_qemu_st (s
, args
, 0);
1825 case INDEX_op_qemu_st16
:
1826 tcg_out_qemu_st (s
, args
, 1);
1828 case INDEX_op_qemu_st32
:
1829 tcg_out_qemu_st (s
, args
, 2);
1831 case INDEX_op_qemu_st64
:
1832 tcg_out_qemu_st (s
, args
, 3);
1835 case INDEX_op_ext8s_i32
:
1836 case INDEX_op_ext8s_i64
:
1839 case INDEX_op_ext16s_i32
:
1840 case INDEX_op_ext16s_i64
:
1843 case INDEX_op_ext32s_i64
:
1847 tcg_out32 (s
, c
| RS (args
[1]) | RA (args
[0]));
1850 case INDEX_op_setcond_i32
:
1851 tcg_out_setcond (s
, TCG_TYPE_I32
, args
[3], args
[0], args
[1], args
[2],
1854 case INDEX_op_setcond_i64
:
1855 tcg_out_setcond (s
, TCG_TYPE_I64
, args
[3], args
[0], args
[1], args
[2],
1859 case INDEX_op_bswap16_i32
:
1860 case INDEX_op_bswap16_i64
:
1861 a0
= args
[0], a1
= args
[1];
1864 /* a0 = (a1 r<< 24) & 0xff # 000c */
1865 tcg_out_rlw(s
, RLWINM
, a0
, a1
, 24, 24, 31);
1866 /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */
1867 tcg_out_rlw(s
, RLWIMI
, a0
, a1
, 8, 16, 23);
1869 /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */
1870 tcg_out_rlw(s
, RLWINM
, TCG_REG_R0
, a1
, 8, 16, 23);
1871 /* a0 = (a1 r<< 24) & 0xff # 000c */
1872 tcg_out_rlw(s
, RLWINM
, a0
, a1
, 24, 24, 31);
1873 /* a0 = a0 | r0 # 00dc */
1874 tcg_out32(s
, OR
| SAB(TCG_REG_R0
, a0
, a0
));
1878 case INDEX_op_bswap32_i32
:
1879 case INDEX_op_bswap32_i64
:
1880 /* Stolen from gcc's builtin_bswap32 */
1882 a0
= args
[0] == a1
? TCG_REG_R0
: args
[0];
1884 /* a1 = args[1] # abcd */
1885 /* a0 = rotate_left (a1, 8) # bcda */
1886 tcg_out_rlw(s
, RLWINM
, a0
, a1
, 8, 0, 31);
1887 /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */
1888 tcg_out_rlw(s
, RLWIMI
, a0
, a1
, 24, 0, 7);
1889 /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */
1890 tcg_out_rlw(s
, RLWIMI
, a0
, a1
, 24, 16, 23);
1892 if (a0
== TCG_REG_R0
) {
1893 tcg_out_mov(s
, TCG_TYPE_I64
, args
[0], a0
);
1897 case INDEX_op_bswap64_i64
:
1898 a0
= args
[0], a1
= args
[1], a2
= 0;
1904 /* a1 = # abcd efgh */
1905 /* a0 = rl32(a1, 8) # 0000 fghe */
1906 tcg_out_rlw(s
, RLWINM
, a0
, a1
, 8, 0, 31);
1907 /* a0 = dep(a0, rl32(a1, 24), 0xff000000) # 0000 hghe */
1908 tcg_out_rlw(s
, RLWIMI
, a0
, a1
, 24, 0, 7);
1909 /* a0 = dep(a0, rl32(a1, 24), 0x0000ff00) # 0000 hgfe */
1910 tcg_out_rlw(s
, RLWIMI
, a0
, a1
, 24, 16, 23);
1912 /* a0 = rl64(a0, 32) # hgfe 0000 */
1913 /* a2 = rl64(a1, 32) # efgh abcd */
1914 tcg_out_rld(s
, RLDICL
, a0
, a0
, 32, 0);
1915 tcg_out_rld(s
, RLDICL
, a2
, a1
, 32, 0);
1917 /* a0 = dep(a0, rl32(a2, 8), 0xffffffff) # hgfe bcda */
1918 tcg_out_rlw(s
, RLWIMI
, a0
, a2
, 8, 0, 31);
1919 /* a0 = dep(a0, rl32(a2, 24), 0xff000000) # hgfe dcda */
1920 tcg_out_rlw(s
, RLWIMI
, a0
, a2
, 24, 0, 7);
1921 /* a0 = dep(a0, rl32(a2, 24), 0x0000ff00) # hgfe dcba */
1922 tcg_out_rlw(s
, RLWIMI
, a0
, a2
, 24, 16, 23);
1925 tcg_out_mov(s
, TCG_TYPE_I64
, args
[0], a0
);
1926 /* Revert the source rotate that we performed above. */
1927 tcg_out_rld(s
, RLDICL
, a1
, a1
, 32, 0);
1931 case INDEX_op_deposit_i32
:
1932 if (const_args
[2]) {
1933 uint32_t mask
= ((2u << (args
[4] - 1)) - 1) << args
[3];
1934 tcg_out_andi32(s
, args
[0], args
[0], ~mask
);
1936 tcg_out_rlw(s
, RLWIMI
, args
[0], args
[2], args
[3],
1937 32 - args
[3] - args
[4], 31 - args
[3]);
1940 case INDEX_op_deposit_i64
:
1941 if (const_args
[2]) {
1942 uint64_t mask
= ((2ull << (args
[4] - 1)) - 1) << args
[3];
1943 tcg_out_andi64(s
, args
[0], args
[0], ~mask
);
1945 tcg_out_rld(s
, RLDIMI
, args
[0], args
[2], args
[3],
1946 64 - args
[3] - args
[4]);
1950 case INDEX_op_movcond_i32
:
1951 tcg_out_movcond(s
, TCG_TYPE_I32
, args
[5], args
[0], args
[1], args
[2],
1952 args
[3], args
[4], const_args
[2]);
1954 case INDEX_op_movcond_i64
:
1955 tcg_out_movcond(s
, TCG_TYPE_I64
, args
[5], args
[0], args
[1], args
[2],
1956 args
[3], args
[4], const_args
[2]);
1959 case INDEX_op_add2_i64
:
1960 /* Note that the CA bit is defined based on the word size of the
1961 environment. So in 64-bit mode it's always carry-out of bit 63.
1962 The fallback code using deposit works just as well for 32-bit. */
1963 a0
= args
[0], a1
= args
[1];
1964 if (a0
== args
[4] || (!const_args
[5] && a0
== args
[5])) {
1967 if (const_args
[3]) {
1968 tcg_out32(s
, ADDIC
| TAI(a0
, args
[2], args
[3]));
1970 tcg_out32(s
, ADDC
| TAB(a0
, args
[2], args
[3]));
1972 if (const_args
[5]) {
1973 tcg_out32(s
, (args
[5] ? ADDME
: ADDZE
) | RT(a1
) | RA(args
[4]));
1975 tcg_out32(s
, ADDE
| TAB(a1
, args
[4], args
[5]));
1977 if (a0
!= args
[0]) {
1978 tcg_out_mov(s
, TCG_TYPE_I64
, args
[0], a0
);
1982 case INDEX_op_sub2_i64
:
1983 a0
= args
[0], a1
= args
[1];
1984 if (a0
== args
[5] || (!const_args
[4] && a0
== args
[4])) {
1987 if (const_args
[2]) {
1988 tcg_out32(s
, SUBFIC
| TAI(a0
, args
[3], args
[2]));
1990 tcg_out32(s
, SUBFC
| TAB(a0
, args
[3], args
[2]));
1992 if (const_args
[4]) {
1993 tcg_out32(s
, (args
[4] ? SUBFME
: SUBFZE
) | RT(a1
) | RA(args
[5]));
1995 tcg_out32(s
, SUBFE
| TAB(a1
, args
[5], args
[4]));
1997 if (a0
!= args
[0]) {
1998 tcg_out_mov(s
, TCG_TYPE_I64
, args
[0], a0
);
2002 case INDEX_op_mulu2_i64
:
2003 case INDEX_op_muls2_i64
:
2005 int oph
= (opc
== INDEX_op_mulu2_i64
? MULHDU
: MULHD
);
2006 TCGReg outl
= args
[0], outh
= args
[1];
2007 a0
= args
[2], a1
= args
[3];
2009 if (outl
== a0
|| outl
== a1
) {
2010 if (outh
== a0
|| outh
== a1
) {
2013 tcg_out32(s
, oph
| TAB(outh
, a0
, a1
));
2017 tcg_out32(s
, MULLD
| TAB(outl
, a0
, a1
));
2019 tcg_out32(s
, oph
| TAB(outh
, a0
, a1
));
2021 if (outl
!= args
[0]) {
2022 tcg_out_mov(s
, TCG_TYPE_I64
, args
[0], outl
);
2033 static const TCGTargetOpDef ppc_op_defs
[] = {
2034 { INDEX_op_exit_tb
, { } },
2035 { INDEX_op_goto_tb
, { } },
2036 { INDEX_op_call
, { "ri" } },
2037 { INDEX_op_br
, { } },
2039 { INDEX_op_mov_i32
, { "r", "r" } },
2040 { INDEX_op_mov_i64
, { "r", "r" } },
2041 { INDEX_op_movi_i32
, { "r" } },
2042 { INDEX_op_movi_i64
, { "r" } },
2044 { INDEX_op_ld8u_i32
, { "r", "r" } },
2045 { INDEX_op_ld8s_i32
, { "r", "r" } },
2046 { INDEX_op_ld16u_i32
, { "r", "r" } },
2047 { INDEX_op_ld16s_i32
, { "r", "r" } },
2048 { INDEX_op_ld_i32
, { "r", "r" } },
2049 { INDEX_op_ld_i64
, { "r", "r" } },
2050 { INDEX_op_st8_i32
, { "r", "r" } },
2051 { INDEX_op_st8_i64
, { "r", "r" } },
2052 { INDEX_op_st16_i32
, { "r", "r" } },
2053 { INDEX_op_st16_i64
, { "r", "r" } },
2054 { INDEX_op_st_i32
, { "r", "r" } },
2055 { INDEX_op_st_i64
, { "r", "r" } },
2056 { INDEX_op_st32_i64
, { "r", "r" } },
2058 { INDEX_op_ld8u_i64
, { "r", "r" } },
2059 { INDEX_op_ld8s_i64
, { "r", "r" } },
2060 { INDEX_op_ld16u_i64
, { "r", "r" } },
2061 { INDEX_op_ld16s_i64
, { "r", "r" } },
2062 { INDEX_op_ld32u_i64
, { "r", "r" } },
2063 { INDEX_op_ld32s_i64
, { "r", "r" } },
2065 { INDEX_op_add_i32
, { "r", "r", "ri" } },
2066 { INDEX_op_mul_i32
, { "r", "r", "rI" } },
2067 { INDEX_op_div_i32
, { "r", "r", "r" } },
2068 { INDEX_op_divu_i32
, { "r", "r", "r" } },
2069 { INDEX_op_rem_i32
, { "r", "r", "r" } },
2070 { INDEX_op_remu_i32
, { "r", "r", "r" } },
2071 { INDEX_op_sub_i32
, { "r", "rI", "ri" } },
2072 { INDEX_op_and_i32
, { "r", "r", "ri" } },
2073 { INDEX_op_or_i32
, { "r", "r", "ri" } },
2074 { INDEX_op_xor_i32
, { "r", "r", "ri" } },
2075 { INDEX_op_andc_i32
, { "r", "r", "ri" } },
2076 { INDEX_op_orc_i32
, { "r", "r", "ri" } },
2077 { INDEX_op_eqv_i32
, { "r", "r", "ri" } },
2078 { INDEX_op_nand_i32
, { "r", "r", "r" } },
2079 { INDEX_op_nor_i32
, { "r", "r", "r" } },
2081 { INDEX_op_shl_i32
, { "r", "r", "ri" } },
2082 { INDEX_op_shr_i32
, { "r", "r", "ri" } },
2083 { INDEX_op_sar_i32
, { "r", "r", "ri" } },
2084 { INDEX_op_rotl_i32
, { "r", "r", "ri" } },
2085 { INDEX_op_rotr_i32
, { "r", "r", "ri" } },
2087 { INDEX_op_brcond_i32
, { "r", "ri" } },
2088 { INDEX_op_brcond_i64
, { "r", "ri" } },
2090 { INDEX_op_neg_i32
, { "r", "r" } },
2091 { INDEX_op_not_i32
, { "r", "r" } },
2093 { INDEX_op_add_i64
, { "r", "r", "rT" } },
2094 { INDEX_op_sub_i64
, { "r", "rI", "rT" } },
2095 { INDEX_op_and_i64
, { "r", "r", "ri" } },
2096 { INDEX_op_or_i64
, { "r", "r", "rU" } },
2097 { INDEX_op_xor_i64
, { "r", "r", "rU" } },
2098 { INDEX_op_andc_i64
, { "r", "r", "ri" } },
2099 { INDEX_op_orc_i64
, { "r", "r", "r" } },
2100 { INDEX_op_eqv_i64
, { "r", "r", "r" } },
2101 { INDEX_op_nand_i64
, { "r", "r", "r" } },
2102 { INDEX_op_nor_i64
, { "r", "r", "r" } },
2104 { INDEX_op_shl_i64
, { "r", "r", "ri" } },
2105 { INDEX_op_shr_i64
, { "r", "r", "ri" } },
2106 { INDEX_op_sar_i64
, { "r", "r", "ri" } },
2107 { INDEX_op_rotl_i64
, { "r", "r", "ri" } },
2108 { INDEX_op_rotr_i64
, { "r", "r", "ri" } },
2110 { INDEX_op_mul_i64
, { "r", "r", "rI" } },
2111 { INDEX_op_div_i64
, { "r", "r", "r" } },
2112 { INDEX_op_divu_i64
, { "r", "r", "r" } },
2113 { INDEX_op_rem_i64
, { "r", "r", "r" } },
2114 { INDEX_op_remu_i64
, { "r", "r", "r" } },
2116 { INDEX_op_neg_i64
, { "r", "r" } },
2117 { INDEX_op_not_i64
, { "r", "r" } },
2119 { INDEX_op_qemu_ld8u
, { "r", "L" } },
2120 { INDEX_op_qemu_ld8s
, { "r", "L" } },
2121 { INDEX_op_qemu_ld16u
, { "r", "L" } },
2122 { INDEX_op_qemu_ld16s
, { "r", "L" } },
2123 { INDEX_op_qemu_ld32
, { "r", "L" } },
2124 { INDEX_op_qemu_ld32u
, { "r", "L" } },
2125 { INDEX_op_qemu_ld32s
, { "r", "L" } },
2126 { INDEX_op_qemu_ld64
, { "r", "L" } },
2128 { INDEX_op_qemu_st8
, { "S", "S" } },
2129 { INDEX_op_qemu_st16
, { "S", "S" } },
2130 { INDEX_op_qemu_st32
, { "S", "S" } },
2131 { INDEX_op_qemu_st64
, { "S", "S" } },
2133 { INDEX_op_ext8s_i32
, { "r", "r" } },
2134 { INDEX_op_ext16s_i32
, { "r", "r" } },
2135 { INDEX_op_ext8s_i64
, { "r", "r" } },
2136 { INDEX_op_ext16s_i64
, { "r", "r" } },
2137 { INDEX_op_ext32s_i64
, { "r", "r" } },
2139 { INDEX_op_setcond_i32
, { "r", "r", "ri" } },
2140 { INDEX_op_setcond_i64
, { "r", "r", "ri" } },
2141 { INDEX_op_movcond_i32
, { "r", "r", "ri", "rZ", "rZ" } },
2142 { INDEX_op_movcond_i64
, { "r", "r", "ri", "rZ", "rZ" } },
2144 { INDEX_op_bswap16_i32
, { "r", "r" } },
2145 { INDEX_op_bswap16_i64
, { "r", "r" } },
2146 { INDEX_op_bswap32_i32
, { "r", "r" } },
2147 { INDEX_op_bswap32_i64
, { "r", "r" } },
2148 { INDEX_op_bswap64_i64
, { "r", "r" } },
2150 { INDEX_op_deposit_i32
, { "r", "0", "rZ" } },
2151 { INDEX_op_deposit_i64
, { "r", "0", "rZ" } },
2153 { INDEX_op_add2_i64
, { "r", "r", "r", "rI", "r", "rZM" } },
2154 { INDEX_op_sub2_i64
, { "r", "r", "rI", "r", "rZM", "r" } },
2155 { INDEX_op_muls2_i64
, { "r", "r", "r", "r" } },
2156 { INDEX_op_mulu2_i64
, { "r", "r", "r", "r" } },
2161 static void tcg_target_init (TCGContext
*s
)
2163 #ifdef CONFIG_GETAUXVAL
2164 unsigned long hwcap
= getauxval(AT_HWCAP
);
2165 if (hwcap
& PPC_FEATURE_ARCH_2_06
) {
2166 have_isa_2_06
= true;
2170 tcg_regset_set32 (tcg_target_available_regs
[TCG_TYPE_I32
], 0, 0xffffffff);
2171 tcg_regset_set32 (tcg_target_available_regs
[TCG_TYPE_I64
], 0, 0xffffffff);
2172 tcg_regset_set32 (tcg_target_call_clobber_regs
, 0,
2184 (1 << TCG_REG_R10
) |
2185 (1 << TCG_REG_R11
) |
2189 tcg_regset_clear (s
->reserved_regs
);
2190 tcg_regset_set_reg (s
->reserved_regs
, TCG_REG_R0
);
2191 tcg_regset_set_reg (s
->reserved_regs
, TCG_REG_R1
);
2193 tcg_regset_set_reg (s
->reserved_regs
, TCG_REG_R2
);
2195 tcg_regset_set_reg (s
->reserved_regs
, TCG_REG_R13
);
2197 tcg_add_target_add_op_defs (ppc_op_defs
);