tcg/sparc/tcg-target.c

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #ifndef NDEBUG
  26 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
  27     "%g0",
  28     "%g1",
  29     "%g2",
  30     "%g3",
  31     "%g4",
  32     "%g5",
  33     "%g6",
  34     "%g7",
  35     "%o0",
  36     "%o1",
  37     "%o2",
  38     "%o3",
  39     "%o4",
  40     "%o5",
  41     "%o6",
  42     "%o7",
  43     "%l0",
  44     "%l1",
  45     "%l2",
  46     "%l3",
  47     "%l4",
  48     "%l5",
  49     "%l6",
  50     "%l7",
  51     "%i0",
  52     "%i1",
  53     "%i2",
  54     "%i3",
  55     "%i4",
  56     "%i5",
  57     "%i6",
  58     "%i7",
  59 };
  60 #endif
  61
  62 #define ARG_OFFSET 1
  63
  64 static const int tcg_target_reg_alloc_order[] = {
  65     TCG_REG_L0,
  66     TCG_REG_L1,
  67     TCG_REG_L2,
  68     TCG_REG_L3,
  69     TCG_REG_L4,
  70     TCG_REG_L5,
  71     TCG_REG_L6,
  72     TCG_REG_L7,
  73     TCG_REG_I0,
  74     TCG_REG_I1,
  75     TCG_REG_I2,
  76     TCG_REG_I3,
  77     TCG_REG_I4,
  78 };
  79
  80 static const int tcg_target_call_iarg_regs[6] = {
  81     TCG_REG_O0,
  82     TCG_REG_O1,
  83     TCG_REG_O2,
  84     TCG_REG_O3,
  85     TCG_REG_O4,
  86     TCG_REG_O5,
  87 };
  88
  89 static const int tcg_target_call_oarg_regs[] = {
  90     TCG_REG_O0,
  91     TCG_REG_O1,
  92     TCG_REG_O2,
  93     TCG_REG_O3,
  94 };
  95
  96 static inline int check_fit_tl(tcg_target_long val, unsigned int bits)
  97 {
  98     return (val << ((sizeof(tcg_target_long) * 8 - bits))
  99             >> (sizeof(tcg_target_long) * 8 - bits)) == val;
 100 }
 101
 102 static inline int check_fit_i32(uint32_t val, unsigned int bits)
 103 {
 104     return ((val << (32 - bits)) >> (32 - bits)) == val;
 105 }
 106
 107 static void patch_reloc(uint8_t *code_ptr, int type,
 108                         tcg_target_long value, tcg_target_long addend)
 109 {
 110     value += addend;
 111     switch (type) {
 112     case R_SPARC_32:
 113         if (value != (uint32_t)value)
 114             tcg_abort();
 115         *(uint32_t *)code_ptr = value;
 116         break;
 117     case R_SPARC_WDISP22:
 118         value -= (long)code_ptr;
 119         value >>= 2;
 120         if (!check_fit_tl(value, 22))
 121             tcg_abort();
 122         *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x3fffff) | value;
 123         break;
 124     case R_SPARC_WDISP19:
 125         value -= (long)code_ptr;
 126         value >>= 2;
 127         if (!check_fit_tl(value, 19))
 128             tcg_abort();
 129         *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x7ffff) | value;
 130         break;
 131     default:
 132         tcg_abort();
 133     }
 134 }
 135
 136 /* parse target specific constraints */
 137 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
 138 {
 139     const char *ct_str;
 140
 141     ct_str = *pct_str;
 142     switch (ct_str[0]) {
 143     case 'r':
 144         ct->ct |= TCG_CT_REG;
 145         tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
 146         break;
 147     case 'L': /* qemu_ld/st constraint */
 148         ct->ct |= TCG_CT_REG;
 149         tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
 150         // Helper args
 151         tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
 152         tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
 153         tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
 154         tcg_regset_reset_reg(ct->u.regs, TCG_REG_O3);
 155         break;
 156     case 'I':
 157         ct->ct |= TCG_CT_CONST_S11;
 158         break;
 159     case 'J':
 160         ct->ct |= TCG_CT_CONST_S13;
 161         break;
 162     default:
 163         return -1;
 164     }
 165     ct_str++;
 166     *pct_str = ct_str;
 167     return 0;
 168 }
 169
 170 /* test if a constant matches the constraint */
 171 static inline int tcg_target_const_match(tcg_target_long val,
 172                                          const TCGArgConstraint *arg_ct)
 173 {
 174     int ct;
 175
 176     ct = arg_ct->ct;
 177     if (ct & TCG_CT_CONST)
 178         return 1;
 179     else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11))
 180         return 1;
 181     else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13))
 182         return 1;
 183     else
 184         return 0;
 185 }
 186
 187 #define INSN_OP(x)  ((x) << 30)
 188 #define INSN_OP2(x) ((x) << 22)
 189 #define INSN_OP3(x) ((x) << 19)
 190 #define INSN_OPF(x) ((x) << 5)
 191 #define INSN_RD(x)  ((x) << 25)
 192 #define INSN_RS1(x) ((x) << 14)
 193 #define INSN_RS2(x) (x)
 194 #define INSN_ASI(x) ((x) << 5)
 195
 196 #define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff))
 197 #define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
 198 #define INSN_OFF19(x) (((x) >> 2) & 0x07ffff)
 199 #define INSN_OFF22(x) (((x) >> 2) & 0x3fffff)
 200
 201 #define INSN_COND(x, a) (((x) << 25) | ((a) << 29))
 202 #define COND_N     0x0
 203 #define COND_E     0x1
 204 #define COND_LE    0x2
 205 #define COND_L     0x3
 206 #define COND_LEU   0x4
 207 #define COND_CS    0x5
 208 #define COND_NEG   0x6
 209 #define COND_VS    0x7
 210 #define COND_A     0x8
 211 #define COND_NE    0x9
 212 #define COND_G     0xa
 213 #define COND_GE    0xb
 214 #define COND_GU    0xc
 215 #define COND_CC    0xd
 216 #define COND_POS   0xe
 217 #define COND_VC    0xf
 218 #define BA         (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2))
 219
 220 #define MOVCC_ICC  (1 << 18)
 221 #define MOVCC_XCC  (1 << 18 | 1 << 12)
 222
 223 #define ARITH_ADD  (INSN_OP(2) | INSN_OP3(0x00))
 224 #define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10))
 225 #define ARITH_AND  (INSN_OP(2) | INSN_OP3(0x01))
 226 #define ARITH_ANDN (INSN_OP(2) | INSN_OP3(0x05))
 227 #define ARITH_OR   (INSN_OP(2) | INSN_OP3(0x02))
 228 #define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12))
 229 #define ARITH_ORN  (INSN_OP(2) | INSN_OP3(0x06))
 230 #define ARITH_XOR  (INSN_OP(2) | INSN_OP3(0x03))
 231 #define ARITH_SUB  (INSN_OP(2) | INSN_OP3(0x04))
 232 #define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14))
 233 #define ARITH_ADDX (INSN_OP(2) | INSN_OP3(0x10))
 234 #define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c))
 235 #define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a))
 236 #define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e))
 237 #define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f))
 238 #define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09))
 239 #define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
 240 #define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
 241 #define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c))
 242
 243 #define SHIFT_SLL  (INSN_OP(2) | INSN_OP3(0x25))
 244 #define SHIFT_SRL  (INSN_OP(2) | INSN_OP3(0x26))
 245 #define SHIFT_SRA  (INSN_OP(2) | INSN_OP3(0x27))
 246
 247 #define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12))
 248 #define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12))
 249 #define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12))
 250
 251 #define RDY        (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(0))
 252 #define WRY        (INSN_OP(2) | INSN_OP3(0x30) | INSN_RD(0))
 253 #define JMPL       (INSN_OP(2) | INSN_OP3(0x38))
 254 #define SAVE       (INSN_OP(2) | INSN_OP3(0x3c))
 255 #define RESTORE    (INSN_OP(2) | INSN_OP3(0x3d))
 256 #define SETHI      (INSN_OP(0) | INSN_OP2(0x4))
 257 #define CALL       INSN_OP(1)
 258 #define LDUB       (INSN_OP(3) | INSN_OP3(0x01))
 259 #define LDSB       (INSN_OP(3) | INSN_OP3(0x09))
 260 #define LDUH       (INSN_OP(3) | INSN_OP3(0x02))
 261 #define LDSH       (INSN_OP(3) | INSN_OP3(0x0a))
 262 #define LDUW       (INSN_OP(3) | INSN_OP3(0x00))
 263 #define LDSW       (INSN_OP(3) | INSN_OP3(0x08))
 264 #define LDX        (INSN_OP(3) | INSN_OP3(0x0b))
 265 #define STB        (INSN_OP(3) | INSN_OP3(0x05))
 266 #define STH        (INSN_OP(3) | INSN_OP3(0x06))
 267 #define STW        (INSN_OP(3) | INSN_OP3(0x04))
 268 #define STX        (INSN_OP(3) | INSN_OP3(0x0e))
 269 #define LDUBA      (INSN_OP(3) | INSN_OP3(0x11))
 270 #define LDSBA      (INSN_OP(3) | INSN_OP3(0x19))
 271 #define LDUHA      (INSN_OP(3) | INSN_OP3(0x12))
 272 #define LDSHA      (INSN_OP(3) | INSN_OP3(0x1a))
 273 #define LDUWA      (INSN_OP(3) | INSN_OP3(0x10))
 274 #define LDSWA      (INSN_OP(3) | INSN_OP3(0x18))
 275 #define LDXA       (INSN_OP(3) | INSN_OP3(0x1b))
 276 #define STBA       (INSN_OP(3) | INSN_OP3(0x15))
 277 #define STHA       (INSN_OP(3) | INSN_OP3(0x16))
 278 #define STWA       (INSN_OP(3) | INSN_OP3(0x14))
 279 #define STXA       (INSN_OP(3) | INSN_OP3(0x1e))
 280
 281 #ifndef ASI_PRIMARY_LITTLE
 282 #define ASI_PRIMARY_LITTLE 0x88
 283 #endif
 284
 285 static inline void tcg_out_arith(TCGContext *s, int rd, int rs1, int rs2,
 286                                  int op)
 287 {
 288     tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
 289               INSN_RS2(rs2));
 290 }
 291
 292 static inline void tcg_out_arithi(TCGContext *s, int rd, int rs1,
 293                                   uint32_t offset, int op)
 294 {
 295     tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
 296               INSN_IMM13(offset));
 297 }
 298
 299 static void tcg_out_arithc(TCGContext *s, int rd, int rs1,
 300                            int val2, int val2const, int op)
 301 {
 302     tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1)
 303               | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2)));
 304 }
 305
 306 static inline void tcg_out_mov(TCGContext *s, TCGType type,
 307                                TCGReg ret, TCGReg arg)
 308 {
 309     tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR);
 310 }
 311
 312 static inline void tcg_out_sethi(TCGContext *s, int ret, uint32_t arg)
 313 {
 314     tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10));
 315 }
 316
 317 static inline void tcg_out_movi_imm13(TCGContext *s, int ret, uint32_t arg)
 318 {
 319     tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR);
 320 }
 321
 322 static inline void tcg_out_movi_imm32(TCGContext *s, int ret, uint32_t arg)
 323 {
 324     if (check_fit_tl(arg, 13))
 325         tcg_out_movi_imm13(s, ret, arg);
 326     else {
 327         tcg_out_sethi(s, ret, arg);
 328         if (arg & 0x3ff)
 329             tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
 330     }
 331 }
 332
 333 static inline void tcg_out_movi(TCGContext *s, TCGType type,
 334                                 TCGReg ret, tcg_target_long arg)
 335 {
 336     /* All 32-bit constants, as well as 64-bit constants with
 337        no high bits set go through movi_imm32.  */
 338     if (TCG_TARGET_REG_BITS == 32
 339         || type == TCG_TYPE_I32
 340         || (arg & ~(tcg_target_long)0xffffffff) == 0) {
 341         tcg_out_movi_imm32(s, ret, arg);
 342     } else if (check_fit_tl(arg, 13)) {
 343         /* A 13-bit constant sign-extended to 64-bits.  */
 344         tcg_out_movi_imm13(s, ret, arg);
 345     } else if (check_fit_tl(arg, 32)) {
 346         /* A 32-bit constant sign-extended to 64-bits.  */
 347         tcg_out_sethi(s, ret, ~arg);
 348         tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR);
 349     } else {
 350         tcg_out_movi_imm32(s, TCG_REG_I4, arg >> (TCG_TARGET_REG_BITS / 2));
 351         tcg_out_arithi(s, TCG_REG_I4, TCG_REG_I4, 32, SHIFT_SLLX);
 352         tcg_out_movi_imm32(s, ret, arg);
 353         tcg_out_arith(s, ret, ret, TCG_REG_I4, ARITH_OR);
 354     }
 355 }
 356
 357 static inline void tcg_out_ld_raw(TCGContext *s, int ret,
 358                                   tcg_target_long arg)
 359 {
 360     tcg_out_sethi(s, ret, arg);
 361     tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
 362               INSN_IMM13(arg & 0x3ff));
 363 }
 364
 365 static inline void tcg_out_ld_ptr(TCGContext *s, int ret,
 366                                   tcg_target_long arg)
 367 {
 368     if (!check_fit_tl(arg, 10))
 369         tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ffULL);
 370     if (TCG_TARGET_REG_BITS == 64) {
 371         tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) |
 372                   INSN_IMM13(arg & 0x3ff));
 373     } else {
 374         tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
 375                   INSN_IMM13(arg & 0x3ff));
 376     }
 377 }
 378
 379 static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, int op)
 380 {
 381     if (check_fit_tl(offset, 13))
 382         tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) |
 383                   INSN_IMM13(offset));
 384     else {
 385         tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset);
 386         tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
 387                   INSN_RS2(addr));
 388     }
 389 }
 390
 391 static inline void tcg_out_ldst_asi(TCGContext *s, int ret, int addr,
 392                                     int offset, int op, int asi)
 393 {
 394     tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset);
 395     tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
 396               INSN_ASI(asi) | INSN_RS2(addr));
 397 }
 398
 399 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
 400                               TCGReg arg1, tcg_target_long arg2)
 401 {
 402     if (type == TCG_TYPE_I32)
 403         tcg_out_ldst(s, ret, arg1, arg2, LDUW);
 404     else
 405         tcg_out_ldst(s, ret, arg1, arg2, LDX);
 406 }
 407
 408 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
 409                               TCGReg arg1, tcg_target_long arg2)
 410 {
 411     if (type == TCG_TYPE_I32)
 412         tcg_out_ldst(s, arg, arg1, arg2, STW);
 413     else
 414         tcg_out_ldst(s, arg, arg1, arg2, STX);
 415 }
 416
 417 static inline void tcg_out_sety(TCGContext *s, int rs)
 418 {
 419     tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs));
 420 }
 421
 422 static inline void tcg_out_rdy(TCGContext *s, int rd)
 423 {
 424     tcg_out32(s, RDY | INSN_RD(rd));
 425 }
 426
 427 static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
 428 {
 429     if (val != 0) {
 430         if (check_fit_tl(val, 13))
 431             tcg_out_arithi(s, reg, reg, val, ARITH_ADD);
 432         else {
 433             tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, val);
 434             tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_ADD);
 435         }
 436     }
 437 }
 438
 439 static inline void tcg_out_andi(TCGContext *s, int reg, tcg_target_long val)
 440 {
 441     if (val != 0) {
 442         if (check_fit_tl(val, 13))
 443             tcg_out_arithi(s, reg, reg, val, ARITH_AND);
 444         else {
 445             tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, val);
 446             tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_AND);
 447         }
 448     }
 449 }
 450
 451 static void tcg_out_div32(TCGContext *s, int rd, int rs1,
 452                           int val2, int val2const, int uns)
 453 {
 454     /* Load Y with the sign/zero extension of RS1 to 64-bits.  */
 455     if (uns) {
 456         tcg_out_sety(s, TCG_REG_G0);
 457     } else {
 458         tcg_out_arithi(s, TCG_REG_I5, rs1, 31, SHIFT_SRA);
 459         tcg_out_sety(s, TCG_REG_I5);
 460     }
 461
 462     tcg_out_arithc(s, rd, rs1, val2, val2const,
 463                    uns ? ARITH_UDIV : ARITH_SDIV);
 464 }
 465
 466 static inline void tcg_out_nop(TCGContext *s)
 467 {
 468     tcg_out_sethi(s, TCG_REG_G0, 0);
 469 }
 470
 471 static void tcg_out_branch_i32(TCGContext *s, int opc, int label_index)
 472 {
 473     TCGLabel *l = &s->labels[label_index];
 474
 475     if (l->has_value) {
 476         tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2)
 477                       | INSN_OFF22(l->u.value - (unsigned long)s->code_ptr)));
 478     } else {
 479         tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP22, label_index, 0);
 480         tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) | 0));
 481     }
 482 }
 483
 484 #if TCG_TARGET_REG_BITS == 64
 485 static void tcg_out_branch_i64(TCGContext *s, int opc, int label_index)
 486 {
 487     TCGLabel *l = &s->labels[label_index];
 488
 489     if (l->has_value) {
 490         tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) |
 491                       (0x5 << 19) |
 492                       INSN_OFF19(l->u.value - (unsigned long)s->code_ptr)));
 493     } else {
 494         tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, label_index, 0);
 495         tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) |
 496                       (0x5 << 19) | 0));
 497     }
 498 }
 499 #endif
 500
 501 static const uint8_t tcg_cond_to_bcond[10] = {
 502     [TCG_COND_EQ] = COND_E,
 503     [TCG_COND_NE] = COND_NE,
 504     [TCG_COND_LT] = COND_L,
 505     [TCG_COND_GE] = COND_GE,
 506     [TCG_COND_LE] = COND_LE,
 507     [TCG_COND_GT] = COND_G,
 508     [TCG_COND_LTU] = COND_CS,
 509     [TCG_COND_GEU] = COND_CC,
 510     [TCG_COND_LEU] = COND_LEU,
 511     [TCG_COND_GTU] = COND_GU,
 512 };
 513
 514 static void tcg_out_cmp(TCGContext *s, TCGArg c1, TCGArg c2, int c2const)
 515 {
 516     tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC);
 517 }
 518
 519 static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond,
 520                                TCGArg arg1, TCGArg arg2, int const_arg2,
 521                                int label_index)
 522 {
 523     tcg_out_cmp(s, arg1, arg2, const_arg2);
 524     tcg_out_branch_i32(s, tcg_cond_to_bcond[cond], label_index);
 525     tcg_out_nop(s);
 526 }
 527
 528 #if TCG_TARGET_REG_BITS == 64
 529 static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond,
 530                                TCGArg arg1, TCGArg arg2, int const_arg2,
 531                                int label_index)
 532 {
 533     tcg_out_cmp(s, arg1, arg2, const_arg2);
 534     tcg_out_branch_i64(s, tcg_cond_to_bcond[cond], label_index);
 535     tcg_out_nop(s);
 536 }
 537 #else
 538 static void tcg_out_brcond2_i32(TCGContext *s, TCGCond cond,
 539                                 TCGArg al, TCGArg ah,
 540                                 TCGArg bl, int blconst,
 541                                 TCGArg bh, int bhconst, int label_dest)
 542 {
 543     int cc, label_next = gen_new_label();
 544
 545     tcg_out_cmp(s, ah, bh, bhconst);
 546
 547     /* Note that we fill one of the delay slots with the second compare.  */
 548     switch (cond) {
 549     case TCG_COND_EQ:
 550         cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
 551         tcg_out_branch_i32(s, cc, label_next);
 552         tcg_out_cmp(s, al, bl, blconst);
 553         cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_EQ], 0);
 554         tcg_out_branch_i32(s, cc, label_dest);
 555         break;
 556
 557     case TCG_COND_NE:
 558         cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
 559         tcg_out_branch_i32(s, cc, label_dest);
 560         tcg_out_cmp(s, al, bl, blconst);
 561         tcg_out_branch_i32(s, cc, label_dest);
 562         break;
 563
 564     default:
 565         /* ??? One could fairly easily special-case 64-bit unsigned
 566            compares against 32-bit zero-extended constants.  For instance,
 567            we know that (unsigned)AH < 0 is false and need not emit it.
 568            Similarly, (unsigned)AH > 0 being true implies AH != 0, so the
 569            second branch will never be taken.  */
 570         cc = INSN_COND(tcg_cond_to_bcond[cond], 0);
 571         tcg_out_branch_i32(s, cc, label_dest);
 572         tcg_out_nop(s);
 573         cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
 574         tcg_out_branch_i32(s, cc, label_next);
 575         tcg_out_cmp(s, al, bl, blconst);
 576         cc = INSN_COND(tcg_cond_to_bcond[tcg_unsigned_cond(cond)], 0);
 577         tcg_out_branch_i32(s, cc, label_dest);
 578         break;
 579     }
 580     tcg_out_nop(s);
 581
 582     tcg_out_label(s, label_next, s->code_ptr);
 583 }
 584 #endif
 585
 586 static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGArg ret,
 587                                 TCGArg c1, TCGArg c2, int c2const)
 588 {
 589     TCGArg t;
 590
 591     /* For 32-bit comparisons, we can play games with ADDX/SUBX.  */
 592     switch (cond) {
 593     case TCG_COND_EQ:
 594     case TCG_COND_NE:
 595         if (c2 != 0) {
 596             tcg_out_arithc(s, ret, c1, c2, c2const, ARITH_XOR);
 597         }
 598         c1 = TCG_REG_G0, c2 = ret, c2const = 0;
 599         cond = (cond == TCG_COND_EQ ? TCG_COND_LEU : TCG_COND_LTU);
 600         break;
 601
 602     case TCG_COND_GTU:
 603     case TCG_COND_GEU:
 604         if (c2const && c2 != 0) {
 605             tcg_out_movi_imm13(s, TCG_REG_I5, c2);
 606             c2 = TCG_REG_I5;
 607         }
 608         t = c1, c1 = c2, c2 = t, c2const = 0;
 609         cond = tcg_swap_cond(cond);
 610         break;
 611
 612     case TCG_COND_LTU:
 613     case TCG_COND_LEU:
 614         break;
 615
 616     default:
 617         tcg_out_cmp(s, c1, c2, c2const);
 618 #if defined(__sparc_v9__) || defined(__sparc_v8plus__)
 619         tcg_out_movi_imm13(s, ret, 0);
 620         tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret)
 621                    | INSN_RS1(tcg_cond_to_bcond[cond])
 622                    | MOVCC_ICC | INSN_IMM11(1));
 623 #else
 624         t = gen_new_label();
 625         tcg_out_branch_i32(s, INSN_COND(tcg_cond_to_bcond[cond], 1), t);
 626         tcg_out_movi_imm13(s, ret, 1);
 627         tcg_out_movi_imm13(s, ret, 0);
 628         tcg_out_label(s, t, s->code_ptr);
 629 #endif
 630         return;
 631     }
 632
 633     tcg_out_cmp(s, c1, c2, c2const);
 634     if (cond == TCG_COND_LTU) {
 635         tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDX);
 636     } else {
 637         tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBX);
 638     }
 639 }
 640
 641 #if TCG_TARGET_REG_BITS == 64
 642 static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGArg ret,
 643                                 TCGArg c1, TCGArg c2, int c2const)
 644 {
 645     tcg_out_cmp(s, c1, c2, c2const);
 646     tcg_out_movi_imm13(s, ret, 0);
 647     tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret)
 648                | INSN_RS1(tcg_cond_to_bcond[cond])
 649                | MOVCC_XCC | INSN_IMM11(1));
 650 }
 651 #else
 652 static void tcg_out_setcond2_i32(TCGContext *s, TCGCond cond, TCGArg ret,
 653                                  TCGArg al, TCGArg ah,
 654                                  TCGArg bl, int blconst,
 655                                  TCGArg bh, int bhconst)
 656 {
 657     int lab;
 658
 659     switch (cond) {
 660     case TCG_COND_EQ:
 661         tcg_out_setcond_i32(s, TCG_COND_EQ, TCG_REG_I5, al, bl, blconst);
 662         tcg_out_setcond_i32(s, TCG_COND_EQ, ret, ah, bh, bhconst);
 663         tcg_out_arith(s, ret, ret, TCG_REG_I5, ARITH_AND);
 664         break;
 665
 666     case TCG_COND_NE:
 667         tcg_out_setcond_i32(s, TCG_COND_NE, TCG_REG_I5, al, al, blconst);
 668         tcg_out_setcond_i32(s, TCG_COND_NE, ret, ah, bh, bhconst);
 669         tcg_out_arith(s, ret, ret, TCG_REG_I5, ARITH_OR);
 670         break;
 671
 672     default:
 673         lab = gen_new_label();
 674
 675         tcg_out_cmp(s, ah, bh, bhconst);
 676         tcg_out_branch_i32(s, INSN_COND(tcg_cond_to_bcond[cond], 1), lab);
 677         tcg_out_movi_imm13(s, ret, 1);
 678         tcg_out_branch_i32(s, INSN_COND(COND_NE, 1), lab);
 679         tcg_out_movi_imm13(s, ret, 0);
 680
 681         tcg_out_setcond_i32(s, tcg_unsigned_cond(cond), ret, al, bl, blconst);
 682
 683         tcg_out_label(s, lab, s->code_ptr);
 684         break;
 685     }
 686 }
 687 #endif
 688
 689 /* Generate global QEMU prologue and epilogue code */
 690 static void tcg_target_qemu_prologue(TCGContext *s)
 691 {
 692     tcg_set_frame(s, TCG_REG_I6, TCG_TARGET_CALL_STACK_OFFSET,
 693                   CPU_TEMP_BUF_NLONGS * (int)sizeof(long));
 694     tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) |
 695               INSN_IMM13(-(TCG_TARGET_STACK_MINFRAME +
 696                            CPU_TEMP_BUF_NLONGS * (int)sizeof(long))));
 697     tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I1) |
 698               INSN_RS2(TCG_REG_G0));
 699     tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_I0);
 700 }
 701
 702 #if defined(CONFIG_SOFTMMU)
 703
 704 #include "../../softmmu_defs.h"
 705
 706 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
 707    int mmu_idx) */
 708 static const void * const qemu_ld_helpers[4] = {
 709     helper_ldb_mmu,
 710     helper_ldw_mmu,
 711     helper_ldl_mmu,
 712     helper_ldq_mmu,
 713 };
 714
 715 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
 716    uintxx_t val, int mmu_idx) */
 717 static const void * const qemu_st_helpers[4] = {
 718     helper_stb_mmu,
 719     helper_stw_mmu,
 720     helper_stl_mmu,
 721     helper_stq_mmu,
 722 };
 723 #endif
 724
 725 #if TARGET_LONG_BITS == 32
 726 #define TARGET_LD_OP LDUW
 727 #else
 728 #define TARGET_LD_OP LDX
 729 #endif
 730
 731 #if defined(CONFIG_SOFTMMU)
 732 #if HOST_LONG_BITS == 32
 733 #define TARGET_ADDEND_LD_OP LDUW
 734 #else
 735 #define TARGET_ADDEND_LD_OP LDX
 736 #endif
 737 #endif
 738
 739 #ifdef __arch64__
 740 #define HOST_LD_OP LDX
 741 #define HOST_ST_OP STX
 742 #define HOST_SLL_OP SHIFT_SLLX
 743 #define HOST_SRA_OP SHIFT_SRAX
 744 #else
 745 #define HOST_LD_OP LDUW
 746 #define HOST_ST_OP STW
 747 #define HOST_SLL_OP SHIFT_SLL
 748 #define HOST_SRA_OP SHIFT_SRA
 749 #endif
 750
 751 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
 752                             int opc)
 753 {
 754     int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
 755 #if defined(CONFIG_SOFTMMU)
 756     uint32_t *label1_ptr, *label2_ptr;
 757 #endif
 758
 759     data_reg = *args++;
 760     addr_reg = *args++;
 761     mem_index = *args;
 762     s_bits = opc & 3;
 763
 764     arg0 = TCG_REG_O0;
 765     arg1 = TCG_REG_O1;
 766     arg2 = TCG_REG_O2;
 767
 768 #if defined(CONFIG_SOFTMMU)
 769     /* srl addr_reg, x, arg1 */
 770     tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
 771                    SHIFT_SRL);
 772     /* and addr_reg, x, arg0 */
 773     tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
 774                    ARITH_AND);
 775
 776     /* and arg1, x, arg1 */
 777     tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
 778
 779     /* add arg1, x, arg1 */
 780     tcg_out_addi(s, arg1, offsetof(CPUArchState,
 781                                    tlb_table[mem_index][0].addr_read));
 782
 783     /* add env, arg1, arg1 */
 784     tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD);
 785
 786     /* ld [arg1], arg2 */
 787     tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) |
 788               INSN_RS2(TCG_REG_G0));
 789
 790     /* subcc arg0, arg2, %g0 */
 791     tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC);
 792
 793     /* will become:
 794        be label1
 795         or
 796        be,pt %xcc label1 */
 797     label1_ptr = (uint32_t *)s->code_ptr;
 798     tcg_out32(s, 0);
 799
 800     /* mov (delay slot) */
 801     tcg_out_mov(s, TCG_TYPE_PTR, arg0, addr_reg);
 802
 803     /* mov */
 804     tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index);
 805     /* XXX/FIXME: suboptimal */
 806     tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3],
 807                 tcg_target_call_iarg_regs[2]);
 808     tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[2],
 809                 tcg_target_call_iarg_regs[1]);
 810     tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1],
 811                 tcg_target_call_iarg_regs[0]);
 812     tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
 813                 TCG_AREG0);
 814
 815     /* XXX: move that code at the end of the TB */
 816     /* qemu_ld_helper[s_bits](arg0, arg1) */
 817     tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_ld_helpers[s_bits]
 818                            - (tcg_target_ulong)s->code_ptr) >> 2)
 819                          & 0x3fffffff));
 820     /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
 821        global registers */
 822     // delay slot
 823     tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
 824                  TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
 825                  sizeof(long), HOST_ST_OP);
 826     tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
 827                  TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
 828                  sizeof(long), HOST_LD_OP);
 829
 830     /* data_reg = sign_extend(arg0) */
 831     switch(opc) {
 832     case 0 | 4:
 833         /* sll arg0, 24/56, data_reg */
 834         tcg_out_arithi(s, data_reg, arg0, (int)sizeof(tcg_target_long) * 8 - 8,
 835                        HOST_SLL_OP);
 836         /* sra data_reg, 24/56, data_reg */
 837         tcg_out_arithi(s, data_reg, data_reg,
 838                        (int)sizeof(tcg_target_long) * 8 - 8, HOST_SRA_OP);
 839         break;
 840     case 1 | 4:
 841         /* sll arg0, 16/48, data_reg */
 842         tcg_out_arithi(s, data_reg, arg0,
 843                        (int)sizeof(tcg_target_long) * 8 - 16, HOST_SLL_OP);
 844         /* sra data_reg, 16/48, data_reg */
 845         tcg_out_arithi(s, data_reg, data_reg,
 846                        (int)sizeof(tcg_target_long) * 8 - 16, HOST_SRA_OP);
 847         break;
 848     case 2 | 4:
 849         /* sll arg0, 32, data_reg */
 850         tcg_out_arithi(s, data_reg, arg0, 32, HOST_SLL_OP);
 851         /* sra data_reg, 32, data_reg */
 852         tcg_out_arithi(s, data_reg, data_reg, 32, HOST_SRA_OP);
 853         break;
 854     case 0:
 855     case 1:
 856     case 2:
 857     case 3:
 858     default:
 859         /* mov */
 860         tcg_out_mov(s, TCG_TYPE_REG, data_reg, arg0);
 861         break;
 862     }
 863
 864     /* will become:
 865        ba label2 */
 866     label2_ptr = (uint32_t *)s->code_ptr;
 867     tcg_out32(s, 0);
 868
 869     /* nop (delay slot */
 870     tcg_out_nop(s);
 871
 872     /* label1: */
 873 #if TARGET_LONG_BITS == 32
 874     /* be label1 */
 875     *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) |
 876                    INSN_OFF22((unsigned long)s->code_ptr -
 877                               (unsigned long)label1_ptr));
 878 #else
 879     /* be,pt %xcc label1 */
 880     *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1) |
 881                    (0x5 << 19) | INSN_OFF19((unsigned long)s->code_ptr -
 882                               (unsigned long)label1_ptr));
 883 #endif
 884
 885     /* ld [arg1 + x], arg1 */
 886     tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) -
 887                  offsetof(CPUTLBEntry, addr_read), TARGET_ADDEND_LD_OP);
 888
 889 #if TARGET_LONG_BITS == 32
 890     /* and addr_reg, x, arg0 */
 891     tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
 892     tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND);
 893     /* add arg0, arg1, arg0 */
 894     tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD);
 895 #else
 896     /* add addr_reg, arg1, arg0 */
 897     tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD);
 898 #endif
 899
 900 #else
 901     arg0 = addr_reg;
 902 #endif
 903
 904     switch(opc) {
 905     case 0:
 906         /* ldub [arg0], data_reg */
 907         tcg_out_ldst(s, data_reg, arg0, 0, LDUB);
 908         break;
 909     case 0 | 4:
 910         /* ldsb [arg0], data_reg */
 911         tcg_out_ldst(s, data_reg, arg0, 0, LDSB);
 912         break;
 913     case 1:
 914 #ifdef TARGET_WORDS_BIGENDIAN
 915         /* lduh [arg0], data_reg */
 916         tcg_out_ldst(s, data_reg, arg0, 0, LDUH);
 917 #else
 918         /* lduha [arg0] ASI_PRIMARY_LITTLE, data_reg */
 919         tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUHA, ASI_PRIMARY_LITTLE);
 920 #endif
 921         break;
 922     case 1 | 4:
 923 #ifdef TARGET_WORDS_BIGENDIAN
 924         /* ldsh [arg0], data_reg */
 925         tcg_out_ldst(s, data_reg, arg0, 0, LDSH);
 926 #else
 927         /* ldsha [arg0] ASI_PRIMARY_LITTLE, data_reg */
 928         tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSHA, ASI_PRIMARY_LITTLE);
 929 #endif
 930         break;
 931     case 2:
 932 #ifdef TARGET_WORDS_BIGENDIAN
 933         /* lduw [arg0], data_reg */
 934         tcg_out_ldst(s, data_reg, arg0, 0, LDUW);
 935 #else
 936         /* lduwa [arg0] ASI_PRIMARY_LITTLE, data_reg */
 937         tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUWA, ASI_PRIMARY_LITTLE);
 938 #endif
 939         break;
 940     case 2 | 4:
 941 #ifdef TARGET_WORDS_BIGENDIAN
 942         /* ldsw [arg0], data_reg */
 943         tcg_out_ldst(s, data_reg, arg0, 0, LDSW);
 944 #else
 945         /* ldswa [arg0] ASI_PRIMARY_LITTLE, data_reg */
 946         tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSWA, ASI_PRIMARY_LITTLE);
 947 #endif
 948         break;
 949     case 3:
 950 #ifdef TARGET_WORDS_BIGENDIAN
 951         /* ldx [arg0], data_reg */
 952         tcg_out_ldst(s, data_reg, arg0, 0, LDX);
 953 #else
 954         /* ldxa [arg0] ASI_PRIMARY_LITTLE, data_reg */
 955         tcg_out_ldst_asi(s, data_reg, arg0, 0, LDXA, ASI_PRIMARY_LITTLE);
 956 #endif
 957         break;
 958     default:
 959         tcg_abort();
 960     }
 961
 962 #if defined(CONFIG_SOFTMMU)
 963     /* label2: */
 964     *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
 965                    INSN_OFF22((unsigned long)s->code_ptr -
 966                               (unsigned long)label2_ptr));
 967 #endif
 968 }
 969
 970 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
 971                             int opc)
 972 {
 973     int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
 974 #if defined(CONFIG_SOFTMMU)
 975     uint32_t *label1_ptr, *label2_ptr;
 976 #endif
 977
 978     data_reg = *args++;
 979     addr_reg = *args++;
 980     mem_index = *args;
 981
 982     s_bits = opc;
 983
 984     arg0 = TCG_REG_O0;
 985     arg1 = TCG_REG_O1;
 986     arg2 = TCG_REG_O2;
 987
 988 #if defined(CONFIG_SOFTMMU)
 989     /* srl addr_reg, x, arg1 */
 990     tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
 991                    SHIFT_SRL);
 992
 993     /* and addr_reg, x, arg0 */
 994     tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
 995                    ARITH_AND);
 996
 997     /* and arg1, x, arg1 */
 998     tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
 999
1000     /* add arg1, x, arg1 */
1001     tcg_out_addi(s, arg1, offsetof(CPUArchState,
1002                                    tlb_table[mem_index][0].addr_write));
1003
1004     /* add env, arg1, arg1 */
1005     tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD);
1006
1007     /* ld [arg1], arg2 */
1008     tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) |
1009               INSN_RS2(TCG_REG_G0));
1010
1011     /* subcc arg0, arg2, %g0 */
1012     tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC);
1013
1014     /* will become:
1015        be label1
1016         or
1017        be,pt %xcc label1 */
1018     label1_ptr = (uint32_t *)s->code_ptr;
1019     tcg_out32(s, 0);
1020
1021     /* mov (delay slot) */
1022     tcg_out_mov(s, TCG_TYPE_PTR, arg0, addr_reg);
1023
1024     /* mov */
1025     tcg_out_mov(s, TCG_TYPE_REG, arg1, data_reg);
1026
1027     /* mov */
1028     tcg_out_movi(s, TCG_TYPE_I32, arg2, mem_index);
1029
1030     /* XXX/FIXME: suboptimal */
1031     tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3],
1032                 tcg_target_call_iarg_regs[2]);
1033     tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[2],
1034                 tcg_target_call_iarg_regs[1]);
1035     tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1],
1036                 tcg_target_call_iarg_regs[0]);
1037     tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
1038                 TCG_AREG0);
1039     /* XXX: move that code at the end of the TB */
1040     /* qemu_st_helper[s_bits](arg0, arg1, arg2) */
1041     tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_st_helpers[s_bits]
1042                            - (tcg_target_ulong)s->code_ptr) >> 2)
1043                          & 0x3fffffff));
1044     /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
1045        global registers */
1046     // delay slot
1047     tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
1048                  TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
1049                  sizeof(long), HOST_ST_OP);
1050     tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
1051                  TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
1052                  sizeof(long), HOST_LD_OP);
1053
1054     /* will become:
1055        ba label2 */
1056     label2_ptr = (uint32_t *)s->code_ptr;
1057     tcg_out32(s, 0);
1058
1059     /* nop (delay slot) */
1060     tcg_out_nop(s);
1061
1062 #if TARGET_LONG_BITS == 32
1063     /* be label1 */
1064     *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) |
1065                    INSN_OFF22((unsigned long)s->code_ptr -
1066                               (unsigned long)label1_ptr));
1067 #else
1068     /* be,pt %xcc label1 */
1069     *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1) |
1070                    (0x5 << 19) | INSN_OFF19((unsigned long)s->code_ptr -
1071                               (unsigned long)label1_ptr));
1072 #endif
1073
1074     /* ld [arg1 + x], arg1 */
1075     tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) -
1076                  offsetof(CPUTLBEntry, addr_write), TARGET_ADDEND_LD_OP);
1077
1078 #if TARGET_LONG_BITS == 32
1079     /* and addr_reg, x, arg0 */
1080     tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
1081     tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND);
1082     /* add arg0, arg1, arg0 */
1083     tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD);
1084 #else
1085     /* add addr_reg, arg1, arg0 */
1086     tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD);
1087 #endif
1088
1089 #else
1090     arg0 = addr_reg;
1091 #endif
1092
1093     switch(opc) {
1094     case 0:
1095         /* stb data_reg, [arg0] */
1096         tcg_out_ldst(s, data_reg, arg0, 0, STB);
1097         break;
1098     case 1:
1099 #ifdef TARGET_WORDS_BIGENDIAN
1100         /* sth data_reg, [arg0] */
1101         tcg_out_ldst(s, data_reg, arg0, 0, STH);
1102 #else
1103         /* stha data_reg, [arg0] ASI_PRIMARY_LITTLE */
1104         tcg_out_ldst_asi(s, data_reg, arg0, 0, STHA, ASI_PRIMARY_LITTLE);
1105 #endif
1106         break;
1107     case 2:
1108 #ifdef TARGET_WORDS_BIGENDIAN
1109         /* stw data_reg, [arg0] */
1110         tcg_out_ldst(s, data_reg, arg0, 0, STW);
1111 #else
1112         /* stwa data_reg, [arg0] ASI_PRIMARY_LITTLE */
1113         tcg_out_ldst_asi(s, data_reg, arg0, 0, STWA, ASI_PRIMARY_LITTLE);
1114 #endif
1115         break;
1116     case 3:
1117 #ifdef TARGET_WORDS_BIGENDIAN
1118         /* stx data_reg, [arg0] */
1119         tcg_out_ldst(s, data_reg, arg0, 0, STX);
1120 #else
1121         /* stxa data_reg, [arg0] ASI_PRIMARY_LITTLE */
1122         tcg_out_ldst_asi(s, data_reg, arg0, 0, STXA, ASI_PRIMARY_LITTLE);
1123 #endif
1124         break;
1125     default:
1126         tcg_abort();
1127     }
1128
1129 #if defined(CONFIG_SOFTMMU)
1130     /* label2: */
1131     *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
1132                    INSN_OFF22((unsigned long)s->code_ptr -
1133                               (unsigned long)label2_ptr));
1134 #endif
1135 }
1136
1137 static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
1138                               const int *const_args)
1139 {
1140     int c;
1141
1142     switch (opc) {
1143     case INDEX_op_exit_tb:
1144         tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, args[0]);
1145         tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I7) |
1146                   INSN_IMM13(8));
1147         tcg_out32(s, RESTORE | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_G0) |
1148                       INSN_RS2(TCG_REG_G0));
1149         break;
1150     case INDEX_op_goto_tb:
1151         if (s->tb_jmp_offset) {
1152             /* direct jump method */
1153             tcg_out_sethi(s, TCG_REG_I5, args[0] & 0xffffe000);
1154             tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
1155                       INSN_IMM13((args[0] & 0x1fff)));
1156             s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1157         } else {
1158             /* indirect jump method */
1159             tcg_out_ld_ptr(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
1160             tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
1161                       INSN_RS2(TCG_REG_G0));
1162         }
1163         tcg_out_nop(s);
1164         s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1165         break;
1166     case INDEX_op_call:
1167         if (const_args[0])
1168             tcg_out32(s, CALL | ((((tcg_target_ulong)args[0]
1169                                    - (tcg_target_ulong)s->code_ptr) >> 2)
1170                                  & 0x3fffffff));
1171         else {
1172             tcg_out_ld_ptr(s, TCG_REG_I5,
1173                            (tcg_target_long)(s->tb_next + args[0]));
1174             tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_I5) |
1175                       INSN_RS2(TCG_REG_G0));
1176         }
1177         /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
1178            global registers */
1179         // delay slot
1180         tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
1181                      TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
1182                      sizeof(long), HOST_ST_OP);
1183         tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
1184                      TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
1185                      sizeof(long), HOST_LD_OP);
1186         break;
1187     case INDEX_op_jmp:
1188     case INDEX_op_br:
1189         tcg_out_branch_i32(s, COND_A, args[0]);
1190         tcg_out_nop(s);
1191         break;
1192     case INDEX_op_movi_i32:
1193         tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
1194         break;
1195
1196 #if TCG_TARGET_REG_BITS == 64
1197 #define OP_32_64(x)                             \
1198         glue(glue(case INDEX_op_, x), _i32):    \
1199         glue(glue(case INDEX_op_, x), _i64)
1200 #else
1201 #define OP_32_64(x)                             \
1202         glue(glue(case INDEX_op_, x), _i32)
1203 #endif
1204     OP_32_64(ld8u):
1205         tcg_out_ldst(s, args[0], args[1], args[2], LDUB);
1206         break;
1207     OP_32_64(ld8s):
1208         tcg_out_ldst(s, args[0], args[1], args[2], LDSB);
1209         break;
1210     OP_32_64(ld16u):
1211         tcg_out_ldst(s, args[0], args[1], args[2], LDUH);
1212         break;
1213     OP_32_64(ld16s):
1214         tcg_out_ldst(s, args[0], args[1], args[2], LDSH);
1215         break;
1216     case INDEX_op_ld_i32:
1217 #if TCG_TARGET_REG_BITS == 64
1218     case INDEX_op_ld32u_i64:
1219 #endif
1220         tcg_out_ldst(s, args[0], args[1], args[2], LDUW);
1221         break;
1222     OP_32_64(st8):
1223         tcg_out_ldst(s, args[0], args[1], args[2], STB);
1224         break;
1225     OP_32_64(st16):
1226         tcg_out_ldst(s, args[0], args[1], args[2], STH);
1227         break;
1228     case INDEX_op_st_i32:
1229 #if TCG_TARGET_REG_BITS == 64
1230     case INDEX_op_st32_i64:
1231 #endif
1232         tcg_out_ldst(s, args[0], args[1], args[2], STW);
1233         break;
1234     OP_32_64(add):
1235         c = ARITH_ADD;
1236         goto gen_arith;
1237     OP_32_64(sub):
1238         c = ARITH_SUB;
1239         goto gen_arith;
1240     OP_32_64(and):
1241         c = ARITH_AND;
1242         goto gen_arith;
1243     OP_32_64(andc):
1244         c = ARITH_ANDN;
1245         goto gen_arith;
1246     OP_32_64(or):
1247         c = ARITH_OR;
1248         goto gen_arith;
1249     OP_32_64(orc):
1250         c = ARITH_ORN;
1251         goto gen_arith;
1252     OP_32_64(xor):
1253         c = ARITH_XOR;
1254         goto gen_arith;
1255     case INDEX_op_shl_i32:
1256         c = SHIFT_SLL;
1257         goto gen_arith;
1258     case INDEX_op_shr_i32:
1259         c = SHIFT_SRL;
1260         goto gen_arith;
1261     case INDEX_op_sar_i32:
1262         c = SHIFT_SRA;
1263         goto gen_arith;
1264     case INDEX_op_mul_i32:
1265         c = ARITH_UMUL;
1266         goto gen_arith;
1267
1268     OP_32_64(neg):
1269         c = ARITH_SUB;
1270         goto gen_arith1;
1271     OP_32_64(not):
1272         c = ARITH_ORN;
1273         goto gen_arith1;
1274
1275     case INDEX_op_div_i32:
1276         tcg_out_div32(s, args[0], args[1], args[2], const_args[2], 0);
1277         break;
1278     case INDEX_op_divu_i32:
1279         tcg_out_div32(s, args[0], args[1], args[2], const_args[2], 1);
1280         break;
1281
1282     case INDEX_op_rem_i32:
1283     case INDEX_op_remu_i32:
1284         tcg_out_div32(s, TCG_REG_I5, args[1], args[2], const_args[2],
1285                       opc == INDEX_op_remu_i32);
1286         tcg_out_arithc(s, TCG_REG_I5, TCG_REG_I5, args[2], const_args[2],
1287                        ARITH_UMUL);
1288         tcg_out_arith(s, args[0], args[1], TCG_REG_I5, ARITH_SUB);
1289         break;
1290
1291     case INDEX_op_brcond_i32:
1292         tcg_out_brcond_i32(s, args[2], args[0], args[1], const_args[1],
1293                            args[3]);
1294         break;
1295     case INDEX_op_setcond_i32:
1296         tcg_out_setcond_i32(s, args[3], args[0], args[1],
1297                             args[2], const_args[2]);
1298         break;
1299
1300 #if TCG_TARGET_REG_BITS == 32
1301     case INDEX_op_brcond2_i32:
1302         tcg_out_brcond2_i32(s, args[4], args[0], args[1],
1303                             args[2], const_args[2],
1304                             args[3], const_args[3], args[5]);
1305         break;
1306     case INDEX_op_setcond2_i32:
1307         tcg_out_setcond2_i32(s, args[5], args[0], args[1], args[2],
1308                              args[3], const_args[3],
1309                              args[4], const_args[4]);
1310         break;
1311     case INDEX_op_add2_i32:
1312         tcg_out_arithc(s, args[0], args[2], args[4], const_args[4],
1313                        ARITH_ADDCC);
1314         tcg_out_arithc(s, args[1], args[3], args[5], const_args[5],
1315                        ARITH_ADDX);
1316         break;
1317     case INDEX_op_sub2_i32:
1318         tcg_out_arithc(s, args[0], args[2], args[4], const_args[4],
1319                        ARITH_SUBCC);
1320         tcg_out_arithc(s, args[1], args[3], args[5], const_args[5],
1321                        ARITH_SUBX);
1322         break;
1323     case INDEX_op_mulu2_i32:
1324         tcg_out_arithc(s, args[0], args[2], args[3], const_args[3],
1325                        ARITH_UMUL);
1326         tcg_out_rdy(s, args[1]);
1327         break;
1328 #endif
1329
1330     case INDEX_op_qemu_ld8u:
1331         tcg_out_qemu_ld(s, args, 0);
1332         break;
1333     case INDEX_op_qemu_ld8s:
1334         tcg_out_qemu_ld(s, args, 0 | 4);
1335         break;
1336     case INDEX_op_qemu_ld16u:
1337         tcg_out_qemu_ld(s, args, 1);
1338         break;
1339     case INDEX_op_qemu_ld16s:
1340         tcg_out_qemu_ld(s, args, 1 | 4);
1341         break;
1342     case INDEX_op_qemu_ld32:
1343 #if TCG_TARGET_REG_BITS == 64
1344     case INDEX_op_qemu_ld32u:
1345 #endif
1346         tcg_out_qemu_ld(s, args, 2);
1347         break;
1348 #if TCG_TARGET_REG_BITS == 64
1349     case INDEX_op_qemu_ld32s:
1350         tcg_out_qemu_ld(s, args, 2 | 4);
1351         break;
1352 #endif
1353     case INDEX_op_qemu_st8:
1354         tcg_out_qemu_st(s, args, 0);
1355         break;
1356     case INDEX_op_qemu_st16:
1357         tcg_out_qemu_st(s, args, 1);
1358         break;
1359     case INDEX_op_qemu_st32:
1360         tcg_out_qemu_st(s, args, 2);
1361         break;
1362
1363 #if TCG_TARGET_REG_BITS == 64
1364     case INDEX_op_movi_i64:
1365         tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
1366         break;
1367     case INDEX_op_ld32s_i64:
1368         tcg_out_ldst(s, args[0], args[1], args[2], LDSW);
1369         break;
1370     case INDEX_op_ld_i64:
1371         tcg_out_ldst(s, args[0], args[1], args[2], LDX);
1372         break;
1373     case INDEX_op_st_i64:
1374         tcg_out_ldst(s, args[0], args[1], args[2], STX);
1375         break;
1376     case INDEX_op_shl_i64:
1377         c = SHIFT_SLLX;
1378         goto gen_arith;
1379     case INDEX_op_shr_i64:
1380         c = SHIFT_SRLX;
1381         goto gen_arith;
1382     case INDEX_op_sar_i64:
1383         c = SHIFT_SRAX;
1384         goto gen_arith;
1385     case INDEX_op_mul_i64:
1386         c = ARITH_MULX;
1387         goto gen_arith;
1388     case INDEX_op_div_i64:
1389         c = ARITH_SDIVX;
1390         goto gen_arith;
1391     case INDEX_op_divu_i64:
1392         c = ARITH_UDIVX;
1393         goto gen_arith;
1394     case INDEX_op_rem_i64:
1395     case INDEX_op_remu_i64:
1396         tcg_out_arithc(s, TCG_REG_I5, args[1], args[2], const_args[2],
1397                        opc == INDEX_op_rem_i64 ? ARITH_SDIVX : ARITH_UDIVX);
1398         tcg_out_arithc(s, TCG_REG_I5, TCG_REG_I5, args[2], const_args[2],
1399                        ARITH_MULX);
1400         tcg_out_arith(s, args[0], args[1], TCG_REG_I5, ARITH_SUB);
1401         break;
1402     case INDEX_op_ext32s_i64:
1403         if (const_args[1]) {
1404             tcg_out_movi(s, TCG_TYPE_I64, args[0], (int32_t)args[1]);
1405         } else {
1406             tcg_out_arithi(s, args[0], args[1], 0, SHIFT_SRA);
1407         }
1408         break;
1409     case INDEX_op_ext32u_i64:
1410         if (const_args[1]) {
1411             tcg_out_movi_imm32(s, args[0], args[1]);
1412         } else {
1413             tcg_out_arithi(s, args[0], args[1], 0, SHIFT_SRL);
1414         }
1415         break;
1416
1417     case INDEX_op_brcond_i64:
1418         tcg_out_brcond_i64(s, args[2], args[0], args[1], const_args[1],
1419                            args[3]);
1420         break;
1421     case INDEX_op_setcond_i64:
1422         tcg_out_setcond_i64(s, args[3], args[0], args[1],
1423                             args[2], const_args[2]);
1424         break;
1425
1426     case INDEX_op_qemu_ld64:
1427         tcg_out_qemu_ld(s, args, 3);
1428         break;
1429     case INDEX_op_qemu_st64:
1430         tcg_out_qemu_st(s, args, 3);
1431         break;
1432
1433 #endif
1434     gen_arith:
1435         tcg_out_arithc(s, args[0], args[1], args[2], const_args[2], c);
1436         break;
1437
1438     gen_arith1:
1439         tcg_out_arithc(s, args[0], TCG_REG_G0, args[1], const_args[1], c);
1440         break;
1441
1442     default:
1443         fprintf(stderr, "unknown opcode 0x%x\n", opc);
1444         tcg_abort();
1445     }
1446 }
1447
1448 static const TCGTargetOpDef sparc_op_defs[] = {
1449     { INDEX_op_exit_tb, { } },
1450     { INDEX_op_goto_tb, { } },
1451     { INDEX_op_call, { "ri" } },
1452     { INDEX_op_jmp, { "ri" } },
1453     { INDEX_op_br, { } },
1454
1455     { INDEX_op_mov_i32, { "r", "r" } },
1456     { INDEX_op_movi_i32, { "r" } },
1457     { INDEX_op_ld8u_i32, { "r", "r" } },
1458     { INDEX_op_ld8s_i32, { "r", "r" } },
1459     { INDEX_op_ld16u_i32, { "r", "r" } },
1460     { INDEX_op_ld16s_i32, { "r", "r" } },
1461     { INDEX_op_ld_i32, { "r", "r" } },
1462     { INDEX_op_st8_i32, { "r", "r" } },
1463     { INDEX_op_st16_i32, { "r", "r" } },
1464     { INDEX_op_st_i32, { "r", "r" } },
1465
1466     { INDEX_op_add_i32, { "r", "r", "rJ" } },
1467     { INDEX_op_mul_i32, { "r", "r", "rJ" } },
1468     { INDEX_op_div_i32, { "r", "r", "rJ" } },
1469     { INDEX_op_divu_i32, { "r", "r", "rJ" } },
1470     { INDEX_op_rem_i32, { "r", "r", "rJ" } },
1471     { INDEX_op_remu_i32, { "r", "r", "rJ" } },
1472     { INDEX_op_sub_i32, { "r", "r", "rJ" } },
1473     { INDEX_op_and_i32, { "r", "r", "rJ" } },
1474     { INDEX_op_andc_i32, { "r", "r", "rJ" } },
1475     { INDEX_op_or_i32, { "r", "r", "rJ" } },
1476     { INDEX_op_orc_i32, { "r", "r", "rJ" } },
1477     { INDEX_op_xor_i32, { "r", "r", "rJ" } },
1478
1479     { INDEX_op_shl_i32, { "r", "r", "rJ" } },
1480     { INDEX_op_shr_i32, { "r", "r", "rJ" } },
1481     { INDEX_op_sar_i32, { "r", "r", "rJ" } },
1482
1483     { INDEX_op_neg_i32, { "r", "rJ" } },
1484     { INDEX_op_not_i32, { "r", "rJ" } },
1485
1486     { INDEX_op_brcond_i32, { "r", "rJ" } },
1487     { INDEX_op_setcond_i32, { "r", "r", "rJ" } },
1488
1489 #if TCG_TARGET_REG_BITS == 32
1490     { INDEX_op_brcond2_i32, { "r", "r", "rJ", "rJ" } },
1491     { INDEX_op_setcond2_i32, { "r", "r", "r", "rJ", "rJ" } },
1492     { INDEX_op_add2_i32, { "r", "r", "r", "r", "rJ", "rJ" } },
1493     { INDEX_op_sub2_i32, { "r", "r", "r", "r", "rJ", "rJ" } },
1494     { INDEX_op_mulu2_i32, { "r", "r", "r", "rJ" } },
1495 #endif
1496
1497     { INDEX_op_qemu_ld8u, { "r", "L" } },
1498     { INDEX_op_qemu_ld8s, { "r", "L" } },
1499     { INDEX_op_qemu_ld16u, { "r", "L" } },
1500     { INDEX_op_qemu_ld16s, { "r", "L" } },
1501     { INDEX_op_qemu_ld32, { "r", "L" } },
1502 #if TCG_TARGET_REG_BITS == 64
1503     { INDEX_op_qemu_ld32u, { "r", "L" } },
1504     { INDEX_op_qemu_ld32s, { "r", "L" } },
1505 #endif
1506
1507     { INDEX_op_qemu_st8, { "L", "L" } },
1508     { INDEX_op_qemu_st16, { "L", "L" } },
1509     { INDEX_op_qemu_st32, { "L", "L" } },
1510
1511 #if TCG_TARGET_REG_BITS == 64
1512     { INDEX_op_mov_i64, { "r", "r" } },
1513     { INDEX_op_movi_i64, { "r" } },
1514     { INDEX_op_ld8u_i64, { "r", "r" } },
1515     { INDEX_op_ld8s_i64, { "r", "r" } },
1516     { INDEX_op_ld16u_i64, { "r", "r" } },
1517     { INDEX_op_ld16s_i64, { "r", "r" } },
1518     { INDEX_op_ld32u_i64, { "r", "r" } },
1519     { INDEX_op_ld32s_i64, { "r", "r" } },
1520     { INDEX_op_ld_i64, { "r", "r" } },
1521     { INDEX_op_st8_i64, { "r", "r" } },
1522     { INDEX_op_st16_i64, { "r", "r" } },
1523     { INDEX_op_st32_i64, { "r", "r" } },
1524     { INDEX_op_st_i64, { "r", "r" } },
1525     { INDEX_op_qemu_ld64, { "L", "L" } },
1526     { INDEX_op_qemu_st64, { "L", "L" } },
1527
1528     { INDEX_op_add_i64, { "r", "r", "rJ" } },
1529     { INDEX_op_mul_i64, { "r", "r", "rJ" } },
1530     { INDEX_op_div_i64, { "r", "r", "rJ" } },
1531     { INDEX_op_divu_i64, { "r", "r", "rJ" } },
1532     { INDEX_op_rem_i64, { "r", "r", "rJ" } },
1533     { INDEX_op_remu_i64, { "r", "r", "rJ" } },
1534     { INDEX_op_sub_i64, { "r", "r", "rJ" } },
1535     { INDEX_op_and_i64, { "r", "r", "rJ" } },
1536     { INDEX_op_andc_i64, { "r", "r", "rJ" } },
1537     { INDEX_op_or_i64, { "r", "r", "rJ" } },
1538     { INDEX_op_orc_i64, { "r", "r", "rJ" } },
1539     { INDEX_op_xor_i64, { "r", "r", "rJ" } },
1540
1541     { INDEX_op_shl_i64, { "r", "r", "rJ" } },
1542     { INDEX_op_shr_i64, { "r", "r", "rJ" } },
1543     { INDEX_op_sar_i64, { "r", "r", "rJ" } },
1544
1545     { INDEX_op_neg_i64, { "r", "rJ" } },
1546     { INDEX_op_not_i64, { "r", "rJ" } },
1547
1548     { INDEX_op_ext32s_i64, { "r", "ri" } },
1549     { INDEX_op_ext32u_i64, { "r", "ri" } },
1550
1551     { INDEX_op_brcond_i64, { "r", "rJ" } },
1552     { INDEX_op_setcond_i64, { "r", "r", "rJ" } },
1553 #endif
1554     { -1 },
1555 };
1556
1557 static void tcg_target_init(TCGContext *s)
1558 {
1559     tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1560 #if TCG_TARGET_REG_BITS == 64
1561     tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
1562 #endif
1563     tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1564                      (1 << TCG_REG_G1) |
1565                      (1 << TCG_REG_G2) |
1566                      (1 << TCG_REG_G3) |
1567                      (1 << TCG_REG_G4) |
1568                      (1 << TCG_REG_G5) |
1569                      (1 << TCG_REG_G6) |
1570                      (1 << TCG_REG_G7) |
1571                      (1 << TCG_REG_O0) |
1572                      (1 << TCG_REG_O1) |
1573                      (1 << TCG_REG_O2) |
1574                      (1 << TCG_REG_O3) |
1575                      (1 << TCG_REG_O4) |
1576                      (1 << TCG_REG_O5) |
1577                      (1 << TCG_REG_O7));
1578
1579     tcg_regset_clear(s->reserved_regs);
1580     tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0);
1581 #if TCG_TARGET_REG_BITS == 64
1582     tcg_regset_set_reg(s->reserved_regs, TCG_REG_I4); // for internal use
1583 #endif
1584     tcg_regset_set_reg(s->reserved_regs, TCG_REG_I5); // for internal use
1585     tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6);
1586     tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7);
1587     tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6);
1588     tcg_regset_set_reg(s->reserved_regs, TCG_REG_O7);
1589     tcg_add_target_add_op_defs(sparc_op_defs);
1590 }
1591
1592 #if TCG_TARGET_REG_BITS == 64
1593 # define ELF_HOST_MACHINE  EM_SPARCV9
1594 #elif defined(__sparc_v8plus__)
1595 # define ELF_HOST_MACHINE  EM_SPARC32PLUS
1596 # define ELF_HOST_FLAGS    EF_SPARC_32PLUS
1597 #else
1598 # define ELF_HOST_MACHINE  EM_SPARC
1599 #endif
1600
1601 typedef struct {
1602     uint32_t len __attribute__((aligned((sizeof(void *)))));
1603     uint32_t id;
1604     uint8_t version;
1605     char augmentation[1];
1606     uint8_t code_align;
1607     uint8_t data_align;
1608     uint8_t return_column;
1609 } DebugFrameCIE;
1610
1611 typedef struct {
1612     uint32_t len __attribute__((aligned((sizeof(void *)))));
1613     uint32_t cie_offset;
1614     tcg_target_long func_start __attribute__((packed));
1615     tcg_target_long func_len __attribute__((packed));
1616     uint8_t def_cfa[TCG_TARGET_REG_BITS == 64 ? 4 : 2];
1617     uint8_t win_save;
1618     uint8_t ret_save[3];
1619 } DebugFrameFDE;
1620
1621 typedef struct {
1622     DebugFrameCIE cie;
1623     DebugFrameFDE fde;
1624 } DebugFrame;
1625
1626 static DebugFrame debug_frame = {
1627     .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
1628     .cie.id = -1,
1629     .cie.version = 1,
1630     .cie.code_align = 1,
1631     .cie.data_align = -sizeof(void *) & 0x7f,
1632     .cie.return_column = 15,            /* o7 */
1633
1634     .fde.len = sizeof(DebugFrameFDE)-4, /* length after .len member */
1635     .fde.def_cfa = {
1636 #if TCG_TARGET_REG_BITS == 64
1637         12, 30,                         /* DW_CFA_def_cfa i6, 2047 */
1638         (2047 & 0x7f) | 0x80, (2047 >> 7)
1639 #else
1640         13, 30                          /* DW_CFA_def_cfa_register i6 */
1641 #endif
1642     },
1643     .fde.win_save = 0x2d,               /* DW_CFA_GNU_window_save */
1644     .fde.ret_save = { 9, 15, 31 },      /* DW_CFA_register o7, i7 */
1645 };
1646
1647 void tcg_register_jit(void *buf, size_t buf_size)
1648 {
1649     debug_frame.fde.func_start = (tcg_target_long) buf;
1650     debug_frame.fde.func_len = buf_size;
1651
1652     tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
1653 }