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more precise PIT gate emulation
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1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include <stdlib.h>
25 #include <stdio.h>
26 #include <stdarg.h>
27 #include <string.h>
28 #include <getopt.h>
29 #include <inttypes.h>
30 #include <unistd.h>
31 #include <sys/mman.h>
32 #include <fcntl.h>
33 #include <signal.h>
34 #include <time.h>
35 #include <sys/time.h>
36 #include <malloc.h>
37 #include <termios.h>
38 #include <sys/poll.h>
39 #include <errno.h>
40 #include <sys/wait.h>
41
42 #include <sys/ioctl.h>
43 #include <sys/socket.h>
44 #include <linux/if.h>
45 #include <linux/if_tun.h>
46
47 #include "cpu.h"
48 #include "disas.h"
49 #include "thunk.h"
50
51 #include "vl.h"
52
53 #define DEFAULT_NETWORK_SCRIPT "/etc/qemu-ifup"
54 #define BIOS_FILENAME "bios.bin"
55 #define VGABIOS_FILENAME "vgabios.bin"
56
57 //#define DEBUG_UNUSED_IOPORT
58
59 //#define DEBUG_IRQ_LATENCY
60
61 /* output Bochs bios info messages */
62 //#define DEBUG_BIOS
63
64 //#define DEBUG_CMOS
65
66 /* debug PIC */
67 //#define DEBUG_PIC
68
69 /* debug NE2000 card */
70 //#define DEBUG_NE2000
71
72 /* debug PC keyboard */
73 //#define DEBUG_KBD
74
75 /* debug PC keyboard : only mouse */
76 //#define DEBUG_MOUSE
77
78 //#define DEBUG_SERIAL
79
80 #define PHYS_RAM_BASE 0xac000000
81 #define PHYS_RAM_MAX_SIZE (256 * 1024 * 1024)
82
83 #define KERNEL_LOAD_ADDR 0x00100000
84 #define INITRD_LOAD_ADDR 0x00400000
85 #define KERNEL_PARAMS_ADDR 0x00090000
86
87 #define GUI_REFRESH_INTERVAL 30
88
89 /* from plex86 (BSD license) */
90 struct __attribute__ ((packed)) linux_params {
91 // For 0x00..0x3f, see 'struct screen_info' in linux/include/linux/tty.h.
92 // I just padded out the VESA parts, rather than define them.
93
94 /* 0x000 */ uint8_t orig_x;
95 /* 0x001 */ uint8_t orig_y;
96 /* 0x002 */ uint16_t ext_mem_k;
97 /* 0x004 */ uint16_t orig_video_page;
98 /* 0x006 */ uint8_t orig_video_mode;
99 /* 0x007 */ uint8_t orig_video_cols;
100 /* 0x008 */ uint16_t unused1;
101 /* 0x00a */ uint16_t orig_video_ega_bx;
102 /* 0x00c */ uint16_t unused2;
103 /* 0x00e */ uint8_t orig_video_lines;
104 /* 0x00f */ uint8_t orig_video_isVGA;
105 /* 0x010 */ uint16_t orig_video_points;
106 /* 0x012 */ uint8_t pad0[0x20 - 0x12]; // VESA info.
107 /* 0x020 */ uint16_t cl_magic; // Commandline magic number (0xA33F)
108 /* 0x022 */ uint16_t cl_offset; // Commandline offset. Address of commandline
109 // is calculated as 0x90000 + cl_offset, bu
110 // only if cl_magic == 0xA33F.
111 /* 0x024 */ uint8_t pad1[0x40 - 0x24]; // VESA info.
112
113 /* 0x040 */ uint8_t apm_bios_info[20]; // struct apm_bios_info
114 /* 0x054 */ uint8_t pad2[0x80 - 0x54];
115
116 // Following 2 from 'struct drive_info_struct' in drivers/block/cciss.h.
117 // Might be truncated?
118 /* 0x080 */ uint8_t hd0_info[16]; // hd0-disk-parameter from intvector 0x41
119 /* 0x090 */ uint8_t hd1_info[16]; // hd1-disk-parameter from intvector 0x46
120
121 // System description table truncated to 16 bytes
122 // From 'struct sys_desc_table_struct' in linux/arch/i386/kernel/setup.c.
123 /* 0x0a0 */ uint16_t sys_description_len;
124 /* 0x0a2 */ uint8_t sys_description_table[14];
125 // [0] machine id
126 // [1] machine submodel id
127 // [2] BIOS revision
128 // [3] bit1: MCA bus
129
130 /* 0x0b0 */ uint8_t pad3[0x1e0 - 0xb0];
131 /* 0x1e0 */ uint32_t alt_mem_k;
132 /* 0x1e4 */ uint8_t pad4[4];
133 /* 0x1e8 */ uint8_t e820map_entries;
134 /* 0x1e9 */ uint8_t eddbuf_entries; // EDD_NR
135 /* 0x1ea */ uint8_t pad5[0x1f1 - 0x1ea];
136 /* 0x1f1 */ uint8_t setup_sects; // size of setup.S, number of sectors
137 /* 0x1f2 */ uint16_t mount_root_rdonly; // MOUNT_ROOT_RDONLY (if !=0)
138 /* 0x1f4 */ uint16_t sys_size; // size of compressed kernel-part in the
139 // (b)zImage-file (in 16 byte units, rounded up)
140 /* 0x1f6 */ uint16_t swap_dev; // (unused AFAIK)
141 /* 0x1f8 */ uint16_t ramdisk_flags;
142 /* 0x1fa */ uint16_t vga_mode; // (old one)
143 /* 0x1fc */ uint16_t orig_root_dev; // (high=Major, low=minor)
144 /* 0x1fe */ uint8_t pad6[1];
145 /* 0x1ff */ uint8_t aux_device_info;
146 /* 0x200 */ uint16_t jump_setup; // Jump to start of setup code,
147 // aka "reserved" field.
148 /* 0x202 */ uint8_t setup_signature[4]; // Signature for SETUP-header, ="HdrS"
149 /* 0x206 */ uint16_t header_format_version; // Version number of header format;
150 /* 0x208 */ uint8_t setup_S_temp0[8]; // Used by setup.S for communication with
151 // boot loaders, look there.
152 /* 0x210 */ uint8_t loader_type;
153 // 0 for old one.
154 // else 0xTV:
155 // T=0: LILO
156 // T=1: Loadlin
157 // T=2: bootsect-loader
158 // T=3: SYSLINUX
159 // T=4: ETHERBOOT
160 // V=version
161 /* 0x211 */ uint8_t loadflags;
162 // bit0 = 1: kernel is loaded high (bzImage)
163 // bit7 = 1: Heap and pointer (see below) set by boot
164 // loader.
165 /* 0x212 */ uint16_t setup_S_temp1;
166 /* 0x214 */ uint32_t kernel_start;
167 /* 0x218 */ uint32_t initrd_start;
168 /* 0x21c */ uint32_t initrd_size;
169 /* 0x220 */ uint8_t setup_S_temp2[4];
170 /* 0x224 */ uint16_t setup_S_heap_end_pointer;
171 /* 0x226 */ uint8_t pad7[0x2d0 - 0x226];
172
173 /* 0x2d0 : Int 15, ax=e820 memory map. */
174 // (linux/include/asm-i386/e820.h, 'struct e820entry')
175 #define E820MAX 32
176 #define E820_RAM 1
177 #define E820_RESERVED 2
178 #define E820_ACPI 3 /* usable as RAM once ACPI tables have been read */
179 #define E820_NVS 4
180 struct {
181 uint64_t addr;
182 uint64_t size;
183 uint32_t type;
184 } e820map[E820MAX];
185
186 /* 0x550 */ uint8_t pad8[0x600 - 0x550];
187
188 // BIOS Enhanced Disk Drive Services.
189 // (From linux/include/asm-i386/edd.h, 'struct edd_info')
190 // Each 'struct edd_info is 78 bytes, times a max of 6 structs in array.
191 /* 0x600 */ uint8_t eddbuf[0x7d4 - 0x600];
192
193 /* 0x7d4 */ uint8_t pad9[0x800 - 0x7d4];
194 /* 0x800 */ uint8_t commandline[0x800];
195
196 /* 0x1000 */
197 uint64_t gdt_table[256];
198 uint64_t idt_table[48];
199 };
200
201 #define KERNEL_CS 0x10
202 #define KERNEL_DS 0x18
203
204 /* XXX: use a two level table to limit memory usage */
205 #define MAX_IOPORTS 65536
206
207 static const char *bios_dir = CONFIG_QEMU_SHAREDIR;
208 char phys_ram_file[1024];
209 CPUX86State *global_env;
210 CPUX86State *cpu_single_env;
211 IOPortReadFunc *ioport_read_table[3][MAX_IOPORTS];
212 IOPortWriteFunc *ioport_write_table[3][MAX_IOPORTS];
213 BlockDriverState *bs_table[MAX_DISKS];
214 int vga_ram_size;
215 static DisplayState display_state;
216 int nographic;
217 int term_inited;
218 int64_t ticks_per_sec;
219 int boot_device = 'c';
220
221 /***********************************************************/
222 /* x86 io ports */
223
224 uint32_t default_ioport_readb(CPUX86State *env, uint32_t address)
225 {
226 #ifdef DEBUG_UNUSED_IOPORT
227 fprintf(stderr, "inb: port=0x%04x\n", address);
228 #endif
229 return 0xff;
230 }
231
232 void default_ioport_writeb(CPUX86State *env, uint32_t address, uint32_t data)
233 {
234 #ifdef DEBUG_UNUSED_IOPORT
235 fprintf(stderr, "outb: port=0x%04x data=0x%02x\n", address, data);
236 #endif
237 }
238
239 /* default is to make two byte accesses */
240 uint32_t default_ioport_readw(CPUX86State *env, uint32_t address)
241 {
242 uint32_t data;
243 data = ioport_read_table[0][address & (MAX_IOPORTS - 1)](env, address);
244 data |= ioport_read_table[0][(address + 1) & (MAX_IOPORTS - 1)](env, address + 1) << 8;
245 return data;
246 }
247
248 void default_ioport_writew(CPUX86State *env, uint32_t address, uint32_t data)
249 {
250 ioport_write_table[0][address & (MAX_IOPORTS - 1)](env, address, data & 0xff);
251 ioport_write_table[0][(address + 1) & (MAX_IOPORTS - 1)](env, address + 1, (data >> 8) & 0xff);
252 }
253
254 uint32_t default_ioport_readl(CPUX86State *env, uint32_t address)
255 {
256 #ifdef DEBUG_UNUSED_IOPORT
257 fprintf(stderr, "inl: port=0x%04x\n", address);
258 #endif
259 return 0xffffffff;
260 }
261
262 void default_ioport_writel(CPUX86State *env, uint32_t address, uint32_t data)
263 {
264 #ifdef DEBUG_UNUSED_IOPORT
265 fprintf(stderr, "outl: port=0x%04x data=0x%02x\n", address, data);
266 #endif
267 }
268
269 void init_ioports(void)
270 {
271 int i;
272
273 for(i = 0; i < MAX_IOPORTS; i++) {
274 ioport_read_table[0][i] = default_ioport_readb;
275 ioport_write_table[0][i] = default_ioport_writeb;
276 ioport_read_table[1][i] = default_ioport_readw;
277 ioport_write_table[1][i] = default_ioport_writew;
278 ioport_read_table[2][i] = default_ioport_readl;
279 ioport_write_table[2][i] = default_ioport_writel;
280 }
281 }
282
283 /* size is the word size in byte */
284 int register_ioport_read(int start, int length, IOPortReadFunc *func, int size)
285 {
286 int i, bsize;
287
288 if (size == 1)
289 bsize = 0;
290 else if (size == 2)
291 bsize = 1;
292 else if (size == 4)
293 bsize = 2;
294 else
295 return -1;
296 for(i = start; i < start + length; i += size)
297 ioport_read_table[bsize][i] = func;
298 return 0;
299 }
300
301 /* size is the word size in byte */
302 int register_ioport_write(int start, int length, IOPortWriteFunc *func, int size)
303 {
304 int i, bsize;
305
306 if (size == 1)
307 bsize = 0;
308 else if (size == 2)
309 bsize = 1;
310 else if (size == 4)
311 bsize = 2;
312 else
313 return -1;
314 for(i = start; i < start + length; i += size)
315 ioport_write_table[bsize][i] = func;
316 return 0;
317 }
318
319 void pstrcpy(char *buf, int buf_size, const char *str)
320 {
321 int c;
322 char *q = buf;
323
324 if (buf_size <= 0)
325 return;
326
327 for(;;) {
328 c = *str++;
329 if (c == 0 || q >= buf + buf_size - 1)
330 break;
331 *q++ = c;
332 }
333 *q = '\0';
334 }
335
336 /* strcat and truncate. */
337 char *pstrcat(char *buf, int buf_size, const char *s)
338 {
339 int len;
340 len = strlen(buf);
341 if (len < buf_size)
342 pstrcpy(buf + len, buf_size - len, s);
343 return buf;
344 }
345
346 int load_kernel(const char *filename, uint8_t *addr)
347 {
348 int fd, size, setup_sects;
349 uint8_t bootsect[512];
350
351 fd = open(filename, O_RDONLY);
352 if (fd < 0)
353 return -1;
354 if (read(fd, bootsect, 512) != 512)
355 goto fail;
356 setup_sects = bootsect[0x1F1];
357 if (!setup_sects)
358 setup_sects = 4;
359 /* skip 16 bit setup code */
360 lseek(fd, (setup_sects + 1) * 512, SEEK_SET);
361 size = read(fd, addr, 16 * 1024 * 1024);
362 if (size < 0)
363 goto fail;
364 close(fd);
365 return size;
366 fail:
367 close(fd);
368 return -1;
369 }
370
371 /* return the size or -1 if error */
372 int load_image(const char *filename, uint8_t *addr)
373 {
374 int fd, size;
375 fd = open(filename, O_RDONLY);
376 if (fd < 0)
377 return -1;
378 size = lseek(fd, 0, SEEK_END);
379 lseek(fd, 0, SEEK_SET);
380 if (read(fd, addr, size) != size) {
381 close(fd);
382 return -1;
383 }
384 close(fd);
385 return size;
386 }
387
388 void cpu_x86_outb(CPUX86State *env, int addr, int val)
389 {
390 ioport_write_table[0][addr & (MAX_IOPORTS - 1)](env, addr, val);
391 }
392
393 void cpu_x86_outw(CPUX86State *env, int addr, int val)
394 {
395 ioport_write_table[1][addr & (MAX_IOPORTS - 1)](env, addr, val);
396 }
397
398 void cpu_x86_outl(CPUX86State *env, int addr, int val)
399 {
400 ioport_write_table[2][addr & (MAX_IOPORTS - 1)](env, addr, val);
401 }
402
403 int cpu_x86_inb(CPUX86State *env, int addr)
404 {
405 return ioport_read_table[0][addr & (MAX_IOPORTS - 1)](env, addr);
406 }
407
408 int cpu_x86_inw(CPUX86State *env, int addr)
409 {
410 return ioport_read_table[1][addr & (MAX_IOPORTS - 1)](env, addr);
411 }
412
413 int cpu_x86_inl(CPUX86State *env, int addr)
414 {
415 return ioport_read_table[2][addr & (MAX_IOPORTS - 1)](env, addr);
416 }
417
418 /***********************************************************/
419 void ioport80_write(CPUX86State *env, uint32_t addr, uint32_t data)
420 {
421 }
422
423 void hw_error(const char *fmt, ...)
424 {
425 va_list ap;
426
427 va_start(ap, fmt);
428 fprintf(stderr, "qemu: hardware error: ");
429 vfprintf(stderr, fmt, ap);
430 fprintf(stderr, "\n");
431 #ifdef TARGET_I386
432 cpu_x86_dump_state(global_env, stderr, X86_DUMP_FPU | X86_DUMP_CCOP);
433 #endif
434 va_end(ap);
435 abort();
436 }
437
438 /***********************************************************/
439 /* cmos emulation */
440
441 #define RTC_SECONDS 0
442 #define RTC_SECONDS_ALARM 1
443 #define RTC_MINUTES 2
444 #define RTC_MINUTES_ALARM 3
445 #define RTC_HOURS 4
446 #define RTC_HOURS_ALARM 5
447 #define RTC_ALARM_DONT_CARE 0xC0
448
449 #define RTC_DAY_OF_WEEK 6
450 #define RTC_DAY_OF_MONTH 7
451 #define RTC_MONTH 8
452 #define RTC_YEAR 9
453
454 #define RTC_REG_A 10
455 #define RTC_REG_B 11
456 #define RTC_REG_C 12
457 #define RTC_REG_D 13
458
459 /* PC cmos mappings */
460 #define REG_EQUIPMENT_BYTE 0x14
461
462 uint8_t cmos_data[128];
463 uint8_t cmos_index;
464
465 void cmos_ioport_write(CPUX86State *env, uint32_t addr, uint32_t data)
466 {
467 if (addr == 0x70) {
468 cmos_index = data & 0x7f;
469 } else {
470 #ifdef DEBUG_CMOS
471 printf("cmos: write index=0x%02x val=0x%02x\n",
472 cmos_index, data);
473 #endif
474 switch(addr) {
475 case RTC_SECONDS_ALARM:
476 case RTC_MINUTES_ALARM:
477 case RTC_HOURS_ALARM:
478 /* XXX: not supported */
479 cmos_data[cmos_index] = data;
480 break;
481 case RTC_SECONDS:
482 case RTC_MINUTES:
483 case RTC_HOURS:
484 case RTC_DAY_OF_WEEK:
485 case RTC_DAY_OF_MONTH:
486 case RTC_MONTH:
487 case RTC_YEAR:
488 cmos_data[cmos_index] = data;
489 break;
490 case RTC_REG_A:
491 case RTC_REG_B:
492 cmos_data[cmos_index] = data;
493 break;
494 case RTC_REG_C:
495 case RTC_REG_D:
496 /* cannot write to them */
497 break;
498 default:
499 cmos_data[cmos_index] = data;
500 break;
501 }
502 }
503 }
504
505 uint32_t cmos_ioport_read(CPUX86State *env, uint32_t addr)
506 {
507 int ret;
508
509 if (addr == 0x70) {
510 return 0xff;
511 } else {
512 ret = cmos_data[cmos_index];
513 switch(cmos_index) {
514 case RTC_REG_A:
515 /* toggle update-in-progress bit for Linux (same hack as
516 plex86) */
517 cmos_data[RTC_REG_A] ^= 0x80;
518 break;
519 case RTC_REG_C:
520 pic_set_irq(8, 0);
521 cmos_data[RTC_REG_C] = 0x00;
522 break;
523 }
524 #ifdef DEBUG_CMOS
525 printf("cmos: read index=0x%02x val=0x%02x\n",
526 cmos_index, ret);
527 #endif
528 return ret;
529 }
530 }
531
532
533 static inline int to_bcd(int a)
534 {
535 return ((a / 10) << 4) | (a % 10);
536 }
537
538 void cmos_init(void)
539 {
540 struct tm *tm;
541 time_t ti;
542 int val;
543
544 ti = time(NULL);
545 tm = gmtime(&ti);
546 cmos_data[RTC_SECONDS] = to_bcd(tm->tm_sec);
547 cmos_data[RTC_MINUTES] = to_bcd(tm->tm_min);
548 cmos_data[RTC_HOURS] = to_bcd(tm->tm_hour);
549 cmos_data[RTC_DAY_OF_WEEK] = to_bcd(tm->tm_wday);
550 cmos_data[RTC_DAY_OF_MONTH] = to_bcd(tm->tm_mday);
551 cmos_data[RTC_MONTH] = to_bcd(tm->tm_mon + 1);
552 cmos_data[RTC_YEAR] = to_bcd(tm->tm_year % 100);
553
554 cmos_data[RTC_REG_A] = 0x26;
555 cmos_data[RTC_REG_B] = 0x02;
556 cmos_data[RTC_REG_C] = 0x00;
557 cmos_data[RTC_REG_D] = 0x80;
558
559 /* various important CMOS locations needed by PC/Bochs bios */
560
561 cmos_data[REG_EQUIPMENT_BYTE] = 0x02; /* FPU is there */
562 cmos_data[REG_EQUIPMENT_BYTE] |= 0x04; /* PS/2 mouse installed */
563
564 /* memory size */
565 val = (phys_ram_size / 1024) - 1024;
566 if (val > 65535)
567 val = 65535;
568 cmos_data[0x17] = val;
569 cmos_data[0x18] = val >> 8;
570 cmos_data[0x30] = val;
571 cmos_data[0x31] = val >> 8;
572
573 val = (phys_ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
574 if (val > 65535)
575 val = 65535;
576 cmos_data[0x34] = val;
577 cmos_data[0x35] = val >> 8;
578
579 switch(boot_device) {
580 case 'a':
581 cmos_data[0x3d] = 0x01; /* floppy boot */
582 break;
583 default:
584 case 'c':
585 cmos_data[0x3d] = 0x02; /* hard drive boot */
586 break;
587 case 'd':
588 cmos_data[0x3d] = 0x03; /* CD-ROM boot */
589 break;
590 }
591
592 register_ioport_write(0x70, 2, cmos_ioport_write, 1);
593 register_ioport_read(0x70, 2, cmos_ioport_read, 1);
594 }
595
596 /***********************************************************/
597 /* 8259 pic emulation */
598
599 typedef struct PicState {
600 uint8_t last_irr; /* edge detection */
601 uint8_t irr; /* interrupt request register */
602 uint8_t imr; /* interrupt mask register */
603 uint8_t isr; /* interrupt service register */
604 uint8_t priority_add; /* used to compute irq priority */
605 uint8_t irq_base;
606 uint8_t read_reg_select;
607 uint8_t special_mask;
608 uint8_t init_state;
609 uint8_t auto_eoi;
610 uint8_t rotate_on_autoeoi;
611 uint8_t init4; /* true if 4 byte init */
612 } PicState;
613
614 /* 0 is master pic, 1 is slave pic */
615 PicState pics[2];
616 int pic_irq_requested;
617
618 /* set irq level. If an edge is detected, then the IRR is set to 1 */
619 static inline void pic_set_irq1(PicState *s, int irq, int level)
620 {
621 int mask;
622 mask = 1 << irq;
623 if (level) {
624 if ((s->last_irr & mask) == 0)
625 s->irr |= mask;
626 s->last_irr |= mask;
627 } else {
628 s->last_irr &= ~mask;
629 }
630 }
631
632 static inline int get_priority(PicState *s, int mask)
633 {
634 int priority;
635 if (mask == 0)
636 return -1;
637 priority = 7;
638 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
639 priority--;
640 return priority;
641 }
642
643 /* return the pic wanted interrupt. return -1 if none */
644 static int pic_get_irq(PicState *s)
645 {
646 int mask, cur_priority, priority;
647
648 mask = s->irr & ~s->imr;
649 priority = get_priority(s, mask);
650 if (priority < 0)
651 return -1;
652 /* compute current priority */
653 cur_priority = get_priority(s, s->isr);
654 if (priority > cur_priority) {
655 /* higher priority found: an irq should be generated */
656 return priority;
657 } else {
658 return -1;
659 }
660 }
661
662 /* raise irq to CPU if necessary. must be called every time the active
663 irq may change */
664 static void pic_update_irq(void)
665 {
666 int irq2, irq;
667
668 /* first look at slave pic */
669 irq2 = pic_get_irq(&pics[1]);
670 if (irq2 >= 0) {
671 /* if irq request by slave pic, signal master PIC */
672 pic_set_irq1(&pics[0], 2, 1);
673 pic_set_irq1(&pics[0], 2, 0);
674 }
675 /* look at requested irq */
676 irq = pic_get_irq(&pics[0]);
677 if (irq >= 0) {
678 if (irq == 2) {
679 /* from slave pic */
680 pic_irq_requested = 8 + irq2;
681 } else {
682 /* from master pic */
683 pic_irq_requested = irq;
684 }
685 cpu_x86_interrupt(global_env, CPU_INTERRUPT_HARD);
686 }
687 }
688
689 #ifdef DEBUG_IRQ_LATENCY
690 int64_t irq_time[16];
691 int64_t cpu_get_ticks(void);
692 #endif
693 #if defined(DEBUG_PIC)
694 int irq_level[16];
695 #endif
696
697 void pic_set_irq(int irq, int level)
698 {
699 #if defined(DEBUG_PIC)
700 if (level != irq_level[irq]) {
701 printf("pic_set_irq: irq=%d level=%d\n", irq, level);
702 irq_level[irq] = level;
703 }
704 #endif
705 #ifdef DEBUG_IRQ_LATENCY
706 if (level) {
707 irq_time[irq] = cpu_get_ticks();
708 }
709 #endif
710 pic_set_irq1(&pics[irq >> 3], irq & 7, level);
711 pic_update_irq();
712 }
713
714 int cpu_x86_get_pic_interrupt(CPUX86State *env)
715 {
716 int irq, irq2, intno;
717
718 /* signal the pic that the irq was acked by the CPU */
719 irq = pic_irq_requested;
720 #ifdef DEBUG_IRQ_LATENCY
721 printf("IRQ%d latency=%0.3fus\n",
722 irq,
723 (double)(cpu_get_ticks() - irq_time[irq]) * 1000000.0 / ticks_per_sec);
724 #endif
725 #if defined(DEBUG_PIC)
726 printf("pic_interrupt: irq=%d\n", irq);
727 #endif
728
729 if (irq >= 8) {
730 irq2 = irq & 7;
731 pics[1].isr |= (1 << irq2);
732 pics[1].irr &= ~(1 << irq2);
733 irq = 2;
734 intno = pics[1].irq_base + irq2;
735 } else {
736 intno = pics[0].irq_base + irq;
737 }
738 pics[0].isr |= (1 << irq);
739 pics[0].irr &= ~(1 << irq);
740 return intno;
741 }
742
743 void pic_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
744 {
745 PicState *s;
746 int priority;
747
748 #ifdef DEBUG_PIC
749 printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
750 #endif
751 s = &pics[addr >> 7];
752 addr &= 1;
753 if (addr == 0) {
754 if (val & 0x10) {
755 /* init */
756 memset(s, 0, sizeof(PicState));
757 s->init_state = 1;
758 s->init4 = val & 1;
759 if (val & 0x02)
760 hw_error("single mode not supported");
761 if (val & 0x08)
762 hw_error("level sensitive irq not supported");
763 } else if (val & 0x08) {
764 if (val & 0x02)
765 s->read_reg_select = val & 1;
766 if (val & 0x40)
767 s->special_mask = (val >> 5) & 1;
768 } else {
769 switch(val) {
770 case 0x00:
771 case 0x80:
772 s->rotate_on_autoeoi = val >> 7;
773 break;
774 case 0x20: /* end of interrupt */
775 case 0xa0:
776 priority = get_priority(s, s->isr);
777 if (priority >= 0) {
778 s->isr &= ~(1 << ((priority + s->priority_add) & 7));
779 }
780 if (val == 0xa0)
781 s->priority_add = (s->priority_add + 1) & 7;
782 pic_update_irq();
783 break;
784 case 0x60 ... 0x67:
785 priority = val & 7;
786 s->isr &= ~(1 << priority);
787 pic_update_irq();
788 break;
789 case 0xc0 ... 0xc7:
790 s->priority_add = (val + 1) & 7;
791 pic_update_irq();
792 break;
793 case 0xe0 ... 0xe7:
794 priority = val & 7;
795 s->isr &= ~(1 << priority);
796 s->priority_add = (priority + 1) & 7;
797 pic_update_irq();
798 break;
799 }
800 }
801 } else {
802 switch(s->init_state) {
803 case 0:
804 /* normal mode */
805 s->imr = val;
806 pic_update_irq();
807 break;
808 case 1:
809 s->irq_base = val & 0xf8;
810 s->init_state = 2;
811 break;
812 case 2:
813 if (s->init4) {
814 s->init_state = 3;
815 } else {
816 s->init_state = 0;
817 }
818 break;
819 case 3:
820 s->auto_eoi = (val >> 1) & 1;
821 s->init_state = 0;
822 break;
823 }
824 }
825 }
826
827 uint32_t pic_ioport_read(CPUX86State *env, uint32_t addr1)
828 {
829 PicState *s;
830 unsigned int addr;
831 int ret;
832
833 addr = addr1;
834 s = &pics[addr >> 7];
835 addr &= 1;
836 if (addr == 0) {
837 if (s->read_reg_select)
838 ret = s->isr;
839 else
840 ret = s->irr;
841 } else {
842 ret = s->imr;
843 }
844 #ifdef DEBUG_PIC
845 printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
846 #endif
847 return ret;
848 }
849
850 void pic_init(void)
851 {
852 register_ioport_write(0x20, 2, pic_ioport_write, 1);
853 register_ioport_read(0x20, 2, pic_ioport_read, 1);
854 register_ioport_write(0xa0, 2, pic_ioport_write, 1);
855 register_ioport_read(0xa0, 2, pic_ioport_read, 1);
856 }
857
858 /***********************************************************/
859 /* 8253 PIT emulation */
860
861 #define PIT_FREQ 1193182
862
863 #define RW_STATE_LSB 0
864 #define RW_STATE_MSB 1
865 #define RW_STATE_WORD0 2
866 #define RW_STATE_WORD1 3
867 #define RW_STATE_LATCHED_WORD0 4
868 #define RW_STATE_LATCHED_WORD1 5
869
870 typedef struct PITChannelState {
871 int count; /* can be 65536 */
872 uint16_t latched_count;
873 uint8_t rw_state;
874 uint8_t mode;
875 uint8_t bcd; /* not supported */
876 uint8_t gate; /* timer start */
877 int64_t count_load_time;
878 int64_t count_last_edge_check_time;
879 } PITChannelState;
880
881 PITChannelState pit_channels[3];
882 int speaker_data_on;
883 int dummy_refresh_clock;
884 int pit_min_timer_count = 0;
885
886
887 #if defined(__powerpc__)
888
889 static inline uint32_t get_tbl(void)
890 {
891 uint32_t tbl;
892 asm volatile("mftb %0" : "=r" (tbl));
893 return tbl;
894 }
895
896 static inline uint32_t get_tbu(void)
897 {
898 uint32_t tbl;
899 asm volatile("mftbu %0" : "=r" (tbl));
900 return tbl;
901 }
902
903 int64_t cpu_get_real_ticks(void)
904 {
905 uint32_t l, h, h1;
906 /* NOTE: we test if wrapping has occurred */
907 do {
908 h = get_tbu();
909 l = get_tbl();
910 h1 = get_tbu();
911 } while (h != h1);
912 return ((int64_t)h << 32) | l;
913 }
914
915 #elif defined(__i386__)
916
917 int64_t cpu_get_real_ticks(void)
918 {
919 int64_t val;
920 asm("rdtsc" : "=A" (val));
921 return val;
922 }
923
924 #else
925 #error unsupported CPU
926 #endif
927
928 static int64_t cpu_ticks_offset;
929 static int64_t cpu_ticks_last;
930
931 int64_t cpu_get_ticks(void)
932 {
933 return cpu_get_real_ticks() + cpu_ticks_offset;
934 }
935
936 /* enable cpu_get_ticks() */
937 void cpu_enable_ticks(void)
938 {
939 cpu_ticks_offset = cpu_ticks_last - cpu_get_real_ticks();
940 }
941
942 /* disable cpu_get_ticks() : the clock is stopped. You must not call
943 cpu_get_ticks() after that. */
944 void cpu_disable_ticks(void)
945 {
946 cpu_ticks_last = cpu_get_ticks();
947 }
948
949 int64_t get_clock(void)
950 {
951 struct timeval tv;
952 gettimeofday(&tv, NULL);
953 return tv.tv_sec * 1000000LL + tv.tv_usec;
954 }
955
956 void cpu_calibrate_ticks(void)
957 {
958 int64_t usec, ticks;
959
960 usec = get_clock();
961 ticks = cpu_get_ticks();
962 usleep(50 * 1000);
963 usec = get_clock() - usec;
964 ticks = cpu_get_ticks() - ticks;
965 ticks_per_sec = (ticks * 1000000LL + (usec >> 1)) / usec;
966 }
967
968 /* compute with 96 bit intermediate result: (a*b)/c */
969 static uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c)
970 {
971 union {
972 uint64_t ll;
973 struct {
974 #ifdef WORDS_BIGENDIAN
975 uint32_t high, low;
976 #else
977 uint32_t low, high;
978 #endif
979 } l;
980 } u, res;
981 uint64_t rl, rh;
982
983 u.ll = a;
984 rl = (uint64_t)u.l.low * (uint64_t)b;
985 rh = (uint64_t)u.l.high * (uint64_t)b;
986 rh += (rl >> 32);
987 res.l.high = rh / c;
988 res.l.low = (((rh % c) << 32) + (rl & 0xffffffff)) / c;
989 return res.ll;
990 }
991
992 static int pit_get_count(PITChannelState *s)
993 {
994 uint64_t d;
995 int counter;
996
997 d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
998 switch(s->mode) {
999 case 0:
1000 case 1:
1001 case 4:
1002 case 5:
1003 counter = (s->count - d) & 0xffff;
1004 break;
1005 case 3:
1006 /* XXX: may be incorrect for odd counts */
1007 counter = s->count - ((2 * d) % s->count);
1008 break;
1009 default:
1010 counter = s->count - (d % s->count);
1011 break;
1012 }
1013 return counter;
1014 }
1015
1016 /* get pit output bit */
1017 static int pit_get_out(PITChannelState *s)
1018 {
1019 uint64_t d;
1020 int out;
1021
1022 d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
1023 switch(s->mode) {
1024 default:
1025 case 0:
1026 out = (d >= s->count);
1027 break;
1028 case 1:
1029 out = (d < s->count);
1030 break;
1031 case 2:
1032 if ((d % s->count) == 0 && d != 0)
1033 out = 1;
1034 else
1035 out = 0;
1036 break;
1037 case 3:
1038 out = (d % s->count) < ((s->count + 1) >> 1);
1039 break;
1040 case 4:
1041 case 5:
1042 out = (d == s->count);
1043 break;
1044 }
1045 return out;
1046 }
1047
1048 /* get the number of 0 to 1 transitions we had since we call this
1049 function */
1050 /* XXX: maybe better to use ticks precision to avoid getting edges
1051 twice if checks are done at very small intervals */
1052 static int pit_get_out_edges(PITChannelState *s)
1053 {
1054 uint64_t d1, d2;
1055 int64_t ticks;
1056 int ret, v;
1057
1058 ticks = cpu_get_ticks();
1059 d1 = muldiv64(s->count_last_edge_check_time - s->count_load_time,
1060 PIT_FREQ, ticks_per_sec);
1061 d2 = muldiv64(ticks - s->count_load_time,
1062 PIT_FREQ, ticks_per_sec);
1063 s->count_last_edge_check_time = ticks;
1064 switch(s->mode) {
1065 default:
1066 case 0:
1067 if (d1 < s->count && d2 >= s->count)
1068 ret = 1;
1069 else
1070 ret = 0;
1071 break;
1072 case 1:
1073 ret = 0;
1074 break;
1075 case 2:
1076 d1 /= s->count;
1077 d2 /= s->count;
1078 ret = d2 - d1;
1079 break;
1080 case 3:
1081 v = s->count - ((s->count + 1) >> 1);
1082 d1 = (d1 + v) / s->count;
1083 d2 = (d2 + v) / s->count;
1084 ret = d2 - d1;
1085 break;
1086 case 4:
1087 case 5:
1088 if (d1 < s->count && d2 >= s->count)
1089 ret = 1;
1090 else
1091 ret = 0;
1092 break;
1093 }
1094 return ret;
1095 }
1096
1097 /* val must be 0 or 1 */
1098 static inline void pit_set_gate(PITChannelState *s, int val)
1099 {
1100 switch(s->mode) {
1101 default:
1102 case 0:
1103 case 4:
1104 /* XXX: just disable/enable counting */
1105 break;
1106 case 1:
1107 case 5:
1108 if (s->gate < val) {
1109 /* restart counting on rising edge */
1110 s->count_load_time = cpu_get_ticks();
1111 s->count_last_edge_check_time = s->count_load_time;
1112 }
1113 break;
1114 case 2:
1115 case 3:
1116 if (s->gate < val) {
1117 /* restart counting on rising edge */
1118 s->count_load_time = cpu_get_ticks();
1119 s->count_last_edge_check_time = s->count_load_time;
1120 }
1121 /* XXX: disable/enable counting */
1122 break;
1123 }
1124 s->gate = val;
1125 }
1126
1127 static inline void pit_load_count(PITChannelState *s, int val)
1128 {
1129 if (val == 0)
1130 val = 0x10000;
1131 s->count_load_time = cpu_get_ticks();
1132 s->count_last_edge_check_time = s->count_load_time;
1133 s->count = val;
1134 if (s == &pit_channels[0] && val <= pit_min_timer_count) {
1135 fprintf(stderr,
1136 "\nWARNING: qemu: on your system, accurate timer emulation is impossible if its frequency is more than %d Hz. If using a 2.5.xx Linux kernel, you must patch asm/param.h to change HZ from 1000 to 100.\n\n",
1137 PIT_FREQ / pit_min_timer_count);
1138 }
1139 }
1140
1141 void pit_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1142 {
1143 int channel, access;
1144 PITChannelState *s;
1145
1146 addr &= 3;
1147 if (addr == 3) {
1148 channel = val >> 6;
1149 if (channel == 3)
1150 return;
1151 s = &pit_channels[channel];
1152 access = (val >> 4) & 3;
1153 switch(access) {
1154 case 0:
1155 s->latched_count = pit_get_count(s);
1156 s->rw_state = RW_STATE_LATCHED_WORD0;
1157 break;
1158 default:
1159 s->mode = (val >> 1) & 7;
1160 s->bcd = val & 1;
1161 s->rw_state = access - 1 + RW_STATE_LSB;
1162 break;
1163 }
1164 } else {
1165 s = &pit_channels[addr];
1166 switch(s->rw_state) {
1167 case RW_STATE_LSB:
1168 pit_load_count(s, val);
1169 break;
1170 case RW_STATE_MSB:
1171 pit_load_count(s, val << 8);
1172 break;
1173 case RW_STATE_WORD0:
1174 case RW_STATE_WORD1:
1175 if (s->rw_state & 1) {
1176 pit_load_count(s, (s->latched_count & 0xff) | (val << 8));
1177 } else {
1178 s->latched_count = val;
1179 }
1180 s->rw_state ^= 1;
1181 break;
1182 }
1183 }
1184 }
1185
1186 uint32_t pit_ioport_read(CPUX86State *env, uint32_t addr)
1187 {
1188 int ret, count;
1189 PITChannelState *s;
1190
1191 addr &= 3;
1192 s = &pit_channels[addr];
1193 switch(s->rw_state) {
1194 case RW_STATE_LSB:
1195 case RW_STATE_MSB:
1196 case RW_STATE_WORD0:
1197 case RW_STATE_WORD1:
1198 count = pit_get_count(s);
1199 if (s->rw_state & 1)
1200 ret = (count >> 8) & 0xff;
1201 else
1202 ret = count & 0xff;
1203 if (s->rw_state & 2)
1204 s->rw_state ^= 1;
1205 break;
1206 default:
1207 case RW_STATE_LATCHED_WORD0:
1208 case RW_STATE_LATCHED_WORD1:
1209 if (s->rw_state & 1)
1210 ret = s->latched_count >> 8;
1211 else
1212 ret = s->latched_count & 0xff;
1213 s->rw_state ^= 1;
1214 break;
1215 }
1216 return ret;
1217 }
1218
1219 void speaker_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1220 {
1221 speaker_data_on = (val >> 1) & 1;
1222 pit_set_gate(&pit_channels[2], val & 1);
1223 }
1224
1225 uint32_t speaker_ioport_read(CPUX86State *env, uint32_t addr)
1226 {
1227 int out;
1228 out = pit_get_out(&pit_channels[2]);
1229 dummy_refresh_clock ^= 1;
1230 return (speaker_data_on << 1) | pit_channels[2].gate | (out << 5) |
1231 (dummy_refresh_clock << 4);
1232 }
1233
1234 void pit_init(void)
1235 {
1236 PITChannelState *s;
1237 int i;
1238
1239 cpu_calibrate_ticks();
1240
1241 for(i = 0;i < 3; i++) {
1242 s = &pit_channels[i];
1243 s->mode = 3;
1244 s->gate = (i != 2);
1245 pit_load_count(s, 0);
1246 }
1247
1248 register_ioport_write(0x40, 4, pit_ioport_write, 1);
1249 register_ioport_read(0x40, 3, pit_ioport_read, 1);
1250
1251 register_ioport_read(0x61, 1, speaker_ioport_read, 1);
1252 register_ioport_write(0x61, 1, speaker_ioport_write, 1);
1253 }
1254
1255 /***********************************************************/
1256 /* serial port emulation */
1257
1258 #define UART_IRQ 4
1259
1260 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
1261
1262 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1263 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1264 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1265 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1266
1267 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1268 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1269
1270 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
1271 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1272 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1273 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1274
1275 /*
1276 * These are the definitions for the Modem Control Register
1277 */
1278 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
1279 #define UART_MCR_OUT2 0x08 /* Out2 complement */
1280 #define UART_MCR_OUT1 0x04 /* Out1 complement */
1281 #define UART_MCR_RTS 0x02 /* RTS complement */
1282 #define UART_MCR_DTR 0x01 /* DTR complement */
1283
1284 /*
1285 * These are the definitions for the Modem Status Register
1286 */
1287 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
1288 #define UART_MSR_RI 0x40 /* Ring Indicator */
1289 #define UART_MSR_DSR 0x20 /* Data Set Ready */
1290 #define UART_MSR_CTS 0x10 /* Clear to Send */
1291 #define UART_MSR_DDCD 0x08 /* Delta DCD */
1292 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
1293 #define UART_MSR_DDSR 0x02 /* Delta DSR */
1294 #define UART_MSR_DCTS 0x01 /* Delta CTS */
1295 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
1296
1297 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
1298 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1299 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
1300 #define UART_LSR_FE 0x08 /* Frame error indicator */
1301 #define UART_LSR_PE 0x04 /* Parity error indicator */
1302 #define UART_LSR_OE 0x02 /* Overrun error indicator */
1303 #define UART_LSR_DR 0x01 /* Receiver data ready */
1304
1305 typedef struct SerialState {
1306 uint8_t divider;
1307 uint8_t rbr; /* receive register */
1308 uint8_t ier;
1309 uint8_t iir; /* read only */
1310 uint8_t lcr;
1311 uint8_t mcr;
1312 uint8_t lsr; /* read only */
1313 uint8_t msr;
1314 uint8_t scr;
1315 /* NOTE: this hidden state is necessary for tx irq generation as
1316 it can be reset while reading iir */
1317 int thr_ipending;
1318 } SerialState;
1319
1320 SerialState serial_ports[1];
1321
1322 void serial_update_irq(void)
1323 {
1324 SerialState *s = &serial_ports[0];
1325
1326 if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
1327 s->iir = UART_IIR_RDI;
1328 } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
1329 s->iir = UART_IIR_THRI;
1330 } else {
1331 s->iir = UART_IIR_NO_INT;
1332 }
1333 if (s->iir != UART_IIR_NO_INT) {
1334 pic_set_irq(UART_IRQ, 1);
1335 } else {
1336 pic_set_irq(UART_IRQ, 0);
1337 }
1338 }
1339
1340 void serial_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1341 {
1342 SerialState *s = &serial_ports[0];
1343 unsigned char ch;
1344 int ret;
1345
1346 addr &= 7;
1347 #ifdef DEBUG_SERIAL
1348 printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
1349 #endif
1350 switch(addr) {
1351 default:
1352 case 0:
1353 if (s->lcr & UART_LCR_DLAB) {
1354 s->divider = (s->divider & 0xff00) | val;
1355 } else {
1356 s->thr_ipending = 0;
1357 s->lsr &= ~UART_LSR_THRE;
1358 serial_update_irq();
1359
1360 ch = val;
1361 do {
1362 ret = write(1, &ch, 1);
1363 } while (ret != 1);
1364 s->thr_ipending = 1;
1365 s->lsr |= UART_LSR_THRE;
1366 s->lsr |= UART_LSR_TEMT;
1367 serial_update_irq();
1368 }
1369 break;
1370 case 1:
1371 if (s->lcr & UART_LCR_DLAB) {
1372 s->divider = (s->divider & 0x00ff) | (val << 8);
1373 } else {
1374 s->ier = val;
1375 serial_update_irq();
1376 }
1377 break;
1378 case 2:
1379 break;
1380 case 3:
1381 s->lcr = val;
1382 break;
1383 case 4:
1384 s->mcr = val;
1385 break;
1386 case 5:
1387 break;
1388 case 6:
1389 s->msr = val;
1390 break;
1391 case 7:
1392 s->scr = val;
1393 break;
1394 }
1395 }
1396
1397 uint32_t serial_ioport_read(CPUX86State *env, uint32_t addr)
1398 {
1399 SerialState *s = &serial_ports[0];
1400 uint32_t ret;
1401
1402 addr &= 7;
1403 switch(addr) {
1404 default:
1405 case 0:
1406 if (s->lcr & UART_LCR_DLAB) {
1407 ret = s->divider & 0xff;
1408 } else {
1409 ret = s->rbr;
1410 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
1411 serial_update_irq();
1412 }
1413 break;
1414 case 1:
1415 if (s->lcr & UART_LCR_DLAB) {
1416 ret = (s->divider >> 8) & 0xff;
1417 } else {
1418 ret = s->ier;
1419 }
1420 break;
1421 case 2:
1422 ret = s->iir;
1423 /* reset THR pending bit */
1424 if ((ret & 0x7) == UART_IIR_THRI)
1425 s->thr_ipending = 0;
1426 serial_update_irq();
1427 break;
1428 case 3:
1429 ret = s->lcr;
1430 break;
1431 case 4:
1432 ret = s->mcr;
1433 break;
1434 case 5:
1435 ret = s->lsr;
1436 break;
1437 case 6:
1438 if (s->mcr & UART_MCR_LOOP) {
1439 /* in loopback, the modem output pins are connected to the
1440 inputs */
1441 ret = (s->mcr & 0x0c) << 4;
1442 ret |= (s->mcr & 0x02) << 3;
1443 ret |= (s->mcr & 0x01) << 5;
1444 } else {
1445 ret = s->msr;
1446 }
1447 break;
1448 case 7:
1449 ret = s->scr;
1450 break;
1451 }
1452 #ifdef DEBUG_SERIAL
1453 printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
1454 #endif
1455 return ret;
1456 }
1457
1458 #define TERM_ESCAPE 0x01 /* ctrl-a is used for escape */
1459 static int term_got_escape;
1460
1461 void term_print_help(void)
1462 {
1463 printf("\n"
1464 "C-a h print this help\n"
1465 "C-a x exit emulatior\n"
1466 "C-a s save disk data back to file (if -snapshot)\n"
1467 "C-a b send break (magic sysrq)\n"
1468 "C-a C-a send C-a\n"
1469 );
1470 }
1471
1472 /* called when a char is received */
1473 void serial_received_byte(SerialState *s, int ch)
1474 {
1475 if (term_got_escape) {
1476 term_got_escape = 0;
1477 switch(ch) {
1478 case 'h':
1479 term_print_help();
1480 break;
1481 case 'x':
1482 exit(0);
1483 break;
1484 case 's':
1485 {
1486 int i;
1487 for (i = 0; i < MAX_DISKS; i++) {
1488 if (bs_table[i])
1489 bdrv_commit(bs_table[i]);
1490 }
1491 }
1492 break;
1493 case 'b':
1494 /* send break */
1495 s->rbr = 0;
1496 s->lsr |= UART_LSR_BI | UART_LSR_DR;
1497 serial_update_irq();
1498 break;
1499 case 'd':
1500 cpu_set_log(CPU_LOG_ALL);
1501 break;
1502 case TERM_ESCAPE:
1503 goto send_char;
1504 }
1505 } else if (ch == TERM_ESCAPE) {
1506 term_got_escape = 1;
1507 } else {
1508 send_char:
1509 s->rbr = ch;
1510 s->lsr |= UART_LSR_DR;
1511 serial_update_irq();
1512 }
1513 }
1514
1515 void serial_init(void)
1516 {
1517 SerialState *s = &serial_ports[0];
1518
1519 s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
1520 s->iir = UART_IIR_NO_INT;
1521
1522 register_ioport_write(0x3f8, 8, serial_ioport_write, 1);
1523 register_ioport_read(0x3f8, 8, serial_ioport_read, 1);
1524 }
1525
1526 /***********************************************************/
1527 /* ne2000 emulation */
1528
1529 #define NE2000_IOPORT 0x300
1530 #define NE2000_IRQ 9
1531
1532 #define MAX_ETH_FRAME_SIZE 1514
1533
1534 #define E8390_CMD 0x00 /* The command register (for all pages) */
1535 /* Page 0 register offsets. */
1536 #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
1537 #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
1538 #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
1539 #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
1540 #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
1541 #define EN0_TSR 0x04 /* Transmit status reg RD */
1542 #define EN0_TPSR 0x04 /* Transmit starting page WR */
1543 #define EN0_NCR 0x05 /* Number of collision reg RD */
1544 #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
1545 #define EN0_FIFO 0x06 /* FIFO RD */
1546 #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
1547 #define EN0_ISR 0x07 /* Interrupt status reg RD WR */
1548 #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
1549 #define EN0_RSARLO 0x08 /* Remote start address reg 0 */
1550 #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
1551 #define EN0_RSARHI 0x09 /* Remote start address reg 1 */
1552 #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
1553 #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
1554 #define EN0_RSR 0x0c /* rx status reg RD */
1555 #define EN0_RXCR 0x0c /* RX configuration reg WR */
1556 #define EN0_TXCR 0x0d /* TX configuration reg WR */
1557 #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
1558 #define EN0_DCFG 0x0e /* Data configuration reg WR */
1559 #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
1560 #define EN0_IMR 0x0f /* Interrupt mask reg WR */
1561 #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
1562
1563 #define EN1_PHYS 0x11
1564 #define EN1_CURPAG 0x17
1565 #define EN1_MULT 0x18
1566
1567 /* Register accessed at EN_CMD, the 8390 base addr. */
1568 #define E8390_STOP 0x01 /* Stop and reset the chip */
1569 #define E8390_START 0x02 /* Start the chip, clear reset */
1570 #define E8390_TRANS 0x04 /* Transmit a frame */
1571 #define E8390_RREAD 0x08 /* Remote read */
1572 #define E8390_RWRITE 0x10 /* Remote write */
1573 #define E8390_NODMA 0x20 /* Remote DMA */
1574 #define E8390_PAGE0 0x00 /* Select page chip registers */
1575 #define E8390_PAGE1 0x40 /* using the two high-order bits */
1576 #define E8390_PAGE2 0x80 /* Page 3 is invalid. */
1577
1578 /* Bits in EN0_ISR - Interrupt status register */
1579 #define ENISR_RX 0x01 /* Receiver, no error */
1580 #define ENISR_TX 0x02 /* Transmitter, no error */
1581 #define ENISR_RX_ERR 0x04 /* Receiver, with error */
1582 #define ENISR_TX_ERR 0x08 /* Transmitter, with error */
1583 #define ENISR_OVER 0x10 /* Receiver overwrote the ring */
1584 #define ENISR_COUNTERS 0x20 /* Counters need emptying */
1585 #define ENISR_RDC 0x40 /* remote dma complete */
1586 #define ENISR_RESET 0x80 /* Reset completed */
1587 #define ENISR_ALL 0x3f /* Interrupts we will enable */
1588
1589 /* Bits in received packet status byte and EN0_RSR*/
1590 #define ENRSR_RXOK 0x01 /* Received a good packet */
1591 #define ENRSR_CRC 0x02 /* CRC error */
1592 #define ENRSR_FAE 0x04 /* frame alignment error */
1593 #define ENRSR_FO 0x08 /* FIFO overrun */
1594 #define ENRSR_MPA 0x10 /* missed pkt */
1595 #define ENRSR_PHY 0x20 /* physical/multicast address */
1596 #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
1597 #define ENRSR_DEF 0x80 /* deferring */
1598
1599 /* Transmitted packet status, EN0_TSR. */
1600 #define ENTSR_PTX 0x01 /* Packet transmitted without error */
1601 #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
1602 #define ENTSR_COL 0x04 /* The transmit collided at least once. */
1603 #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
1604 #define ENTSR_CRS 0x10 /* The carrier sense was lost. */
1605 #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
1606 #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
1607 #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
1608
1609 #define NE2000_MEM_SIZE 32768
1610
1611 typedef struct NE2000State {
1612 uint8_t cmd;
1613 uint32_t start;
1614 uint32_t stop;
1615 uint8_t boundary;
1616 uint8_t tsr;
1617 uint8_t tpsr;
1618 uint16_t tcnt;
1619 uint16_t rcnt;
1620 uint32_t rsar;
1621 uint8_t isr;
1622 uint8_t dcfg;
1623 uint8_t imr;
1624 uint8_t phys[6]; /* mac address */
1625 uint8_t curpag;
1626 uint8_t mult[8]; /* multicast mask array */
1627 uint8_t mem[NE2000_MEM_SIZE];
1628 } NE2000State;
1629
1630 NE2000State ne2000_state;
1631 int net_fd = -1;
1632 char network_script[1024];
1633
1634 void ne2000_reset(void)
1635 {
1636 NE2000State *s = &ne2000_state;
1637 int i;
1638
1639 s->isr = ENISR_RESET;
1640 s->mem[0] = 0x52;
1641 s->mem[1] = 0x54;
1642 s->mem[2] = 0x00;
1643 s->mem[3] = 0x12;
1644 s->mem[4] = 0x34;
1645 s->mem[5] = 0x56;
1646 s->mem[14] = 0x57;
1647 s->mem[15] = 0x57;
1648
1649 /* duplicate prom data */
1650 for(i = 15;i >= 0; i--) {
1651 s->mem[2 * i] = s->mem[i];
1652 s->mem[2 * i + 1] = s->mem[i];
1653 }
1654 }
1655
1656 void ne2000_update_irq(NE2000State *s)
1657 {
1658 int isr;
1659 isr = s->isr & s->imr;
1660 if (isr)
1661 pic_set_irq(NE2000_IRQ, 1);
1662 else
1663 pic_set_irq(NE2000_IRQ, 0);
1664 }
1665
1666 int net_init(void)
1667 {
1668 struct ifreq ifr;
1669 int fd, ret, pid, status;
1670
1671 fd = open("/dev/net/tun", O_RDWR);
1672 if (fd < 0) {
1673 fprintf(stderr, "warning: could not open /dev/net/tun: no virtual network emulation\n");
1674 return -1;
1675 }
1676 memset(&ifr, 0, sizeof(ifr));
1677 ifr.ifr_flags = IFF_TAP | IFF_NO_PI;
1678 pstrcpy(ifr.ifr_name, IFNAMSIZ, "tun%d");
1679 ret = ioctl(fd, TUNSETIFF, (void *) &ifr);
1680 if (ret != 0) {
1681 fprintf(stderr, "warning: could not configure /dev/net/tun: no virtual network emulation\n");
1682 close(fd);
1683 return -1;
1684 }
1685 printf("Connected to host network interface: %s\n", ifr.ifr_name);
1686 fcntl(fd, F_SETFL, O_NONBLOCK);
1687 net_fd = fd;
1688
1689 /* try to launch network init script */
1690 pid = fork();
1691 if (pid >= 0) {
1692 if (pid == 0) {
1693 execl(network_script, network_script, ifr.ifr_name, NULL);
1694 exit(1);
1695 }
1696 while (waitpid(pid, &status, 0) != pid);
1697 if (!WIFEXITED(status) ||
1698 WEXITSTATUS(status) != 0) {
1699 fprintf(stderr, "%s: could not launch network script for '%s'\n",
1700 network_script, ifr.ifr_name);
1701 }
1702 }
1703 return 0;
1704 }
1705
1706 void net_send_packet(NE2000State *s, const uint8_t *buf, int size)
1707 {
1708 #ifdef DEBUG_NE2000
1709 printf("NE2000: sending packet size=%d\n", size);
1710 #endif
1711 write(net_fd, buf, size);
1712 }
1713
1714 /* return true if the NE2000 can receive more data */
1715 int ne2000_can_receive(NE2000State *s)
1716 {
1717 int avail, index, boundary;
1718
1719 if (s->cmd & E8390_STOP)
1720 return 0;
1721 index = s->curpag << 8;
1722 boundary = s->boundary << 8;
1723 if (index < boundary)
1724 avail = boundary - index;
1725 else
1726 avail = (s->stop - s->start) - (index - boundary);
1727 if (avail < (MAX_ETH_FRAME_SIZE + 4))
1728 return 0;
1729 return 1;
1730 }
1731
1732 void ne2000_receive(NE2000State *s, uint8_t *buf, int size)
1733 {
1734 uint8_t *p;
1735 int total_len, next, avail, len, index;
1736
1737 #if defined(DEBUG_NE2000)
1738 printf("NE2000: received len=%d\n", size);
1739 #endif
1740
1741 index = s->curpag << 8;
1742 /* 4 bytes for header */
1743 total_len = size + 4;
1744 /* address for next packet (4 bytes for CRC) */
1745 next = index + ((total_len + 4 + 255) & ~0xff);
1746 if (next >= s->stop)
1747 next -= (s->stop - s->start);
1748 /* prepare packet header */
1749 p = s->mem + index;
1750 p[0] = ENRSR_RXOK; /* receive status */
1751 p[1] = next >> 8;
1752 p[2] = total_len;
1753 p[3] = total_len >> 8;
1754 index += 4;
1755
1756 /* write packet data */
1757 while (size > 0) {
1758 avail = s->stop - index;
1759 len = size;
1760 if (len > avail)
1761 len = avail;
1762 memcpy(s->mem + index, buf, len);
1763 buf += len;
1764 index += len;
1765 if (index == s->stop)
1766 index = s->start;
1767 size -= len;
1768 }
1769 s->curpag = next >> 8;
1770
1771 /* now we can signal we have receive something */
1772 s->isr |= ENISR_RX;
1773 ne2000_update_irq(s);
1774 }
1775
1776 void ne2000_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1777 {
1778 NE2000State *s = &ne2000_state;
1779 int offset, page;
1780
1781 addr &= 0xf;
1782 #ifdef DEBUG_NE2000
1783 printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
1784 #endif
1785 if (addr == E8390_CMD) {
1786 /* control register */
1787 s->cmd = val;
1788 if (val & E8390_START) {
1789 /* test specific case: zero length transfert */
1790 if ((val & (E8390_RREAD | E8390_RWRITE)) &&
1791 s->rcnt == 0) {
1792 s->isr |= ENISR_RDC;
1793 ne2000_update_irq(s);
1794 }
1795 if (val & E8390_TRANS) {
1796 net_send_packet(s, s->mem + (s->tpsr << 8), s->tcnt);
1797 /* signal end of transfert */
1798 s->tsr = ENTSR_PTX;
1799 s->isr |= ENISR_TX;
1800 ne2000_update_irq(s);
1801 }
1802 }
1803 } else {
1804 page = s->cmd >> 6;
1805 offset = addr | (page << 4);
1806 switch(offset) {
1807 case EN0_STARTPG:
1808 s->start = val << 8;
1809 break;
1810 case EN0_STOPPG:
1811 s->stop = val << 8;
1812 break;
1813 case EN0_BOUNDARY:
1814 s->boundary = val;
1815 break;
1816 case EN0_IMR:
1817 s->imr = val;
1818 ne2000_update_irq(s);
1819 break;
1820 case EN0_TPSR:
1821 s->tpsr = val;
1822 break;
1823 case EN0_TCNTLO:
1824 s->tcnt = (s->tcnt & 0xff00) | val;
1825 break;
1826 case EN0_TCNTHI:
1827 s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
1828 break;
1829 case EN0_RSARLO:
1830 s->rsar = (s->rsar & 0xff00) | val;
1831 break;
1832 case EN0_RSARHI:
1833 s->rsar = (s->rsar & 0x00ff) | (val << 8);
1834 break;
1835 case EN0_RCNTLO:
1836 s->rcnt = (s->rcnt & 0xff00) | val;
1837 break;
1838 case EN0_RCNTHI:
1839 s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
1840 break;
1841 case EN0_DCFG:
1842 s->dcfg = val;
1843 break;
1844 case EN0_ISR:
1845 s->isr &= ~val;
1846 ne2000_update_irq(s);
1847 break;
1848 case EN1_PHYS ... EN1_PHYS + 5:
1849 s->phys[offset - EN1_PHYS] = val;
1850 break;
1851 case EN1_CURPAG:
1852 s->curpag = val;
1853 break;
1854 case EN1_MULT ... EN1_MULT + 7:
1855 s->mult[offset - EN1_MULT] = val;
1856 break;
1857 }
1858 }
1859 }
1860
1861 uint32_t ne2000_ioport_read(CPUX86State *env, uint32_t addr)
1862 {
1863 NE2000State *s = &ne2000_state;
1864 int offset, page, ret;
1865
1866 addr &= 0xf;
1867 if (addr == E8390_CMD) {
1868 ret = s->cmd;
1869 } else {
1870 page = s->cmd >> 6;
1871 offset = addr | (page << 4);
1872 switch(offset) {
1873 case EN0_TSR:
1874 ret = s->tsr;
1875 break;
1876 case EN0_BOUNDARY:
1877 ret = s->boundary;
1878 break;
1879 case EN0_ISR:
1880 ret = s->isr;
1881 break;
1882 case EN1_PHYS ... EN1_PHYS + 5:
1883 ret = s->phys[offset - EN1_PHYS];
1884 break;
1885 case EN1_CURPAG:
1886 ret = s->curpag;
1887 break;
1888 case EN1_MULT ... EN1_MULT + 7:
1889 ret = s->mult[offset - EN1_MULT];
1890 break;
1891 default:
1892 ret = 0x00;
1893 break;
1894 }
1895 }
1896 #ifdef DEBUG_NE2000
1897 printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
1898 #endif
1899 return ret;
1900 }
1901
1902 void ne2000_asic_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1903 {
1904 NE2000State *s = &ne2000_state;
1905 uint8_t *p;
1906
1907 #ifdef DEBUG_NE2000
1908 printf("NE2000: asic write val=0x%04x\n", val);
1909 #endif
1910 p = s->mem + s->rsar;
1911 if (s->dcfg & 0x01) {
1912 /* 16 bit access */
1913 p[0] = val;
1914 p[1] = val >> 8;
1915 s->rsar += 2;
1916 s->rcnt -= 2;
1917 } else {
1918 /* 8 bit access */
1919 p[0] = val;
1920 s->rsar++;
1921 s->rcnt--;
1922 }
1923 /* wrap */
1924 if (s->rsar == s->stop)
1925 s->rsar = s->start;
1926 if (s->rcnt == 0) {
1927 /* signal end of transfert */
1928 s->isr |= ENISR_RDC;
1929 ne2000_update_irq(s);
1930 }
1931 }
1932
1933 uint32_t ne2000_asic_ioport_read(CPUX86State *env, uint32_t addr)
1934 {
1935 NE2000State *s = &ne2000_state;
1936 uint8_t *p;
1937 int ret;
1938
1939 p = s->mem + s->rsar;
1940 if (s->dcfg & 0x01) {
1941 /* 16 bit access */
1942 ret = p[0] | (p[1] << 8);
1943 s->rsar += 2;
1944 s->rcnt -= 2;
1945 } else {
1946 /* 8 bit access */
1947 ret = p[0];
1948 s->rsar++;
1949 s->rcnt--;
1950 }
1951 /* wrap */
1952 if (s->rsar == s->stop)
1953 s->rsar = s->start;
1954 if (s->rcnt == 0) {
1955 /* signal end of transfert */
1956 s->isr |= ENISR_RDC;
1957 ne2000_update_irq(s);
1958 }
1959 #ifdef DEBUG_NE2000
1960 printf("NE2000: asic read val=0x%04x\n", ret);
1961 #endif
1962 return ret;
1963 }
1964
1965 void ne2000_reset_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1966 {
1967 /* nothing to do (end of reset pulse) */
1968 }
1969
1970 uint32_t ne2000_reset_ioport_read(CPUX86State *env, uint32_t addr)
1971 {
1972 ne2000_reset();
1973 return 0;
1974 }
1975
1976 void ne2000_init(void)
1977 {
1978 register_ioport_write(NE2000_IOPORT, 16, ne2000_ioport_write, 1);
1979 register_ioport_read(NE2000_IOPORT, 16, ne2000_ioport_read, 1);
1980
1981 register_ioport_write(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_write, 1);
1982 register_ioport_read(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_read, 1);
1983 register_ioport_write(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_write, 2);
1984 register_ioport_read(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_read, 2);
1985
1986 register_ioport_write(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_write, 1);
1987 register_ioport_read(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_read, 1);
1988 ne2000_reset();
1989 }
1990
1991 /***********************************************************/
1992 /* keyboard emulation */
1993
1994 /* Keyboard Controller Commands */
1995 #define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */
1996 #define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */
1997 #define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */
1998 #define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */
1999 #define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */
2000 #define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */
2001 #define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */
2002 #define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */
2003 #define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */
2004 #define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */
2005 #define KBD_CCMD_READ_INPORT 0xC0 /* read input port */
2006 #define KBD_CCMD_READ_OUTPORT 0xD0 /* read output port */
2007 #define KBD_CCMD_WRITE_OUTPORT 0xD1 /* write output port */
2008 #define KBD_CCMD_WRITE_OBUF 0xD2
2009 #define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if
2010 initiated by the auxiliary device */
2011 #define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
2012 #define KBD_CCMD_DISABLE_A20 0xDD /* HP vectra only ? */
2013 #define KBD_CCMD_ENABLE_A20 0xDF /* HP vectra only ? */
2014 #define KBD_CCMD_RESET 0xFE
2015
2016 /* Keyboard Commands */
2017 #define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */
2018 #define KBD_CMD_ECHO 0xEE
2019 #define KBD_CMD_GET_ID 0xF2 /* get keyboard ID */
2020 #define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */
2021 #define KBD_CMD_ENABLE 0xF4 /* Enable scanning */
2022 #define KBD_CMD_RESET_DISABLE 0xF5 /* reset and disable scanning */
2023 #define KBD_CMD_RESET_ENABLE 0xF6 /* reset and enable scanning */
2024 #define KBD_CMD_RESET 0xFF /* Reset */
2025
2026 /* Keyboard Replies */
2027 #define KBD_REPLY_POR 0xAA /* Power on reset */
2028 #define KBD_REPLY_ACK 0xFA /* Command ACK */
2029 #define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */
2030
2031 /* Status Register Bits */
2032 #define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
2033 #define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
2034 #define KBD_STAT_SELFTEST 0x04 /* Self test successful */
2035 #define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */
2036 #define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */
2037 #define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */
2038 #define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */
2039 #define KBD_STAT_PERR 0x80 /* Parity error */
2040
2041 /* Controller Mode Register Bits */
2042 #define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */
2043 #define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */
2044 #define KBD_MODE_SYS 0x04 /* The system flag (?) */
2045 #define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */
2046 #define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */
2047 #define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */
2048 #define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
2049 #define KBD_MODE_RFU 0x80
2050
2051 /* Mouse Commands */
2052 #define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */
2053 #define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */
2054 #define AUX_SET_RES 0xE8 /* Set resolution */
2055 #define AUX_GET_SCALE 0xE9 /* Get scaling factor */
2056 #define AUX_SET_STREAM 0xEA /* Set stream mode */
2057 #define AUX_POLL 0xEB /* Poll */
2058 #define AUX_RESET_WRAP 0xEC /* Reset wrap mode */
2059 #define AUX_SET_WRAP 0xEE /* Set wrap mode */
2060 #define AUX_SET_REMOTE 0xF0 /* Set remote mode */
2061 #define AUX_GET_TYPE 0xF2 /* Get type */
2062 #define AUX_SET_SAMPLE 0xF3 /* Set sample rate */
2063 #define AUX_ENABLE_DEV 0xF4 /* Enable aux device */
2064 #define AUX_DISABLE_DEV 0xF5 /* Disable aux device */
2065 #define AUX_SET_DEFAULT 0xF6
2066 #define AUX_RESET 0xFF /* Reset aux device */
2067 #define AUX_ACK 0xFA /* Command byte ACK. */
2068
2069 #define MOUSE_STATUS_REMOTE 0x40
2070 #define MOUSE_STATUS_ENABLED 0x20
2071 #define MOUSE_STATUS_SCALE21 0x10
2072
2073 #define KBD_QUEUE_SIZE 256
2074
2075 typedef struct {
2076 uint8_t data[KBD_QUEUE_SIZE];
2077 int rptr, wptr, count;
2078 } KBDQueue;
2079
2080 typedef struct KBDState {
2081 KBDQueue queues[2];
2082 uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
2083 uint8_t status;
2084 uint8_t mode;
2085 /* keyboard state */
2086 int kbd_write_cmd;
2087 int scan_enabled;
2088 /* mouse state */
2089 int mouse_write_cmd;
2090 uint8_t mouse_status;
2091 uint8_t mouse_resolution;
2092 uint8_t mouse_sample_rate;
2093 uint8_t mouse_wrap;
2094 uint8_t mouse_type; /* 0 = PS2, 3 = IMPS/2, 4 = IMEX */
2095 uint8_t mouse_detect_state;
2096 int mouse_dx; /* current values, needed for 'poll' mode */
2097 int mouse_dy;
2098 int mouse_dz;
2099 uint8_t mouse_buttons;
2100 } KBDState;
2101
2102 KBDState kbd_state;
2103 int reset_requested;
2104
2105 /* update irq and KBD_STAT_[MOUSE_]OBF */
2106 /* XXX: not generating the irqs if KBD_MODE_DISABLE_KBD is set may be
2107 incorrect, but it avoids having to simulate exact delays */
2108 static void kbd_update_irq(KBDState *s)
2109 {
2110 int irq12_level, irq1_level;
2111
2112 irq1_level = 0;
2113 irq12_level = 0;
2114 s->status &= ~(KBD_STAT_OBF | KBD_STAT_MOUSE_OBF);
2115 if (s->queues[0].count != 0 ||
2116 s->queues[1].count != 0) {
2117 s->status |= KBD_STAT_OBF;
2118 if (s->queues[1].count != 0) {
2119 s->status |= KBD_STAT_MOUSE_OBF;
2120 if (s->mode & KBD_MODE_MOUSE_INT)
2121 irq12_level = 1;
2122 } else {
2123 if ((s->mode & KBD_MODE_KBD_INT) &&
2124 !(s->mode & KBD_MODE_DISABLE_KBD))
2125 irq1_level = 1;
2126 }
2127 }
2128 pic_set_irq(1, irq1_level);
2129 pic_set_irq(12, irq12_level);
2130 }
2131
2132 static void kbd_queue(KBDState *s, int b, int aux)
2133 {
2134 KBDQueue *q = &kbd_state.queues[aux];
2135
2136 #if defined(DEBUG_MOUSE) || defined(DEBUG_KBD)
2137 if (aux)
2138 printf("mouse event: 0x%02x\n", b);
2139 #ifdef DEBUG_KBD
2140 else
2141 printf("kbd event: 0x%02x\n", b);
2142 #endif
2143 #endif
2144 if (q->count >= KBD_QUEUE_SIZE)
2145 return;
2146 q->data[q->wptr] = b;
2147 if (++q->wptr == KBD_QUEUE_SIZE)
2148 q->wptr = 0;
2149 q->count++;
2150 kbd_update_irq(s);
2151 }
2152
2153 void kbd_put_keycode(int keycode)
2154 {
2155 KBDState *s = &kbd_state;
2156 kbd_queue(s, keycode, 0);
2157 }
2158
2159 uint32_t kbd_read_status(CPUX86State *env, uint32_t addr)
2160 {
2161 KBDState *s = &kbd_state;
2162 int val;
2163 val = s->status;
2164 #if defined(DEBUG_KBD) && 0
2165 printf("kbd: read status=0x%02x\n", val);
2166 #endif
2167 return val;
2168 }
2169
2170 void kbd_write_command(CPUX86State *env, uint32_t addr, uint32_t val)
2171 {
2172 KBDState *s = &kbd_state;
2173
2174 #ifdef DEBUG_KBD
2175 printf("kbd: write cmd=0x%02x\n", val);
2176 #endif
2177 switch(val) {
2178 case KBD_CCMD_READ_MODE:
2179 kbd_queue(s, s->mode, 0);
2180 break;
2181 case KBD_CCMD_WRITE_MODE:
2182 case KBD_CCMD_WRITE_OBUF:
2183 case KBD_CCMD_WRITE_AUX_OBUF:
2184 case KBD_CCMD_WRITE_MOUSE:
2185 case KBD_CCMD_WRITE_OUTPORT:
2186 s->write_cmd = val;
2187 break;
2188 case KBD_CCMD_MOUSE_DISABLE:
2189 s->mode |= KBD_MODE_DISABLE_MOUSE;
2190 break;
2191 case KBD_CCMD_MOUSE_ENABLE:
2192 s->mode &= ~KBD_MODE_DISABLE_MOUSE;
2193 break;
2194 case KBD_CCMD_TEST_MOUSE:
2195 kbd_queue(s, 0x00, 0);
2196 break;
2197 case KBD_CCMD_SELF_TEST:
2198 s->status |= KBD_STAT_SELFTEST;
2199 kbd_queue(s, 0x55, 0);
2200 break;
2201 case KBD_CCMD_KBD_TEST:
2202 kbd_queue(s, 0x00, 0);
2203 break;
2204 case KBD_CCMD_KBD_DISABLE:
2205 s->mode |= KBD_MODE_DISABLE_KBD;
2206 kbd_update_irq(s);
2207 break;
2208 case KBD_CCMD_KBD_ENABLE:
2209 s->mode &= ~KBD_MODE_DISABLE_KBD;
2210 kbd_update_irq(s);
2211 break;
2212 case KBD_CCMD_READ_INPORT:
2213 kbd_queue(s, 0x00, 0);
2214 break;
2215 case KBD_CCMD_READ_OUTPORT:
2216 /* XXX: check that */
2217 val = 0x01 | (a20_enabled << 1);
2218 if (s->status & KBD_STAT_OBF)
2219 val |= 0x10;
2220 if (s->status & KBD_STAT_MOUSE_OBF)
2221 val |= 0x20;
2222 kbd_queue(s, val, 0);
2223 break;
2224 case KBD_CCMD_ENABLE_A20:
2225 cpu_x86_set_a20(env, 1);
2226 break;
2227 case KBD_CCMD_DISABLE_A20:
2228 cpu_x86_set_a20(env, 0);
2229 break;
2230 case KBD_CCMD_RESET:
2231 reset_requested = 1;
2232 cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT);
2233 break;
2234 case 0xff:
2235 /* ignore that - I don't know what is its use */
2236 break;
2237 default:
2238 fprintf(stderr, "qemu: unsupported keyboard cmd=0x%02x\n", val);
2239 break;
2240 }
2241 }
2242
2243 uint32_t kbd_read_data(CPUX86State *env, uint32_t addr)
2244 {
2245 KBDState *s = &kbd_state;
2246 KBDQueue *q;
2247 int val, index;
2248
2249 q = &s->queues[0]; /* first check KBD data */
2250 if (q->count == 0)
2251 q = &s->queues[1]; /* then check AUX data */
2252 if (q->count == 0) {
2253 /* NOTE: if no data left, we return the last keyboard one
2254 (needed for EMM386) */
2255 /* XXX: need a timer to do things correctly */
2256 q = &s->queues[0];
2257 index = q->rptr - 1;
2258 if (index < 0)
2259 index = KBD_QUEUE_SIZE - 1;
2260 val = q->data[index];
2261 } else {
2262 val = q->data[q->rptr];
2263 if (++q->rptr == KBD_QUEUE_SIZE)
2264 q->rptr = 0;
2265 q->count--;
2266 /* reading deasserts IRQ */
2267 if (q == &s->queues[0])
2268 pic_set_irq(1, 0);
2269 else
2270 pic_set_irq(12, 0);
2271 }
2272 /* reassert IRQs if data left */
2273 kbd_update_irq(s);
2274 #ifdef DEBUG_KBD
2275 printf("kbd: read data=0x%02x\n", val);
2276 #endif
2277 return val;
2278 }
2279
2280 static void kbd_reset_keyboard(KBDState *s)
2281 {
2282 s->scan_enabled = 1;
2283 }
2284
2285 static void kbd_write_keyboard(KBDState *s, int val)
2286 {
2287 switch(s->kbd_write_cmd) {
2288 default:
2289 case -1:
2290 switch(val) {
2291 case 0x00:
2292 kbd_queue(s, KBD_REPLY_ACK, 0);
2293 break;
2294 case 0x05:
2295 kbd_queue(s, KBD_REPLY_RESEND, 0);
2296 break;
2297 case KBD_CMD_GET_ID:
2298 kbd_queue(s, KBD_REPLY_ACK, 0);
2299 kbd_queue(s, 0xab, 0);
2300 kbd_queue(s, 0x83, 0);
2301 break;
2302 case KBD_CMD_ECHO:
2303 kbd_queue(s, KBD_CMD_ECHO, 0);
2304 break;
2305 case KBD_CMD_ENABLE:
2306 s->scan_enabled = 1;
2307 kbd_queue(s, KBD_REPLY_ACK, 0);
2308 break;
2309 case KBD_CMD_SET_LEDS:
2310 case KBD_CMD_SET_RATE:
2311 s->kbd_write_cmd = val;
2312 kbd_queue(s, KBD_REPLY_ACK, 0);
2313 break;
2314 case KBD_CMD_RESET_DISABLE:
2315 kbd_reset_keyboard(s);
2316 s->scan_enabled = 0;
2317 kbd_queue(s, KBD_REPLY_ACK, 0);
2318 break;
2319 case KBD_CMD_RESET_ENABLE:
2320 kbd_reset_keyboard(s);
2321 s->scan_enabled = 1;
2322 kbd_queue(s, KBD_REPLY_ACK, 0);
2323 break;
2324 case KBD_CMD_RESET:
2325 kbd_reset_keyboard(s);
2326 kbd_queue(s, KBD_REPLY_ACK, 0);
2327 kbd_queue(s, KBD_REPLY_POR, 0);
2328 break;
2329 default:
2330 kbd_queue(s, KBD_REPLY_ACK, 0);
2331 break;
2332 }
2333 break;
2334 case KBD_CMD_SET_LEDS:
2335 kbd_queue(s, KBD_REPLY_ACK, 0);
2336 s->kbd_write_cmd = -1;
2337 break;
2338 case KBD_CMD_SET_RATE:
2339 kbd_queue(s, KBD_REPLY_ACK, 0);
2340 s->kbd_write_cmd = -1;
2341 break;
2342 }
2343 }
2344
2345 static void kbd_mouse_send_packet(KBDState *s)
2346 {
2347 unsigned int b;
2348 int dx1, dy1, dz1;
2349
2350 dx1 = s->mouse_dx;
2351 dy1 = s->mouse_dy;
2352 dz1 = s->mouse_dz;
2353 /* XXX: increase range to 8 bits ? */
2354 if (dx1 > 127)
2355 dx1 = 127;
2356 else if (dx1 < -127)
2357 dx1 = -127;
2358 if (dy1 > 127)
2359 dy1 = 127;
2360 else if (dy1 < -127)
2361 dy1 = -127;
2362 b = 0x08 | ((dx1 < 0) << 4) | ((dy1 < 0) << 5) | (s->mouse_buttons & 0x07);
2363 kbd_queue(s, b, 1);
2364 kbd_queue(s, dx1 & 0xff, 1);
2365 kbd_queue(s, dy1 & 0xff, 1);
2366 /* extra byte for IMPS/2 or IMEX */
2367 switch(s->mouse_type) {
2368 default:
2369 break;
2370 case 3:
2371 if (dz1 > 127)
2372 dz1 = 127;
2373 else if (dz1 < -127)
2374 dz1 = -127;
2375 kbd_queue(s, dz1 & 0xff, 1);
2376 break;
2377 case 4:
2378 if (dz1 > 7)
2379 dz1 = 7;
2380 else if (dz1 < -7)
2381 dz1 = -7;
2382 b = (dz1 & 0x0f) | ((s->mouse_buttons & 0x18) << 1);
2383 kbd_queue(s, b, 1);
2384 break;
2385 }
2386
2387 /* update deltas */
2388 s->mouse_dx -= dx1;
2389 s->mouse_dy -= dy1;
2390 s->mouse_dz -= dz1;
2391 }
2392
2393 void kbd_mouse_event(int dx, int dy, int dz, int buttons_state)
2394 {
2395 KBDState *s = &kbd_state;
2396
2397 /* check if deltas are recorded when disabled */
2398 if (!(s->mouse_status & MOUSE_STATUS_ENABLED))
2399 return;
2400
2401 s->mouse_dx += dx;
2402 s->mouse_dy -= dy;
2403 s->mouse_dz += dz;
2404 s->mouse_buttons = buttons_state;
2405
2406 if (!(s->mouse_status & MOUSE_STATUS_REMOTE) &&
2407 (s->queues[1].count < (KBD_QUEUE_SIZE - 16))) {
2408 for(;;) {
2409 /* if not remote, send event. Multiple events are sent if
2410 too big deltas */
2411 kbd_mouse_send_packet(s);
2412 if (s->mouse_dx == 0 && s->mouse_dy == 0 && s->mouse_dz == 0)
2413 break;
2414 }
2415 }
2416 }
2417
2418 static void kbd_write_mouse(KBDState *s, int val)
2419 {
2420 #ifdef DEBUG_MOUSE
2421 printf("kbd: write mouse 0x%02x\n", val);
2422 #endif
2423 switch(s->mouse_write_cmd) {
2424 default:
2425 case -1:
2426 /* mouse command */
2427 if (s->mouse_wrap) {
2428 if (val == AUX_RESET_WRAP) {
2429 s->mouse_wrap = 0;
2430 kbd_queue(s, AUX_ACK, 1);
2431 return;
2432 } else if (val != AUX_RESET) {
2433 kbd_queue(s, val, 1);
2434 return;
2435 }
2436 }
2437 switch(val) {
2438 case AUX_SET_SCALE11:
2439 s->mouse_status &= ~MOUSE_STATUS_SCALE21;
2440 kbd_queue(s, AUX_ACK, 1);
2441 break;
2442 case AUX_SET_SCALE21:
2443 s->mouse_status |= MOUSE_STATUS_SCALE21;
2444 kbd_queue(s, AUX_ACK, 1);
2445 break;
2446 case AUX_SET_STREAM:
2447 s->mouse_status &= ~MOUSE_STATUS_REMOTE;
2448 kbd_queue(s, AUX_ACK, 1);
2449 break;
2450 case AUX_SET_WRAP:
2451 s->mouse_wrap = 1;
2452 kbd_queue(s, AUX_ACK, 1);
2453 break;
2454 case AUX_SET_REMOTE:
2455 s->mouse_status |= MOUSE_STATUS_REMOTE;
2456 kbd_queue(s, AUX_ACK, 1);
2457 break;
2458 case AUX_GET_TYPE:
2459 kbd_queue(s, AUX_ACK, 1);
2460 kbd_queue(s, s->mouse_type, 1);
2461 break;
2462 case AUX_SET_RES:
2463 case AUX_SET_SAMPLE:
2464 s->mouse_write_cmd = val;
2465 kbd_queue(s, AUX_ACK, 1);
2466 break;
2467 case AUX_GET_SCALE:
2468 kbd_queue(s, AUX_ACK, 1);
2469 kbd_queue(s, s->mouse_status, 1);
2470 kbd_queue(s, s->mouse_resolution, 1);
2471 kbd_queue(s, s->mouse_sample_rate, 1);
2472 break;
2473 case AUX_POLL:
2474 kbd_queue(s, AUX_ACK, 1);
2475 kbd_mouse_send_packet(s);
2476 break;
2477 case AUX_ENABLE_DEV:
2478 s->mouse_status |= MOUSE_STATUS_ENABLED;
2479 kbd_queue(s, AUX_ACK, 1);
2480 break;
2481 case AUX_DISABLE_DEV:
2482 s->mouse_status &= ~MOUSE_STATUS_ENABLED;
2483 kbd_queue(s, AUX_ACK, 1);
2484 break;
2485 case AUX_SET_DEFAULT:
2486 s->mouse_sample_rate = 100;
2487 s->mouse_resolution = 2;
2488 s->mouse_status = 0;
2489 kbd_queue(s, AUX_ACK, 1);
2490 break;
2491 case AUX_RESET:
2492 s->mouse_sample_rate = 100;
2493 s->mouse_resolution = 2;
2494 s->mouse_status = 0;
2495 kbd_queue(s, AUX_ACK, 1);
2496 kbd_queue(s, 0xaa, 1);
2497 kbd_queue(s, s->mouse_type, 1);
2498 break;
2499 default:
2500 break;
2501 }
2502 break;
2503 case AUX_SET_SAMPLE:
2504 s->mouse_sample_rate = val;
2505 #if 0
2506 /* detect IMPS/2 or IMEX */
2507 switch(s->mouse_detect_state) {
2508 default:
2509 case 0:
2510 if (val == 200)
2511 s->mouse_detect_state = 1;
2512 break;
2513 case 1:
2514 if (val == 100)
2515 s->mouse_detect_state = 2;
2516 else if (val == 200)
2517 s->mouse_detect_state = 3;
2518 else
2519 s->mouse_detect_state = 0;
2520 break;
2521 case 2:
2522 if (val == 80)
2523 s->mouse_type = 3; /* IMPS/2 */
2524 s->mouse_detect_state = 0;
2525 break;
2526 case 3:
2527 if (val == 80)
2528 s->mouse_type = 4; /* IMEX */
2529 s->mouse_detect_state = 0;
2530 break;
2531 }
2532 #endif
2533 kbd_queue(s, AUX_ACK, 1);
2534 s->mouse_write_cmd = -1;
2535 break;
2536 case AUX_SET_RES:
2537 s->mouse_resolution = val;
2538 kbd_queue(s, AUX_ACK, 1);
2539 s->mouse_write_cmd = -1;
2540 break;
2541 }
2542 }
2543
2544 void kbd_write_data(CPUX86State *env, uint32_t addr, uint32_t val)
2545 {
2546 KBDState *s = &kbd_state;
2547
2548 #ifdef DEBUG_KBD
2549 printf("kbd: write data=0x%02x\n", val);
2550 #endif
2551
2552 switch(s->write_cmd) {
2553 case 0:
2554 kbd_write_keyboard(s, val);
2555 break;
2556 case KBD_CCMD_WRITE_MODE:
2557 s->mode = val;
2558 kbd_update_irq(s);
2559 break;
2560 case KBD_CCMD_WRITE_OBUF:
2561 kbd_queue(s, val, 0);
2562 break;
2563 case KBD_CCMD_WRITE_AUX_OBUF:
2564 kbd_queue(s, val, 1);
2565 break;
2566 case KBD_CCMD_WRITE_OUTPORT:
2567 cpu_x86_set_a20(env, (val >> 1) & 1);
2568 if (!(val & 1)) {
2569 reset_requested = 1;
2570 cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT);
2571 }
2572 break;
2573 case KBD_CCMD_WRITE_MOUSE:
2574 kbd_write_mouse(s, val);
2575 break;
2576 default:
2577 break;
2578 }
2579 s->write_cmd = 0;
2580 }
2581
2582 void kbd_reset(KBDState *s)
2583 {
2584 KBDQueue *q;
2585 int i;
2586
2587 s->kbd_write_cmd = -1;
2588 s->mouse_write_cmd = -1;
2589 s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT;
2590 s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED;
2591 for(i = 0; i < 2; i++) {
2592 q = &s->queues[i];
2593 q->rptr = 0;
2594 q->wptr = 0;
2595 q->count = 0;
2596 }
2597 }
2598
2599 void kbd_init(void)
2600 {
2601 kbd_reset(&kbd_state);
2602 register_ioport_read(0x60, 1, kbd_read_data, 1);
2603 register_ioport_write(0x60, 1, kbd_write_data, 1);
2604 register_ioport_read(0x64, 1, kbd_read_status, 1);
2605 register_ioport_write(0x64, 1, kbd_write_command, 1);
2606 }
2607
2608 /***********************************************************/
2609 /* Bochs BIOS debug ports */
2610
2611 void bochs_bios_write(CPUX86State *env, uint32_t addr, uint32_t val)
2612 {
2613 switch(addr) {
2614 /* Bochs BIOS messages */
2615 case 0x400:
2616 case 0x401:
2617 fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
2618 exit(1);
2619 case 0x402:
2620 case 0x403:
2621 #ifdef DEBUG_BIOS
2622 fprintf(stderr, "%c", val);
2623 #endif
2624 break;
2625
2626 /* LGPL'ed VGA BIOS messages */
2627 case 0x501:
2628 case 0x502:
2629 fprintf(stderr, "VGA BIOS panic, line %d\n", val);
2630 exit(1);
2631 case 0x500:
2632 case 0x503:
2633 #ifdef DEBUG_BIOS
2634 fprintf(stderr, "%c", val);
2635 #endif
2636 break;
2637 }
2638 }
2639
2640 void bochs_bios_init(void)
2641 {
2642 register_ioport_write(0x400, 1, bochs_bios_write, 2);
2643 register_ioport_write(0x401, 1, bochs_bios_write, 2);
2644 register_ioport_write(0x402, 1, bochs_bios_write, 1);
2645 register_ioport_write(0x403, 1, bochs_bios_write, 1);
2646
2647 register_ioport_write(0x501, 1, bochs_bios_write, 2);
2648 register_ioport_write(0x502, 1, bochs_bios_write, 2);
2649 register_ioport_write(0x500, 1, bochs_bios_write, 1);
2650 register_ioport_write(0x503, 1, bochs_bios_write, 1);
2651 }
2652
2653 /***********************************************************/
2654 /* dumb display */
2655
2656 /* init terminal so that we can grab keys */
2657 static struct termios oldtty;
2658
2659 static void term_exit(void)
2660 {
2661 tcsetattr (0, TCSANOW, &oldtty);
2662 }
2663
2664 static void term_init(void)
2665 {
2666 struct termios tty;
2667
2668 tcgetattr (0, &tty);
2669 oldtty = tty;
2670
2671 tty.c_iflag &= ~(IGNBRK|BRKINT|PARMRK|ISTRIP
2672 |INLCR|IGNCR|ICRNL|IXON);
2673 tty.c_oflag |= OPOST;
2674 tty.c_lflag &= ~(ECHO|ECHONL|ICANON|IEXTEN);
2675 /* if graphical mode, we allow Ctrl-C handling */
2676 if (nographic)
2677 tty.c_lflag &= ~ISIG;
2678 tty.c_cflag &= ~(CSIZE|PARENB);
2679 tty.c_cflag |= CS8;
2680 tty.c_cc[VMIN] = 1;
2681 tty.c_cc[VTIME] = 0;
2682
2683 tcsetattr (0, TCSANOW, &tty);
2684
2685 atexit(term_exit);
2686
2687 fcntl(0, F_SETFL, O_NONBLOCK);
2688 }
2689
2690 static void dumb_update(DisplayState *ds, int x, int y, int w, int h)
2691 {
2692 }
2693
2694 static void dumb_resize(DisplayState *ds, int w, int h)
2695 {
2696 }
2697
2698 static void dumb_refresh(DisplayState *ds)
2699 {
2700 vga_update_display();
2701 }
2702
2703 void dumb_display_init(DisplayState *ds)
2704 {
2705 ds->data = NULL;
2706 ds->linesize = 0;
2707 ds->depth = 0;
2708 ds->dpy_update = dumb_update;
2709 ds->dpy_resize = dumb_resize;
2710 ds->dpy_refresh = dumb_refresh;
2711 }
2712
2713 #if !defined(CONFIG_SOFTMMU)
2714 /***********************************************************/
2715 /* cpu signal handler */
2716 static void host_segv_handler(int host_signum, siginfo_t *info,
2717 void *puc)
2718 {
2719 if (cpu_signal_handler(host_signum, info, puc))
2720 return;
2721 term_exit();
2722 abort();
2723 }
2724 #endif
2725
2726 static int timer_irq_pending;
2727 static int timer_irq_count;
2728
2729 static int timer_ms;
2730 static int gui_refresh_pending, gui_refresh_count;
2731
2732 static void host_alarm_handler(int host_signum, siginfo_t *info,
2733 void *puc)
2734 {
2735 /* NOTE: since usually the OS asks a 100 Hz clock, there can be
2736 some drift between cpu_get_ticks() and the interrupt time. So
2737 we queue some interrupts to avoid missing some */
2738 timer_irq_count += pit_get_out_edges(&pit_channels[0]);
2739 if (timer_irq_count) {
2740 if (timer_irq_count > 2)
2741 timer_irq_count = 2;
2742 timer_irq_count--;
2743 timer_irq_pending = 1;
2744 }
2745 gui_refresh_count += timer_ms;
2746 if (gui_refresh_count >= GUI_REFRESH_INTERVAL) {
2747 gui_refresh_count = 0;
2748 gui_refresh_pending = 1;
2749 }
2750
2751 /* XXX: seems dangerous to run that here. */
2752 DMA_run();
2753 SB16_run();
2754
2755 if (gui_refresh_pending || timer_irq_pending) {
2756 /* just exit from the cpu to have a chance to handle timers */
2757 cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT);
2758 }
2759 }
2760
2761 #ifdef CONFIG_SOFTMMU
2762 void *get_mmap_addr(unsigned long size)
2763 {
2764 return NULL;
2765 }
2766 #else
2767 unsigned long mmap_addr = PHYS_RAM_BASE;
2768
2769 void *get_mmap_addr(unsigned long size)
2770 {
2771 unsigned long addr;
2772 addr = mmap_addr;
2773 mmap_addr += ((size + 4095) & ~4095) + 4096;
2774 return (void *)addr;
2775 }
2776 #endif
2777
2778 /* main execution loop */
2779
2780 CPUState *cpu_gdbstub_get_env(void *opaque)
2781 {
2782 return global_env;
2783 }
2784
2785 int main_loop(void *opaque)
2786 {
2787 struct pollfd ufds[3], *pf, *serial_ufd, *net_ufd, *gdb_ufd;
2788 int ret, n, timeout, serial_ok;
2789 uint8_t ch;
2790 CPUState *env = global_env;
2791
2792 if (!term_inited) {
2793 /* initialize terminal only there so that the user has a
2794 chance to stop QEMU with Ctrl-C before the gdb connection
2795 is launched */
2796 term_inited = 1;
2797 term_init();
2798 }
2799
2800 serial_ok = 1;
2801 cpu_enable_ticks();
2802 for(;;) {
2803 ret = cpu_x86_exec(env);
2804 if (reset_requested) {
2805 ret = EXCP_INTERRUPT;
2806 break;
2807 }
2808 if (ret == EXCP_DEBUG) {
2809 ret = EXCP_DEBUG;
2810 break;
2811 }
2812 /* if hlt instruction, we wait until the next IRQ */
2813 if (ret == EXCP_HLT)
2814 timeout = 10;
2815 else
2816 timeout = 0;
2817 /* poll any events */
2818 serial_ufd = NULL;
2819 pf = ufds;
2820 if (serial_ok && !(serial_ports[0].lsr & UART_LSR_DR)) {
2821 serial_ufd = pf;
2822 pf->fd = 0;
2823 pf->events = POLLIN;
2824 pf++;
2825 }
2826 net_ufd = NULL;
2827 if (net_fd > 0 && ne2000_can_receive(&ne2000_state)) {
2828 net_ufd = pf;
2829 pf->fd = net_fd;
2830 pf->events = POLLIN;
2831 pf++;
2832 }
2833 gdb_ufd = NULL;
2834 if (gdbstub_fd > 0) {
2835 gdb_ufd = pf;
2836 pf->fd = gdbstub_fd;
2837 pf->events = POLLIN;
2838 pf++;
2839 }
2840
2841 ret = poll(ufds, pf - ufds, timeout);
2842 if (ret > 0) {
2843 if (serial_ufd && (serial_ufd->revents & POLLIN)) {
2844 n = read(0, &ch, 1);
2845 if (n == 1) {
2846 serial_received_byte(&serial_ports[0], ch);
2847 } else {
2848 /* Closed, stop polling. */
2849 serial_ok = 0;
2850 }
2851 }
2852 if (net_ufd && (net_ufd->revents & POLLIN)) {
2853 uint8_t buf[MAX_ETH_FRAME_SIZE];
2854
2855 n = read(net_fd, buf, MAX_ETH_FRAME_SIZE);
2856 if (n > 0) {
2857 if (n < 60) {
2858 memset(buf + n, 0, 60 - n);
2859 n = 60;
2860 }
2861 ne2000_receive(&ne2000_state, buf, n);
2862 }
2863 }
2864 if (gdb_ufd && (gdb_ufd->revents & POLLIN)) {
2865 uint8_t buf[1];
2866 /* stop emulation if requested by gdb */
2867 n = read(gdbstub_fd, buf, 1);
2868 if (n == 1) {
2869 ret = EXCP_INTERRUPT;
2870 break;
2871 }
2872 }
2873 }
2874
2875 /* timer IRQ */
2876 if (timer_irq_pending) {
2877 pic_set_irq(0, 1);
2878 pic_set_irq(0, 0);
2879 timer_irq_pending = 0;
2880 /* XXX: RTC test */
2881 if (cmos_data[RTC_REG_B] & 0x50) {
2882 pic_set_irq(8, 1);
2883 }
2884 }
2885
2886 /* VGA */
2887 if (gui_refresh_pending) {
2888 display_state.dpy_refresh(&display_state);
2889 gui_refresh_pending = 0;
2890 }
2891 }
2892 cpu_disable_ticks();
2893 return ret;
2894 }
2895
2896 void help(void)
2897 {
2898 printf("QEMU PC emulator version " QEMU_VERSION ", Copyright (c) 2003 Fabrice Bellard\n"
2899 "usage: %s [options] [disk_image]\n"
2900 "\n"
2901 "'disk_image' is a raw hard image image for IDE hard disk 0\n"
2902 "\n"
2903 "Standard options:\n"
2904 "-hda/-hdb file use 'file' as IDE hard disk 0/1 image\n"
2905 "-hdc/-hdd file use 'file' as IDE hard disk 2/3 image\n"
2906 "-cdrom file use 'file' as IDE cdrom 2 image\n"
2907 "-boot [c|d] boot on hard disk (c) or CD-ROM (d)\n"
2908 "-snapshot write to temporary files instead of disk image files\n"
2909 "-m megs set virtual RAM size to megs MB\n"
2910 "-n script set network init script [default=%s]\n"
2911 "-tun-fd fd this fd talks to tap/tun, use it.\n"
2912 "-nographic disable graphical output\n"
2913 "\n"
2914 "Linux boot specific (does not require PC BIOS):\n"
2915 "-kernel bzImage use 'bzImage' as kernel image\n"
2916 "-append cmdline use 'cmdline' as kernel command line\n"
2917 "-initrd file use 'file' as initial ram disk\n"
2918 "\n"
2919 "Debug/Expert options:\n"
2920 "-s wait gdb connection to port %d\n"
2921 "-p port change gdb connection port\n"
2922 "-d output log in /tmp/vl.log\n"
2923 "-hdachs c,h,s force hard disk 0 geometry (usually qemu can guess it)\n"
2924 "-L path set the directory for the BIOS and VGA BIOS\n"
2925 "\n"
2926 "During emulation, use C-a h to get terminal commands:\n",
2927 #ifdef CONFIG_SOFTMMU
2928 "qemu",
2929 #else
2930 "qemu-fast",
2931 #endif
2932 DEFAULT_NETWORK_SCRIPT,
2933 DEFAULT_GDBSTUB_PORT);
2934 term_print_help();
2935 #ifndef CONFIG_SOFTMMU
2936 printf("\n"
2937 "NOTE: this version of QEMU is faster but it needs slightly patched OSes to\n"
2938 "work. Please use the 'qemu' executable to have a more accurate (but slower)\n"
2939 "PC emulation.\n");
2940 #endif
2941 exit(1);
2942 }
2943
2944 struct option long_options[] = {
2945 { "initrd", 1, NULL, 0, },
2946 { "hda", 1, NULL, 0, },
2947 { "hdb", 1, NULL, 0, },
2948 { "snapshot", 0, NULL, 0, },
2949 { "hdachs", 1, NULL, 0, },
2950 { "nographic", 0, NULL, 0, },
2951 { "kernel", 1, NULL, 0, },
2952 { "append", 1, NULL, 0, },
2953 { "tun-fd", 1, NULL, 0, },
2954 { "hdc", 1, NULL, 0, },
2955 { "hdd", 1, NULL, 0, },
2956 { "cdrom", 1, NULL, 0, },
2957 { "boot", 1, NULL, 0, },
2958 { NULL, 0, NULL, 0 },
2959 };
2960
2961 #ifdef CONFIG_SDL
2962 /* SDL use the pthreads and they modify sigaction. We don't
2963 want that. */
2964 #if __GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 3)
2965 extern void __libc_sigaction();
2966 #define sigaction(sig, act, oact) __libc_sigaction(sig, act, oact)
2967 #else
2968 extern void __sigaction();
2969 #define sigaction(sig, act, oact) __sigaction(sig, act, oact)
2970 #endif
2971 #endif /* CONFIG_SDL */
2972
2973 int main(int argc, char **argv)
2974 {
2975 int c, ret, initrd_size, i, use_gdbstub, gdbstub_port, long_index;
2976 int snapshot, linux_boot, total_ram_size;
2977 struct linux_params *params;
2978 struct sigaction act;
2979 struct itimerval itv;
2980 CPUX86State *env;
2981 const char *initrd_filename;
2982 const char *hd_filename[MAX_DISKS];
2983 const char *kernel_filename, *kernel_cmdline;
2984 DisplayState *ds = &display_state;
2985
2986 /* we never want that malloc() uses mmap() */
2987 mallopt(M_MMAP_THRESHOLD, 4096 * 1024);
2988 initrd_filename = NULL;
2989 for(i = 0; i < MAX_DISKS; i++)
2990 hd_filename[i] = NULL;
2991 phys_ram_size = 32 * 1024 * 1024;
2992 vga_ram_size = VGA_RAM_SIZE;
2993 pstrcpy(network_script, sizeof(network_script), DEFAULT_NETWORK_SCRIPT);
2994 use_gdbstub = 0;
2995 gdbstub_port = DEFAULT_GDBSTUB_PORT;
2996 snapshot = 0;
2997 nographic = 0;
2998 kernel_filename = NULL;
2999 kernel_cmdline = "";
3000 for(;;) {
3001 c = getopt_long_only(argc, argv, "hm:dn:sp:L:", long_options, &long_index);
3002 if (c == -1)
3003 break;
3004 switch(c) {
3005 case 0:
3006 switch(long_index) {
3007 case 0:
3008 initrd_filename = optarg;
3009 break;
3010 case 1:
3011 hd_filename[0] = optarg;
3012 break;
3013 case 2:
3014 hd_filename[1] = optarg;
3015 break;
3016 case 3:
3017 snapshot = 1;
3018 break;
3019 case 4:
3020 {
3021 int cyls, heads, secs;
3022 const char *p;
3023 p = optarg;
3024 cyls = strtol(p, (char **)&p, 0);
3025 if (*p != ',')
3026 goto chs_fail;
3027 p++;
3028 heads = strtol(p, (char **)&p, 0);
3029 if (*p != ',')
3030 goto chs_fail;
3031 p++;
3032 secs = strtol(p, (char **)&p, 0);
3033 if (*p != '\0')
3034 goto chs_fail;
3035 ide_set_geometry(0, cyls, heads, secs);
3036 chs_fail: ;
3037 }
3038 break;
3039 case 5:
3040 nographic = 1;
3041 break;
3042 case 6:
3043 kernel_filename = optarg;
3044 break;
3045 case 7:
3046 kernel_cmdline = optarg;
3047 break;
3048 case 8:
3049 net_fd = atoi(optarg);
3050 break;
3051 case 9:
3052 hd_filename[2] = optarg;
3053 break;
3054 case 10:
3055 hd_filename[3] = optarg;
3056 break;
3057 case 11:
3058 hd_filename[2] = optarg;
3059 ide_set_cdrom(2, 1);
3060 break;
3061 case 12:
3062 boot_device = optarg[0];
3063 if (boot_device != 'c' && boot_device != 'd') {
3064 fprintf(stderr, "qemu: invalid boot device '%c'\n", boot_device);
3065 exit(1);
3066 }
3067 break;
3068 }
3069 break;
3070 case 'h':
3071 help();
3072 break;
3073 case 'm':
3074 phys_ram_size = atoi(optarg) * 1024 * 1024;
3075 if (phys_ram_size <= 0)
3076 help();
3077 if (phys_ram_size > PHYS_RAM_MAX_SIZE) {
3078 fprintf(stderr, "qemu: at most %d MB RAM can be simulated\n",
3079 PHYS_RAM_MAX_SIZE / (1024 * 1024));
3080 exit(1);
3081 }
3082 break;
3083 case 'd':
3084 cpu_set_log(CPU_LOG_ALL);
3085 break;
3086 case 'n':
3087 pstrcpy(network_script, sizeof(network_script), optarg);
3088 break;
3089 case 's':
3090 use_gdbstub = 1;
3091 break;
3092 case 'p':
3093 gdbstub_port = atoi(optarg);
3094 break;
3095 case 'L':
3096 bios_dir = optarg;
3097 break;
3098 }
3099 }
3100
3101 if (optind < argc) {
3102 hd_filename[0] = argv[optind++];
3103 }
3104
3105 linux_boot = (kernel_filename != NULL);
3106
3107 if (!linux_boot && hd_filename[0] == '\0' && hd_filename[2] == '\0')
3108 help();
3109
3110 /* boot to cd by default if no hard disk */
3111 if (hd_filename[0] == '\0' && boot_device == 'c')
3112 boot_device = 'd';
3113
3114 /* init debug */
3115 setvbuf(stdout, NULL, _IOLBF, 0);
3116
3117 /* init network tun interface */
3118 if (net_fd < 0)
3119 net_init();
3120
3121 /* init the memory */
3122 total_ram_size = phys_ram_size + vga_ram_size;
3123
3124 #ifdef CONFIG_SOFTMMU
3125 phys_ram_base = malloc(total_ram_size);
3126 if (!phys_ram_base) {
3127 fprintf(stderr, "Could not allocate physical memory\n");
3128 exit(1);
3129 }
3130 #else
3131 /* as we must map the same page at several addresses, we must use
3132 a fd */
3133 {
3134 const char *tmpdir;
3135
3136 tmpdir = getenv("QEMU_TMPDIR");
3137 if (!tmpdir)
3138 tmpdir = "/tmp";
3139 snprintf(phys_ram_file, sizeof(phys_ram_file), "%s/vlXXXXXX", tmpdir);
3140 if (mkstemp(phys_ram_file) < 0) {
3141 fprintf(stderr, "Could not create temporary memory file '%s'\n",
3142 phys_ram_file);
3143 exit(1);
3144 }
3145 phys_ram_fd = open(phys_ram_file, O_CREAT | O_TRUNC | O_RDWR, 0600);
3146 if (phys_ram_fd < 0) {
3147 fprintf(stderr, "Could not open temporary memory file '%s'\n",
3148 phys_ram_file);
3149 exit(1);
3150 }
3151 ftruncate(phys_ram_fd, total_ram_size);
3152 unlink(phys_ram_file);
3153 phys_ram_base = mmap(get_mmap_addr(total_ram_size),
3154 total_ram_size,
3155 PROT_WRITE | PROT_READ, MAP_SHARED | MAP_FIXED,
3156 phys_ram_fd, 0);
3157 if (phys_ram_base == MAP_FAILED) {
3158 fprintf(stderr, "Could not map physical memory\n");
3159 exit(1);
3160 }
3161 }
3162 #endif
3163
3164 /* open the virtual block devices */
3165 for(i = 0; i < MAX_DISKS; i++) {
3166 if (hd_filename[i]) {
3167 bs_table[i] = bdrv_open(hd_filename[i], snapshot);
3168 if (!bs_table[i]) {
3169 fprintf(stderr, "qemu: could not open hard disk image '%s\n",
3170 hd_filename[i]);
3171 exit(1);
3172 }
3173 }
3174 }
3175
3176 /* init CPU state */
3177 env = cpu_init();
3178 global_env = env;
3179 cpu_single_env = env;
3180
3181 init_ioports();
3182
3183 /* allocate RAM */
3184 cpu_register_physical_memory(0, phys_ram_size, 0);
3185
3186 if (linux_boot) {
3187 /* now we can load the kernel */
3188 ret = load_kernel(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
3189 if (ret < 0) {
3190 fprintf(stderr, "qemu: could not load kernel '%s'\n",
3191 kernel_filename);
3192 exit(1);
3193 }
3194
3195 /* load initrd */
3196 initrd_size = 0;
3197 if (initrd_filename) {
3198 initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
3199 if (initrd_size < 0) {
3200 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
3201 initrd_filename);
3202 exit(1);
3203 }
3204 }
3205
3206 /* init kernel params */
3207 params = (void *)(phys_ram_base + KERNEL_PARAMS_ADDR);
3208 memset(params, 0, sizeof(struct linux_params));
3209 params->mount_root_rdonly = 0;
3210 stw_raw(&params->cl_magic, 0xA33F);
3211 stw_raw(&params->cl_offset, params->commandline - (uint8_t *)params);
3212 stl_raw(&params->alt_mem_k, (phys_ram_size / 1024) - 1024);
3213 pstrcat(params->commandline, sizeof(params->commandline), kernel_cmdline);
3214 params->loader_type = 0x01;
3215 if (initrd_size > 0) {
3216 stl_raw(&params->initrd_start, INITRD_LOAD_ADDR);
3217 stl_raw(&params->initrd_size, initrd_size);
3218 }
3219 params->orig_video_lines = 25;
3220 params->orig_video_cols = 80;
3221
3222 /* setup basic memory access */
3223 env->cr[0] = 0x00000033;
3224 cpu_x86_init_mmu(env);
3225
3226 memset(params->idt_table, 0, sizeof(params->idt_table));
3227
3228 stq_raw(&params->gdt_table[2], 0x00cf9a000000ffffLL); /* KERNEL_CS */
3229 stq_raw(&params->gdt_table[3], 0x00cf92000000ffffLL); /* KERNEL_DS */
3230 /* for newer kernels (2.6.0) CS/DS are at different addresses */
3231 stq_raw(&params->gdt_table[12], 0x00cf9a000000ffffLL); /* KERNEL_CS */
3232 stq_raw(&params->gdt_table[13], 0x00cf92000000ffffLL); /* KERNEL_DS */
3233
3234 env->idt.base = (void *)((uint8_t *)params->idt_table - phys_ram_base);
3235 env->idt.limit = sizeof(params->idt_table) - 1;
3236 env->gdt.base = (void *)((uint8_t *)params->gdt_table - phys_ram_base);
3237 env->gdt.limit = sizeof(params->gdt_table) - 1;
3238
3239 cpu_x86_load_seg_cache(env, R_CS, KERNEL_CS, NULL, 0xffffffff, 0x00cf9a00);
3240 cpu_x86_load_seg_cache(env, R_DS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
3241 cpu_x86_load_seg_cache(env, R_ES, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
3242 cpu_x86_load_seg_cache(env, R_SS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
3243 cpu_x86_load_seg_cache(env, R_FS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
3244 cpu_x86_load_seg_cache(env, R_GS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
3245
3246 env->eip = KERNEL_LOAD_ADDR;
3247 env->regs[R_ESI] = KERNEL_PARAMS_ADDR;
3248 env->eflags = 0x2;
3249
3250 } else {
3251 char buf[1024];
3252
3253 /* RAW PC boot */
3254
3255 /* BIOS load */
3256 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
3257 ret = load_image(buf, phys_ram_base + 0x000f0000);
3258 if (ret != 0x10000) {
3259 fprintf(stderr, "qemu: could not load PC bios '%s'\n", buf);
3260 exit(1);
3261 }
3262
3263 /* VGA BIOS load */
3264 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
3265 ret = load_image(buf, phys_ram_base + 0x000c0000);
3266
3267 /* setup basic memory access */
3268 env->cr[0] = 0x60000010;
3269 cpu_x86_init_mmu(env);
3270
3271 env->idt.limit = 0xffff;
3272 env->gdt.limit = 0xffff;
3273 env->ldt.limit = 0xffff;
3274 env->ldt.flags = DESC_P_MASK;
3275 env->tr.limit = 0xffff;
3276 env->tr.flags = DESC_P_MASK;
3277
3278 /* not correct (CS base=0xffff0000) */
3279 cpu_x86_load_seg_cache(env, R_CS, 0xf000, (uint8_t *)0x000f0000, 0xffff, 0);
3280 cpu_x86_load_seg_cache(env, R_DS, 0, NULL, 0xffff, 0);
3281 cpu_x86_load_seg_cache(env, R_ES, 0, NULL, 0xffff, 0);
3282 cpu_x86_load_seg_cache(env, R_SS, 0, NULL, 0xffff, 0);
3283 cpu_x86_load_seg_cache(env, R_FS, 0, NULL, 0xffff, 0);
3284 cpu_x86_load_seg_cache(env, R_GS, 0, NULL, 0xffff, 0);
3285
3286 env->eip = 0xfff0;
3287 env->regs[R_EDX] = 0x600; /* indicate P6 processor */
3288
3289 env->eflags = 0x2;
3290
3291 bochs_bios_init();
3292 }
3293
3294 /* terminal init */
3295 if (nographic) {
3296 dumb_display_init(ds);
3297 } else {
3298 #ifdef CONFIG_SDL
3299 sdl_display_init(ds);
3300 #else
3301 dumb_display_init(ds);
3302 #endif
3303 }
3304 /* init basic PC hardware */
3305 register_ioport_write(0x80, 1, ioport80_write, 1);
3306
3307 vga_init(ds, phys_ram_base + phys_ram_size, phys_ram_size,
3308 vga_ram_size);
3309 cmos_init();
3310 pic_init();
3311 pit_init();
3312 serial_init();
3313 ne2000_init();
3314 ide_init();
3315 kbd_init();
3316 AUD_init();
3317 DMA_init();
3318 SB16_init();
3319
3320 /* setup cpu signal handlers for MMU / self modifying code handling */
3321 sigfillset(&act.sa_mask);
3322 act.sa_flags = SA_SIGINFO;
3323 #if !defined(CONFIG_SOFTMMU)
3324 act.sa_sigaction = host_segv_handler;
3325 sigaction(SIGSEGV, &act, NULL);
3326 sigaction(SIGBUS, &act, NULL);
3327 #endif
3328
3329 act.sa_sigaction = host_alarm_handler;
3330 sigaction(SIGALRM, &act, NULL);
3331
3332 itv.it_interval.tv_sec = 0;
3333 itv.it_interval.tv_usec = 1000;
3334 itv.it_value.tv_sec = 0;
3335 itv.it_value.tv_usec = 10 * 1000;
3336 setitimer(ITIMER_REAL, &itv, NULL);
3337 /* we probe the tick duration of the kernel to inform the user if
3338 the emulated kernel requested a too high timer frequency */
3339 getitimer(ITIMER_REAL, &itv);
3340 timer_ms = itv.it_interval.tv_usec / 1000;
3341 pit_min_timer_count = ((uint64_t)itv.it_interval.tv_usec * PIT_FREQ) /
3342 1000000;
3343
3344 if (use_gdbstub) {
3345 cpu_gdbstub(NULL, main_loop, gdbstub_port);
3346 } else {
3347 main_loop(NULL);
3348 }
3349 return 0;
3350 }
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