+ # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are\r
+ # specific to their containing address spaces. In order to get the physical\r
+ # address for the CPU, for a given access, the respective translation value\r
+ # has to be added.\r
+ #\r
+ # The translations always have to be initialized like this, using UINT64:\r
+ #\r
+ # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space\r
+ # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space\r
+ # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space\r
+ #\r
+ # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;\r
+ # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r
+ # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r
+ #\r
+ # because (a) the target address space (ie. the cpu-physical space) is\r
+ # 64-bit, and (b) the translation values are meant as offsets for *modular*\r
+ # arithmetic.\r
+ #\r
+ # Accordingly, the translation itself needs to be implemented as:\r
+ #\r
+ # UINT64 UntranslatedIoAddress; // input parameter\r
+ # UINT32 UntranslatedMmio32Address; // input parameter\r
+ # UINT64 UntranslatedMmio64Address; // input parameter\r
+ #\r
+ # UINT64 TranslatedIoAddress; // output parameter\r
+ # UINT64 TranslatedMmio32Address; // output parameter\r
+ # UINT64 TranslatedMmio64Address; // output parameter\r
+ #\r
+ # TranslatedIoAddress = UntranslatedIoAddress +\r
+ # PcdPciIoTranslation;\r
+ # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +\r
+ # PcdPciMmio32Translation;\r
+ # TranslatedMmio64Address = UntranslatedMmio64Address +\r
+ # PcdPciMmio64Translation;\r
+ #\r
+ # The modular arithmetic performed in UINT64 ensures that the translation\r
+ # works correctly regardless of the relation between IoCpuBase and\r
+ # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and\r
+ # PcdPciMmio64Base.\r
+ #\r
+ gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050\r
+ gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051\r
+ gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052\r
+ gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053\r
+ gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054\r
+ gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055\r
+ gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056\r
+ gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057\r
+ gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058\r
+\r
+ #\r
+ # Inclusive range of allowed PCI buses.\r
+ #\r
+ gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059\r
+ gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A\r