+\r
+ #\r
+ # CPU options\r
+ #\r
+ DEFINE MAX_LOGICAL_PROCESSORS = 64\r
+\r
+ #\r
+ # PCI options\r
+ #\r
+ DEFINE PCIE_BASE = 0xE0000000\r
+\r
+ #\r
+ # Serial port set up\r
+ #\r
+ DEFINE BAUD_RATE = 115200\r
+ DEFINE SERIAL_CLOCK_RATE = 1843200\r
+ DEFINE SERIAL_LINE_CONTROL = 3 # 8-bits, no parity\r
+ DEFINE SERIAL_HARDWARE_FLOW_CONTROL = FALSE\r
+ DEFINE SERIAL_DETECT_CABLE = FALSE\r
+ DEFINE SERIAL_FIFO_CONTROL = 7 # Enable FIFO\r
+ DEFINE SERIAL_EXTENDED_TX_FIFO_SIZE = 16\r
+ DEFINE UART_DEFAULT_BAUD_RATE = $(BAUD_RATE)\r
+ DEFINE UART_DEFAULT_DATA_BITS = 8\r
+ DEFINE UART_DEFAULT_PARITY = 1\r
+ DEFINE UART_DEFAULT_STOP_BITS = 1\r
+ DEFINE DEFAULT_TERMINAL_TYPE = 0\r
+\r
+ #\r
+ # typedef struct {\r
+ # UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.\r
+ # UINT16 DeviceId; ///< Device ID to match the PCI device\r
+ # UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz\r
+ # UINT64 Offset; ///< The byte offset into to the BAR\r
+ # UINT8 BarIndex; ///< Which BAR to get the UART base address\r
+ # UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.\r
+ # UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.\r
+ # UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.\r
+ # UINT8 Reserved[2];\r
+ # } PCI_SERIAL_PARAMETER;\r
+ #\r
+ # Vendor FFFF Device 0000 Prog Interface 1, BAR #0, Offset 0, Stride = 1, Clock 1843200 (0x1c2000)\r
+ #\r
+ # [Vendor] [Device] [----ClockRate---] [------------Offset-----------] [Bar] [Stride] [RxFifo] [TxFifo] [Rsvd] [Vendor]\r
+ DEFINE PCI_SERIAL_PARAMETERS = {0xff,0xff, 0x00,0x00, 0x0,0x20,0x1c,0x00, 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, 0x00, 0x01, 0x0,0x0, 0x0,0x0, 0x0,0x0, 0xff,0xff}\r
+\r
+ #\r
+ # Chipset options\r
+ #\r
+ DEFINE USE_HPET_TIMER = FALSE\r
+\r
+ #\r
+ # Shell options: [BUILD_SHELL, FULL_BIN, MIN_BIN, NONE, UEFI]\r
+ #\r
+ DEFINE SHELL_TYPE = FULL_BIN\r
+\r