+ ## Indicates if BiosVideo driver will switch to 80x25 Text VGA Mode when\r
+ # exiting boot service.\r
+ # TRUE - Switch to Text VGA Mode.\r
+ # FALSE - Does not switch to Text VGA Mode.\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdBiosVideoSetTextVgaModeEnable|FALSE|BOOLEAN|0x28\r
+\r
+ ## Indicates if BiosVideo driver will check for VESA BIOS Extension service\r
+ # support.\r
+ # TRUE - Check for VESA BIOS Extension service.\r
+ # FALSE - Does not check for VESA BIOS Extension service.\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdBiosVideoCheckVbeEnable|TRUE|BOOLEAN|0x29\r
+\r
+ ## Indicates if BiosVideo driver will check for VGA service support.\r
+ # NOTE: If both PcdBiosVideoCheckVbeEnable and PcdBiosVideoCheckVgaEnable\r
+ # are set to FALSE, that means Graphics Output protocol will not be\r
+ # installed, the VGA miniport protocol will be installed instead.\r
+ # TRUE - Check for VGA service.<BR>\r
+ # FALSE - Does not check for VGA service.<BR>\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdBiosVideoCheckVgaEnable|TRUE|BOOLEAN|0x2a\r
+\r
+ ## Indicates if memory space for legacy region will be set as cacheable.\r
+ # TRUE - Set cachebility for legacy region.\r
+ # FALSE - Does not set cachebility for legacy region.\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdLegacyBiosCacheLegacyRegion|TRUE|BOOLEAN|0x2b\r
+\r
+ ## Specify memory size with bytes to reserve EBDA below 640K for OPROM.\r
+ # The value should be a multiple of 4KB.\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdEbdaReservedMemorySize|0x8000|UINT32|0x2c\r
+\r
+ ## Specify memory base address for OPROM to find free memory.\r
+ # Some OPROMs do not use EBDA or PMM to allocate memory for its usage,\r
+ # instead they find the memory filled with zero from 0x20000.\r
+ # The value should be a multiple of 4KB.\r
+ # The range should be below the EBDA reserved range from\r
+ # (CONVENTIONAL_MEMORY_TOP - Reserved EBDA Memory Size) to\r
+ # CONVENTIONAL_MEMORY_TOP.\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOpromReservedMemoryBase|0x60000|UINT32|0x2d\r
+\r
+ ## Specify memory size with bytes for OPROM to find free memory.\r
+ # The value should be a multiple of 4KB. And the range should be below the\r
+ # EBDA reserved range from\r
+ # (CONVENTIONAL_MEMORY_TOP - Reserved EBDA Memory Size) to\r
+ # CONVENTIONAL_MEMORY_TOP.\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOpromReservedMemorySize|0x28000|UINT32|0x2e\r
+\r
+ ## Specify the end of address below 1MB for the OPROM.\r
+ # The last shadowed OpROM should not exceed this address.\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdEndOpromShadowAddress|0xdffff|UINT32|0x2f\r
+\r
+ ## Specify the low PMM (Post Memory Manager) size with bytes below 1MB.\r
+ # The value should be a multiple of 4KB.\r
+ # @Prompt Low PMM (Post Memory Manager) Size\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdLowPmmMemorySize|0x10000|UINT32|0x30\r
+\r
+ ## Specify the high PMM (Post Memory Manager) size with bytes above 1MB.\r
+ # The value should be a multiple of 4KB.\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdHighPmmMemorySize|0x400000|UINT32|0x31\r
+\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdXenPvhStartOfDayStructPtr|0x0|UINT32|0x17\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdXenPvhStartOfDayStructPtrSize|0x0|UINT32|0x32\r
+\r
+ ## Number of page frames to use for storing grant table entries.\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdXenGrantFrames|4|UINT32|0x33\r
+\r
+ ## Specify the extra page table needed to mark the GHCB as unencrypted.\r
+ # The value should be a multiple of 4KB for each.\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableBase|0x0|UINT32|0x3e\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableSize|0x0|UINT32|0x3f\r
+\r
+ ## The base address of the SEC GHCB page used by SEV-ES.\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBase|0|UINT32|0x40\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbSize|0|UINT32|0x41\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupBase|0|UINT32|0x44\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupSize|0|UINT32|0x45\r
+\r
+ ## The base address and size of the SEV Launch Secret Area provisioned\r
+ # after remote attestation. If this is set in the .fdf, the platform\r
+ # is responsible for protecting the area from DXE phase overwrites.\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdSevLaunchSecretBase|0x0|UINT32|0x42\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdSevLaunchSecretSize|0x0|UINT32|0x43\r
+\r
+ ## The base address and size of a hash table confirming allowed\r
+ # parameters to be passed in via the Qemu firmware configuration\r
+ # device\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdQemuHashTableBase|0x0|UINT32|0x47\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdQemuHashTableSize|0x0|UINT32|0x48\r
+\r
+ ## The base address and size of the work area used during the SEC\r
+ # phase by the SEV and TDX supports.\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase|0|UINT32|0x49\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaSize|0|UINT32|0x50\r
+\r
+ ## The work area contains a fixed size header in the Include/WorkArea.h.\r
+ # The size of this header is used early boot, and is provided through\r
+ # a fixed PCD. It need to be kept in sync with any changes to the\r
+ # header definition.\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentialComputingWorkAreaHeader|4|UINT32|0x51\r
+\r
+ ## The base address and size of the TDX Cfv base and size.\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdCfvBase|0|UINT32|0x52\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdCfvRawDataOffset|0|UINT32|0x53\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdCfvRawDataSize|0|UINT32|0x54\r
+\r
+ ## The base address and size of the TDX Bfv base and size.\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdBfvBase|0|UINT32|0x55\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdBfvRawDataOffset|0|UINT32|0x56\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdBfvRawDataSize|0|UINT32|0x57\r
+\r
+ ## The base address and size of the SEV-SNP Secrets Area that contains\r
+ # the VM platform communication key used to send and recieve the\r
+ # messages to the PSP. If this is set in the .fdf, the platform\r
+ # is responsible to reserve this area from DXE phase overwrites.\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSnpSecretsBase|0|UINT32|0x58\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSnpSecretsSize|0|UINT32|0x59\r
+\r
+ ## The base address and size of a CPUID Area that contains the hypervisor\r
+ # provided CPUID results. In the case of SEV-SNP, the CPUID results are\r
+ # filtered by the SEV-SNP firmware. If this is set in the .fdf, the\r
+ # platform is responsible to reserve this area from DXE phase overwrites.\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidBase|0|UINT32|0x60\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidSize|0|UINT32|0x61\r
+\r
+ ## The range of memory that is validated by the SEC phase.\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecValidatedStart|0|UINT32|0x62\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecValidatedEnd|0|UINT32|0x63\r
+\r
+ ## The Tdx accept page size. 0x1000(4k),0x200000(2M)\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdTdxAcceptPageSize|0x200000|UINT32|0x65\r
+\r
+ ## The QEMU fw_cfg variable that UefiDriverEntryPointFwCfgOverrideLib will\r
+ # check to decide whether to abort dispatch of the driver it is linked into.\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdEntryPointOverrideFwCfgVarName|""|VOID*|0x68\r
+\r