+ ## Specifies delay value in microseconds after sending out an INIT IPI.\r
+ # @Prompt Configure delay value after send an INIT IPI\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10000|UINT32|0x30000002\r
+\r
+ ## This value specifies the Application Processor (AP) stack size, used for Mp Service, which must\r
+ ## aligns the address on a 4-KByte boundary.\r
+ # @Prompt Configure stack size for Application Processor (AP)\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x8000|UINT32|0x00000003\r
+\r
+ ## Specifies stack size in the temporary RAM. 0 means half of TemporaryRamSize.\r
+ # @Prompt Stack size in the temporary RAM.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0|UINT32|0x10001003\r
+\r
+ ## Specifies buffer size in bytes to save SMM profile data. The value should be a multiple of 4KB.\r
+ # @Prompt SMM profile data buffer size.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileSize|0x200000|UINT32|0x32132107\r
+\r
+ ## Specifies stack size in bytes for each processor in SMM.\r
+ # @Prompt Processor stack size in SMM.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x2000|UINT32|0x32132105\r
+\r
+ ## Indicates if SMM Code Access Check is enabled.\r
+ # If enabled, the SMM handler cannot execute the code outside SMM regions.\r
+ # This PCD is suggested to TRUE in production image.<BR><BR>\r
+ # TRUE - SMM Code Access Check will be enabled.<BR>\r
+ # FALSE - SMM Code Access Check will be disabled.<BR>\r
+ # @Prompt SMM Code Access Check.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable|TRUE|BOOLEAN|0x60000013\r
+\r
+ ## Specifies the number of variable MTRRs reserved for OS use. The default number of\r
+ # MTRRs reserved for OS use is 2.\r
+ # @Prompt Number of reserved variable MTRRs.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0x2|UINT32|0x00000015\r
+\r
+ ## Specifies buffer size in bytes for STM exception stack. The value should be a multiple of 4KB.\r
+ # @Prompt STM exception stack size.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStmExceptionStackSize|0x1000|UINT32|0x32132111\r
+\r
+ ## Specifies buffer size in bytes of MSEG. The value should be a multiple of 4KB.\r
+ # @Prompt MSEG size.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize|0x200000|UINT32|0x32132112\r
+\r
+ ## Specifies the supported CPU features bit in array.\r
+ # @Prompt Supported CPU features.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSupport|{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}|VOID*|0x00000016\r
+\r
+ ## Specifies if CPU features will be initialized after SMM relocation.\r
+ # @Prompt If CPU features will be initialized after SMM relocation.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitAfterSmmRelocation|FALSE|BOOLEAN|0x0000001C\r
+\r
+ ## Specifies if CPU features will be initialized during S3 resume.\r
+ # @Prompt If CPU features will be initialized during S3 resume.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume|FALSE|BOOLEAN|0x0000001D\r
+\r
+[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]\r
+ ## Specifies max supported number of Logical Processors.\r
+ # @Prompt Configure max supported number of Logical Processors\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64|UINT32|0x00000002\r
+ ## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.\r
+ # @Prompt Timeout for the BSP to detect all APs for the first time.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000|UINT32|0x00000004\r
+ ## Specifies the base address of the first microcode Patch in the microcode Region.\r
+ # @Prompt Microcode Region base address.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x00000005\r
+ ## Specifies the size of the microcode Region.\r
+ # @Prompt Microcode Region size.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x00000006\r
+ ## Specifies the AP wait loop state during POST phase.\r
+ # The value is defined as below.<BR><BR>\r
+ # 1: Place AP in the Hlt-Loop state.<BR>\r
+ # 2: Place AP in the Mwait-Loop state.<BR>\r
+ # 3: Place AP in the Run-Loop state.<BR>\r
+ # @Prompt The AP wait loop state.\r
+ # @ValidRange 0x80000001 | 1 - 3\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|1|UINT8|0x60008006\r
+ ## Specifies the AP target C-state for Mwait during POST phase.\r
+ # The default value 0 means C1 state.\r
+ # The value is defined as below.<BR><BR>\r
+ # @Prompt The specified AP target C-state for Mwait.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0|UINT8|0x00000007\r
+\r
+ ## Indicates if SMM uses static page table.\r
+ # If enabled, SMM will not use on-demand paging. SMM will build static page table for all memory.<BR><BR>\r
+ # This flag only impacts X64 build, because SMM alway builds static page table for IA32.\r
+ # TRUE - SMM uses static page table for all memory.<BR>\r
+ # FALSE - SMM uses static page table for below 4G memory and use on-demand paging for above 4G memory.<BR>\r
+ # @Prompt Use static page table for all memory in SMM.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStaticPageTable|TRUE|BOOLEAN|0x3213210D\r
+\r
+ ## Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM.\r
+ # @Prompt AP synchronization timeout value in SMM.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x32132104\r
+\r
+ ## Indicates the CPU synchronization method used when processing an SMI.\r
+ # 0x00 - Traditional CPU synchronization method.<BR>\r
+ # 0x01 - Relaxed CPU synchronization method.<BR>\r
+ # @Prompt SMM CPU Synchronization Method.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode|0x00|UINT8|0x60000014\r
+\r
+ ## Specifies user's desired settings for enabling/disabling processor features.\r
+ # @Prompt User settings for enabling/disabling processor features.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesUserConfiguration|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000017\r
+\r
+ ## Specifies the On-demand clock modulation duty cycle when ACPI feature is enabled.\r
+ # @Prompt The encoded values for target duty cycle modulation.\r
+ # @ValidRange 0x80000001 | 0 - 15\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle|0x0|UINT8|0x0000001A\r
+\r
+ ## Indicates if the current boot is a power-on reset.<BR><BR>\r
+ # TRUE - Current boot is a power-on reset.<BR>\r
+ # FALSE - Current boot is not a power-on reset.<BR>\r
+ # @Prompt Current boot is a power-on reset.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset|FALSE|BOOLEAN|0x0000001B\r
+\r
+[PcdsDynamic, PcdsDynamicEx]\r
+ ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.\r
+ # @Prompt The pointer to a CPU S3 data buffer.\r
+ # @ValidList 0x80000001 | 0\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0x0|UINT64|0x60000010\r
+\r
+ ## Contains the pointer to a CPU Hot Plug Data structure if CPU hot-plug is supported.\r
+ # @Prompt The pointer to CPU Hot Plug Data.\r
+ # @ValidList 0x80000001 | 0\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0x0|UINT64|0x60000011\r
+\r
+ ## Indicates processor feature capabilities, each bit corresponding to a specific feature.\r
+ # @Prompt Processor feature capabilities.\r
+ # @ValidList 0x80000001 | 0\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000018\r
+\r
+ ## Specifies actual settings for processor features, each bit corresponding to a specific feature.\r
+ # @Prompt Actual processor feature settings.\r
+ # @ValidList 0x80000001 | 0\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000019\r
+\r
+[UserExtensions.TianoCore."ExtraFiles"]\r
+ UefiCpuPkgExtra.uni\r