# ARM processor package.\r
#\r
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r
+# Copyright (c) 2011 - 2018, ARM Limited. All rights reserved.\r
#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
#\r
#**/\r
\r
\r
[LibraryClasses.common]\r
ArmLib|Include/Library/ArmLib.h\r
+ ArmMmuLib|Include/Library/ArmMmuLib.h\r
SemihostLib|Include/Library/Semihosting.h\r
- UncachedMemoryAllocationLib|Include/Library/UncachedMemoryAllocationLib.h\r
DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h\r
ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h\r
- \r
+ ArmGicArchLib|Include/Library/ArmGicArchLib.h\r
+ ArmMtlLib|ArmPlatformPkg/Include/Library/ArmMtlLib.h\r
+ ArmSvcLib|Include/Library/ArmSvcLib.h\r
+ OpteeLib|Include/Library/OpteeLib.h\r
+ StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h\r
+\r
[Guids.common]\r
gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }\r
\r
+ ## ARM MPCore table\r
+ # Include/Guid/ArmMpCoreInfo.h\r
+ gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }\r
+\r
[Protocols.common]\r
- gVirtualUncachedPagesProtocolGuid = { 0xAD651C7D, 0x3C22, 0x4DBF, { 0x92, 0xe8, 0x38, 0xa7, 0xcd, 0xae, 0x87, 0xb2 } }\r
+ ## Arm System Control and Management Interface(SCMI) Base protocol\r
+ ## ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h\r
+ gArmScmiBaseProtocolGuid = { 0xd7e5abe9, 0x33ab, 0x418e, { 0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f } }\r
+\r
+ ## Arm System Control and Management Interface(SCMI) Clock management protocol\r
+ ## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h\r
+ gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } }\r
+ gArmScmiClock2ProtocolGuid = { 0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } }\r
+\r
+ ## Arm System Control and Management Interface(SCMI) Clock management protocol\r
+ ## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h\r
+ gArmScmiPerformanceProtocolGuid = { 0x9b8ba84, 0x3dd3, 0x49a6, { 0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad } }\r
+\r
+[Ppis]\r
+ ## Include/Ppi/ArmMpCoreInfo.h\r
+ gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }\r
\r
[PcdsFeatureFlag.common]\r
gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001\r
# On ARM Architecture with the Security Extension, the address for the\r
# Vector Table can be mapped anywhere in the memory map. It means we can\r
# point the Exception Vector Table to its location in CpuDxe.\r
- # By default we copy the Vector Table at PcdGet32(PcdCpuVectorBaseAddress)\r
+ # By default we copy the Vector Table at PcdGet64(PcdCpuVectorBaseAddress)\r
gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022\r
# Set this PCD to TRUE if the Exception Vector is changed to add debugger support before\r
# it has been configured by the CPU DXE\r
gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032\r
- \r
- gArmTokenSpaceGuid.PcdEfiUncachedMemoryToStronglyOrdered|FALSE|BOOLEAN|0x00000025\r
+\r
+ # Define if the GICv3 controller should use the GICv2 legacy\r
+ gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042\r
+\r
+[PcdsFeatureFlag.ARM]\r
+ # Whether to map normal memory as non-shareable. FALSE is the safe choice, but\r
+ # TRUE may be appropriate to fix performance problems if you don't care about\r
+ # hardware coherency (i.e., no virtualization or cache coherent DMA)\r
+ gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043\r
+\r
+[PcdsFeatureFlag.AARCH64]\r
+ ## Used to select method for requesting services from S-EL1.<BR><BR>\r
+ # TRUE - Selects FF-A calls for communication between S-EL0 and SPMC.<BR>\r
+ # FALSE - Selects SVC calls for communication between S-EL0 and SPMC.<BR>\r
+ # @Prompt Enable FF-A support.\r
+ gArmTokenSpaceGuid.PcdFfaEnable|FALSE|BOOLEAN|0x0000005B\r
\r
[PcdsFixedAtBuild.common]\r
+ gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006\r
+\r
# This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.\r
# Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.\r
gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024\r
\r
- gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000080000000|UINT64|0x00000002\r
- gArmTokenSpaceGuid.PcdArmCacheOperationThreshold|1024|UINT32|0x00000003\r
- gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT32|0x00000004\r
+ gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004\r
gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005\r
- \r
- #\r
- # ARM PL390 General Interrupt Controller\r
- #\r
- gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C\r
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D\r
- gArmTokenSpaceGuid.PcdGicNumInterrupts|96|UINT32|0x00000023\r
\r
#\r
# ARM Secure Firmware PCDs\r
#\r
- gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT32|0x00000015\r
+ gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015\r
gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016\r
- gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT32|0x0000002F\r
+ gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F\r
gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030\r
\r
#\r
- # ARM Normal (or Non Secure) Firmware PCDs\r
+ # ARM Hypervisor Firmware PCDs\r
#\r
- gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT32|0x0000002B\r
- gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C\r
- gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT32|0x0000002D\r
- gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E\r
-\r
- # System Memory (DRAM): These PCDs define the region of in-built system memory\r
- # Some platforms can get DRAM extensions, these additional regions will be declared\r
- # to UEFI by ArmPLatformPlib \r
- gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT32|0x00000029\r
- gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT32|0x0000002A\r
+ gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A\r
+ gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B\r
+ gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C\r
+ gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D\r
\r
# Use ClusterId + CoreId to identify the PrimaryCore\r
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031\r
- # The Primary Core is ClusterId[0] & CoreId[0] \r
+ # The Primary Core is ClusterId[0] & CoreId[0]\r
gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037\r
\r
#\r
- # ARM MPCore MailBox PCDs\r
+ # SMBIOS PCDs\r
#\r
- # Address to Set/Get to Mailbox in Multicore system\r
- gArmTokenSpaceGuid.PcdMPCoreMailboxSetAddress|0|UINT32|0x00000017\r
- gArmTokenSpaceGuid.PcdMPCoreMailboxGetAddress|0|UINT32|0x00000018\r
- # Address/Value to clear Mailbox in Multicore system\r
- gArmTokenSpaceGuid.PcdMPCoreMailboxClearAddress|0|UINT32|0x00000019\r
- gArmTokenSpaceGuid.PcdMPCoreMailboxClearValue|0|UINT32|0x0000001A\r
+ gArmTokenSpaceGuid.PcdSystemProductName|L""|VOID*|0x30000053\r
+ gArmTokenSpaceGuid.PcdSystemVersion|L""|VOID*|0x30000054\r
+ gArmTokenSpaceGuid.PcdBaseBoardManufacturer|L""|VOID*|0x30000055\r
+ gArmTokenSpaceGuid.PcdBaseBoardProductName|L""|VOID*|0x30000056\r
+ gArmTokenSpaceGuid.PcdBaseBoardVersion|L""|VOID*|0x30000057\r
+ gArmTokenSpaceGuid.PcdProcessorManufacturer|L""|VOID*|0x30000071\r
+ gArmTokenSpaceGuid.PcdProcessorVersion|L""|VOID*|0x30000072\r
+ gArmTokenSpaceGuid.PcdProcessorSerialNumber|L""|VOID*|0x30000073\r
+ gArmTokenSpaceGuid.PcdProcessorAssetTag|L""|VOID*|0x30000074\r
+ gArmTokenSpaceGuid.PcdProcessorPartNumber|L""|VOID*|0x30000075\r
\r
#\r
# ARM L2x0 PCDs\r
#\r
gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B\r
- \r
+\r
#\r
- # ARM PL390 General Interrupt Controller\r
+ # ARM Normal (or Non Secure) Firmware PCDs\r
+ #\r
+ gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C\r
+ gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E\r
+\r
+ #\r
+ # Value to add to a host address to obtain a device address, using\r
+ # unsigned 64-bit integer arithmetic on both ARM and AArch64. This\r
+ # means we can rely on truncation on overflow to specify negative\r
+ # offsets.\r
+ #\r
+ gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044\r
+\r
+[PcdsFixedAtBuild.common, PcdsPatchableInModule.common]\r
+ gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B\r
+ gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D\r
+\r
+[PcdsFixedAtBuild.ARM]\r
#\r
- gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000001C\r
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000001D\r
- \r
- # \r
- # BdsLib\r
+ # ARM Security Extension\r
#\r
- gArmTokenSpaceGuid.PcdArmMachineType|0|UINT32|0x0000001E\r
- # The compressed Linux kernel is expected to be under 128MB from the beginning of the System Memory\r
- gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x08000000|UINT32|0x0000001F\r
- # The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory\r
- gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020\r
\r
+ # Secure Configuration Register\r
+ # - BIT0 : NS - Non Secure bit\r
+ # - BIT1 : IRQ Handler\r
+ # - BIT2 : FIQ Handler\r
+ # - BIT3 : EA - External Abort\r
+ # - BIT4 : FW - F bit writable\r
+ # - BIT5 : AW - A bit writable\r
+ # - BIT6 : nET - Not Early Termination\r
+ # - BIT7 : SCD - Secure Monitor Call Disable\r
+ # - BIT8 : HCE - Hyp Call enable\r
+ # - BIT9 : SIF - Secure Instruction Fetch\r
+ # 0x31 = NS | EA | FW\r
+ gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038\r
+\r
+ # By default we do not do a transition to non-secure mode\r
+ gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E\r
+\r
+ # Non Secure Access Control Register\r
+ # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality\r
+ # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31\r
+ # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable\r
+ # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable\r
+ # 0xC00 = cp10 | cp11\r
+ gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039\r
+\r
+[PcdsFixedAtBuild.AARCH64]\r
+ #\r
+ # AArch64 Security Extension\r
+ #\r
+\r
+ # Secure Configuration Register\r
+ # - BIT0 : NS - Non Secure bit\r
+ # - BIT1 : IRQ Handler\r
+ # - BIT2 : FIQ Handler\r
+ # - BIT3 : EA - External Abort\r
+ # - BIT4 : FW - F bit writable\r
+ # - BIT5 : AW - A bit writable\r
+ # - BIT6 : nET - Not Early Termination\r
+ # - BIT7 : SCD - Secure Monitor Call Disable\r
+ # - BIT8 : HCE - Hyp Call enable\r
+ # - BIT9 : SIF - Secure Instruction Fetch\r
+ # - BIT10: RW - Register width control for lower exception levels\r
+ # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer\r
+ # - BIT12: TWI - Trap WFI\r
+ # - BIT13: TWE - Trap WFE\r
+ # 0x501 = NS | HCE | RW\r
+ gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038\r
+\r
+ # By default we do transition to EL2 non-secure mode with Stack for EL2.\r
+ # Mode Description Bits\r
+ # NS EL2 SP2 all interrupts disabled = 0x3c9\r
+ # NS EL1 SP1 all interrupts disabled = 0x3c5\r
+ # Other modes include using SP0 or switching to Aarch32, but these are\r
+ # not currently supported.\r
+ gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E\r
+\r
+\r
+#\r
+# These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be\r
+# redefined when using UEFI in a context of virtual machine.\r
+#\r
+[PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]\r
+\r
+ # System Memory (DRAM): These PCDs define the region of in-built system memory\r
+ # Some platforms can get DRAM extensions, these additional regions may be\r
+ # declared to UEFI using separate resource descriptor HOBs\r
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029\r
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A\r
+\r
+ gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045\r
+ gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046\r
+\r
+ gArmTokenSpaceGuid.PcdSystemBiosRelease|0xFFFF|UINT16|0x30000058\r
+ gArmTokenSpaceGuid.PcdEmbeddedControllerFirmwareRelease|0xFFFF|UINT16|0x30000059\r
+\r
+[PcdsFixedAtBuild.common, PcdsDynamic.common]\r
+ #\r
+ # ARM Architectural Timer\r
+ #\r
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034\r
+\r
+ # ARM Architectural Timer Interrupt(GIC PPI) numbers\r
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035\r
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036\r
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040\r
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041\r
+\r
+ #\r
+ # ARM Generic Watchdog\r
+ #\r
+\r
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007\r
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008\r
+ gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009\r
+\r
+ #\r
+ # ARM Generic Interrupt Controller\r
+ #\r
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C\r
+ # Base address for the GIC Redistributor region that contains the boot CPU\r
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E\r
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D\r
+ gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025\r
+\r
+ #\r
+ # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.\r
+ # Note that "IO" is just another MMIO range that simulates IO space; there\r
+ # are no special instructions to access it.\r
+ #\r
+ # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are\r
+ # specific to their containing address spaces. In order to get the physical\r
+ # address for the CPU, for a given access, the respective translation value\r
+ # has to be added.\r
+ #\r
+ # The translations always have to be initialized like this, using UINT64:\r
+ #\r
+ # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space\r
+ # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space\r
+ # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space\r
+ #\r
+ # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;\r
+ # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r
+ # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r
+ #\r
+ # because (a) the target address space (ie. the cpu-physical space) is\r
+ # 64-bit, and (b) the translation values are meant as offsets for *modular*\r
+ # arithmetic.\r
+ #\r
+ # Accordingly, the translation itself needs to be implemented as:\r
+ #\r
+ # UINT64 UntranslatedIoAddress; // input parameter\r
+ # UINT32 UntranslatedMmio32Address; // input parameter\r
+ # UINT64 UntranslatedMmio64Address; // input parameter\r
+ #\r
+ # UINT64 TranslatedIoAddress; // output parameter\r
+ # UINT64 TranslatedMmio32Address; // output parameter\r
+ # UINT64 TranslatedMmio64Address; // output parameter\r
+ #\r
+ # TranslatedIoAddress = UntranslatedIoAddress +\r
+ # PcdPciIoTranslation;\r
+ # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +\r
+ # PcdPciMmio32Translation;\r
+ # TranslatedMmio64Address = UntranslatedMmio64Address +\r
+ # PcdPciMmio64Translation;\r
+ #\r
+ # The modular arithmetic performed in UINT64 ensures that the translation\r
+ # works correctly regardless of the relation between IoCpuBase and\r
+ # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and\r
+ # PcdPciMmio64Base.\r
+ #\r
+ gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050\r
+ gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051\r
+ gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052\r
+ gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053\r
+ gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054\r
+ gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055\r
+ gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056\r
+ gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057\r
+ gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058\r
+\r
+ #\r
+ # Inclusive range of allowed PCI buses.\r
+ #\r
+ gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059\r
+ gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A\r