# ARM processor package.\r
#\r
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# it has been configured by the CPU DXE\r
gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032\r
\r
- gArmTokenSpaceGuid.PcdEfiUncachedMemoryToStronglyOrdered|FALSE|BOOLEAN|0x00000025\r
-\r
+ # Define if the Power State Coordination Interface (PSCI) is supported by the Platform Trusted Firmware\r
+ gArmTokenSpaceGuid.PcdArmPsciSupport|FALSE|BOOLEAN|0x00000033\r
+ \r
[PcdsFixedAtBuild.common]\r
+ gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006\r
+\r
# This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.\r
# Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.\r
gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024\r
gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005\r
\r
#\r
- # ARM PL390 General Interrupt Controller\r
+ # ARM General Interrupt Controller\r
#\r
gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C\r
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D\r
- gArmTokenSpaceGuid.PcdGicNumInterrupts|96|UINT32|0x00000023\r
+ gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025\r
\r
#\r
# ARM Secure Firmware PCDs\r
gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C\r
gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT32|0x0000002D\r
gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E\r
+ \r
+ #\r
+ # ARM Hypervisor Firmware PCDs\r
+ # \r
+ gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A\r
+ gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B\r
+ gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C\r
+ gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D\r
\r
# System Memory (DRAM): These PCDs define the region of in-built system memory\r
# Some platforms can get DRAM extensions, these additional regions will be declared\r
# to UEFI by ArmPLatformPlib \r
- gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT32|0x00000029\r
- gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT32|0x0000002A\r
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029\r
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A\r
\r
# Use ClusterId + CoreId to identify the PrimaryCore\r
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031\r
# The Primary Core is ClusterId[0] & CoreId[0] \r
gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037\r
\r
- #\r
- # ARM MPCore MailBox PCDs\r
- #\r
- # Address to Set/Get to Mailbox in Multicore system\r
- gArmTokenSpaceGuid.PcdMPCoreMailboxSetAddress|0|UINT32|0x00000017\r
- gArmTokenSpaceGuid.PcdMPCoreMailboxGetAddress|0|UINT32|0x00000018\r
- # Address/Value to clear Mailbox in Multicore system\r
- gArmTokenSpaceGuid.PcdMPCoreMailboxClearAddress|0|UINT32|0x00000019\r
- gArmTokenSpaceGuid.PcdMPCoreMailboxClearValue|0|UINT32|0x0000001A\r
-\r
#\r
# ARM L2x0 PCDs\r
#\r
gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B\r
\r
- #\r
- # ARM PL390 General Interrupt Controller\r
- #\r
- gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000001C\r
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000001D\r
- \r
# \r
# BdsLib\r
#\r
gArmTokenSpaceGuid.PcdArmMachineType|0|UINT32|0x0000001E\r
# The compressed Linux kernel is expected to be under 128MB from the beginning of the System Memory\r
gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x08000000|UINT32|0x0000001F\r
+\r
+ #\r
+ # ARM Architectural Timer\r
+ #\r
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034\r
+ # ARM Architectural Timer Interrupt(GIC PPI) number\r
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035 \r
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036\r
+\r
+[PcdsFixedAtBuild.ARM]\r
+ #\r
+ # ARM Security Extension\r
+ #\r
+\r
+ # Secure Configuration Register\r
+ # - BIT0 : NS - Non Secure bit\r
+ # - BIT1 : IRQ Handler\r
+ # - BIT2 : FIQ Handler\r
+ # - BIT3 : EA - External Abort\r
+ # - BIT4 : FW - F bit writable\r
+ # - BIT5 : AW - A bit writable\r
+ # - BIT6 : nET - Not Early Termination\r
+ # - BIT7 : SCD - Secure Monitor Call Disable\r
+ # - BIT8 : HCE - Hyp Call enable\r
+ # - BIT9 : SIF - Secure Instruction Fetch\r
+ # 0x31 = NS | EA | FW\r
+ gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038\r
+\r
+ # By default we do not do a transition to non-secure mode\r
+ gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E\r
+\r
# The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory\r
gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020\r
\r
+ # If the fixed FDT address is not available, then it should be loaded below the kernel.\r
+ # The recommendation from the Linux kernel is to have the FDT below 16KB.\r
+ # (see the kernel doc: Documentation/arm/Booting)\r
+ gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x4000|UINT32|0x00000023\r
+ # The FDT blob must be loaded at a 64bit aligned address.\r
+ gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x8|UINT32|0x00000026\r
+\r
+ # Non Secure Access Control Register\r
+ # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality\r
+ # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31\r
+ # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable\r
+ # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable\r
+ # 0xC00 = cp10 | cp11\r
+ gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039\r
+\r
+[PcdsFixedAtBuild.AARCH64]\r
+ #\r
+ # AArch64 Security Extension\r
+ #\r
+\r
+ # Secure Configuration Register\r
+ # - BIT0 : NS - Non Secure bit\r
+ # - BIT1 : IRQ Handler\r
+ # - BIT2 : FIQ Handler\r
+ # - BIT3 : EA - External Abort\r
+ # - BIT4 : FW - F bit writable\r
+ # - BIT5 : AW - A bit writable\r
+ # - BIT6 : nET - Not Early Termination\r
+ # - BIT7 : SCD - Secure Monitor Call Disable\r
+ # - BIT8 : HCE - Hyp Call enable\r
+ # - BIT9 : SIF - Secure Instruction Fetch\r
+ # - BIT10: RW - Register width control for lower exception levels\r
+ # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer\r
+ # - BIT12: TWI - Trap WFI\r
+ # - BIT13: TWE - Trap WFE\r
+ # 0x501 = NS | HCE | RW\r
+ gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038\r
+\r
+ # By default we do transition to EL2 non-secure mode with Stack for EL2.\r
+ # Mode Description Bits\r
+ # NS EL2 SP2 all interupts disabled = 0x3c9\r
+ # NS EL1 SP1 all interupts disabled = 0x3c5\r
+ # Other modes include using SP0 or switching to Aarch32, but these are\r
+ # not currently supported.\r
+ gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E\r
+ # If the fixed FDT address is not available, then it should be loaded above the kernel.\r
+ # The recommendation from the AArch64 Linux kernel is to have the FDT below 512MB.\r
+ # (see the kernel doc: Documentation/arm64/booting.txt)\r
+ gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x20000000|UINT32|0x00000023\r
+ # The FDT blob must be loaded at a 2MB aligned address.\r
+ gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x00200000|UINT32|0x00000026\r