# ARM processor package.\r
#\r
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2011 - 2015, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011 - 2017, ARM Limited. All rights reserved.\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
\r
[LibraryClasses.common]\r
ArmLib|Include/Library/ArmLib.h\r
+ ArmMmuLib|Include/Library/ArmMmuLib.h\r
SemihostLib|Include/Library/Semihosting.h\r
- UncachedMemoryAllocationLib|Include/Library/UncachedMemoryAllocationLib.h\r
DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h\r
ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h\r
+ ArmGicArchLib|Include/Library/ArmGicArchLib.h\r
+ ArmSvcLib|Include/Library/ArmSvcLib.h\r
\r
[Guids.common]\r
gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }\r
## Include/Ppi/ArmMpCoreInfo.h\r
gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }\r
\r
-[Protocols.common]\r
- gVirtualUncachedPagesProtocolGuid = { 0xAD651C7D, 0x3C22, 0x4DBF, { 0x92, 0xe8, 0x38, 0xa7, 0xcd, 0xae, 0x87, 0xb2 } }\r
-\r
[PcdsFeatureFlag.common]\r
gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001\r
\r
# On ARM Architecture with the Security Extension, the address for the\r
# Vector Table can be mapped anywhere in the memory map. It means we can\r
# point the Exception Vector Table to its location in CpuDxe.\r
- # By default we copy the Vector Table at PcdGet32(PcdCpuVectorBaseAddress)\r
+ # By default we copy the Vector Table at PcdGet64(PcdCpuVectorBaseAddress)\r
gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022\r
# Set this PCD to TRUE if the Exception Vector is changed to add debugger support before\r
# it has been configured by the CPU DXE\r
# Linux (instead of PSCI)\r
gArmTokenSpaceGuid.PcdArmLinuxSpinTable|FALSE|BOOLEAN|0x00000033\r
\r
+ # Define if the GICv3 controller should use the GICv2 legacy\r
+ gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042\r
+\r
+[PcdsFeatureFlag.ARM]\r
+ # Whether to map normal memory as non-shareable. FALSE is the safe choice, but\r
+ # TRUE may be appropriate to fix performance problems if you don't care about\r
+ # hardware coherency (i.e., no virtualization or cache coherent DMA)\r
+ gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043\r
+\r
[PcdsFixedAtBuild.common]\r
gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006\r
\r
# Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.\r
gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024\r
\r
- gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000080000000|UINT64|0x00000002\r
- # This PCD will free the unallocated buffers if their size reach this threshold.\r
- # We set the default value to 512MB.\r
- gArmTokenSpaceGuid.PcdArmFreeUncachedMemorySizeThreshold|0x20000000|UINT64|0x00000043\r
- gArmTokenSpaceGuid.PcdArmCacheOperationThreshold|1024|UINT32|0x00000003\r
- gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT32|0x00000004\r
+ gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004\r
gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005\r
\r
#\r
gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F\r
gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030\r
\r
- #\r
- # ARM Normal (or Non Secure) Firmware PCDs\r
- #\r
- gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B\r
- gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C\r
- gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D\r
- gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E\r
-\r
#\r
# ARM Hypervisor Firmware PCDs\r
#\r
#\r
# BdsLib\r
#\r
- gArmTokenSpaceGuid.PcdArmMachineType|0|UINT32|0x0000001E\r
# The compressed Linux kernel is expected to be under 128MB from the beginning of the System Memory\r
gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x08000000|UINT32|0x0000001F\r
# Maximum file size for TFTP servers that do not support 'tsize' extension\r
gArmTokenSpaceGuid.PcdMaxTftpFileSize|0x01000000|UINT32|0x00000000\r
\r
+ #\r
+ # ARM Normal (or Non Secure) Firmware PCDs\r
+ #\r
+ gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C\r
+ gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E\r
+\r
+ #\r
+ # Value to add to a host address to obtain a device address, using\r
+ # unsigned 64-bit integer arithmetic on both ARM and AArch64. This\r
+ # means we can rely on truncation on overflow to specify negative\r
+ # offsets.\r
+ #\r
+ gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044\r
+\r
+[PcdsFixedAtBuild.common, PcdsPatchableInModule.common]\r
+ gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B\r
+ gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D\r
\r
[PcdsFixedAtBuild.ARM]\r
#\r
\r
\r
#\r
-# These PCDs are also defined as 'PcdsDynamic' to be redefined when using UEFI in a\r
-# context of virtual machine.\r
+# These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be\r
+# redefined when using UEFI in a context of virtual machine.\r
#\r
-[PcdsFixedAtBuild.common, PcdsDynamic.common]\r
+[PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]\r
+\r
# System Memory (DRAM): These PCDs define the region of in-built system memory\r
# Some platforms can get DRAM extensions, these additional regions will be declared\r
# to UEFI by ArmPlatformLib\r
gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029\r
gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A\r
\r
+[PcdsFixedAtBuild.common, PcdsDynamic.common]\r
#\r
# ARM Architectural Timer\r
#\r
# ARM Generic Watchdog\r
#\r
\r
- gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT32|0x00000007\r
- gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT32|0x00000008\r
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007\r
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008\r
gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009\r
\r
#\r
# ARM Generic Interrupt Controller\r
#\r
- gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C\r
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C\r
# Base address for the GIC Redistributor region that contains the boot CPU\r
- gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT32|0x0000000E\r
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D\r
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E\r
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D\r
gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025\r
+\r
+ #\r
+ # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.\r
+ # Note that "IO" is just another MMIO range that simulates IO space; there\r
+ # are no special instructions to access it.\r
+ #\r
+ # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are\r
+ # specific to their containing address spaces. In order to get the physical\r
+ # address for the CPU, for a given access, the respective translation value\r
+ # has to be added.\r
+ #\r
+ # The translations always have to be initialized like this, using UINT64:\r
+ #\r
+ # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space\r
+ # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space\r
+ # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space\r
+ #\r
+ # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;\r
+ # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r
+ # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r
+ #\r
+ # because (a) the target address space (ie. the cpu-physical space) is\r
+ # 64-bit, and (b) the translation values are meant as offsets for *modular*\r
+ # arithmetic.\r
+ #\r
+ # Accordingly, the translation itself needs to be implemented as:\r
+ #\r
+ # UINT64 UntranslatedIoAddress; // input parameter\r
+ # UINT32 UntranslatedMmio32Address; // input parameter\r
+ # UINT64 UntranslatedMmio64Address; // input parameter\r
+ #\r
+ # UINT64 TranslatedIoAddress; // output parameter\r
+ # UINT64 TranslatedMmio32Address; // output parameter\r
+ # UINT64 TranslatedMmio64Address; // output parameter\r
+ #\r
+ # TranslatedIoAddress = UntranslatedIoAddress +\r
+ # PcdPciIoTranslation;\r
+ # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +\r
+ # PcdPciMmio32Translation;\r
+ # TranslatedMmio64Address = UntranslatedMmio64Address +\r
+ # PcdPciMmio64Translation;\r
+ #\r
+ # The modular arithmetic performed in UINT64 ensures that the translation\r
+ # works correctly regardless of the relation between IoCpuBase and\r
+ # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and\r
+ # PcdPciMmio64Base.\r
+ #\r
+ gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050\r
+ gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051\r
+ gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052\r
+ gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053\r
+ gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054\r
+ gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055\r
+ gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056\r
+ gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057\r
+ gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058\r
+\r
+ #\r
+ # Inclusive range of allowed PCI buses.\r
+ #\r
+ gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059\r
+ gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A\r