ArmPlatformPkg/PeiServicesTablePointerLib: Update PeiServicesTablePointerLib instance...

[mirror_edk2.git] / ArmPlatformPkg / Documentation / ArmPlatformPkg.txt

diff --git a/ArmPlatformPkg/Documentation/ArmPlatformPkg.txt b/ArmPlatformPkg/Documentation/ArmPlatformPkg.txt
index e45a3f0666a08297f166cc36ff91fbc952bb26ae..e591767a103e52d8142688d22d44d5011e5d2eba 100644 (file)
--- a/ArmPlatformPkg/Documentation/ArmPlatformPkg.txt
+++ b/ArmPlatformPkg/Documentation/ArmPlatformPkg.txt
@@ -15,22 +15,22 @@ PCDs        Description :
 # Firmware Device / Volume\r
 gArmTokenSpaceGuid.PcdSecureFdBaseAddress       : Base address of your Secure Firmware Device \r
 gArmTokenSpaceGuid.PcdSecureFdSize              : Size in byte of your Secure Firmware Device.\r
-gArmTokenSpaceGuid.PcdNormalFdBaseAddress       : Base Address of your Non-Secure/Normal World Firmware Device.\r
-gArmTokenSpaceGuid.PcdNormalFdSize              : Size in bytes of your Non-Secure/Normal World Firmware Device \r
+gArmTokenSpaceGuid.PcdFdBaseAddress       : Base Address of your Non-Secure/Normal World Firmware Device.\r
+gArmTokenSpaceGuid.PcdFdSize              : Size in bytes of your Non-Secure/Normal World Firmware Device \r
 \r
 # Stacks\r
-gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase                   : Top of Secure Stack for Secure World\r
-gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize                    : Size of the stack for each of the 4 CPU cores\r
-gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase                : Top of Stack for Monitor World\r
-gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize                 : Size of the stack for each of the 4 CPU cores\r
-gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase                : Top of SEC Stack for Normal World\r
-gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize                : Size of the stack for each of the 4 CPU Cores\r
+gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase             : Base of Secure Stack for Secure World\r
+gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize       : Size of the stack for the Primary Core in Secure World\r
+gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize     : Size of the stack for the Secondary Cores in Secure World\r
+gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase          : Base of Stack for Monitor World\r
+gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize           : Size of the stack for each cores\r
+gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase                : Base of SEC Stack for Normal World\r
+gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize          : Size of the stack for the Primary Core\r
+gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize        : Size of the stack for the Secondary Core\r
 \r
 # CPU / Architectural controllers\r
 gArmTokenSpaceGuid.PcdGicDistributorBase        : Base address of the Distributor of your General Interrupt Controller\r
 gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase : Base address of the Interface of your General Interrupt Controller\r
-gArmPlatformTokenSpaceGuid.PcdMPCoreSupport     : Set to 1 when MP Core platforms\r
-gArmPlatformTokenSpaceGuid.PcdMPCoreMaxCores    : Maximum number of CPU cores on the platform (used for instance to know how many stacks we need to configure)\r
 \r
 # Memory Regions\r
 gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize  : Size of the region reserve for PI & UEFI\r