/** @file\r
* Main file supporting the transition to PEI Core in Normal World for Versatile Express\r
*\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
-* \r
-* This program and the accompanying materials \r
-* are licensed and made available under the terms and conditions of the BSD License \r
-* which accompanies this distribution. The full text of the license may be found at \r
-* http://opensource.org/licenses/bsd-license.php \r
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
-#include <PiPei.h>\r
-#include <Ppi/TemporaryRamSupport.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <Library/IoLib.h>\r
#include <Library/BaseLib.h>\r
-#include <Library/BaseMemoryLib.h>\r
+#include <Library/DebugAgentLib.h>\r
#include <Library/ArmLib.h>\r
-#include <Chipset/ArmV7.h>\r
\r
-EFI_STATUS\r
-EFIAPI\r
-SecTemporaryRamSupport (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,\r
- IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,\r
- IN UINTN CopySize\r
- );\r
+#include "PrePeiCore.h"\r
\r
-VOID\r
-SecSwitchStack (\r
- INTN StackDelta\r
- );\r
+CONST EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi = { PrePeiCoreTemporaryRamSupport };\r
\r
-TEMPORARY_RAM_SUPPORT_PPI mSecTemporaryRamSupportPpi = {SecTemporaryRamSupport};\r
-\r
-EFI_PEI_PPI_DESCRIPTOR gSecPpiTable[] = {\r
+CONST EFI_PEI_PPI_DESCRIPTOR gCommonPpiTable[] = {\r
{\r
- EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
+ EFI_PEI_PPI_DESCRIPTOR_PPI,\r
&gEfiTemporaryRamSupportPpiGuid,\r
- &mSecTemporaryRamSupportPpi\r
+ (VOID *) &mTemporaryRamSupportPpi\r
}\r
};\r
\r
-// Vector Table for Pei Phase\r
-VOID PeiVectorTable (VOID);\r
-\r
+VOID\r
+CreatePpiList (\r
+ OUT UINTN *PpiListSize,\r
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList\r
+ )\r
+{\r
+ EFI_PEI_PPI_DESCRIPTOR *PlatformPpiList;\r
+ UINTN PlatformPpiListSize;\r
+ UINTN ListBase;\r
+ EFI_PEI_PPI_DESCRIPTOR *LastPpi;\r
+\r
+ // Get the Platform PPIs\r
+ PlatformPpiListSize = 0;\r
+ ArmPlatformGetPlatformPpiList (&PlatformPpiListSize, &PlatformPpiList);\r
+\r
+ // Copy the Common and Platform PPis in Temporrary Memory\r
+ ListBase = PcdGet64 (PcdCPUCoresStackBase);\r
+ CopyMem ((VOID*)ListBase, gCommonPpiTable, sizeof(gCommonPpiTable));\r
+ CopyMem ((VOID*)(ListBase + sizeof(gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize);\r
+\r
+ // Set the Terminate flag on the last PPI entry\r
+ LastPpi = (EFI_PEI_PPI_DESCRIPTOR*)ListBase + ((sizeof(gCommonPpiTable) + PlatformPpiListSize) / sizeof(EFI_PEI_PPI_DESCRIPTOR)) - 1;\r
+ LastPpi->Flags |= EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;\r
+\r
+ *PpiList = (EFI_PEI_PPI_DESCRIPTOR*)ListBase;\r
+ *PpiListSize = sizeof(gCommonPpiTable) + PlatformPpiListSize;\r
+}\r
\r
VOID\r
CEntryPoint (\r
- IN UINTN CoreId,\r
+ IN UINTN MpId,\r
IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r
)\r
{\r
- //Clean Data cache\r
- ArmCleanInvalidateDataCache();\r
-\r
- //Invalidate instruction cache\r
- ArmInvalidateInstructionCache();\r
-\r
- // Enable Instruction & Data caches\r
- ArmEnableDataCache();\r
- ArmEnableInstructionCache();\r
+ // Data Cache enabled on Primary core when MMU is enabled.\r
+ ArmDisableDataCache ();\r
+ // Invalidate Data cache\r
+ ArmInvalidateDataCache ();\r
+ // Invalidate instruction cache\r
+ ArmInvalidateInstructionCache ();\r
+ // Enable Instruction Caches on all cores.\r
+ ArmEnableInstructionCache ();\r
\r
//\r
// Note: Doesn't have to Enable CPU interface in non-secure world,\r
// as Non-secure interface is already enabled in Secure world.\r
//\r
\r
- // Write VBAR - The Vector table must be 32-byte aligned\r
- ASSERT(((UINT32)PeiVectorTable & ((1 << 5)-1)) == 0);\r
- ArmWriteVBar((UINT32)PeiVectorTable);\r
+ // Write VBAR - The Exception Vector table must be aligned to its requirement\r
+ // Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure\r
+ // 'Align=4K' is defined into your FDF for this module.\r
+ ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);\r
+ ArmWriteVBar ((UINTN)PeiVectorTable);\r
\r
//Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.\r
\r
- //If not primary Jump to Secondary Main\r
- if(0 == CoreId) {\r
- //Goto primary Main.\r
- primary_main(PeiCoreEntryPoint);\r
+ // If not primary Jump to Secondary Main\r
+ if (ArmPlatformIsPrimaryCore (MpId)) {\r
+ // Initialize the Debug Agent for Source Level Debugging\r
+ InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);\r
+ SaveAndSetDebugTimerInterrupt (TRUE);\r
+\r
+ // Initialize the platform specific controllers\r
+ ArmPlatformInitialize (MpId);\r
+\r
+ // Goto primary Main.\r
+ PrimaryMain (PeiCoreEntryPoint);\r
} else {\r
- secondary_main(CoreId);\r
+ SecondaryMain (MpId);\r
}\r
\r
// PEI Core should always load and never return\r
\r
EFI_STATUS\r
EFIAPI\r
-SecTemporaryRamSupport (\r
+PrePeiCoreTemporaryRamSupport (\r
IN CONST EFI_PEI_SERVICES **PeiServices,\r
IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,\r
IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,\r
IN UINTN CopySize\r
)\r
{\r
+ VOID *OldHeap;\r
+ VOID *NewHeap;\r
+ VOID *OldStack;\r
+ VOID *NewStack;\r
+ UINTN HeapSize;\r
+\r
+ HeapSize = ALIGN_VALUE (CopySize / 2, CPU_STACK_ALIGNMENT);\r
+\r
+ OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;\r
+ NewHeap = (VOID*)((UINTN)PermanentMemoryBase + (CopySize - HeapSize));\r
+\r
+ OldStack = (VOID*)((UINTN)TemporaryMemoryBase + HeapSize);\r
+ NewStack = (VOID*)(UINTN)PermanentMemoryBase;\r
+\r
//\r
- // Migrate the whole temporary memory to permenent memory.\r
- // \r
- CopyMem (\r
- (VOID*)(UINTN)PermanentMemoryBase, \r
- (VOID*)(UINTN)TemporaryMemoryBase, \r
- CopySize\r
- );\r
+ // Migrate the temporary memory stack to permanent memory stack.\r
+ //\r
+ CopyMem (NewStack, OldStack, CopySize - HeapSize);\r
\r
- SecSwitchStack((UINTN)(PermanentMemoryBase - TemporaryMemoryBase));\r
+ //\r
+ // Migrate the temporary memory heap to permanent memory heap.\r
+ //\r
+ CopyMem (NewHeap, OldHeap, HeapSize);\r
\r
- return EFI_SUCCESS;\r
-}\r
+ SecSwitchStack ((UINTN)NewStack - (UINTN)OldStack);\r
\r
-VOID PeiCommonExceptionEntry(UINT32 Entry, UINT32 LR) {\r
- switch (Entry) {\r
- case 0:\r
- DEBUG((EFI_D_ERROR,"Reset Exception at 0x%X\n",LR));\r
- break;\r
- case 1:\r
- DEBUG((EFI_D_ERROR,"Undefined Exception at 0x%X\n",LR));\r
- break;\r
- case 2:\r
- DEBUG((EFI_D_ERROR,"SWI Exception at 0x%X\n",LR));\r
- break;\r
- case 3:\r
- DEBUG((EFI_D_ERROR,"PrefetchAbort Exception at 0x%X\n",LR));\r
- break;\r
- case 4:\r
- DEBUG((EFI_D_ERROR,"DataAbort Exception at 0x%X\n",LR));\r
- break;\r
- case 5:\r
- DEBUG((EFI_D_ERROR,"Reserved Exception at 0x%X\n",LR));\r
- break;\r
- case 6:\r
- DEBUG((EFI_D_ERROR,"IRQ Exception at 0x%X\n",LR));\r
- break;\r
- case 7:\r
- DEBUG((EFI_D_ERROR,"FIQ Exception at 0x%X\n",LR));\r
- break;\r
- default:\r
- DEBUG((EFI_D_ERROR,"Unknown Exception at 0x%X\n",LR));\r
- break;\r
- }\r
- while(1);\r
+ return EFI_SUCCESS;\r
}\r